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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_defines.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
165 #define MOCS_PTE 0x18
168 #define MOCS_PTE (1 << 1)
169 #define MOCS_WB (2 << 1)
173 mocs(struct iris_bo
*bo
)
175 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
179 * Statically assert that PIPE_* enums match the hardware packets.
180 * (As long as they match, we don't need to translate them.)
182 UNUSED
static void pipe_asserts()
184 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
186 /* pipe_logicop happens to match the hardware. */
187 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
188 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
189 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
190 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
192 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
193 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
194 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
195 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
196 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
197 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
198 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
199 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
200 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
202 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
204 /* pipe_blend_func happens to match the hardware. */
205 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
225 /* pipe_blend_func happens to match the hardware. */
226 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
227 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
228 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
230 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
232 /* pipe_stencil_op happens to match the hardware. */
233 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
234 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
242 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
243 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
244 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
249 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
251 static const unsigned map
[] = {
252 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
253 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
254 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
255 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
256 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
257 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
258 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
259 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
260 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
261 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
262 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
263 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
264 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
265 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
266 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
269 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
273 translate_compare_func(enum pipe_compare_func pipe_func
)
275 static const unsigned map
[] = {
276 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
277 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
278 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
279 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
280 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
281 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
282 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
283 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
285 return map
[pipe_func
];
289 translate_shadow_func(enum pipe_compare_func pipe_func
)
291 /* Gallium specifies the result of shadow comparisons as:
293 * 1 if ref <op> texel,
298 * 0 if texel <op> ref,
301 * So we need to flip the operator and also negate.
303 static const unsigned map
[] = {
304 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
305 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
306 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
307 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
308 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
309 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
310 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
311 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
313 return map
[pipe_func
];
317 translate_cull_mode(unsigned pipe_face
)
319 static const unsigned map
[4] = {
320 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
321 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
322 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
323 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
325 return map
[pipe_face
];
329 translate_fill_mode(unsigned pipe_polymode
)
331 static const unsigned map
[4] = {
332 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
333 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
334 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
335 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
337 return map
[pipe_polymode
];
341 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
343 static const unsigned map
[] = {
344 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
345 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
346 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
348 return map
[pipe_mip
];
352 translate_wrap(unsigned pipe_wrap
)
354 static const unsigned map
[] = {
355 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
356 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
357 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
358 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
359 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
360 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
362 /* These are unsupported. */
363 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
364 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
366 return map
[pipe_wrap
];
369 static struct iris_address
370 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
372 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
373 * validation list at CSO creation time, instead of draw time.
375 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
378 static struct iris_address
379 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
381 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
382 * validation list at CSO creation time, instead of draw time.
384 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
388 * Allocate space for some indirect state.
390 * Return a pointer to the map (to fill it out) and a state ref (for
391 * referring to the state in GPU commands).
394 upload_state(struct u_upload_mgr
*uploader
,
395 struct iris_state_ref
*ref
,
400 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
405 * Stream out temporary/short-lived state.
407 * This allocates space, pins the BO, and includes the BO address in the
408 * returned offset (which works because all state lives in 32-bit memory
412 stream_state(struct iris_batch
*batch
,
413 struct u_upload_mgr
*uploader
,
414 struct pipe_resource
**out_res
,
417 uint32_t *out_offset
)
421 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
423 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
424 iris_use_pinned_bo(batch
, bo
, false);
426 *out_offset
+= iris_bo_offset_from_base_address(bo
);
432 * stream_state() + memcpy.
435 emit_state(struct iris_batch
*batch
,
436 struct u_upload_mgr
*uploader
,
437 struct pipe_resource
**out_res
,
444 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
447 memcpy(map
, data
, size
);
453 * Did field 'x' change between 'old_cso' and 'new_cso'?
455 * (If so, we may want to set some dirty flags.)
457 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
458 #define cso_changed_memcmp(x) \
459 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
462 flush_for_state_base_change(struct iris_batch
*batch
)
464 /* Flush before emitting STATE_BASE_ADDRESS.
466 * This isn't documented anywhere in the PRM. However, it seems to be
467 * necessary prior to changing the surface state base adress. We've
468 * seen issues in Vulkan where we get GPU hangs when using multi-level
469 * command buffers which clear depth, reset state base address, and then
472 * Normally, in GL, we would trust the kernel to do sufficient stalls
473 * and flushes prior to executing our batch. However, it doesn't seem
474 * as if the kernel's flushing is always sufficient and we don't want to
477 * We make this an end-of-pipe sync instead of a normal flush because we
478 * do not know the current status of the GPU. On Haswell at least,
479 * having a fast-clear operation in flight at the same time as a normal
480 * rendering operation can cause hangs. Since the kernel's flushing is
481 * insufficient, we need to ensure that any rendering operations from
482 * other processes are definitely complete before we try to do our own
483 * rendering. It's a bit of a big hammer but it appears to work.
485 iris_emit_end_of_pipe_sync(batch
,
486 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
487 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
488 PIPE_CONTROL_DATA_CACHE_FLUSH
);
492 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
494 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
495 lri
.RegisterOffset
= reg
;
499 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
502 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
504 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
505 lrr
.SourceRegisterAddress
= src
;
506 lrr
.DestinationRegisterAddress
= dst
;
511 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
513 #if GEN_GEN >= 8 && GEN_GEN < 10
514 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
516 * Software must clear the COLOR_CALC_STATE Valid field in
517 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
518 * with Pipeline Select set to GPGPU.
520 * The internal hardware docs recommend the same workaround for Gen9
523 if (pipeline
== GPGPU
)
524 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
528 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
529 * PIPELINE_SELECT [DevBWR+]":
533 * Software must ensure all the write caches are flushed through a
534 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
535 * command to invalidate read only caches prior to programming
536 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
538 iris_emit_pipe_control_flush(batch
,
539 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
540 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
541 PIPE_CONTROL_DATA_CACHE_FLUSH
|
542 PIPE_CONTROL_CS_STALL
);
544 iris_emit_pipe_control_flush(batch
,
545 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
546 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
547 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
548 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
550 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
554 sel
.PipelineSelection
= pipeline
;
559 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
564 * "This chicken bit works around a hardware issue with barrier
565 * logic encountered when switching between GPGPU and 3D pipelines.
566 * To workaround the issue, this mode bit should be set after a
567 * pipeline is selected."
570 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
571 reg
.GLKBarrierMode
= value
;
572 reg
.GLKBarrierModeMask
= 1;
574 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
579 init_state_base_address(struct iris_batch
*batch
)
581 flush_for_state_base_change(batch
);
583 /* We program most base addresses once at context initialization time.
584 * Each base address points at a 4GB memory zone, and never needs to
585 * change. See iris_bufmgr.h for a description of the memory zones.
587 * The one exception is Surface State Base Address, which needs to be
588 * updated occasionally. See iris_binder.c for the details there.
590 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
591 sba
.GeneralStateMOCS
= MOCS_WB
;
592 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
593 sba
.DynamicStateMOCS
= MOCS_WB
;
594 sba
.IndirectObjectMOCS
= MOCS_WB
;
595 sba
.InstructionMOCS
= MOCS_WB
;
597 sba
.GeneralStateBaseAddressModifyEnable
= true;
598 sba
.DynamicStateBaseAddressModifyEnable
= true;
599 sba
.IndirectObjectBaseAddressModifyEnable
= true;
600 sba
.InstructionBaseAddressModifyEnable
= true;
601 sba
.GeneralStateBufferSizeModifyEnable
= true;
602 sba
.DynamicStateBufferSizeModifyEnable
= true;
604 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
605 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
607 sba
.IndirectObjectBufferSizeModifyEnable
= true;
608 sba
.InstructionBuffersizeModifyEnable
= true;
610 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
611 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
613 sba
.GeneralStateBufferSize
= 0xfffff;
614 sba
.IndirectObjectBufferSize
= 0xfffff;
615 sba
.InstructionBufferSize
= 0xfffff;
616 sba
.DynamicStateBufferSize
= 0xfffff;
621 * Upload the initial GPU state for a render context.
623 * This sets some invariant state that needs to be programmed a particular
624 * way, but we never actually change.
627 iris_init_render_context(struct iris_screen
*screen
,
628 struct iris_batch
*batch
,
629 struct iris_vtable
*vtbl
,
630 struct pipe_debug_callback
*dbg
)
632 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
635 emit_pipeline_select(batch
, _3D
);
637 init_state_base_address(batch
);
640 // XXX: INSTPM on Gen8
641 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
642 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
643 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
645 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
647 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
648 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
649 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
651 iris_emit_lri(batch
, INSTPM
, reg_val
);
655 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
656 reg
.FloatBlendOptimizationEnable
= true;
657 reg
.FloatBlendOptimizationEnableMask
= true;
658 reg
.PartialResolveDisableInVC
= true;
659 reg
.PartialResolveDisableInVCMask
= true;
661 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
663 if (devinfo
->is_geminilake
)
664 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
668 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
669 reg
.HeaderlessMessageforPreemptableContexts
= 1;
670 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
672 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
677 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
678 * changing it dynamically. We set it to the maximum size here, and
679 * instead include the render target dimensions in the viewport, so
680 * viewport extents clipping takes care of pruning stray geometry.
682 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
683 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
684 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
687 /* Set the initial MSAA sample positions. */
688 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
689 GEN_SAMPLE_POS_1X(pat
._1xSample
);
690 GEN_SAMPLE_POS_2X(pat
._2xSample
);
691 GEN_SAMPLE_POS_4X(pat
._4xSample
);
692 GEN_SAMPLE_POS_8X(pat
._8xSample
);
694 GEN_SAMPLE_POS_16X(pat
._16xSample
);
698 /* Use the legacy AA line coverage computation. */
699 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
701 /* Disable chromakeying (it's for media) */
702 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
704 /* We want regular rendering, not special HiZ operations. */
705 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
707 /* No polygon stippling offsets are necessary. */
708 // XXX: may need to set an offset for origin-UL framebuffers
709 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
711 /* Set a static partitioning of the push constant area. */
712 // XXX: this may be a bad idea...could starve the push ringbuffers...
713 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
714 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
715 alloc
._3DCommandSubOpcode
= 18 + i
;
716 alloc
.ConstantBufferOffset
= 6 * i
;
717 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
723 iris_init_compute_context(struct iris_screen
*screen
,
724 struct iris_batch
*batch
,
725 struct iris_vtable
*vtbl
,
726 struct pipe_debug_callback
*dbg
)
728 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
730 emit_pipeline_select(batch
, GPGPU
);
732 const bool has_slm
= true;
733 const bool wants_dc_cache
= true;
735 const struct gen_l3_weights w
=
736 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
737 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
740 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
741 reg
.SLMEnable
= has_slm
;
743 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
744 * in L3CNTLREG register. The default setting of the bit is not the
745 * desirable behavior.
747 reg
.ErrorDetectionBehaviorControl
= true;
749 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
750 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
751 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
752 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
754 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
756 init_state_base_address(batch
);
759 if (devinfo
->is_geminilake
)
760 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
764 struct iris_vertex_buffer_state
{
765 /** The VERTEX_BUFFER_STATE hardware structure. */
766 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
768 /** The resource to source vertex data from. */
769 struct pipe_resource
*resource
;
772 struct iris_depth_buffer_state
{
773 /* Depth/HiZ/Stencil related hardware packets. */
774 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
775 GENX(3DSTATE_STENCIL_BUFFER_length
) +
776 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
777 GENX(3DSTATE_CLEAR_PARAMS_length
)];
781 * Generation-specific context state (ice->state.genx->...).
783 * Most state can go in iris_context directly, but these encode hardware
784 * packets which vary by generation.
786 struct iris_genx_state
{
787 struct iris_vertex_buffer_state vertex_buffers
[33];
789 /** The number of bound vertex buffers. */
790 uint64_t bound_vertex_buffers
;
792 struct iris_depth_buffer_state depth_buffer
;
794 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
798 * The pipe->set_blend_color() driver hook.
800 * This corresponds to our COLOR_CALC_STATE.
803 iris_set_blend_color(struct pipe_context
*ctx
,
804 const struct pipe_blend_color
*state
)
806 struct iris_context
*ice
= (struct iris_context
*) ctx
;
808 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
809 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
810 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
814 * Gallium CSO for blend state (see pipe_blend_state).
816 struct iris_blend_state
{
817 /** Partial 3DSTATE_PS_BLEND */
818 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
820 /** Partial BLEND_STATE */
821 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
822 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
824 bool alpha_to_coverage
; /* for shader key */
826 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
827 uint8_t blend_enables
;
830 static enum pipe_blendfactor
831 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
834 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
835 return PIPE_BLENDFACTOR_ONE
;
837 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
838 return PIPE_BLENDFACTOR_ZERO
;
845 * The pipe->create_blend_state() driver hook.
847 * Translates a pipe_blend_state into iris_blend_state.
850 iris_create_blend_state(struct pipe_context
*ctx
,
851 const struct pipe_blend_state
*state
)
853 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
854 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
856 cso
->blend_enables
= 0;
857 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
859 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
861 bool indep_alpha_blend
= false;
863 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
864 const struct pipe_rt_blend_state
*rt
=
865 &state
->rt
[state
->independent_blend_enable
? i
: 0];
867 enum pipe_blendfactor src_rgb
=
868 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
869 enum pipe_blendfactor src_alpha
=
870 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
871 enum pipe_blendfactor dst_rgb
=
872 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
873 enum pipe_blendfactor dst_alpha
=
874 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
876 if (rt
->rgb_func
!= rt
->alpha_func
||
877 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
878 indep_alpha_blend
= true;
880 if (rt
->blend_enable
)
881 cso
->blend_enables
|= 1u << i
;
883 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
884 be
.LogicOpEnable
= state
->logicop_enable
;
885 be
.LogicOpFunction
= state
->logicop_func
;
887 be
.PreBlendSourceOnlyClampEnable
= false;
888 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
889 be
.PreBlendColorClampEnable
= true;
890 be
.PostBlendColorClampEnable
= true;
892 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
894 be
.ColorBlendFunction
= rt
->rgb_func
;
895 be
.AlphaBlendFunction
= rt
->alpha_func
;
896 be
.SourceBlendFactor
= src_rgb
;
897 be
.SourceAlphaBlendFactor
= src_alpha
;
898 be
.DestinationBlendFactor
= dst_rgb
;
899 be
.DestinationAlphaBlendFactor
= dst_alpha
;
901 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
902 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
903 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
904 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
906 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
909 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
910 /* pb.HasWriteableRT is filled in at draw time. */
911 /* pb.AlphaTestEnable is filled in at draw time. */
912 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
913 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
915 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
917 pb
.SourceBlendFactor
=
918 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
919 pb
.SourceAlphaBlendFactor
=
920 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
921 pb
.DestinationBlendFactor
=
922 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
923 pb
.DestinationAlphaBlendFactor
=
924 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
927 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
928 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
929 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
930 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
931 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
932 bs
.ColorDitherEnable
= state
->dither
;
933 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
941 * The pipe->bind_blend_state() driver hook.
943 * Bind a blending CSO and flag related dirty bits.
946 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
948 struct iris_context
*ice
= (struct iris_context
*) ctx
;
949 struct iris_blend_state
*cso
= state
;
951 ice
->state
.cso_blend
= cso
;
952 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
954 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
955 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
956 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
960 * Gallium CSO for depth, stencil, and alpha testing state.
962 struct iris_depth_stencil_alpha_state
{
963 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
964 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
966 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
967 struct pipe_alpha_state alpha
;
969 /** Outbound to resolve and cache set tracking. */
970 bool depth_writes_enabled
;
971 bool stencil_writes_enabled
;
975 * The pipe->create_depth_stencil_alpha_state() driver hook.
977 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
978 * testing state since we need pieces of it in a variety of places.
981 iris_create_zsa_state(struct pipe_context
*ctx
,
982 const struct pipe_depth_stencil_alpha_state
*state
)
984 struct iris_depth_stencil_alpha_state
*cso
=
985 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
987 bool two_sided_stencil
= state
->stencil
[1].enabled
;
989 cso
->alpha
= state
->alpha
;
990 cso
->depth_writes_enabled
= state
->depth
.writemask
;
991 cso
->stencil_writes_enabled
=
992 state
->stencil
[0].writemask
!= 0 ||
993 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
995 /* The state tracker needs to optimize away EQUAL writes for us. */
996 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
998 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
999 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1000 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1001 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1002 wmds
.StencilTestFunction
=
1003 translate_compare_func(state
->stencil
[0].func
);
1004 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1005 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1006 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1007 wmds
.BackfaceStencilTestFunction
=
1008 translate_compare_func(state
->stencil
[1].func
);
1009 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1010 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1011 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1012 wmds
.StencilBufferWriteEnable
=
1013 state
->stencil
[0].writemask
!= 0 ||
1014 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1015 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1016 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1017 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1018 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1019 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1020 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1021 /* wmds.[Backface]StencilReferenceValue are merged later */
1028 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1030 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1033 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1035 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1036 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1037 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1040 if (cso_changed(alpha
.ref_value
))
1041 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1043 if (cso_changed(alpha
.enabled
))
1044 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1046 if (cso_changed(alpha
.func
))
1047 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1049 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1050 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1053 ice
->state
.cso_zsa
= new_cso
;
1054 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1055 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1056 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1060 * Gallium CSO for rasterizer state.
1062 struct iris_rasterizer_state
{
1063 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1064 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1065 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1066 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1067 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1069 uint8_t num_clip_plane_consts
;
1070 bool clip_halfz
; /* for CC_VIEWPORT */
1071 bool depth_clip_near
; /* for CC_VIEWPORT */
1072 bool depth_clip_far
; /* for CC_VIEWPORT */
1073 bool flatshade
; /* for shader state */
1074 bool flatshade_first
; /* for stream output */
1075 bool clamp_fragment_color
; /* for shader state */
1076 bool light_twoside
; /* for shader state */
1077 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1078 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1079 bool line_stipple_enable
;
1080 bool poly_stipple_enable
;
1082 bool force_persample_interp
;
1083 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1084 uint16_t sprite_coord_enable
;
1088 get_line_width(const struct pipe_rasterizer_state
*state
)
1090 float line_width
= state
->line_width
;
1092 /* From the OpenGL 4.4 spec:
1094 * "The actual width of non-antialiased lines is determined by rounding
1095 * the supplied width to the nearest integer, then clamping it to the
1096 * implementation-dependent maximum non-antialiased line width."
1098 if (!state
->multisample
&& !state
->line_smooth
)
1099 line_width
= roundf(state
->line_width
);
1101 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1102 /* For 1 pixel line thickness or less, the general anti-aliasing
1103 * algorithm gives up, and a garbage line is generated. Setting a
1104 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1105 * (one-pixel-wide), non-antialiased lines.
1107 * Lines rendered with zero Line Width are rasterized using the
1108 * "Grid Intersection Quantization" rules as specified by the
1109 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1118 * The pipe->create_rasterizer_state() driver hook.
1121 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1122 const struct pipe_rasterizer_state
*state
)
1124 struct iris_rasterizer_state
*cso
=
1125 malloc(sizeof(struct iris_rasterizer_state
));
1128 point_quad_rasterization
-> SBE
?
1135 offset_units_unscaled
- cap
not exposed
1139 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1140 // we're copying a lot of booleans here. But we don't need all of them...
1142 cso
->multisample
= state
->multisample
;
1143 cso
->force_persample_interp
= state
->force_persample_interp
;
1144 cso
->clip_halfz
= state
->clip_halfz
;
1145 cso
->depth_clip_near
= state
->depth_clip_near
;
1146 cso
->depth_clip_far
= state
->depth_clip_far
;
1147 cso
->flatshade
= state
->flatshade
;
1148 cso
->flatshade_first
= state
->flatshade_first
;
1149 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1150 cso
->light_twoside
= state
->light_twoside
;
1151 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1152 cso
->half_pixel_center
= state
->half_pixel_center
;
1153 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1154 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1155 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1156 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1158 if (state
->clip_plane_enable
!= 0)
1159 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1161 cso
->num_clip_plane_consts
= 0;
1163 float line_width
= get_line_width(state
);
1165 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1166 sf
.StatisticsEnable
= true;
1167 sf
.ViewportTransformEnable
= true;
1168 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1169 sf
.LineEndCapAntialiasingRegionWidth
=
1170 state
->line_smooth
? _10pixels
: _05pixels
;
1171 sf
.LastPixelEnable
= state
->line_last_pixel
;
1172 sf
.LineWidth
= line_width
;
1173 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1174 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1175 sf
.PointWidth
= state
->point_size
;
1177 if (state
->flatshade_first
) {
1178 sf
.TriangleFanProvokingVertexSelect
= 1;
1180 sf
.TriangleStripListProvokingVertexSelect
= 2;
1181 sf
.TriangleFanProvokingVertexSelect
= 2;
1182 sf
.LineStripListProvokingVertexSelect
= 1;
1186 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1187 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1188 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1189 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1190 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1191 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1192 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1193 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1194 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1195 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1196 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1197 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1198 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1199 rr
.AntialiasingEnable
= state
->line_smooth
;
1200 rr
.ScissorRectangleEnable
= state
->scissor
;
1202 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1203 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1205 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1207 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1210 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1211 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1212 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1214 cl
.EarlyCullEnable
= true;
1215 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1216 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1217 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1218 cl
.GuardbandClipTestEnable
= true;
1219 cl
.ClipEnable
= true;
1220 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1221 cl
.MinimumPointWidth
= 0.125;
1222 cl
.MaximumPointWidth
= 255.875;
1224 if (state
->flatshade_first
) {
1225 cl
.TriangleFanProvokingVertexSelect
= 1;
1227 cl
.TriangleStripListProvokingVertexSelect
= 2;
1228 cl
.TriangleFanProvokingVertexSelect
= 2;
1229 cl
.LineStripListProvokingVertexSelect
= 1;
1233 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1234 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1235 * filled in at draw time from the FS program.
1237 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1238 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1239 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1240 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1241 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1244 /* Remap from 0..255 back to 1..256 */
1245 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1247 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1248 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1249 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1250 line
.LineStippleRepeatCount
= line_stipple_factor
;
1257 * The pipe->bind_rasterizer_state() driver hook.
1259 * Bind a rasterizer CSO and flag related dirty bits.
1262 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1264 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1265 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1266 struct iris_rasterizer_state
*new_cso
= state
;
1269 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1270 if (cso_changed_memcmp(line_stipple
))
1271 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1273 if (cso_changed(half_pixel_center
))
1274 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1276 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1277 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1279 if (cso_changed(rasterizer_discard
))
1280 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1282 if (cso_changed(flatshade_first
))
1283 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1285 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1286 cso_changed(clip_halfz
))
1287 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1289 if (cso_changed(sprite_coord_enable
) ||
1290 cso_changed(sprite_coord_mode
) ||
1291 cso_changed(light_twoside
))
1292 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1295 ice
->state
.cso_rast
= new_cso
;
1296 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1297 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1298 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1302 * Return true if the given wrap mode requires the border color to exist.
1304 * (We can skip uploading it if the sampler isn't going to use it.)
1307 wrap_mode_needs_border_color(unsigned wrap_mode
)
1309 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1313 * Gallium CSO for sampler state.
1315 struct iris_sampler_state
{
1316 union pipe_color_union border_color
;
1317 bool needs_border_color
;
1319 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1323 * The pipe->create_sampler_state() driver hook.
1325 * We fill out SAMPLER_STATE (except for the border color pointer), and
1326 * store that on the CPU. It doesn't make sense to upload it to a GPU
1327 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1328 * all bound sampler states to be in contiguous memor.
1331 iris_create_sampler_state(struct pipe_context
*ctx
,
1332 const struct pipe_sampler_state
*state
)
1334 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1339 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1340 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1342 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1343 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1344 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1346 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1348 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1349 wrap_mode_needs_border_color(wrap_t
) ||
1350 wrap_mode_needs_border_color(wrap_r
);
1352 float min_lod
= state
->min_lod
;
1353 unsigned mag_img_filter
= state
->mag_img_filter
;
1355 // XXX: explain this code ported from ilo...I don't get it at all...
1356 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1357 state
->min_lod
> 0.0f
) {
1359 mag_img_filter
= state
->min_img_filter
;
1362 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1363 samp
.TCXAddressControlMode
= wrap_s
;
1364 samp
.TCYAddressControlMode
= wrap_t
;
1365 samp
.TCZAddressControlMode
= wrap_r
;
1366 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1367 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1368 samp
.MinModeFilter
= state
->min_img_filter
;
1369 samp
.MagModeFilter
= mag_img_filter
;
1370 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1371 samp
.MaximumAnisotropy
= RATIO21
;
1373 if (state
->max_anisotropy
>= 2) {
1374 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1375 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1376 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1379 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1380 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1382 samp
.MaximumAnisotropy
=
1383 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1386 /* Set address rounding bits if not using nearest filtering. */
1387 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1388 samp
.UAddressMinFilterRoundingEnable
= true;
1389 samp
.VAddressMinFilterRoundingEnable
= true;
1390 samp
.RAddressMinFilterRoundingEnable
= true;
1393 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1394 samp
.UAddressMagFilterRoundingEnable
= true;
1395 samp
.VAddressMagFilterRoundingEnable
= true;
1396 samp
.RAddressMagFilterRoundingEnable
= true;
1399 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1400 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1402 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1404 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1405 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1406 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1407 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1409 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1416 * The pipe->bind_sampler_states() driver hook.
1418 * Now that we know all the sampler states, we upload them all into a
1419 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1420 * We also fill out the border color state pointers at this point.
1422 * We could defer this work to draw time, but we assume that binding
1423 * will be less frequent than drawing.
1425 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1426 // XXX: with the complete set of shaders. If it makes multiple calls to
1427 // XXX: things one at a time, we could waste a lot of time assembling things.
1428 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1429 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1431 iris_bind_sampler_states(struct pipe_context
*ctx
,
1432 enum pipe_shader_type p_stage
,
1433 unsigned start
, unsigned count
,
1436 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1437 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1438 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1440 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1442 for (int i
= 0; i
< count
; i
++) {
1443 shs
->samplers
[start
+ i
] = states
[i
];
1446 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1447 * in the dynamic state memory zone, so we can point to it via the
1448 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1451 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1452 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1456 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1457 shs
->sampler_table
.offset
+=
1458 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1460 /* Make sure all land in the same BO */
1461 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1463 for (int i
= 0; i
< count
; i
++) {
1464 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1467 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1468 } else if (!state
->needs_border_color
) {
1469 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1471 ice
->state
.need_border_colors
= true;
1473 /* Stream out the border color and merge the pointer. */
1475 iris_upload_border_color(ice
, &state
->border_color
);
1477 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1478 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1479 dyns
.BorderColorPointer
= offset
;
1482 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1483 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1486 map
+= GENX(SAMPLER_STATE_length
);
1489 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1492 static enum isl_channel_select
1493 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1496 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1497 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1498 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1499 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1500 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1501 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1502 default: unreachable("invalid swizzle");
1507 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1510 enum isl_format format
,
1514 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1515 const unsigned cpp
= fmtl
->bpb
/ 8;
1517 /* The ARB_texture_buffer_specification says:
1519 * "The number of texels in the buffer texture's texel array is given by
1521 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1523 * where <buffer_size> is the size of the buffer object, in basic
1524 * machine units and <components> and <base_type> are the element count
1525 * and base data type for elements, as specified in Table X.1. The
1526 * number of texels in the texel array is then clamped to the
1527 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1529 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1530 * so that when ISL divides by stride to obtain the number of texels, that
1531 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1533 unsigned final_size
=
1534 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1536 isl_buffer_fill_state(isl_dev
, map
,
1537 .address
= bo
->gtt_offset
+ offset
,
1538 .size_B
= final_size
,
1545 * Allocate a SURFACE_STATE structure.
1548 alloc_surface_states(struct u_upload_mgr
*mgr
,
1549 struct iris_state_ref
*ref
)
1551 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1553 void *map
= upload_state(mgr
, ref
, surf_size
, 64);
1555 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1561 fill_surface_state(struct isl_device
*isl_dev
,
1563 struct iris_resource
*res
,
1564 struct isl_view
*view
)
1566 struct isl_surf_fill_state_info f
= {
1569 .mocs
= mocs(res
->bo
),
1570 .address
= res
->bo
->gtt_offset
,
1573 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1577 * The pipe->create_sampler_view() driver hook.
1579 static struct pipe_sampler_view
*
1580 iris_create_sampler_view(struct pipe_context
*ctx
,
1581 struct pipe_resource
*tex
,
1582 const struct pipe_sampler_view
*tmpl
)
1584 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1585 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1586 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1587 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1592 /* initialize base object */
1594 isv
->base
.context
= ctx
;
1595 isv
->base
.texture
= NULL
;
1596 pipe_reference_init(&isv
->base
.reference
, 1);
1597 pipe_resource_reference(&isv
->base
.texture
, tex
);
1599 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1600 &isv
->surface_state
);
1604 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1605 struct iris_resource
*zres
, *sres
;
1606 const struct util_format_description
*desc
=
1607 util_format_description(tmpl
->format
);
1609 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1611 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1614 isv
->res
= (struct iris_resource
*) tex
;
1616 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1618 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1619 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1620 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1622 const struct iris_format_info fmt
=
1623 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1625 isv
->view
= (struct isl_view
) {
1627 .swizzle
= (struct isl_swizzle
) {
1628 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1629 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1630 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1631 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1636 /* Fill out SURFACE_STATE for this view. */
1637 if (tmpl
->target
!= PIPE_BUFFER
) {
1638 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1639 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1640 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1641 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1642 isv
->view
.array_len
=
1643 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1645 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
);
1647 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1648 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1656 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1657 struct pipe_sampler_view
*state
)
1659 struct iris_sampler_view
*isv
= (void *) state
;
1660 pipe_resource_reference(&state
->texture
, NULL
);
1661 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1666 * The pipe->create_surface() driver hook.
1668 * In Gallium nomenclature, "surfaces" are a view of a resource that
1669 * can be bound as a render target or depth/stencil buffer.
1671 static struct pipe_surface
*
1672 iris_create_surface(struct pipe_context
*ctx
,
1673 struct pipe_resource
*tex
,
1674 const struct pipe_surface
*tmpl
)
1676 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1677 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1678 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1679 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1680 struct pipe_surface
*psurf
= &surf
->base
;
1681 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1686 pipe_reference_init(&psurf
->reference
, 1);
1687 pipe_resource_reference(&psurf
->texture
, tex
);
1688 psurf
->context
= ctx
;
1689 psurf
->format
= tmpl
->format
;
1690 psurf
->width
= tex
->width0
;
1691 psurf
->height
= tex
->height0
;
1692 psurf
->texture
= tex
;
1693 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1694 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1695 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1697 isl_surf_usage_flags_t usage
= 0;
1699 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1700 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1701 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1703 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1705 const struct iris_format_info fmt
=
1706 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1708 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1709 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1710 /* Framebuffer validation will reject this invalid case, but it
1711 * hasn't had the opportunity yet. In the meantime, we need to
1712 * avoid hitting ISL asserts about unsupported formats below.
1718 surf
->view
= (struct isl_view
) {
1720 .base_level
= tmpl
->u
.tex
.level
,
1722 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1723 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1724 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1728 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1729 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1730 ISL_SURF_USAGE_STENCIL_BIT
))
1734 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1735 &surf
->surface_state
);
1739 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
);
1745 * The pipe->set_shader_images() driver hook.
1748 iris_set_shader_images(struct pipe_context
*ctx
,
1749 enum pipe_shader_type p_stage
,
1750 unsigned start_slot
, unsigned count
,
1751 const struct pipe_image_view
*p_images
)
1753 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1754 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1755 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1756 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1757 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1759 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1761 for (unsigned i
= 0; i
< count
; i
++) {
1762 if (p_images
&& p_images
[i
].resource
) {
1763 const struct pipe_image_view
*img
= &p_images
[i
];
1764 struct iris_resource
*res
= (void *) img
->resource
;
1765 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1767 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1769 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1771 // XXX: these are not retained forever, use a separate uploader?
1773 alloc_surface_states(ice
->state
.surface_uploader
,
1774 &shs
->image
[start_slot
+ i
].surface_state
);
1775 if (!unlikely(map
)) {
1776 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1780 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1781 enum isl_format isl_format
=
1782 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1784 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1785 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1787 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1789 if (res
->base
.target
!= PIPE_BUFFER
) {
1790 struct isl_view view
= {
1791 .format
= isl_format
,
1792 .base_level
= img
->u
.tex
.level
,
1794 .base_array_layer
= img
->u
.tex
.first_layer
,
1795 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1796 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1800 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
);
1802 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1803 isl_format
, img
->u
.buf
.offset
,
1807 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1808 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1813 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1818 * The pipe->set_sampler_views() driver hook.
1821 iris_set_sampler_views(struct pipe_context
*ctx
,
1822 enum pipe_shader_type p_stage
,
1823 unsigned start
, unsigned count
,
1824 struct pipe_sampler_view
**views
)
1826 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1827 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1828 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1830 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1832 for (unsigned i
= 0; i
< count
; i
++) {
1833 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1834 &shs
->textures
[start
+ i
], views
[i
]);
1835 struct iris_sampler_view
*view
= (void *) views
[i
];
1837 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1838 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1842 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1846 * The pipe->set_tess_state() driver hook.
1849 iris_set_tess_state(struct pipe_context
*ctx
,
1850 const float default_outer_level
[4],
1851 const float default_inner_level
[2])
1853 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1855 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1856 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1858 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1862 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1864 struct iris_surface
*surf
= (void *) p_surf
;
1865 pipe_resource_reference(&p_surf
->texture
, NULL
);
1866 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1871 iris_set_clip_state(struct pipe_context
*ctx
,
1872 const struct pipe_clip_state
*state
)
1874 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1875 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1877 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1879 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1880 shs
->cbuf0_needs_upload
= true;
1884 * The pipe->set_polygon_stipple() driver hook.
1887 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1888 const struct pipe_poly_stipple
*state
)
1890 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1891 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1892 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1896 * The pipe->set_sample_mask() driver hook.
1899 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1901 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1903 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1904 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1906 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1907 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1911 * The pipe->set_scissor_states() driver hook.
1913 * This corresponds to our SCISSOR_RECT state structures. It's an
1914 * exact match, so we just store them, and memcpy them out later.
1917 iris_set_scissor_states(struct pipe_context
*ctx
,
1918 unsigned start_slot
,
1919 unsigned num_scissors
,
1920 const struct pipe_scissor_state
*rects
)
1922 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1924 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1925 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1926 /* If the scissor was out of bounds and got clamped to 0 width/height
1927 * at the bounds, the subtraction of 1 from maximums could produce a
1928 * negative number and thus not clip anything. Instead, just provide
1929 * a min > max scissor inside the bounds, which produces the expected
1932 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1933 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1936 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1937 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1938 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1943 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1947 * The pipe->set_stencil_ref() driver hook.
1949 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1952 iris_set_stencil_ref(struct pipe_context
*ctx
,
1953 const struct pipe_stencil_ref
*state
)
1955 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1956 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1958 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1960 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1964 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1966 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1970 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1971 float m00
, float m11
, float m30
, float m31
,
1972 float *xmin
, float *xmax
,
1973 float *ymin
, float *ymax
)
1975 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1976 * Strips and Fans documentation:
1978 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1979 * fixed-point "guardband" range supported by the rasterization hardware"
1983 * "In almost all circumstances, if an object’s vertices are actually
1984 * modified by this clamping (i.e., had X or Y coordinates outside of
1985 * the guardband extent the rendered object will not match the intended
1986 * result. Therefore software should take steps to ensure that this does
1987 * not happen - e.g., by clipping objects such that they do not exceed
1988 * these limits after the Drawing Rectangle is applied."
1990 * I believe the fundamental restriction is that the rasterizer (in
1991 * the SF/WM stages) have a limit on the number of pixels that can be
1992 * rasterized. We need to ensure any coordinates beyond the rasterizer
1993 * limit are handled by the clipper. So effectively that limit becomes
1994 * the clipper's guardband size.
1996 * It goes on to say:
1998 * "In addition, in order to be correctly rendered, objects must have a
1999 * screenspace bounding box not exceeding 8K in the X or Y direction.
2000 * This additional restriction must also be comprehended by software,
2001 * i.e., enforced by use of clipping."
2003 * This makes no sense. Gen7+ hardware supports 16K render targets,
2004 * and you definitely need to be able to draw polygons that fill the
2005 * surface. Our assumption is that the rasterizer was limited to 8K
2006 * on Sandybridge, which only supports 8K surfaces, and it was actually
2007 * increased to 16K on Ivybridge and later.
2009 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2011 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2013 if (m00
!= 0 && m11
!= 0) {
2014 /* First, we compute the screen-space render area */
2015 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2016 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2017 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2018 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2020 /* We want the guardband to be centered on that */
2021 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2022 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2023 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2024 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2026 /* Now we need it in native device coordinates */
2027 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2028 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2029 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2030 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2032 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2033 * flipped upside-down. X should be fine though.
2035 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2036 *xmin
= ndc_gb_xmin
;
2037 *xmax
= ndc_gb_xmax
;
2038 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2039 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2041 /* The viewport scales to 0, so nothing will be rendered. */
2050 * The pipe->set_viewport_states() driver hook.
2052 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2053 * the guardband yet, as we need the framebuffer dimensions, but we can
2054 * at least fill out the rest.
2057 iris_set_viewport_states(struct pipe_context
*ctx
,
2058 unsigned start_slot
,
2060 const struct pipe_viewport_state
*states
)
2062 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2064 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2066 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2068 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2069 !ice
->state
.cso_rast
->depth_clip_far
))
2070 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2074 * The pipe->set_framebuffer_state() driver hook.
2076 * Sets the current draw FBO, including color render targets, depth,
2077 * and stencil buffers.
2080 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2081 const struct pipe_framebuffer_state
*state
)
2083 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2084 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2085 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2086 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2087 struct iris_resource
*zres
;
2088 struct iris_resource
*stencil_res
;
2090 unsigned samples
= util_framebuffer_get_num_samples(state
);
2092 if (cso
->samples
!= samples
) {
2093 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2096 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2097 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2100 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2101 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2104 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2105 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2108 util_copy_framebuffer_state(cso
, state
);
2109 cso
->samples
= samples
;
2111 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2113 struct isl_view view
= {
2116 .base_array_layer
= 0,
2118 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2121 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2124 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2127 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2128 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2130 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2133 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2135 info
.depth_surf
= &zres
->surf
;
2136 info
.depth_address
= zres
->bo
->gtt_offset
;
2137 info
.mocs
= mocs(zres
->bo
);
2139 view
.format
= zres
->surf
.format
;
2143 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2144 info
.stencil_surf
= &stencil_res
->surf
;
2145 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2147 view
.format
= stencil_res
->surf
.format
;
2148 info
.mocs
= mocs(stencil_res
->bo
);
2153 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2155 /* Make a null surface for unbound buffers */
2156 void *null_surf_map
=
2157 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2158 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2159 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2160 isl_extent3d(MAX2(cso
->width
, 1),
2161 MAX2(cso
->height
, 1),
2162 cso
->layers
? cso
->layers
: 1));
2163 ice
->state
.null_fb
.offset
+=
2164 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2166 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2168 /* Render target change */
2169 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2171 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2174 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2175 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2177 /* The PIPE_CONTROL command description says:
2179 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2180 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2181 * Target Cache Flush by enabling this bit. When render target flush
2182 * is set due to new association of BTI, PS Scoreboard Stall bit must
2183 * be set in this packet."
2185 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2186 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2187 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2188 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2193 upload_ubo_surf_state(struct iris_context
*ice
,
2194 struct iris_const_buffer
*cbuf
,
2195 unsigned buffer_size
)
2197 struct pipe_context
*ctx
= &ice
->ctx
;
2198 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2200 // XXX: these are not retained forever, use a separate uploader?
2202 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2203 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2204 if (!unlikely(map
)) {
2205 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2209 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2210 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2211 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2213 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2214 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2215 .size_B
= MIN2(buffer_size
,
2216 res
->bo
->size
- cbuf
->data
.offset
),
2217 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2219 .mocs
= mocs(res
->bo
))
2223 * The pipe->set_constant_buffer() driver hook.
2225 * This uploads any constant data in user buffers, and references
2226 * any UBO resources containing constant data.
2229 iris_set_constant_buffer(struct pipe_context
*ctx
,
2230 enum pipe_shader_type p_stage
, unsigned index
,
2231 const struct pipe_constant_buffer
*input
)
2233 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2234 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2235 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2236 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2238 if (input
&& input
->buffer
) {
2241 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2242 cbuf
->data
.offset
= input
->buffer_offset
;
2244 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2245 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2247 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2249 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2250 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2255 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2257 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2259 shs
->cbuf0_needs_upload
= true;
2262 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2263 // XXX: maybe not necessary all the time...?
2264 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2265 // XXX: pull model we may need actual new bindings...
2266 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2270 upload_uniforms(struct iris_context
*ice
,
2271 gl_shader_stage stage
)
2273 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2274 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2275 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2277 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2278 shs
->cbuf0
.buffer_size
;
2280 if (upload_size
== 0)
2284 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2286 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2287 uint32_t sysval
= shader
->system_values
[i
];
2290 if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2291 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2292 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2293 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2294 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2295 if (stage
== MESA_SHADER_TESS_CTRL
) {
2296 value
= ice
->state
.vertices_per_patch
;
2298 assert(stage
== MESA_SHADER_TESS_EVAL
);
2299 const struct shader_info
*tcs_info
=
2300 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2303 value
= tcs_info
->tess
.tcs_vertices_out
;
2306 assert(!"unhandled system value");
2312 if (shs
->cbuf0
.user_buffer
) {
2313 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2316 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2320 * The pipe->set_shader_buffers() driver hook.
2322 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2323 * SURFACE_STATE here, as the buffer offset may change each time.
2326 iris_set_shader_buffers(struct pipe_context
*ctx
,
2327 enum pipe_shader_type p_stage
,
2328 unsigned start_slot
, unsigned count
,
2329 const struct pipe_shader_buffer
*buffers
)
2331 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2332 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2333 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2334 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2336 for (unsigned i
= 0; i
< count
; i
++) {
2337 if (buffers
&& buffers
[i
].buffer
) {
2338 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2339 struct iris_resource
*res
= (void *) buffer
->buffer
;
2340 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2342 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2344 // XXX: these are not retained forever, use a separate uploader?
2346 upload_state(ice
->state
.surface_uploader
,
2347 &shs
->ssbo_surface_state
[start_slot
+ i
],
2348 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2349 if (!unlikely(map
)) {
2350 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2354 struct iris_bo
*surf_state_bo
=
2355 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2356 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2357 iris_bo_offset_from_base_address(surf_state_bo
);
2359 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2361 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2363 MIN2(buffer
->buffer_size
,
2364 res
->bo
->size
- buffer
->buffer_offset
),
2365 .format
= ISL_FORMAT_RAW
,
2367 .mocs
= mocs(res
->bo
));
2369 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2370 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2375 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2379 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2385 * The pipe->set_vertex_buffers() driver hook.
2387 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2390 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2391 unsigned start_slot
, unsigned count
,
2392 const struct pipe_vertex_buffer
*buffers
)
2394 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2395 struct iris_genx_state
*genx
= ice
->state
.genx
;
2397 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2399 for (unsigned i
= 0; i
< count
; i
++) {
2400 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2401 struct iris_vertex_buffer_state
*state
=
2402 &genx
->vertex_buffers
[start_slot
+ i
];
2405 pipe_resource_reference(&state
->resource
, NULL
);
2409 assert(!buffer
->is_user_buffer
);
2411 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2413 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2414 struct iris_resource
*res
= (void *) state
->resource
;
2417 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2419 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2420 vb
.VertexBufferIndex
= start_slot
+ i
;
2421 vb
.AddressModifyEnable
= true;
2422 vb
.BufferPitch
= buffer
->stride
;
2424 vb
.BufferSize
= res
->bo
->size
;
2425 vb
.BufferStartingAddress
=
2426 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2427 vb
.MOCS
= mocs(res
->bo
);
2429 vb
.NullVertexBuffer
= true;
2434 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2438 * Gallium CSO for vertex elements.
2440 struct iris_vertex_element_state
{
2441 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2442 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2447 * The pipe->create_vertex_elements() driver hook.
2449 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2450 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2453 iris_create_vertex_elements(struct pipe_context
*ctx
,
2455 const struct pipe_vertex_element
*state
)
2457 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2458 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2459 struct iris_vertex_element_state
*cso
=
2460 malloc(sizeof(struct iris_vertex_element_state
));
2465 * - create edge flag one
2467 * - if those are necessary, use count + 1/2/3... OR in the length
2469 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2471 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2474 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2475 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2478 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2480 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2481 ve
.Component0Control
= VFCOMP_STORE_0
;
2482 ve
.Component1Control
= VFCOMP_STORE_0
;
2483 ve
.Component2Control
= VFCOMP_STORE_0
;
2484 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2487 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2491 for (int i
= 0; i
< count
; i
++) {
2492 const struct iris_format_info fmt
=
2493 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2494 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2495 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2497 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2498 case 0: comp
[0] = VFCOMP_STORE_0
;
2499 case 1: comp
[1] = VFCOMP_STORE_0
;
2500 case 2: comp
[2] = VFCOMP_STORE_0
;
2502 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2503 : VFCOMP_STORE_1_FP
;
2506 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2507 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2509 ve
.SourceElementOffset
= state
[i
].src_offset
;
2510 ve
.SourceElementFormat
= fmt
.fmt
;
2511 ve
.Component0Control
= comp
[0];
2512 ve
.Component1Control
= comp
[1];
2513 ve
.Component2Control
= comp
[2];
2514 ve
.Component3Control
= comp
[3];
2517 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2518 vi
.VertexElementIndex
= i
;
2519 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2520 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2523 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2524 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2531 * The pipe->bind_vertex_elements_state() driver hook.
2534 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2536 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2537 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2538 struct iris_vertex_element_state
*new_cso
= state
;
2540 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2541 * we need to re-emit it to ensure we're overriding the right one.
2543 if (new_cso
&& cso_changed(count
))
2544 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2546 ice
->state
.cso_vertex_elements
= state
;
2547 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2551 * The pipe->create_stream_output_target() driver hook.
2553 * "Target" here refers to a destination buffer. We translate this into
2554 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2555 * know which buffer this represents, or whether we ought to zero the
2556 * write-offsets, or append. Those are handled in the set() hook.
2558 static struct pipe_stream_output_target
*
2559 iris_create_stream_output_target(struct pipe_context
*ctx
,
2560 struct pipe_resource
*p_res
,
2561 unsigned buffer_offset
,
2562 unsigned buffer_size
)
2564 struct iris_resource
*res
= (void *) p_res
;
2565 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2569 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2571 pipe_reference_init(&cso
->base
.reference
, 1);
2572 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2573 cso
->base
.buffer_offset
= buffer_offset
;
2574 cso
->base
.buffer_size
= buffer_size
;
2575 cso
->base
.context
= ctx
;
2577 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2583 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2584 struct pipe_stream_output_target
*state
)
2586 struct iris_stream_output_target
*cso
= (void *) state
;
2588 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2589 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2595 * The pipe->set_stream_output_targets() driver hook.
2597 * At this point, we know which targets are bound to a particular index,
2598 * and also whether we want to append or start over. We can finish the
2599 * 3DSTATE_SO_BUFFER packets we started earlier.
2602 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2603 unsigned num_targets
,
2604 struct pipe_stream_output_target
**targets
,
2605 const unsigned *offsets
)
2607 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2608 struct iris_genx_state
*genx
= ice
->state
.genx
;
2609 uint32_t *so_buffers
= genx
->so_buffers
;
2611 const bool active
= num_targets
> 0;
2612 if (ice
->state
.streamout_active
!= active
) {
2613 ice
->state
.streamout_active
= active
;
2614 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2616 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2617 * it's a non-pipelined command. If we're switching streamout on, we
2618 * may have missed emitting it earlier, so do so now. (We're already
2619 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2622 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2625 for (int i
= 0; i
< 4; i
++) {
2626 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2627 i
< num_targets
? targets
[i
] : NULL
);
2630 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2634 for (unsigned i
= 0; i
< 4; i
++,
2635 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2637 if (i
>= num_targets
|| !targets
[i
]) {
2638 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2639 sob
.SOBufferIndex
= i
;
2643 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2644 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2646 /* Note that offsets[i] will either be 0, causing us to zero
2647 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2648 * "continue appending at the existing offset."
2650 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2652 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
2653 sob
.SurfaceBaseAddress
=
2654 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
2655 sob
.SOBufferEnable
= true;
2656 sob
.StreamOffsetWriteEnable
= true;
2657 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2658 sob
.MOCS
= mocs(res
->bo
);
2660 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
2662 sob
.SOBufferIndex
= i
;
2663 sob
.StreamOffset
= offsets
[i
];
2664 sob
.StreamOutputBufferOffsetAddress
=
2665 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
2666 tgt
->offset
.offset
);
2670 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2674 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2675 * 3DSTATE_STREAMOUT packets.
2677 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2678 * hardware to record. We can create it entirely based on the shader, with
2679 * no dynamic state dependencies.
2681 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2682 * state-based settings. We capture the shader-related ones here, and merge
2683 * the rest in at draw time.
2686 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2687 const struct brw_vue_map
*vue_map
)
2689 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2690 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2691 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2692 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2694 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2696 memset(so_decl
, 0, sizeof(so_decl
));
2698 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2699 * command feels strange -- each dword pair contains a SO_DECL per stream.
2701 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2702 const struct pipe_stream_output
*output
= &info
->output
[i
];
2703 const int buffer
= output
->output_buffer
;
2704 const int varying
= output
->register_index
;
2705 const unsigned stream_id
= output
->stream
;
2706 assert(stream_id
< MAX_VERTEX_STREAMS
);
2708 buffer_mask
[stream_id
] |= 1 << buffer
;
2710 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2712 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2713 * array. Instead, it simply increments DstOffset for the following
2714 * input by the number of components that should be skipped.
2716 * Our hardware is unusual in that it requires us to program SO_DECLs
2717 * for fake "hole" components, rather than simply taking the offset
2718 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2719 * program as many size = 4 holes as we can, then a final hole to
2720 * accommodate the final 1, 2, or 3 remaining.
2722 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2724 while (skip_components
> 0) {
2725 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2727 .OutputBufferSlot
= output
->output_buffer
,
2728 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2730 skip_components
-= 4;
2733 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2735 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2736 .OutputBufferSlot
= output
->output_buffer
,
2737 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2739 ((1 << output
->num_components
) - 1) << output
->start_component
,
2742 if (decls
[stream_id
] > max_decls
)
2743 max_decls
= decls
[stream_id
];
2746 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2747 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2748 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2750 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2751 int urb_entry_read_offset
= 0;
2752 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2753 urb_entry_read_offset
;
2755 /* We always read the whole vertex. This could be reduced at some
2756 * point by reading less and offsetting the register index in the
2759 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2760 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2761 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2762 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2763 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2764 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2765 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2766 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2768 /* Set buffer pitches; 0 means unbound. */
2769 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2770 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2771 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2772 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2775 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2776 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2777 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2778 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2779 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2780 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2781 list
.NumEntries0
= decls
[0];
2782 list
.NumEntries1
= decls
[1];
2783 list
.NumEntries2
= decls
[2];
2784 list
.NumEntries3
= decls
[3];
2787 for (int i
= 0; i
< max_decls
; i
++) {
2788 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2789 entry
.Stream0Decl
= so_decl
[0][i
];
2790 entry
.Stream1Decl
= so_decl
[1][i
];
2791 entry
.Stream2Decl
= so_decl
[2][i
];
2792 entry
.Stream3Decl
= so_decl
[3][i
];
2800 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2801 const struct brw_vue_map
*last_vue_map
,
2802 bool two_sided_color
,
2803 unsigned *out_offset
,
2804 unsigned *out_length
)
2806 /* The compiler computes the first URB slot without considering COL/BFC
2807 * swizzling (because it doesn't know whether it's enabled), so we need
2808 * to do that here too. This may result in a smaller offset, which
2811 const unsigned first_slot
=
2812 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2814 /* This becomes the URB read offset (counted in pairs of slots). */
2815 assert(first_slot
% 2 == 0);
2816 *out_offset
= first_slot
/ 2;
2818 /* We need to adjust the inputs read to account for front/back color
2819 * swizzling, as it can make the URB length longer.
2821 for (int c
= 0; c
<= 1; c
++) {
2822 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2823 /* If two sided color is enabled, the fragment shader's gl_Color
2824 * (COL0) input comes from either the gl_FrontColor (COL0) or
2825 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2827 if (two_sided_color
)
2828 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2830 /* If front color isn't written, we opt to give them back color
2831 * instead of an undefined value. Switch from COL to BFC.
2833 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2834 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2835 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2840 /* Compute the minimum URB Read Length necessary for the FS inputs.
2842 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2843 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2845 * "This field should be set to the minimum length required to read the
2846 * maximum source attribute. The maximum source attribute is indicated
2847 * by the maximum value of the enabled Attribute # Source Attribute if
2848 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2849 * enable is not set.
2850 * read_length = ceiling((max_source_attr + 1) / 2)
2852 * [errata] Corruption/Hang possible if length programmed larger than
2855 * Similar text exists for Ivy Bridge.
2857 * We find the last URB slot that's actually read by the FS.
2859 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2860 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2861 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2864 /* The URB read length is the difference of the two, counted in pairs. */
2865 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2869 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2870 const struct iris_context
*ice
,
2871 unsigned urb_read_offset
,
2872 unsigned sprite_coord_enables
)
2874 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2875 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2876 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2877 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2878 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2880 /* XXX: this should be generated when putting programs in place */
2882 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2883 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2884 if (input_index
< 0 || input_index
>= 16)
2887 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2888 &attr_overrides
[input_index
];
2889 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2891 /* Viewport and Layer are stored in the VUE header. We need to override
2892 * them to zero if earlier stages didn't write them, as GL requires that
2893 * they read back as zero when not explicitly set.
2896 case VARYING_SLOT_VIEWPORT
:
2897 case VARYING_SLOT_LAYER
:
2898 attr
->ComponentOverrideX
= true;
2899 attr
->ComponentOverrideW
= true;
2900 attr
->ConstantSource
= CONST_0000
;
2902 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2903 attr
->ComponentOverrideY
= true;
2904 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2905 attr
->ComponentOverrideZ
= true;
2908 case VARYING_SLOT_PRIMITIVE_ID
:
2909 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2911 attr
->ComponentOverrideX
= true;
2912 attr
->ComponentOverrideY
= true;
2913 attr
->ComponentOverrideZ
= true;
2914 attr
->ComponentOverrideW
= true;
2915 attr
->ConstantSource
= PRIM_ID
;
2923 if (sprite_coord_enables
& (1 << input_index
))
2926 /* If there was only a back color written but not front, use back
2927 * as the color instead of undefined.
2929 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2930 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2931 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2932 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2934 /* Not written by the previous stage - undefined. */
2936 attr
->ComponentOverrideX
= true;
2937 attr
->ComponentOverrideY
= true;
2938 attr
->ComponentOverrideZ
= true;
2939 attr
->ComponentOverrideW
= true;
2940 attr
->ConstantSource
= CONST_0001_FLOAT
;
2944 /* Compute the location of the attribute relative to the read offset,
2945 * which is counted in 256-bit increments (two 128-bit VUE slots).
2947 const int source_attr
= slot
- 2 * urb_read_offset
;
2948 assert(source_attr
>= 0 && source_attr
<= 32);
2949 attr
->SourceAttribute
= source_attr
;
2951 /* If we are doing two-sided color, and the VUE slot following this one
2952 * represents a back-facing color, then we need to instruct the SF unit
2953 * to do back-facing swizzling.
2955 if (cso_rast
->light_twoside
&&
2956 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2957 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2958 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2959 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2960 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2963 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2964 for (int i
= 0; i
< 16; i
++)
2965 sbes
.Attribute
[i
] = attr_overrides
[i
];
2970 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2971 const struct iris_rasterizer_state
*cso
)
2973 unsigned overrides
= 0;
2975 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2976 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2978 for (int i
= 0; i
< 8; i
++) {
2979 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2980 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2981 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2988 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2990 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2991 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2992 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2993 const struct shader_info
*fs_info
=
2994 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2996 unsigned urb_read_offset
, urb_read_length
;
2997 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2998 ice
->shaders
.last_vue_map
,
2999 cso_rast
->light_twoside
,
3000 &urb_read_offset
, &urb_read_length
);
3002 unsigned sprite_coord_overrides
=
3003 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3005 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3006 sbe
.AttributeSwizzleEnable
= true;
3007 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3008 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3009 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3010 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3011 sbe
.ForceVertexURBEntryReadOffset
= true;
3012 sbe
.ForceVertexURBEntryReadLength
= true;
3013 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3014 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3016 for (int i
= 0; i
< 32; i
++) {
3017 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3022 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3025 /* ------------------------------------------------------------------- */
3028 * Populate VS program key fields based on the current state.
3031 iris_populate_vs_key(const struct iris_context
*ice
,
3032 const struct shader_info
*info
,
3033 struct brw_vs_prog_key
*key
)
3035 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3037 if (info
->clip_distance_array_size
== 0 &&
3038 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3039 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3043 * Populate TCS program key fields based on the current state.
3046 iris_populate_tcs_key(const struct iris_context
*ice
,
3047 struct brw_tcs_prog_key
*key
)
3052 * Populate TES program key fields based on the current state.
3055 iris_populate_tes_key(const struct iris_context
*ice
,
3056 struct brw_tes_prog_key
*key
)
3061 * Populate GS program key fields based on the current state.
3064 iris_populate_gs_key(const struct iris_context
*ice
,
3065 struct brw_gs_prog_key
*key
)
3070 * Populate FS program key fields based on the current state.
3073 iris_populate_fs_key(const struct iris_context
*ice
,
3074 struct brw_wm_prog_key
*key
)
3076 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3077 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3078 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3079 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3081 key
->nr_color_regions
= fb
->nr_cbufs
;
3083 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3085 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3086 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3088 /* XXX: only bother if COL0/1 are read */
3089 key
->flat_shade
= rast
->flatshade
;
3091 key
->persample_interp
= rast
->force_persample_interp
;
3092 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3094 key
->coherent_fb_fetch
= true;
3096 // XXX: key->force_dual_color_blend for unigine
3097 // XXX: respect hint for high_quality_derivatives:1;
3101 iris_populate_cs_key(const struct iris_context
*ice
,
3102 struct brw_cs_prog_key
*key
)
3107 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3108 pkt
.SamplerCount
= \
3109 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3114 KSP(const struct iris_compiled_shader
*shader
)
3116 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3117 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3120 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3121 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3122 // this WA on C0 stepping.
3124 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3125 pkt.KernelStartPointer = KSP(shader); \
3126 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3127 prog_data->binding_table.size_bytes / 4; \
3128 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3130 pkt.DispatchGRFStartRegisterForURBData = \
3131 prog_data->dispatch_grf_start_reg; \
3132 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3133 pkt.prefix##URBEntryReadOffset = 0; \
3135 pkt.StatisticsEnable = true; \
3136 pkt.Enable = true; \
3138 if (prog_data->total_scratch) { \
3139 struct iris_bo *bo = \
3140 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3141 uint32_t scratch_addr = bo->gtt_offset; \
3142 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3143 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3147 * Encode most of 3DSTATE_VS based on the compiled shader.
3150 iris_store_vs_state(struct iris_context
*ice
,
3151 const struct gen_device_info
*devinfo
,
3152 struct iris_compiled_shader
*shader
)
3154 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3155 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3157 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3158 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3159 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3160 vs
.SIMD8DispatchEnable
= true;
3161 vs
.UserClipDistanceCullTestEnableBitmask
=
3162 vue_prog_data
->cull_distance_mask
;
3167 * Encode most of 3DSTATE_HS based on the compiled shader.
3170 iris_store_tcs_state(struct iris_context
*ice
,
3171 const struct gen_device_info
*devinfo
,
3172 struct iris_compiled_shader
*shader
)
3174 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3175 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3176 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3178 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3179 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3181 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3182 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3183 hs
.IncludeVertexHandles
= true;
3188 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3191 iris_store_tes_state(struct iris_context
*ice
,
3192 const struct gen_device_info
*devinfo
,
3193 struct iris_compiled_shader
*shader
)
3195 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3196 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3197 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3199 uint32_t *te_state
= (void *) shader
->derived_data
;
3200 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3202 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3203 te
.Partitioning
= tes_prog_data
->partitioning
;
3204 te
.OutputTopology
= tes_prog_data
->output_topology
;
3205 te
.TEDomain
= tes_prog_data
->domain
;
3207 te
.MaximumTessellationFactorOdd
= 63.0;
3208 te
.MaximumTessellationFactorNotOdd
= 64.0;
3211 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3212 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3214 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3215 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3216 ds
.ComputeWCoordinateEnable
=
3217 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3219 ds
.UserClipDistanceCullTestEnableBitmask
=
3220 vue_prog_data
->cull_distance_mask
;
3226 * Encode most of 3DSTATE_GS based on the compiled shader.
3229 iris_store_gs_state(struct iris_context
*ice
,
3230 const struct gen_device_info
*devinfo
,
3231 struct iris_compiled_shader
*shader
)
3233 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3234 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3235 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3237 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3238 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3240 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3241 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3242 gs
.ControlDataHeaderSize
=
3243 gs_prog_data
->control_data_header_size_hwords
;
3244 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3245 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3246 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3247 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3248 gs
.ReorderMode
= TRAILING
;
3249 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3250 gs
.MaximumNumberofThreads
=
3251 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3252 : (devinfo
->max_gs_threads
- 1);
3254 if (gs_prog_data
->static_vertex_count
!= -1) {
3255 gs
.StaticOutput
= true;
3256 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3258 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3260 gs
.UserClipDistanceCullTestEnableBitmask
=
3261 vue_prog_data
->cull_distance_mask
;
3263 const int urb_entry_write_offset
= 1;
3264 const uint32_t urb_entry_output_length
=
3265 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3266 urb_entry_write_offset
;
3268 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3269 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3274 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3277 iris_store_fs_state(struct iris_context
*ice
,
3278 const struct gen_device_info
*devinfo
,
3279 struct iris_compiled_shader
*shader
)
3281 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3282 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3284 uint32_t *ps_state
= (void *) shader
->derived_data
;
3285 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3287 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3288 ps
.VectorMaskEnable
= true;
3289 //ps.SamplerCount = ...
3290 // XXX: WABTPPrefetchDisable, see above, drop at C0
3291 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3292 prog_data
->binding_table
.size_bytes
/ 4;
3293 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3294 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3296 ps
.PushConstantEnable
= shader
->num_system_values
> 0 ||
3297 prog_data
->ubo_ranges
[0].length
> 0;
3299 /* From the documentation for this packet:
3300 * "If the PS kernel does not need the Position XY Offsets to
3301 * compute a Position Value, then this field should be programmed
3302 * to POSOFFSET_NONE."
3304 * "SW Recommendation: If the PS kernel needs the Position Offsets
3305 * to compute a Position XY value, this field should match Position
3306 * ZW Interpolation Mode to ensure a consistent position.xyzw
3309 * We only require XY sample offsets. So, this recommendation doesn't
3310 * look useful at the moment. We might need this in future.
3312 ps
.PositionXYOffsetSelect
=
3313 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3314 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3315 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3316 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3318 // XXX: Disable SIMD32 with 16x MSAA
3320 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3321 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3322 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3323 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3324 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3325 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3327 ps
.KernelStartPointer0
=
3328 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3329 ps
.KernelStartPointer1
=
3330 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3331 ps
.KernelStartPointer2
=
3332 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3334 if (prog_data
->total_scratch
) {
3335 struct iris_bo
*bo
=
3336 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3337 MESA_SHADER_FRAGMENT
);
3338 uint32_t scratch_addr
= bo
->gtt_offset
;
3339 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3340 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3344 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3345 psx
.PixelShaderValid
= true;
3346 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3347 // XXX: alpha test / alpha to coverage :/
3348 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
||
3349 wm_prog_data
->uses_omask
;
3350 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3351 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3352 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3353 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3354 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3357 if (wm_prog_data
->uses_sample_mask
) {
3358 /* TODO: conservative rasterization */
3359 if (wm_prog_data
->post_depth_coverage
)
3360 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3362 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3365 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3366 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3368 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3375 * Compute the size of the derived data (shader command packets).
3377 * This must match the data written by the iris_store_xs_state() functions.
3380 iris_store_cs_state(struct iris_context
*ice
,
3381 const struct gen_device_info
*devinfo
,
3382 struct iris_compiled_shader
*shader
)
3384 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3385 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3386 void *map
= shader
->derived_data
;
3388 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3389 desc
.KernelStartPointer
= KSP(shader
);
3390 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3391 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3392 desc
.SharedLocalMemorySize
=
3393 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3394 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3395 desc
.CrossThreadConstantDataReadLength
=
3396 cs_prog_data
->push
.cross_thread
.regs
;
3401 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3403 assert(cache_id
<= IRIS_CACHE_BLORP
);
3405 static const unsigned dwords
[] = {
3406 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3407 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3408 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3409 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3411 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3412 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3413 [IRIS_CACHE_BLORP
] = 0,
3416 return sizeof(uint32_t) * dwords
[cache_id
];
3420 * Create any state packets corresponding to the given shader stage
3421 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3422 * This means that we can look up a program in the in-memory cache and
3423 * get most of the state packet without having to reconstruct it.
3426 iris_store_derived_program_state(struct iris_context
*ice
,
3427 enum iris_program_cache_id cache_id
,
3428 struct iris_compiled_shader
*shader
)
3430 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3431 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3435 iris_store_vs_state(ice
, devinfo
, shader
);
3437 case IRIS_CACHE_TCS
:
3438 iris_store_tcs_state(ice
, devinfo
, shader
);
3440 case IRIS_CACHE_TES
:
3441 iris_store_tes_state(ice
, devinfo
, shader
);
3444 iris_store_gs_state(ice
, devinfo
, shader
);
3447 iris_store_fs_state(ice
, devinfo
, shader
);
3450 iris_store_cs_state(ice
, devinfo
, shader
);
3451 case IRIS_CACHE_BLORP
:
3458 /* ------------------------------------------------------------------- */
3461 * Configure the URB.
3463 * XXX: write a real comment.
3466 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3468 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3469 const unsigned push_size_kB
= 32;
3470 unsigned entries
[4];
3474 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3475 if (!ice
->shaders
.prog
[i
]) {
3478 struct brw_vue_prog_data
*vue_prog_data
=
3479 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3480 size
[i
] = vue_prog_data
->urb_entry_size
;
3482 assert(size
[i
] != 0);
3485 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3486 1024 * ice
->shaders
.urb_size
,
3487 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3488 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3489 size
, entries
, start
);
3491 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3492 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3493 urb
._3DCommandSubOpcode
+= i
;
3494 urb
.VSURBStartingAddress
= start
[i
];
3495 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3496 urb
.VSNumberofURBEntries
= entries
[i
];
3501 static const uint32_t push_constant_opcodes
[] = {
3502 [MESA_SHADER_VERTEX
] = 21,
3503 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3504 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3505 [MESA_SHADER_GEOMETRY
] = 22,
3506 [MESA_SHADER_FRAGMENT
] = 23,
3507 [MESA_SHADER_COMPUTE
] = 0,
3511 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3513 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3515 iris_use_pinned_bo(batch
, state_bo
, false);
3517 return ice
->state
.unbound_tex
.offset
;
3521 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3523 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3524 if (!ice
->state
.null_fb
.res
)
3525 return use_null_surface(batch
, ice
);
3527 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3529 iris_use_pinned_bo(batch
, state_bo
, false);
3531 return ice
->state
.null_fb
.offset
;
3535 * Add a surface to the validation list, as well as the buffer containing
3536 * the corresponding SURFACE_STATE.
3538 * Returns the binding table entry (offset to SURFACE_STATE).
3541 use_surface(struct iris_batch
*batch
,
3542 struct pipe_surface
*p_surf
,
3545 struct iris_surface
*surf
= (void *) p_surf
;
3547 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3548 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3550 return surf
->surface_state
.offset
;
3554 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3556 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3557 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3559 return isv
->surface_state
.offset
;
3563 use_const_buffer(struct iris_batch
*batch
,
3564 struct iris_context
*ice
,
3565 struct iris_const_buffer
*cbuf
)
3567 if (!cbuf
->surface_state
.res
)
3568 return use_null_surface(batch
, ice
);
3570 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3571 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3573 return cbuf
->surface_state
.offset
;
3577 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3578 struct iris_shader_state
*shs
, int i
)
3581 return use_null_surface(batch
, ice
);
3583 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3585 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3586 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3588 return surf_state
->offset
;
3592 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3593 struct iris_shader_state
*shs
, int i
)
3595 if (!shs
->image
[i
].res
)
3596 return use_null_surface(batch
, ice
);
3598 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3600 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3601 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3602 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3604 return surf_state
->offset
;
3607 #define push_bt_entry(addr) \
3608 assert(addr >= binder_addr); \
3609 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3610 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3612 #define bt_assert(section, exists) \
3613 if (!pin_only) assert(prog_data->binding_table.section == \
3614 (exists) ? s : 0xd0d0d0d0)
3617 * Populate the binding table for a given shader stage.
3619 * This fills out the table of pointers to surfaces required by the shader,
3620 * and also adds those buffers to the validation list so the kernel can make
3621 * resident before running our batch.
3624 iris_populate_binding_table(struct iris_context
*ice
,
3625 struct iris_batch
*batch
,
3626 gl_shader_stage stage
,
3629 const struct iris_binder
*binder
= &ice
->state
.binder
;
3630 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3634 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3635 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3636 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3638 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3639 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3642 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3644 /* TCS passthrough doesn't need a binding table. */
3645 assert(stage
== MESA_SHADER_TESS_CTRL
);
3649 if (stage
== MESA_SHADER_COMPUTE
) {
3650 /* surface for gl_NumWorkGroups */
3651 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3652 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3653 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3654 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3655 push_bt_entry(grid_state
->offset
);
3658 if (stage
== MESA_SHADER_FRAGMENT
) {
3659 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3660 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3661 if (cso_fb
->nr_cbufs
) {
3662 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3664 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3665 : use_null_fb_surface(batch
, ice
);
3666 push_bt_entry(addr
);
3669 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3670 push_bt_entry(addr
);
3674 bt_assert(texture_start
, info
->num_textures
> 0);
3676 for (int i
= 0; i
< info
->num_textures
; i
++) {
3677 struct iris_sampler_view
*view
= shs
->textures
[i
];
3678 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3679 : use_null_surface(batch
, ice
);
3680 push_bt_entry(addr
);
3683 bt_assert(image_start
, info
->num_images
> 0);
3685 for (int i
= 0; i
< info
->num_images
; i
++) {
3686 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3687 push_bt_entry(addr
);
3690 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3692 bt_assert(ubo_start
, num_ubos
> 0);
3694 for (int i
= 0; i
< num_ubos
; i
++) {
3695 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3696 push_bt_entry(addr
);
3699 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3701 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3702 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3703 * in st_atom_storagebuf.c so it'll compact them into one range, with
3704 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3706 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3707 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3708 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3709 push_bt_entry(addr
);
3714 // XXX: not implemented yet
3715 bt_assert(plane_start
[1], ...);
3716 bt_assert(plane_start
[2], ...);
3721 iris_use_optional_res(struct iris_batch
*batch
,
3722 struct pipe_resource
*res
,
3726 struct iris_bo
*bo
= iris_resource_bo(res
);
3727 iris_use_pinned_bo(batch
, bo
, writeable
);
3731 /* ------------------------------------------------------------------- */
3734 * Pin any BOs which were installed by a previous batch, and restored
3735 * via the hardware logical context mechanism.
3737 * We don't need to re-emit all state every batch - the hardware context
3738 * mechanism will save and restore it for us. This includes pointers to
3739 * various BOs...which won't exist unless we ask the kernel to pin them
3740 * by adding them to the validation list.
3742 * We can skip buffers if we've re-emitted those packets, as we're
3743 * overwriting those stale pointers with new ones, and don't actually
3744 * refer to the old BOs.
3747 iris_restore_render_saved_bos(struct iris_context
*ice
,
3748 struct iris_batch
*batch
,
3749 const struct pipe_draw_info
*draw
)
3751 struct iris_genx_state
*genx
= ice
->state
.genx
;
3753 const uint64_t clean
= ~ice
->state
.dirty
;
3755 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3756 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3759 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3760 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3763 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3764 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3767 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3768 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3771 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3772 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3775 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3776 for (int i
= 0; i
< 4; i
++) {
3777 struct iris_stream_output_target
*tgt
=
3778 (void *) ice
->state
.so_target
[i
];
3780 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3782 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3788 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3789 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3792 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3793 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3798 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3800 for (int i
= 0; i
< 4; i
++) {
3801 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3803 if (range
->length
== 0)
3806 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3807 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3810 iris_use_pinned_bo(batch
, res
->bo
, false);
3812 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3816 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3817 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3818 /* Re-pin any buffers referred to by the binding table. */
3819 iris_populate_binding_table(ice
, batch
, stage
, true);
3823 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3824 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3825 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3827 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3830 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3831 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3832 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3835 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3836 iris_use_pinned_bo(batch
, bo
, false);
3838 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3840 if (prog_data
->total_scratch
> 0) {
3841 struct iris_bo
*bo
=
3842 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
3843 iris_use_pinned_bo(batch
, bo
, true);
3849 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3850 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3852 if (cso_fb
->zsbuf
) {
3853 struct iris_resource
*zres
, *sres
;
3854 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3857 iris_use_pinned_bo(batch
, zres
->bo
,
3858 ice
->state
.depth_writes_enabled
);
3861 iris_use_pinned_bo(batch
, sres
->bo
,
3862 ice
->state
.stencil_writes_enabled
);
3867 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3868 /* This draw didn't emit a new index buffer, so we are inheriting the
3869 * older index buffer. This draw didn't need it, but future ones may.
3871 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3872 iris_use_pinned_bo(batch
, bo
, false);
3875 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3876 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
3878 const int i
= u_bit_scan64(&bound
);
3879 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
3880 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3886 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3887 struct iris_batch
*batch
,
3888 const struct pipe_grid_info
*grid
)
3890 const uint64_t clean
= ~ice
->state
.dirty
;
3892 const int stage
= MESA_SHADER_COMPUTE
;
3893 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3895 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3896 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3899 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3900 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3902 if (range
->length
> 0) {
3903 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3904 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3907 iris_use_pinned_bo(batch
, res
->bo
, false);
3909 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3914 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3915 /* Re-pin any buffers referred to by the binding table. */
3916 iris_populate_binding_table(ice
, batch
, stage
, true);
3919 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3921 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3923 if (clean
& IRIS_DIRTY_CS
) {
3924 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3927 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3928 iris_use_pinned_bo(batch
, bo
, false);
3930 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3932 if (prog_data
->total_scratch
> 0) {
3933 struct iris_bo
*bo
=
3934 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
3935 iris_use_pinned_bo(batch
, bo
, true);
3942 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3945 iris_update_surface_base_address(struct iris_batch
*batch
,
3946 struct iris_binder
*binder
)
3948 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3951 flush_for_state_base_change(batch
);
3953 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3954 sba
.SurfaceStateMOCS
= MOCS_WB
;
3955 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3956 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3959 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3963 iris_upload_dirty_render_state(struct iris_context
*ice
,
3964 struct iris_batch
*batch
,
3965 const struct pipe_draw_info
*draw
)
3967 const uint64_t dirty
= ice
->state
.dirty
;
3969 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3972 struct iris_genx_state
*genx
= ice
->state
.genx
;
3973 struct iris_binder
*binder
= &ice
->state
.binder
;
3974 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3975 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3977 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3978 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3979 uint32_t cc_vp_address
;
3981 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3982 uint32_t *cc_vp_map
=
3983 stream_state(batch
, ice
->state
.dynamic_uploader
,
3984 &ice
->state
.last_res
.cc_vp
,
3985 4 * ice
->state
.num_viewports
*
3986 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3987 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3989 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3990 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3991 if (cso_rast
->depth_clip_near
)
3993 if (cso_rast
->depth_clip_far
)
3996 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3997 ccv
.MinimumDepth
= zmin
;
3998 ccv
.MaximumDepth
= zmax
;
4001 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4004 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4005 ptr
.CCViewportPointer
= cc_vp_address
;
4009 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4010 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4011 uint32_t sf_cl_vp_address
;
4013 stream_state(batch
, ice
->state
.dynamic_uploader
,
4014 &ice
->state
.last_res
.sf_cl_vp
,
4015 4 * ice
->state
.num_viewports
*
4016 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4018 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4019 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4020 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4022 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4023 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4024 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4025 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4027 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4028 state
->scale
[0], state
->scale
[1],
4029 state
->translate
[0], state
->translate
[1],
4030 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4032 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4033 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4034 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4035 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4036 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4037 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4038 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4039 vp
.XMinClipGuardband
= gb_xmin
;
4040 vp
.XMaxClipGuardband
= gb_xmax
;
4041 vp
.YMinClipGuardband
= gb_ymin
;
4042 vp
.YMaxClipGuardband
= gb_ymax
;
4043 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4044 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4045 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4046 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4049 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4052 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4053 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4057 if (dirty
& IRIS_DIRTY_URB
) {
4058 iris_upload_urb_config(ice
, batch
);
4061 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4062 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4063 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4064 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4065 const int header_dwords
= GENX(BLEND_STATE_length
);
4066 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
4067 uint32_t blend_offset
;
4068 uint32_t *blend_map
=
4069 stream_state(batch
, ice
->state
.dynamic_uploader
,
4070 &ice
->state
.last_res
.blend
,
4071 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4073 uint32_t blend_state_header
;
4074 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4075 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4076 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4079 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4080 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4082 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4083 ptr
.BlendStatePointer
= blend_offset
;
4084 ptr
.BlendStatePointerValid
= true;
4088 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4089 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4091 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4095 stream_state(batch
, ice
->state
.dynamic_uploader
,
4096 &ice
->state
.last_res
.color_calc
,
4097 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4099 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4100 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4101 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4102 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4103 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4104 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4105 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4107 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4108 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4111 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4112 ptr
.ColorCalcStatePointer
= cc_offset
;
4113 ptr
.ColorCalcStatePointerValid
= true;
4117 /* Upload constants for TCS passthrough. */
4118 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4119 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4120 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4121 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4124 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4125 * it is in the right layout for TES.
4128 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4129 switch (tes_prog_data
->domain
) {
4130 case BRW_TESS_DOMAIN_QUAD
:
4131 for (int i
= 0; i
< 4; i
++)
4132 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4133 hdr
[3] = ice
->state
.default_inner_level
[0];
4134 hdr
[2] = ice
->state
.default_inner_level
[1];
4136 case BRW_TESS_DOMAIN_TRI
:
4137 for (int i
= 0; i
< 3; i
++)
4138 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4139 hdr
[4] = ice
->state
.default_inner_level
[0];
4141 case BRW_TESS_DOMAIN_ISOLINE
:
4142 hdr
[7] = ice
->state
.default_outer_level
[1];
4143 hdr
[6] = ice
->state
.default_outer_level
[0];
4147 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4148 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4149 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4150 &hdr
[0], &cbuf
->data
.offset
,
4154 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4155 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4158 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4159 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4164 if (shs
->cbuf0_needs_upload
)
4165 upload_uniforms(ice
, stage
);
4167 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4169 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4170 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4172 /* The Skylake PRM contains the following restriction:
4174 * "The driver must ensure The following case does not occur
4175 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4176 * buffer 3 read length equal to zero committed followed by a
4177 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4180 * To avoid this, we program the buffers in the highest slots.
4181 * This way, slot 0 is only used if slot 3 is also used.
4185 for (int i
= 3; i
>= 0; i
--) {
4186 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4188 if (range
->length
== 0)
4191 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4192 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4194 assert(cbuf
->data
.offset
% 32 == 0);
4196 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4197 pkt
.ConstantBody
.Buffer
[n
] =
4198 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4199 : ro_bo(batch
->screen
->workaround_bo
, 0);
4206 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4207 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4208 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4209 ptr
._3DCommandSubOpcode
= 38 + stage
;
4210 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4215 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4216 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4217 iris_populate_binding_table(ice
, batch
, stage
, false);
4221 if (ice
->state
.need_border_colors
)
4222 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4224 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4225 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4226 !ice
->shaders
.prog
[stage
])
4229 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4230 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4232 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4234 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4235 ptr
._3DCommandSubOpcode
= 43 + stage
;
4236 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4240 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4241 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4243 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4244 if (ice
->state
.framebuffer
.samples
> 0)
4245 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4249 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4250 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4251 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4255 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4256 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4259 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4262 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4263 iris_use_pinned_bo(batch
, cache
->bo
, false);
4264 iris_batch_emit(batch
, shader
->derived_data
,
4265 iris_derived_program_state_size(stage
));
4267 if (stage
== MESA_SHADER_TESS_EVAL
) {
4268 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4269 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4270 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4271 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4272 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4277 if (ice
->state
.streamout_active
) {
4278 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4279 iris_batch_emit(batch
, genx
->so_buffers
,
4280 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4281 for (int i
= 0; i
< 4; i
++) {
4282 struct iris_stream_output_target
*tgt
=
4283 (void *) ice
->state
.so_target
[i
];
4285 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4287 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4293 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4294 uint32_t *decl_list
=
4295 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4296 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4299 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4300 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4302 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4303 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4304 sol
.SOFunctionEnable
= true;
4305 sol
.SOStatisticsEnable
= true;
4307 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4308 !ice
->state
.prims_generated_query_active
;
4309 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4312 assert(ice
->state
.streamout
);
4314 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4315 GENX(3DSTATE_STREAMOUT_length
));
4318 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4319 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4323 if (dirty
& IRIS_DIRTY_CLIP
) {
4324 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4325 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4327 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4328 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4329 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4330 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4332 if (wm_prog_data
->barycentric_interp_modes
&
4333 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4334 cl
.NonPerspectiveBarycentricEnable
= true;
4336 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4337 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4339 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4340 ARRAY_SIZE(cso_rast
->clip
));
4343 if (dirty
& IRIS_DIRTY_RASTER
) {
4344 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4345 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4346 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4350 if (dirty
& IRIS_DIRTY_WM
) {
4351 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4352 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4354 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4355 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4357 wm
.BarycentricInterpolationMode
=
4358 wm_prog_data
->barycentric_interp_modes
;
4360 if (wm_prog_data
->early_fragment_tests
)
4361 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4362 else if (wm_prog_data
->has_side_effects
)
4363 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4365 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4368 if (dirty
& IRIS_DIRTY_SBE
) {
4369 iris_emit_sbe(batch
, ice
);
4372 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4373 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4374 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4375 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4376 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4377 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4378 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4381 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4382 ARRAY_SIZE(cso_blend
->ps_blend
));
4385 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4386 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4388 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4389 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4390 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4391 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4392 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4394 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4396 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4400 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4401 uint32_t scissor_offset
=
4402 emit_state(batch
, ice
->state
.dynamic_uploader
,
4403 &ice
->state
.last_res
.scissor
,
4404 ice
->state
.scissors
,
4405 sizeof(struct pipe_scissor_state
) *
4406 ice
->state
.num_viewports
, 32);
4408 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4409 ptr
.ScissorRectPointer
= scissor_offset
;
4413 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4414 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4415 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4417 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4419 if (cso_fb
->zsbuf
) {
4420 struct iris_resource
*zres
, *sres
;
4421 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4424 iris_use_pinned_bo(batch
, zres
->bo
,
4425 ice
->state
.depth_writes_enabled
);
4429 iris_use_pinned_bo(batch
, sres
->bo
,
4430 ice
->state
.stencil_writes_enabled
);
4435 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4436 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4437 for (int i
= 0; i
< 32; i
++) {
4438 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4443 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4444 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4445 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4448 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4449 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4450 topo
.PrimitiveTopologyType
=
4451 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4455 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4456 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4459 /* The VF cache designers cut corners, and made the cache key's
4460 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4461 * 32 bits of the address. If you have two vertex buffers which get
4462 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4463 * you can get collisions (even within a single batch).
4465 * So, we need to do a VF cache invalidate if the buffer for a VB
4466 * slot slot changes [48:32] address bits from the previous time.
4468 unsigned flush_flags
= 0;
4470 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4472 const int i
= u_bit_scan64(&bound
);
4473 uint16_t high_bits
= 0;
4475 struct iris_resource
*res
=
4476 (void *) genx
->vertex_buffers
[i
].resource
;
4478 iris_use_pinned_bo(batch
, res
->bo
, false);
4480 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4481 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4482 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4483 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4486 /* If the buffer was written to by streamout, we may need
4487 * to stall so those writes land and become visible to the
4490 * TODO: This may stall more than necessary.
4492 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4493 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4498 iris_emit_pipe_control_flush(batch
, flush_flags
);
4500 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4503 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
4504 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
4505 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
4509 bound
= ice
->state
.bound_vertex_buffers
;
4511 const int i
= u_bit_scan64(&bound
);
4512 memcpy(map
, genx
->vertex_buffers
[i
].state
,
4513 sizeof(uint32_t) * vb_dwords
);
4519 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4520 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4521 const unsigned entries
= MAX2(cso
->count
, 1);
4522 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4523 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4524 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4525 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4528 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4529 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4530 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4531 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4533 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4534 if (vs_prog_data
->uses_vertexid
) {
4535 sgv
.VertexIDEnable
= true;
4536 sgv
.VertexIDComponentNumber
= 2;
4537 sgv
.VertexIDElementOffset
= cso
->count
;
4540 if (vs_prog_data
->uses_instanceid
) {
4541 sgv
.InstanceIDEnable
= true;
4542 sgv
.InstanceIDComponentNumber
= 3;
4543 sgv
.InstanceIDElementOffset
= cso
->count
;
4548 if (dirty
& IRIS_DIRTY_VF
) {
4549 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4550 if (draw
->primitive_restart
) {
4551 vf
.IndexedDrawCutIndexEnable
= true;
4552 vf
.CutIndex
= draw
->restart_index
;
4557 // XXX: Gen8 - PMA fix
4561 iris_upload_render_state(struct iris_context
*ice
,
4562 struct iris_batch
*batch
,
4563 const struct pipe_draw_info
*draw
)
4565 /* Always pin the binder. If we're emitting new binding table pointers,
4566 * we need it. If not, we're probably inheriting old tables via the
4567 * context, and need it anyway. Since true zero-bindings cases are
4568 * practically non-existent, just pin it and avoid last_res tracking.
4570 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4572 if (!batch
->contains_draw
) {
4573 iris_restore_render_saved_bos(ice
, batch
, draw
);
4574 batch
->contains_draw
= true;
4577 iris_upload_dirty_render_state(ice
, batch
, draw
);
4579 if (draw
->index_size
> 0) {
4582 if (draw
->has_user_indices
) {
4583 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4584 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4585 &offset
, &ice
->state
.last_res
.index_buffer
);
4587 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4588 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4590 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4591 draw
->index
.resource
);
4595 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4597 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4598 ib
.IndexFormat
= draw
->index_size
>> 1;
4600 ib
.BufferSize
= bo
->size
;
4601 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4604 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4605 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4606 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4607 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4608 ice
->state
.last_index_bo_high_bits
= high_bits
;
4612 #define _3DPRIM_END_OFFSET 0x2420
4613 #define _3DPRIM_START_VERTEX 0x2430
4614 #define _3DPRIM_VERTEX_COUNT 0x2434
4615 #define _3DPRIM_INSTANCE_COUNT 0x2438
4616 #define _3DPRIM_START_INSTANCE 0x243C
4617 #define _3DPRIM_BASE_VERTEX 0x2440
4619 if (draw
->indirect
) {
4620 /* We don't support this MultidrawIndirect. */
4621 assert(!draw
->indirect
->indirect_draw_count
);
4623 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4626 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4627 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4628 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4630 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4631 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4632 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4634 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4635 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4636 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4638 if (draw
->index_size
) {
4639 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4640 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4641 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4643 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4644 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4645 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4648 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4649 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4650 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4652 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4653 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4657 } else if (draw
->count_from_stream_output
) {
4658 struct iris_stream_output_target
*so
=
4659 (void *) draw
->count_from_stream_output
;
4661 // XXX: avoid if possible
4662 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4664 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4665 lrm
.RegisterAddress
= CS_GPR(0);
4667 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
4669 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
4670 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
4672 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
4673 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
4674 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
4675 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
4678 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4679 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4680 prim
.PredicateEnable
=
4681 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4683 if (draw
->indirect
|| draw
->count_from_stream_output
) {
4684 prim
.IndirectParameterEnable
= true;
4686 prim
.StartInstanceLocation
= draw
->start_instance
;
4687 prim
.InstanceCount
= draw
->instance_count
;
4688 prim
.VertexCountPerInstance
= draw
->count
;
4690 // XXX: this is probably bonkers.
4691 prim
.StartVertexLocation
= draw
->start
;
4693 if (draw
->index_size
) {
4694 prim
.BaseVertexLocation
+= draw
->index_bias
;
4696 prim
.StartVertexLocation
+= draw
->index_bias
;
4699 //prim.BaseVertexLocation = ...;
4705 iris_upload_compute_state(struct iris_context
*ice
,
4706 struct iris_batch
*batch
,
4707 const struct pipe_grid_info
*grid
)
4709 const uint64_t dirty
= ice
->state
.dirty
;
4710 struct iris_screen
*screen
= batch
->screen
;
4711 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4712 struct iris_binder
*binder
= &ice
->state
.binder
;
4713 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4714 struct iris_compiled_shader
*shader
=
4715 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4716 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4717 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4719 /* Always pin the binder. If we're emitting new binding table pointers,
4720 * we need it. If not, we're probably inheriting old tables via the
4721 * context, and need it anyway. Since true zero-bindings cases are
4722 * practically non-existent, just pin it and avoid last_res tracking.
4724 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4726 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4727 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4729 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4730 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4732 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4733 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4735 if (ice
->state
.need_border_colors
)
4736 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4738 if (dirty
& IRIS_DIRTY_CS
) {
4739 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4741 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4742 * the only bits that are changed are scoreboard related: Scoreboard
4743 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4744 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4747 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4749 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4750 if (prog_data
->total_scratch
) {
4751 struct iris_bo
*bo
=
4752 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4753 MESA_SHADER_COMPUTE
);
4754 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4755 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
4758 vfe
.MaximumNumberofThreads
=
4759 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4761 vfe
.ResetGatewayTimer
=
4762 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4765 vfe
.BypassGatewayControl
= true;
4767 vfe
.NumberofURBEntries
= 2;
4768 vfe
.URBEntryAllocationSize
= 2;
4770 // XXX: Use Indirect Payload Storage?
4771 vfe
.CURBEAllocationSize
=
4772 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4773 cs_prog_data
->push
.cross_thread
.regs
, 2);
4777 // XXX: hack iris_set_constant_buffers to upload these thread counts
4778 // XXX: along with regular uniforms for compute shaders, somehow.
4780 uint32_t curbe_data_offset
= 0;
4781 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4782 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4783 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4784 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4785 struct pipe_resource
*curbe_data_res
= NULL
;
4786 uint32_t *curbe_data_map
=
4787 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4788 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4789 &curbe_data_offset
);
4790 assert(curbe_data_map
);
4791 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4792 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4794 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4795 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4796 curbe
.CURBETotalDataLength
=
4797 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4798 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4802 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4803 IRIS_DIRTY_BINDINGS_CS
|
4804 IRIS_DIRTY_CONSTANTS_CS
|
4806 struct pipe_resource
*desc_res
= NULL
;
4807 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4809 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4810 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4811 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4814 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4815 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4817 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4818 load
.InterfaceDescriptorTotalLength
=
4819 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4820 load
.InterfaceDescriptorDataStartAddress
=
4821 emit_state(batch
, ice
->state
.dynamic_uploader
,
4822 &desc_res
, desc
, sizeof(desc
), 32);
4825 pipe_resource_reference(&desc_res
, NULL
);
4828 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4829 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4830 uint32_t right_mask
;
4833 right_mask
= ~0u >> (32 - remainder
);
4835 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4837 #define GPGPU_DISPATCHDIMX 0x2500
4838 #define GPGPU_DISPATCHDIMY 0x2504
4839 #define GPGPU_DISPATCHDIMZ 0x2508
4841 if (grid
->indirect
) {
4842 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4843 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4844 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4845 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4846 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4848 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4849 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4850 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4852 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4853 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4854 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4858 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4859 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4860 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4861 ggw
.ThreadDepthCounterMaximum
= 0;
4862 ggw
.ThreadHeightCounterMaximum
= 0;
4863 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4864 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4865 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4866 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4867 ggw
.RightExecutionMask
= right_mask
;
4868 ggw
.BottomExecutionMask
= 0xffffffff;
4871 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4873 if (!batch
->contains_draw
) {
4874 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4875 batch
->contains_draw
= true;
4880 * State module teardown.
4883 iris_destroy_state(struct iris_context
*ice
)
4885 struct iris_genx_state
*genx
= ice
->state
.genx
;
4887 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
4889 const int i
= u_bit_scan64(&bound_vbs
);
4890 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
4893 // XXX: unreference resources/surfaces.
4894 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4895 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4897 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4899 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4900 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4901 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4903 free(ice
->state
.genx
);
4905 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
4907 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4908 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4909 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4910 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4911 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4912 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4915 /* ------------------------------------------------------------------- */
4918 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
4921 _iris_emit_lrr(batch
, dst
, src
);
4925 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
4928 _iris_emit_lrr(batch
, dst
, src
);
4929 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
4933 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4936 _iris_emit_lri(batch
, reg
, val
);
4940 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4943 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4944 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4948 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4951 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4952 struct iris_bo
*bo
, uint32_t offset
)
4954 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4955 lrm
.RegisterAddress
= reg
;
4956 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4961 * Load a 64-bit value from a buffer into a MMIO register via
4962 * two MI_LOAD_REGISTER_MEM commands.
4965 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4966 struct iris_bo
*bo
, uint32_t offset
)
4968 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4969 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4973 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4974 struct iris_bo
*bo
, uint32_t offset
,
4977 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4978 srm
.RegisterAddress
= reg
;
4979 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4980 srm
.PredicateEnable
= predicated
;
4985 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4986 struct iris_bo
*bo
, uint32_t offset
,
4989 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4990 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4994 iris_store_data_imm32(struct iris_batch
*batch
,
4995 struct iris_bo
*bo
, uint32_t offset
,
4998 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4999 sdi
.Address
= rw_bo(bo
, offset
);
5000 sdi
.ImmediateData
= imm
;
5005 iris_store_data_imm64(struct iris_batch
*batch
,
5006 struct iris_bo
*bo
, uint32_t offset
,
5009 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5010 * 2 in genxml but it's actually variable length and we need 5 DWords.
5012 void *map
= iris_get_command_space(batch
, 4 * 5);
5013 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5014 sdi
.DWordLength
= 5 - 2;
5015 sdi
.Address
= rw_bo(bo
, offset
);
5016 sdi
.ImmediateData
= imm
;
5021 iris_copy_mem_mem(struct iris_batch
*batch
,
5022 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5023 struct iris_bo
*src_bo
, uint32_t src_offset
,
5026 /* MI_COPY_MEM_MEM operates on DWords. */
5027 assert(bytes
% 4 == 0);
5028 assert(dst_offset
% 4 == 0);
5029 assert(src_offset
% 4 == 0);
5031 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5032 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5033 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5034 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5039 /* ------------------------------------------------------------------- */
5042 flags_to_post_sync_op(uint32_t flags
)
5044 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5045 return WriteImmediateData
;
5047 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5048 return WritePSDepthCount
;
5050 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5051 return WriteTimestamp
;
5057 * Do the given flags have a Post Sync or LRI Post Sync operation?
5059 static enum pipe_control_flags
5060 get_post_sync_flags(enum pipe_control_flags flags
)
5062 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5063 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5064 PIPE_CONTROL_WRITE_TIMESTAMP
|
5065 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5067 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5068 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5070 assert(util_bitcount(flags
) <= 1);
5075 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5078 * Emit a series of PIPE_CONTROL commands, taking into account any
5079 * workarounds necessary to actually accomplish the caller's request.
5081 * Unless otherwise noted, spec quotations in this function come from:
5083 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5084 * Restrictions for PIPE_CONTROL.
5086 * You should not use this function directly. Use the helpers in
5087 * iris_pipe_control.c instead, which may split the pipe control further.
5090 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5091 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5093 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5094 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5095 enum pipe_control_flags non_lri_post_sync_flags
=
5096 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5098 /* Recursive PIPE_CONTROL workarounds --------------------------------
5099 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5101 * We do these first because we want to look at the original operation,
5102 * rather than any workarounds we set.
5104 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5105 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5106 * lists several workarounds:
5108 * "Project: SKL, KBL, BXT
5110 * If the VF Cache Invalidation Enable is set to a 1 in a
5111 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5112 * sets to 0, with the VF Cache Invalidation Enable set to 0
5113 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5114 * Invalidation Enable set to a 1."
5116 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5119 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5120 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5122 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5123 * programmed prior to programming a PIPECONTROL command with "LRI
5124 * Post Sync Operation" in GPGPU mode of operation (i.e when
5125 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5127 * The same text exists a few rows below for Post Sync Op.
5129 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5132 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5134 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5135 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5136 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5138 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5142 /* "Flush Types" workarounds ---------------------------------------------
5143 * We do these now because they may add post-sync operations or CS stalls.
5146 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5147 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5149 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5150 * 'Write PS Depth Count' or 'Write Timestamp'."
5153 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5154 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5155 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5156 bo
= batch
->screen
->workaround_bo
;
5160 /* #1130 from Gen10 workarounds page:
5162 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5163 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5164 * board stall if Render target cache flush is enabled."
5166 * Applicable to CNL B0 and C0 steppings only.
5168 * The wording here is unclear, and this workaround doesn't look anything
5169 * like the internal bug report recommendations, but leave it be for now...
5171 if (GEN_GEN
== 10) {
5172 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5173 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5174 } else if (flags
& non_lri_post_sync_flags
) {
5175 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5179 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5180 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5182 * "This bit must be DISABLED for operations other than writing
5185 * This seems like nonsense. An Ivybridge workaround requires us to
5186 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5187 * operation. Gen8+ requires us to emit depth stalls and depth cache
5188 * flushes together. So, it's hard to imagine this means anything other
5189 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5191 * We ignore the supposed restriction and do nothing.
5195 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5196 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5197 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5199 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5200 * PS_DEPTH_COUNT or TIMESTAMP queries."
5202 * TODO: Implement end-of-pipe checking.
5204 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5205 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5208 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5209 /* From the PIPE_CONTROL instruction table, bit 1:
5211 * "This bit is ignored if Depth Stall Enable is set.
5212 * Further, the render cache is not flushed even if Write Cache
5213 * Flush Enable bit is set."
5215 * We assert that the caller doesn't do this combination, to try and
5216 * prevent mistakes. It shouldn't hurt the GPU, though.
5218 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5219 * and "Render Target Flush" combo is explicitly required for BTI
5220 * update workarounds.
5222 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5223 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5226 /* PIPE_CONTROL page workarounds ------------------------------------- */
5228 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5229 /* From the PIPE_CONTROL page itself:
5232 * Restriction: Pipe_control with CS-stall bit set must be issued
5233 * before a pipe-control command that has the State Cache
5234 * Invalidate bit set."
5236 flags
|= PIPE_CONTROL_CS_STALL
;
5239 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5240 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5243 * SW must always program Post-Sync Operation to "Write Immediate
5244 * Data" when Flush LLC is set."
5246 * For now, we just require the caller to do it.
5248 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5251 /* "Post-Sync Operation" workarounds -------------------------------- */
5253 /* Project: All / Argument: Global Snapshot Count Reset [19]
5255 * "This bit must not be exercised on any product.
5256 * Requires stall bit ([20] of DW1) set."
5258 * We don't use this, so we just assert that it isn't used. The
5259 * PIPE_CONTROL instruction page indicates that they intended this
5260 * as a debug feature and don't think it is useful in production,
5261 * but it may actually be usable, should we ever want to.
5263 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5265 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5266 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5267 /* Project: All / Arguments:
5269 * - Generic Media State Clear [16]
5270 * - Indirect State Pointers Disable [16]
5272 * "Requires stall bit ([20] of DW1) set."
5274 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5275 * State Clear) says:
5277 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5278 * programmed prior to programming a PIPECONTROL command with "Media
5279 * State Clear" set in GPGPU mode of operation"
5281 * This is a subset of the earlier rule, so there's nothing to do.
5283 flags
|= PIPE_CONTROL_CS_STALL
;
5286 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5287 /* Project: All / Argument: Store Data Index
5289 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5292 * For now, we just assert that the caller does this. We might want to
5293 * automatically add a write to the workaround BO...
5295 assert(non_lri_post_sync_flags
!= 0);
5298 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5299 /* Project: All / Argument: Sync GFDT
5301 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5302 * than '0' or 0x2520[13] must be set."
5304 * For now, we just assert that the caller does this.
5306 assert(non_lri_post_sync_flags
!= 0);
5309 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5310 /* Project: IVB+ / Argument: TLB inv
5312 * "Requires stall bit ([20] of DW1) set."
5314 * Also, from the PIPE_CONTROL instruction table:
5317 * Post Sync Operation or CS stall must be set to ensure a TLB
5318 * invalidation occurs. Otherwise no cycle will occur to the TLB
5319 * cache to invalidate."
5321 * This is not a subset of the earlier rule, so there's nothing to do.
5323 flags
|= PIPE_CONTROL_CS_STALL
;
5326 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5327 /* TODO: The big Skylake GT4 post sync op workaround */
5330 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5332 if (IS_COMPUTE_PIPELINE(batch
)) {
5333 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5334 /* Project: SKL+ / Argument: Tex Invalidate
5335 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5337 flags
|= PIPE_CONTROL_CS_STALL
;
5340 if (GEN_GEN
== 8 && (post_sync_flags
||
5341 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5342 PIPE_CONTROL_DEPTH_STALL
|
5343 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5344 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5345 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5346 /* Project: BDW / Arguments:
5348 * - LRI Post Sync Operation [23]
5349 * - Post Sync Op [15:14]
5351 * - Depth Stall [13]
5352 * - Render Target Cache Flush [12]
5353 * - Depth Cache Flush [0]
5354 * - DC Flush Enable [5]
5356 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5359 flags
|= PIPE_CONTROL_CS_STALL
;
5361 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5364 * This bit must be always set when PIPE_CONTROL command is
5365 * programmed by GPGPU and MEDIA workloads, except for the cases
5366 * when only Read Only Cache Invalidation bits are set (State
5367 * Cache Invalidation Enable, Instruction cache Invalidation
5368 * Enable, Texture Cache Invalidation Enable, Constant Cache
5369 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5370 * need not implemented when FF_DOP_CG is disable via "Fixed
5371 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5373 * It sounds like we could avoid CS stalls in some cases, but we
5374 * don't currently bother. This list isn't exactly the list above,
5380 /* "Stall" workarounds ----------------------------------------------
5381 * These have to come after the earlier ones because we may have added
5382 * some additional CS stalls above.
5385 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5386 /* Project: PRE-SKL, VLV, CHV
5388 * "[All Stepping][All SKUs]:
5390 * One of the following must also be set:
5392 * - Render Target Cache Flush Enable ([12] of DW1)
5393 * - Depth Cache Flush Enable ([0] of DW1)
5394 * - Stall at Pixel Scoreboard ([1] of DW1)
5395 * - Depth Stall ([13] of DW1)
5396 * - Post-Sync Operation ([13] of DW1)
5397 * - DC Flush Enable ([5] of DW1)"
5399 * If we don't already have one of those bits set, we choose to add
5400 * "Stall at Pixel Scoreboard". Some of the other bits require a
5401 * CS stall as a workaround (see above), which would send us into
5402 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5403 * appears to be safe, so we choose that.
5405 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5406 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5407 PIPE_CONTROL_WRITE_IMMEDIATE
|
5408 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5409 PIPE_CONTROL_WRITE_TIMESTAMP
|
5410 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5411 PIPE_CONTROL_DEPTH_STALL
|
5412 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5413 if (!(flags
& wa_bits
))
5414 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5417 /* Emit --------------------------------------------------------------- */
5419 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5420 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5421 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5422 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5423 pc
.StoreDataIndex
= 0;
5424 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5425 pc
.GlobalSnapshotCountReset
=
5426 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5427 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5428 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5429 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5430 pc
.RenderTargetCacheFlushEnable
=
5431 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5432 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5433 pc
.StateCacheInvalidationEnable
=
5434 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5435 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5436 pc
.ConstantCacheInvalidationEnable
=
5437 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5438 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5439 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5440 pc
.InstructionCacheInvalidateEnable
=
5441 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5442 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5443 pc
.IndirectStatePointersDisable
=
5444 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5445 pc
.TextureCacheInvalidationEnable
=
5446 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5447 pc
.Address
= rw_bo(bo
, offset
);
5448 pc
.ImmediateData
= imm
;
5453 genX(init_state
)(struct iris_context
*ice
)
5455 struct pipe_context
*ctx
= &ice
->ctx
;
5456 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5458 ctx
->create_blend_state
= iris_create_blend_state
;
5459 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5460 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5461 ctx
->create_sampler_state
= iris_create_sampler_state
;
5462 ctx
->create_sampler_view
= iris_create_sampler_view
;
5463 ctx
->create_surface
= iris_create_surface
;
5464 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5465 ctx
->bind_blend_state
= iris_bind_blend_state
;
5466 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5467 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5468 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5469 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5470 ctx
->delete_blend_state
= iris_delete_state
;
5471 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5472 ctx
->delete_rasterizer_state
= iris_delete_state
;
5473 ctx
->delete_sampler_state
= iris_delete_state
;
5474 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5475 ctx
->set_blend_color
= iris_set_blend_color
;
5476 ctx
->set_clip_state
= iris_set_clip_state
;
5477 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5478 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5479 ctx
->set_shader_images
= iris_set_shader_images
;
5480 ctx
->set_sampler_views
= iris_set_sampler_views
;
5481 ctx
->set_tess_state
= iris_set_tess_state
;
5482 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5483 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5484 ctx
->set_sample_mask
= iris_set_sample_mask
;
5485 ctx
->set_scissor_states
= iris_set_scissor_states
;
5486 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5487 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5488 ctx
->set_viewport_states
= iris_set_viewport_states
;
5489 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5490 ctx
->surface_destroy
= iris_surface_destroy
;
5491 ctx
->draw_vbo
= iris_draw_vbo
;
5492 ctx
->launch_grid
= iris_launch_grid
;
5493 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5494 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5495 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5497 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5498 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5499 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5500 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5501 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5502 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5503 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5504 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5505 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5506 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5507 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5508 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5509 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5510 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5511 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5512 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5513 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5514 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5515 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5516 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5517 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5518 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5519 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5520 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5521 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5522 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5523 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5525 ice
->state
.dirty
= ~0ull;
5527 ice
->state
.statistics_counters_enabled
= true;
5529 ice
->state
.sample_mask
= 0xffff;
5530 ice
->state
.num_viewports
= 1;
5531 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5533 /* Make a 1x1x1 null surface for unbound textures */
5534 void *null_surf_map
=
5535 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5536 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5537 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5538 ice
->state
.unbound_tex
.offset
+=
5539 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5541 /* Default all scissor rectangles to be empty regions. */
5542 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5543 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5544 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,