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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #include "iris_genx_macros.h"
110 #include "intel/common/gen_guardband.h"
113 #define MOCS_PTE 0x18
116 #define MOCS_PTE (1 << 1)
117 #define MOCS_WB (2 << 1)
121 mocs(const struct iris_bo
*bo
)
123 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
127 * Statically assert that PIPE_* enums match the hardware packets.
128 * (As long as they match, we don't need to translate them.)
130 UNUSED
static void pipe_asserts()
132 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
134 /* pipe_logicop happens to match the hardware. */
135 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
136 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
137 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
138 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
139 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
140 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
141 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
142 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
143 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
144 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
145 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
146 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
147 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
148 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
149 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
150 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
152 /* pipe_blend_func happens to match the hardware. */
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
173 /* pipe_blend_func happens to match the hardware. */
174 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
175 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
176 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
177 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
178 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
180 /* pipe_stencil_op happens to match the hardware. */
181 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
182 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
183 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
184 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
185 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
186 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
187 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
188 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
190 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
191 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
192 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
197 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
199 static const unsigned map
[] = {
200 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
201 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
202 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
203 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
204 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
205 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
206 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
207 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
208 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
209 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
210 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
211 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
212 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
213 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
214 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
217 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
221 translate_compare_func(enum pipe_compare_func pipe_func
)
223 static const unsigned map
[] = {
224 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
225 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
226 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
227 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
228 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
229 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
230 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
231 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
233 return map
[pipe_func
];
237 translate_shadow_func(enum pipe_compare_func pipe_func
)
239 /* Gallium specifies the result of shadow comparisons as:
241 * 1 if ref <op> texel,
246 * 0 if texel <op> ref,
249 * So we need to flip the operator and also negate.
251 static const unsigned map
[] = {
252 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
253 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
254 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
255 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
256 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
257 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
258 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
259 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
261 return map
[pipe_func
];
265 translate_cull_mode(unsigned pipe_face
)
267 static const unsigned map
[4] = {
268 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
269 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
270 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
271 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
273 return map
[pipe_face
];
277 translate_fill_mode(unsigned pipe_polymode
)
279 static const unsigned map
[4] = {
280 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
281 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
282 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
283 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
285 return map
[pipe_polymode
];
289 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
291 static const unsigned map
[] = {
292 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
293 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
294 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
296 return map
[pipe_mip
];
300 translate_wrap(unsigned pipe_wrap
)
302 static const unsigned map
[] = {
303 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
304 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
305 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
306 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
307 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
308 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
310 /* These are unsupported. */
311 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
312 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
314 return map
[pipe_wrap
];
318 * Allocate space for some indirect state.
320 * Return a pointer to the map (to fill it out) and a state ref (for
321 * referring to the state in GPU commands).
324 upload_state(struct u_upload_mgr
*uploader
,
325 struct iris_state_ref
*ref
,
330 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
335 * Stream out temporary/short-lived state.
337 * This allocates space, pins the BO, and includes the BO address in the
338 * returned offset (which works because all state lives in 32-bit memory
342 stream_state(struct iris_batch
*batch
,
343 struct u_upload_mgr
*uploader
,
344 struct pipe_resource
**out_res
,
347 uint32_t *out_offset
)
351 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
353 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
354 iris_use_pinned_bo(batch
, bo
, false);
356 *out_offset
+= iris_bo_offset_from_base_address(bo
);
358 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
364 * stream_state() + memcpy.
367 emit_state(struct iris_batch
*batch
,
368 struct u_upload_mgr
*uploader
,
369 struct pipe_resource
**out_res
,
376 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
379 memcpy(map
, data
, size
);
385 * Did field 'x' change between 'old_cso' and 'new_cso'?
387 * (If so, we may want to set some dirty flags.)
389 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
390 #define cso_changed_memcmp(x) \
391 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
394 flush_for_state_base_change(struct iris_batch
*batch
)
396 /* Flush before emitting STATE_BASE_ADDRESS.
398 * This isn't documented anywhere in the PRM. However, it seems to be
399 * necessary prior to changing the surface state base adress. We've
400 * seen issues in Vulkan where we get GPU hangs when using multi-level
401 * command buffers which clear depth, reset state base address, and then
404 * Normally, in GL, we would trust the kernel to do sufficient stalls
405 * and flushes prior to executing our batch. However, it doesn't seem
406 * as if the kernel's flushing is always sufficient and we don't want to
409 * We make this an end-of-pipe sync instead of a normal flush because we
410 * do not know the current status of the GPU. On Haswell at least,
411 * having a fast-clear operation in flight at the same time as a normal
412 * rendering operation can cause hangs. Since the kernel's flushing is
413 * insufficient, we need to ensure that any rendering operations from
414 * other processes are definitely complete before we try to do our own
415 * rendering. It's a bit of a big hammer but it appears to work.
417 iris_emit_end_of_pipe_sync(batch
,
418 "change STATE_BASE_ADDRESS",
419 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
420 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
421 PIPE_CONTROL_DATA_CACHE_FLUSH
);
425 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
427 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
428 lri
.RegisterOffset
= reg
;
432 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
435 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
437 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
438 lrr
.SourceRegisterAddress
= src
;
439 lrr
.DestinationRegisterAddress
= dst
;
444 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
446 #if GEN_GEN >= 8 && GEN_GEN < 10
447 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
449 * Software must clear the COLOR_CALC_STATE Valid field in
450 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
451 * with Pipeline Select set to GPGPU.
453 * The internal hardware docs recommend the same workaround for Gen9
456 if (pipeline
== GPGPU
)
457 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
461 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
462 * PIPELINE_SELECT [DevBWR+]":
466 * Software must ensure all the write caches are flushed through a
467 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
468 * command to invalidate read only caches prior to programming
469 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
471 iris_emit_pipe_control_flush(batch
,
472 "workaround: PIPELINE_SELECT flushes (1/2)",
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
|
476 PIPE_CONTROL_CS_STALL
);
478 iris_emit_pipe_control_flush(batch
,
479 "workaround: PIPELINE_SELECT flushes (2/2)",
480 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
481 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
482 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
483 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
485 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
489 sel
.PipelineSelection
= pipeline
;
494 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
499 * "This chicken bit works around a hardware issue with barrier
500 * logic encountered when switching between GPGPU and 3D pipelines.
501 * To workaround the issue, this mode bit should be set after a
502 * pipeline is selected."
505 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
506 reg
.GLKBarrierMode
= value
;
507 reg
.GLKBarrierModeMask
= 1;
509 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
514 init_state_base_address(struct iris_batch
*batch
)
516 flush_for_state_base_change(batch
);
518 /* We program most base addresses once at context initialization time.
519 * Each base address points at a 4GB memory zone, and never needs to
520 * change. See iris_bufmgr.h for a description of the memory zones.
522 * The one exception is Surface State Base Address, which needs to be
523 * updated occasionally. See iris_binder.c for the details there.
525 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
526 sba
.GeneralStateMOCS
= MOCS_WB
;
527 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
528 sba
.DynamicStateMOCS
= MOCS_WB
;
529 sba
.IndirectObjectMOCS
= MOCS_WB
;
530 sba
.InstructionMOCS
= MOCS_WB
;
531 sba
.SurfaceStateMOCS
= MOCS_WB
;
533 sba
.GeneralStateBaseAddressModifyEnable
= true;
534 sba
.DynamicStateBaseAddressModifyEnable
= true;
535 sba
.IndirectObjectBaseAddressModifyEnable
= true;
536 sba
.InstructionBaseAddressModifyEnable
= true;
537 sba
.GeneralStateBufferSizeModifyEnable
= true;
538 sba
.DynamicStateBufferSizeModifyEnable
= true;
540 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
541 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
543 sba
.IndirectObjectBufferSizeModifyEnable
= true;
544 sba
.InstructionBuffersizeModifyEnable
= true;
546 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
547 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
549 sba
.GeneralStateBufferSize
= 0xfffff;
550 sba
.IndirectObjectBufferSize
= 0xfffff;
551 sba
.InstructionBufferSize
= 0xfffff;
552 sba
.DynamicStateBufferSize
= 0xfffff;
557 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
558 bool has_slm
, bool wants_dc_cache
)
561 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
562 reg
.SLMEnable
= has_slm
;
564 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
565 * in L3CNTLREG register. The default setting of the bit is not the
566 * desirable behavior.
568 reg
.ErrorDetectionBehaviorControl
= true;
569 reg
.UseFullWays
= true;
571 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
572 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
573 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
574 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
576 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
580 iris_emit_default_l3_config(struct iris_batch
*batch
,
581 const struct gen_device_info
*devinfo
,
584 bool wants_dc_cache
= true;
585 bool has_slm
= compute
;
586 const struct gen_l3_weights w
=
587 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
588 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
589 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
592 #if GEN_GEN == 9 || GEN_GEN == 10
594 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
598 /* A fixed function pipe flush is required before modifying this field */
599 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
600 : "disable preemption",
601 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
603 /* enable object level preemption */
604 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
605 reg
.ReplayMode
= enable
;
606 reg
.ReplayModeMask
= true;
608 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
614 iris_upload_slice_hashing_state(struct iris_batch
*batch
)
616 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
617 int subslices_delta
=
618 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
619 if (subslices_delta
== 0)
622 struct iris_context
*ice
= NULL
;
623 ice
= container_of(batch
, ice
, batches
[IRIS_BATCH_RENDER
]);
624 assert(&ice
->batches
[IRIS_BATCH_RENDER
] == batch
);
626 unsigned size
= GENX(SLICE_HASH_TABLE_length
) * 4;
627 uint32_t hash_address
;
628 struct pipe_resource
*tmp
= NULL
;
630 stream_state(batch
, ice
->state
.dynamic_uploader
, &tmp
,
631 size
, 64, &hash_address
);
632 pipe_resource_reference(&tmp
, NULL
);
634 struct GENX(SLICE_HASH_TABLE
) table0
= {
636 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
637 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
638 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
639 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
640 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
641 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
642 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
643 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
644 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
645 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
646 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
647 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
648 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
649 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
650 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
651 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
655 struct GENX(SLICE_HASH_TABLE
) table1
= {
657 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
658 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
659 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
660 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
661 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
662 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
663 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
664 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
665 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
666 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
667 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
668 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
669 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
670 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
671 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
672 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
676 const struct GENX(SLICE_HASH_TABLE
) *table
=
677 subslices_delta
< 0 ? &table0
: &table1
;
678 GENX(SLICE_HASH_TABLE_pack
)(NULL
, map
, table
);
680 iris_emit_cmd(batch
, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS
), ptr
) {
681 ptr
.SliceHashStatePointerValid
= true;
682 ptr
.SliceHashTableStatePointer
= hash_address
;
685 iris_emit_cmd(batch
, GENX(3DSTATE_3D_MODE
), mode
) {
686 mode
.SliceHashingTableEnable
= true;
692 * Upload the initial GPU state for a render context.
694 * This sets some invariant state that needs to be programmed a particular
695 * way, but we never actually change.
698 iris_init_render_context(struct iris_screen
*screen
,
699 struct iris_batch
*batch
,
700 struct iris_vtable
*vtbl
,
701 struct pipe_debug_callback
*dbg
)
703 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
706 emit_pipeline_select(batch
, _3D
);
708 iris_emit_default_l3_config(batch
, devinfo
, false);
710 init_state_base_address(batch
);
713 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
714 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
715 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
717 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
719 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
720 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
721 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
723 iris_emit_lri(batch
, INSTPM
, reg_val
);
727 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
728 reg
.FloatBlendOptimizationEnable
= true;
729 reg
.FloatBlendOptimizationEnableMask
= true;
730 reg
.PartialResolveDisableInVC
= true;
731 reg
.PartialResolveDisableInVCMask
= true;
733 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
735 if (devinfo
->is_geminilake
)
736 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
740 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
741 reg
.HeaderlessMessageforPreemptableContexts
= 1;
742 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
744 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
746 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
747 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
748 reg
.EnabledTexelOffsetPrecisionFix
= 1;
749 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
751 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
753 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
754 reg
.StateCacheRedirectToCSSectionEnable
= true;
755 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
757 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
759 /* Hardware specification recommends disabling repacking for the
760 * compatibility with decompression mechanism in display controller.
762 if (devinfo
->disable_ccs_repack
) {
763 iris_pack_state(GENX(CACHE_MODE_0
), ®_val
, reg
) {
764 reg
.DisableRepackingforCompression
= true;
765 reg
.DisableRepackingforCompressionMask
= true;
767 iris_emit_lri(batch
, CACHE_MODE_0
, reg_val
);
770 iris_upload_slice_hashing_state(batch
);
773 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
774 * changing it dynamically. We set it to the maximum size here, and
775 * instead include the render target dimensions in the viewport, so
776 * viewport extents clipping takes care of pruning stray geometry.
778 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
779 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
780 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
783 /* Set the initial MSAA sample positions. */
784 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
785 GEN_SAMPLE_POS_1X(pat
._1xSample
);
786 GEN_SAMPLE_POS_2X(pat
._2xSample
);
787 GEN_SAMPLE_POS_4X(pat
._4xSample
);
788 GEN_SAMPLE_POS_8X(pat
._8xSample
);
790 GEN_SAMPLE_POS_16X(pat
._16xSample
);
794 /* Use the legacy AA line coverage computation. */
795 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
797 /* Disable chromakeying (it's for media) */
798 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
800 /* We want regular rendering, not special HiZ operations. */
801 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
803 /* No polygon stippling offsets are necessary. */
804 /* TODO: may need to set an offset for origin-UL framebuffers */
805 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
807 /* Set a static partitioning of the push constant area. */
808 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
809 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
810 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
811 alloc
._3DCommandSubOpcode
= 18 + i
;
812 alloc
.ConstantBufferOffset
= 6 * i
;
813 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
818 /* Gen11+ is enabled for us by the kernel. */
819 iris_enable_obj_preemption(batch
, true);
824 iris_init_compute_context(struct iris_screen
*screen
,
825 struct iris_batch
*batch
,
826 struct iris_vtable
*vtbl
,
827 struct pipe_debug_callback
*dbg
)
829 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
831 emit_pipeline_select(batch
, GPGPU
);
833 iris_emit_default_l3_config(batch
, devinfo
, true);
835 init_state_base_address(batch
);
838 if (devinfo
->is_geminilake
)
839 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
843 struct iris_vertex_buffer_state
{
844 /** The VERTEX_BUFFER_STATE hardware structure. */
845 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
847 /** The resource to source vertex data from. */
848 struct pipe_resource
*resource
;
851 struct iris_depth_buffer_state
{
852 /* Depth/HiZ/Stencil related hardware packets. */
853 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
854 GENX(3DSTATE_STENCIL_BUFFER_length
) +
855 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
856 GENX(3DSTATE_CLEAR_PARAMS_length
)];
860 * Generation-specific context state (ice->state.genx->...).
862 * Most state can go in iris_context directly, but these encode hardware
863 * packets which vary by generation.
865 struct iris_genx_state
{
866 struct iris_vertex_buffer_state vertex_buffers
[33];
867 uint32_t last_index_buffer
[GENX(3DSTATE_INDEX_BUFFER_length
)];
869 struct iris_depth_buffer_state depth_buffer
;
871 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
874 /* Is object level preemption enabled? */
875 bool object_preemption
;
880 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
882 } shaders
[MESA_SHADER_STAGES
];
886 * The pipe->set_blend_color() driver hook.
888 * This corresponds to our COLOR_CALC_STATE.
891 iris_set_blend_color(struct pipe_context
*ctx
,
892 const struct pipe_blend_color
*state
)
894 struct iris_context
*ice
= (struct iris_context
*) ctx
;
896 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
897 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
898 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
902 * Gallium CSO for blend state (see pipe_blend_state).
904 struct iris_blend_state
{
905 /** Partial 3DSTATE_PS_BLEND */
906 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
908 /** Partial BLEND_STATE */
909 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
910 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
912 bool alpha_to_coverage
; /* for shader key */
914 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
915 uint8_t blend_enables
;
917 /** Bitfield of whether color writes are enabled for RT[i] */
918 uint8_t color_write_enables
;
920 /** Does RT[0] use dual color blending? */
921 bool dual_color_blending
;
924 static enum pipe_blendfactor
925 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
928 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
929 return PIPE_BLENDFACTOR_ONE
;
931 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
932 return PIPE_BLENDFACTOR_ZERO
;
939 * The pipe->create_blend_state() driver hook.
941 * Translates a pipe_blend_state into iris_blend_state.
944 iris_create_blend_state(struct pipe_context
*ctx
,
945 const struct pipe_blend_state
*state
)
947 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
948 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
950 cso
->blend_enables
= 0;
951 cso
->color_write_enables
= 0;
952 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
954 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
956 bool indep_alpha_blend
= false;
958 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
959 const struct pipe_rt_blend_state
*rt
=
960 &state
->rt
[state
->independent_blend_enable
? i
: 0];
962 enum pipe_blendfactor src_rgb
=
963 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
964 enum pipe_blendfactor src_alpha
=
965 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
966 enum pipe_blendfactor dst_rgb
=
967 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
968 enum pipe_blendfactor dst_alpha
=
969 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
971 if (rt
->rgb_func
!= rt
->alpha_func
||
972 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
973 indep_alpha_blend
= true;
975 if (rt
->blend_enable
)
976 cso
->blend_enables
|= 1u << i
;
979 cso
->color_write_enables
|= 1u << i
;
981 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
982 be
.LogicOpEnable
= state
->logicop_enable
;
983 be
.LogicOpFunction
= state
->logicop_func
;
985 be
.PreBlendSourceOnlyClampEnable
= false;
986 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
987 be
.PreBlendColorClampEnable
= true;
988 be
.PostBlendColorClampEnable
= true;
990 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
992 be
.ColorBlendFunction
= rt
->rgb_func
;
993 be
.AlphaBlendFunction
= rt
->alpha_func
;
994 be
.SourceBlendFactor
= src_rgb
;
995 be
.SourceAlphaBlendFactor
= src_alpha
;
996 be
.DestinationBlendFactor
= dst_rgb
;
997 be
.DestinationAlphaBlendFactor
= dst_alpha
;
999 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
1000 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
1001 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
1002 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
1004 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
1007 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
1008 /* pb.HasWriteableRT is filled in at draw time.
1009 * pb.AlphaTestEnable is filled in at draw time.
1011 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1012 * setting it when dual color blending without an appropriate shader.
1015 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1016 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1018 pb
.SourceBlendFactor
=
1019 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1020 pb
.SourceAlphaBlendFactor
=
1021 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1022 pb
.DestinationBlendFactor
=
1023 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1024 pb
.DestinationAlphaBlendFactor
=
1025 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1028 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1029 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1030 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1031 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1032 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1033 bs
.ColorDitherEnable
= state
->dither
;
1034 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1037 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1043 * The pipe->bind_blend_state() driver hook.
1045 * Bind a blending CSO and flag related dirty bits.
1048 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1050 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1051 struct iris_blend_state
*cso
= state
;
1053 ice
->state
.cso_blend
= cso
;
1054 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1056 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1057 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1058 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1059 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1063 * Return true if the FS writes to any color outputs which are not disabled
1064 * via color masking.
1067 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1068 const struct shader_info
*fs_info
)
1073 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1075 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1076 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1078 return cso_blend
->color_write_enables
& rt_outputs
;
1082 * Gallium CSO for depth, stencil, and alpha testing state.
1084 struct iris_depth_stencil_alpha_state
{
1085 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1086 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1088 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1089 struct pipe_alpha_state alpha
;
1091 /** Outbound to resolve and cache set tracking. */
1092 bool depth_writes_enabled
;
1093 bool stencil_writes_enabled
;
1097 * The pipe->create_depth_stencil_alpha_state() driver hook.
1099 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1100 * testing state since we need pieces of it in a variety of places.
1103 iris_create_zsa_state(struct pipe_context
*ctx
,
1104 const struct pipe_depth_stencil_alpha_state
*state
)
1106 struct iris_depth_stencil_alpha_state
*cso
=
1107 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1109 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1111 cso
->alpha
= state
->alpha
;
1112 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1113 cso
->stencil_writes_enabled
=
1114 state
->stencil
[0].writemask
!= 0 ||
1115 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1117 /* The state tracker needs to optimize away EQUAL writes for us. */
1118 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1120 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1121 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1122 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1123 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1124 wmds
.StencilTestFunction
=
1125 translate_compare_func(state
->stencil
[0].func
);
1126 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1127 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1128 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1129 wmds
.BackfaceStencilTestFunction
=
1130 translate_compare_func(state
->stencil
[1].func
);
1131 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1132 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1133 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1134 wmds
.StencilBufferWriteEnable
=
1135 state
->stencil
[0].writemask
!= 0 ||
1136 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1137 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1138 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1139 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1140 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1141 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1142 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1143 /* wmds.[Backface]StencilReferenceValue are merged later */
1150 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1152 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1155 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1157 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1158 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1159 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1162 if (cso_changed(alpha
.ref_value
))
1163 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1165 if (cso_changed(alpha
.enabled
))
1166 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1168 if (cso_changed(alpha
.func
))
1169 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1171 if (cso_changed(depth_writes_enabled
))
1172 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1174 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1175 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1178 ice
->state
.cso_zsa
= new_cso
;
1179 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1180 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1181 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1185 * Gallium CSO for rasterizer state.
1187 struct iris_rasterizer_state
{
1188 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1189 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1190 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1191 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1192 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1194 uint8_t num_clip_plane_consts
;
1195 bool clip_halfz
; /* for CC_VIEWPORT */
1196 bool depth_clip_near
; /* for CC_VIEWPORT */
1197 bool depth_clip_far
; /* for CC_VIEWPORT */
1198 bool flatshade
; /* for shader state */
1199 bool flatshade_first
; /* for stream output */
1200 bool clamp_fragment_color
; /* for shader state */
1201 bool light_twoside
; /* for shader state */
1202 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1203 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1204 bool line_stipple_enable
;
1205 bool poly_stipple_enable
;
1207 bool force_persample_interp
;
1208 bool conservative_rasterization
;
1209 bool fill_mode_point_or_line
;
1210 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1211 uint16_t sprite_coord_enable
;
1215 get_line_width(const struct pipe_rasterizer_state
*state
)
1217 float line_width
= state
->line_width
;
1219 /* From the OpenGL 4.4 spec:
1221 * "The actual width of non-antialiased lines is determined by rounding
1222 * the supplied width to the nearest integer, then clamping it to the
1223 * implementation-dependent maximum non-antialiased line width."
1225 if (!state
->multisample
&& !state
->line_smooth
)
1226 line_width
= roundf(state
->line_width
);
1228 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1229 /* For 1 pixel line thickness or less, the general anti-aliasing
1230 * algorithm gives up, and a garbage line is generated. Setting a
1231 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1232 * (one-pixel-wide), non-antialiased lines.
1234 * Lines rendered with zero Line Width are rasterized using the
1235 * "Grid Intersection Quantization" rules as specified by the
1236 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1245 * The pipe->create_rasterizer_state() driver hook.
1248 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1249 const struct pipe_rasterizer_state
*state
)
1251 struct iris_rasterizer_state
*cso
=
1252 malloc(sizeof(struct iris_rasterizer_state
));
1254 cso
->multisample
= state
->multisample
;
1255 cso
->force_persample_interp
= state
->force_persample_interp
;
1256 cso
->clip_halfz
= state
->clip_halfz
;
1257 cso
->depth_clip_near
= state
->depth_clip_near
;
1258 cso
->depth_clip_far
= state
->depth_clip_far
;
1259 cso
->flatshade
= state
->flatshade
;
1260 cso
->flatshade_first
= state
->flatshade_first
;
1261 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1262 cso
->light_twoside
= state
->light_twoside
;
1263 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1264 cso
->half_pixel_center
= state
->half_pixel_center
;
1265 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1266 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1267 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1268 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1269 cso
->conservative_rasterization
=
1270 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1272 cso
->fill_mode_point_or_line
=
1273 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1274 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1275 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1276 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1278 if (state
->clip_plane_enable
!= 0)
1279 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1281 cso
->num_clip_plane_consts
= 0;
1283 float line_width
= get_line_width(state
);
1285 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1286 sf
.StatisticsEnable
= true;
1287 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1288 sf
.LineEndCapAntialiasingRegionWidth
=
1289 state
->line_smooth
? _10pixels
: _05pixels
;
1290 sf
.LastPixelEnable
= state
->line_last_pixel
;
1291 sf
.LineWidth
= line_width
;
1292 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1293 !state
->point_quad_rasterization
;
1294 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1295 sf
.PointWidth
= state
->point_size
;
1297 if (state
->flatshade_first
) {
1298 sf
.TriangleFanProvokingVertexSelect
= 1;
1300 sf
.TriangleStripListProvokingVertexSelect
= 2;
1301 sf
.TriangleFanProvokingVertexSelect
= 2;
1302 sf
.LineStripListProvokingVertexSelect
= 1;
1306 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1307 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1308 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1309 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1310 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1311 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1312 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1313 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1314 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1315 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1316 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1317 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1318 rr
.SmoothPointEnable
= state
->point_smooth
;
1319 rr
.AntialiasingEnable
= state
->line_smooth
;
1320 rr
.ScissorRectangleEnable
= state
->scissor
;
1322 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1323 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1324 rr
.ConservativeRasterizationEnable
=
1325 cso
->conservative_rasterization
;
1327 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1331 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1332 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1333 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1335 cl
.EarlyCullEnable
= true;
1336 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1337 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1338 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1339 cl
.GuardbandClipTestEnable
= true;
1340 cl
.ClipEnable
= true;
1341 cl
.MinimumPointWidth
= 0.125;
1342 cl
.MaximumPointWidth
= 255.875;
1344 if (state
->flatshade_first
) {
1345 cl
.TriangleFanProvokingVertexSelect
= 1;
1347 cl
.TriangleStripListProvokingVertexSelect
= 2;
1348 cl
.TriangleFanProvokingVertexSelect
= 2;
1349 cl
.LineStripListProvokingVertexSelect
= 1;
1353 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1354 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1355 * filled in at draw time from the FS program.
1357 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1358 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1359 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1360 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1361 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1364 /* Remap from 0..255 back to 1..256 */
1365 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1367 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1368 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1369 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1370 line
.LineStippleRepeatCount
= line_stipple_factor
;
1377 * The pipe->bind_rasterizer_state() driver hook.
1379 * Bind a rasterizer CSO and flag related dirty bits.
1382 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1384 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1385 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1386 struct iris_rasterizer_state
*new_cso
= state
;
1389 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1390 if (cso_changed_memcmp(line_stipple
))
1391 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1393 if (cso_changed(half_pixel_center
))
1394 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1396 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1397 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1399 if (cso_changed(rasterizer_discard
))
1400 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1402 if (cso_changed(flatshade_first
))
1403 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1405 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1406 cso_changed(clip_halfz
))
1407 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1409 if (cso_changed(sprite_coord_enable
) ||
1410 cso_changed(sprite_coord_mode
) ||
1411 cso_changed(light_twoside
))
1412 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1414 if (cso_changed(conservative_rasterization
))
1415 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1418 ice
->state
.cso_rast
= new_cso
;
1419 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1420 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1421 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1425 * Return true if the given wrap mode requires the border color to exist.
1427 * (We can skip uploading it if the sampler isn't going to use it.)
1430 wrap_mode_needs_border_color(unsigned wrap_mode
)
1432 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1436 * Gallium CSO for sampler state.
1438 struct iris_sampler_state
{
1439 union pipe_color_union border_color
;
1440 bool needs_border_color
;
1442 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1446 * The pipe->create_sampler_state() driver hook.
1448 * We fill out SAMPLER_STATE (except for the border color pointer), and
1449 * store that on the CPU. It doesn't make sense to upload it to a GPU
1450 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1451 * all bound sampler states to be in contiguous memor.
1454 iris_create_sampler_state(struct pipe_context
*ctx
,
1455 const struct pipe_sampler_state
*state
)
1457 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1462 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1463 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1465 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1466 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1467 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1469 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1471 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1472 wrap_mode_needs_border_color(wrap_t
) ||
1473 wrap_mode_needs_border_color(wrap_r
);
1475 float min_lod
= state
->min_lod
;
1476 unsigned mag_img_filter
= state
->mag_img_filter
;
1478 // XXX: explain this code ported from ilo...I don't get it at all...
1479 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1480 state
->min_lod
> 0.0f
) {
1482 mag_img_filter
= state
->min_img_filter
;
1485 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1486 samp
.TCXAddressControlMode
= wrap_s
;
1487 samp
.TCYAddressControlMode
= wrap_t
;
1488 samp
.TCZAddressControlMode
= wrap_r
;
1489 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1490 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1491 samp
.MinModeFilter
= state
->min_img_filter
;
1492 samp
.MagModeFilter
= mag_img_filter
;
1493 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1494 samp
.MaximumAnisotropy
= RATIO21
;
1496 if (state
->max_anisotropy
>= 2) {
1497 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1498 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1499 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1502 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1503 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1505 samp
.MaximumAnisotropy
=
1506 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1509 /* Set address rounding bits if not using nearest filtering. */
1510 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1511 samp
.UAddressMinFilterRoundingEnable
= true;
1512 samp
.VAddressMinFilterRoundingEnable
= true;
1513 samp
.RAddressMinFilterRoundingEnable
= true;
1516 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1517 samp
.UAddressMagFilterRoundingEnable
= true;
1518 samp
.VAddressMagFilterRoundingEnable
= true;
1519 samp
.RAddressMagFilterRoundingEnable
= true;
1522 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1523 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1525 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1527 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1528 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1529 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1530 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1532 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1539 * The pipe->bind_sampler_states() driver hook.
1542 iris_bind_sampler_states(struct pipe_context
*ctx
,
1543 enum pipe_shader_type p_stage
,
1544 unsigned start
, unsigned count
,
1547 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1548 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1549 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1551 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1553 for (int i
= 0; i
< count
; i
++) {
1554 shs
->samplers
[start
+ i
] = states
[i
];
1557 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1561 * Upload the sampler states into a contiguous area of GPU memory, for
1562 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1564 * Also fill out the border color state pointers.
1567 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1569 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1570 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1572 /* We assume the state tracker will call pipe->bind_sampler_states()
1573 * if the program's number of textures changes.
1575 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1580 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1581 * in the dynamic state memory zone, so we can point to it via the
1582 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1584 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1586 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1590 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1591 shs
->sampler_table
.offset
+=
1592 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1594 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1596 /* Make sure all land in the same BO */
1597 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1599 ice
->state
.need_border_colors
&= ~(1 << stage
);
1601 for (int i
= 0; i
< count
; i
++) {
1602 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1603 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1606 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1607 } else if (!state
->needs_border_color
) {
1608 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1610 ice
->state
.need_border_colors
|= 1 << stage
;
1612 /* We may need to swizzle the border color for format faking.
1613 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1614 * This means we need to move the border color's A channel into
1615 * the R or G channels so that those read swizzles will move it
1618 union pipe_color_union
*color
= &state
->border_color
;
1619 union pipe_color_union tmp
;
1621 enum pipe_format internal_format
= tex
->res
->internal_format
;
1623 if (util_format_is_alpha(internal_format
)) {
1624 unsigned char swz
[4] = {
1625 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1626 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1628 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1630 } else if (util_format_is_luminance_alpha(internal_format
) &&
1631 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1632 unsigned char swz
[4] = {
1633 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1634 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1636 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1641 /* Stream out the border color and merge the pointer. */
1642 uint32_t offset
= iris_upload_border_color(ice
, color
);
1644 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1645 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1646 dyns
.BorderColorPointer
= offset
;
1649 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1650 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1653 map
+= GENX(SAMPLER_STATE_length
);
1657 static enum isl_channel_select
1658 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1661 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1662 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1663 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1664 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1665 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1666 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1667 default: unreachable("invalid swizzle");
1672 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1673 struct iris_resource
*res
,
1675 enum isl_format format
,
1676 struct isl_swizzle swizzle
,
1680 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1681 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1683 /* The ARB_texture_buffer_specification says:
1685 * "The number of texels in the buffer texture's texel array is given by
1687 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1689 * where <buffer_size> is the size of the buffer object, in basic
1690 * machine units and <components> and <base_type> are the element count
1691 * and base data type for elements, as specified in Table X.1. The
1692 * number of texels in the texel array is then clamped to the
1693 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1695 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1696 * so that when ISL divides by stride to obtain the number of texels, that
1697 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1699 unsigned final_size
=
1700 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1701 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1703 isl_buffer_fill_state(isl_dev
, map
,
1704 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1705 .size_B
= final_size
,
1709 .mocs
= mocs(res
->bo
));
1712 #define SURFACE_STATE_ALIGNMENT 64
1715 * Allocate several contiguous SURFACE_STATE structures, one for each
1716 * supported auxiliary surface mode.
1719 alloc_surface_states(struct u_upload_mgr
*mgr
,
1720 struct iris_state_ref
*ref
,
1721 unsigned aux_usages
)
1723 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1725 /* If this changes, update this to explicitly align pointers */
1726 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1728 assert(aux_usages
!= 0);
1731 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1732 SURFACE_STATE_ALIGNMENT
);
1734 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1741 * Return an ISL surface for use with non-coherent render target reads.
1743 * In a few complex cases, we can't use the SURFACE_STATE for normal render
1744 * target writes. We need to make a separate one for sampling which refers
1745 * to the single slice of the texture being read.
1748 get_rt_read_isl_surf(const struct gen_device_info
*devinfo
,
1749 struct iris_resource
*res
,
1750 enum pipe_texture_target target
,
1751 struct isl_view
*view
,
1752 uint32_t *tile_x_sa
,
1753 uint32_t *tile_y_sa
,
1754 struct isl_surf
*surf
)
1759 const enum isl_dim_layout dim_layout
=
1760 iris_get_isl_dim_layout(devinfo
, res
->surf
.tiling
, target
);
1762 surf
->dim
= target_to_isl_surf_dim(target
);
1764 if (surf
->dim_layout
== dim_layout
)
1767 /* The layout of the specified texture target is not compatible with the
1768 * actual layout of the miptree structure in memory -- You're entering
1769 * dangerous territory, this can only possibly work if you only intended
1770 * to access a single level and slice of the texture, and the hardware
1771 * supports the tile offset feature in order to allow non-tile-aligned
1772 * base offsets, since we'll have to point the hardware to the first
1773 * texel of the level instead of relying on the usual base level/layer
1776 assert(view
->levels
== 1 && view
->array_len
== 1);
1777 assert(*tile_x_sa
== 0 && *tile_y_sa
== 0);
1779 res
->offset
+= iris_resource_get_tile_offsets(res
, view
->base_level
,
1780 view
->base_array_layer
,
1781 tile_x_sa
, tile_y_sa
);
1782 const unsigned l
= view
->base_level
;
1784 surf
->logical_level0_px
.width
= minify(surf
->logical_level0_px
.width
, l
);
1785 surf
->logical_level0_px
.height
= surf
->dim
<= ISL_SURF_DIM_1D
? 1 :
1786 minify(surf
->logical_level0_px
.height
, l
);
1787 surf
->logical_level0_px
.depth
= surf
->dim
<= ISL_SURF_DIM_2D
? 1 :
1788 minify(surf
->logical_level0_px
.depth
, l
);
1790 surf
->logical_level0_px
.array_len
= 1;
1792 surf
->dim_layout
= dim_layout
;
1794 view
->base_level
= 0;
1795 view
->base_array_layer
= 0;
1800 fill_surface_state(struct isl_device
*isl_dev
,
1802 struct iris_resource
*res
,
1803 struct isl_surf
*surf
,
1804 struct isl_view
*view
,
1809 struct isl_surf_fill_state_info f
= {
1812 .mocs
= mocs(res
->bo
),
1813 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1814 .x_offset_sa
= tile_x_sa
,
1815 .y_offset_sa
= tile_y_sa
,
1818 assert(!iris_resource_unfinished_aux_import(res
));
1820 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1821 f
.aux_surf
= &res
->aux
.surf
;
1822 f
.aux_usage
= aux_usage
;
1823 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1825 struct iris_bo
*clear_bo
= NULL
;
1826 uint64_t clear_offset
= 0;
1828 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1830 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1831 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1835 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1839 * The pipe->create_sampler_view() driver hook.
1841 static struct pipe_sampler_view
*
1842 iris_create_sampler_view(struct pipe_context
*ctx
,
1843 struct pipe_resource
*tex
,
1844 const struct pipe_sampler_view
*tmpl
)
1846 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1847 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1848 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1849 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1854 /* initialize base object */
1856 isv
->base
.context
= ctx
;
1857 isv
->base
.texture
= NULL
;
1858 pipe_reference_init(&isv
->base
.reference
, 1);
1859 pipe_resource_reference(&isv
->base
.texture
, tex
);
1861 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1862 struct iris_resource
*zres
, *sres
;
1863 const struct util_format_description
*desc
=
1864 util_format_description(tmpl
->format
);
1866 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1868 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1871 isv
->res
= (struct iris_resource
*) tex
;
1873 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1874 &isv
->surface_state
,
1875 isv
->res
->aux
.sampler_usages
);
1879 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1881 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1882 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1883 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1885 const struct iris_format_info fmt
=
1886 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1888 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1890 isv
->view
= (struct isl_view
) {
1892 .swizzle
= (struct isl_swizzle
) {
1893 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1894 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1895 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1896 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1901 /* Fill out SURFACE_STATE for this view. */
1902 if (tmpl
->target
!= PIPE_BUFFER
) {
1903 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1904 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1905 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1906 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1907 isv
->view
.array_len
=
1908 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1910 if (iris_resource_unfinished_aux_import(isv
->res
))
1911 iris_resource_finish_aux_import(&screen
->base
, isv
->res
);
1913 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1915 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1917 /* If we have a multisampled depth buffer, do not create a sampler
1918 * surface state with HiZ.
1920 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->res
->surf
,
1921 &isv
->view
, aux_usage
, 0, 0);
1923 map
+= SURFACE_STATE_ALIGNMENT
;
1926 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1927 isv
->view
.format
, isv
->view
.swizzle
,
1928 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1935 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1936 struct pipe_sampler_view
*state
)
1938 struct iris_sampler_view
*isv
= (void *) state
;
1939 pipe_resource_reference(&state
->texture
, NULL
);
1940 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1945 * The pipe->create_surface() driver hook.
1947 * In Gallium nomenclature, "surfaces" are a view of a resource that
1948 * can be bound as a render target or depth/stencil buffer.
1950 static struct pipe_surface
*
1951 iris_create_surface(struct pipe_context
*ctx
,
1952 struct pipe_resource
*tex
,
1953 const struct pipe_surface
*tmpl
)
1955 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1956 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1957 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1959 isl_surf_usage_flags_t usage
= 0;
1961 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1962 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1963 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1965 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1967 const struct iris_format_info fmt
=
1968 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1970 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1971 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1972 /* Framebuffer validation will reject this invalid case, but it
1973 * hasn't had the opportunity yet. In the meantime, we need to
1974 * avoid hitting ISL asserts about unsupported formats below.
1979 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1980 struct pipe_surface
*psurf
= &surf
->base
;
1981 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1986 pipe_reference_init(&psurf
->reference
, 1);
1987 pipe_resource_reference(&psurf
->texture
, tex
);
1988 psurf
->context
= ctx
;
1989 psurf
->format
= tmpl
->format
;
1990 psurf
->width
= tex
->width0
;
1991 psurf
->height
= tex
->height0
;
1992 psurf
->texture
= tex
;
1993 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1994 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1995 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1997 uint32_t array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1999 struct isl_view
*view
= &surf
->view
;
2000 *view
= (struct isl_view
) {
2002 .base_level
= tmpl
->u
.tex
.level
,
2004 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2005 .array_len
= array_len
,
2006 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2011 enum pipe_texture_target target
= (tex
->target
== PIPE_TEXTURE_3D
&&
2012 array_len
== 1) ? PIPE_TEXTURE_2D
:
2013 tex
->target
== PIPE_TEXTURE_1D_ARRAY
?
2014 PIPE_TEXTURE_2D_ARRAY
: tex
->target
;
2016 struct isl_view
*read_view
= &surf
->read_view
;
2017 *read_view
= (struct isl_view
) {
2019 .base_level
= tmpl
->u
.tex
.level
,
2021 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
2022 .array_len
= array_len
,
2023 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2024 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
2028 surf
->clear_color
= res
->aux
.clear_color
;
2030 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
2031 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
2032 ISL_SURF_USAGE_STENCIL_BIT
))
2036 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
2037 &surf
->surface_state
,
2038 res
->aux
.possible_usages
);
2039 if (!unlikely(map
)) {
2040 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2045 void *map_read
= alloc_surface_states(ice
->state
.surface_uploader
,
2046 &surf
->surface_state_read
,
2047 res
->aux
.possible_usages
);
2048 if (!unlikely(map_read
)) {
2049 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2054 if (!isl_format_is_compressed(res
->surf
.format
)) {
2055 if (iris_resource_unfinished_aux_import(res
))
2056 iris_resource_finish_aux_import(&screen
->base
, res
);
2058 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
2059 * auxiliary surface mode and return the pipe_surface.
2061 unsigned aux_modes
= res
->aux
.possible_usages
;
2064 uint32_t offset
= res
->offset
;
2066 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
2067 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2068 view
, aux_usage
, 0, 0);
2069 map
+= SURFACE_STATE_ALIGNMENT
;
2072 struct isl_surf surf
;
2073 uint32_t tile_x_sa
= 0, tile_y_sa
= 0;
2074 get_rt_read_isl_surf(devinfo
, res
, target
, read_view
,
2075 &tile_x_sa
, &tile_y_sa
, &surf
);
2076 fill_surface_state(&screen
->isl_dev
, map_read
, res
, &surf
, read_view
,
2077 aux_usage
, tile_x_sa
, tile_y_sa
);
2078 /* Restore offset because we change offset in case of handling
2079 * non_coherent fb fetch
2081 res
->offset
= offset
;
2082 map_read
+= SURFACE_STATE_ALIGNMENT
;
2089 /* The resource has a compressed format, which is not renderable, but we
2090 * have a renderable view format. We must be attempting to upload blocks
2091 * of compressed data via an uncompressed view.
2093 * In this case, we can assume there are no auxiliary buffers, a single
2094 * miplevel, and that the resource is single-sampled. Gallium may try
2095 * and create an uncompressed view with multiple layers, however.
2097 assert(!isl_format_is_compressed(fmt
.fmt
));
2098 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
2099 assert(res
->surf
.samples
== 1);
2100 assert(view
->levels
== 1);
2102 struct isl_surf isl_surf
;
2103 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
2105 if (view
->base_level
> 0) {
2106 /* We can't rely on the hardware's miplevel selection with such
2107 * a substantial lie about the format, so we select a single image
2108 * using the Tile X/Y Offset fields. In this case, we can't handle
2109 * multiple array slices.
2111 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
2112 * hard-coded to align to exactly the block size of the compressed
2113 * texture. This means that, when reinterpreted as a non-compressed
2114 * texture, the tile offsets may be anything and we can't rely on
2117 * Return NULL to force the state tracker to take fallback paths.
2119 if (view
->array_len
> 1 || GEN_GEN
== 8)
2122 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
2123 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
2125 is_3d
? 0 : view
->base_array_layer
,
2126 is_3d
? view
->base_array_layer
: 0,
2128 &offset_B
, &tile_x_sa
, &tile_y_sa
);
2130 /* We use address and tile offsets to access a single level/layer
2131 * as a subimage, so reset level/layer so it doesn't offset again.
2133 view
->base_array_layer
= 0;
2134 view
->base_level
= 0;
2136 /* Level 0 doesn't require tile offsets, and the hardware can find
2137 * array slices using QPitch even with the format override, so we
2138 * can allow layers in this case. Copy the original ISL surface.
2140 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2143 /* Scale down the image dimensions by the block size. */
2144 const struct isl_format_layout
*fmtl
=
2145 isl_format_get_layout(res
->surf
.format
);
2146 isl_surf
.format
= fmt
.fmt
;
2147 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2148 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2149 tile_x_sa
/= fmtl
->bw
;
2150 tile_y_sa
/= fmtl
->bh
;
2152 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2153 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2155 struct isl_surf_fill_state_info f
= {
2158 .mocs
= mocs(res
->bo
),
2159 .address
= res
->bo
->gtt_offset
+ offset_B
,
2160 .x_offset_sa
= tile_x_sa
,
2161 .y_offset_sa
= tile_y_sa
,
2164 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2170 fill_default_image_param(struct brw_image_param
*param
)
2172 memset(param
, 0, sizeof(*param
));
2173 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2174 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2175 * detailed explanation of these parameters.
2177 param
->swizzling
[0] = 0xff;
2178 param
->swizzling
[1] = 0xff;
2182 fill_buffer_image_param(struct brw_image_param
*param
,
2183 enum pipe_format pfmt
,
2186 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2188 fill_default_image_param(param
);
2189 param
->size
[0] = size
/ cpp
;
2190 param
->stride
[0] = cpp
;
2193 #define isl_surf_fill_image_param(x, ...)
2194 #define fill_default_image_param(x, ...)
2195 #define fill_buffer_image_param(x, ...)
2199 * The pipe->set_shader_images() driver hook.
2202 iris_set_shader_images(struct pipe_context
*ctx
,
2203 enum pipe_shader_type p_stage
,
2204 unsigned start_slot
, unsigned count
,
2205 const struct pipe_image_view
*p_images
)
2207 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2208 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2209 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2210 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2211 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2213 struct iris_genx_state
*genx
= ice
->state
.genx
;
2214 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2217 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2219 for (unsigned i
= 0; i
< count
; i
++) {
2220 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2222 if (p_images
&& p_images
[i
].resource
) {
2223 const struct pipe_image_view
*img
= &p_images
[i
];
2224 struct iris_resource
*res
= (void *) img
->resource
;
2227 alloc_surface_states(ice
->state
.surface_uploader
,
2228 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2232 util_copy_image_view(&iv
->base
, img
);
2234 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2236 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2238 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2239 enum isl_format isl_fmt
=
2240 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2242 bool untyped_fallback
= false;
2244 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2245 /* On Gen8, try to use typed surfaces reads (which support a
2246 * limited number of formats), and if not possible, fall back
2249 untyped_fallback
= GEN_GEN
== 8 &&
2250 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2252 if (untyped_fallback
)
2253 isl_fmt
= ISL_FORMAT_RAW
;
2255 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2258 if (res
->base
.target
!= PIPE_BUFFER
) {
2259 struct isl_view view
= {
2261 .base_level
= img
->u
.tex
.level
,
2263 .base_array_layer
= img
->u
.tex
.first_layer
,
2264 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2265 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2269 if (untyped_fallback
) {
2270 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2271 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2274 /* Images don't support compression */
2275 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2277 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2279 fill_surface_state(&screen
->isl_dev
, map
, res
, &res
->surf
,
2280 &view
, usage
, 0, 0);
2282 map
+= SURFACE_STATE_ALIGNMENT
;
2286 isl_surf_fill_image_param(&screen
->isl_dev
,
2287 &image_params
[start_slot
+ i
],
2290 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2291 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2293 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2294 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2295 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2296 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2297 img
->format
, img
->u
.buf
.size
);
2300 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2301 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2302 fill_default_image_param(&image_params
[start_slot
+ i
]);
2306 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2308 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2309 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2311 /* Broadwell also needs brw_image_params re-uploaded */
2313 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2314 shs
->sysvals_need_upload
= true;
2320 * The pipe->set_sampler_views() driver hook.
2323 iris_set_sampler_views(struct pipe_context
*ctx
,
2324 enum pipe_shader_type p_stage
,
2325 unsigned start
, unsigned count
,
2326 struct pipe_sampler_view
**views
)
2328 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2329 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2330 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2332 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2334 for (unsigned i
= 0; i
< count
; i
++) {
2335 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2336 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2337 &shs
->textures
[start
+ i
], pview
);
2338 struct iris_sampler_view
*view
= (void *) pview
;
2340 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2341 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2345 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2347 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2348 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2352 * The pipe->set_tess_state() driver hook.
2355 iris_set_tess_state(struct pipe_context
*ctx
,
2356 const float default_outer_level
[4],
2357 const float default_inner_level
[2])
2359 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2360 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2362 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2363 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2365 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2366 shs
->sysvals_need_upload
= true;
2370 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2372 struct iris_surface
*surf
= (void *) p_surf
;
2373 pipe_resource_reference(&p_surf
->texture
, NULL
);
2374 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2375 pipe_resource_reference(&surf
->surface_state_read
.res
, NULL
);
2380 iris_set_clip_state(struct pipe_context
*ctx
,
2381 const struct pipe_clip_state
*state
)
2383 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2384 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2385 struct iris_shader_state
*gshs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
2386 struct iris_shader_state
*tshs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
2388 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2390 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
| IRIS_DIRTY_CONSTANTS_GS
|
2391 IRIS_DIRTY_CONSTANTS_TES
;
2392 shs
->sysvals_need_upload
= true;
2393 gshs
->sysvals_need_upload
= true;
2394 tshs
->sysvals_need_upload
= true;
2398 * The pipe->set_polygon_stipple() driver hook.
2401 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2402 const struct pipe_poly_stipple
*state
)
2404 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2405 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2406 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2410 * The pipe->set_sample_mask() driver hook.
2413 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2415 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2417 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2418 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2420 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2421 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2425 * The pipe->set_scissor_states() driver hook.
2427 * This corresponds to our SCISSOR_RECT state structures. It's an
2428 * exact match, so we just store them, and memcpy them out later.
2431 iris_set_scissor_states(struct pipe_context
*ctx
,
2432 unsigned start_slot
,
2433 unsigned num_scissors
,
2434 const struct pipe_scissor_state
*rects
)
2436 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2438 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2439 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2440 /* If the scissor was out of bounds and got clamped to 0 width/height
2441 * at the bounds, the subtraction of 1 from maximums could produce a
2442 * negative number and thus not clip anything. Instead, just provide
2443 * a min > max scissor inside the bounds, which produces the expected
2446 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2447 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2450 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2451 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2452 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2457 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2461 * The pipe->set_stencil_ref() driver hook.
2463 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2466 iris_set_stencil_ref(struct pipe_context
*ctx
,
2467 const struct pipe_stencil_ref
*state
)
2469 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2470 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2472 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2474 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2478 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2480 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2484 * The pipe->set_viewport_states() driver hook.
2486 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2487 * the guardband yet, as we need the framebuffer dimensions, but we can
2488 * at least fill out the rest.
2491 iris_set_viewport_states(struct pipe_context
*ctx
,
2492 unsigned start_slot
,
2494 const struct pipe_viewport_state
*states
)
2496 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2498 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2500 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2502 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2503 !ice
->state
.cso_rast
->depth_clip_far
))
2504 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2508 * The pipe->set_framebuffer_state() driver hook.
2510 * Sets the current draw FBO, including color render targets, depth,
2511 * and stencil buffers.
2514 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2515 const struct pipe_framebuffer_state
*state
)
2517 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2518 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2519 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2520 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2521 struct iris_resource
*zres
;
2522 struct iris_resource
*stencil_res
;
2524 unsigned samples
= util_framebuffer_get_num_samples(state
);
2525 unsigned layers
= util_framebuffer_get_num_layers(state
);
2527 if (cso
->samples
!= samples
) {
2528 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2530 /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
2531 if (GEN_GEN
>= 9 && (cso
->samples
== 16 || samples
== 16))
2532 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
2535 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2536 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2539 if ((cso
->layers
== 0) != (layers
== 0)) {
2540 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2543 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2544 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2547 if (cso
->zsbuf
|| state
->zsbuf
) {
2548 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2551 util_copy_framebuffer_state(cso
, state
);
2552 cso
->samples
= samples
;
2553 cso
->layers
= layers
;
2555 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2557 struct isl_view view
= {
2560 .base_array_layer
= 0,
2562 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2565 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2568 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2571 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2572 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2574 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2577 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2579 info
.depth_surf
= &zres
->surf
;
2580 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2581 info
.mocs
= mocs(zres
->bo
);
2583 view
.format
= zres
->surf
.format
;
2585 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2586 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2587 info
.hiz_surf
= &zres
->aux
.surf
;
2588 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
+ zres
->aux
.offset
;
2593 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2594 info
.stencil_surf
= &stencil_res
->surf
;
2595 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2597 view
.format
= stencil_res
->surf
.format
;
2598 info
.mocs
= mocs(stencil_res
->bo
);
2603 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2605 /* Make a null surface for unbound buffers */
2606 void *null_surf_map
=
2607 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2608 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2609 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2610 isl_extent3d(MAX2(cso
->width
, 1),
2611 MAX2(cso
->height
, 1),
2612 cso
->layers
? cso
->layers
: 1));
2613 ice
->state
.null_fb
.offset
+=
2614 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2616 /* Render target change */
2617 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2619 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2621 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2624 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2625 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2627 /* The PIPE_CONTROL command description says:
2629 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2630 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2631 * Target Cache Flush by enabling this bit. When render target flush
2632 * is set due to new association of BTI, PS Scoreboard Stall bit must
2633 * be set in this packet."
2635 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2636 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2637 "workaround: RT BTI change [draw]",
2638 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2639 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2644 * The pipe->set_constant_buffer() driver hook.
2646 * This uploads any constant data in user buffers, and references
2647 * any UBO resources containing constant data.
2650 iris_set_constant_buffer(struct pipe_context
*ctx
,
2651 enum pipe_shader_type p_stage
, unsigned index
,
2652 const struct pipe_constant_buffer
*input
)
2654 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2655 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2656 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2657 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2659 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2660 shs
->bound_cbufs
|= 1u << index
;
2662 if (input
->user_buffer
) {
2664 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2665 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2666 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2668 if (!cbuf
->buffer
) {
2669 /* Allocation was unsuccessful - just unbind */
2670 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2675 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2676 } else if (input
->buffer
) {
2677 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2679 cbuf
->buffer_offset
= input
->buffer_offset
;
2681 MIN2(input
->buffer_size
,
2682 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2685 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2686 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2688 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2689 &shs
->constbuf_surf_state
[index
],
2692 shs
->bound_cbufs
&= ~(1u << index
);
2693 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2694 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2697 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2698 // XXX: maybe not necessary all the time...?
2699 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2700 // XXX: pull model we may need actual new bindings...
2701 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2705 upload_sysvals(struct iris_context
*ice
,
2706 gl_shader_stage stage
)
2708 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2709 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2711 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2712 if (!shader
|| shader
->num_system_values
== 0)
2715 assert(shader
->num_cbufs
> 0);
2717 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2718 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2719 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2720 uint32_t *map
= NULL
;
2722 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2723 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2724 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2726 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2727 uint32_t sysval
= shader
->system_values
[i
];
2730 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2732 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2733 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2734 struct brw_image_param
*param
=
2735 &genx
->shaders
[stage
].image_param
[img
];
2737 assert(offset
< sizeof(struct brw_image_param
));
2738 value
= ((uint32_t *) param
)[offset
];
2740 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2742 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2743 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2744 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2745 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2746 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2747 if (stage
== MESA_SHADER_TESS_CTRL
) {
2748 value
= ice
->state
.vertices_per_patch
;
2750 assert(stage
== MESA_SHADER_TESS_EVAL
);
2751 const struct shader_info
*tcs_info
=
2752 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2754 value
= tcs_info
->tess
.tcs_vertices_out
;
2756 value
= ice
->state
.vertices_per_patch
;
2758 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2759 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2760 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2761 value
= fui(ice
->state
.default_outer_level
[i
]);
2762 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2763 value
= fui(ice
->state
.default_inner_level
[0]);
2764 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2765 value
= fui(ice
->state
.default_inner_level
[1]);
2767 assert(!"unhandled system value");
2773 cbuf
->buffer_size
= upload_size
;
2774 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2775 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2777 shs
->sysvals_need_upload
= false;
2781 * The pipe->set_shader_buffers() driver hook.
2783 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2784 * SURFACE_STATE here, as the buffer offset may change each time.
2787 iris_set_shader_buffers(struct pipe_context
*ctx
,
2788 enum pipe_shader_type p_stage
,
2789 unsigned start_slot
, unsigned count
,
2790 const struct pipe_shader_buffer
*buffers
,
2791 unsigned writable_bitmask
)
2793 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2794 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2795 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2797 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2799 shs
->bound_ssbos
&= ~modified_bits
;
2800 shs
->writable_ssbos
&= ~modified_bits
;
2801 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2803 for (unsigned i
= 0; i
< count
; i
++) {
2804 if (buffers
&& buffers
[i
].buffer
) {
2805 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2806 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2807 struct iris_state_ref
*surf_state
=
2808 &shs
->ssbo_surf_state
[start_slot
+ i
];
2809 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2810 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2812 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2814 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2816 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2818 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2820 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2821 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2823 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2824 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2829 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2833 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2839 * The pipe->set_vertex_buffers() driver hook.
2841 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2844 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2845 unsigned start_slot
, unsigned count
,
2846 const struct pipe_vertex_buffer
*buffers
)
2848 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2849 struct iris_genx_state
*genx
= ice
->state
.genx
;
2851 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2853 for (unsigned i
= 0; i
< count
; i
++) {
2854 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2855 struct iris_vertex_buffer_state
*state
=
2856 &genx
->vertex_buffers
[start_slot
+ i
];
2859 pipe_resource_reference(&state
->resource
, NULL
);
2863 /* We may see user buffers that are NULL bindings. */
2864 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2866 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2867 struct iris_resource
*res
= (void *) state
->resource
;
2870 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2871 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2874 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2875 vb
.VertexBufferIndex
= start_slot
+ i
;
2876 vb
.AddressModifyEnable
= true;
2877 vb
.BufferPitch
= buffer
->stride
;
2879 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2880 vb
.BufferStartingAddress
=
2881 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2882 vb
.MOCS
= mocs(res
->bo
);
2884 vb
.NullVertexBuffer
= true;
2889 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2893 * Gallium CSO for vertex elements.
2895 struct iris_vertex_element_state
{
2896 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2897 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2898 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2899 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2904 * The pipe->create_vertex_elements() driver hook.
2906 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2907 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2908 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2909 * needed. In these cases we will need information available at draw time.
2910 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2911 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2912 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2915 iris_create_vertex_elements(struct pipe_context
*ctx
,
2917 const struct pipe_vertex_element
*state
)
2919 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2920 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2921 struct iris_vertex_element_state
*cso
=
2922 malloc(sizeof(struct iris_vertex_element_state
));
2926 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2928 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2931 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2932 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2935 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2937 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2938 ve
.Component0Control
= VFCOMP_STORE_0
;
2939 ve
.Component1Control
= VFCOMP_STORE_0
;
2940 ve
.Component2Control
= VFCOMP_STORE_0
;
2941 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2944 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2948 for (int i
= 0; i
< count
; i
++) {
2949 const struct iris_format_info fmt
=
2950 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2951 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2952 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2954 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2955 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2956 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2957 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2959 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2960 : VFCOMP_STORE_1_FP
;
2963 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2964 ve
.EdgeFlagEnable
= false;
2965 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2967 ve
.SourceElementOffset
= state
[i
].src_offset
;
2968 ve
.SourceElementFormat
= fmt
.fmt
;
2969 ve
.Component0Control
= comp
[0];
2970 ve
.Component1Control
= comp
[1];
2971 ve
.Component2Control
= comp
[2];
2972 ve
.Component3Control
= comp
[3];
2975 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2976 vi
.VertexElementIndex
= i
;
2977 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2978 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2981 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2982 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2985 /* An alternative version of the last VE and VFI is stored so it
2986 * can be used at draw time in case Vertex Shader uses EdgeFlag
2989 const unsigned edgeflag_index
= count
- 1;
2990 const struct iris_format_info fmt
=
2991 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2992 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2993 ve
.EdgeFlagEnable
= true ;
2994 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2996 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2997 ve
.SourceElementFormat
= fmt
.fmt
;
2998 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2999 ve
.Component1Control
= VFCOMP_STORE_0
;
3000 ve
.Component2Control
= VFCOMP_STORE_0
;
3001 ve
.Component3Control
= VFCOMP_STORE_0
;
3003 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
3004 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
3005 * at draw time, as it should change if SGVs are emitted.
3007 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
3008 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
3016 * The pipe->bind_vertex_elements_state() driver hook.
3019 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
3021 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3022 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
3023 struct iris_vertex_element_state
*new_cso
= state
;
3025 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
3026 * we need to re-emit it to ensure we're overriding the right one.
3028 if (new_cso
&& cso_changed(count
))
3029 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
3031 ice
->state
.cso_vertex_elements
= state
;
3032 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
3036 * The pipe->create_stream_output_target() driver hook.
3038 * "Target" here refers to a destination buffer. We translate this into
3039 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
3040 * know which buffer this represents, or whether we ought to zero the
3041 * write-offsets, or append. Those are handled in the set() hook.
3043 static struct pipe_stream_output_target
*
3044 iris_create_stream_output_target(struct pipe_context
*ctx
,
3045 struct pipe_resource
*p_res
,
3046 unsigned buffer_offset
,
3047 unsigned buffer_size
)
3049 struct iris_resource
*res
= (void *) p_res
;
3050 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
3054 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
3056 pipe_reference_init(&cso
->base
.reference
, 1);
3057 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
3058 cso
->base
.buffer_offset
= buffer_offset
;
3059 cso
->base
.buffer_size
= buffer_size
;
3060 cso
->base
.context
= ctx
;
3062 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
3063 buffer_offset
+ buffer_size
);
3065 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
3071 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
3072 struct pipe_stream_output_target
*state
)
3074 struct iris_stream_output_target
*cso
= (void *) state
;
3076 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
3077 pipe_resource_reference(&cso
->offset
.res
, NULL
);
3083 * The pipe->set_stream_output_targets() driver hook.
3085 * At this point, we know which targets are bound to a particular index,
3086 * and also whether we want to append or start over. We can finish the
3087 * 3DSTATE_SO_BUFFER packets we started earlier.
3090 iris_set_stream_output_targets(struct pipe_context
*ctx
,
3091 unsigned num_targets
,
3092 struct pipe_stream_output_target
**targets
,
3093 const unsigned *offsets
)
3095 struct iris_context
*ice
= (struct iris_context
*) ctx
;
3096 struct iris_genx_state
*genx
= ice
->state
.genx
;
3097 uint32_t *so_buffers
= genx
->so_buffers
;
3099 const bool active
= num_targets
> 0;
3100 if (ice
->state
.streamout_active
!= active
) {
3101 ice
->state
.streamout_active
= active
;
3102 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
3104 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
3105 * it's a non-pipelined command. If we're switching streamout on, we
3106 * may have missed emitting it earlier, so do so now. (We're already
3107 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
3110 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
3113 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
3114 struct iris_stream_output_target
*tgt
=
3115 (void *) ice
->state
.so_target
[i
];
3117 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3119 flush
|= iris_flush_bits_for_history(res
);
3120 iris_dirty_for_history(ice
, res
);
3123 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
3124 "make streamout results visible", flush
);
3128 for (int i
= 0; i
< 4; i
++) {
3129 pipe_so_target_reference(&ice
->state
.so_target
[i
],
3130 i
< num_targets
? targets
[i
] : NULL
);
3133 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
3137 for (unsigned i
= 0; i
< 4; i
++,
3138 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
3140 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
3141 unsigned offset
= offsets
[i
];
3144 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3145 sob
.SOBufferIndex
= i
;
3149 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3151 /* Note that offsets[i] will either be 0, causing us to zero
3152 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3153 * "continue appending at the existing offset."
3155 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3157 /* We might be called by Begin (offset = 0), Pause, then Resume
3158 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3159 * will actually be sent to the GPU). In this case, we don't want
3160 * to append - we still want to do our initial zeroing.
3165 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3166 sob
.SurfaceBaseAddress
=
3167 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3168 sob
.SOBufferEnable
= true;
3169 sob
.StreamOffsetWriteEnable
= true;
3170 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3171 sob
.MOCS
= mocs(res
->bo
);
3173 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3175 sob
.SOBufferIndex
= i
;
3176 sob
.StreamOffset
= offset
;
3177 sob
.StreamOutputBufferOffsetAddress
=
3178 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3179 tgt
->offset
.offset
);
3183 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3187 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3188 * 3DSTATE_STREAMOUT packets.
3190 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3191 * hardware to record. We can create it entirely based on the shader, with
3192 * no dynamic state dependencies.
3194 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3195 * state-based settings. We capture the shader-related ones here, and merge
3196 * the rest in at draw time.
3199 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3200 const struct brw_vue_map
*vue_map
)
3202 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3203 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3204 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3205 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3207 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3209 memset(so_decl
, 0, sizeof(so_decl
));
3211 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3212 * command feels strange -- each dword pair contains a SO_DECL per stream.
3214 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3215 const struct pipe_stream_output
*output
= &info
->output
[i
];
3216 const int buffer
= output
->output_buffer
;
3217 const int varying
= output
->register_index
;
3218 const unsigned stream_id
= output
->stream
;
3219 assert(stream_id
< MAX_VERTEX_STREAMS
);
3221 buffer_mask
[stream_id
] |= 1 << buffer
;
3223 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3225 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3226 * array. Instead, it simply increments DstOffset for the following
3227 * input by the number of components that should be skipped.
3229 * Our hardware is unusual in that it requires us to program SO_DECLs
3230 * for fake "hole" components, rather than simply taking the offset
3231 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3232 * program as many size = 4 holes as we can, then a final hole to
3233 * accommodate the final 1, 2, or 3 remaining.
3235 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3237 while (skip_components
> 0) {
3238 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3240 .OutputBufferSlot
= output
->output_buffer
,
3241 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3243 skip_components
-= 4;
3246 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3248 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3249 .OutputBufferSlot
= output
->output_buffer
,
3250 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3252 ((1 << output
->num_components
) - 1) << output
->start_component
,
3255 if (decls
[stream_id
] > max_decls
)
3256 max_decls
= decls
[stream_id
];
3259 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3260 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3261 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3263 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3264 int urb_entry_read_offset
= 0;
3265 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3266 urb_entry_read_offset
;
3268 /* We always read the whole vertex. This could be reduced at some
3269 * point by reading less and offsetting the register index in the
3272 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3273 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3274 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3275 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3276 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3277 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3278 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3279 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3281 /* Set buffer pitches; 0 means unbound. */
3282 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3283 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3284 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3285 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3288 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3289 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3290 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3291 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3292 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3293 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3294 list
.NumEntries0
= decls
[0];
3295 list
.NumEntries1
= decls
[1];
3296 list
.NumEntries2
= decls
[2];
3297 list
.NumEntries3
= decls
[3];
3300 for (int i
= 0; i
< max_decls
; i
++) {
3301 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3302 entry
.Stream0Decl
= so_decl
[0][i
];
3303 entry
.Stream1Decl
= so_decl
[1][i
];
3304 entry
.Stream2Decl
= so_decl
[2][i
];
3305 entry
.Stream3Decl
= so_decl
[3][i
];
3313 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3314 const struct brw_vue_map
*last_vue_map
,
3315 bool two_sided_color
,
3316 unsigned *out_offset
,
3317 unsigned *out_length
)
3319 /* The compiler computes the first URB slot without considering COL/BFC
3320 * swizzling (because it doesn't know whether it's enabled), so we need
3321 * to do that here too. This may result in a smaller offset, which
3324 const unsigned first_slot
=
3325 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3327 /* This becomes the URB read offset (counted in pairs of slots). */
3328 assert(first_slot
% 2 == 0);
3329 *out_offset
= first_slot
/ 2;
3331 /* We need to adjust the inputs read to account for front/back color
3332 * swizzling, as it can make the URB length longer.
3334 for (int c
= 0; c
<= 1; c
++) {
3335 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3336 /* If two sided color is enabled, the fragment shader's gl_Color
3337 * (COL0) input comes from either the gl_FrontColor (COL0) or
3338 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3340 if (two_sided_color
)
3341 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3343 /* If front color isn't written, we opt to give them back color
3344 * instead of an undefined value. Switch from COL to BFC.
3346 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3347 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3348 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3353 /* Compute the minimum URB Read Length necessary for the FS inputs.
3355 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3356 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3358 * "This field should be set to the minimum length required to read the
3359 * maximum source attribute. The maximum source attribute is indicated
3360 * by the maximum value of the enabled Attribute # Source Attribute if
3361 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3362 * enable is not set.
3363 * read_length = ceiling((max_source_attr + 1) / 2)
3365 * [errata] Corruption/Hang possible if length programmed larger than
3368 * Similar text exists for Ivy Bridge.
3370 * We find the last URB slot that's actually read by the FS.
3372 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3373 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3374 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3377 /* The URB read length is the difference of the two, counted in pairs. */
3378 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3382 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3383 const struct iris_context
*ice
,
3384 unsigned urb_read_offset
,
3385 unsigned sprite_coord_enables
)
3387 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3388 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3389 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3390 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3391 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3393 /* XXX: this should be generated when putting programs in place */
3395 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3396 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3397 if (input_index
< 0 || input_index
>= 16)
3400 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3401 &attr_overrides
[input_index
];
3402 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3404 /* Viewport and Layer are stored in the VUE header. We need to override
3405 * them to zero if earlier stages didn't write them, as GL requires that
3406 * they read back as zero when not explicitly set.
3409 case VARYING_SLOT_VIEWPORT
:
3410 case VARYING_SLOT_LAYER
:
3411 attr
->ComponentOverrideX
= true;
3412 attr
->ComponentOverrideW
= true;
3413 attr
->ConstantSource
= CONST_0000
;
3415 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3416 attr
->ComponentOverrideY
= true;
3417 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3418 attr
->ComponentOverrideZ
= true;
3421 case VARYING_SLOT_PRIMITIVE_ID
:
3422 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3424 attr
->ComponentOverrideX
= true;
3425 attr
->ComponentOverrideY
= true;
3426 attr
->ComponentOverrideZ
= true;
3427 attr
->ComponentOverrideW
= true;
3428 attr
->ConstantSource
= PRIM_ID
;
3436 if (sprite_coord_enables
& (1 << input_index
))
3439 /* If there was only a back color written but not front, use back
3440 * as the color instead of undefined.
3442 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3443 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3444 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3445 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3447 /* Not written by the previous stage - undefined. */
3449 attr
->ComponentOverrideX
= true;
3450 attr
->ComponentOverrideY
= true;
3451 attr
->ComponentOverrideZ
= true;
3452 attr
->ComponentOverrideW
= true;
3453 attr
->ConstantSource
= CONST_0001_FLOAT
;
3457 /* Compute the location of the attribute relative to the read offset,
3458 * which is counted in 256-bit increments (two 128-bit VUE slots).
3460 const int source_attr
= slot
- 2 * urb_read_offset
;
3461 assert(source_attr
>= 0 && source_attr
<= 32);
3462 attr
->SourceAttribute
= source_attr
;
3464 /* If we are doing two-sided color, and the VUE slot following this one
3465 * represents a back-facing color, then we need to instruct the SF unit
3466 * to do back-facing swizzling.
3468 if (cso_rast
->light_twoside
&&
3469 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3470 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3471 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3472 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3473 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3476 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3477 for (int i
= 0; i
< 16; i
++)
3478 sbes
.Attribute
[i
] = attr_overrides
[i
];
3483 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3484 const struct iris_rasterizer_state
*cso
)
3486 unsigned overrides
= 0;
3488 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3489 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3491 for (int i
= 0; i
< 8; i
++) {
3492 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3493 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3494 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3501 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3503 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3504 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3505 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3506 const struct shader_info
*fs_info
=
3507 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3509 unsigned urb_read_offset
, urb_read_length
;
3510 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3511 ice
->shaders
.last_vue_map
,
3512 cso_rast
->light_twoside
,
3513 &urb_read_offset
, &urb_read_length
);
3515 unsigned sprite_coord_overrides
=
3516 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3518 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3519 sbe
.AttributeSwizzleEnable
= true;
3520 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3521 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3522 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3523 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3524 sbe
.ForceVertexURBEntryReadOffset
= true;
3525 sbe
.ForceVertexURBEntryReadLength
= true;
3526 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3527 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3529 for (int i
= 0; i
< 32; i
++) {
3530 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3535 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3538 /* ------------------------------------------------------------------- */
3541 * Populate VS program key fields based on the current state.
3544 iris_populate_vs_key(const struct iris_context
*ice
,
3545 const struct shader_info
*info
,
3546 gl_shader_stage last_stage
,
3547 struct brw_vs_prog_key
*key
)
3549 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3551 if (info
->clip_distance_array_size
== 0 &&
3552 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3553 last_stage
== MESA_SHADER_VERTEX
)
3554 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3558 * Populate TCS program key fields based on the current state.
3561 iris_populate_tcs_key(const struct iris_context
*ice
,
3562 struct brw_tcs_prog_key
*key
)
3567 * Populate TES program key fields based on the current state.
3570 iris_populate_tes_key(const struct iris_context
*ice
,
3571 const struct shader_info
*info
,
3572 gl_shader_stage last_stage
,
3573 struct brw_tes_prog_key
*key
)
3575 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3577 if (info
->clip_distance_array_size
== 0 &&
3578 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3579 last_stage
== MESA_SHADER_TESS_EVAL
)
3580 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3584 * Populate GS program key fields based on the current state.
3587 iris_populate_gs_key(const struct iris_context
*ice
,
3588 const struct shader_info
*info
,
3589 gl_shader_stage last_stage
,
3590 struct brw_gs_prog_key
*key
)
3592 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3594 if (info
->clip_distance_array_size
== 0 &&
3595 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)) &&
3596 last_stage
== MESA_SHADER_GEOMETRY
)
3597 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3601 * Populate FS program key fields based on the current state.
3604 iris_populate_fs_key(const struct iris_context
*ice
,
3605 const struct shader_info
*info
,
3606 struct brw_wm_prog_key
*key
)
3608 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3609 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3610 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3611 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3612 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3614 key
->nr_color_regions
= fb
->nr_cbufs
;
3616 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3618 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3620 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3622 key
->flat_shade
= rast
->flatshade
&&
3623 (info
->inputs_read
& (VARYING_BIT_COL0
| VARYING_BIT_COL1
));
3625 key
->persample_interp
= rast
->force_persample_interp
;
3626 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3628 key
->coherent_fb_fetch
= GEN_GEN
>= 9;
3630 key
->force_dual_color_blend
=
3631 screen
->driconf
.dual_color_blend_by_location
&&
3632 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3634 /* TODO: Respect glHint for key->high_quality_derivatives */
3638 iris_populate_cs_key(const struct iris_context
*ice
,
3639 struct brw_cs_prog_key
*key
)
3644 KSP(const struct iris_compiled_shader
*shader
)
3646 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3647 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3650 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3651 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3652 * this WA on C0 stepping.
3654 * TODO: Fill out SamplerCount for prefetching?
3657 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3658 pkt.KernelStartPointer = KSP(shader); \
3659 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3660 shader->bt.size_bytes / 4; \
3661 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3663 pkt.DispatchGRFStartRegisterForURBData = \
3664 prog_data->dispatch_grf_start_reg; \
3665 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3666 pkt.prefix##URBEntryReadOffset = 0; \
3668 pkt.StatisticsEnable = true; \
3669 pkt.Enable = true; \
3671 if (prog_data->total_scratch) { \
3672 struct iris_bo *bo = \
3673 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3674 uint32_t scratch_addr = bo->gtt_offset; \
3675 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3676 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3680 * Encode most of 3DSTATE_VS based on the compiled shader.
3683 iris_store_vs_state(struct iris_context
*ice
,
3684 const struct gen_device_info
*devinfo
,
3685 struct iris_compiled_shader
*shader
)
3687 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3688 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3690 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3691 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3692 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3693 vs
.SIMD8DispatchEnable
= true;
3694 vs
.UserClipDistanceCullTestEnableBitmask
=
3695 vue_prog_data
->cull_distance_mask
;
3700 * Encode most of 3DSTATE_HS based on the compiled shader.
3703 iris_store_tcs_state(struct iris_context
*ice
,
3704 const struct gen_device_info
*devinfo
,
3705 struct iris_compiled_shader
*shader
)
3707 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3708 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3709 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3711 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3712 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3714 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3715 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3716 hs
.IncludeVertexHandles
= true;
3719 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3720 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3726 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3729 iris_store_tes_state(struct iris_context
*ice
,
3730 const struct gen_device_info
*devinfo
,
3731 struct iris_compiled_shader
*shader
)
3733 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3734 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3735 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3737 uint32_t *te_state
= (void *) shader
->derived_data
;
3738 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3740 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3741 te
.Partitioning
= tes_prog_data
->partitioning
;
3742 te
.OutputTopology
= tes_prog_data
->output_topology
;
3743 te
.TEDomain
= tes_prog_data
->domain
;
3745 te
.MaximumTessellationFactorOdd
= 63.0;
3746 te
.MaximumTessellationFactorNotOdd
= 64.0;
3749 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3750 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3752 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3753 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3754 ds
.ComputeWCoordinateEnable
=
3755 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3757 ds
.UserClipDistanceCullTestEnableBitmask
=
3758 vue_prog_data
->cull_distance_mask
;
3764 * Encode most of 3DSTATE_GS based on the compiled shader.
3767 iris_store_gs_state(struct iris_context
*ice
,
3768 const struct gen_device_info
*devinfo
,
3769 struct iris_compiled_shader
*shader
)
3771 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3772 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3773 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3775 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3776 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3778 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3779 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3780 gs
.ControlDataHeaderSize
=
3781 gs_prog_data
->control_data_header_size_hwords
;
3782 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3783 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3784 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3785 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3786 gs
.ReorderMode
= TRAILING
;
3787 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3788 gs
.MaximumNumberofThreads
=
3789 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3790 : (devinfo
->max_gs_threads
- 1);
3792 if (gs_prog_data
->static_vertex_count
!= -1) {
3793 gs
.StaticOutput
= true;
3794 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3796 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3798 gs
.UserClipDistanceCullTestEnableBitmask
=
3799 vue_prog_data
->cull_distance_mask
;
3801 const int urb_entry_write_offset
= 1;
3802 const uint32_t urb_entry_output_length
=
3803 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3804 urb_entry_write_offset
;
3806 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3807 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3812 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3815 iris_store_fs_state(struct iris_context
*ice
,
3816 const struct gen_device_info
*devinfo
,
3817 struct iris_compiled_shader
*shader
)
3819 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3820 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3822 uint32_t *ps_state
= (void *) shader
->derived_data
;
3823 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3825 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3826 ps
.VectorMaskEnable
= true;
3827 // XXX: WABTPPrefetchDisable, see above, drop at C0
3828 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3829 shader
->bt
.size_bytes
/ 4;
3830 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3831 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3833 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3835 /* From the documentation for this packet:
3836 * "If the PS kernel does not need the Position XY Offsets to
3837 * compute a Position Value, then this field should be programmed
3838 * to POSOFFSET_NONE."
3840 * "SW Recommendation: If the PS kernel needs the Position Offsets
3841 * to compute a Position XY value, this field should match Position
3842 * ZW Interpolation Mode to ensure a consistent position.xyzw
3845 * We only require XY sample offsets. So, this recommendation doesn't
3846 * look useful at the moment. We might need this in future.
3848 ps
.PositionXYOffsetSelect
=
3849 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3851 if (prog_data
->total_scratch
) {
3852 struct iris_bo
*bo
=
3853 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3854 MESA_SHADER_FRAGMENT
);
3855 uint32_t scratch_addr
= bo
->gtt_offset
;
3856 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3857 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3861 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3862 psx
.PixelShaderValid
= true;
3863 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3864 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3865 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3866 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3867 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3868 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3869 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3872 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3873 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3879 * Compute the size of the derived data (shader command packets).
3881 * This must match the data written by the iris_store_xs_state() functions.
3884 iris_store_cs_state(struct iris_context
*ice
,
3885 const struct gen_device_info
*devinfo
,
3886 struct iris_compiled_shader
*shader
)
3888 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3889 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3890 void *map
= shader
->derived_data
;
3892 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3893 desc
.KernelStartPointer
= KSP(shader
);
3894 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3895 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3896 desc
.SharedLocalMemorySize
=
3897 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3898 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3899 desc
.CrossThreadConstantDataReadLength
=
3900 cs_prog_data
->push
.cross_thread
.regs
;
3905 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3907 assert(cache_id
<= IRIS_CACHE_BLORP
);
3909 static const unsigned dwords
[] = {
3910 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3911 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3912 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3913 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3915 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3916 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3917 [IRIS_CACHE_BLORP
] = 0,
3920 return sizeof(uint32_t) * dwords
[cache_id
];
3924 * Create any state packets corresponding to the given shader stage
3925 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3926 * This means that we can look up a program in the in-memory cache and
3927 * get most of the state packet without having to reconstruct it.
3930 iris_store_derived_program_state(struct iris_context
*ice
,
3931 enum iris_program_cache_id cache_id
,
3932 struct iris_compiled_shader
*shader
)
3934 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3935 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3939 iris_store_vs_state(ice
, devinfo
, shader
);
3941 case IRIS_CACHE_TCS
:
3942 iris_store_tcs_state(ice
, devinfo
, shader
);
3944 case IRIS_CACHE_TES
:
3945 iris_store_tes_state(ice
, devinfo
, shader
);
3948 iris_store_gs_state(ice
, devinfo
, shader
);
3951 iris_store_fs_state(ice
, devinfo
, shader
);
3954 iris_store_cs_state(ice
, devinfo
, shader
);
3955 case IRIS_CACHE_BLORP
:
3962 /* ------------------------------------------------------------------- */
3964 static const uint32_t push_constant_opcodes
[] = {
3965 [MESA_SHADER_VERTEX
] = 21,
3966 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3967 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3968 [MESA_SHADER_GEOMETRY
] = 22,
3969 [MESA_SHADER_FRAGMENT
] = 23,
3970 [MESA_SHADER_COMPUTE
] = 0,
3974 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3976 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3978 iris_use_pinned_bo(batch
, state_bo
, false);
3980 return ice
->state
.unbound_tex
.offset
;
3984 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3986 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3987 if (!ice
->state
.null_fb
.res
)
3988 return use_null_surface(batch
, ice
);
3990 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3992 iris_use_pinned_bo(batch
, state_bo
, false);
3994 return ice
->state
.null_fb
.offset
;
3998 surf_state_offset_for_aux(struct iris_resource
*res
,
4000 enum isl_aux_usage aux_usage
)
4002 return SURFACE_STATE_ALIGNMENT
*
4003 util_bitcount(aux_modes
& ((1 << aux_usage
) - 1));
4007 surf_state_update_clear_value(struct iris_batch
*batch
,
4008 struct iris_resource
*res
,
4009 struct iris_state_ref
*state
,
4011 enum isl_aux_usage aux_usage
)
4013 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4014 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
4015 uint64_t real_offset
= state
->offset
+ IRIS_MEMZONE_BINDER_START
;
4016 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
4017 uint32_t clear_offset
= offset_into_bo
+
4018 isl_dev
->ss
.clear_value_offset
+
4019 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
4020 uint32_t *color
= res
->aux
.clear_color
.u32
;
4022 assert(isl_dev
->ss
.clear_value_size
== 16);
4024 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
4025 iris_emit_pipe_control_write(batch
, "update fast clear value (Z)",
4026 PIPE_CONTROL_WRITE_IMMEDIATE
,
4027 state_bo
, clear_offset
, color
[0]);
4029 iris_emit_pipe_control_write(batch
, "update fast clear color (RG__)",
4030 PIPE_CONTROL_WRITE_IMMEDIATE
,
4031 state_bo
, clear_offset
,
4032 (uint64_t) color
[0] |
4033 (uint64_t) color
[1] << 32);
4034 iris_emit_pipe_control_write(batch
, "update fast clear color (__BA)",
4035 PIPE_CONTROL_WRITE_IMMEDIATE
,
4036 state_bo
, clear_offset
+ 8,
4037 (uint64_t) color
[2] |
4038 (uint64_t) color
[3] << 32);
4041 iris_emit_pipe_control_flush(batch
,
4042 "update fast clear: state cache invalidate",
4043 PIPE_CONTROL_FLUSH_ENABLE
|
4044 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
4048 update_clear_value(struct iris_context
*ice
,
4049 struct iris_batch
*batch
,
4050 struct iris_resource
*res
,
4051 struct iris_state_ref
*state
,
4052 unsigned all_aux_modes
,
4053 struct isl_view
*view
)
4055 UNUSED
struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
4056 UNUSED
unsigned aux_modes
= all_aux_modes
;
4058 /* We only need to update the clear color in the surface state for gen8 and
4059 * gen9. Newer gens can read it directly from the clear color state buffer.
4062 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
4063 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
4066 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4068 surf_state_update_clear_value(batch
, res
, state
, all_aux_modes
,
4072 pipe_resource_reference(&state
->res
, NULL
);
4074 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
4075 state
, all_aux_modes
);
4077 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
4078 fill_surface_state(isl_dev
, map
, res
, &res
->surf
, view
, aux_usage
, 0, 0);
4079 map
+= SURFACE_STATE_ALIGNMENT
;
4085 * Add a surface to the validation list, as well as the buffer containing
4086 * the corresponding SURFACE_STATE.
4088 * Returns the binding table entry (offset to SURFACE_STATE).
4091 use_surface(struct iris_context
*ice
,
4092 struct iris_batch
*batch
,
4093 struct pipe_surface
*p_surf
,
4095 enum isl_aux_usage aux_usage
,
4096 bool is_read_surface
)
4098 struct iris_surface
*surf
= (void *) p_surf
;
4099 struct iris_resource
*res
= (void *) p_surf
->texture
;
4100 uint32_t offset
= 0;
4102 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
4103 if (GEN_GEN
== 8 && is_read_surface
) {
4104 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state_read
.res
), false);
4106 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
4110 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
4111 if (res
->aux
.clear_color_bo
)
4112 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
4114 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
4115 sizeof(surf
->clear_color
)) != 0) {
4116 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
4117 res
->aux
.possible_usages
, &surf
->view
);
4119 update_clear_value(ice
, batch
, res
, &surf
->surface_state_read
,
4120 res
->aux
.possible_usages
, &surf
->read_view
);
4122 surf
->clear_color
= res
->aux
.clear_color
;
4126 offset
= (GEN_GEN
== 8 && is_read_surface
) ? surf
->surface_state_read
.offset
4127 : surf
->surface_state
.offset
;
4130 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
4134 use_sampler_view(struct iris_context
*ice
,
4135 struct iris_batch
*batch
,
4136 struct iris_sampler_view
*isv
)
4139 enum isl_aux_usage aux_usage
=
4140 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
4142 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
4143 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
4145 if (isv
->res
->aux
.bo
) {
4146 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
4147 if (isv
->res
->aux
.clear_color_bo
)
4148 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
4149 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
4150 sizeof(isv
->clear_color
)) != 0) {
4151 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
4152 isv
->res
->aux
.sampler_usages
, &isv
->view
);
4153 isv
->clear_color
= isv
->res
->aux
.clear_color
;
4157 return isv
->surface_state
.offset
+
4158 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
4163 use_ubo_ssbo(struct iris_batch
*batch
,
4164 struct iris_context
*ice
,
4165 struct pipe_shader_buffer
*buf
,
4166 struct iris_state_ref
*surf_state
,
4170 return use_null_surface(batch
, ice
);
4172 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4173 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4175 return surf_state
->offset
;
4179 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4180 struct iris_shader_state
*shs
, int i
)
4182 struct iris_image_view
*iv
= &shs
->image
[i
];
4183 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4186 return use_null_surface(batch
, ice
);
4188 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4190 iris_use_pinned_bo(batch
, res
->bo
, write
);
4191 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4194 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4196 return iv
->surface_state
.offset
;
4199 #define push_bt_entry(addr) \
4200 assert(addr >= binder_addr); \
4201 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4202 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4204 #define bt_assert(section) \
4205 if (!pin_only && shader->bt.used_mask[section] != 0) \
4206 assert(shader->bt.offsets[section] == s);
4209 * Populate the binding table for a given shader stage.
4211 * This fills out the table of pointers to surfaces required by the shader,
4212 * and also adds those buffers to the validation list so the kernel can make
4213 * resident before running our batch.
4216 iris_populate_binding_table(struct iris_context
*ice
,
4217 struct iris_batch
*batch
,
4218 gl_shader_stage stage
,
4221 const struct iris_binder
*binder
= &ice
->state
.binder
;
4222 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4223 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4227 struct iris_binding_table
*bt
= &shader
->bt
;
4228 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4229 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4230 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4232 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4235 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4237 /* TCS passthrough doesn't need a binding table. */
4238 assert(stage
== MESA_SHADER_TESS_CTRL
);
4242 if (stage
== MESA_SHADER_COMPUTE
&&
4243 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4244 /* surface for gl_NumWorkGroups */
4245 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4246 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4247 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4248 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4249 push_bt_entry(grid_state
->offset
);
4252 if (stage
== MESA_SHADER_FRAGMENT
) {
4253 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4254 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4255 if (cso_fb
->nr_cbufs
) {
4256 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4258 if (cso_fb
->cbufs
[i
]) {
4259 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4260 ice
->state
.draw_aux_usage
[i
], false);
4262 addr
= use_null_fb_surface(batch
, ice
);
4264 push_bt_entry(addr
);
4267 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4268 push_bt_entry(addr
);
4272 #define foreach_surface_used(index, group) \
4274 for (int index = 0; index < bt->sizes[group]; index++) \
4275 if (iris_group_index_to_bti(bt, group, index) != \
4276 IRIS_SURFACE_NOT_USED)
4278 foreach_surface_used(i
, IRIS_SURFACE_GROUP_RENDER_TARGET_READ
) {
4279 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4281 if (cso_fb
->cbufs
[i
]) {
4282 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
],
4283 true, ice
->state
.draw_aux_usage
[i
], true);
4284 push_bt_entry(addr
);
4288 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4289 struct iris_sampler_view
*view
= shs
->textures
[i
];
4290 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4291 : use_null_surface(batch
, ice
);
4292 push_bt_entry(addr
);
4295 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4296 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4297 push_bt_entry(addr
);
4300 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4303 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4304 if (ish
->const_data
) {
4305 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4306 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4308 addr
= ish
->const_data_state
.offset
;
4310 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4311 addr
= use_null_surface(batch
, ice
);
4314 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4315 &shs
->constbuf_surf_state
[i
], false);
4318 push_bt_entry(addr
);
4321 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4323 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4324 shs
->writable_ssbos
& (1u << i
));
4325 push_bt_entry(addr
);
4329 /* XXX: YUV surfaces not implemented yet */
4330 bt_assert(plane_start
[1], ...);
4331 bt_assert(plane_start
[2], ...);
4336 iris_use_optional_res(struct iris_batch
*batch
,
4337 struct pipe_resource
*res
,
4341 struct iris_bo
*bo
= iris_resource_bo(res
);
4342 iris_use_pinned_bo(batch
, bo
, writeable
);
4347 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4348 struct pipe_surface
*zsbuf
,
4349 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4354 struct iris_resource
*zres
, *sres
;
4355 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4358 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4360 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4361 cso_zsa
->depth_writes_enabled
);
4366 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4370 /* ------------------------------------------------------------------- */
4373 * Pin any BOs which were installed by a previous batch, and restored
4374 * via the hardware logical context mechanism.
4376 * We don't need to re-emit all state every batch - the hardware context
4377 * mechanism will save and restore it for us. This includes pointers to
4378 * various BOs...which won't exist unless we ask the kernel to pin them
4379 * by adding them to the validation list.
4381 * We can skip buffers if we've re-emitted those packets, as we're
4382 * overwriting those stale pointers with new ones, and don't actually
4383 * refer to the old BOs.
4386 iris_restore_render_saved_bos(struct iris_context
*ice
,
4387 struct iris_batch
*batch
,
4388 const struct pipe_draw_info
*draw
)
4390 struct iris_genx_state
*genx
= ice
->state
.genx
;
4392 const uint64_t clean
= ~ice
->state
.dirty
;
4394 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4395 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4398 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4399 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4402 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4403 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4406 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4407 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4410 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4411 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4414 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4415 for (int i
= 0; i
< 4; i
++) {
4416 struct iris_stream_output_target
*tgt
=
4417 (void *) ice
->state
.so_target
[i
];
4419 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4421 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4427 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4428 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4431 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4432 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4437 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4439 for (int i
= 0; i
< 4; i
++) {
4440 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4442 if (range
->length
== 0)
4445 /* Range block is a binding table index, map back to UBO index. */
4446 unsigned block_index
= iris_bti_to_group_index(
4447 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4448 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4450 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4451 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4454 iris_use_pinned_bo(batch
, res
->bo
, false);
4456 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4460 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4461 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4462 /* Re-pin any buffers referred to by the binding table. */
4463 iris_populate_binding_table(ice
, batch
, stage
, true);
4467 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4468 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4469 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4471 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4474 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4475 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4476 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4479 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4480 iris_use_pinned_bo(batch
, bo
, false);
4482 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4484 if (prog_data
->total_scratch
> 0) {
4485 struct iris_bo
*bo
=
4486 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4487 iris_use_pinned_bo(batch
, bo
, true);
4493 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4494 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4495 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4496 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4499 iris_use_optional_res(batch
, ice
->state
.last_res
.index_buffer
, false);
4501 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4502 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4504 const int i
= u_bit_scan64(&bound
);
4505 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4506 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4512 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4513 struct iris_batch
*batch
,
4514 const struct pipe_grid_info
*grid
)
4516 const uint64_t clean
= ~ice
->state
.dirty
;
4518 const int stage
= MESA_SHADER_COMPUTE
;
4519 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4521 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4522 /* Re-pin any buffers referred to by the binding table. */
4523 iris_populate_binding_table(ice
, batch
, stage
, true);
4526 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4528 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4530 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4531 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4532 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4533 (clean
& IRIS_DIRTY_CS
)) {
4534 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4537 if (clean
& IRIS_DIRTY_CS
) {
4538 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4541 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4542 iris_use_pinned_bo(batch
, bo
, false);
4544 struct iris_bo
*curbe_bo
=
4545 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4546 iris_use_pinned_bo(batch
, curbe_bo
, false);
4548 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4550 if (prog_data
->total_scratch
> 0) {
4551 struct iris_bo
*bo
=
4552 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4553 iris_use_pinned_bo(batch
, bo
, true);
4560 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4563 iris_update_surface_base_address(struct iris_batch
*batch
,
4564 struct iris_binder
*binder
)
4566 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4569 flush_for_state_base_change(batch
);
4571 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4572 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4573 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4575 /* The hardware appears to pay attention to the MOCS fields even
4576 * if you don't set the "Address Modify Enable" bit for the base.
4578 sba
.GeneralStateMOCS
= MOCS_WB
;
4579 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
4580 sba
.DynamicStateMOCS
= MOCS_WB
;
4581 sba
.IndirectObjectMOCS
= MOCS_WB
;
4582 sba
.InstructionMOCS
= MOCS_WB
;
4583 sba
.SurfaceStateMOCS
= MOCS_WB
;
4585 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
4589 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4593 iris_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
4594 bool window_space_position
, float *zmin
, float *zmax
)
4596 if (window_space_position
) {
4601 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
4605 iris_upload_dirty_render_state(struct iris_context
*ice
,
4606 struct iris_batch
*batch
,
4607 const struct pipe_draw_info
*draw
)
4609 const uint64_t dirty
= ice
->state
.dirty
;
4611 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4614 struct iris_genx_state
*genx
= ice
->state
.genx
;
4615 struct iris_binder
*binder
= &ice
->state
.binder
;
4616 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4617 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4619 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4620 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4621 uint32_t cc_vp_address
;
4623 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4624 uint32_t *cc_vp_map
=
4625 stream_state(batch
, ice
->state
.dynamic_uploader
,
4626 &ice
->state
.last_res
.cc_vp
,
4627 4 * ice
->state
.num_viewports
*
4628 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4629 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4631 iris_viewport_zmin_zmax(&ice
->state
.viewports
[i
], cso_rast
->clip_halfz
,
4632 ice
->state
.window_space_position
,
4634 if (cso_rast
->depth_clip_near
)
4636 if (cso_rast
->depth_clip_far
)
4639 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4640 ccv
.MinimumDepth
= zmin
;
4641 ccv
.MaximumDepth
= zmax
;
4644 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4647 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4648 ptr
.CCViewportPointer
= cc_vp_address
;
4652 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4653 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4654 uint32_t sf_cl_vp_address
;
4656 stream_state(batch
, ice
->state
.dynamic_uploader
,
4657 &ice
->state
.last_res
.sf_cl_vp
,
4658 4 * ice
->state
.num_viewports
*
4659 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4661 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4662 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4663 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4665 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4666 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4667 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4668 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4670 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4671 state
->scale
[0], state
->scale
[1],
4672 state
->translate
[0], state
->translate
[1],
4673 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4675 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4676 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4677 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4678 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4679 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4680 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4681 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4682 vp
.XMinClipGuardband
= gb_xmin
;
4683 vp
.XMaxClipGuardband
= gb_xmax
;
4684 vp
.YMinClipGuardband
= gb_ymin
;
4685 vp
.YMaxClipGuardband
= gb_ymax
;
4686 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4687 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4688 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4689 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4692 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4695 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4696 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4700 if (dirty
& IRIS_DIRTY_URB
) {
4703 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4704 if (!ice
->shaders
.prog
[i
]) {
4707 struct brw_vue_prog_data
*vue_prog_data
=
4708 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4709 size
[i
] = vue_prog_data
->urb_entry_size
;
4711 assert(size
[i
] != 0);
4714 genX(emit_urb_setup
)(ice
, batch
, size
,
4715 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4716 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4719 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4720 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4721 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4722 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4723 const int header_dwords
= GENX(BLEND_STATE_length
);
4725 /* Always write at least one BLEND_STATE - the final RT message will
4726 * reference BLEND_STATE[0] even if there aren't color writes. There
4727 * may still be alpha testing, computed depth, and so on.
4729 const int rt_dwords
=
4730 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4732 uint32_t blend_offset
;
4733 uint32_t *blend_map
=
4734 stream_state(batch
, ice
->state
.dynamic_uploader
,
4735 &ice
->state
.last_res
.blend
,
4736 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4738 uint32_t blend_state_header
;
4739 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4740 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4741 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4744 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4745 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4747 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4748 ptr
.BlendStatePointer
= blend_offset
;
4749 ptr
.BlendStatePointerValid
= true;
4753 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4754 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4756 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4760 stream_state(batch
, ice
->state
.dynamic_uploader
,
4761 &ice
->state
.last_res
.color_calc
,
4762 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4764 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4765 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4766 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4767 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4768 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4769 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4770 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4772 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4773 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4776 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4777 ptr
.ColorCalcStatePointer
= cc_offset
;
4778 ptr
.ColorCalcStatePointerValid
= true;
4782 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4783 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4786 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4787 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4792 if (shs
->sysvals_need_upload
)
4793 upload_sysvals(ice
, stage
);
4795 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4797 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4798 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4800 /* The Skylake PRM contains the following restriction:
4802 * "The driver must ensure The following case does not occur
4803 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4804 * buffer 3 read length equal to zero committed followed by a
4805 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4808 * To avoid this, we program the buffers in the highest slots.
4809 * This way, slot 0 is only used if slot 3 is also used.
4813 for (int i
= 3; i
>= 0; i
--) {
4814 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4816 if (range
->length
== 0)
4819 /* Range block is a binding table index, map back to UBO index. */
4820 unsigned block_index
= iris_bti_to_group_index(
4821 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4822 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4824 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4825 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4827 assert(cbuf
->buffer_offset
% 32 == 0);
4829 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4830 pkt
.ConstantBody
.Buffer
[n
] =
4831 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4832 : ro_bo(batch
->screen
->workaround_bo
, 0);
4839 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4840 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4841 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4842 ptr
._3DCommandSubOpcode
= 38 + stage
;
4843 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4848 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4849 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4850 iris_populate_binding_table(ice
, batch
, stage
, false);
4854 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4855 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4856 !ice
->shaders
.prog
[stage
])
4859 iris_upload_sampler_states(ice
, stage
);
4861 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4862 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4864 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4866 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4867 ptr
._3DCommandSubOpcode
= 43 + stage
;
4868 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4872 if (ice
->state
.need_border_colors
)
4873 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4875 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4876 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4878 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4879 if (ice
->state
.framebuffer
.samples
> 0)
4880 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4884 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4885 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4886 ms
.SampleMask
= ice
->state
.sample_mask
;
4890 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4891 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4894 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4897 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4898 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4899 iris_use_pinned_bo(batch
, cache
->bo
, false);
4901 if (prog_data
->total_scratch
> 0) {
4902 struct iris_bo
*bo
=
4903 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4904 iris_use_pinned_bo(batch
, bo
, true);
4907 if (stage
== MESA_SHADER_FRAGMENT
) {
4908 UNUSED
struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4909 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4911 uint32_t ps_state
[GENX(3DSTATE_PS_length
)] = {0};
4912 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
4913 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
4914 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
4915 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
4917 /* The docs for 3DSTATE_PS::32 Pixel Dispatch Enable say:
4919 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16,
4920 * SIMD32 Dispatch must not be enabled for PER_PIXEL dispatch
4923 * 16x MSAA only exists on Gen9+, so we can skip this on Gen8.
4925 if (GEN_GEN
>= 9 && cso_fb
->samples
== 16 &&
4926 !wm_prog_data
->persample_dispatch
) {
4927 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
4928 ps
._32PixelDispatchEnable
= false;
4931 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
4932 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
4933 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
4934 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
4935 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
4936 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
4938 ps
.KernelStartPointer0
= KSP(shader
) +
4939 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
4940 ps
.KernelStartPointer1
= KSP(shader
) +
4941 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
4942 ps
.KernelStartPointer2
= KSP(shader
) +
4943 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
4946 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4947 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
4949 if (!wm_prog_data
->uses_sample_mask
)
4950 psx
.InputCoverageMaskState
= ICMS_NONE
;
4951 else if (wm_prog_data
->post_depth_coverage
)
4952 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4953 else if (wm_prog_data
->inner_coverage
&&
4954 cso
->conservative_rasterization
)
4955 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4957 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4959 psx
.PixelShaderUsesInputCoverageMask
=
4960 wm_prog_data
->uses_sample_mask
;
4964 uint32_t *shader_ps
= (uint32_t *) shader
->derived_data
;
4965 uint32_t *shader_psx
= shader_ps
+ GENX(3DSTATE_PS_length
);
4966 iris_emit_merge(batch
, shader_ps
, ps_state
,
4967 GENX(3DSTATE_PS_length
));
4968 iris_emit_merge(batch
, shader_psx
, psx_state
,
4969 GENX(3DSTATE_PS_EXTRA_length
));
4971 iris_batch_emit(batch
, shader
->derived_data
,
4972 iris_derived_program_state_size(stage
));
4975 if (stage
== MESA_SHADER_TESS_EVAL
) {
4976 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4977 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4978 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4979 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4980 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4985 if (ice
->state
.streamout_active
) {
4986 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4987 iris_batch_emit(batch
, genx
->so_buffers
,
4988 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4989 for (int i
= 0; i
< 4; i
++) {
4990 struct iris_stream_output_target
*tgt
=
4991 (void *) ice
->state
.so_target
[i
];
4994 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4996 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
5002 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
5003 uint32_t *decl_list
=
5004 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
5005 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
5008 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5009 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5011 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
5012 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
5013 sol
.SOFunctionEnable
= true;
5014 sol
.SOStatisticsEnable
= true;
5016 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
5017 !ice
->state
.prims_generated_query_active
;
5018 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
5021 assert(ice
->state
.streamout
);
5023 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
5024 GENX(3DSTATE_STREAMOUT_length
));
5027 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
5028 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
5032 if (dirty
& IRIS_DIRTY_CLIP
) {
5033 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
5034 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5036 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
5037 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
5038 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
5039 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
5040 : ice
->state
.prim_is_points_or_lines
);
5042 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
5043 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
5044 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5045 if (cso_rast
->rasterizer_discard
)
5046 cl
.ClipMode
= CLIPMODE_REJECT_ALL
;
5047 else if (ice
->state
.window_space_position
)
5048 cl
.ClipMode
= CLIPMODE_ACCEPT_ALL
;
5050 cl
.ClipMode
= CLIPMODE_NORMAL
;
5052 cl
.PerspectiveDivideDisable
= ice
->state
.window_space_position
;
5053 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
5055 if (wm_prog_data
->barycentric_interp_modes
&
5056 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
5057 cl
.NonPerspectiveBarycentricEnable
= true;
5059 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
5060 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
5062 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
5063 ARRAY_SIZE(cso_rast
->clip
));
5066 if (dirty
& IRIS_DIRTY_RASTER
) {
5067 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5068 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
5070 uint32_t dynamic_sf
[GENX(3DSTATE_SF_length
)];
5071 iris_pack_command(GENX(3DSTATE_SF
), &dynamic_sf
, sf
) {
5072 sf
.ViewportTransformEnable
= !ice
->state
.window_space_position
;
5074 iris_emit_merge(batch
, cso
->sf
, dynamic_sf
,
5075 ARRAY_SIZE(dynamic_sf
));
5078 if (dirty
& IRIS_DIRTY_WM
) {
5079 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5080 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
5082 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
5083 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
5085 wm
.BarycentricInterpolationMode
=
5086 wm_prog_data
->barycentric_interp_modes
;
5088 if (wm_prog_data
->early_fragment_tests
)
5089 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
5090 else if (wm_prog_data
->has_side_effects
)
5091 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
5093 /* We could skip this bit if color writes are enabled. */
5094 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
5095 wm
.ForceThreadDispatchEnable
= ForceON
;
5097 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
5100 if (dirty
& IRIS_DIRTY_SBE
) {
5101 iris_emit_sbe(batch
, ice
);
5104 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
5105 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
5106 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
5107 const struct shader_info
*fs_info
=
5108 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
5110 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
5111 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
5112 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
5113 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
5115 /* The dual source blending docs caution against using SRC1 factors
5116 * when the shader doesn't use a dual source render target write.
5117 * Empirically, this can lead to GPU hangs, and the results are
5118 * undefined anyway, so simply disable blending to avoid the hang.
5120 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
5121 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
5124 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
5125 ARRAY_SIZE(cso_blend
->ps_blend
));
5128 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
5129 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
5131 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
5132 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
5133 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
5134 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
5135 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
5137 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
5139 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
5143 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
5144 uint32_t scissor_offset
=
5145 emit_state(batch
, ice
->state
.dynamic_uploader
,
5146 &ice
->state
.last_res
.scissor
,
5147 ice
->state
.scissors
,
5148 sizeof(struct pipe_scissor_state
) *
5149 ice
->state
.num_viewports
, 32);
5151 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
5152 ptr
.ScissorRectPointer
= scissor_offset
;
5156 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
5157 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
5159 /* Do not emit the clear params yets. We need to update the clear value
5162 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
5163 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
5164 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
5166 union isl_color_value clear_value
= { .f32
= { 0, } };
5168 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5169 if (cso_fb
->zsbuf
) {
5170 struct iris_resource
*zres
, *sres
;
5171 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
5173 if (zres
&& zres
->aux
.bo
)
5174 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
5177 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
5178 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
5179 clear
.DepthClearValueValid
= true;
5180 clear
.DepthClearValue
= clear_value
.f32
[0];
5182 iris_batch_emit(batch
, clear_params
, clear_length
);
5185 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
5186 /* Listen for buffer changes, and also write enable changes. */
5187 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
5188 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
5191 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
5192 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
5193 for (int i
= 0; i
< 32; i
++) {
5194 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
5199 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
5200 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
5201 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
5204 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
5205 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
5206 topo
.PrimitiveTopologyType
=
5207 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
5211 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
5212 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
5213 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
5215 if (ice
->state
.vs_uses_draw_params
) {
5216 if (ice
->draw
.draw_params_offset
== 0) {
5217 u_upload_data(ice
->ctx
.stream_uploader
, 0, sizeof(ice
->draw
.params
),
5218 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
5219 &ice
->draw
.draw_params_res
);
5221 assert(ice
->draw
.draw_params_res
);
5223 struct iris_vertex_buffer_state
*state
=
5224 &(ice
->state
.genx
->vertex_buffers
[count
]);
5225 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
5226 struct iris_resource
*res
= (void *) state
->resource
;
5228 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5229 vb
.VertexBufferIndex
= count
;
5230 vb
.AddressModifyEnable
= true;
5232 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
5233 vb
.BufferStartingAddress
=
5234 ro_bo(NULL
, res
->bo
->gtt_offset
+
5235 (int) ice
->draw
.draw_params_offset
);
5236 vb
.MOCS
= mocs(res
->bo
);
5238 dynamic_bound
|= 1ull << count
;
5242 if (ice
->state
.vs_uses_derived_draw_params
) {
5243 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5244 sizeof(ice
->draw
.derived_params
), 4,
5245 &ice
->draw
.derived_params
,
5246 &ice
->draw
.derived_draw_params_offset
,
5247 &ice
->draw
.derived_draw_params_res
);
5249 struct iris_vertex_buffer_state
*state
=
5250 &(ice
->state
.genx
->vertex_buffers
[count
]);
5251 pipe_resource_reference(&state
->resource
,
5252 ice
->draw
.derived_draw_params_res
);
5253 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
5255 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5256 vb
.VertexBufferIndex
= count
;
5257 vb
.AddressModifyEnable
= true;
5260 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
5261 vb
.BufferStartingAddress
=
5262 ro_bo(NULL
, res
->bo
->gtt_offset
+
5263 (int) ice
->draw
.derived_draw_params_offset
);
5264 vb
.MOCS
= mocs(res
->bo
);
5266 dynamic_bound
|= 1ull << count
;
5271 /* The VF cache designers cut corners, and made the cache key's
5272 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5273 * 32 bits of the address. If you have two vertex buffers which get
5274 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5275 * you can get collisions (even within a single batch).
5277 * So, we need to do a VF cache invalidate if the buffer for a VB
5278 * slot slot changes [48:32] address bits from the previous time.
5280 unsigned flush_flags
= 0;
5282 uint64_t bound
= dynamic_bound
;
5284 const int i
= u_bit_scan64(&bound
);
5285 uint16_t high_bits
= 0;
5287 struct iris_resource
*res
=
5288 (void *) genx
->vertex_buffers
[i
].resource
;
5290 iris_use_pinned_bo(batch
, res
->bo
, false);
5292 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5293 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5294 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5295 PIPE_CONTROL_CS_STALL
;
5296 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5302 iris_emit_pipe_control_flush(batch
,
5303 "workaround: VF cache 32-bit key [VB]",
5307 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5310 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5311 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5312 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5316 bound
= dynamic_bound
;
5318 const int i
= u_bit_scan64(&bound
);
5319 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5320 sizeof(uint32_t) * vb_dwords
);
5326 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5327 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5328 const unsigned entries
= MAX2(cso
->count
, 1);
5329 if (!(ice
->state
.vs_needs_sgvs_element
||
5330 ice
->state
.vs_uses_derived_draw_params
||
5331 ice
->state
.vs_needs_edge_flag
)) {
5332 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5333 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5335 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5336 const unsigned dyn_count
= cso
->count
+
5337 ice
->state
.vs_needs_sgvs_element
+
5338 ice
->state
.vs_uses_derived_draw_params
;
5340 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5343 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5345 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5346 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5347 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5348 uint32_t *ve_pack_dest
=
5349 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5350 GENX(VERTEX_ELEMENT_STATE_length
)];
5352 if (ice
->state
.vs_needs_sgvs_element
) {
5353 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5354 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5355 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5357 ve
.VertexBufferIndex
=
5358 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5359 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5360 ve
.Component0Control
= base_ctrl
;
5361 ve
.Component1Control
= base_ctrl
;
5362 ve
.Component2Control
= VFCOMP_STORE_0
;
5363 ve
.Component3Control
= VFCOMP_STORE_0
;
5365 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5367 if (ice
->state
.vs_uses_derived_draw_params
) {
5368 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5370 ve
.VertexBufferIndex
=
5371 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5372 ice
->state
.vs_uses_draw_params
;
5373 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5374 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5375 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5376 ve
.Component2Control
= VFCOMP_STORE_0
;
5377 ve
.Component3Control
= VFCOMP_STORE_0
;
5379 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5381 if (ice
->state
.vs_needs_edge_flag
) {
5382 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5383 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5386 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5387 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5390 if (!ice
->state
.vs_needs_edge_flag
) {
5391 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5392 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5394 assert(cso
->count
> 0);
5395 const unsigned edgeflag_index
= cso
->count
- 1;
5396 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5397 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5398 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5400 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5401 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5402 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5403 vi
.VertexElementIndex
= edgeflag_index
+
5404 ice
->state
.vs_needs_sgvs_element
+
5405 ice
->state
.vs_uses_derived_draw_params
;
5407 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5408 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5410 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5411 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5415 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5416 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5417 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5418 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5420 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5421 if (vs_prog_data
->uses_vertexid
) {
5422 sgv
.VertexIDEnable
= true;
5423 sgv
.VertexIDComponentNumber
= 2;
5424 sgv
.VertexIDElementOffset
=
5425 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5428 if (vs_prog_data
->uses_instanceid
) {
5429 sgv
.InstanceIDEnable
= true;
5430 sgv
.InstanceIDComponentNumber
= 3;
5431 sgv
.InstanceIDElementOffset
=
5432 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5437 if (dirty
& IRIS_DIRTY_VF
) {
5438 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5439 if (draw
->primitive_restart
) {
5440 vf
.IndexedDrawCutIndexEnable
= true;
5441 vf
.CutIndex
= draw
->restart_index
;
5446 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5447 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5448 vf
.StatisticsEnable
= true;
5452 if (ice
->state
.current_hash_scale
!= 1)
5453 genX(emit_hashing_mode
)(ice
, batch
, UINT_MAX
, UINT_MAX
, 1);
5455 /* TODO: Gen8 PMA fix */
5459 iris_upload_render_state(struct iris_context
*ice
,
5460 struct iris_batch
*batch
,
5461 const struct pipe_draw_info
*draw
)
5463 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5465 /* Always pin the binder. If we're emitting new binding table pointers,
5466 * we need it. If not, we're probably inheriting old tables via the
5467 * context, and need it anyway. Since true zero-bindings cases are
5468 * practically non-existent, just pin it and avoid last_res tracking.
5470 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5472 if (!batch
->contains_draw
) {
5473 iris_restore_render_saved_bos(ice
, batch
, draw
);
5474 batch
->contains_draw
= true;
5477 iris_upload_dirty_render_state(ice
, batch
, draw
);
5479 if (draw
->index_size
> 0) {
5482 if (draw
->has_user_indices
) {
5483 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5484 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5485 &offset
, &ice
->state
.last_res
.index_buffer
);
5487 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5488 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5490 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5491 draw
->index
.resource
);
5495 struct iris_genx_state
*genx
= ice
->state
.genx
;
5496 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5498 uint32_t ib_packet
[GENX(3DSTATE_INDEX_BUFFER_length
)];
5499 iris_pack_command(GENX(3DSTATE_INDEX_BUFFER
), ib_packet
, ib
) {
5500 ib
.IndexFormat
= draw
->index_size
>> 1;
5502 ib
.BufferSize
= bo
->size
- offset
;
5503 ib
.BufferStartingAddress
= ro_bo(NULL
, bo
->gtt_offset
+ offset
);
5506 if (memcmp(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
)) != 0) {
5507 memcpy(genx
->last_index_buffer
, ib_packet
, sizeof(ib_packet
));
5508 iris_batch_emit(batch
, ib_packet
, sizeof(ib_packet
));
5509 iris_use_pinned_bo(batch
, bo
, false);
5512 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5513 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5514 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5515 iris_emit_pipe_control_flush(batch
,
5516 "workaround: VF cache 32-bit key [IB]",
5517 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5518 PIPE_CONTROL_CS_STALL
);
5519 ice
->state
.last_index_bo_high_bits
= high_bits
;
5523 #define _3DPRIM_END_OFFSET 0x2420
5524 #define _3DPRIM_START_VERTEX 0x2430
5525 #define _3DPRIM_VERTEX_COUNT 0x2434
5526 #define _3DPRIM_INSTANCE_COUNT 0x2438
5527 #define _3DPRIM_START_INSTANCE 0x243C
5528 #define _3DPRIM_BASE_VERTEX 0x2440
5530 if (draw
->indirect
) {
5531 if (draw
->indirect
->indirect_draw_count
) {
5532 use_predicate
= true;
5534 struct iris_bo
*draw_count_bo
=
5535 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5536 unsigned draw_count_offset
=
5537 draw
->indirect
->indirect_draw_count_offset
;
5539 iris_emit_pipe_control_flush(batch
,
5540 "ensure indirect draw buffer is flushed",
5541 PIPE_CONTROL_FLUSH_ENABLE
);
5543 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5544 struct gen_mi_builder b
;
5545 gen_mi_builder_init(&b
, batch
);
5547 /* comparison = draw id < draw count */
5548 struct gen_mi_value comparison
=
5549 gen_mi_ult(&b
, gen_mi_imm(draw
->drawid
),
5550 gen_mi_mem32(ro_bo(draw_count_bo
,
5551 draw_count_offset
)));
5553 /* predicate = comparison & conditional rendering predicate */
5554 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_RESULT
),
5555 gen_mi_iand(&b
, comparison
,
5556 gen_mi_reg32(CS_GPR(15))));
5558 uint32_t mi_predicate
;
5560 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5561 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5563 /* Upload the current draw count from the draw parameters buffer
5564 * to MI_PREDICATE_SRC0.
5566 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5567 draw_count_bo
, draw_count_offset
);
5568 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5569 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5571 if (draw
->drawid
== 0) {
5572 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5573 MI_PREDICATE_COMBINEOP_SET
|
5574 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5576 /* While draw_index < draw_count the predicate's result will be
5577 * (draw_index == draw_count) ^ TRUE = TRUE
5578 * When draw_index == draw_count the result is
5579 * (TRUE) ^ TRUE = FALSE
5580 * After this all results will be:
5581 * (FALSE) ^ FALSE = FALSE
5583 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5584 MI_PREDICATE_COMBINEOP_XOR
|
5585 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5587 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5590 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5593 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5594 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5595 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5597 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5598 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5599 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5601 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5602 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5603 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5605 if (draw
->index_size
) {
5606 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5607 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5608 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5610 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5611 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5612 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5615 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5616 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5617 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5619 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5620 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5624 } else if (draw
->count_from_stream_output
) {
5625 struct iris_stream_output_target
*so
=
5626 (void *) draw
->count_from_stream_output
;
5628 /* XXX: Replace with actual cache tracking */
5629 iris_emit_pipe_control_flush(batch
,
5630 "draw count from stream output stall",
5631 PIPE_CONTROL_CS_STALL
);
5633 struct gen_mi_builder b
;
5634 gen_mi_builder_init(&b
, batch
);
5636 struct iris_address addr
=
5637 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5638 struct gen_mi_value offset
=
5639 gen_mi_iadd_imm(&b
, gen_mi_mem32(addr
), -so
->base
.buffer_offset
);
5641 gen_mi_store(&b
, gen_mi_reg32(_3DPRIM_VERTEX_COUNT
),
5642 gen_mi_udiv32_imm(&b
, offset
, so
->stride
));
5644 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5645 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5646 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5647 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5650 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5651 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5652 prim
.PredicateEnable
= use_predicate
;
5654 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5655 prim
.IndirectParameterEnable
= true;
5657 prim
.StartInstanceLocation
= draw
->start_instance
;
5658 prim
.InstanceCount
= draw
->instance_count
;
5659 prim
.VertexCountPerInstance
= draw
->count
;
5661 prim
.StartVertexLocation
= draw
->start
;
5663 if (draw
->index_size
) {
5664 prim
.BaseVertexLocation
+= draw
->index_bias
;
5666 prim
.StartVertexLocation
+= draw
->index_bias
;
5673 iris_upload_compute_state(struct iris_context
*ice
,
5674 struct iris_batch
*batch
,
5675 const struct pipe_grid_info
*grid
)
5677 const uint64_t dirty
= ice
->state
.dirty
;
5678 struct iris_screen
*screen
= batch
->screen
;
5679 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5680 struct iris_binder
*binder
= &ice
->state
.binder
;
5681 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5682 struct iris_compiled_shader
*shader
=
5683 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5684 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5685 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5687 /* Always pin the binder. If we're emitting new binding table pointers,
5688 * we need it. If not, we're probably inheriting old tables via the
5689 * context, and need it anyway. Since true zero-bindings cases are
5690 * practically non-existent, just pin it and avoid last_res tracking.
5692 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5694 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5695 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5697 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5698 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5700 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5701 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5703 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5704 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5706 if (ice
->state
.need_border_colors
)
5707 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5709 if (dirty
& IRIS_DIRTY_CS
) {
5710 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5712 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5713 * the only bits that are changed are scoreboard related: Scoreboard
5714 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5715 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5718 iris_emit_pipe_control_flush(batch
,
5719 "workaround: stall before MEDIA_VFE_STATE",
5720 PIPE_CONTROL_CS_STALL
);
5722 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5723 if (prog_data
->total_scratch
) {
5724 struct iris_bo
*bo
=
5725 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5726 MESA_SHADER_COMPUTE
);
5727 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5728 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5731 vfe
.MaximumNumberofThreads
=
5732 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5734 vfe
.ResetGatewayTimer
=
5735 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5738 vfe
.BypassGatewayControl
= true;
5740 vfe
.NumberofURBEntries
= 2;
5741 vfe
.URBEntryAllocationSize
= 2;
5743 vfe
.CURBEAllocationSize
=
5744 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5745 cs_prog_data
->push
.cross_thread
.regs
, 2);
5749 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5750 if (dirty
& IRIS_DIRTY_CS
) {
5751 uint32_t curbe_data_offset
= 0;
5752 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5753 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5754 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5755 uint32_t *curbe_data_map
=
5756 stream_state(batch
, ice
->state
.dynamic_uploader
,
5757 &ice
->state
.last_res
.cs_thread_ids
,
5758 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5759 &curbe_data_offset
);
5760 assert(curbe_data_map
);
5761 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5762 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5764 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5765 curbe
.CURBETotalDataLength
=
5766 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5767 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5771 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5772 IRIS_DIRTY_BINDINGS_CS
|
5773 IRIS_DIRTY_CONSTANTS_CS
|
5775 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5777 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5778 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5779 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5782 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5783 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5785 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5786 load
.InterfaceDescriptorTotalLength
=
5787 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5788 load
.InterfaceDescriptorDataStartAddress
=
5789 emit_state(batch
, ice
->state
.dynamic_uploader
,
5790 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5794 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5795 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5796 uint32_t right_mask
;
5799 right_mask
= ~0u >> (32 - remainder
);
5801 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5803 #define GPGPU_DISPATCHDIMX 0x2500
5804 #define GPGPU_DISPATCHDIMY 0x2504
5805 #define GPGPU_DISPATCHDIMZ 0x2508
5807 if (grid
->indirect
) {
5808 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5809 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5810 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5811 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5812 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5814 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5815 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5816 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5818 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5819 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5820 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5824 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5825 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5826 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5827 ggw
.ThreadDepthCounterMaximum
= 0;
5828 ggw
.ThreadHeightCounterMaximum
= 0;
5829 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5830 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5831 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5832 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5833 ggw
.RightExecutionMask
= right_mask
;
5834 ggw
.BottomExecutionMask
= 0xffffffff;
5837 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5839 if (!batch
->contains_draw
) {
5840 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5841 batch
->contains_draw
= true;
5846 * State module teardown.
5849 iris_destroy_state(struct iris_context
*ice
)
5851 struct iris_genx_state
*genx
= ice
->state
.genx
;
5853 pipe_resource_reference(&ice
->draw
.draw_params_res
, NULL
);
5854 pipe_resource_reference(&ice
->draw
.derived_draw_params_res
, NULL
);
5856 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5858 const int i
= u_bit_scan64(&bound_vbs
);
5859 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5861 free(ice
->state
.genx
);
5863 for (int i
= 0; i
< 4; i
++) {
5864 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5867 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5868 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5870 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5872 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5873 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5874 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5875 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5876 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5877 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5879 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5880 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5881 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5883 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5884 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5885 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5887 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5888 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5889 &shs
->textures
[i
], NULL
);
5893 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5894 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5896 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5897 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5899 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5900 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5901 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5902 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5903 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5904 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5905 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5906 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5909 /* ------------------------------------------------------------------- */
5912 iris_rebind_buffer(struct iris_context
*ice
,
5913 struct iris_resource
*res
,
5914 uint64_t old_address
)
5916 struct pipe_context
*ctx
= &ice
->ctx
;
5917 struct iris_screen
*screen
= (void *) ctx
->screen
;
5918 struct iris_genx_state
*genx
= ice
->state
.genx
;
5920 assert(res
->base
.target
== PIPE_BUFFER
);
5922 /* Buffers can't be framebuffer attachments, nor display related,
5923 * and we don't have upstream Clover support.
5925 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5926 PIPE_BIND_RENDER_TARGET
|
5927 PIPE_BIND_BLENDABLE
|
5928 PIPE_BIND_DISPLAY_TARGET
|
5930 PIPE_BIND_COMPUTE_RESOURCE
|
5931 PIPE_BIND_GLOBAL
)));
5933 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5934 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5936 const int i
= u_bit_scan64(&bound_vbs
);
5937 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5939 /* Update the CPU struct */
5940 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5941 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5942 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5944 if (*addr
== old_address
) {
5945 *addr
= res
->bo
->gtt_offset
;
5946 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5951 /* We don't need to handle PIPE_BIND_INDEX_BUFFER here: we re-emit
5952 * the 3DSTATE_INDEX_BUFFER packet whenever the address changes.
5954 * There is also no need to handle these:
5955 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5956 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5959 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5960 /* XXX: be careful about resetting vs appending... */
5964 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5965 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5966 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5968 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5969 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5970 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5971 while (bound_cbufs
) {
5972 const int i
= u_bit_scan(&bound_cbufs
);
5973 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5974 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5976 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5977 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5978 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5983 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5984 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5985 while (bound_ssbos
) {
5986 const int i
= u_bit_scan(&bound_ssbos
);
5987 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5989 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5990 struct pipe_shader_buffer buf
= {
5991 .buffer
= &res
->base
,
5992 .buffer_offset
= ssbo
->buffer_offset
,
5993 .buffer_size
= ssbo
->buffer_size
,
5995 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5996 (shs
->writable_ssbos
>> i
) & 1);
6001 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
6002 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
6003 while (bound_sampler_views
) {
6004 const int i
= u_bit_scan(&bound_sampler_views
);
6005 struct iris_sampler_view
*isv
= shs
->textures
[i
];
6007 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
6008 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
6009 &isv
->surface_state
,
6010 isv
->res
->aux
.sampler_usages
);
6012 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
6013 isv
->view
.format
, isv
->view
.swizzle
,
6014 isv
->base
.u
.buf
.offset
,
6015 isv
->base
.u
.buf
.size
);
6016 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
6021 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
6022 uint32_t bound_image_views
= shs
->bound_image_views
;
6023 while (bound_image_views
) {
6024 const int i
= u_bit_scan(&bound_image_views
);
6025 struct iris_image_view
*iv
= &shs
->image
[i
];
6027 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
6028 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
6035 /* ------------------------------------------------------------------- */
6038 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
6041 _iris_emit_lrr(batch
, dst
, src
);
6045 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
6048 _iris_emit_lrr(batch
, dst
, src
);
6049 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
6053 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
6056 _iris_emit_lri(batch
, reg
, val
);
6060 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
6063 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
6064 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
6068 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
6071 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6072 struct iris_bo
*bo
, uint32_t offset
)
6074 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
6075 lrm
.RegisterAddress
= reg
;
6076 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
6081 * Load a 64-bit value from a buffer into a MMIO register via
6082 * two MI_LOAD_REGISTER_MEM commands.
6085 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6086 struct iris_bo
*bo
, uint32_t offset
)
6088 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
6089 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
6093 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
6094 struct iris_bo
*bo
, uint32_t offset
,
6097 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
6098 srm
.RegisterAddress
= reg
;
6099 srm
.MemoryAddress
= rw_bo(bo
, offset
);
6100 srm
.PredicateEnable
= predicated
;
6105 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
6106 struct iris_bo
*bo
, uint32_t offset
,
6109 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
6110 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
6114 iris_store_data_imm32(struct iris_batch
*batch
,
6115 struct iris_bo
*bo
, uint32_t offset
,
6118 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
6119 sdi
.Address
= rw_bo(bo
, offset
);
6120 sdi
.ImmediateData
= imm
;
6125 iris_store_data_imm64(struct iris_batch
*batch
,
6126 struct iris_bo
*bo
, uint32_t offset
,
6129 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
6130 * 2 in genxml but it's actually variable length and we need 5 DWords.
6132 void *map
= iris_get_command_space(batch
, 4 * 5);
6133 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
6134 sdi
.DWordLength
= 5 - 2;
6135 sdi
.Address
= rw_bo(bo
, offset
);
6136 sdi
.ImmediateData
= imm
;
6141 iris_copy_mem_mem(struct iris_batch
*batch
,
6142 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
6143 struct iris_bo
*src_bo
, uint32_t src_offset
,
6146 /* MI_COPY_MEM_MEM operates on DWords. */
6147 assert(bytes
% 4 == 0);
6148 assert(dst_offset
% 4 == 0);
6149 assert(src_offset
% 4 == 0);
6151 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
6152 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
6153 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
6154 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
6159 /* ------------------------------------------------------------------- */
6162 flags_to_post_sync_op(uint32_t flags
)
6164 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
6165 return WriteImmediateData
;
6167 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
6168 return WritePSDepthCount
;
6170 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
6171 return WriteTimestamp
;
6177 * Do the given flags have a Post Sync or LRI Post Sync operation?
6179 static enum pipe_control_flags
6180 get_post_sync_flags(enum pipe_control_flags flags
)
6182 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
6183 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6184 PIPE_CONTROL_WRITE_TIMESTAMP
|
6185 PIPE_CONTROL_LRI_POST_SYNC_OP
;
6187 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
6188 * "LRI Post Sync Operation". So more than one bit set would be illegal.
6190 assert(util_bitcount(flags
) <= 1);
6195 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
6198 * Emit a series of PIPE_CONTROL commands, taking into account any
6199 * workarounds necessary to actually accomplish the caller's request.
6201 * Unless otherwise noted, spec quotations in this function come from:
6203 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
6204 * Restrictions for PIPE_CONTROL.
6206 * You should not use this function directly. Use the helpers in
6207 * iris_pipe_control.c instead, which may split the pipe control further.
6210 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
6217 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6218 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
6219 enum pipe_control_flags non_lri_post_sync_flags
=
6220 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
6222 /* Recursive PIPE_CONTROL workarounds --------------------------------
6223 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
6225 * We do these first because we want to look at the original operation,
6226 * rather than any workarounds we set.
6228 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
6229 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
6230 * lists several workarounds:
6232 * "Project: SKL, KBL, BXT
6234 * If the VF Cache Invalidation Enable is set to a 1 in a
6235 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
6236 * sets to 0, with the VF Cache Invalidation Enable set to 0
6237 * needs to be sent prior to the PIPE_CONTROL with VF Cache
6238 * Invalidation Enable set to a 1."
6240 iris_emit_raw_pipe_control(batch
,
6241 "workaround: recursive VF cache invalidate",
6245 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6246 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6248 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6249 * programmed prior to programming a PIPECONTROL command with "LRI
6250 * Post Sync Operation" in GPGPU mode of operation (i.e when
6251 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6253 * The same text exists a few rows below for Post Sync Op.
6255 iris_emit_raw_pipe_control(batch
,
6256 "workaround: CS stall before gpgpu post-sync",
6257 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6260 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6262 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6263 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6264 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6266 iris_emit_raw_pipe_control(batch
,
6267 "workaround: PC flush before RT flush",
6268 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6271 /* "Flush Types" workarounds ---------------------------------------------
6272 * We do these now because they may add post-sync operations or CS stalls.
6275 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6276 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6278 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6279 * 'Write PS Depth Count' or 'Write Timestamp'."
6282 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6283 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6284 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6285 bo
= batch
->screen
->workaround_bo
;
6289 /* #1130 from Gen10 workarounds page:
6291 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6292 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6293 * board stall if Render target cache flush is enabled."
6295 * Applicable to CNL B0 and C0 steppings only.
6297 * The wording here is unclear, and this workaround doesn't look anything
6298 * like the internal bug report recommendations, but leave it be for now...
6300 if (GEN_GEN
== 10) {
6301 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6302 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6303 } else if (flags
& non_lri_post_sync_flags
) {
6304 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6308 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6309 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6311 * "This bit must be DISABLED for operations other than writing
6314 * This seems like nonsense. An Ivybridge workaround requires us to
6315 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6316 * operation. Gen8+ requires us to emit depth stalls and depth cache
6317 * flushes together. So, it's hard to imagine this means anything other
6318 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6320 * We ignore the supposed restriction and do nothing.
6324 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6325 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6326 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6328 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6329 * PS_DEPTH_COUNT or TIMESTAMP queries."
6331 * TODO: Implement end-of-pipe checking.
6333 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6334 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6337 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6338 /* From the PIPE_CONTROL instruction table, bit 1:
6340 * "This bit is ignored if Depth Stall Enable is set.
6341 * Further, the render cache is not flushed even if Write Cache
6342 * Flush Enable bit is set."
6344 * We assert that the caller doesn't do this combination, to try and
6345 * prevent mistakes. It shouldn't hurt the GPU, though.
6347 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6348 * and "Render Target Flush" combo is explicitly required for BTI
6349 * update workarounds.
6351 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6352 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6355 /* PIPE_CONTROL page workarounds ------------------------------------- */
6357 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6358 /* From the PIPE_CONTROL page itself:
6361 * Restriction: Pipe_control with CS-stall bit set must be issued
6362 * before a pipe-control command that has the State Cache
6363 * Invalidate bit set."
6365 flags
|= PIPE_CONTROL_CS_STALL
;
6368 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6369 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6372 * SW must always program Post-Sync Operation to "Write Immediate
6373 * Data" when Flush LLC is set."
6375 * For now, we just require the caller to do it.
6377 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6380 /* "Post-Sync Operation" workarounds -------------------------------- */
6382 /* Project: All / Argument: Global Snapshot Count Reset [19]
6384 * "This bit must not be exercised on any product.
6385 * Requires stall bit ([20] of DW1) set."
6387 * We don't use this, so we just assert that it isn't used. The
6388 * PIPE_CONTROL instruction page indicates that they intended this
6389 * as a debug feature and don't think it is useful in production,
6390 * but it may actually be usable, should we ever want to.
6392 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6394 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6395 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6396 /* Project: All / Arguments:
6398 * - Generic Media State Clear [16]
6399 * - Indirect State Pointers Disable [16]
6401 * "Requires stall bit ([20] of DW1) set."
6403 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6404 * State Clear) says:
6406 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6407 * programmed prior to programming a PIPECONTROL command with "Media
6408 * State Clear" set in GPGPU mode of operation"
6410 * This is a subset of the earlier rule, so there's nothing to do.
6412 flags
|= PIPE_CONTROL_CS_STALL
;
6415 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6416 /* Project: All / Argument: Store Data Index
6418 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6421 * For now, we just assert that the caller does this. We might want to
6422 * automatically add a write to the workaround BO...
6424 assert(non_lri_post_sync_flags
!= 0);
6427 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6428 /* Project: All / Argument: Sync GFDT
6430 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6431 * than '0' or 0x2520[13] must be set."
6433 * For now, we just assert that the caller does this.
6435 assert(non_lri_post_sync_flags
!= 0);
6438 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6439 /* Project: IVB+ / Argument: TLB inv
6441 * "Requires stall bit ([20] of DW1) set."
6443 * Also, from the PIPE_CONTROL instruction table:
6446 * Post Sync Operation or CS stall must be set to ensure a TLB
6447 * invalidation occurs. Otherwise no cycle will occur to the TLB
6448 * cache to invalidate."
6450 * This is not a subset of the earlier rule, so there's nothing to do.
6452 flags
|= PIPE_CONTROL_CS_STALL
;
6455 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6456 /* TODO: The big Skylake GT4 post sync op workaround */
6459 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6461 if (IS_COMPUTE_PIPELINE(batch
)) {
6462 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6463 /* Project: SKL+ / Argument: Tex Invalidate
6464 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6466 flags
|= PIPE_CONTROL_CS_STALL
;
6469 if (GEN_GEN
== 8 && (post_sync_flags
||
6470 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6471 PIPE_CONTROL_DEPTH_STALL
|
6472 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6473 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6474 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6475 /* Project: BDW / Arguments:
6477 * - LRI Post Sync Operation [23]
6478 * - Post Sync Op [15:14]
6480 * - Depth Stall [13]
6481 * - Render Target Cache Flush [12]
6482 * - Depth Cache Flush [0]
6483 * - DC Flush Enable [5]
6485 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6488 flags
|= PIPE_CONTROL_CS_STALL
;
6490 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6493 * This bit must be always set when PIPE_CONTROL command is
6494 * programmed by GPGPU and MEDIA workloads, except for the cases
6495 * when only Read Only Cache Invalidation bits are set (State
6496 * Cache Invalidation Enable, Instruction cache Invalidation
6497 * Enable, Texture Cache Invalidation Enable, Constant Cache
6498 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6499 * need not implemented when FF_DOP_CG is disable via "Fixed
6500 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6502 * It sounds like we could avoid CS stalls in some cases, but we
6503 * don't currently bother. This list isn't exactly the list above,
6509 /* "Stall" workarounds ----------------------------------------------
6510 * These have to come after the earlier ones because we may have added
6511 * some additional CS stalls above.
6514 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6515 /* Project: PRE-SKL, VLV, CHV
6517 * "[All Stepping][All SKUs]:
6519 * One of the following must also be set:
6521 * - Render Target Cache Flush Enable ([12] of DW1)
6522 * - Depth Cache Flush Enable ([0] of DW1)
6523 * - Stall at Pixel Scoreboard ([1] of DW1)
6524 * - Depth Stall ([13] of DW1)
6525 * - Post-Sync Operation ([13] of DW1)
6526 * - DC Flush Enable ([5] of DW1)"
6528 * If we don't already have one of those bits set, we choose to add
6529 * "Stall at Pixel Scoreboard". Some of the other bits require a
6530 * CS stall as a workaround (see above), which would send us into
6531 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6532 * appears to be safe, so we choose that.
6534 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6535 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6536 PIPE_CONTROL_WRITE_IMMEDIATE
|
6537 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6538 PIPE_CONTROL_WRITE_TIMESTAMP
|
6539 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6540 PIPE_CONTROL_DEPTH_STALL
|
6541 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6542 if (!(flags
& wa_bits
))
6543 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6546 /* Emit --------------------------------------------------------------- */
6548 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6550 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6551 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6552 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6553 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6554 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6555 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6556 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6557 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6558 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6559 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6560 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6561 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6562 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6563 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6564 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6565 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6566 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6568 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6570 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6571 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6572 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6576 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6577 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6578 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6579 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6580 pc
.StoreDataIndex
= 0;
6581 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6582 pc
.GlobalSnapshotCountReset
=
6583 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6584 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6585 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6586 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6587 pc
.RenderTargetCacheFlushEnable
=
6588 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6589 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6590 pc
.StateCacheInvalidationEnable
=
6591 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6592 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6593 pc
.ConstantCacheInvalidationEnable
=
6594 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6595 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6596 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6597 pc
.InstructionCacheInvalidateEnable
=
6598 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6599 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6600 pc
.IndirectStatePointersDisable
=
6601 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6602 pc
.TextureCacheInvalidationEnable
=
6603 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6604 pc
.Address
= rw_bo(bo
, offset
);
6605 pc
.ImmediateData
= imm
;
6610 genX(emit_urb_setup
)(struct iris_context
*ice
,
6611 struct iris_batch
*batch
,
6612 const unsigned size
[4],
6613 bool tess_present
, bool gs_present
)
6615 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6616 const unsigned push_size_kB
= 32;
6617 unsigned entries
[4];
6620 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6622 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6623 1024 * ice
->shaders
.urb_size
,
6624 tess_present
, gs_present
,
6625 size
, entries
, start
);
6627 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6628 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6629 urb
._3DCommandSubOpcode
+= i
;
6630 urb
.VSURBStartingAddress
= start
[i
];
6631 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6632 urb
.VSNumberofURBEntries
= entries
[i
];
6639 * Preemption on Gen9 has to be enabled or disabled in various cases.
6641 * See these workarounds for preemption:
6642 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6643 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6644 * - WaDisableMidObjectPreemptionForLineLoop
6647 * We don't put this in the vtable because it's only used on Gen9.
6650 gen9_toggle_preemption(struct iris_context
*ice
,
6651 struct iris_batch
*batch
,
6652 const struct pipe_draw_info
*draw
)
6654 struct iris_genx_state
*genx
= ice
->state
.genx
;
6655 bool object_preemption
= true;
6657 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6659 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6660 * and GS is enabled."
6662 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6663 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6664 object_preemption
= false;
6666 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6668 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6669 * on a previous context. End the previous, the resume another context
6670 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6671 * prempt again we will cause corruption.
6673 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6675 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6676 object_preemption
= false;
6678 /* WaDisableMidObjectPreemptionForLineLoop
6680 * "VF Stats Counters Missing a vertex when preemption enabled.
6682 * WA: Disable mid-draw preemption when the draw uses a lineloop
6685 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6686 object_preemption
= false;
6690 * "VF is corrupting GAFS data when preempted on an instance boundary
6691 * and replayed with instancing enabled.
6693 * WA: Disable preemption when using instanceing."
6695 if (draw
->instance_count
> 1)
6696 object_preemption
= false;
6698 if (genx
->object_preemption
!= object_preemption
) {
6699 iris_enable_obj_preemption(batch
, object_preemption
);
6700 genx
->object_preemption
= object_preemption
;
6706 iris_lost_genx_state(struct iris_context
*ice
, struct iris_batch
*batch
)
6708 struct iris_genx_state
*genx
= ice
->state
.genx
;
6710 memset(genx
->last_index_buffer
, 0, sizeof(genx
->last_index_buffer
));
6714 iris_emit_mi_report_perf_count(struct iris_batch
*batch
,
6716 uint32_t offset_in_bytes
,
6719 iris_emit_cmd(batch
, GENX(MI_REPORT_PERF_COUNT
), mi_rpc
) {
6720 mi_rpc
.MemoryAddress
= rw_bo(bo
, offset_in_bytes
);
6721 mi_rpc
.ReportID
= report_id
;
6726 * Update the pixel hashing modes that determine the balancing of PS threads
6727 * across subslices and slices.
6729 * \param width Width bound of the rendering area (already scaled down if \p
6730 * scale is greater than 1).
6731 * \param height Height bound of the rendering area (already scaled down if \p
6732 * scale is greater than 1).
6733 * \param scale The number of framebuffer samples that could potentially be
6734 * affected by an individual channel of the PS thread. This is
6735 * typically one for single-sampled rendering, but for operations
6736 * like CCS resolves and fast clears a single PS invocation may
6737 * update a huge number of pixels, in which case a finer
6738 * balancing is desirable in order to maximally utilize the
6739 * bandwidth available. UINT_MAX can be used as shorthand for
6740 * "finest hashing mode available".
6743 genX(emit_hashing_mode
)(struct iris_context
*ice
, struct iris_batch
*batch
,
6744 unsigned width
, unsigned height
, unsigned scale
)
6747 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6748 const unsigned slice_hashing
[] = {
6749 /* Because all Gen9 platforms with more than one slice require
6750 * three-way subslice hashing, a single "normal" 16x16 slice hashing
6751 * block is guaranteed to suffer from substantial imbalance, with one
6752 * subslice receiving twice as much work as the other two in the
6755 * The performance impact of that would be particularly severe when
6756 * three-way hashing is also in use for slice balancing (which is the
6757 * case for all Gen9 GT4 platforms), because one of the slices
6758 * receives one every three 16x16 blocks in either direction, which
6759 * is roughly the periodicity of the underlying subslice imbalance
6760 * pattern ("roughly" because in reality the hardware's
6761 * implementation of three-way hashing doesn't do exact modulo 3
6762 * arithmetic, which somewhat decreases the magnitude of this effect
6763 * in practice). This leads to a systematic subslice imbalance
6764 * within that slice regardless of the size of the primitive. The
6765 * 32x32 hashing mode guarantees that the subslice imbalance within a
6766 * single slice hashing block is minimal, largely eliminating this
6770 /* Finest slice hashing mode available. */
6773 const unsigned subslice_hashing
[] = {
6774 /* 16x16 would provide a slight cache locality benefit especially
6775 * visible in the sampler L1 cache efficiency of low-bandwidth
6776 * non-LLC platforms, but it comes at the cost of greater subslice
6777 * imbalance for primitives of dimensions approximately intermediate
6778 * between 16x4 and 16x16.
6781 /* Finest subslice hashing mode available. */
6784 /* Dimensions of the smallest hashing block of a given hashing mode. If
6785 * the rendering area is smaller than this there can't possibly be any
6786 * benefit from switching to this mode, so we optimize out the
6789 const unsigned min_size
[][2] = {
6793 const unsigned idx
= scale
> 1;
6795 if (width
> min_size
[idx
][0] || height
> min_size
[idx
][1]) {
6798 iris_pack_state(GENX(GT_MODE
), >_mode
, reg
) {
6799 reg
.SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0);
6800 reg
.SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0);
6801 reg
.SubsliceHashing
= subslice_hashing
[idx
];
6802 reg
.SubsliceHashingMask
= -1;
6805 iris_emit_raw_pipe_control(batch
,
6806 "workaround: CS stall before GT_MODE LRI",
6807 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6808 PIPE_CONTROL_CS_STALL
,
6811 iris_emit_lri(batch
, GT_MODE
, gt_mode
);
6813 ice
->state
.current_hash_scale
= scale
;
6819 genX(init_state
)(struct iris_context
*ice
)
6821 struct pipe_context
*ctx
= &ice
->ctx
;
6822 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6824 ctx
->create_blend_state
= iris_create_blend_state
;
6825 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6826 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6827 ctx
->create_sampler_state
= iris_create_sampler_state
;
6828 ctx
->create_sampler_view
= iris_create_sampler_view
;
6829 ctx
->create_surface
= iris_create_surface
;
6830 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6831 ctx
->bind_blend_state
= iris_bind_blend_state
;
6832 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6833 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6834 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6835 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6836 ctx
->delete_blend_state
= iris_delete_state
;
6837 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6838 ctx
->delete_rasterizer_state
= iris_delete_state
;
6839 ctx
->delete_sampler_state
= iris_delete_state
;
6840 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6841 ctx
->set_blend_color
= iris_set_blend_color
;
6842 ctx
->set_clip_state
= iris_set_clip_state
;
6843 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6844 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6845 ctx
->set_shader_images
= iris_set_shader_images
;
6846 ctx
->set_sampler_views
= iris_set_sampler_views
;
6847 ctx
->set_tess_state
= iris_set_tess_state
;
6848 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6849 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6850 ctx
->set_sample_mask
= iris_set_sample_mask
;
6851 ctx
->set_scissor_states
= iris_set_scissor_states
;
6852 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6853 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6854 ctx
->set_viewport_states
= iris_set_viewport_states
;
6855 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6856 ctx
->surface_destroy
= iris_surface_destroy
;
6857 ctx
->draw_vbo
= iris_draw_vbo
;
6858 ctx
->launch_grid
= iris_launch_grid
;
6859 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6860 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6861 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6863 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6864 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6865 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6866 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6867 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6868 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6869 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6870 ice
->vtbl
.emit_mi_report_perf_count
= iris_emit_mi_report_perf_count
;
6871 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6872 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6873 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6874 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6875 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6876 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6877 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6878 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6879 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6880 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6881 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6882 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6883 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6884 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6885 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6886 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6887 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6888 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6889 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6890 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6891 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6892 ice
->vtbl
.mocs
= mocs
;
6893 ice
->vtbl
.lost_genx_state
= iris_lost_genx_state
;
6895 ice
->state
.dirty
= ~0ull;
6897 ice
->state
.statistics_counters_enabled
= true;
6899 ice
->state
.sample_mask
= 0xffff;
6900 ice
->state
.num_viewports
= 1;
6901 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6903 /* Make a 1x1x1 null surface for unbound textures */
6904 void *null_surf_map
=
6905 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6906 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6907 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6908 ice
->state
.unbound_tex
.offset
+=
6909 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6911 /* Default all scissor rectangles to be empty regions. */
6912 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6913 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6914 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,