2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_resource.h"
47 #define __gen_address_type unsigned
48 #define __gen_user_data void
51 __gen_combine_address(void *user_data
, void *location
,
52 unsigned address
, uint32_t delta
)
57 #define __genxml_cmd_length(cmd) cmd ## _length
58 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
59 #define __genxml_cmd_header(cmd) cmd ## _header
60 #define __genxml_cmd_pack(cmd) cmd ## _pack
62 #define iris_pack_command(cmd, dst, name) \
63 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
64 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
65 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
66 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
70 #define iris_pack_state(cmd, dst, name) \
71 for (struct cmd name = {}, \
72 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
73 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
76 #define iris_emit_cmd(batch, cmd, name) \
77 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
78 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
80 #define iris_emit_merge(batch, dwords0, dwords1) \
82 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
84 iris_require_command_space(batch, ARRAY_SIZE(dwords0)); \
85 uint32_t *dw = batch->cmdbuf.map_next; \
86 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
87 dw[i] = (dwords0)[i] | (dwords1)[i]; \
88 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4)); \
91 #include "genxml/genX_pack.h"
92 #include "genxml/gen_macros.h"
94 #define MOCS_WB (2 << 1)
96 UNUSED
static void pipe_asserts()
98 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
100 /* pipe_logicop happens to match the hardware. */
101 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
102 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
103 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
104 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
105 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
106 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
107 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
108 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
109 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
110 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
111 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
112 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
113 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
114 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
115 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
116 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
118 /* pipe_blend_func happens to match the hardware. */
119 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
120 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
121 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
122 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
123 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
124 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
125 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
126 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
127 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
128 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
129 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
130 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
131 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
132 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
133 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
139 /* pipe_blend_func happens to match the hardware. */
140 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
141 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
142 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
143 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
144 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
146 /* pipe_stencil_op happens to match the hardware. */
147 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
148 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
149 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
150 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
151 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
152 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
153 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
154 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
159 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
161 assert(prim
== PIPE_PRIM_PATCHES
|| verts_per_patch
== 0);
163 static const unsigned map
[] = {
164 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
165 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
166 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
167 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
168 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
169 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
170 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
171 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
172 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
173 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
174 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
175 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
176 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
177 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
178 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
181 return map
[prim
] + verts_per_patch
;
185 translate_compare_func(enum pipe_compare_func pipe_func
)
187 static const unsigned map
[] = {
188 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
189 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
190 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
191 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
192 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
193 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
194 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
195 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
197 return map
[pipe_func
];
201 translate_shadow_func(enum pipe_compare_func pipe_func
)
203 /* Gallium specifies the result of shadow comparisons as:
205 * 1 if ref <op> texel,
210 * 0 if texel <op> ref,
213 * So we need to flip the operator and also negate.
215 static const unsigned map
[] = {
216 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
217 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
218 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
219 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
220 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
221 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
222 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
223 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
225 return map
[pipe_func
];
229 translate_cull_mode(unsigned pipe_face
)
231 static const unsigned map
[4] = {
232 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
233 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
234 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
235 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
237 return map
[pipe_face
];
241 translate_fill_mode(unsigned pipe_polymode
)
243 static const unsigned map
[4] = {
244 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
245 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
246 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
247 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
249 return map
[pipe_polymode
];
253 iris_upload_initial_gpu_state(struct iris_context
*ice
,
254 struct iris_batch
*batch
)
256 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
257 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
258 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
260 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
261 GEN_SAMPLE_POS_1X(pat
._1xSample
);
262 GEN_SAMPLE_POS_2X(pat
._2xSample
);
263 GEN_SAMPLE_POS_4X(pat
._4xSample
);
264 GEN_SAMPLE_POS_8X(pat
._8xSample
);
265 GEN_SAMPLE_POS_16X(pat
._16xSample
);
267 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
268 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
269 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
270 /* XXX: may need to set an offset for origin-UL framebuffers */
271 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
275 iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
280 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
285 iris_set_blend_color(struct pipe_context
*ctx
,
286 const struct pipe_blend_color
*state
)
288 struct iris_context
*ice
= (struct iris_context
*) ctx
;
290 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
291 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
294 struct iris_blend_state
{
295 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
296 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
297 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
298 GENX(BLEND_STATE_ENTRY_length
)];
302 iris_create_blend_state(struct pipe_context
*ctx
,
303 const struct pipe_blend_state
*state
)
305 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
307 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
308 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
309 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
310 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
311 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
312 bs
.ColorDitherEnable
= state
->dither
;
313 //bs.AlphaTestEnable = <comes from alpha state> :(
314 //bs.AlphaTestFunction = <comes from alpha state> :(
317 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
318 //pb.HasWriteableRT = <comes from somewhere> :(
319 //pb.AlphaTestEnable = <comes from alpha state> :(
320 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
321 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
323 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
325 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
326 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
327 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
328 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
331 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
332 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
333 be
.LogicOpEnable
= state
->logicop_enable
;
334 be
.LogicOpFunction
= state
->logicop_func
;
336 be
.PreBlendSourceOnlyClampEnable
= false;
337 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
338 be
.PreBlendColorClampEnable
= true;
339 be
.PostBlendColorClampEnable
= true;
341 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
343 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
344 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
345 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
346 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
347 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
348 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
350 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
351 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
352 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
353 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
361 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
363 struct iris_context
*ice
= (struct iris_context
*) ctx
;
364 ice
->state
.cso_blend
= state
;
365 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
366 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
369 struct iris_depth_stencil_alpha_state
{
370 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
371 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
373 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
377 iris_create_zsa_state(struct pipe_context
*ctx
,
378 const struct pipe_depth_stencil_alpha_state
*state
)
380 struct iris_depth_stencil_alpha_state
*cso
=
381 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
383 cso
->alpha
= state
->alpha
;
385 bool two_sided_stencil
= state
->stencil
[1].enabled
;
387 /* The state tracker needs to optimize away EQUAL writes for us. */
388 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
390 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
391 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
392 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
393 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
394 wmds
.StencilTestFunction
=
395 translate_compare_func(state
->stencil
[0].func
);
396 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
397 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
398 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
399 wmds
.BackfaceStencilTestFunction
=
400 translate_compare_func(state
->stencil
[1].func
);
401 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
402 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
403 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
404 wmds
.StencilBufferWriteEnable
=
405 state
->stencil
[0].writemask
!= 0 ||
406 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
407 wmds
.DepthTestEnable
= state
->depth
.enabled
;
408 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
409 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
410 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
411 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
412 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
413 /* wmds.[Backface]StencilReferenceValue are merged later */
416 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
417 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
418 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
425 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
427 struct iris_context
*ice
= (struct iris_context
*) ctx
;
428 ice
->state
.cso_zsa
= state
;
429 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
430 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
433 struct iris_rasterizer_state
{
434 uint32_t sf
[GENX(3DSTATE_SF_length
)];
435 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
436 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
437 uint32_t wm
[GENX(3DSTATE_WM_length
)];
439 bool flatshade
; /* for shader state */
440 bool light_twoside
; /* for shader state */
441 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
442 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
443 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
445 uint8_t line_stipple_factor
;
446 uint16_t line_stipple_pattern
;
450 iris_create_rasterizer_state(struct pipe_context
*ctx
,
451 const struct pipe_rasterizer_state
*state
)
453 struct iris_rasterizer_state
*cso
=
454 malloc(sizeof(struct iris_rasterizer_state
));
457 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
458 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
459 point_quad_rasterization
-> SBE
?
464 force_persample_interp
- ?
467 offset_units_unscaled
- cap
not exposed
470 unsigned line_stipple_factor
:8; /**< [1..256] actually */
471 unsigned line_stipple_pattern
:16;
474 cso
->flatshade
= state
->flatshade
;
475 cso
->light_twoside
= state
->light_twoside
;
476 cso
->rasterizer_discard
= state
->rasterizer_discard
;
477 cso
->line_stipple_factor
= state
->line_stipple_factor
;
478 cso
->line_stipple_pattern
= state
->line_stipple_pattern
;
479 // for 3DSTATE_MULTISAMPLE, if we want it.
480 cso
->half_pixel_center
= state
->half_pixel_center
;
482 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
483 sf
.StatisticsEnable
= true;
484 sf
.ViewportTransformEnable
= true;
485 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
486 sf
.LineEndCapAntialiasingRegionWidth
=
487 state
->line_smooth
? _10pixels
: _05pixels
;
488 sf
.LastPixelEnable
= state
->line_last_pixel
;
489 sf
.LineWidth
= state
->line_width
;
490 sf
.SmoothPointEnable
= state
->point_smooth
;
491 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
492 sf
.PointWidth
= state
->point_size
;
494 if (state
->flatshade_first
) {
495 sf
.TriangleStripListProvokingVertexSelect
= 2;
496 sf
.TriangleFanProvokingVertexSelect
= 2;
497 sf
.LineStripListProvokingVertexSelect
= 1;
499 sf
.TriangleFanProvokingVertexSelect
= 1;
504 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
505 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
506 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
507 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
508 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
509 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
510 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
511 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
512 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
513 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
514 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
515 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
516 rr
.SmoothPointEnable
= state
->point_smooth
;
517 rr
.AntialiasingEnable
= state
->line_smooth
;
518 rr
.ScissorRectangleEnable
= state
->scissor
;
519 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
520 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
521 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
524 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
525 cl
.StatisticsEnable
= true;
526 cl
.EarlyCullEnable
= true;
527 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
528 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
529 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
530 cl
.GuardbandClipTestEnable
= true;
531 cl
.ClipMode
= CLIPMODE_NORMAL
;
532 cl
.ClipEnable
= true;
533 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
534 cl
.MinimumPointWidth
= 0.125;
535 cl
.MaximumPointWidth
= 255.875;
536 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
537 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
539 if (state
->flatshade_first
) {
540 cl
.TriangleStripListProvokingVertexSelect
= 2;
541 cl
.TriangleFanProvokingVertexSelect
= 2;
542 cl
.LineStripListProvokingVertexSelect
= 1;
544 cl
.TriangleFanProvokingVertexSelect
= 1;
548 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
549 wm
.LineAntialiasingRegionWidth
= _10pixels
;
550 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
551 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
552 wm
.StatisticsEnable
= true;
553 wm
.LineStippleEnable
= state
->line_stipple_enable
;
554 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
555 // wm.BarycentricInterpolationMode = <comes from FS program> :(
556 // wm.EarlyDepthStencilControl = <comes from FS program> :(
563 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
565 struct iris_context
*ice
= (struct iris_context
*) ctx
;
566 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
567 struct iris_rasterizer_state
*new_cso
= state
;
569 if (old_cso
&& new_cso
) {
570 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
571 if (old_cso
->line_stipple_factor
!= new_cso
->line_stipple_factor
||
572 old_cso
->line_stipple_pattern
!= new_cso
->line_stipple_pattern
) {
573 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
576 if (old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
577 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
581 ice
->state
.cso_rast
= new_cso
;
582 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
586 translate_wrap(unsigned pipe_wrap
)
588 static const unsigned map
[] = {
589 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
590 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
591 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
592 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
593 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
594 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
595 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
596 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
598 return map
[pipe_wrap
];
602 * Return true if the given wrap mode requires the border color to exist.
605 wrap_mode_needs_border_color(unsigned wrap_mode
)
607 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
611 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
613 static const unsigned map
[] = {
614 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
615 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
616 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
618 return map
[pipe_mip
];
621 struct iris_sampler_state
{
622 struct pipe_sampler_state base
;
624 bool needs_border_color
;
626 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
630 iris_create_sampler_state(struct pipe_context
*pctx
,
631 const struct pipe_sampler_state
*state
)
633 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
638 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
639 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
641 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
642 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
643 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
645 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
646 wrap_mode_needs_border_color(wrap_t
) ||
647 wrap_mode_needs_border_color(wrap_r
);
649 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
650 samp
.TCXAddressControlMode
= wrap_s
;
651 samp
.TCYAddressControlMode
= wrap_t
;
652 samp
.TCZAddressControlMode
= wrap_r
;
653 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
654 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
655 samp
.MinModeFilter
= state
->min_img_filter
;
656 samp
.MagModeFilter
= state
->mag_img_filter
;
657 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
658 samp
.MaximumAnisotropy
= RATIO21
;
660 if (state
->max_anisotropy
>= 2) {
661 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
662 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
663 samp
.AnisotropicAlgorithm
= EWAApproximation
;
666 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
667 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
669 samp
.MaximumAnisotropy
=
670 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
673 /* Set address rounding bits if not using nearest filtering. */
674 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
675 samp
.UAddressMinFilterRoundingEnable
= true;
676 samp
.VAddressMinFilterRoundingEnable
= true;
677 samp
.RAddressMinFilterRoundingEnable
= true;
680 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
681 samp
.UAddressMagFilterRoundingEnable
= true;
682 samp
.VAddressMagFilterRoundingEnable
= true;
683 samp
.RAddressMagFilterRoundingEnable
= true;
686 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
687 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
689 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
691 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
692 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
693 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
694 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
696 //samp.BorderColorPointer = <<comes from elsewhere>>
702 struct iris_sampler_view
{
703 struct pipe_sampler_view pipe
;
704 struct isl_view view
;
705 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
709 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
710 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
712 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
715 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
717 * which is simply adding 4 then modding by 8 (or anding with 7).
719 * We then may need to apply workarounds for textureGather hardware bugs.
721 static enum isl_channel_select
722 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
724 return (swizzle
+ 4) & 7;
727 static struct pipe_sampler_view
*
728 iris_create_sampler_view(struct pipe_context
*ctx
,
729 struct pipe_resource
*tex
,
730 const struct pipe_sampler_view
*tmpl
)
732 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
733 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
734 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
739 /* initialize base object */
741 isv
->pipe
.context
= ctx
;
742 isv
->pipe
.texture
= NULL
;
743 pipe_reference_init(&isv
->pipe
.reference
, 1);
744 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
746 /* XXX: do we need brw_get_texture_swizzle hacks here? */
748 isv
->view
= (struct isl_view
) {
749 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
750 .base_level
= tmpl
->u
.tex
.first_level
,
751 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
752 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
753 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
754 .swizzle
= (struct isl_swizzle
) {
755 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
756 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
757 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
758 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
760 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
763 isl_surf_fill_state(&screen
->isl_dev
, isv
->surface_state
,
764 .surf
= &itex
->surf
, .view
= &isv
->view
,
768 // .clear_color = clear_color,
773 struct iris_surface
{
774 struct pipe_surface pipe
;
775 struct isl_view view
;
776 uint32_t surface_state
[GENX(RENDER_SURFACE_STATE_length
)];
779 static struct pipe_surface
*
780 iris_create_surface(struct pipe_context
*ctx
,
781 struct pipe_resource
*tex
,
782 const struct pipe_surface
*tmpl
)
784 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
785 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
786 struct pipe_surface
*psurf
= &surf
->pipe
;
787 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
792 pipe_reference_init(&psurf
->reference
, 1);
793 pipe_resource_reference(&psurf
->texture
, tex
);
794 psurf
->context
= ctx
;
795 psurf
->format
= tmpl
->format
;
796 psurf
->width
= tex
->width0
;
797 psurf
->height
= tex
->height0
;
798 psurf
->texture
= tex
;
799 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
800 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
801 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
803 surf
->view
= (struct isl_view
) {
804 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
805 .base_level
= tmpl
->u
.tex
.level
,
807 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
808 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
809 .swizzle
= ISL_SWIZZLE_IDENTITY
,
810 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
811 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
814 isl_surf_fill_state(&screen
->isl_dev
, surf
->surface_state
,
815 .surf
= &itex
->surf
, .view
= &surf
->view
,
819 // .clear_color = clear_color,
825 iris_set_sampler_views(struct pipe_context
*ctx
,
826 enum pipe_shader_type shader
,
827 unsigned start
, unsigned count
,
828 struct pipe_sampler_view
**views
)
833 iris_bind_sampler_states(struct pipe_context
*ctx
,
834 enum pipe_shader_type shader
,
835 unsigned start
, unsigned count
,
841 iris_set_clip_state(struct pipe_context
*ctx
,
842 const struct pipe_clip_state
*state
)
847 iris_set_polygon_stipple(struct pipe_context
*ctx
,
848 const struct pipe_poly_stipple
*state
)
850 struct iris_context
*ice
= (struct iris_context
*) ctx
;
851 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
852 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
856 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
858 struct iris_context
*ice
= (struct iris_context
*) ctx
;
860 ice
->state
.sample_mask
= sample_mask
;
861 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
865 iris_set_scissor_states(struct pipe_context
*ctx
,
867 unsigned num_scissors
,
868 const struct pipe_scissor_state
*state
)
870 struct iris_context
*ice
= (struct iris_context
*) ctx
;
873 ice
->state
.num_scissors
= num_scissors
;
875 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
876 ice
->state
.scissors
[i
] = *state
;
879 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
883 iris_set_stencil_ref(struct pipe_context
*ctx
,
884 const struct pipe_stencil_ref
*state
)
886 struct iris_context
*ice
= (struct iris_context
*) ctx
;
887 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
888 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
892 struct iris_viewport_state
{
893 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
)];
897 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
899 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
904 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
905 float m00
, float m11
, float m30
, float m31
,
906 float *xmin
, float *xmax
,
907 float *ymin
, float *ymax
)
909 /* According to the "Vertex X,Y Clamping and Quantization" section of the
910 * Strips and Fans documentation:
912 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
913 * fixed-point "guardband" range supported by the rasterization hardware"
917 * "In almost all circumstances, if an object’s vertices are actually
918 * modified by this clamping (i.e., had X or Y coordinates outside of
919 * the guardband extent the rendered object will not match the intended
920 * result. Therefore software should take steps to ensure that this does
921 * not happen - e.g., by clipping objects such that they do not exceed
922 * these limits after the Drawing Rectangle is applied."
924 * I believe the fundamental restriction is that the rasterizer (in
925 * the SF/WM stages) have a limit on the number of pixels that can be
926 * rasterized. We need to ensure any coordinates beyond the rasterizer
927 * limit are handled by the clipper. So effectively that limit becomes
928 * the clipper's guardband size.
932 * "In addition, in order to be correctly rendered, objects must have a
933 * screenspace bounding box not exceeding 8K in the X or Y direction.
934 * This additional restriction must also be comprehended by software,
935 * i.e., enforced by use of clipping."
937 * This makes no sense. Gen7+ hardware supports 16K render targets,
938 * and you definitely need to be able to draw polygons that fill the
939 * surface. Our assumption is that the rasterizer was limited to 8K
940 * on Sandybridge, which only supports 8K surfaces, and it was actually
941 * increased to 16K on Ivybridge and later.
943 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
945 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
947 if (m00
!= 0 && m11
!= 0) {
948 /* First, we compute the screen-space render area */
949 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
950 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
951 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
952 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
954 /* We want the guardband to be centered on that */
955 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
956 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
957 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
958 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
960 /* Now we need it in native device coordinates */
961 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
962 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
963 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
964 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
966 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
967 * flipped upside-down. X should be fine though.
969 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
972 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
973 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
975 /* The viewport scales to 0, so nothing will be rendered. */
985 iris_set_viewport_states(struct pipe_context
*ctx
,
987 unsigned num_viewports
,
988 const struct pipe_viewport_state
*state
)
990 struct iris_context
*ice
= (struct iris_context
*) ctx
;
991 struct iris_viewport_state
*cso
=
992 malloc(sizeof(struct iris_viewport_state
));
994 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
995 float x_extent
= extent_from_matrix(&state
[i
], 0);
996 float y_extent
= extent_from_matrix(&state
[i
], 1);
998 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
999 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1000 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1001 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1002 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1003 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1004 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1005 /* XXX: in i965 this is computed based on the drawbuffer size,
1006 * but we don't have that here...
1008 vp
.XMinClipGuardband
= -1.0;
1009 vp
.XMaxClipGuardband
= 1.0;
1010 vp
.YMinClipGuardband
= -1.0;
1011 vp
.YMaxClipGuardband
= 1.0;
1012 vp
.XMinViewPort
= -x_extent
;
1013 vp
.XMaxViewPort
= x_extent
;
1014 vp
.YMinViewPort
= -y_extent
;
1015 vp
.YMaxViewPort
= y_extent
;
1019 ice
->state
.cso_vp
= cso
;
1021 ice
->state
.num_viewports
= num_viewports
;
1022 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1025 struct iris_depth_state
1027 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1028 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1029 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1033 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1034 const struct pipe_framebuffer_state
*state
)
1036 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1037 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1039 if (cso
->samples
!= state
->samples
) {
1040 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1043 cso
->width
= state
->width
;
1044 cso
->height
= state
->height
;
1045 cso
->layers
= state
->layers
;
1046 cso
->samples
= state
->samples
;
1049 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1050 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1051 for (; i
< cso
->nr_cbufs
; i
++)
1052 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1054 cso
->nr_cbufs
= state
->nr_cbufs
;
1056 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1058 struct isl_depth_stencil_hiz_emit_info info
= {
1062 // XXX: depth buffers
1066 iris_set_constant_buffer(struct pipe_context
*ctx
,
1067 enum pipe_shader_type shader
, uint index
,
1068 const struct pipe_constant_buffer
*cb
)
1074 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1075 struct pipe_sampler_view
*state
)
1077 pipe_resource_reference(&state
->texture
, NULL
);
1083 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
1085 pipe_resource_reference(&surface
->texture
, NULL
);
1090 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1095 struct iris_vertex_buffer_state
{
1096 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1097 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
1101 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1102 unsigned start_slot
, unsigned count
,
1103 const struct pipe_vertex_buffer
*buffers
)
1105 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1106 struct iris_vertex_buffer_state
*cso
=
1107 malloc(sizeof(struct iris_vertex_buffer_state
));
1109 cso
->length
= 4 * count
- 1;
1111 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1112 vb
.DWordLength
= cso
->length
;
1115 /* If there are no buffers, do nothing. We can leave the stale
1116 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1117 * elements that point to them, it should be fine.
1122 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1124 for (unsigned i
= 0; i
< count
; i
++) {
1125 assert(!buffers
[i
].is_user_buffer
);
1127 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1128 vb
.VertexBufferIndex
= start_slot
+ i
;
1130 vb
.AddressModifyEnable
= true;
1131 vb
.BufferPitch
= buffers
[i
].stride
;
1132 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
1133 //vb.BufferSize = bo->size;
1136 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1139 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1142 struct iris_vertex_element_state
{
1143 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1144 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1149 iris_create_vertex_elements(struct pipe_context
*ctx
,
1151 const struct pipe_vertex_element
*state
)
1153 struct iris_vertex_element_state
*cso
=
1154 malloc(sizeof(struct iris_vertex_element_state
));
1159 * - create edge flag one
1161 * - if those are necessary, use count + 1/2/3... OR in the length
1163 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1165 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1167 for (int i
= 0; i
< count
; i
++) {
1168 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1169 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1171 ve
.SourceElementOffset
= state
[i
].src_offset
;
1172 ve
.SourceElementFormat
=
1173 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1176 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1177 vi
.VertexElementIndex
= i
;
1178 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1179 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1182 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1189 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1191 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1193 ice
->state
.cso_vertex_elements
= state
;
1194 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1198 iris_create_compute_state(struct pipe_context
*ctx
,
1199 const struct pipe_compute_state
*state
)
1204 static struct pipe_stream_output_target
*
1205 iris_create_stream_output_target(struct pipe_context
*ctx
,
1206 struct pipe_resource
*res
,
1207 unsigned buffer_offset
,
1208 unsigned buffer_size
)
1210 struct pipe_stream_output_target
*t
=
1211 CALLOC_STRUCT(pipe_stream_output_target
);
1215 pipe_reference_init(&t
->reference
, 1);
1216 pipe_resource_reference(&t
->buffer
, res
);
1217 t
->buffer_offset
= buffer_offset
;
1218 t
->buffer_size
= buffer_size
;
1223 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1224 struct pipe_stream_output_target
*t
)
1226 pipe_resource_reference(&t
->buffer
, NULL
);
1231 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1232 unsigned num_targets
,
1233 struct pipe_stream_output_target
**targets
,
1234 const unsigned *offsets
)
1239 iris_upload_render_state(struct iris_context
*ice
,
1240 struct iris_batch
*batch
,
1241 struct pipe_draw_info
*draw
)
1243 const uint64_t dirty
= ice
->state
.dirty
;
1245 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1246 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1247 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
1249 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1250 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
1251 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
1252 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
1254 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
);
1257 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1258 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1259 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1260 ptr
.CCViewportPointer
=
1261 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1265 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1266 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1267 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1270 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1271 //struct iris_blend_state *cso = ice->state.cso_blend;
1272 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1273 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1274 // (alpha test function/enable) + has writeable RT from ???????
1277 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1278 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
1279 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
1280 ptr
.SFClipViewportPointer
=
1281 iris_emit_state(batch
, cso
->sf_cl_vp
, sizeof(cso
->sf_cl_vp
), 64);
1285 if (dirty
& IRIS_DIRTY_CLIP
) {
1286 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1288 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
1289 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
1290 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1291 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1292 // also userclip stuffs...
1294 iris_emit_merge(batch
, cso
->clip
, dynamic_clip
);
1297 if (dirty
& IRIS_DIRTY_RASTER
) {
1298 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1299 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
1300 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
1303 if (dirty
& IRIS_DIRTY_SCISSOR
) {
1304 uint32_t scissor_offset
=
1305 iris_emit_state(batch
, ice
->state
.scissors
,
1306 sizeof(struct pipe_scissor_state
) *
1307 ice
->state
.num_scissors
, 32);
1309 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
1310 ptr
.ScissorRectPointer
= scissor_offset
;
1314 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
1315 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
1316 for (int i
= 0; i
< 32; i
++) {
1317 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
1322 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
1323 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
1324 iris_emit_cmd(batch
, GENX(3DSTATE_LINE_STIPPLE
), line
) {
1325 line
.LineStipplePattern
= cso
->line_stipple_pattern
;
1326 line
.LineStippleInverseRepeatCount
= 1.0f
/ cso
->line_stipple_factor
;
1327 line
.LineStippleRepeatCount
= cso
->line_stipple_factor
;
1331 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
1332 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
1334 iris_batch_emit(batch
, cso
->vertex_buffers
,
1335 sizeof(uint32_t) * cso
->length
);
1338 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
1339 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
1340 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
1341 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
1342 for (int i
= 0; i
< cso
->count
; i
++) {
1343 iris_batch_emit(batch
, cso
->vf_instancing
[i
],
1344 sizeof(cso
->vf_instancing
[0]));
1346 for (int i
= 0; i
< cso
->count
; i
++) {
1347 /* TODO: vertexid, instanceid support */
1348 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
1352 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
1353 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1355 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
1356 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
1360 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
1361 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
1362 ms
.SampleMask
= ice
->state
.sample_mask
;
1367 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
1368 topo
.PrimitiveTopologyType
=
1369 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
1374 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
1375 vf
.IndexedDrawCutIndexEnable
= draw
->primitive_restart
;
1376 vf
.CutIndex
= draw
->restart_index
;
1380 // draw->index_size > 0
1382 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
1384 assert(!draw
->has_user_indices
);
1386 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
1387 ib
.IndexFormat
= draw
->index_size
;
1389 ib
.BufferSize
= res
->bo
->size
;
1390 // XXX: gah, addresses :( need two different combine address funcs
1391 // ib.BufferStartingAddress = res->bo;
1394 assert(!draw
->indirect
); // XXX: indirect support
1396 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
1397 prim
.StartInstanceLocation
= draw
->start_instance
;
1398 prim
.InstanceCount
= draw
->instance_count
;
1400 // XXX: this is probably bonkers.
1401 prim
.StartVertexLocation
= draw
->start
;
1403 if (draw
->index_size
) {
1404 prim
.BaseVertexLocation
+= draw
->index_bias
;
1406 prim
.StartVertexLocation
+= draw
->index_bias
;
1409 //prim.BaseVertexLocation = ...;
1415 3DSTATE_PUSH_CONSTANT_ALLOC_
*
1419 3DSTATE_CC_STATE_POINTERS
- COLOR_CALC_STATE
1420 -> from ice
->state
.blend_color
+ iris_depth_stencil_alpha_state
1423 3DSTATE_CONSTANT_
* - push constants
1431 - render targets
- write
and read
1432 3DSTATE_BINDING_TABLE_POINTERS_
*
1435 3DSTATE_SAMPLER_STATE_POINTERS_
*
1450 3DSTATE_SO_DECL_LIST
1453 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1455 -> iris_raster_state (point sprite texture coordinate origin
)
1456 -> bunch of shader state
...
1460 3DSTATE_DEPTH_BUFFER
1461 3DSTATE_HIER_DEPTH_BUFFER
1462 3DSTATE_STENCIL_BUFFER
1463 3DSTATE_CLEAR_PARAMS
1464 -> iris_framebuffer_state
?
1469 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1474 iris_destroy_state(struct iris_context
*ice
)
1476 // XXX: unreference resources/surfaces.
1477 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
1478 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
1480 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
1484 iris_init_state_functions(struct pipe_context
*ctx
)
1486 ctx
->create_blend_state
= iris_create_blend_state
;
1487 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1488 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1489 ctx
->create_sampler_state
= iris_create_sampler_state
;
1490 ctx
->create_sampler_view
= iris_create_sampler_view
;
1491 ctx
->create_surface
= iris_create_surface
;
1492 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1493 ctx
->create_compute_state
= iris_create_compute_state
;
1494 ctx
->bind_blend_state
= iris_bind_blend_state
;
1495 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1496 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1497 ctx
->bind_fs_state
= iris_bind_state
;
1498 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
1499 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
1500 ctx
->bind_compute_state
= iris_bind_state
;
1501 ctx
->bind_tcs_state
= iris_bind_state
;
1502 ctx
->bind_tes_state
= iris_bind_state
;
1503 ctx
->bind_gs_state
= iris_bind_state
;
1504 ctx
->bind_vs_state
= iris_bind_state
;
1505 ctx
->delete_blend_state
= iris_delete_state
;
1506 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1507 ctx
->delete_fs_state
= iris_delete_state
;
1508 ctx
->delete_rasterizer_state
= iris_delete_state
;
1509 ctx
->delete_sampler_state
= iris_delete_state
;
1510 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1511 ctx
->delete_compute_state
= iris_delete_state
;
1512 ctx
->delete_tcs_state
= iris_delete_state
;
1513 ctx
->delete_tes_state
= iris_delete_state
;
1514 ctx
->delete_gs_state
= iris_delete_state
;
1515 ctx
->delete_vs_state
= iris_delete_state
;
1516 ctx
->set_blend_color
= iris_set_blend_color
;
1517 ctx
->set_clip_state
= iris_set_clip_state
;
1518 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1519 ctx
->set_sampler_views
= iris_set_sampler_views
;
1520 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1521 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1522 ctx
->set_sample_mask
= iris_set_sample_mask
;
1523 ctx
->set_scissor_states
= iris_set_scissor_states
;
1524 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1525 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1526 ctx
->set_viewport_states
= iris_set_viewport_states
;
1527 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1528 ctx
->surface_destroy
= iris_surface_destroy
;
1529 ctx
->draw_vbo
= iris_draw_vbo
;
1530 ctx
->launch_grid
= iris_launch_grid
;
1531 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1532 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1533 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;