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iris: compctrl
[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "i915_drm.h"
42 #include "intel/compiler/brw_compiler.h"
43 #include "intel/common/gen_l3_config.h"
44 #include "intel/common/gen_sample_positions.h"
45 #include "iris_batch.h"
46 #include "iris_context.h"
47 #include "iris_pipe.h"
48 #include "iris_resource.h"
49
50 #define __gen_address_type struct iris_address
51 #define __gen_user_data struct iris_batch
52
53 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
54
55 static uint64_t
56 __gen_combine_address(struct iris_batch *batch, void *location,
57 struct iris_address addr, uint32_t delta)
58 {
59 if (addr.bo == NULL)
60 return addr.offset + delta;
61
62 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
63 addr.offset + delta, addr.reloc_flags);
64 }
65
66 #define __genxml_cmd_length(cmd) cmd ## _length
67 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
68 #define __genxml_cmd_header(cmd) cmd ## _header
69 #define __genxml_cmd_pack(cmd) cmd ## _pack
70
71 static void *
72 get_command_space(struct iris_batch *batch, unsigned bytes)
73 {
74 iris_require_command_space(batch, bytes);
75 void *map = batch->cmdbuf.map_next;
76 batch->cmdbuf.map_next += bytes;
77 return map;
78 }
79
80 #define _iris_pack_command(batch, cmd, dst, name) \
81 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
82 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
83 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
84 _dst = NULL; \
85 }))
86
87 #define iris_pack_command(cmd, dst, name) \
88 _iris_pack_command(NULL, cmd, dst, name)
89
90 #define iris_pack_state(cmd, dst, name) \
91 for (struct cmd name = {}, \
92 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
93 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
94 _dst = NULL)
95
96 #define iris_emit_cmd(batch, cmd, name) \
97 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
98
99 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
100 do { \
101 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
102 for (uint32_t i = 0; i < num_dwords; i++) \
103 dw[i] = (dwords0)[i] | (dwords1)[i]; \
104 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
105 } while (0)
106
107 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
108 do { \
109 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
110 assert(num_dw <= ARRAY_SIZE(dwords)); \
111 int addr_idx = GENX(addr_field) / 32; \
112 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
113 for (uint32_t i = 0; i < addr_idx; i++) { \
114 dw[i] = (dwords)[i]; \
115 } \
116 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
117 *qw = iris_batch_reloc(batch, (void *)qw - batch->cmdbuf.map, \
118 addr.bo, \
119 addr.offset + (dwords)[addr_idx + 1], \
120 addr.reloc_flags); \
121 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
122 dw[i] = (dwords)[i]; \
123 } \
124 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
125 } while (0)
126
127 #include "genxml/genX_pack.h"
128 #include "genxml/gen_macros.h"
129 #include "genxml/genX_bits.h"
130
131 #define MOCS_WB (2 << 1)
132
133 UNUSED static void pipe_asserts()
134 {
135 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
136
137 /* pipe_logicop happens to match the hardware. */
138 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
139 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
140 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
141 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
142 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
143 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
144 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
145 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
146 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
147 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
148 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
149 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
150 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
151 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
152 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
153 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
154
155 /* pipe_blend_func happens to match the hardware. */
156 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
171 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
172 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
173 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
174 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
175
176 /* pipe_blend_func happens to match the hardware. */
177 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
178 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
179 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
180 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
181 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
182
183 /* pipe_stencil_op happens to match the hardware. */
184 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
185 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
186 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
187 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
188 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
189 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
190 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
191 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
192
193 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
194 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT == UPPERLEFT);
195 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT == LOWERLEFT);
196 #undef PIPE_ASSERT
197 }
198
199 static unsigned
200 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
201 {
202 static const unsigned map[] = {
203 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
204 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
205 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
206 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
207 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
208 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
209 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
210 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
211 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
212 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
213 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
214 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
215 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
216 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
217 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
218 };
219
220 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
221 }
222
223 static unsigned
224 translate_compare_func(enum pipe_compare_func pipe_func)
225 {
226 static const unsigned map[] = {
227 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
228 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
229 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
230 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
231 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
232 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
233 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
234 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
235 };
236 return map[pipe_func];
237 }
238
239 static unsigned
240 translate_shadow_func(enum pipe_compare_func pipe_func)
241 {
242 /* Gallium specifies the result of shadow comparisons as:
243 *
244 * 1 if ref <op> texel,
245 * 0 otherwise.
246 *
247 * The hardware does:
248 *
249 * 0 if texel <op> ref,
250 * 1 otherwise.
251 *
252 * So we need to flip the operator and also negate.
253 */
254 static const unsigned map[] = {
255 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
256 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
257 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
258 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
259 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
260 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
261 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
262 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
263 };
264 return map[pipe_func];
265 }
266
267 static unsigned
268 translate_cull_mode(unsigned pipe_face)
269 {
270 static const unsigned map[4] = {
271 [PIPE_FACE_NONE] = CULLMODE_NONE,
272 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
273 [PIPE_FACE_BACK] = CULLMODE_BACK,
274 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
275 };
276 return map[pipe_face];
277 }
278
279 static unsigned
280 translate_fill_mode(unsigned pipe_polymode)
281 {
282 static const unsigned map[4] = {
283 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
284 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
285 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
286 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
287 };
288 return map[pipe_polymode];
289 }
290
291 static struct iris_address
292 ro_bo(struct iris_bo *bo, uint32_t offset)
293 {
294 return (struct iris_address) { .bo = bo, .offset = offset };
295 }
296
297 static void
298 iris_emit_state_base_address(struct iris_batch *batch)
299 {
300 /* XXX: PIPE_CONTROLs */
301
302 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
303 #if 0
304 // XXX: MOCS is stupid for this.
305 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
306 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
307 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
308 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
309 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
310 sba.InstructionMemoryObjectControlState = MOCS_WB;
311 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
312 #endif
313
314 sba.GeneralStateBaseAddressModifyEnable = true;
315 sba.SurfaceStateBaseAddressModifyEnable = true;
316 sba.DynamicStateBaseAddressModifyEnable = true;
317 sba.IndirectObjectBaseAddressModifyEnable = true;
318 sba.InstructionBaseAddressModifyEnable = true;
319 sba.GeneralStateBufferSizeModifyEnable = true;
320 sba.DynamicStateBufferSizeModifyEnable = true;
321 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
322 sba.IndirectObjectBufferSizeModifyEnable = true;
323 sba.InstructionBuffersizeModifyEnable = true;
324
325 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
326 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
327
328 sba.GeneralStateBufferSize = 0xfffff;
329 sba.IndirectObjectBufferSize = 0xfffff;
330 sba.InstructionBufferSize = 0xfffff;
331 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
332 }
333 }
334
335 static void
336 iris_init_render_context(struct iris_screen *screen,
337 struct iris_batch *batch,
338 struct pipe_debug_callback *dbg)
339 {
340 batch->emit_state_base_address = iris_emit_state_base_address;
341 iris_init_batch(batch, screen, dbg, I915_EXEC_RENDER);
342
343 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
344 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
345 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
346 }
347 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
348 GEN_SAMPLE_POS_1X(pat._1xSample);
349 GEN_SAMPLE_POS_2X(pat._2xSample);
350 GEN_SAMPLE_POS_4X(pat._4xSample);
351 GEN_SAMPLE_POS_8X(pat._8xSample);
352 GEN_SAMPLE_POS_16X(pat._16xSample);
353 }
354 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
355 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
356 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
357 /* XXX: may need to set an offset for origin-UL framebuffers */
358 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
359
360 /* Just assign a static partitioning. */
361 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
362 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
363 alloc._3DCommandSubOpcode = 18 + i;
364 alloc.ConstantBufferOffset = 6 * i;
365 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
366 }
367 }
368 }
369
370 static void
371 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
372 {
373 }
374
375 static void
376 iris_set_blend_color(struct pipe_context *ctx,
377 const struct pipe_blend_color *state)
378 {
379 struct iris_context *ice = (struct iris_context *) ctx;
380
381 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
382 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
383 }
384
385 struct iris_blend_state {
386 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
387 uint32_t blend_state[GENX(BLEND_STATE_length) +
388 BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)];
389
390 bool alpha_to_coverage; /* for shader key */
391 };
392
393 static void *
394 iris_create_blend_state(struct pipe_context *ctx,
395 const struct pipe_blend_state *state)
396 {
397 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
398 uint32_t *blend_state = cso->blend_state;
399
400 cso->alpha_to_coverage = state->alpha_to_coverage;
401
402 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
403 /* pb.HasWriteableRT is filled in at draw time. */
404 /* pb.AlphaTestEnable is filled in at draw time. */
405 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
406 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
407
408 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
409
410 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
411 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
412 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
413 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
414 }
415
416 iris_pack_state(GENX(BLEND_STATE), blend_state, bs) {
417 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
418 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
419 bs.AlphaToOneEnable = state->alpha_to_one;
420 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
421 bs.ColorDitherEnable = state->dither;
422 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
423 }
424
425 blend_state += GENX(BLEND_STATE_length);
426
427 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
428 iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_state, be) {
429 be.LogicOpEnable = state->logicop_enable;
430 be.LogicOpFunction = state->logicop_func;
431
432 be.PreBlendSourceOnlyClampEnable = false;
433 be.ColorClampRange = COLORCLAMP_RTFORMAT;
434 be.PreBlendColorClampEnable = true;
435 be.PostBlendColorClampEnable = true;
436
437 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
438
439 be.ColorBlendFunction = state->rt[i].rgb_func;
440 be.AlphaBlendFunction = state->rt[i].alpha_func;
441 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
442 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
443 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
444 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
445
446 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
447 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
448 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
449 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
450 }
451 blend_state += GENX(BLEND_STATE_ENTRY_length);
452 }
453
454 return cso;
455 }
456
457 static void
458 iris_bind_blend_state(struct pipe_context *ctx, void *state)
459 {
460 struct iris_context *ice = (struct iris_context *) ctx;
461 ice->state.cso_blend = state;
462 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
463 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
464 }
465
466 struct iris_depth_stencil_alpha_state {
467 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
468 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
469
470 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
471 };
472
473 static void *
474 iris_create_zsa_state(struct pipe_context *ctx,
475 const struct pipe_depth_stencil_alpha_state *state)
476 {
477 struct iris_depth_stencil_alpha_state *cso =
478 malloc(sizeof(struct iris_depth_stencil_alpha_state));
479
480 cso->alpha = state->alpha;
481
482 bool two_sided_stencil = state->stencil[1].enabled;
483
484 /* The state tracker needs to optimize away EQUAL writes for us. */
485 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
486
487 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
488 wmds.StencilFailOp = state->stencil[0].fail_op;
489 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
490 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
491 wmds.StencilTestFunction =
492 translate_compare_func(state->stencil[0].func);
493 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
494 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
495 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
496 wmds.BackfaceStencilTestFunction =
497 translate_compare_func(state->stencil[1].func);
498 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
499 wmds.DoubleSidedStencilEnable = two_sided_stencil;
500 wmds.StencilTestEnable = state->stencil[0].enabled;
501 wmds.StencilBufferWriteEnable =
502 state->stencil[0].writemask != 0 ||
503 (two_sided_stencil && state->stencil[1].writemask != 0);
504 wmds.DepthTestEnable = state->depth.enabled;
505 wmds.DepthBufferWriteEnable = state->depth.writemask;
506 wmds.StencilTestMask = state->stencil[0].valuemask;
507 wmds.StencilWriteMask = state->stencil[0].writemask;
508 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
509 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
510 /* wmds.[Backface]StencilReferenceValue are merged later */
511 }
512
513 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
514 ccvp.MinimumDepth = state->depth.bounds_min;
515 ccvp.MaximumDepth = state->depth.bounds_max;
516 }
517
518 return cso;
519 }
520
521 static void
522 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
523 {
524 struct iris_context *ice = (struct iris_context *) ctx;
525 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
526 struct iris_depth_stencil_alpha_state *new_cso = state;
527
528 if (new_cso) {
529 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
530 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
531 }
532 }
533
534 ice->state.cso_zsa = new_cso;
535 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
536 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
537 }
538
539 struct iris_rasterizer_state {
540 uint32_t sf[GENX(3DSTATE_SF_length)];
541 uint32_t clip[GENX(3DSTATE_CLIP_length)];
542 uint32_t raster[GENX(3DSTATE_RASTER_length)];
543 uint32_t wm[GENX(3DSTATE_WM_length)];
544 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
545
546 bool flatshade; /* for shader state */
547 bool clamp_fragment_color; /* for shader state */
548 bool light_twoside; /* for shader state */
549 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
550 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
551 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
552 uint16_t sprite_coord_enable;
553 };
554
555 static void *
556 iris_create_rasterizer_state(struct pipe_context *ctx,
557 const struct pipe_rasterizer_state *state)
558 {
559 struct iris_rasterizer_state *cso =
560 malloc(sizeof(struct iris_rasterizer_state));
561
562 #if 0
563 point_quad_rasterization -> SBE?
564
565 not necessary?
566 {
567 poly_smooth
568 force_persample_interp - ?
569 bottom_edge_rule
570
571 offset_units_unscaled - cap not exposed
572 }
573 #endif
574
575 cso->flatshade = state->flatshade;
576 cso->clamp_fragment_color = state->clamp_fragment_color;
577 cso->light_twoside = state->light_twoside;
578 cso->rasterizer_discard = state->rasterizer_discard;
579 cso->half_pixel_center = state->half_pixel_center;
580 cso->sprite_coord_mode = state->sprite_coord_mode;
581 cso->sprite_coord_enable = state->sprite_coord_enable;
582
583 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
584 sf.StatisticsEnable = true;
585 sf.ViewportTransformEnable = true;
586 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
587 sf.LineEndCapAntialiasingRegionWidth =
588 state->line_smooth ? _10pixels : _05pixels;
589 sf.LastPixelEnable = state->line_last_pixel;
590 sf.LineWidth = state->line_width;
591 sf.SmoothPointEnable = state->point_smooth;
592 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
593 sf.PointWidth = state->point_size;
594
595 if (state->flatshade_first) {
596 sf.TriangleStripListProvokingVertexSelect = 2;
597 sf.TriangleFanProvokingVertexSelect = 2;
598 sf.LineStripListProvokingVertexSelect = 1;
599 } else {
600 sf.TriangleFanProvokingVertexSelect = 1;
601 }
602 }
603
604 /* COMPLETE! */
605 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
606 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
607 rr.CullMode = translate_cull_mode(state->cull_face);
608 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
609 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
610 rr.DXMultisampleRasterizationEnable = state->multisample;
611 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
612 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
613 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
614 rr.GlobalDepthOffsetConstant = state->offset_units;
615 rr.GlobalDepthOffsetScale = state->offset_scale;
616 rr.GlobalDepthOffsetClamp = state->offset_clamp;
617 rr.SmoothPointEnable = state->point_smooth;
618 rr.AntialiasingEnable = state->line_smooth;
619 rr.ScissorRectangleEnable = state->scissor;
620 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
621 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
622 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
623 }
624
625 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
626 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
627 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
628 */
629 cl.StatisticsEnable = true;
630 cl.EarlyCullEnable = true;
631 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
632 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
633 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
634 cl.GuardbandClipTestEnable = true;
635 cl.ClipMode = CLIPMODE_NORMAL;
636 cl.ClipEnable = true;
637 cl.ViewportXYClipTestEnable = state->point_tri_clip;
638 cl.MinimumPointWidth = 0.125;
639 cl.MaximumPointWidth = 255.875;
640
641 if (state->flatshade_first) {
642 cl.TriangleStripListProvokingVertexSelect = 2;
643 cl.TriangleFanProvokingVertexSelect = 2;
644 cl.LineStripListProvokingVertexSelect = 1;
645 } else {
646 cl.TriangleFanProvokingVertexSelect = 1;
647 }
648 }
649
650 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
651 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
652 * filled in at draw time from the FS program.
653 */
654 wm.LineAntialiasingRegionWidth = _10pixels;
655 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
656 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
657 wm.StatisticsEnable = true;
658 wm.LineStippleEnable = state->line_stipple_enable;
659 wm.PolygonStippleEnable = state->poly_stipple_enable;
660 }
661
662 /* Remap from 0..255 back to 1..256 */
663 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
664
665 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
666 line.LineStipplePattern = state->line_stipple_pattern;
667 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
668 line.LineStippleRepeatCount = line_stipple_factor;
669 }
670
671 return cso;
672 }
673
674 static void
675 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
676 {
677 struct iris_context *ice = (struct iris_context *) ctx;
678 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
679 struct iris_rasterizer_state *new_cso = state;
680
681 if (new_cso) {
682 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
683 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
684 sizeof(old_cso->line_stipple)) != 0) {
685 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
686 }
687
688 if (!old_cso ||
689 old_cso->half_pixel_center != new_cso->half_pixel_center) {
690 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
691 }
692 }
693
694 ice->state.cso_rast = new_cso;
695 ice->state.dirty |= IRIS_DIRTY_RASTER;
696 }
697
698 static uint32_t
699 translate_wrap(unsigned pipe_wrap)
700 {
701 static const unsigned map[] = {
702 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
703 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
704 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
705 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
706 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
707 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
708 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
709 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
710 };
711 return map[pipe_wrap];
712 }
713
714 /**
715 * Return true if the given wrap mode requires the border color to exist.
716 */
717 static bool
718 wrap_mode_needs_border_color(unsigned wrap_mode)
719 {
720 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
721 }
722
723 static unsigned
724 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
725 {
726 static const unsigned map[] = {
727 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
728 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
729 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
730 };
731 return map[pipe_mip];
732 }
733
734 struct iris_sampler_state {
735 struct pipe_sampler_state base;
736
737 bool needs_border_color;
738
739 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
740 };
741
742 static void *
743 iris_create_sampler_state(struct pipe_context *pctx,
744 const struct pipe_sampler_state *state)
745 {
746 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
747
748 if (!cso)
749 return NULL;
750
751 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
752 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
753
754 unsigned wrap_s = translate_wrap(state->wrap_s);
755 unsigned wrap_t = translate_wrap(state->wrap_t);
756 unsigned wrap_r = translate_wrap(state->wrap_r);
757
758 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
759 wrap_mode_needs_border_color(wrap_t) ||
760 wrap_mode_needs_border_color(wrap_r);
761
762 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
763 samp.TCXAddressControlMode = wrap_s;
764 samp.TCYAddressControlMode = wrap_t;
765 samp.TCZAddressControlMode = wrap_r;
766 samp.CubeSurfaceControlMode = state->seamless_cube_map;
767 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
768 samp.MinModeFilter = state->min_img_filter;
769 samp.MagModeFilter = state->mag_img_filter;
770 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
771 samp.MaximumAnisotropy = RATIO21;
772
773 if (state->max_anisotropy >= 2) {
774 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
775 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
776 samp.AnisotropicAlgorithm = EWAApproximation;
777 }
778
779 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
780 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
781
782 samp.MaximumAnisotropy =
783 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
784 }
785
786 /* Set address rounding bits if not using nearest filtering. */
787 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
788 samp.UAddressMinFilterRoundingEnable = true;
789 samp.VAddressMinFilterRoundingEnable = true;
790 samp.RAddressMinFilterRoundingEnable = true;
791 }
792
793 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
794 samp.UAddressMagFilterRoundingEnable = true;
795 samp.VAddressMagFilterRoundingEnable = true;
796 samp.RAddressMagFilterRoundingEnable = true;
797 }
798
799 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
800 samp.ShadowFunction = translate_shadow_func(state->compare_func);
801
802 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
803
804 samp.LODPreClampMode = CLAMP_MODE_OGL;
805 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
806 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
807 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
808
809 //samp.BorderColorPointer = <<comes from elsewhere>>
810 }
811
812 return cso;
813 }
814
815 static void
816 iris_bind_sampler_states(struct pipe_context *ctx,
817 enum pipe_shader_type p_stage,
818 unsigned start, unsigned count,
819 void **states)
820 {
821 struct iris_context *ice = (struct iris_context *) ctx;
822 gl_shader_stage stage = stage_from_pipe(p_stage);
823
824 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
825
826 for (int i = 0; i < count; i++) {
827 ice->state.samplers[stage][start + i] = states[i];
828 }
829
830 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
831 }
832
833 struct iris_sampler_view {
834 struct pipe_sampler_view pipe;
835 struct isl_view view;
836 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
837 };
838
839 /**
840 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
841 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
842 *
843 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
844 * 0 1 2 3 4 5
845 * 4 5 6 7 0 1
846 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
847 *
848 * which is simply adding 4 then modding by 8 (or anding with 7).
849 *
850 * We then may need to apply workarounds for textureGather hardware bugs.
851 */
852 static enum isl_channel_select
853 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
854 {
855 return (swizzle + 4) & 7;
856 }
857
858 static struct pipe_sampler_view *
859 iris_create_sampler_view(struct pipe_context *ctx,
860 struct pipe_resource *tex,
861 const struct pipe_sampler_view *tmpl)
862 {
863 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
864 struct iris_resource *itex = (struct iris_resource *) tex;
865 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
866
867 if (!isv)
868 return NULL;
869
870 /* initialize base object */
871 isv->pipe = *tmpl;
872 isv->pipe.context = ctx;
873 isv->pipe.texture = NULL;
874 pipe_reference_init(&isv->pipe.reference, 1);
875 pipe_resource_reference(&isv->pipe.texture, tex);
876
877 /* XXX: do we need brw_get_texture_swizzle hacks here? */
878
879 isv->view = (struct isl_view) {
880 .format = iris_isl_format_for_pipe_format(tmpl->format),
881 .base_level = tmpl->u.tex.first_level,
882 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
883 .base_array_layer = tmpl->u.tex.first_layer,
884 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
885 .swizzle = (struct isl_swizzle) {
886 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
887 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
888 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
889 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
890 },
891 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
892 };
893
894 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
895 .surf = &itex->surf, .view = &isv->view,
896 .mocs = MOCS_WB);
897 // .address = ...
898 // .aux_surf =
899 // .clear_color = clear_color,
900
901 return &isv->pipe;
902 }
903
904 struct iris_surface {
905 struct pipe_surface pipe;
906 struct isl_view view;
907 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
908 };
909
910 static struct pipe_surface *
911 iris_create_surface(struct pipe_context *ctx,
912 struct pipe_resource *tex,
913 const struct pipe_surface *tmpl)
914 {
915 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
916 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
917 struct pipe_surface *psurf = &surf->pipe;
918 struct iris_resource *itex = (struct iris_resource *) tex;
919
920 if (!surf)
921 return NULL;
922
923 pipe_reference_init(&psurf->reference, 1);
924 pipe_resource_reference(&psurf->texture, tex);
925 psurf->context = ctx;
926 psurf->format = tmpl->format;
927 psurf->width = tex->width0;
928 psurf->height = tex->height0;
929 psurf->texture = tex;
930 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
931 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
932 psurf->u.tex.level = tmpl->u.tex.level;
933
934 surf->view = (struct isl_view) {
935 .format = iris_isl_format_for_pipe_format(tmpl->format),
936 .base_level = tmpl->u.tex.level,
937 .levels = 1,
938 .base_array_layer = tmpl->u.tex.first_layer,
939 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
940 .swizzle = ISL_SWIZZLE_IDENTITY,
941 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
942 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
943 };
944
945 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
946 .surf = &itex->surf, .view = &surf->view,
947 .mocs = MOCS_WB);
948 // .address = ...
949 // .aux_surf =
950 // .clear_color = clear_color,
951
952 return psurf;
953 }
954
955 static void
956 iris_set_sampler_views(struct pipe_context *ctx,
957 enum pipe_shader_type shader,
958 unsigned start, unsigned count,
959 struct pipe_sampler_view **views)
960 {
961 }
962
963 static void
964 iris_set_clip_state(struct pipe_context *ctx,
965 const struct pipe_clip_state *state)
966 {
967 }
968
969 static void
970 iris_set_polygon_stipple(struct pipe_context *ctx,
971 const struct pipe_poly_stipple *state)
972 {
973 struct iris_context *ice = (struct iris_context *) ctx;
974 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
975 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
976 }
977
978 static void
979 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
980 {
981 struct iris_context *ice = (struct iris_context *) ctx;
982
983 ice->state.sample_mask = sample_mask;
984 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
985 }
986
987 static void
988 iris_set_scissor_states(struct pipe_context *ctx,
989 unsigned start_slot,
990 unsigned num_scissors,
991 const struct pipe_scissor_state *states)
992 {
993 struct iris_context *ice = (struct iris_context *) ctx;
994
995 ice->state.num_scissors = num_scissors;
996
997 for (unsigned i = 0; i < num_scissors; i++) {
998 ice->state.scissors[start_slot + i] = states[i];
999 }
1000
1001 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
1002 }
1003
1004 static void
1005 iris_set_stencil_ref(struct pipe_context *ctx,
1006 const struct pipe_stencil_ref *state)
1007 {
1008 struct iris_context *ice = (struct iris_context *) ctx;
1009 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
1010 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
1011 }
1012
1013
1014 struct iris_viewport_state {
1015 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
1016 };
1017
1018 static float
1019 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
1020 {
1021 return fabsf(state->scale[axis]) * state->translate[axis];
1022 }
1023
1024 #if 0
1025 static void
1026 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
1027 float m00, float m11, float m30, float m31,
1028 float *xmin, float *xmax,
1029 float *ymin, float *ymax)
1030 {
1031 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1032 * Strips and Fans documentation:
1033 *
1034 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1035 * fixed-point "guardband" range supported by the rasterization hardware"
1036 *
1037 * and
1038 *
1039 * "In almost all circumstances, if an object’s vertices are actually
1040 * modified by this clamping (i.e., had X or Y coordinates outside of
1041 * the guardband extent the rendered object will not match the intended
1042 * result. Therefore software should take steps to ensure that this does
1043 * not happen - e.g., by clipping objects such that they do not exceed
1044 * these limits after the Drawing Rectangle is applied."
1045 *
1046 * I believe the fundamental restriction is that the rasterizer (in
1047 * the SF/WM stages) have a limit on the number of pixels that can be
1048 * rasterized. We need to ensure any coordinates beyond the rasterizer
1049 * limit are handled by the clipper. So effectively that limit becomes
1050 * the clipper's guardband size.
1051 *
1052 * It goes on to say:
1053 *
1054 * "In addition, in order to be correctly rendered, objects must have a
1055 * screenspace bounding box not exceeding 8K in the X or Y direction.
1056 * This additional restriction must also be comprehended by software,
1057 * i.e., enforced by use of clipping."
1058 *
1059 * This makes no sense. Gen7+ hardware supports 16K render targets,
1060 * and you definitely need to be able to draw polygons that fill the
1061 * surface. Our assumption is that the rasterizer was limited to 8K
1062 * on Sandybridge, which only supports 8K surfaces, and it was actually
1063 * increased to 16K on Ivybridge and later.
1064 *
1065 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1066 */
1067 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
1068
1069 if (m00 != 0 && m11 != 0) {
1070 /* First, we compute the screen-space render area */
1071 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1072 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1073 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1074 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1075
1076 /* We want the guardband to be centered on that */
1077 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1078 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1079 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1080 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1081
1082 /* Now we need it in native device coordinates */
1083 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1084 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1085 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1086 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1087
1088 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1089 * flipped upside-down. X should be fine though.
1090 */
1091 assert(ndc_gb_xmin <= ndc_gb_xmax);
1092 *xmin = ndc_gb_xmin;
1093 *xmax = ndc_gb_xmax;
1094 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1095 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1096 } else {
1097 /* The viewport scales to 0, so nothing will be rendered. */
1098 *xmin = 0.0f;
1099 *xmax = 0.0f;
1100 *ymin = 0.0f;
1101 *ymax = 0.0f;
1102 }
1103 }
1104 #endif
1105
1106 static void
1107 iris_set_viewport_states(struct pipe_context *ctx,
1108 unsigned start_slot,
1109 unsigned num_viewports,
1110 const struct pipe_viewport_state *state)
1111 {
1112 struct iris_context *ice = (struct iris_context *) ctx;
1113 struct iris_viewport_state *cso =
1114 malloc(sizeof(struct iris_viewport_state));
1115
1116 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1117 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1118 float x_extent = extent_from_matrix(&state[i], 0);
1119 float y_extent = extent_from_matrix(&state[i], 1);
1120
1121 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1122 vp.ViewportMatrixElementm00 = state[i].scale[0];
1123 vp.ViewportMatrixElementm11 = state[i].scale[1];
1124 vp.ViewportMatrixElementm22 = state[i].scale[2];
1125 vp.ViewportMatrixElementm30 = state[i].translate[0];
1126 vp.ViewportMatrixElementm31 = state[i].translate[1];
1127 vp.ViewportMatrixElementm32 = state[i].translate[2];
1128 /* XXX: in i965 this is computed based on the drawbuffer size,
1129 * but we don't have that here...
1130 */
1131 vp.XMinClipGuardband = -1.0;
1132 vp.XMaxClipGuardband = 1.0;
1133 vp.YMinClipGuardband = -1.0;
1134 vp.YMaxClipGuardband = 1.0;
1135 vp.XMinViewPort = -x_extent;
1136 vp.XMaxViewPort = x_extent;
1137 vp.YMinViewPort = -y_extent;
1138 vp.YMaxViewPort = y_extent;
1139 }
1140 }
1141
1142 ice->state.cso_vp = cso;
1143 // XXX: start_slot
1144 ice->state.num_viewports = num_viewports;
1145 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1146 }
1147
1148 struct iris_depth_state
1149 {
1150 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1151 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1152 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1153 };
1154
1155 static void
1156 iris_set_framebuffer_state(struct pipe_context *ctx,
1157 const struct pipe_framebuffer_state *state)
1158 {
1159 struct iris_context *ice = (struct iris_context *) ctx;
1160 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1161
1162 if (cso->samples != state->samples) {
1163 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1164 }
1165
1166 if (cso->nr_cbufs != state->nr_cbufs) {
1167 ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
1168 }
1169
1170 cso->width = state->width;
1171 cso->height = state->height;
1172 cso->layers = state->layers;
1173 cso->samples = state->samples;
1174
1175 unsigned i;
1176 for (i = 0; i < state->nr_cbufs; i++)
1177 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1178 for (; i < cso->nr_cbufs; i++)
1179 pipe_surface_reference(&cso->cbufs[i], NULL);
1180
1181 cso->nr_cbufs = state->nr_cbufs;
1182
1183 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1184
1185 struct isl_depth_stencil_hiz_emit_info info = {
1186 .mocs = MOCS_WB,
1187 };
1188
1189 // XXX: depth buffers
1190 }
1191
1192 static void
1193 iris_set_constant_buffer(struct pipe_context *ctx,
1194 enum pipe_shader_type shader, uint index,
1195 const struct pipe_constant_buffer *cb)
1196 {
1197 }
1198
1199
1200 static void
1201 iris_sampler_view_destroy(struct pipe_context *ctx,
1202 struct pipe_sampler_view *state)
1203 {
1204 pipe_resource_reference(&state->texture, NULL);
1205 free(state);
1206 }
1207
1208
1209 static void
1210 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1211 {
1212 pipe_resource_reference(&surface->texture, NULL);
1213 free(surface);
1214 }
1215
1216 static void
1217 iris_delete_state(struct pipe_context *ctx, void *state)
1218 {
1219 free(state);
1220 }
1221
1222 struct iris_vertex_buffer_state {
1223 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1224 struct iris_address bos[33];
1225 unsigned num_buffers;
1226 };
1227
1228 static void
1229 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1230 {
1231 if (cso) {
1232 for (unsigned i = 0; i < cso->num_buffers; i++)
1233 iris_bo_unreference(cso->bos[i].bo);
1234 free(cso);
1235 }
1236 }
1237
1238 static void
1239 iris_set_vertex_buffers(struct pipe_context *ctx,
1240 unsigned start_slot, unsigned count,
1241 const struct pipe_vertex_buffer *buffers)
1242 {
1243 struct iris_context *ice = (struct iris_context *) ctx;
1244 struct iris_vertex_buffer_state *cso =
1245 malloc(sizeof(struct iris_vertex_buffer_state));
1246
1247 /* If there are no buffers, do nothing. We can leave the stale
1248 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1249 * elements that point to them, it should be fine.
1250 */
1251 if (!buffers)
1252 return;
1253
1254 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1255
1256 cso->num_buffers = count;
1257
1258 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1259 vb.DWordLength = 4 * cso->num_buffers - 1;
1260 }
1261
1262 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1263
1264 for (unsigned i = 0; i < count; i++) {
1265 assert(!buffers[i].is_user_buffer);
1266
1267 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1268 iris_bo_reference(res->bo);
1269 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1270
1271 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1272 vb.VertexBufferIndex = start_slot + i;
1273 vb.MOCS = MOCS_WB;
1274 vb.AddressModifyEnable = true;
1275 vb.BufferPitch = buffers[i].stride;
1276 vb.BufferSize = res->bo->size;
1277 /* vb.BufferStartingAddress is filled in at draw time */
1278 }
1279
1280 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1281 }
1282
1283 ice->state.cso_vertex_buffers = cso;
1284 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1285 }
1286
1287 struct iris_vertex_element_state {
1288 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1289 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1290 unsigned count;
1291 };
1292
1293 static void *
1294 iris_create_vertex_elements(struct pipe_context *ctx,
1295 unsigned count,
1296 const struct pipe_vertex_element *state)
1297 {
1298 struct iris_vertex_element_state *cso =
1299 malloc(sizeof(struct iris_vertex_element_state));
1300
1301 cso->count = count;
1302
1303 /* TODO:
1304 * - create edge flag one
1305 * - create SGV ones
1306 * - if those are necessary, use count + 1/2/3... OR in the length
1307 */
1308 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1309
1310 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1311
1312 for (int i = 0; i < count; i++) {
1313 enum isl_format isl_format =
1314 iris_isl_format_for_pipe_format(state[i].src_format);
1315 unsigned comp[4] = { VFCOMP_STORE_SRC, VFCOMP_STORE_SRC,
1316 VFCOMP_STORE_SRC, VFCOMP_STORE_SRC };
1317
1318 switch (isl_format_get_num_channels(isl_format)) {
1319 case 0: comp[0] = VFCOMP_STORE_0;
1320 case 1: comp[1] = VFCOMP_STORE_0;
1321 case 2: comp[2] = VFCOMP_STORE_0;
1322 case 3:
1323 comp[3] = isl_format_has_int_channel(isl_format) ? VFCOMP_STORE_1_INT
1324 : VFCOMP_STORE_1_FP;
1325 break;
1326 }
1327 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1328 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1329 ve.Valid = true;
1330 ve.SourceElementOffset = state[i].src_offset;
1331 ve.SourceElementFormat = isl_format;
1332 ve.Component0Control = comp[0];
1333 ve.Component1Control = comp[1];
1334 ve.Component2Control = comp[2];
1335 ve.Component3Control = comp[3];
1336 }
1337
1338 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1339 vi.VertexElementIndex = i;
1340 vi.InstancingEnable = state[i].instance_divisor > 0;
1341 vi.InstanceDataStepRate = state[i].instance_divisor;
1342 }
1343
1344 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1345 }
1346
1347 return cso;
1348 }
1349
1350 static void
1351 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1352 {
1353 struct iris_context *ice = (struct iris_context *) ctx;
1354
1355 ice->state.cso_vertex_elements = state;
1356 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1357 }
1358
1359 static void *
1360 iris_create_compute_state(struct pipe_context *ctx,
1361 const struct pipe_compute_state *state)
1362 {
1363 return malloc(1);
1364 }
1365
1366 static struct pipe_stream_output_target *
1367 iris_create_stream_output_target(struct pipe_context *ctx,
1368 struct pipe_resource *res,
1369 unsigned buffer_offset,
1370 unsigned buffer_size)
1371 {
1372 struct pipe_stream_output_target *t =
1373 CALLOC_STRUCT(pipe_stream_output_target);
1374 if (!t)
1375 return NULL;
1376
1377 pipe_reference_init(&t->reference, 1);
1378 pipe_resource_reference(&t->buffer, res);
1379 t->buffer_offset = buffer_offset;
1380 t->buffer_size = buffer_size;
1381 return t;
1382 }
1383
1384 static void
1385 iris_stream_output_target_destroy(struct pipe_context *ctx,
1386 struct pipe_stream_output_target *t)
1387 {
1388 pipe_resource_reference(&t->buffer, NULL);
1389 free(t);
1390 }
1391
1392 static void
1393 iris_set_stream_output_targets(struct pipe_context *ctx,
1394 unsigned num_targets,
1395 struct pipe_stream_output_target **targets,
1396 const unsigned *offsets)
1397 {
1398 }
1399
1400 #if 0
1401 static void
1402 iris_compute_sbe(const struct iris_context *ice,
1403 const struct brw_wm_prog_data *wm_prog_data)
1404 {
1405 uint32_t sbe_map[GENX(3DSTATE_SBE_length)];
1406 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
1407
1408 unsigned urb_read_offset, urb_read_length;
1409 brw_compute_sbe_urb_slot_interval(fp->info.inputs_read,
1410 ice->shaders.last_vue_map,
1411 &urb_read_offset, &urb_read_length);
1412
1413 iris_pack_command(GENX(3DSTATE_SBE), sbe_map, sbe) {
1414 sbe.AttributeSwizzleEnable = true;
1415 sbe.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs;
1416 sbe.PointSpriteTextureCoordinateOrigin = cso_rast->sprite_coord_mode;
1417 sbe.VertexURBEntryReadOffset = urb_read_offset;
1418 sbe.VertexURBEntryReadLength = urb_read_length;
1419 sbe.ForceVertexURBEntryReadOffset = true;
1420 sbe.ForceVertexURBEntryReadLength = true;
1421 sbe.ConstantInterpolationEnable = wm_prog_data->flat_inputs;
1422
1423 for (int i = 0; i < urb_read_length * 2; i++) {
1424 sbe.AttributeActiveComponentFormat[i] = ACTIVE_COMPONENT_XYZW;
1425 }
1426 }
1427 }
1428 #endif
1429
1430 static void
1431 iris_bind_compute_state(struct pipe_context *ctx, void *state)
1432 {
1433 }
1434
1435 static void
1436 iris_populate_vs_key(const struct iris_context *ice,
1437 struct brw_vs_prog_key *key)
1438 {
1439 memset(key, 0, sizeof(*key));
1440 }
1441
1442 static void
1443 iris_populate_tcs_key(const struct iris_context *ice,
1444 struct brw_tcs_prog_key *key)
1445 {
1446 memset(key, 0, sizeof(*key));
1447 }
1448
1449 static void
1450 iris_populate_tes_key(const struct iris_context *ice,
1451 struct brw_tes_prog_key *key)
1452 {
1453 memset(key, 0, sizeof(*key));
1454 }
1455
1456 static void
1457 iris_populate_gs_key(const struct iris_context *ice,
1458 struct brw_gs_prog_key *key)
1459 {
1460 memset(key, 0, sizeof(*key));
1461 }
1462
1463 static void
1464 iris_populate_fs_key(const struct iris_context *ice,
1465 struct brw_wm_prog_key *key)
1466 {
1467 memset(key, 0, sizeof(*key));
1468
1469 /* XXX: dirty flags? */
1470 const struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
1471 const struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
1472 const struct iris_rasterizer_state *rast = ice->state.cso_rast;
1473 const struct iris_blend_state *blend = ice->state.cso_blend;
1474
1475 key->nr_color_regions = fb->nr_cbufs;
1476
1477 key->clamp_fragment_color = rast->clamp_fragment_color;
1478
1479 key->replicate_alpha = fb->nr_cbufs > 1 &&
1480 (zsa->alpha.enabled || blend->alpha_to_coverage);
1481
1482 // key->force_dual_color_blend for unigine
1483 #if 0
1484 if (cso_rast->multisample) {
1485 key->persample_interp =
1486 ctx->Multisample.SampleShading &&
1487 (ctx->Multisample.MinSampleShadingValue *
1488 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
1489
1490 key->multisample_fbo = fb->samples > 1;
1491 }
1492 #endif
1493
1494 key->coherent_fb_fetch = true;
1495 }
1496
1497 //pkt.SamplerCount = \
1498 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1499 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1500 //ffs(stage_state->per_thread_scratch) - 11; \
1501
1502 static uint64_t
1503 KSP(const struct iris_compiled_shader *shader)
1504 {
1505 struct iris_resource *res = (void *) shader->buffer;
1506 return res->bo->gtt_offset + shader->offset;
1507 }
1508
1509 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1510 pkt.KernelStartPointer = KSP(shader); \
1511 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1512 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1513 \
1514 pkt.DispatchGRFStartRegisterForURBData = \
1515 prog_data->dispatch_grf_start_reg; \
1516 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1517 pkt.prefix##URBEntryReadOffset = 0; \
1518 \
1519 pkt.StatisticsEnable = true; \
1520 pkt.Enable = true;
1521
1522 static void
1523 iris_set_vs_state(const struct gen_device_info *devinfo,
1524 struct iris_compiled_shader *shader)
1525 {
1526 struct brw_stage_prog_data *prog_data = shader->prog_data;
1527 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1528
1529 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
1530 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
1531 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1532 vs.SIMD8DispatchEnable = true;
1533 vs.UserClipDistanceCullTestEnableBitmask =
1534 vue_prog_data->cull_distance_mask;
1535 }
1536 }
1537
1538 static void
1539 iris_set_tcs_state(const struct gen_device_info *devinfo,
1540 struct iris_compiled_shader *shader)
1541 {
1542 struct brw_stage_prog_data *prog_data = shader->prog_data;
1543 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1544 struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
1545
1546 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
1547 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
1548
1549 hs.InstanceCount = tcs_prog_data->instances - 1;
1550 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1551 hs.IncludeVertexHandles = true;
1552 }
1553 }
1554
1555 static void
1556 iris_set_tes_state(const struct gen_device_info *devinfo,
1557 struct iris_compiled_shader *shader)
1558 {
1559 struct brw_stage_prog_data *prog_data = shader->prog_data;
1560 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1561 struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
1562
1563 uint32_t *te_state = (void *) shader->derived_data;
1564 uint32_t *ds_state = te_state + GENX(3DSTATE_TE_length);
1565
1566 iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
1567 te.Partitioning = tes_prog_data->partitioning;
1568 te.OutputTopology = tes_prog_data->output_topology;
1569 te.TEDomain = tes_prog_data->domain;
1570 te.TEEnable = true;
1571 te.MaximumTessellationFactorOdd = 63.0;
1572 te.MaximumTessellationFactorNotOdd = 64.0;
1573 }
1574
1575 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
1576 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
1577
1578 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
1579 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1580 ds.ComputeWCoordinateEnable =
1581 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1582
1583 ds.UserClipDistanceCullTestEnableBitmask =
1584 vue_prog_data->cull_distance_mask;
1585 }
1586
1587 }
1588
1589 static void
1590 iris_set_gs_state(const struct gen_device_info *devinfo,
1591 struct iris_compiled_shader *shader)
1592 {
1593 struct brw_stage_prog_data *prog_data = shader->prog_data;
1594 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1595 struct brw_gs_prog_data *gs_prog_data = (void *) prog_data;
1596
1597 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) {
1598 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
1599
1600 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1601 gs.OutputTopology = gs_prog_data->output_topology;
1602 gs.ControlDataHeaderSize =
1603 gs_prog_data->control_data_header_size_hwords;
1604 gs.InstanceControl = gs_prog_data->invocations - 1;
1605 gs.DispatchMode = SIMD8;
1606 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1607 gs.ControlDataFormat = gs_prog_data->control_data_format;
1608 gs.ReorderMode = TRAILING;
1609 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1610 gs.MaximumNumberofThreads =
1611 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
1612 : (devinfo->max_gs_threads - 1);
1613
1614 if (gs_prog_data->static_vertex_count != -1) {
1615 gs.StaticOutput = true;
1616 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
1617 }
1618 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
1619
1620 gs.UserClipDistanceCullTestEnableBitmask =
1621 vue_prog_data->cull_distance_mask;
1622
1623 const int urb_entry_write_offset = 1;
1624 const uint32_t urb_entry_output_length =
1625 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
1626 urb_entry_write_offset;
1627
1628 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
1629 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
1630 }
1631 }
1632
1633 static void
1634 iris_set_fs_state(const struct gen_device_info *devinfo,
1635 struct iris_compiled_shader *shader)
1636 {
1637 struct brw_stage_prog_data *prog_data = shader->prog_data;
1638 struct brw_wm_prog_data *wm_prog_data = (void *) shader->prog_data;
1639
1640 uint32_t *ps_state = (void *) shader->derived_data;
1641 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length);
1642
1643 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
1644 ps.VectorMaskEnable = true;
1645 //ps.SamplerCount = ...
1646 ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
1647 ps.FloatingPointMode = prog_data->use_alt_mode;
1648 ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
1649
1650 ps.PushConstantEnable = prog_data->nr_params > 0 ||
1651 prog_data->ubo_ranges[0].length > 0;
1652
1653 /* From the documentation for this packet:
1654 * "If the PS kernel does not need the Position XY Offsets to
1655 * compute a Position Value, then this field should be programmed
1656 * to POSOFFSET_NONE."
1657 *
1658 * "SW Recommendation: If the PS kernel needs the Position Offsets
1659 * to compute a Position XY value, this field should match Position
1660 * ZW Interpolation Mode to ensure a consistent position.xyzw
1661 * computation."
1662 *
1663 * We only require XY sample offsets. So, this recommendation doesn't
1664 * look useful at the moment. We might need this in future.
1665 */
1666 ps.PositionXYOffsetSelect =
1667 wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
1668 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1669 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1670 ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1671
1672 // XXX: Disable SIMD32 with 16x MSAA
1673
1674 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1675 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
1676 ps.DispatchGRFStartRegisterForConstantSetupData1 =
1677 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
1678 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1679 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
1680
1681 ps.KernelStartPointer0 =
1682 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
1683 ps.KernelStartPointer1 =
1684 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
1685 ps.KernelStartPointer2 =
1686 KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
1687 }
1688
1689 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
1690 psx.PixelShaderValid = true;
1691 psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1692 psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
1693 psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
1694 psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1695 psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1696 psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1697
1698 if (wm_prog_data->uses_sample_mask) {
1699 /* TODO: conservative rasterization */
1700 if (wm_prog_data->post_depth_coverage)
1701 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
1702 else
1703 psx.InputCoverageMaskState = ICMS_NORMAL;
1704 }
1705
1706 psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1707 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1708 psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
1709
1710 // XXX: UAV bit
1711 }
1712 }
1713
1714 static unsigned
1715 iris_derived_program_state_size(enum iris_program_cache_id cache_id)
1716 {
1717 assert(cache_id <= IRIS_CACHE_CS);
1718
1719 static const unsigned dwords[] = {
1720 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length),
1721 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length),
1722 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length),
1723 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length),
1724 [IRIS_CACHE_FS] =
1725 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length),
1726 [IRIS_CACHE_CS] = 0,
1727 [IRIS_CACHE_BLORP_BLIT] = 0,
1728 };
1729
1730 return sizeof(uint32_t) * dwords[cache_id];
1731 }
1732
1733 static void
1734 iris_set_derived_program_state(const struct gen_device_info *devinfo,
1735 enum iris_program_cache_id cache_id,
1736 struct iris_compiled_shader *shader)
1737 {
1738 switch (cache_id) {
1739 case IRIS_CACHE_VS:
1740 iris_set_vs_state(devinfo, shader);
1741 break;
1742 case IRIS_CACHE_TCS:
1743 iris_set_tcs_state(devinfo, shader);
1744 break;
1745 case IRIS_CACHE_TES:
1746 iris_set_tes_state(devinfo, shader);
1747 break;
1748 case IRIS_CACHE_GS:
1749 iris_set_gs_state(devinfo, shader);
1750 break;
1751 case IRIS_CACHE_FS:
1752 iris_set_fs_state(devinfo, shader);
1753 break;
1754 case IRIS_CACHE_CS:
1755 break;
1756 default:
1757 break;
1758 }
1759 }
1760
1761 static void
1762 iris_upload_urb_config(struct iris_context *ice, struct iris_batch *batch)
1763 {
1764 const struct gen_device_info *devinfo = &batch->screen->devinfo;
1765 const unsigned push_size_kB = 32;
1766 unsigned entries[4];
1767 unsigned start[4];
1768 unsigned size[4];
1769
1770 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1771 if (!ice->shaders.prog[i]) {
1772 size[i] = 1;
1773 } else {
1774 struct brw_vue_prog_data *vue_prog_data =
1775 (void *) ice->shaders.prog[i]->prog_data;
1776 size[i] = vue_prog_data->urb_entry_size;
1777 }
1778 assert(size[i] != 0);
1779 }
1780
1781 gen_get_urb_config(devinfo, 1024 * push_size_kB,
1782 1024 * ice->shaders.urb_size,
1783 ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
1784 ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
1785 size, entries, start);
1786
1787 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
1788 iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
1789 urb._3DCommandSubOpcode += i;
1790 urb.VSURBStartingAddress = start[i];
1791 urb.VSURBEntryAllocationSize = size[i] - 1;
1792 urb.VSNumberofURBEntries = entries[i];
1793 }
1794 }
1795 }
1796
1797 static const uint32_t push_constant_opcodes[] = {
1798 [MESA_SHADER_VERTEX] = 21,
1799 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
1800 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
1801 [MESA_SHADER_GEOMETRY] = 22,
1802 [MESA_SHADER_FRAGMENT] = 23,
1803 [MESA_SHADER_COMPUTE] = 0,
1804 };
1805
1806 static uint32_t
1807 emit_patched_surface_state(struct iris_batch *batch,
1808 uint32_t *surface_state,
1809 const struct iris_resource *res,
1810 unsigned reloc_flags)
1811 {
1812 const int num_dwords = GENX(RENDER_SURFACE_STATE_length);
1813 uint32_t offset;
1814 uint32_t *dw = iris_alloc_state(batch, 4 * num_dwords, 64, &offset);
1815
1816 STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) % 32 == 0);
1817 int addr_idx = GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) / 32;
1818 for (uint32_t i = 0; i < addr_idx; i++)
1819 dw[i] = surface_state[i];
1820
1821 uint64_t *qw = (uint64_t *) &dw[addr_idx];
1822 // XXX: mt->offset, if needed
1823 *qw = iris_state_reloc(batch, (void *)qw - batch->statebuf.map, res->bo,
1824 surface_state[addr_idx + 1], reloc_flags);
1825
1826 for (uint32_t i = addr_idx + 1; i < num_dwords; i++)
1827 dw[i] = surface_state[i];
1828
1829 return offset;
1830 }
1831
1832 static void
1833 iris_upload_render_state(struct iris_context *ice,
1834 struct iris_batch *batch,
1835 const struct pipe_draw_info *draw)
1836 {
1837 const uint64_t dirty = ice->state.dirty;
1838
1839 struct brw_wm_prog_data *wm_prog_data = (void *)
1840 ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
1841
1842 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1843 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1844 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1845 ptr.CCViewportPointer =
1846 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1847 }
1848 }
1849
1850 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1851 struct iris_viewport_state *cso = ice->state.cso_vp;
1852 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1853 ptr.SFClipViewportPointer =
1854 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1855 }
1856 }
1857
1858 /* XXX: L3 State */
1859
1860 if (dirty & IRIS_DIRTY_URB) {
1861 iris_upload_urb_config(ice, batch);
1862 }
1863
1864 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1865 struct iris_blend_state *cso_blend = ice->state.cso_blend;
1866 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1867 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
1868 const int num_dwords = 4 * (GENX(BLEND_STATE_length) +
1869 cso_fb->nr_cbufs * GENX(BLEND_STATE_ENTRY_length));
1870 uint32_t blend_offset;
1871 uint32_t *blend_map =
1872 iris_alloc_state(batch, num_dwords, 64, &blend_offset);
1873
1874 uint32_t blend_state_header;
1875 iris_pack_state(GENX(BLEND_STATE), &blend_state_header, bs) {
1876 bs.AlphaTestEnable = cso_zsa->alpha.enabled;
1877 bs.AlphaTestFunction = translate_compare_func(cso_zsa->alpha.func);
1878 }
1879
1880 blend_map[0] = blend_state_header | cso_blend->blend_state[0];
1881 memcpy(&blend_map[1], &cso_blend->blend_state[1],
1882 sizeof(cso_blend->blend_state) - sizeof(uint32_t));
1883
1884 iris_emit_cmd(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) {
1885 ptr.BlendStatePointer = blend_offset;
1886 ptr.BlendStatePointerValid = true;
1887 }
1888 }
1889
1890 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1891 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1892 uint32_t cc_offset;
1893 void *cc_map =
1894 iris_alloc_state(batch,
1895 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1896 64, &cc_offset);
1897 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1898 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1899 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1900 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1901 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1902 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1903 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1904 }
1905 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1906 ptr.ColorCalcStatePointer = cc_offset;
1907 ptr.ColorCalcStatePointerValid = true;
1908 }
1909 }
1910
1911 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1912 if (!(dirty & (IRIS_DIRTY_CONSTANTS_VS << stage)))
1913 continue;
1914
1915 iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
1916 pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
1917 if (ice->shaders.prog[stage]) {
1918 // XXX: 3DSTATE_CONSTANT_XS
1919 }
1920 }
1921 }
1922
1923 // Surfaces:
1924 // - pull constants
1925 // - ubos/ssbos/abos
1926 // - images
1927 // - textures
1928 // - render targets - write and read
1929 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
1930
1931 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1932 struct iris_compiled_shader *shader = ice->shaders.prog[stage];
1933 if (!shader) // XXX: dirty bits...also, emit a disable maybe?
1934 continue;
1935
1936 struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
1937 uint32_t bt_offset = 0;
1938 uint32_t *bt_map = NULL;
1939
1940 if (prog_data->binding_table.size_bytes != 0) {
1941 bt_map = iris_alloc_state(batch, prog_data->binding_table.size_bytes,
1942 64, &bt_offset);
1943 }
1944
1945 iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) {
1946 ptr._3DCommandSubOpcode = 38 + stage;
1947 ptr.PointertoVSBindingTable = bt_offset;
1948 }
1949
1950 if (stage == MESA_SHADER_FRAGMENT) {
1951 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1952 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
1953 struct iris_surface *surf = (void *) cso_fb->cbufs[i];
1954 struct iris_resource *res = (void *) surf->pipe.texture;
1955
1956 *bt_map++ = emit_patched_surface_state(batch, surf->surface_state,
1957 res, RELOC_WRITE);
1958 }
1959 }
1960 }
1961
1962 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1963 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)) ||
1964 !ice->shaders.prog[stage])
1965 continue;
1966
1967 // XXX: get sampler count from shader; don't emit them all...
1968 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1969
1970 uint32_t offset;
1971 uint32_t *map = iris_alloc_state(batch,
1972 count * 4 * GENX(SAMPLER_STATE_length),
1973 32, &offset);
1974
1975 for (int i = 0; i < count; i++) {
1976 // XXX: when we have a correct count, these better be bound
1977 if (!ice->state.samplers[stage][i])
1978 continue;
1979 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1980 4 * GENX(SAMPLER_STATE_length));
1981 map += GENX(SAMPLER_STATE_length);
1982 }
1983
1984 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1985 ptr._3DCommandSubOpcode = 43 + stage;
1986 ptr.PointertoVSSamplerState = offset;
1987 }
1988 }
1989
1990 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1991 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1992 ms.PixelLocation =
1993 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1994 if (ice->state.framebuffer.samples > 0)
1995 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1996 }
1997 }
1998
1999 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
2000 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
2001 ms.SampleMask = ice->state.sample_mask;
2002 }
2003 }
2004
2005 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
2006 if (!(dirty & (IRIS_DIRTY_VS << stage)))
2007 continue;
2008
2009 struct iris_compiled_shader *shader = ice->shaders.prog[stage];
2010
2011 if (shader) {
2012 struct iris_resource *cache = (void *) shader->buffer;
2013 iris_use_pinned_bo(batch, cache->bo);
2014 iris_batch_emit(batch, shader->derived_data,
2015 iris_derived_program_state_size(stage));
2016 } else {
2017 if (stage == MESA_SHADER_TESS_EVAL) {
2018 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
2019 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
2020 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
2021 } else if (stage == MESA_SHADER_GEOMETRY) {
2022 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
2023 }
2024 }
2025 }
2026
2027 // XXX: SOL:
2028 // 3DSTATE_STREAMOUT
2029 // 3DSTATE_SO_BUFFER
2030 // 3DSTATE_SO_DECL_LIST
2031
2032 if (dirty & IRIS_DIRTY_CLIP) {
2033 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
2034 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
2035
2036 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
2037 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
2038 if (wm_prog_data->barycentric_interp_modes &
2039 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
2040 cl.NonPerspectiveBarycentricEnable = true;
2041
2042 cl.ForceZeroRTAIndexEnable = cso_fb->layers == 0;
2043 }
2044 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
2045 ARRAY_SIZE(cso_rast->clip));
2046 }
2047
2048 if (dirty & IRIS_DIRTY_RASTER) {
2049 struct iris_rasterizer_state *cso = ice->state.cso_rast;
2050 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
2051 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
2052
2053 }
2054
2055 if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_FS)) {
2056 struct iris_rasterizer_state *cso = ice->state.cso_rast;
2057 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
2058
2059 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) {
2060 wm.BarycentricInterpolationMode =
2061 wm_prog_data->barycentric_interp_modes;
2062
2063 if (wm_prog_data->early_fragment_tests)
2064 wm.EarlyDepthStencilControl = EDSC_PREPS;
2065 else if (wm_prog_data->has_side_effects)
2066 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
2067 }
2068 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
2069 }
2070
2071 if (1) {
2072 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2073 // -> iris_raster_state (point sprite texture coordinate origin)
2074 // -> bunch of shader state...
2075 iris_emit_cmd(batch, GENX(3DSTATE_SBE), sbe) {
2076 }
2077 iris_emit_cmd(batch, GENX(3DSTATE_SBE_SWIZ), sbe) {
2078 }
2079 }
2080
2081 if (dirty & IRIS_DIRTY_PS_BLEND) {
2082 struct iris_blend_state *cso_blend = ice->state.cso_blend;
2083 struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
2084 uint32_t dynamic_pb[GENX(3DSTATE_PS_BLEND_length)];
2085 iris_pack_command(GENX(3DSTATE_PS_BLEND), &dynamic_pb, pb) {
2086 pb.HasWriteableRT = true; // XXX: comes from somewhere :(
2087 pb.AlphaTestEnable = cso_zsa->alpha.enabled;
2088 }
2089
2090 iris_emit_merge(batch, cso_blend->ps_blend, dynamic_pb,
2091 ARRAY_SIZE(cso_blend->ps_blend));
2092 }
2093
2094 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
2095 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
2096 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
2097
2098 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
2099 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
2100 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
2101 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
2102 }
2103 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
2104 }
2105
2106 if (dirty & IRIS_DIRTY_SCISSOR) {
2107 uint32_t scissor_offset =
2108 iris_emit_state(batch, ice->state.scissors,
2109 sizeof(struct pipe_scissor_state) *
2110 ice->state.num_scissors, 32);
2111
2112 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
2113 ptr.ScissorRectPointer = scissor_offset;
2114 }
2115 }
2116
2117 // XXX: 3DSTATE_DEPTH_BUFFER
2118 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
2119 // XXX: 3DSTATE_STENCIL_BUFFER
2120 // XXX: 3DSTATE_CLEAR_PARAMS
2121
2122 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
2123 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
2124 for (int i = 0; i < 32; i++) {
2125 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
2126 }
2127 }
2128 }
2129
2130 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
2131 struct iris_rasterizer_state *cso = ice->state.cso_rast;
2132 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
2133 }
2134
2135 if (1) {
2136 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
2137 topo.PrimitiveTopologyType =
2138 translate_prim_type(draw->mode, draw->vertices_per_patch);
2139 }
2140 }
2141
2142 if (draw->index_size > 0) {
2143 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
2144
2145 assert(!draw->has_user_indices);
2146
2147 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
2148 ib.IndexFormat = draw->index_size;
2149 ib.MOCS = MOCS_WB;
2150 ib.BufferSize = res->bo->size;
2151 ib.BufferStartingAddress = ro_bo(res->bo, 0);
2152 }
2153 }
2154
2155 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
2156 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
2157
2158 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
2159 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
2160
2161 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
2162 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
2163 uint32_t *delta = cso->vertex_buffers +
2164 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
2165
2166 iris_batch_emit(batch, cso->vertex_buffers,
2167 sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
2168
2169 for (unsigned i = 0; i < cso->num_buffers; i++) {
2170 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
2171 cso->bos[i].bo, cso->bos[i].offset +
2172 *delta, cso->bos[i].reloc_flags);
2173 addr = (void *) addr + 16;
2174 delta = (void *) delta + 16;
2175 }
2176 }
2177
2178 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
2179 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
2180 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
2181 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
2182 for (int i = 0; i < cso->count; i++) {
2183 iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
2184 (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
2185 }
2186 for (int i = 0; i < cso->count; i++) {
2187 /* TODO: vertexid, instanceid support */
2188 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
2189 }
2190 }
2191
2192 if (1) {
2193 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
2194 if (draw->primitive_restart) {
2195 vf.IndexedDrawCutIndexEnable = true;
2196 vf.CutIndex = draw->restart_index;
2197 }
2198 }
2199 }
2200
2201 // XXX: Gen8 - PMA fix
2202
2203 assert(!draw->indirect); // XXX: indirect support
2204
2205 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
2206 prim.StartInstanceLocation = draw->start_instance;
2207 prim.InstanceCount = draw->instance_count;
2208 prim.VertexCountPerInstance = draw->count;
2209 prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
2210
2211 // XXX: this is probably bonkers.
2212 prim.StartVertexLocation = draw->start;
2213
2214 if (draw->index_size) {
2215 prim.BaseVertexLocation += draw->index_bias;
2216 } else {
2217 prim.StartVertexLocation += draw->index_bias;
2218 }
2219
2220 //prim.BaseVertexLocation = ...;
2221 }
2222 }
2223
2224 static void
2225 iris_destroy_state(struct iris_context *ice)
2226 {
2227 // XXX: unreference resources/surfaces.
2228 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
2229 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
2230 }
2231 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
2232 }
2233
2234 void
2235 genX(init_state)(struct iris_context *ice)
2236 {
2237 struct pipe_context *ctx = &ice->ctx;
2238
2239 ctx->create_blend_state = iris_create_blend_state;
2240 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
2241 ctx->create_rasterizer_state = iris_create_rasterizer_state;
2242 ctx->create_sampler_state = iris_create_sampler_state;
2243 ctx->create_sampler_view = iris_create_sampler_view;
2244 ctx->create_surface = iris_create_surface;
2245 ctx->create_vertex_elements_state = iris_create_vertex_elements;
2246 ctx->create_compute_state = iris_create_compute_state;
2247 ctx->bind_blend_state = iris_bind_blend_state;
2248 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
2249 ctx->bind_sampler_states = iris_bind_sampler_states;
2250 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
2251 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
2252 ctx->bind_compute_state = iris_bind_compute_state;
2253 ctx->delete_blend_state = iris_delete_state;
2254 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
2255 ctx->delete_fs_state = iris_delete_state;
2256 ctx->delete_rasterizer_state = iris_delete_state;
2257 ctx->delete_sampler_state = iris_delete_state;
2258 ctx->delete_vertex_elements_state = iris_delete_state;
2259 ctx->delete_compute_state = iris_delete_state;
2260 ctx->delete_tcs_state = iris_delete_state;
2261 ctx->delete_tes_state = iris_delete_state;
2262 ctx->delete_gs_state = iris_delete_state;
2263 ctx->delete_vs_state = iris_delete_state;
2264 ctx->set_blend_color = iris_set_blend_color;
2265 ctx->set_clip_state = iris_set_clip_state;
2266 ctx->set_constant_buffer = iris_set_constant_buffer;
2267 ctx->set_sampler_views = iris_set_sampler_views;
2268 ctx->set_framebuffer_state = iris_set_framebuffer_state;
2269 ctx->set_polygon_stipple = iris_set_polygon_stipple;
2270 ctx->set_sample_mask = iris_set_sample_mask;
2271 ctx->set_scissor_states = iris_set_scissor_states;
2272 ctx->set_stencil_ref = iris_set_stencil_ref;
2273 ctx->set_vertex_buffers = iris_set_vertex_buffers;
2274 ctx->set_viewport_states = iris_set_viewport_states;
2275 ctx->sampler_view_destroy = iris_sampler_view_destroy;
2276 ctx->surface_destroy = iris_surface_destroy;
2277 ctx->draw_vbo = iris_draw_vbo;
2278 ctx->launch_grid = iris_launch_grid;
2279 ctx->create_stream_output_target = iris_create_stream_output_target;
2280 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
2281 ctx->set_stream_output_targets = iris_set_stream_output_targets;
2282
2283 ice->state.destroy_state = iris_destroy_state;
2284 ice->state.init_render_context = iris_init_render_context;
2285 ice->state.upload_render_state = iris_upload_render_state;
2286 ice->state.derived_program_state_size = iris_derived_program_state_size;
2287 ice->state.set_derived_program_state = iris_set_derived_program_state;
2288 ice->state.populate_vs_key = iris_populate_vs_key;
2289 ice->state.populate_tcs_key = iris_populate_tcs_key;
2290 ice->state.populate_tes_key = iris_populate_tes_key;
2291 ice->state.populate_gs_key = iris_populate_gs_key;
2292 ice->state.populate_fs_key = iris_populate_fs_key;
2293
2294
2295 ice->state.dirty = ~0ull;
2296 }