2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * ============================= GENXML CODE =============================
28 * [This file is compiled once per generation.]
29 * =======================================================================
31 * This is the main state upload code.
33 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
34 * complex, or highly reusable state can be created once, and bound and
35 * rebound multiple times. This is modeled with the pipe->create_*_state()
36 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
37 * streamed out on the fly, via pipe->set_*_state() hooks.
39 * OpenGL involves frequently mutating context state, which is mirrored in
40 * core Mesa by highly mutable data structures. However, most applications
41 * typically draw the same things over and over - from frame to frame, most
42 * of the same objects are still visible and need to be redrawn. So, rather
43 * than inventing new state all the time, applications usually mutate to swap
44 * between known states that we've seen before.
46 * Gallium isolates us from this mutation by tracking API state, and
47 * distilling it into a set of Constant State Objects, or CSOs. Large,
48 * complex, or typically reusable state can be created once, then reused
49 * multiple times. Drivers can create and store their own associated data.
50 * This create/bind model corresponds to the pipe->create_*_state() and
51 * pipe->bind_*_state() driver hooks.
53 * Some state is cheap to create, or expected to be highly dynamic. Rather
54 * than creating and caching piles of CSOs for these, Gallium simply streams
55 * them out, via the pipe->set_*_state() driver hooks.
57 * To reduce draw time overhead, we try to compute as much state at create
58 * time as possible. Wherever possible, we translate the Gallium pipe state
59 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
60 * we can simply memcpy them into a batch buffer.
62 * No hardware matches the abstraction perfectly, so some commands require
63 * information from multiple CSOs. In this case, we can store two copies
64 * of the packet (one in each CSO), and simply | together their DWords at
65 * draw time. Sometimes the second set is trivial (one or two fields), so
66 * we simply pack it at draw time.
68 * There are two main components in the file below. First, the CSO hooks
69 * create/bind/track state. The second are the draw-time upload functions,
70 * iris_upload_render_state() and iris_upload_compute_state(), which read
71 * the context state and emit the commands into the actual batch.
82 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
88 #include "pipe/p_defines.h"
89 #include "pipe/p_state.h"
90 #include "pipe/p_context.h"
91 #include "pipe/p_screen.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_pipe.h"
106 #include "iris_resource.h"
108 #define __gen_address_type struct iris_address
109 #define __gen_user_data struct iris_batch
111 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
114 __gen_combine_address(struct iris_batch
*batch
, void *location
,
115 struct iris_address addr
, uint32_t delta
)
117 uint64_t result
= addr
.offset
+ delta
;
120 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
121 /* Assume this is a general address, not relative to a base. */
122 result
+= addr
.bo
->gtt_offset
;
128 #define __genxml_cmd_length(cmd) cmd ## _length
129 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
130 #define __genxml_cmd_header(cmd) cmd ## _header
131 #define __genxml_cmd_pack(cmd) cmd ## _pack
133 #define _iris_pack_command(batch, cmd, dst, name) \
134 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
135 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
136 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
140 #define iris_pack_command(cmd, dst, name) \
141 _iris_pack_command(NULL, cmd, dst, name)
143 #define iris_pack_state(cmd, dst, name) \
144 for (struct cmd name = {}, \
145 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
146 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
149 #define iris_emit_cmd(batch, cmd, name) \
150 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
152 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
154 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
155 for (uint32_t i = 0; i < num_dwords; i++) \
156 dw[i] = (dwords0)[i] | (dwords1)[i]; \
157 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
160 #include "genxml/genX_pack.h"
161 #include "genxml/gen_macros.h"
162 #include "genxml/genX_bits.h"
164 #define MOCS_WB (2 << 1)
167 * Statically assert that PIPE_* enums match the hardware packets.
168 * (As long as they match, we don't need to translate them.)
170 UNUSED
static void pipe_asserts()
172 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
174 /* pipe_logicop happens to match the hardware. */
175 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
176 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
177 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
179 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
180 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
181 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
182 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
183 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
184 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
185 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
186 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
187 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
189 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
190 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
192 /* pipe_blend_func happens to match the hardware. */
193 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
213 /* pipe_blend_func happens to match the hardware. */
214 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
215 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
217 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
218 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
220 /* pipe_stencil_op happens to match the hardware. */
221 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
228 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
230 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
231 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
232 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
237 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
239 static const unsigned map
[] = {
240 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
241 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
242 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
243 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
244 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
245 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
246 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
247 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
248 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
249 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
250 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
251 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
252 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
253 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
254 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
257 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
261 translate_compare_func(enum pipe_compare_func pipe_func
)
263 static const unsigned map
[] = {
264 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
265 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
266 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
267 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
268 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
269 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
270 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
271 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
273 return map
[pipe_func
];
277 translate_shadow_func(enum pipe_compare_func pipe_func
)
279 /* Gallium specifies the result of shadow comparisons as:
281 * 1 if ref <op> texel,
286 * 0 if texel <op> ref,
289 * So we need to flip the operator and also negate.
291 static const unsigned map
[] = {
292 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
293 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
294 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
295 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
296 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
297 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
298 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
299 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
301 return map
[pipe_func
];
305 translate_cull_mode(unsigned pipe_face
)
307 static const unsigned map
[4] = {
308 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
309 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
310 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
311 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
313 return map
[pipe_face
];
317 translate_fill_mode(unsigned pipe_polymode
)
319 static const unsigned map
[4] = {
320 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
321 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
322 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
323 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
325 return map
[pipe_polymode
];
329 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
331 static const unsigned map
[] = {
332 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
333 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
334 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
336 return map
[pipe_mip
];
340 translate_wrap(unsigned pipe_wrap
)
342 static const unsigned map
[] = {
343 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
344 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
345 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
346 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
347 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
348 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
350 /* These are unsupported. */
351 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
352 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
354 return map
[pipe_wrap
];
357 static struct iris_address
358 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
360 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
361 * validation list at CSO creation time, instead of draw time.
363 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
366 static struct iris_address
367 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
369 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
370 * validation list at CSO creation time, instead of draw time.
372 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
376 * Allocate space for some indirect state.
378 * Return a pointer to the map (to fill it out) and a state ref (for
379 * referring to the state in GPU commands).
382 upload_state(struct u_upload_mgr
*uploader
,
383 struct iris_state_ref
*ref
,
388 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
393 * Stream out temporary/short-lived state.
395 * This allocates space, pins the BO, and includes the BO address in the
396 * returned offset (which works because all state lives in 32-bit memory
400 stream_state(struct iris_batch
*batch
,
401 struct u_upload_mgr
*uploader
,
402 struct pipe_resource
**out_res
,
405 uint32_t *out_offset
)
409 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
411 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
412 iris_use_pinned_bo(batch
, bo
, false);
414 *out_offset
+= iris_bo_offset_from_base_address(bo
);
420 * stream_state() + memcpy.
423 emit_state(struct iris_batch
*batch
,
424 struct u_upload_mgr
*uploader
,
425 struct pipe_resource
**out_res
,
432 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
435 memcpy(map
, data
, size
);
441 * Did field 'x' change between 'old_cso' and 'new_cso'?
443 * (If so, we may want to set some dirty flags.)
445 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
446 #define cso_changed_memcmp(x) \
447 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
450 * Upload the initial GPU state for a render context.
452 * This sets some invariant state that needs to be programmed a particular
453 * way, but we never actually change.
456 iris_init_render_context(struct iris_screen
*screen
,
457 struct iris_batch
*batch
,
458 struct iris_vtable
*vtbl
,
459 struct pipe_debug_callback
*dbg
)
461 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
463 /* XXX: PIPE_CONTROLs */
465 /* We program STATE_BASE_ADDRESS once at context initialization time.
466 * Each base address points at a 4GB memory zone, and never needs to
467 * change. See iris_bufmgr.h for a description of the memory zones.
469 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
471 // XXX: MOCS is stupid for this.
472 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
473 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
474 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
475 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
476 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
477 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
478 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
481 sba
.GeneralStateBaseAddressModifyEnable
= true;
482 sba
.SurfaceStateBaseAddressModifyEnable
= true;
483 sba
.DynamicStateBaseAddressModifyEnable
= true;
484 sba
.IndirectObjectBaseAddressModifyEnable
= true;
485 sba
.InstructionBaseAddressModifyEnable
= true;
486 sba
.GeneralStateBufferSizeModifyEnable
= true;
487 sba
.DynamicStateBufferSizeModifyEnable
= true;
488 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
489 sba
.IndirectObjectBufferSizeModifyEnable
= true;
490 sba
.InstructionBuffersizeModifyEnable
= true;
492 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
493 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
494 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
496 sba
.GeneralStateBufferSize
= 0xfffff;
497 sba
.IndirectObjectBufferSize
= 0xfffff;
498 sba
.InstructionBufferSize
= 0xfffff;
499 sba
.DynamicStateBufferSize
= 0xfffff;
502 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
503 * changing it dynamically. We set it to the maximum size here, and
504 * instead include the render target dimensions in the viewport, so
505 * viewport extents clipping takes care of pruning stray geometry.
507 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
508 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
509 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
512 /* Set the initial MSAA sample positions. */
513 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
514 GEN_SAMPLE_POS_1X(pat
._1xSample
);
515 GEN_SAMPLE_POS_2X(pat
._2xSample
);
516 GEN_SAMPLE_POS_4X(pat
._4xSample
);
517 GEN_SAMPLE_POS_8X(pat
._8xSample
);
518 GEN_SAMPLE_POS_16X(pat
._16xSample
);
521 /* Use the legacy AA line coverage computation. */
522 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
524 /* Disable chromakeying (it's for media) */
525 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
527 /* We want regular rendering, not special HiZ operations. */
528 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
530 /* No polygon stippling offsets are necessary. */
531 // XXX: may need to set an offset for origin-UL framebuffers
532 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
534 /* Set a static partitioning of the push constant area. */
535 // XXX: this may be a bad idea...could starve the push ringbuffers...
536 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
537 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
538 alloc
._3DCommandSubOpcode
= 18 + i
;
539 alloc
.ConstantBufferOffset
= 6 * i
;
540 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
545 struct iris_vertex_buffer_state
{
546 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
547 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
549 /** The resource to source vertex data from. */
550 struct pipe_resource
*resources
[33];
552 /** The number of bound vertex buffers. */
553 unsigned num_buffers
;
556 struct iris_depth_buffer_state
{
557 /* Depth/HiZ/Stencil related hardware packets. */
558 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
559 GENX(3DSTATE_STENCIL_BUFFER_length
) +
560 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
561 GENX(3DSTATE_CLEAR_PARAMS_length
)];
565 * Generation-specific context state (ice->state.genx->...).
567 * Most state can go in iris_context directly, but these encode hardware
568 * packets which vary by generation.
570 struct iris_genx_state
{
571 /** SF_CLIP_VIEWPORT */
572 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
574 struct iris_vertex_buffer_state vertex_buffers
;
575 struct iris_depth_buffer_state depth_buffer
;
577 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
578 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
581 // XXX: move this to iris_draw.c
583 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
588 * The pipe->set_blend_color() driver hook.
590 * This corresponds to our COLOR_CALC_STATE.
593 iris_set_blend_color(struct pipe_context
*ctx
,
594 const struct pipe_blend_color
*state
)
596 struct iris_context
*ice
= (struct iris_context
*) ctx
;
598 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
599 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
600 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
604 * Gallium CSO for blend state (see pipe_blend_state).
606 struct iris_blend_state
{
607 /** Partial 3DSTATE_PS_BLEND */
608 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
610 /** Partial BLEND_STATE */
611 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
612 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
614 bool alpha_to_coverage
; /* for shader key */
618 * The pipe->create_blend_state() driver hook.
620 * Translates a pipe_blend_state into iris_blend_state.
623 iris_create_blend_state(struct pipe_context
*ctx
,
624 const struct pipe_blend_state
*state
)
626 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
627 uint32_t *blend_state
= cso
->blend_state
;
629 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
631 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
632 /* pb.HasWriteableRT is filled in at draw time. */
633 /* pb.AlphaTestEnable is filled in at draw time. */
634 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
635 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
637 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
639 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
640 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
641 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
642 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
645 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
646 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
647 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
648 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
649 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
650 bs
.ColorDitherEnable
= state
->dither
;
651 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
654 blend_state
+= GENX(BLEND_STATE_length
);
656 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
657 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
658 be
.LogicOpEnable
= state
->logicop_enable
;
659 be
.LogicOpFunction
= state
->logicop_func
;
661 be
.PreBlendSourceOnlyClampEnable
= false;
662 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
663 be
.PreBlendColorClampEnable
= true;
664 be
.PostBlendColorClampEnable
= true;
666 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
668 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
669 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
670 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
671 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
672 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
673 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
675 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
676 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
677 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
678 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
680 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
687 * The pipe->bind_blend_state() driver hook.
689 * Bind a blending CSO and flag related dirty bits.
692 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
694 struct iris_context
*ice
= (struct iris_context
*) ctx
;
695 ice
->state
.cso_blend
= state
;
696 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
697 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
698 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
702 * Gallium CSO for depth, stencil, and alpha testing state.
704 struct iris_depth_stencil_alpha_state
{
705 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
706 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
708 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
709 struct pipe_alpha_state alpha
;
713 * The pipe->create_depth_stencil_alpha_state() driver hook.
715 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
716 * testing state since we need pieces of it in a variety of places.
719 iris_create_zsa_state(struct pipe_context
*ctx
,
720 const struct pipe_depth_stencil_alpha_state
*state
)
722 struct iris_depth_stencil_alpha_state
*cso
=
723 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
725 cso
->alpha
= state
->alpha
;
727 bool two_sided_stencil
= state
->stencil
[1].enabled
;
729 /* The state tracker needs to optimize away EQUAL writes for us. */
730 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
732 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
733 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
734 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
735 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
736 wmds
.StencilTestFunction
=
737 translate_compare_func(state
->stencil
[0].func
);
738 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
739 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
740 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
741 wmds
.BackfaceStencilTestFunction
=
742 translate_compare_func(state
->stencil
[1].func
);
743 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
744 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
745 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
746 wmds
.StencilBufferWriteEnable
=
747 state
->stencil
[0].writemask
!= 0 ||
748 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
749 wmds
.DepthTestEnable
= state
->depth
.enabled
;
750 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
751 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
752 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
753 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
754 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
755 /* wmds.[Backface]StencilReferenceValue are merged later */
762 * The pipe->bind_depth_stencil_alpha_state() driver hook.
764 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
767 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
769 struct iris_context
*ice
= (struct iris_context
*) ctx
;
770 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
771 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
774 if (cso_changed(alpha
.ref_value
))
775 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
777 if (cso_changed(alpha
.enabled
))
778 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
780 if (cso_changed(alpha
.func
))
781 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
784 ice
->state
.cso_zsa
= new_cso
;
785 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
786 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
787 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
791 * Gallium CSO for rasterizer state.
793 struct iris_rasterizer_state
{
794 uint32_t sf
[GENX(3DSTATE_SF_length
)];
795 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
796 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
797 uint32_t wm
[GENX(3DSTATE_WM_length
)];
798 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
800 bool clip_halfz
; /* for CC_VIEWPORT */
801 bool depth_clip_near
; /* for CC_VIEWPORT */
802 bool depth_clip_far
; /* for CC_VIEWPORT */
803 bool flatshade
; /* for shader state */
804 bool flatshade_first
; /* for stream output */
805 bool clamp_fragment_color
; /* for shader state */
806 bool light_twoside
; /* for shader state */
807 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
808 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
809 bool line_stipple_enable
;
810 bool poly_stipple_enable
;
812 bool force_persample_interp
;
813 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
814 uint16_t sprite_coord_enable
;
818 * The pipe->create_rasterizer_state() driver hook.
821 iris_create_rasterizer_state(struct pipe_context
*ctx
,
822 const struct pipe_rasterizer_state
*state
)
824 struct iris_rasterizer_state
*cso
=
825 malloc(sizeof(struct iris_rasterizer_state
));
828 point_quad_rasterization
-> SBE
?
833 force_persample_interp
- ?
836 offset_units_unscaled
- cap
not exposed
840 // XXX: it may make more sense just to store the pipe_rasterizer_state,
841 // we're copying a lot of booleans here. But we don't need all of them...
843 cso
->multisample
= state
->multisample
;
844 cso
->force_persample_interp
= state
->force_persample_interp
;
845 cso
->clip_halfz
= state
->clip_halfz
;
846 cso
->depth_clip_near
= state
->depth_clip_near
;
847 cso
->depth_clip_far
= state
->depth_clip_far
;
848 cso
->flatshade
= state
->flatshade
;
849 cso
->flatshade_first
= state
->flatshade_first
;
850 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
851 cso
->light_twoside
= state
->light_twoside
;
852 cso
->rasterizer_discard
= state
->rasterizer_discard
;
853 cso
->half_pixel_center
= state
->half_pixel_center
;
854 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
855 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
856 cso
->line_stipple_enable
= state
->line_stipple_enable
;
857 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
859 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
860 sf
.StatisticsEnable
= true;
861 sf
.ViewportTransformEnable
= true;
862 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
863 sf
.LineEndCapAntialiasingRegionWidth
=
864 state
->line_smooth
? _10pixels
: _05pixels
;
865 sf
.LastPixelEnable
= state
->line_last_pixel
;
866 sf
.LineWidth
= state
->line_width
;
867 sf
.SmoothPointEnable
= state
->point_smooth
;
868 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
869 sf
.PointWidth
= state
->point_size
;
871 if (state
->flatshade_first
) {
872 sf
.TriangleFanProvokingVertexSelect
= 1;
874 sf
.TriangleStripListProvokingVertexSelect
= 2;
875 sf
.TriangleFanProvokingVertexSelect
= 2;
876 sf
.LineStripListProvokingVertexSelect
= 1;
880 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
881 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
882 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
883 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
884 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
885 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
886 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
887 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
888 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
889 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
890 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
891 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
892 rr
.SmoothPointEnable
= state
->point_smooth
;
893 rr
.AntialiasingEnable
= state
->line_smooth
;
894 rr
.ScissorRectangleEnable
= state
->scissor
;
895 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
896 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
897 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
900 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
901 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
902 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
904 cl
.StatisticsEnable
= true;
905 cl
.EarlyCullEnable
= true;
906 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
907 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
908 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
909 cl
.GuardbandClipTestEnable
= true;
910 cl
.ClipMode
= CLIPMODE_NORMAL
;
911 cl
.ClipEnable
= true;
912 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
913 cl
.MinimumPointWidth
= 0.125;
914 cl
.MaximumPointWidth
= 255.875;
916 if (state
->flatshade_first
) {
917 cl
.TriangleFanProvokingVertexSelect
= 1;
919 cl
.TriangleStripListProvokingVertexSelect
= 2;
920 cl
.TriangleFanProvokingVertexSelect
= 2;
921 cl
.LineStripListProvokingVertexSelect
= 1;
925 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
926 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
927 * filled in at draw time from the FS program.
929 wm
.LineAntialiasingRegionWidth
= _10pixels
;
930 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
931 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
932 wm
.StatisticsEnable
= true;
933 wm
.LineStippleEnable
= state
->line_stipple_enable
;
934 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
937 /* Remap from 0..255 back to 1..256 */
938 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
940 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
941 line
.LineStipplePattern
= state
->line_stipple_pattern
;
942 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
943 line
.LineStippleRepeatCount
= line_stipple_factor
;
950 * The pipe->bind_rasterizer_state() driver hook.
952 * Bind a rasterizer CSO and flag related dirty bits.
955 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
957 struct iris_context
*ice
= (struct iris_context
*) ctx
;
958 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
959 struct iris_rasterizer_state
*new_cso
= state
;
962 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
963 if (cso_changed_memcmp(line_stipple
))
964 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
966 if (cso_changed(half_pixel_center
))
967 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
969 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
970 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
972 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
973 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
975 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
976 cso_changed(clip_halfz
))
977 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
979 if (cso_changed(sprite_coord_enable
) || cso_changed(light_twoside
))
980 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
983 ice
->state
.cso_rast
= new_cso
;
984 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
985 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
986 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
990 * Return true if the given wrap mode requires the border color to exist.
992 * (We can skip uploading it if the sampler isn't going to use it.)
995 wrap_mode_needs_border_color(unsigned wrap_mode
)
997 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1001 * Gallium CSO for sampler state.
1003 struct iris_sampler_state
{
1004 // XXX: do we need this
1005 struct pipe_sampler_state base
;
1007 bool needs_border_color
;
1009 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1013 * The pipe->create_sampler_state() driver hook.
1015 * We fill out SAMPLER_STATE (except for the border color pointer), and
1016 * store that on the CPU. It doesn't make sense to upload it to a GPU
1017 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1018 * all bound sampler states to be in contiguous memor.
1021 iris_create_sampler_state(struct pipe_context
*ctx
,
1022 const struct pipe_sampler_state
*state
)
1024 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1029 memcpy(&cso
->base
, state
, sizeof(*state
));
1031 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1032 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1034 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1035 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1036 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1038 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1039 wrap_mode_needs_border_color(wrap_t
) ||
1040 wrap_mode_needs_border_color(wrap_r
);
1042 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1043 samp
.TCXAddressControlMode
= wrap_s
;
1044 samp
.TCYAddressControlMode
= wrap_t
;
1045 samp
.TCZAddressControlMode
= wrap_r
;
1046 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1047 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1048 samp
.MinModeFilter
= state
->min_img_filter
;
1049 samp
.MagModeFilter
= state
->mag_img_filter
;
1050 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1051 samp
.MaximumAnisotropy
= RATIO21
;
1053 if (state
->max_anisotropy
>= 2) {
1054 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1055 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1056 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1059 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1060 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1062 samp
.MaximumAnisotropy
=
1063 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1066 /* Set address rounding bits if not using nearest filtering. */
1067 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1068 samp
.UAddressMinFilterRoundingEnable
= true;
1069 samp
.VAddressMinFilterRoundingEnable
= true;
1070 samp
.RAddressMinFilterRoundingEnable
= true;
1073 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1074 samp
.UAddressMagFilterRoundingEnable
= true;
1075 samp
.VAddressMagFilterRoundingEnable
= true;
1076 samp
.RAddressMagFilterRoundingEnable
= true;
1079 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1080 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1082 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1084 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1085 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
1086 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1087 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1089 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1096 * The pipe->bind_sampler_states() driver hook.
1098 * Now that we know all the sampler states, we upload them all into a
1099 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1100 * We also fill out the border color state pointers at this point.
1102 * We could defer this work to draw time, but we assume that binding
1103 * will be less frequent than drawing.
1105 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1106 // XXX: with the complete set of shaders. If it makes multiple calls to
1107 // XXX: things one at a time, we could waste a lot of time assembling things.
1108 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1109 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1111 iris_bind_sampler_states(struct pipe_context
*ctx
,
1112 enum pipe_shader_type p_stage
,
1113 unsigned start
, unsigned count
,
1116 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1117 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1119 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1120 ice
->state
.num_samplers
[stage
] =
1121 MAX2(ice
->state
.num_samplers
[stage
], start
+ count
);
1123 for (int i
= 0; i
< count
; i
++) {
1124 ice
->state
.samplers
[stage
][start
+ i
] = states
[i
];
1127 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1128 * in the dynamic state memory zone, so we can point to it via the
1129 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1131 void *map
= upload_state(ice
->state
.dynamic_uploader
,
1132 &ice
->state
.sampler_table
[stage
],
1133 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1137 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
1138 ice
->state
.sampler_table
[stage
].offset
+=
1139 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1141 /* Make sure all land in the same BO */
1142 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1144 for (int i
= 0; i
< count
; i
++) {
1145 struct iris_sampler_state
*state
= ice
->state
.samplers
[stage
][i
];
1147 /* Save a pointer to the iris_sampler_state, a few fields need
1148 * to inform draw-time decisions.
1150 ice
->state
.samplers
[stage
][start
+ i
] = state
;
1153 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1154 } else if (!state
->needs_border_color
) {
1155 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1157 ice
->state
.need_border_colors
= true;
1159 /* Stream out the border color and merge the pointer. */
1161 iris_upload_border_color(ice
, &state
->base
.border_color
);
1163 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1164 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1165 dyns
.BorderColorPointer
= offset
;
1168 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1169 ((uint32_t *) map
)[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1172 map
+= GENX(SAMPLER_STATE_length
);
1175 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1179 * Gallium CSO for sampler views (texture views).
1181 * In addition to the normal pipe_resource, this adds an ISL view
1182 * which may reinterpret the format or restrict levels/layers.
1184 * These can also be linear texture buffers.
1186 struct iris_sampler_view
{
1187 // XXX: just store the resource, not the rest of this
1188 struct pipe_sampler_view base
;
1189 struct isl_view view
;
1191 /** The resource (BO) holding our SURFACE_STATE. */
1192 struct iris_state_ref surface_state
;
1196 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the HW's
1197 * "Shader Channel Select" enumerations (i.e. SCS_RED). The mappings are
1199 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
1202 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
1204 * which is simply adding 4 then modding by 8 (or anding with 7).
1206 static enum isl_channel_select
1207 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
1209 return (swizzle
+ 4) & 7;
1213 * The pipe->create_sampler_view() driver hook.
1215 static struct pipe_sampler_view
*
1216 iris_create_sampler_view(struct pipe_context
*ctx
,
1217 struct pipe_resource
*tex
,
1218 const struct pipe_sampler_view
*tmpl
)
1220 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1221 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1222 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1223 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1228 /* initialize base object */
1230 isv
->base
.context
= ctx
;
1231 isv
->base
.texture
= NULL
;
1232 pipe_reference_init(&isv
->base
.reference
, 1);
1233 pipe_resource_reference(&isv
->base
.texture
, tex
);
1235 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1236 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1240 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1241 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1243 /* XXX: do we need brw_get_texture_swizzle hacks here? */
1244 isv
->view
= (struct isl_view
) {
1245 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1246 .swizzle
= (struct isl_swizzle
) {
1247 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
1248 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
1249 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
1250 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
1252 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
1253 (itex
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
),
1256 /* Fill out SURFACE_STATE for this view. */
1257 if (tmpl
->target
!= PIPE_BUFFER
) {
1258 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1259 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1260 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1261 isv
->view
.array_len
=
1262 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1264 isl_surf_fill_state(&screen
->isl_dev
, map
,
1265 .surf
= &itex
->surf
, .view
= &isv
->view
,
1267 .address
= itex
->bo
->gtt_offset
);
1269 // .clear_color = clear_color,
1271 // XXX: what to do about isv->view? other drivers don't use it for bufs
1272 const struct isl_format_layout
*fmtl
=
1273 isl_format_get_layout(isv
->view
.format
);
1274 const unsigned cpp
= fmtl
->bpb
/ 8;
1276 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1277 .address
= itex
->bo
->gtt_offset
+
1279 // XXX: buffer_texture_range_size from i965?
1280 .size_B
= tmpl
->u
.buf
.size
,
1281 .format
= isv
->view
.format
,
1290 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1291 struct pipe_sampler_view
*state
)
1293 struct iris_sampler_view
*isv
= (void *) state
;
1294 pipe_resource_reference(&state
->texture
, NULL
);
1295 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1300 * The pipe->create_surface() driver hook.
1302 * In Gallium nomenclature, "surfaces" are a view of a resource that
1303 * can be bound as a render target or depth/stencil buffer.
1305 static struct pipe_surface
*
1306 iris_create_surface(struct pipe_context
*ctx
,
1307 struct pipe_resource
*tex
,
1308 const struct pipe_surface
*tmpl
)
1310 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1311 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1312 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1313 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1314 struct pipe_surface
*psurf
= &surf
->base
;
1315 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1320 pipe_reference_init(&psurf
->reference
, 1);
1321 pipe_resource_reference(&psurf
->texture
, tex
);
1322 psurf
->context
= ctx
;
1323 psurf
->format
= tmpl
->format
;
1324 psurf
->width
= tex
->width0
;
1325 psurf
->height
= tex
->height0
;
1326 psurf
->texture
= tex
;
1327 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1328 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1329 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1331 isl_surf_usage_flags_t usage
= 0;
1333 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1334 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1335 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1337 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1339 enum isl_format isl_format
=
1340 iris_isl_format_for_usage(devinfo
, psurf
->format
, usage
);
1342 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1343 !isl_format_supports_rendering(devinfo
, isl_format
)) {
1344 /* Framebuffer validation will reject this invalid case, but it
1345 * hasn't had the opportunity yet. In the meantime, we need to
1346 * avoid hitting ISL asserts about unsupported formats below.
1352 surf
->view
= (struct isl_view
) {
1353 .format
= isl_format
,
1354 .base_level
= tmpl
->u
.tex
.level
,
1356 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1357 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1358 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1362 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1363 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1364 ISL_SURF_USAGE_STENCIL_BIT
))
1368 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1369 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1373 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1374 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1376 isl_surf_fill_state(&screen
->isl_dev
, map
,
1377 .surf
= &res
->surf
, .view
= &surf
->view
,
1379 .address
= res
->bo
->gtt_offset
);
1381 // .clear_color = clear_color,
1387 * The pipe->set_sampler_views() driver hook.
1390 iris_set_sampler_views(struct pipe_context
*ctx
,
1391 enum pipe_shader_type p_stage
,
1392 unsigned start
, unsigned count
,
1393 struct pipe_sampler_view
**views
)
1395 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1396 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1399 for (i
= 0; i
< count
; i
++) {
1400 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1401 &ice
->state
.textures
[stage
][i
], views
[i
]);
1403 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1404 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1405 &ice
->state
.textures
[stage
][i
], NULL
);
1408 ice
->state
.num_textures
[stage
] = count
;
1410 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1414 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1416 struct iris_surface
*surf
= (void *) p_surf
;
1417 pipe_resource_reference(&p_surf
->texture
, NULL
);
1418 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1422 // XXX: actually implement user clip planes
1424 iris_set_clip_state(struct pipe_context
*ctx
,
1425 const struct pipe_clip_state
*state
)
1430 * The pipe->set_polygon_stipple() driver hook.
1433 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1434 const struct pipe_poly_stipple
*state
)
1436 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1437 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1438 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1442 * The pipe->set_sample_mask() driver hook.
1445 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1447 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1449 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1450 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1452 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1453 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1457 * The pipe->set_scissor_states() driver hook.
1459 * This corresponds to our SCISSOR_RECT state structures. It's an
1460 * exact match, so we just store them, and memcpy them out later.
1463 iris_set_scissor_states(struct pipe_context
*ctx
,
1464 unsigned start_slot
,
1465 unsigned num_scissors
,
1466 const struct pipe_scissor_state
*states
)
1468 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1470 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1471 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1474 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1478 * The pipe->set_stencil_ref() driver hook.
1480 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1483 iris_set_stencil_ref(struct pipe_context
*ctx
,
1484 const struct pipe_stencil_ref
*state
)
1486 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1487 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1488 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1492 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1494 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1499 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1500 float m00
, float m11
, float m30
, float m31
,
1501 float *xmin
, float *xmax
,
1502 float *ymin
, float *ymax
)
1504 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1505 * Strips and Fans documentation:
1507 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1508 * fixed-point "guardband" range supported by the rasterization hardware"
1512 * "In almost all circumstances, if an object’s vertices are actually
1513 * modified by this clamping (i.e., had X or Y coordinates outside of
1514 * the guardband extent the rendered object will not match the intended
1515 * result. Therefore software should take steps to ensure that this does
1516 * not happen - e.g., by clipping objects such that they do not exceed
1517 * these limits after the Drawing Rectangle is applied."
1519 * I believe the fundamental restriction is that the rasterizer (in
1520 * the SF/WM stages) have a limit on the number of pixels that can be
1521 * rasterized. We need to ensure any coordinates beyond the rasterizer
1522 * limit are handled by the clipper. So effectively that limit becomes
1523 * the clipper's guardband size.
1525 * It goes on to say:
1527 * "In addition, in order to be correctly rendered, objects must have a
1528 * screenspace bounding box not exceeding 8K in the X or Y direction.
1529 * This additional restriction must also be comprehended by software,
1530 * i.e., enforced by use of clipping."
1532 * This makes no sense. Gen7+ hardware supports 16K render targets,
1533 * and you definitely need to be able to draw polygons that fill the
1534 * surface. Our assumption is that the rasterizer was limited to 8K
1535 * on Sandybridge, which only supports 8K surfaces, and it was actually
1536 * increased to 16K on Ivybridge and later.
1538 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1540 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1542 if (m00
!= 0 && m11
!= 0) {
1543 /* First, we compute the screen-space render area */
1544 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1545 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1546 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1547 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1549 /* We want the guardband to be centered on that */
1550 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1551 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1552 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1553 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1555 /* Now we need it in native device coordinates */
1556 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1557 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1558 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1559 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1561 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1562 * flipped upside-down. X should be fine though.
1564 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1565 *xmin
= ndc_gb_xmin
;
1566 *xmax
= ndc_gb_xmax
;
1567 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1568 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1570 /* The viewport scales to 0, so nothing will be rendered. */
1580 * The pipe->set_viewport_states() driver hook.
1582 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1583 * the guardband yet, as we need the framebuffer dimensions, but we can
1584 * at least fill out the rest.
1587 iris_set_viewport_states(struct pipe_context
*ctx
,
1588 unsigned start_slot
,
1590 const struct pipe_viewport_state
*states
)
1592 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1593 struct iris_genx_state
*genx
= ice
->state
.genx
;
1594 uint32_t *vp_map
= &genx
->sf_cl_vp
[start_slot
];
1596 for (unsigned i
= 0; i
< count
; i
++) {
1597 const struct pipe_viewport_state
*state
= &states
[i
];
1599 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
1601 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1602 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1603 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1604 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1605 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1606 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1607 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1608 /* XXX: in i965 this is computed based on the drawbuffer size,
1609 * but we don't have that here...
1611 vp
.XMinClipGuardband
= -1.0;
1612 vp
.XMaxClipGuardband
= 1.0;
1613 vp
.YMinClipGuardband
= -1.0;
1614 vp
.YMaxClipGuardband
= 1.0;
1615 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1616 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1617 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1618 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1621 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1624 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1626 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1627 !ice
->state
.cso_rast
->depth_clip_far
))
1628 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1632 * The pipe->set_framebuffer_state() driver hook.
1634 * Sets the current draw FBO, including color render targets, depth,
1635 * and stencil buffers.
1638 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1639 const struct pipe_framebuffer_state
*state
)
1641 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1642 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1643 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1644 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1645 struct iris_resource
*zres
;
1646 struct iris_resource
*stencil_res
;
1648 unsigned samples
= util_framebuffer_get_num_samples(state
);
1650 if (cso
->samples
!= samples
) {
1651 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1654 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1655 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1658 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
1659 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1662 util_copy_framebuffer_state(cso
, state
);
1663 cso
->samples
= samples
;
1665 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
1667 struct isl_view view
= {
1670 .base_array_layer
= 0,
1672 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1675 struct isl_depth_stencil_hiz_emit_info info
= {
1681 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
1684 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1685 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1687 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1690 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1692 info
.depth_surf
= &zres
->surf
;
1693 info
.depth_address
= zres
->bo
->gtt_offset
;
1694 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1696 view
.format
= zres
->surf
.format
;
1700 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1701 info
.stencil_surf
= &stencil_res
->surf
;
1702 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
1704 view
.format
= stencil_res
->surf
.format
;
1708 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1710 /* Make a null surface for unbound buffers */
1711 void *null_surf_map
=
1712 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
1713 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1714 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(cso
->width
, cso
->height
, cso
->layers
? cso
->layers
: 1));
1716 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1718 /* Render target change */
1719 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1721 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
1725 * The pipe->set_constant_buffer() driver hook.
1727 * This uploads any constant data in user buffers, and references
1728 * any UBO resources containing constant data.
1731 iris_set_constant_buffer(struct pipe_context
*ctx
,
1732 enum pipe_shader_type p_stage
, unsigned index
,
1733 const struct pipe_constant_buffer
*input
)
1735 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1736 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1737 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1738 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1739 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1741 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1742 if (input
->user_buffer
) {
1743 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1744 input
->user_buffer
, &cbuf
->data
.offset
,
1747 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1750 // XXX: these are not retained forever, use a separate uploader?
1752 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1753 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1754 if (!unlikely(map
)) {
1755 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1759 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1760 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1761 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1763 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1764 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1765 .size_B
= input
->buffer_size
,
1766 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1770 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1771 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1774 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1775 // XXX: maybe not necessary all the time...?
1776 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
1777 // XXX: pull model we may need actual new bindings...
1778 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1782 * The pipe->set_shader_buffers() driver hook.
1784 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
1785 * SURFACE_STATE here, as the buffer offset may change each time.
1788 iris_set_shader_buffers(struct pipe_context
*ctx
,
1789 enum pipe_shader_type p_stage
,
1790 unsigned start_slot
, unsigned count
,
1791 const struct pipe_shader_buffer
*buffers
)
1793 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1794 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1795 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1796 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
1798 for (unsigned i
= 0; i
< count
; i
++) {
1799 if (buffers
&& buffers
[i
].buffer
) {
1800 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
1801 struct iris_resource
*res
= (void *) buffer
->buffer
;
1802 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
1804 // XXX: these are not retained forever, use a separate uploader?
1806 upload_state(ice
->state
.surface_uploader
,
1807 &shs
->ssbo_surface_state
[start_slot
+ i
],
1808 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1809 if (!unlikely(map
)) {
1810 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1814 struct iris_bo
*surf_state_bo
=
1815 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
1816 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
1817 iris_bo_offset_from_base_address(surf_state_bo
);
1819 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1821 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
1822 .size_B
= buffer
->buffer_size
,
1823 .format
= ISL_FORMAT_RAW
,
1827 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1828 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
1833 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1837 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1843 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1845 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1846 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1850 * The pipe->set_vertex_buffers() driver hook.
1852 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
1855 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1856 unsigned start_slot
, unsigned count
,
1857 const struct pipe_vertex_buffer
*buffers
)
1859 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1860 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
1862 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
1867 cso
->num_buffers
= count
;
1869 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1870 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1873 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1876 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1877 vb
.VertexBufferIndex
= start_slot
;
1878 vb
.NullVertexBuffer
= true;
1879 vb
.AddressModifyEnable
= true;
1883 for (unsigned i
= 0; i
< count
; i
++) {
1884 assert(!buffers
[i
].is_user_buffer
);
1886 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1887 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1889 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1890 vb
.VertexBufferIndex
= start_slot
+ i
;
1892 vb
.AddressModifyEnable
= true;
1893 vb
.BufferPitch
= buffers
[i
].stride
;
1894 vb
.BufferSize
= res
->bo
->size
;
1895 vb
.BufferStartingAddress
=
1896 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1899 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1902 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1906 * Gallium CSO for vertex elements.
1908 struct iris_vertex_element_state
{
1909 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1910 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1915 * The pipe->create_vertex_elements() driver hook.
1917 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
1918 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
1921 iris_create_vertex_elements(struct pipe_context
*ctx
,
1923 const struct pipe_vertex_element
*state
)
1925 struct iris_vertex_element_state
*cso
=
1926 malloc(sizeof(struct iris_vertex_element_state
));
1931 * - create edge flag one
1933 * - if those are necessary, use count + 1/2/3... OR in the length
1935 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1937 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
1940 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1941 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1944 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1946 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1947 ve
.Component0Control
= VFCOMP_STORE_0
;
1948 ve
.Component1Control
= VFCOMP_STORE_0
;
1949 ve
.Component2Control
= VFCOMP_STORE_0
;
1950 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1953 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1957 for (int i
= 0; i
< count
; i
++) {
1958 enum isl_format isl_format
=
1959 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1960 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1961 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1963 switch (isl_format_get_num_channels(isl_format
)) {
1964 case 0: comp
[0] = VFCOMP_STORE_0
;
1965 case 1: comp
[1] = VFCOMP_STORE_0
;
1966 case 2: comp
[2] = VFCOMP_STORE_0
;
1968 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1969 : VFCOMP_STORE_1_FP
;
1972 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1973 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1975 ve
.SourceElementOffset
= state
[i
].src_offset
;
1976 ve
.SourceElementFormat
= isl_format
;
1977 ve
.Component0Control
= comp
[0];
1978 ve
.Component1Control
= comp
[1];
1979 ve
.Component2Control
= comp
[2];
1980 ve
.Component3Control
= comp
[3];
1983 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1984 vi
.VertexElementIndex
= i
;
1985 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1986 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1989 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1990 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
1997 * The pipe->bind_vertex_elements_state() driver hook.
2000 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2002 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2003 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2004 struct iris_vertex_element_state
*new_cso
= state
;
2006 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2007 * we need to re-emit it to ensure we're overriding the right one.
2009 if (new_cso
&& cso_changed(count
))
2010 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2012 ice
->state
.cso_vertex_elements
= state
;
2013 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2017 iris_create_compute_state(struct pipe_context
*ctx
,
2018 const struct pipe_compute_state
*state
)
2020 // XXX: actually do something
2025 * Gallium CSO for stream output (transform feedback) targets.
2027 struct iris_stream_output_target
{
2028 struct pipe_stream_output_target base
;
2030 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2032 /** Storage holding the offset where we're writing in the buffer */
2033 struct iris_state_ref offset
;
2037 * The pipe->create_stream_output_target() driver hook.
2039 * "Target" here refers to a destination buffer. We translate this into
2040 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2041 * know which buffer this represents, or whether we ought to zero the
2042 * write-offsets, or append. Those are handled in the set() hook.
2044 static struct pipe_stream_output_target
*
2045 iris_create_stream_output_target(struct pipe_context
*ctx
,
2046 struct pipe_resource
*res
,
2047 unsigned buffer_offset
,
2048 unsigned buffer_size
)
2050 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2054 pipe_reference_init(&cso
->base
.reference
, 1);
2055 pipe_resource_reference(&cso
->base
.buffer
, res
);
2056 cso
->base
.buffer_offset
= buffer_offset
;
2057 cso
->base
.buffer_size
= buffer_size
;
2058 cso
->base
.context
= ctx
;
2060 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4, 4);
2062 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2063 sob
.SurfaceBaseAddress
=
2064 rw_bo(NULL
, iris_resource_bo(res
)->gtt_offset
+ buffer_offset
);
2065 sob
.SOBufferEnable
= true;
2066 sob
.StreamOffsetWriteEnable
= true;
2067 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2068 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2070 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2071 sob
.StreamOutputBufferOffsetAddress
=
2072 rw_bo(NULL
, iris_resource_bo(cso
->offset
.res
)->gtt_offset
+ cso
->offset
.offset
);
2074 /* .SOBufferIndex and .StreamOffset are filled in later */
2081 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2082 struct pipe_stream_output_target
*state
)
2084 struct iris_stream_output_target
*cso
= (void *) state
;
2086 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2087 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2093 * The pipe->set_stream_output_targets() driver hook.
2095 * At this point, we know which targets are bound to a particular index,
2096 * and also whether we want to append or start over. We can finish the
2097 * 3DSTATE_SO_BUFFER packets we started earlier.
2100 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2101 unsigned num_targets
,
2102 struct pipe_stream_output_target
**targets
,
2103 const unsigned *offsets
)
2105 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2106 struct iris_genx_state
*genx
= ice
->state
.genx
;
2107 uint32_t *so_buffers
= genx
->so_buffers
;
2109 const bool active
= num_targets
> 0;
2110 if (ice
->state
.streamout_active
!= active
) {
2111 ice
->state
.streamout_active
= active
;
2112 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2115 for (int i
= 0; i
< 4; i
++) {
2116 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2117 i
< num_targets
? targets
[i
] : NULL
);
2120 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2124 for (unsigned i
= 0; i
< 4; i
++,
2125 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2127 if (i
>= num_targets
|| !targets
[i
]) {
2128 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2129 sob
.SOBufferIndex
= i
;
2133 /* Note that offsets[i] will either be 0, causing us to zero
2134 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2135 * "continue appending at the existing offset."
2137 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2139 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2140 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2141 dyns
.SOBufferIndex
= i
;
2142 dyns
.StreamOffset
= offsets
[i
];
2145 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2146 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2147 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2151 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2155 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2156 * 3DSTATE_STREAMOUT packets.
2158 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2159 * hardware to record. We can create it entirely based on the shader, with
2160 * no dynamic state dependencies.
2162 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2163 * state-based settings. We capture the shader-related ones here, and merge
2164 * the rest in at draw time.
2167 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2168 const struct brw_vue_map
*vue_map
)
2170 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2171 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2172 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2173 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2175 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2177 memset(so_decl
, 0, sizeof(so_decl
));
2179 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2180 * command feels strange -- each dword pair contains a SO_DECL per stream.
2182 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2183 const struct pipe_stream_output
*output
= &info
->output
[i
];
2184 const int buffer
= output
->output_buffer
;
2185 const int varying
= output
->register_index
;
2186 const unsigned stream_id
= output
->stream
;
2187 assert(stream_id
< MAX_VERTEX_STREAMS
);
2189 buffer_mask
[stream_id
] |= 1 << buffer
;
2191 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2193 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2194 * array. Instead, it simply increments DstOffset for the following
2195 * input by the number of components that should be skipped.
2197 * Our hardware is unusual in that it requires us to program SO_DECLs
2198 * for fake "hole" components, rather than simply taking the offset
2199 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2200 * program as many size = 4 holes as we can, then a final hole to
2201 * accommodate the final 1, 2, or 3 remaining.
2203 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2205 while (skip_components
> 0) {
2206 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2208 .OutputBufferSlot
= output
->output_buffer
,
2209 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2211 skip_components
-= 4;
2214 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2216 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2217 .OutputBufferSlot
= output
->output_buffer
,
2218 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2220 ((1 << output
->num_components
) - 1) << output
->start_component
,
2223 if (decls
[stream_id
] > max_decls
)
2224 max_decls
= decls
[stream_id
];
2227 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2228 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2229 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2231 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2232 int urb_entry_read_offset
= 0;
2233 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2234 urb_entry_read_offset
;
2236 /* We always read the whole vertex. This could be reduced at some
2237 * point by reading less and offsetting the register index in the
2240 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2241 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2242 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2243 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2244 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2245 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2246 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2247 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2249 /* Set buffer pitches; 0 means unbound. */
2250 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2251 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2252 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2253 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2256 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2257 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2258 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2259 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2260 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2261 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2262 list
.NumEntries0
= decls
[0];
2263 list
.NumEntries1
= decls
[1];
2264 list
.NumEntries2
= decls
[2];
2265 list
.NumEntries3
= decls
[3];
2268 for (int i
= 0; i
< max_decls
; i
++) {
2269 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2270 entry
.Stream0Decl
= so_decl
[0][i
];
2271 entry
.Stream1Decl
= so_decl
[1][i
];
2272 entry
.Stream2Decl
= so_decl
[2][i
];
2273 entry
.Stream3Decl
= so_decl
[3][i
];
2281 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2282 const struct brw_vue_map
*last_vue_map
,
2283 bool two_sided_color
,
2284 unsigned *out_offset
,
2285 unsigned *out_length
)
2287 /* The compiler computes the first URB slot without considering COL/BFC
2288 * swizzling (because it doesn't know whether it's enabled), so we need
2289 * to do that here too. This may result in a smaller offset, which
2292 const unsigned first_slot
=
2293 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2295 /* This becomes the URB read offset (counted in pairs of slots). */
2296 assert(first_slot
% 2 == 0);
2297 *out_offset
= first_slot
/ 2;
2299 /* We need to adjust the inputs read to account for front/back color
2300 * swizzling, as it can make the URB length longer.
2302 for (int c
= 0; c
<= 1; c
++) {
2303 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2304 /* If two sided color is enabled, the fragment shader's gl_Color
2305 * (COL0) input comes from either the gl_FrontColor (COL0) or
2306 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2308 if (two_sided_color
)
2309 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2311 /* If front color isn't written, we opt to give them back color
2312 * instead of an undefined value. Switch from COL to BFC.
2314 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2315 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2316 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2321 /* Compute the minimum URB Read Length necessary for the FS inputs.
2323 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2324 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2326 * "This field should be set to the minimum length required to read the
2327 * maximum source attribute. The maximum source attribute is indicated
2328 * by the maximum value of the enabled Attribute # Source Attribute if
2329 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2330 * enable is not set.
2331 * read_length = ceiling((max_source_attr + 1) / 2)
2333 * [errata] Corruption/Hang possible if length programmed larger than
2336 * Similar text exists for Ivy Bridge.
2338 * We find the last URB slot that's actually read by the FS.
2340 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2341 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2342 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2345 /* The URB read length is the difference of the two, counted in pairs. */
2346 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2350 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2351 const struct iris_context
*ice
,
2352 unsigned urb_read_offset
,
2353 unsigned sprite_coord_enables
)
2355 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2356 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2357 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2358 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2359 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2361 /* XXX: this should be generated when putting programs in place */
2363 // XXX: raster->sprite_coord_enable
2365 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2366 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2367 if (input_index
< 0 || input_index
>= 16)
2370 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2371 &attr_overrides
[input_index
];
2373 /* Viewport and Layer are stored in the VUE header. We need to override
2374 * them to zero if earlier stages didn't write them, as GL requires that
2375 * they read back as zero when not explicitly set.
2378 case VARYING_SLOT_VIEWPORT
:
2379 case VARYING_SLOT_LAYER
:
2380 attr
->ComponentOverrideX
= true;
2381 attr
->ComponentOverrideW
= true;
2382 attr
->ConstantSource
= CONST_0000
;
2384 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2385 attr
->ComponentOverrideY
= true;
2386 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2387 attr
->ComponentOverrideZ
= true;
2390 case VARYING_SLOT_PRIMITIVE_ID
:
2391 attr
->ComponentOverrideX
= true;
2392 attr
->ComponentOverrideY
= true;
2393 attr
->ComponentOverrideZ
= true;
2394 attr
->ComponentOverrideW
= true;
2395 attr
->ConstantSource
= PRIM_ID
;
2402 if (sprite_coord_enables
& (1 << input_index
))
2405 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2407 /* If there was only a back color written but not front, use back
2408 * as the color instead of undefined.
2410 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2411 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2412 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2413 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2415 /* Not written by the previous stage - undefined. */
2417 attr
->ComponentOverrideX
= true;
2418 attr
->ComponentOverrideY
= true;
2419 attr
->ComponentOverrideZ
= true;
2420 attr
->ComponentOverrideW
= true;
2421 attr
->ConstantSource
= CONST_0001_FLOAT
;
2425 /* Compute the location of the attribute relative to the read offset,
2426 * which is counted in 256-bit increments (two 128-bit VUE slots).
2428 const int source_attr
= slot
- 2 * urb_read_offset
;
2429 assert(source_attr
>= 0 && source_attr
<= 32);
2430 attr
->SourceAttribute
= source_attr
;
2432 /* If we are doing two-sided color, and the VUE slot following this one
2433 * represents a back-facing color, then we need to instruct the SF unit
2434 * to do back-facing swizzling.
2436 if (cso_rast
->light_twoside
&&
2437 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2438 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2439 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2440 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2441 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2444 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2445 for (int i
= 0; i
< 16; i
++)
2446 sbes
.Attribute
[i
] = attr_overrides
[i
];
2451 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2452 const struct iris_rasterizer_state
*cso
)
2454 unsigned overrides
= 0;
2456 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2457 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2459 for (int i
= 0; i
< 8; i
++) {
2460 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2461 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2462 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2469 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2471 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2472 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2473 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2474 const struct shader_info
*fs_info
=
2475 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2477 unsigned urb_read_offset
, urb_read_length
;
2478 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2479 ice
->shaders
.last_vue_map
,
2480 cso_rast
->light_twoside
,
2481 &urb_read_offset
, &urb_read_length
);
2483 unsigned sprite_coord_overrides
=
2484 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2486 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2487 sbe
.AttributeSwizzleEnable
= true;
2488 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2489 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2490 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2491 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2492 sbe
.ForceVertexURBEntryReadOffset
= true;
2493 sbe
.ForceVertexURBEntryReadLength
= true;
2494 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2495 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2497 for (int i
= 0; i
< 32; i
++) {
2498 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2502 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2506 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
2508 // XXX: do something
2511 /* ------------------------------------------------------------------- */
2514 * Set sampler-related program key fields based on the current state.
2517 iris_populate_sampler_key(const struct iris_context
*ice
,
2518 struct brw_sampler_prog_key_data
*key
)
2520 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2521 key
->swizzles
[i
] = 0x688; /* XYZW */
2526 * Populate VS program key fields based on the current state.
2529 iris_populate_vs_key(const struct iris_context
*ice
,
2530 struct brw_vs_prog_key
*key
)
2532 iris_populate_sampler_key(ice
, &key
->tex
);
2536 * Populate TCS program key fields based on the current state.
2539 iris_populate_tcs_key(const struct iris_context
*ice
,
2540 struct brw_tcs_prog_key
*key
)
2542 iris_populate_sampler_key(ice
, &key
->tex
);
2546 * Populate TES program key fields based on the current state.
2549 iris_populate_tes_key(const struct iris_context
*ice
,
2550 struct brw_tes_prog_key
*key
)
2552 iris_populate_sampler_key(ice
, &key
->tex
);
2556 * Populate GS program key fields based on the current state.
2559 iris_populate_gs_key(const struct iris_context
*ice
,
2560 struct brw_gs_prog_key
*key
)
2562 iris_populate_sampler_key(ice
, &key
->tex
);
2566 * Populate FS program key fields based on the current state.
2569 iris_populate_fs_key(const struct iris_context
*ice
,
2570 struct brw_wm_prog_key
*key
)
2572 iris_populate_sampler_key(ice
, &key
->tex
);
2574 /* XXX: dirty flags? */
2575 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
2576 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
2577 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
2578 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
2580 key
->nr_color_regions
= fb
->nr_cbufs
;
2582 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
2584 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
2585 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
2587 /* XXX: only bother if COL0/1 are read */
2588 key
->flat_shade
= rast
->flatshade
;
2590 key
->persample_interp
= rast
->force_persample_interp
;
2591 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
2593 key
->coherent_fb_fetch
= true;
2595 // XXX: uint64_t input_slots_valid; - for >16 inputs
2597 // XXX: key->force_dual_color_blend for unigine
2598 // XXX: respect hint for high_quality_derivatives:1;
2602 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
2603 pkt
.SamplerCount
= \
2604 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
2605 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
2606 ffs(stage_state
->per_thread_scratch
) - 11; \
2611 KSP(const struct iris_compiled_shader
*shader
)
2613 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
2614 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
2617 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2618 pkt.KernelStartPointer = KSP(shader); \
2619 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
2620 pkt.FloatingPointMode = prog_data->use_alt_mode; \
2622 pkt.DispatchGRFStartRegisterForURBData = \
2623 prog_data->dispatch_grf_start_reg; \
2624 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2625 pkt.prefix##URBEntryReadOffset = 0; \
2627 pkt.StatisticsEnable = true; \
2631 * Encode most of 3DSTATE_VS based on the compiled shader.
2634 iris_store_vs_state(const struct gen_device_info
*devinfo
,
2635 struct iris_compiled_shader
*shader
)
2637 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2638 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2640 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
2641 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2642 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2643 vs
.SIMD8DispatchEnable
= true;
2644 vs
.UserClipDistanceCullTestEnableBitmask
=
2645 vue_prog_data
->cull_distance_mask
;
2650 * Encode most of 3DSTATE_HS based on the compiled shader.
2653 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
2654 struct iris_compiled_shader
*shader
)
2656 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2657 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2658 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
2660 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
2661 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
2663 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
2664 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
2665 hs
.IncludeVertexHandles
= true;
2670 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
2673 iris_store_tes_state(const struct gen_device_info
*devinfo
,
2674 struct iris_compiled_shader
*shader
)
2676 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2677 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2678 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
2680 uint32_t *te_state
= (void *) shader
->derived_data
;
2681 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
2683 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
2684 te
.Partitioning
= tes_prog_data
->partitioning
;
2685 te
.OutputTopology
= tes_prog_data
->output_topology
;
2686 te
.TEDomain
= tes_prog_data
->domain
;
2688 te
.MaximumTessellationFactorOdd
= 63.0;
2689 te
.MaximumTessellationFactorNotOdd
= 64.0;
2692 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
2693 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
2695 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
2696 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
2697 ds
.ComputeWCoordinateEnable
=
2698 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
2700 ds
.UserClipDistanceCullTestEnableBitmask
=
2701 vue_prog_data
->cull_distance_mask
;
2707 * Encode most of 3DSTATE_GS based on the compiled shader.
2710 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2711 struct iris_compiled_shader
*shader
)
2713 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2714 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2715 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2717 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2718 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2720 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2721 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2722 gs
.ControlDataHeaderSize
=
2723 gs_prog_data
->control_data_header_size_hwords
;
2724 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2725 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2726 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2727 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2728 gs
.ReorderMode
= TRAILING
;
2729 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2730 gs
.MaximumNumberofThreads
=
2731 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2732 : (devinfo
->max_gs_threads
- 1);
2734 if (gs_prog_data
->static_vertex_count
!= -1) {
2735 gs
.StaticOutput
= true;
2736 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2738 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2740 gs
.UserClipDistanceCullTestEnableBitmask
=
2741 vue_prog_data
->cull_distance_mask
;
2743 const int urb_entry_write_offset
= 1;
2744 const uint32_t urb_entry_output_length
=
2745 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2746 urb_entry_write_offset
;
2748 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2749 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2754 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
2757 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2758 struct iris_compiled_shader
*shader
)
2760 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2761 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2763 uint32_t *ps_state
= (void *) shader
->derived_data
;
2764 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2766 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2767 ps
.VectorMaskEnable
= true;
2768 //ps.SamplerCount = ...
2769 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2770 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2771 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2773 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2774 prog_data
->ubo_ranges
[0].length
> 0;
2776 /* From the documentation for this packet:
2777 * "If the PS kernel does not need the Position XY Offsets to
2778 * compute a Position Value, then this field should be programmed
2779 * to POSOFFSET_NONE."
2781 * "SW Recommendation: If the PS kernel needs the Position Offsets
2782 * to compute a Position XY value, this field should match Position
2783 * ZW Interpolation Mode to ensure a consistent position.xyzw
2786 * We only require XY sample offsets. So, this recommendation doesn't
2787 * look useful at the moment. We might need this in future.
2789 ps
.PositionXYOffsetSelect
=
2790 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2791 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2792 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2793 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2795 // XXX: Disable SIMD32 with 16x MSAA
2797 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2798 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2799 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2800 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2801 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2802 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2804 ps
.KernelStartPointer0
=
2805 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2806 ps
.KernelStartPointer1
=
2807 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2808 ps
.KernelStartPointer2
=
2809 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2812 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2813 psx
.PixelShaderValid
= true;
2814 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2815 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2816 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2817 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2818 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2819 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2821 if (wm_prog_data
->uses_sample_mask
) {
2822 /* TODO: conservative rasterization */
2823 if (wm_prog_data
->post_depth_coverage
)
2824 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2826 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2829 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2830 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2831 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2838 * Compute the size of the derived data (shader command packets).
2840 * This must match the data written by the iris_store_xs_state() functions.
2843 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2845 assert(cache_id
<= IRIS_CACHE_BLORP
);
2847 static const unsigned dwords
[] = {
2848 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2849 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2850 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2851 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2853 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2854 [IRIS_CACHE_CS
] = 0,
2855 [IRIS_CACHE_BLORP
] = 0,
2858 return sizeof(uint32_t) * dwords
[cache_id
];
2862 * Create any state packets corresponding to the given shader stage
2863 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
2864 * This means that we can look up a program in the in-memory cache and
2865 * get most of the state packet without having to reconstruct it.
2868 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2869 enum iris_program_cache_id cache_id
,
2870 struct iris_compiled_shader
*shader
)
2874 iris_store_vs_state(devinfo
, shader
);
2876 case IRIS_CACHE_TCS
:
2877 iris_store_tcs_state(devinfo
, shader
);
2879 case IRIS_CACHE_TES
:
2880 iris_store_tes_state(devinfo
, shader
);
2883 iris_store_gs_state(devinfo
, shader
);
2886 iris_store_fs_state(devinfo
, shader
);
2889 case IRIS_CACHE_BLORP
:
2896 /* ------------------------------------------------------------------- */
2899 * Configure the URB.
2901 * XXX: write a real comment.
2904 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2906 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2907 const unsigned push_size_kB
= 32;
2908 unsigned entries
[4];
2912 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2913 if (!ice
->shaders
.prog
[i
]) {
2916 struct brw_vue_prog_data
*vue_prog_data
=
2917 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2918 size
[i
] = vue_prog_data
->urb_entry_size
;
2920 assert(size
[i
] != 0);
2923 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2924 1024 * ice
->shaders
.urb_size
,
2925 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2926 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2927 size
, entries
, start
);
2929 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2930 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2931 urb
._3DCommandSubOpcode
+= i
;
2932 urb
.VSURBStartingAddress
= start
[i
];
2933 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2934 urb
.VSNumberofURBEntries
= entries
[i
];
2939 static const uint32_t push_constant_opcodes
[] = {
2940 [MESA_SHADER_VERTEX
] = 21,
2941 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2942 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2943 [MESA_SHADER_GEOMETRY
] = 22,
2944 [MESA_SHADER_FRAGMENT
] = 23,
2945 [MESA_SHADER_COMPUTE
] = 0,
2949 * Add a surface to the validation list, as well as the buffer containing
2950 * the corresponding SURFACE_STATE.
2952 * Returns the binding table entry (offset to SURFACE_STATE).
2955 use_surface(struct iris_batch
*batch
,
2956 struct pipe_surface
*p_surf
,
2959 struct iris_surface
*surf
= (void *) p_surf
;
2961 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2962 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2964 return surf
->surface_state
.offset
;
2968 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2970 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->base
.texture
), false);
2971 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
2973 return isv
->surface_state
.offset
;
2977 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
2979 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
2980 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
2982 return cbuf
->surface_state
.offset
;
2986 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2988 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
2990 iris_use_pinned_bo(batch
, state_bo
, false);
2992 return ice
->state
.unbound_tex
.offset
;
2996 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
2998 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3000 iris_use_pinned_bo(batch
, state_bo
, false);
3002 return ice
->state
.null_fb
.offset
;
3006 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3007 struct iris_shader_state
*shs
, int i
)
3010 return use_null_surface(batch
, ice
);
3012 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3014 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3015 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3017 return surf_state
->offset
;
3021 * Populate the binding table for a given shader stage.
3023 * This fills out the table of pointers to surfaces required by the shader,
3024 * and also adds those buffers to the validation list so the kernel can make
3025 * resident before running our batch.
3028 iris_populate_binding_table(struct iris_context
*ice
,
3029 struct iris_batch
*batch
,
3030 gl_shader_stage stage
)
3032 const struct iris_binder
*binder
= &batch
->binder
;
3033 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3037 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3038 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
3040 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3041 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3044 if (stage
== MESA_SHADER_FRAGMENT
) {
3045 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3046 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3047 if (cso_fb
->nr_cbufs
) {
3048 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3049 if (cso_fb
->cbufs
[i
])
3050 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
3052 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3055 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3059 //assert(prog_data->binding_table.texture_start ==
3060 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
3062 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
3063 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
3064 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
3065 : use_null_surface(batch
, ice
);
3068 for (int i
= 0; i
< 1 + info
->num_ubos
; i
++) {
3069 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
3070 if (!cbuf
->surface_state
.res
)
3073 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
3076 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3077 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3078 * in st_atom_storagebuf.c so it'll compact them into one range, with
3079 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3081 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3082 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3083 bt_map
[s
++] = use_ssbo(batch
, ice
, shs
, i
);
3088 // XXX: not implemented yet
3089 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
3090 assert(prog_data
->binding_table
.plane_start
[1] == 0xd0d0d0d0);
3091 assert(prog_data
->binding_table
.plane_start
[2] == 0xd0d0d0d0);
3096 iris_use_optional_res(struct iris_batch
*batch
,
3097 struct pipe_resource
*res
,
3101 struct iris_bo
*bo
= iris_resource_bo(res
);
3102 iris_use_pinned_bo(batch
, bo
, writeable
);
3106 /* ------------------------------------------------------------------- */
3109 * Pin any BOs which were installed by a previous batch, and restored
3110 * via the hardware logical context mechanism.
3112 * We don't need to re-emit all state every batch - the hardware context
3113 * mechanism will save and restore it for us. This includes pointers to
3114 * various BOs...which won't exist unless we ask the kernel to pin them
3115 * by adding them to the validation list.
3117 * We can skip buffers if we've re-emitted those packets, as we're
3118 * overwriting those stale pointers with new ones, and don't actually
3119 * refer to the old BOs.
3122 iris_restore_context_saved_bos(struct iris_context
*ice
,
3123 struct iris_batch
*batch
,
3124 const struct pipe_draw_info
*draw
)
3126 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3128 const uint64_t clean
= ~ice
->state
.dirty
;
3130 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3131 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3134 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3135 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3138 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3139 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3142 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3143 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3146 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3147 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3150 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3151 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
3154 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
3155 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3160 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3162 for (int i
= 0; i
< 4; i
++) {
3163 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3165 if (range
->length
== 0)
3168 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3169 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3172 iris_use_pinned_bo(batch
, res
->bo
, false);
3174 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3178 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3179 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
3181 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3184 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3185 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3186 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3188 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3189 iris_use_pinned_bo(batch
, bo
, false);
3192 // XXX: scratch buffer
3196 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3197 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3199 if (cso_fb
->zsbuf
) {
3200 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3201 // XXX: depth might not be writable...
3202 iris_use_pinned_bo(batch
, zres
->bo
, true);
3206 if (draw
->index_size
> 0) {
3207 // XXX: index buffer
3210 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3211 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3212 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3213 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3214 iris_use_pinned_bo(batch
, res
->bo
, false);
3220 iris_upload_render_state(struct iris_context
*ice
,
3221 struct iris_batch
*batch
,
3222 const struct pipe_draw_info
*draw
)
3224 const uint64_t dirty
= ice
->state
.dirty
;
3226 struct iris_genx_state
*genx
= ice
->state
.genx
;
3227 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3228 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3230 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3231 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3232 uint32_t cc_vp_address
;
3234 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3235 uint32_t *cc_vp_map
=
3236 stream_state(batch
, ice
->state
.dynamic_uploader
,
3237 &ice
->state
.last_res
.cc_vp
,
3238 4 * ice
->state
.num_viewports
*
3239 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3240 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3242 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3243 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3244 if (cso_rast
->depth_clip_near
)
3246 if (cso_rast
->depth_clip_far
)
3249 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3250 ccv
.MinimumDepth
= zmin
;
3251 ccv
.MaximumDepth
= zmax
;
3254 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3257 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3258 ptr
.CCViewportPointer
= cc_vp_address
;
3262 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3263 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3264 ptr
.SFClipViewportPointer
=
3265 emit_state(batch
, ice
->state
.dynamic_uploader
,
3266 &ice
->state
.last_res
.sf_cl_vp
,
3267 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
3268 ice
->state
.num_viewports
, 64);
3274 // XXX: this is only flagged at setup, we assume a static configuration
3275 if (dirty
& IRIS_DIRTY_URB
) {
3276 iris_upload_urb_config(ice
, batch
);
3279 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3280 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3281 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3282 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3283 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
3284 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
3285 uint32_t blend_offset
;
3286 uint32_t *blend_map
=
3287 stream_state(batch
, ice
->state
.dynamic_uploader
,
3288 &ice
->state
.last_res
.blend
,
3289 4 * num_dwords
, 64, &blend_offset
);
3291 uint32_t blend_state_header
;
3292 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
3293 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3294 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
3297 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
3298 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
3299 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
3301 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3302 ptr
.BlendStatePointer
= blend_offset
;
3303 ptr
.BlendStatePointerValid
= true;
3307 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3308 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3311 stream_state(batch
, ice
->state
.dynamic_uploader
,
3312 &ice
->state
.last_res
.color_calc
,
3313 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
3315 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
3316 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
3317 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
3318 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
3319 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
3320 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
3321 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
3323 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3324 ptr
.ColorCalcStatePointer
= cc_offset
;
3325 ptr
.ColorCalcStatePointerValid
= true;
3329 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3330 // XXX: wrong dirty tracking...
3331 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3334 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
3335 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3340 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3342 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3343 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3345 /* The Skylake PRM contains the following restriction:
3347 * "The driver must ensure The following case does not occur
3348 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3349 * buffer 3 read length equal to zero committed followed by a
3350 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3353 * To avoid this, we program the buffers in the highest slots.
3354 * This way, slot 0 is only used if slot 3 is also used.
3358 for (int i
= 3; i
>= 0; i
--) {
3359 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3361 if (range
->length
== 0)
3364 // XXX: is range->block a constbuf index? it would be nice
3365 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3366 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3368 assert(cbuf
->data
.offset
% 32 == 0);
3370 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3371 pkt
.ConstantBody
.Buffer
[n
] =
3372 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
3373 : ro_bo(batch
->screen
->workaround_bo
, 0);
3380 struct iris_binder
*binder
= &batch
->binder
;
3382 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3383 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3384 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
3385 ptr
._3DCommandSubOpcode
= 38 + stage
;
3386 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
3391 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3392 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3393 iris_populate_binding_table(ice
, batch
, stage
);
3397 if (ice
->state
.need_border_colors
)
3398 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
3400 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3401 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
3402 !ice
->shaders
.prog
[stage
])
3405 struct pipe_resource
*res
= ice
->state
.sampler_table
[stage
].res
;
3407 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3409 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
3410 ptr
._3DCommandSubOpcode
= 43 + stage
;
3411 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table
[stage
].offset
;
3415 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
3416 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
3418 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
3419 if (ice
->state
.framebuffer
.samples
> 0)
3420 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
3424 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
3425 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
3426 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
3430 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3431 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
3434 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3437 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
3438 iris_use_pinned_bo(batch
, cache
->bo
, false);
3439 iris_batch_emit(batch
, shader
->derived_data
,
3440 iris_derived_program_state_size(stage
));
3442 if (stage
== MESA_SHADER_TESS_EVAL
) {
3443 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
3444 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
3445 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
3446 } else if (stage
== MESA_SHADER_GEOMETRY
) {
3447 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
3452 if (ice
->state
.streamout_active
) {
3453 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
3454 iris_batch_emit(batch
, genx
->so_buffers
,
3455 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
3456 for (int i
= 0; i
< 4; i
++) {
3457 struct iris_stream_output_target
*tgt
=
3458 (void *) ice
->state
.so_target
[i
];
3460 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3462 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3468 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
3469 uint32_t *decl_list
=
3470 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
3471 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
3474 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3475 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3477 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
3478 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
3479 sol
.SOFunctionEnable
= true;
3480 sol
.SOStatisticsEnable
= true;
3482 // XXX: GL_PRIMITIVES_GENERATED query
3483 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
;
3484 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
3487 assert(ice
->state
.streamout
);
3489 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
3490 GENX(3DSTATE_STREAMOUT_length
));
3493 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3494 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
3498 if (dirty
& IRIS_DIRTY_CLIP
) {
3499 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3500 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3502 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
3503 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
3504 if (wm_prog_data
->barycentric_interp_modes
&
3505 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
3506 cl
.NonPerspectiveBarycentricEnable
= true;
3508 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
3509 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
3511 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
3512 ARRAY_SIZE(cso_rast
->clip
));
3515 if (dirty
& IRIS_DIRTY_RASTER
) {
3516 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3517 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
3518 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
3522 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
3523 if (dirty
& IRIS_DIRTY_WM
) {
3524 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3525 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
3527 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
3528 wm
.BarycentricInterpolationMode
=
3529 wm_prog_data
->barycentric_interp_modes
;
3531 if (wm_prog_data
->early_fragment_tests
)
3532 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
3533 else if (wm_prog_data
->has_side_effects
)
3534 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
3536 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
3539 if (dirty
& IRIS_DIRTY_SBE
) {
3540 iris_emit_sbe(batch
, ice
);
3543 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
3544 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3545 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3546 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
3547 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
3548 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
3549 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3552 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
3553 ARRAY_SIZE(cso_blend
->ps_blend
));
3556 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
3557 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3558 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
3560 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
3561 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
3562 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
3563 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
3565 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
3568 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
3569 uint32_t scissor_offset
=
3570 emit_state(batch
, ice
->state
.dynamic_uploader
,
3571 &ice
->state
.last_res
.scissor
,
3572 ice
->state
.scissors
,
3573 sizeof(struct pipe_scissor_state
) *
3574 ice
->state
.num_viewports
, 32);
3576 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
3577 ptr
.ScissorRectPointer
= scissor_offset
;
3581 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
3582 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3583 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3585 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
3587 if (cso_fb
->zsbuf
) {
3588 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3589 // XXX: depth might not be writable...
3590 iris_use_pinned_bo(batch
, zres
->bo
, true);
3594 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
3595 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
3596 for (int i
= 0; i
< 32; i
++) {
3597 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
3602 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
3603 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3604 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
3608 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
3609 topo
.PrimitiveTopologyType
=
3610 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
3614 if (draw
->index_size
> 0) {
3615 struct iris_resource
*res
= NULL
;
3618 if (draw
->has_user_indices
) {
3619 u_upload_data(ice
->ctx
.stream_uploader
, 0,
3620 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
3621 &offset
, (struct pipe_resource
**) &res
);
3623 res
= (struct iris_resource
*) draw
->index
.resource
;
3627 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
3628 ib
.IndexFormat
= draw
->index_size
>> 1;
3630 ib
.BufferSize
= res
->bo
->size
;
3631 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
3635 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3636 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3637 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
3639 if (cso
->num_buffers
> 0) {
3640 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
3641 (1 + vb_dwords
* cso
->num_buffers
));
3643 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3644 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3645 iris_use_pinned_bo(batch
, res
->bo
, false);
3650 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
3651 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3652 const unsigned entries
= MAX2(cso
->count
, 1);
3653 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
3654 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
3655 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
3656 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
3659 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
3660 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
3661 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
3662 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3664 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
3665 if (vs_prog_data
->uses_vertexid
) {
3666 sgv
.VertexIDEnable
= true;
3667 sgv
.VertexIDComponentNumber
= 2;
3668 sgv
.VertexIDElementOffset
= cso
->count
;
3671 if (vs_prog_data
->uses_instanceid
) {
3672 sgv
.InstanceIDEnable
= true;
3673 sgv
.InstanceIDComponentNumber
= 3;
3674 sgv
.InstanceIDElementOffset
= cso
->count
;
3680 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
3681 if (draw
->primitive_restart
) {
3682 vf
.IndexedDrawCutIndexEnable
= true;
3683 vf
.CutIndex
= draw
->restart_index
;
3688 // XXX: Gen8 - PMA fix
3690 #define _3DPRIM_END_OFFSET 0x2420
3691 #define _3DPRIM_START_VERTEX 0x2430
3692 #define _3DPRIM_VERTEX_COUNT 0x2434
3693 #define _3DPRIM_INSTANCE_COUNT 0x2438
3694 #define _3DPRIM_START_INSTANCE 0x243C
3695 #define _3DPRIM_BASE_VERTEX 0x2440
3697 if (draw
->indirect
) {
3698 /* We don't support this MultidrawIndirect. */
3699 assert(!draw
->indirect
->indirect_draw_count
);
3701 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
3704 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3705 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
3706 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
3708 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3709 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
3710 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
3712 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3713 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
3714 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
3716 if (draw
->index_size
) {
3717 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3718 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
3719 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3721 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3722 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3723 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
3726 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3727 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3728 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3730 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3731 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
3737 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
3738 prim
.StartInstanceLocation
= draw
->start_instance
;
3739 prim
.InstanceCount
= draw
->instance_count
;
3740 prim
.VertexCountPerInstance
= draw
->count
;
3741 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
3743 // XXX: this is probably bonkers.
3744 prim
.StartVertexLocation
= draw
->start
;
3746 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
3748 if (draw
->index_size
) {
3749 prim
.BaseVertexLocation
+= draw
->index_bias
;
3751 prim
.StartVertexLocation
+= draw
->index_bias
;
3754 //prim.BaseVertexLocation = ...;
3757 if (!batch
->contains_draw
) {
3758 iris_restore_context_saved_bos(ice
, batch
, draw
);
3759 batch
->contains_draw
= true;
3764 * State module teardown.
3767 iris_destroy_state(struct iris_context
*ice
)
3769 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
3771 // XXX: unreference resources/surfaces.
3772 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
3773 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
3775 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
3777 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
3778 pipe_resource_reference(&ice
->state
.sampler_table
[stage
].res
, NULL
);
3780 free(ice
->state
.genx
);
3782 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
3783 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
3784 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
3785 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
3786 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
3789 /* ------------------------------------------------------------------- */
3792 flags_to_post_sync_op(uint32_t flags
)
3794 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
3795 return WriteImmediateData
;
3797 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
3798 return WritePSDepthCount
;
3800 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
3801 return WriteTimestamp
;
3807 * Do the given flags have a Post Sync or LRI Post Sync operation?
3809 static enum pipe_control_flags
3810 get_post_sync_flags(enum pipe_control_flags flags
)
3812 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
3813 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3814 PIPE_CONTROL_WRITE_TIMESTAMP
|
3815 PIPE_CONTROL_LRI_POST_SYNC_OP
;
3817 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
3818 * "LRI Post Sync Operation". So more than one bit set would be illegal.
3820 assert(util_bitcount(flags
) <= 1);
3825 // XXX: compute support
3826 #define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
3829 * Emit a series of PIPE_CONTROL commands, taking into account any
3830 * workarounds necessary to actually accomplish the caller's request.
3832 * Unless otherwise noted, spec quotations in this function come from:
3834 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
3835 * Restrictions for PIPE_CONTROL.
3837 * You should not use this function directly. Use the helpers in
3838 * iris_pipe_control.c instead, which may split the pipe control further.
3841 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
3842 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
3844 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3845 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
3846 enum pipe_control_flags non_lri_post_sync_flags
=
3847 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
3849 /* Recursive PIPE_CONTROL workarounds --------------------------------
3850 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
3852 * We do these first because we want to look at the original operation,
3853 * rather than any workarounds we set.
3855 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
3856 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
3857 * lists several workarounds:
3859 * "Project: SKL, KBL, BXT
3861 * If the VF Cache Invalidation Enable is set to a 1 in a
3862 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
3863 * sets to 0, with the VF Cache Invalidation Enable set to 0
3864 * needs to be sent prior to the PIPE_CONTROL with VF Cache
3865 * Invalidation Enable set to a 1."
3867 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
3870 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
3871 /* Project: SKL / Argument: LRI Post Sync Operation [23]
3873 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3874 * programmed prior to programming a PIPECONTROL command with "LRI
3875 * Post Sync Operation" in GPGPU mode of operation (i.e when
3876 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
3878 * The same text exists a few rows below for Post Sync Op.
3880 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
3883 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
3885 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
3886 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
3887 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
3889 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
3893 /* "Flush Types" workarounds ---------------------------------------------
3894 * We do these now because they may add post-sync operations or CS stalls.
3897 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
3898 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
3900 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3901 * 'Write PS Depth Count' or 'Write Timestamp'."
3904 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3905 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3906 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3907 bo
= batch
->screen
->workaround_bo
;
3911 /* #1130 from Gen10 workarounds page:
3913 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3914 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3915 * board stall if Render target cache flush is enabled."
3917 * Applicable to CNL B0 and C0 steppings only.
3919 * The wording here is unclear, and this workaround doesn't look anything
3920 * like the internal bug report recommendations, but leave it be for now...
3922 if (GEN_GEN
== 10) {
3923 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3924 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3925 } else if (flags
& non_lri_post_sync_flags
) {
3926 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3930 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3931 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3933 * "This bit must be DISABLED for operations other than writing
3936 * This seems like nonsense. An Ivybridge workaround requires us to
3937 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3938 * operation. Gen8+ requires us to emit depth stalls and depth cache
3939 * flushes together. So, it's hard to imagine this means anything other
3940 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3942 * We ignore the supposed restriction and do nothing.
3946 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3947 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3948 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3950 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3951 * PS_DEPTH_COUNT or TIMESTAMP queries."
3953 * TODO: Implement end-of-pipe checking.
3955 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3956 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3959 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3960 /* From the PIPE_CONTROL instruction table, bit 1:
3962 * "This bit is ignored if Depth Stall Enable is set.
3963 * Further, the render cache is not flushed even if Write Cache
3964 * Flush Enable bit is set."
3966 * We assert that the caller doesn't do this combination, to try and
3967 * prevent mistakes. It shouldn't hurt the GPU, though.
3969 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
3970 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
3973 /* PIPE_CONTROL page workarounds ------------------------------------- */
3975 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
3976 /* From the PIPE_CONTROL page itself:
3979 * Restriction: Pipe_control with CS-stall bit set must be issued
3980 * before a pipe-control command that has the State Cache
3981 * Invalidate bit set."
3983 flags
|= PIPE_CONTROL_CS_STALL
;
3986 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
3987 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
3990 * SW must always program Post-Sync Operation to "Write Immediate
3991 * Data" when Flush LLC is set."
3993 * For now, we just require the caller to do it.
3995 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
3998 /* "Post-Sync Operation" workarounds -------------------------------- */
4000 /* Project: All / Argument: Global Snapshot Count Reset [19]
4002 * "This bit must not be exercised on any product.
4003 * Requires stall bit ([20] of DW1) set."
4005 * We don't use this, so we just assert that it isn't used. The
4006 * PIPE_CONTROL instruction page indicates that they intended this
4007 * as a debug feature and don't think it is useful in production,
4008 * but it may actually be usable, should we ever want to.
4010 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
4012 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
4013 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
4014 /* Project: All / Arguments:
4016 * - Generic Media State Clear [16]
4017 * - Indirect State Pointers Disable [16]
4019 * "Requires stall bit ([20] of DW1) set."
4021 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
4022 * State Clear) says:
4024 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4025 * programmed prior to programming a PIPECONTROL command with "Media
4026 * State Clear" set in GPGPU mode of operation"
4028 * This is a subset of the earlier rule, so there's nothing to do.
4030 flags
|= PIPE_CONTROL_CS_STALL
;
4033 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
4034 /* Project: All / Argument: Store Data Index
4036 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4039 * For now, we just assert that the caller does this. We might want to
4040 * automatically add a write to the workaround BO...
4042 assert(non_lri_post_sync_flags
!= 0);
4045 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
4046 /* Project: All / Argument: Sync GFDT
4048 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4049 * than '0' or 0x2520[13] must be set."
4051 * For now, we just assert that the caller does this.
4053 assert(non_lri_post_sync_flags
!= 0);
4056 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
4057 /* Project: IVB+ / Argument: TLB inv
4059 * "Requires stall bit ([20] of DW1) set."
4061 * Also, from the PIPE_CONTROL instruction table:
4064 * Post Sync Operation or CS stall must be set to ensure a TLB
4065 * invalidation occurs. Otherwise no cycle will occur to the TLB
4066 * cache to invalidate."
4068 * This is not a subset of the earlier rule, so there's nothing to do.
4070 flags
|= PIPE_CONTROL_CS_STALL
;
4073 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
4074 /* TODO: The big Skylake GT4 post sync op workaround */
4077 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
4079 if (IS_COMPUTE_PIPELINE(batch
)) {
4080 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
4081 /* Project: SKL+ / Argument: Tex Invalidate
4082 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
4084 flags
|= PIPE_CONTROL_CS_STALL
;
4087 if (GEN_GEN
== 8 && (post_sync_flags
||
4088 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
4089 PIPE_CONTROL_DEPTH_STALL
|
4090 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4091 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4092 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
4093 /* Project: BDW / Arguments:
4095 * - LRI Post Sync Operation [23]
4096 * - Post Sync Op [15:14]
4098 * - Depth Stall [13]
4099 * - Render Target Cache Flush [12]
4100 * - Depth Cache Flush [0]
4101 * - DC Flush Enable [5]
4103 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
4106 flags
|= PIPE_CONTROL_CS_STALL
;
4108 /* Also, from the PIPE_CONTROL instruction table, bit 20:
4111 * This bit must be always set when PIPE_CONTROL command is
4112 * programmed by GPGPU and MEDIA workloads, except for the cases
4113 * when only Read Only Cache Invalidation bits are set (State
4114 * Cache Invalidation Enable, Instruction cache Invalidation
4115 * Enable, Texture Cache Invalidation Enable, Constant Cache
4116 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
4117 * need not implemented when FF_DOP_CG is disable via "Fixed
4118 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
4120 * It sounds like we could avoid CS stalls in some cases, but we
4121 * don't currently bother. This list isn't exactly the list above,
4127 /* "Stall" workarounds ----------------------------------------------
4128 * These have to come after the earlier ones because we may have added
4129 * some additional CS stalls above.
4132 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
4133 /* Project: PRE-SKL, VLV, CHV
4135 * "[All Stepping][All SKUs]:
4137 * One of the following must also be set:
4139 * - Render Target Cache Flush Enable ([12] of DW1)
4140 * - Depth Cache Flush Enable ([0] of DW1)
4141 * - Stall at Pixel Scoreboard ([1] of DW1)
4142 * - Depth Stall ([13] of DW1)
4143 * - Post-Sync Operation ([13] of DW1)
4144 * - DC Flush Enable ([5] of DW1)"
4146 * If we don't already have one of those bits set, we choose to add
4147 * "Stall at Pixel Scoreboard". Some of the other bits require a
4148 * CS stall as a workaround (see above), which would send us into
4149 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
4150 * appears to be safe, so we choose that.
4152 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4153 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4154 PIPE_CONTROL_WRITE_IMMEDIATE
|
4155 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4156 PIPE_CONTROL_WRITE_TIMESTAMP
|
4157 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
4158 PIPE_CONTROL_DEPTH_STALL
|
4159 PIPE_CONTROL_DATA_CACHE_FLUSH
;
4160 if (!(flags
& wa_bits
))
4161 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4164 /* Emit --------------------------------------------------------------- */
4166 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
4167 pc
.LRIPostSyncOperation
= NoLRIOperation
;
4168 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
4169 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
4170 pc
.StoreDataIndex
= 0;
4171 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
4172 pc
.GlobalSnapshotCountReset
=
4173 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
4174 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
4175 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
4176 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4177 pc
.RenderTargetCacheFlushEnable
=
4178 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
4179 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4180 pc
.StateCacheInvalidationEnable
=
4181 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4182 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4183 pc
.ConstantCacheInvalidationEnable
=
4184 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4185 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
4186 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
4187 pc
.InstructionCacheInvalidateEnable
=
4188 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
4189 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
4190 pc
.IndirectStatePointersDisable
=
4191 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
4192 pc
.TextureCacheInvalidationEnable
=
4193 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4194 pc
.Address
= ro_bo(bo
, offset
);
4195 pc
.ImmediateData
= imm
;
4200 genX(init_state
)(struct iris_context
*ice
)
4202 struct pipe_context
*ctx
= &ice
->ctx
;
4203 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
4205 ctx
->create_blend_state
= iris_create_blend_state
;
4206 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
4207 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
4208 ctx
->create_sampler_state
= iris_create_sampler_state
;
4209 ctx
->create_sampler_view
= iris_create_sampler_view
;
4210 ctx
->create_surface
= iris_create_surface
;
4211 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
4212 ctx
->create_compute_state
= iris_create_compute_state
;
4213 ctx
->bind_blend_state
= iris_bind_blend_state
;
4214 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
4215 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
4216 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
4217 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
4218 ctx
->bind_compute_state
= iris_bind_compute_state
;
4219 ctx
->delete_blend_state
= iris_delete_state
;
4220 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
4221 ctx
->delete_fs_state
= iris_delete_state
;
4222 ctx
->delete_rasterizer_state
= iris_delete_state
;
4223 ctx
->delete_sampler_state
= iris_delete_state
;
4224 ctx
->delete_vertex_elements_state
= iris_delete_state
;
4225 ctx
->delete_compute_state
= iris_delete_state
;
4226 ctx
->delete_tcs_state
= iris_delete_state
;
4227 ctx
->delete_tes_state
= iris_delete_state
;
4228 ctx
->delete_gs_state
= iris_delete_state
;
4229 ctx
->delete_vs_state
= iris_delete_state
;
4230 ctx
->set_blend_color
= iris_set_blend_color
;
4231 ctx
->set_clip_state
= iris_set_clip_state
;
4232 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
4233 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
4234 ctx
->set_sampler_views
= iris_set_sampler_views
;
4235 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
4236 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
4237 ctx
->set_sample_mask
= iris_set_sample_mask
;
4238 ctx
->set_scissor_states
= iris_set_scissor_states
;
4239 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
4240 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
4241 ctx
->set_viewport_states
= iris_set_viewport_states
;
4242 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
4243 ctx
->surface_destroy
= iris_surface_destroy
;
4244 ctx
->draw_vbo
= iris_draw_vbo
;
4245 ctx
->launch_grid
= iris_launch_grid
;
4246 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
4247 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
4248 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
4250 ice
->vtbl
.destroy_state
= iris_destroy_state
;
4251 ice
->vtbl
.init_render_context
= iris_init_render_context
;
4252 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
4253 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
4254 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
4255 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
4256 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
4257 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
4258 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
4259 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
4260 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
4261 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
4263 ice
->state
.dirty
= ~0ull;
4265 ice
->state
.sample_mask
= 0xffff;
4266 ice
->state
.num_viewports
= 1;
4267 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
4269 /* Make a 1x1x1 null surface for unbound textures */
4270 void *null_surf_map
=
4271 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
4272 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
4273 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));