2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "iris_batch.h"
43 #include "iris_context.h"
44 #include "iris_resource.h"
46 #define __gen_address_type unsigned
47 #define __gen_user_data void
50 __gen_combine_address(void *user_data
, void *location
,
51 unsigned address
, uint32_t delta
)
56 #define __genxml_cmd_length(cmd) cmd ## _length
57 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
58 #define __genxml_cmd_header(cmd) cmd ## _header
59 #define __genxml_cmd_pack(cmd) cmd ## _pack
61 #define iris_pack_command(cmd, dst, name) \
62 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
63 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
64 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
65 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
69 #define iris_pack_state(cmd, dst, name) \
70 for (struct cmd name = {}, \
71 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
72 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
75 #define iris_emit_cmd(batch, cmd, name) \
76 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
77 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
79 #include "genxml/genX_pack.h"
80 #include "genxml/gen_macros.h"
82 #define MOCS_WB (2 << 1)
84 UNUSED
static void pipe_asserts()
86 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
88 /* pipe_logicop happens to match the hardware. */
89 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
90 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
91 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
92 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
93 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
94 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
95 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
96 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
97 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
98 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
99 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
100 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
101 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
102 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
103 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
104 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
106 /* pipe_blend_func happens to match the hardware. */
107 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
108 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
109 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
110 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
111 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
112 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
113 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
114 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
115 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
116 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
117 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
118 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
119 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
120 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
121 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
122 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
123 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
124 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
125 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
127 /* pipe_blend_func happens to match the hardware. */
128 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
129 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
130 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
131 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
132 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
134 /* pipe_stencil_op happens to match the hardware. */
135 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
136 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
137 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
138 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
139 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
140 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
141 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
142 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
147 translate_compare_func(enum pipe_compare_func pipe_func
)
149 static const unsigned map
[] = {
150 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
151 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
152 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
153 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
154 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
155 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
156 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
157 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
159 return map
[pipe_func
];
163 translate_shadow_func(enum pipe_compare_func pipe_func
)
165 /* Gallium specifies the result of shadow comparisons as:
167 * 1 if ref <op> texel,
172 * 0 if texel <op> ref,
175 * So we need to flip the operator and also negate.
177 static const unsigned map
[] = {
178 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
179 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
180 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
181 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
182 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
183 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
184 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
185 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
187 return map
[pipe_func
];
191 translate_cull_mode(unsigned pipe_face
)
193 static const unsigned map
[4] = {
194 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
195 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
196 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
197 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
199 return map
[pipe_face
];
203 translate_fill_mode(unsigned pipe_polymode
)
205 static const unsigned map
[4] = {
206 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
207 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
208 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
209 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
211 return map
[pipe_polymode
];
215 iris_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
220 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
225 iris_set_blend_color(struct pipe_context
*ctx
,
226 const struct pipe_blend_color
*state
)
228 struct iris_context
*ice
= (struct iris_context
*) ctx
;
230 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
231 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
234 struct iris_blend_state
{
235 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
236 uint32_t blend_state
[GENX(BLEND_STATE_length
)];
237 uint32_t blend_entries
[BRW_MAX_DRAW_BUFFERS
*
238 GENX(BLEND_STATE_ENTRY_length
)];
242 iris_create_blend_state(struct pipe_context
*ctx
,
243 const struct pipe_blend_state
*state
)
245 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
247 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
248 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
249 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
250 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
251 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
252 bs
.ColorDitherEnable
= state
->dither
;
253 //bs.AlphaTestEnable = <comes from alpha state> :(
254 //bs.AlphaTestFunction = <comes from alpha state> :(
257 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
258 //pb.HasWriteableRT = <comes from somewhere> :(
259 //pb.AlphaTestEnable = <comes from alpha state> :(
260 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
261 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
263 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
265 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
266 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
267 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
268 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
271 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
272 iris_pack_state(GENX(BLEND_STATE_ENTRY
), &cso
->blend_entries
[i
], be
) {
273 be
.LogicOpEnable
= state
->logicop_enable
;
274 be
.LogicOpFunction
= state
->logicop_func
;
276 be
.PreBlendSourceOnlyClampEnable
= false;
277 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
278 be
.PreBlendColorClampEnable
= true;
279 be
.PostBlendColorClampEnable
= true;
281 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
283 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
284 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
285 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
286 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
287 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
288 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
290 be
.WriteDisableRed
= state
->rt
[i
].colormask
& PIPE_MASK_R
;
291 be
.WriteDisableGreen
= state
->rt
[i
].colormask
& PIPE_MASK_G
;
292 be
.WriteDisableBlue
= state
->rt
[i
].colormask
& PIPE_MASK_B
;
293 be
.WriteDisableAlpha
= state
->rt
[i
].colormask
& PIPE_MASK_A
;
301 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
303 struct iris_context
*ice
= (struct iris_context
*) ctx
;
304 ice
->state
.cso_blend
= state
;
305 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
306 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
309 struct iris_depth_stencil_alpha_state
{
310 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
311 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
313 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
317 iris_create_zsa_state(struct pipe_context
*ctx
,
318 const struct pipe_depth_stencil_alpha_state
*state
)
320 struct iris_depth_stencil_alpha_state
*cso
=
321 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
323 cso
->alpha
= state
->alpha
;
325 bool two_sided_stencil
= state
->stencil
[1].enabled
;
327 /* The state tracker needs to optimize away EQUAL writes for us. */
328 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
330 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
331 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
332 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
333 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
334 wmds
.StencilTestFunction
=
335 translate_compare_func(state
->stencil
[0].func
);
336 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
337 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
338 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
339 wmds
.BackfaceStencilTestFunction
=
340 translate_compare_func(state
->stencil
[1].func
);
341 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
342 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
343 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
344 wmds
.StencilBufferWriteEnable
=
345 state
->stencil
[0].writemask
!= 0 ||
346 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
347 wmds
.DepthTestEnable
= state
->depth
.enabled
;
348 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
349 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
350 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
351 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
352 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
353 //wmds.StencilReferenceValue = <comes from elsewhere>
354 //wmds.BackfaceStencilReferenceValue = <comes from elsewhere>
357 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
358 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
359 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
366 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
368 struct iris_context
*ice
= (struct iris_context
*) ctx
;
369 ice
->state
.cso_zsa
= state
;
370 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
371 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
374 struct iris_rasterizer_state
{
375 uint32_t sf
[GENX(3DSTATE_SF_length
)];
376 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
377 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
378 uint32_t wm
[GENX(3DSTATE_WM_length
)];
380 bool flatshade
; /* for shader state */
381 bool light_twoside
; /* for shader state */
382 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
383 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
385 uint8_t line_stipple_factor
;
386 uint16_t line_stipple_pattern
;
390 iris_create_rasterizer_state(struct pipe_context
*ctx
,
391 const struct pipe_rasterizer_state
*state
)
393 struct iris_rasterizer_state
*cso
=
394 malloc(sizeof(struct iris_rasterizer_state
));
397 sprite_coord_mode
-> SBE PointSpriteTextureCoordinateOrigin
398 sprite_coord_enable
-> SBE PointSpriteTextureCoordinateEnable
399 point_quad_rasterization
-> SBE
?
404 force_persample_interp
- ?
407 offset_units_unscaled
- cap
not exposed
410 unsigned line_stipple_factor
:8; /**< [1..256] actually */
411 unsigned line_stipple_pattern
:16;
414 cso
->flatshade
= state
->flatshade
;
415 cso
->light_twoside
= state
->light_twoside
;
416 cso
->rasterizer_discard
= state
->rasterizer_discard
;
417 cso
->line_stipple_factor
= state
->line_stipple_factor
;
418 cso
->line_stipple_pattern
= state
->line_stipple_pattern
;
419 // for 3DSTATE_MULTISAMPLE, if we want it.
420 //cso->half_pixel_center = state->half_pixel_center;
422 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
423 sf
.StatisticsEnable
= true;
424 sf
.ViewportTransformEnable
= true;
425 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
426 sf
.LineEndCapAntialiasingRegionWidth
=
427 state
->line_smooth
? _10pixels
: _05pixels
;
428 sf
.LastPixelEnable
= state
->line_last_pixel
;
429 sf
.LineWidth
= state
->line_width
;
430 sf
.SmoothPointEnable
= state
->point_smooth
;
431 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
432 sf
.PointWidth
= state
->point_size
;
434 if (state
->flatshade_first
) {
435 sf
.TriangleStripListProvokingVertexSelect
= 2;
436 sf
.TriangleFanProvokingVertexSelect
= 2;
437 sf
.LineStripListProvokingVertexSelect
= 1;
439 sf
.TriangleFanProvokingVertexSelect
= 1;
444 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
445 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
446 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
447 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
448 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
449 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
450 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
451 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
452 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
453 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
454 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
455 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
456 rr
.SmoothPointEnable
= state
->point_smooth
;
457 rr
.AntialiasingEnable
= state
->line_smooth
;
458 rr
.ScissorRectangleEnable
= state
->scissor
;
459 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
460 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
461 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
464 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
465 cl
.StatisticsEnable
= true;
466 cl
.EarlyCullEnable
= true;
467 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
468 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
469 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
470 cl
.GuardbandClipTestEnable
= true;
471 cl
.ClipMode
= CLIPMODE_NORMAL
;
472 cl
.ClipEnable
= true;
473 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
474 cl
.MinimumPointWidth
= 0.125;
475 cl
.MaximumPointWidth
= 255.875;
476 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
477 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
479 if (state
->flatshade_first
) {
480 cl
.TriangleStripListProvokingVertexSelect
= 2;
481 cl
.TriangleFanProvokingVertexSelect
= 2;
482 cl
.LineStripListProvokingVertexSelect
= 1;
484 cl
.TriangleFanProvokingVertexSelect
= 1;
488 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
489 wm
.LineAntialiasingRegionWidth
= _10pixels
;
490 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
491 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
492 wm
.StatisticsEnable
= true;
493 wm
.LineStippleEnable
= state
->line_stipple_enable
;
494 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
495 // wm.BarycentricInterpolationMode = <comes from FS program> :(
496 // wm.EarlyDepthStencilControl = <comes from FS program> :(
503 translate_wrap(unsigned pipe_wrap
)
505 static const unsigned map
[] = {
506 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
507 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
508 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
509 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
510 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
511 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
512 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
513 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
515 return map
[pipe_wrap
];
519 * Return true if the given wrap mode requires the border color to exist.
522 wrap_mode_needs_border_color(unsigned wrap_mode
)
524 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
528 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
530 static const unsigned map
[] = {
531 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
532 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
533 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
535 return map
[pipe_mip
];
538 struct iris_sampler_state
{
539 struct pipe_sampler_state base
;
541 bool needs_border_color
;
543 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
547 iris_create_sampler_state(struct pipe_context
*pctx
,
548 const struct pipe_sampler_state
*state
)
550 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
555 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
556 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
558 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
559 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
560 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
562 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
563 wrap_mode_needs_border_color(wrap_t
) ||
564 wrap_mode_needs_border_color(wrap_r
);
566 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
567 samp
.TCXAddressControlMode
= wrap_s
;
568 samp
.TCYAddressControlMode
= wrap_t
;
569 samp
.TCZAddressControlMode
= wrap_r
;
570 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
571 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
572 samp
.MinModeFilter
= state
->min_img_filter
;
573 samp
.MagModeFilter
= state
->mag_img_filter
;
574 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
575 samp
.MaximumAnisotropy
= RATIO21
;
577 if (state
->max_anisotropy
>= 2) {
578 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
579 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
580 samp
.AnisotropicAlgorithm
= EWAApproximation
;
583 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
584 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
586 samp
.MaximumAnisotropy
=
587 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
590 /* Set address rounding bits if not using nearest filtering. */
591 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
592 samp
.UAddressMinFilterRoundingEnable
= true;
593 samp
.VAddressMinFilterRoundingEnable
= true;
594 samp
.RAddressMinFilterRoundingEnable
= true;
597 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
598 samp
.UAddressMagFilterRoundingEnable
= true;
599 samp
.VAddressMagFilterRoundingEnable
= true;
600 samp
.RAddressMagFilterRoundingEnable
= true;
603 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
604 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
606 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
608 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
609 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
610 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
611 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
613 //samp.BorderColorPointer = <<comes from elsewhere>>
619 static struct pipe_sampler_view
*
620 iris_create_sampler_view(struct pipe_context
*ctx
,
621 struct pipe_resource
*texture
,
622 const struct pipe_sampler_view
*state
)
624 struct pipe_sampler_view
*sampler_view
= CALLOC_STRUCT(pipe_sampler_view
);
629 /* initialize base object */
630 *sampler_view
= *state
;
631 sampler_view
->texture
= NULL
;
632 pipe_resource_reference(&sampler_view
->texture
, texture
);
633 pipe_reference_init(&sampler_view
->reference
, 1);
634 sampler_view
->context
= ctx
;
638 static struct pipe_surface
*
639 iris_create_surface(struct pipe_context
*ctx
,
640 struct pipe_resource
*tex
,
641 const struct pipe_surface
*surf_tmpl
)
643 struct pipe_surface
*surface
= CALLOC_STRUCT(pipe_surface
);
648 pipe_reference_init(&surface
->reference
, 1);
649 pipe_resource_reference(&surface
->texture
, tex
);
650 surface
->context
= ctx
;
651 surface
->format
= surf_tmpl
->format
;
652 surface
->width
= tex
->width0
;
653 surface
->height
= tex
->height0
;
654 surface
->texture
= tex
;
655 surface
->u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
656 surface
->u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
657 surface
->u
.tex
.level
= surf_tmpl
->u
.tex
.level
;
663 iris_set_sampler_views(struct pipe_context
*ctx
,
664 enum pipe_shader_type shader
,
665 unsigned start
, unsigned count
,
666 struct pipe_sampler_view
**views
)
671 iris_bind_sampler_states(struct pipe_context
*ctx
,
672 enum pipe_shader_type shader
,
673 unsigned start
, unsigned count
,
679 iris_set_clip_state(struct pipe_context
*ctx
,
680 const struct pipe_clip_state
*state
)
685 iris_set_polygon_stipple(struct pipe_context
*ctx
,
686 const struct pipe_poly_stipple
*state
)
688 struct iris_context
*ice
= (struct iris_context
*) ctx
;
689 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
690 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
694 iris_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
699 iris_set_scissor_states(struct pipe_context
*ctx
,
701 unsigned num_scissors
,
702 const struct pipe_scissor_state
*state
)
704 struct iris_context
*ice
= (struct iris_context
*) ctx
;
706 for (unsigned i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
707 ice
->state
.scissors
[i
] = *state
;
710 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
714 iris_set_stencil_ref(struct pipe_context
*ctx
,
715 const struct pipe_stencil_ref
*state
)
717 struct iris_context
*ice
= (struct iris_context
*) ctx
;
718 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
719 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
723 struct iris_viewport_state
{
724 uint32_t sf_cl_vp
[GENX(3DSTATE_SF_length
)];
728 extent_from_matrix(const struct pipe_viewport_state
*state
, int axis
)
730 return fabsf(state
->scale
[axis
]) * state
->translate
[axis
];
735 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
736 float m00
, float m11
, float m30
, float m31
,
737 float *xmin
, float *xmax
,
738 float *ymin
, float *ymax
)
740 /* According to the "Vertex X,Y Clamping and Quantization" section of the
741 * Strips and Fans documentation:
743 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
744 * fixed-point "guardband" range supported by the rasterization hardware"
748 * "In almost all circumstances, if an object’s vertices are actually
749 * modified by this clamping (i.e., had X or Y coordinates outside of
750 * the guardband extent the rendered object will not match the intended
751 * result. Therefore software should take steps to ensure that this does
752 * not happen - e.g., by clipping objects such that they do not exceed
753 * these limits after the Drawing Rectangle is applied."
755 * I believe the fundamental restriction is that the rasterizer (in
756 * the SF/WM stages) have a limit on the number of pixels that can be
757 * rasterized. We need to ensure any coordinates beyond the rasterizer
758 * limit are handled by the clipper. So effectively that limit becomes
759 * the clipper's guardband size.
763 * "In addition, in order to be correctly rendered, objects must have a
764 * screenspace bounding box not exceeding 8K in the X or Y direction.
765 * This additional restriction must also be comprehended by software,
766 * i.e., enforced by use of clipping."
768 * This makes no sense. Gen7+ hardware supports 16K render targets,
769 * and you definitely need to be able to draw polygons that fill the
770 * surface. Our assumption is that the rasterizer was limited to 8K
771 * on Sandybridge, which only supports 8K surfaces, and it was actually
772 * increased to 16K on Ivybridge and later.
774 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
776 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
778 if (m00
!= 0 && m11
!= 0) {
779 /* First, we compute the screen-space render area */
780 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
781 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
782 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
783 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
785 /* We want the guardband to be centered on that */
786 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
787 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
788 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
789 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
791 /* Now we need it in native device coordinates */
792 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
793 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
794 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
795 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
797 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
798 * flipped upside-down. X should be fine though.
800 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
803 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
804 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
806 /* The viewport scales to 0, so nothing will be rendered. */
816 iris_set_viewport_states(struct pipe_context
*ctx
,
818 unsigned num_viewports
,
819 const struct pipe_viewport_state
*state
)
821 struct iris_viewport_state
*cso
=
822 malloc(sizeof(struct iris_viewport_state
));
824 for (unsigned i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
825 float x_extent
= extent_from_matrix(&state
[i
], 0);
826 float y_extent
= extent_from_matrix(&state
[i
], 1);
828 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), cso
->sf_cl_vp
, vp
) {
829 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
830 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
831 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
832 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
833 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
834 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
835 /* XXX: in i965 this is computed based on the drawbuffer size,
836 * but we don't have that here...
838 vp
.XMinClipGuardband
= -1.0;
839 vp
.XMaxClipGuardband
= 1.0;
840 vp
.YMinClipGuardband
= -1.0;
841 vp
.YMaxClipGuardband
= 1.0;
842 vp
.XMinViewPort
= -x_extent
;
843 vp
.XMaxViewPort
= x_extent
;
844 vp
.YMinViewPort
= -y_extent
;
845 vp
.YMaxViewPort
= y_extent
;
851 iris_set_framebuffer_state(struct pipe_context
*ctx
,
852 const struct pipe_framebuffer_state
*state
)
857 iris_set_constant_buffer(struct pipe_context
*ctx
,
858 enum pipe_shader_type shader
, uint index
,
859 const struct pipe_constant_buffer
*cb
)
865 iris_sampler_view_destroy(struct pipe_context
*ctx
,
866 struct pipe_sampler_view
*state
)
868 pipe_resource_reference(&state
->texture
, NULL
);
874 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*surface
)
876 pipe_resource_reference(&surface
->texture
, NULL
);
881 iris_delete_state(struct pipe_context
*ctx
, void *state
)
886 struct iris_vertex_buffer_state
{
887 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
888 unsigned length
; /* length of 3DSTATE_VERTEX_BUFFERS in DWords */
892 iris_set_vertex_buffers(struct pipe_context
*ctx
,
893 unsigned start_slot
, unsigned count
,
894 const struct pipe_vertex_buffer
*buffers
)
896 struct iris_vertex_buffer_state
*cso
=
897 malloc(sizeof(struct iris_vertex_buffer_state
));
899 cso
->length
= 4 * count
- 1;
901 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
902 vb
.DWordLength
= cso
->length
;
905 /* If there are no buffers, do nothing. We can leave the stale
906 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
907 * elements that point to them, it should be fine.
912 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
914 for (unsigned i
= 0; i
< count
; i
++) {
915 assert(!buffers
[i
].is_user_buffer
);
917 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
918 vb
.VertexBufferIndex
= start_slot
+ i
;
920 vb
.AddressModifyEnable
= true;
921 vb
.BufferPitch
= buffers
[i
].stride
;
922 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
923 //vb.BufferSize = bo->size;
926 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
929 /* XXX: actually do something with this! */
932 struct iris_vertex_element_state
{
933 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
934 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)];
939 iris_create_vertex_elements(struct pipe_context
*ctx
,
941 const struct pipe_vertex_element
*state
)
943 struct iris_vertex_element_state
*cso
=
944 malloc(sizeof(struct iris_vertex_element_state
));
949 * - create edge flag one
951 * - if those are necessary, use count + 1/2/3... OR in the length
953 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
955 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
957 for (int i
= 0; i
< count
; i
++) {
958 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
959 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
961 ve
.SourceElementOffset
= state
[i
].src_offset
;
962 ve
.SourceElementFormat
=
963 iris_isl_format_for_pipe_format(state
[i
].src_format
);
966 iris_pack_state(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
, vi
) {
967 vi
.VertexElementIndex
= i
;
968 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
969 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
972 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
979 iris_create_compute_state(struct pipe_context
*ctx
,
980 const struct pipe_compute_state
*state
)
985 static struct pipe_stream_output_target
*
986 iris_create_stream_output_target(struct pipe_context
*ctx
,
987 struct pipe_resource
*res
,
988 unsigned buffer_offset
,
989 unsigned buffer_size
)
991 struct pipe_stream_output_target
*t
=
992 CALLOC_STRUCT(pipe_stream_output_target
);
996 pipe_reference_init(&t
->reference
, 1);
997 pipe_resource_reference(&t
->buffer
, res
);
998 t
->buffer_offset
= buffer_offset
;
999 t
->buffer_size
= buffer_size
;
1004 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1005 struct pipe_stream_output_target
*t
)
1007 pipe_resource_reference(&t
->buffer
, NULL
);
1012 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1013 unsigned num_targets
,
1014 struct pipe_stream_output_target
**targets
,
1015 const unsigned *offsets
)
1020 iris_upload_render_state(struct iris_context
*ice
, struct iris_batch
*batch
)
1022 const uint64_t dirty
= ice
->state
.dirty
;
1024 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
1025 // XXX: import stencil ref...
1026 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1027 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
1030 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
1031 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1032 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1033 ptr
.CCViewportPointer
=
1034 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1038 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
1039 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1040 iris_batch_emit(batch
, cso
->ps_blend
, sizeof(cso
->ps_blend
));
1043 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
1044 struct iris_blend_state
*cso
= ice
->state
.cso_blend
;
1045 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1046 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1047 // (alpha test function/enable) + has writeable RT from ???????
1050 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
1051 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
1052 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
1053 ptr
.CCViewportPointer
=
1054 iris_emit_state(batch
, cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
1061 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
- SF_CLIP_VIEWPORT
1062 -> pipe_viewport_state
for matrix elements
, guardband is calculated
1063 from those
. can calculate screen space from matrix apparently
...
1065 3DSTATE_SCISSOR_STATE_POINTERS
- SCISSOR_RECT
1066 -> from ice
->state
.scissors
1068 3DSTATE_PUSH_CONSTANT_ALLOC_
*
1072 3DSTATE_CC_STATE_POINTERS
- COLOR_CALC_STATE
1073 -> from ice
->state
.blend_color
+ iris_depth_stencil_alpha_state
1076 3DSTATE_CONSTANT_
* - push constants
1084 - render targets
- write
and read
1085 3DSTATE_BINDING_TABLE_POINTERS_
*
1088 3DSTATE_SAMPLER_STATE_POINTERS_
*
1103 3DSTATE_SO_DECL_LIST
1106 -> iris_raster_state
+ ??? (Non
-perspective Bary
, ForceZeroRTAIndex
)
1110 -> iris_raster_state
1113 -> iris_raster_state
+ FS
state (barycentric
, EDSC
)
1115 -> iris_raster_state (point sprite texture coordinate origin
)
1116 -> bunch of shader state
...
1120 3DSTATE_DEPTH_BUFFER
1121 3DSTATE_HIER_DEPTH_BUFFER
1122 3DSTATE_STENCIL_BUFFER
1123 3DSTATE_CLEAR_PARAMS
1124 -> iris_framebuffer_state
?
1127 -> pipe_draw_info (prim_mode
)
1129 -> pipe_draw_info (restart_index
, primitive_restart
)
1131 3DSTATE_INDEX_BUFFER
1132 -> pipe_draw_info (index
)
1133 3DSTATE_VERTEX_BUFFERS
1134 -> pipe_vertex_buffer (set_vertex_buffer hook
)
1135 3DSTATE_VERTEX_ELEMENTS
1136 -> iris_vertex_element
1137 3DSTATE_VF_INSTANCING
1138 -> iris_vertex_element
1141 3DSTATE_VF_COMPONENT_PACKING
1148 3DSTATE_POLY_STIPPLE_OFFSET
1149 3DSTATE_POLY_STIPPLE_PATTERN
1150 -> ice
->state
.poly_stipple
1151 3DSTATE_LINE_STIPPLE
1152 -> iris_raster_state
1155 3DSTATE_AA_LINE_PARAMETERS
1156 3DSTATE_WM_CHROMAKEY
1157 3DSTATE_SAMPLE_PATTERN
1158 3DSTATE_DRAWING_RECTANGLE
1164 iris_bind_state(struct pipe_context
*ctx
, void *state
)
1169 iris_init_state_functions(struct pipe_context
*ctx
)
1171 ctx
->create_blend_state
= iris_create_blend_state
;
1172 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
1173 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
1174 ctx
->create_sampler_state
= iris_create_sampler_state
;
1175 ctx
->create_sampler_view
= iris_create_sampler_view
;
1176 ctx
->create_surface
= iris_create_surface
;
1177 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
1178 ctx
->create_compute_state
= iris_create_compute_state
;
1179 ctx
->bind_blend_state
= iris_bind_blend_state
;
1180 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
1181 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
1182 ctx
->bind_fs_state
= iris_bind_state
;
1183 ctx
->bind_rasterizer_state
= iris_bind_state
;
1184 ctx
->bind_vertex_elements_state
= iris_bind_state
;
1185 ctx
->bind_compute_state
= iris_bind_state
;
1186 ctx
->bind_tcs_state
= iris_bind_state
;
1187 ctx
->bind_tes_state
= iris_bind_state
;
1188 ctx
->bind_gs_state
= iris_bind_state
;
1189 ctx
->bind_vs_state
= iris_bind_state
;
1190 ctx
->delete_blend_state
= iris_delete_state
;
1191 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
1192 ctx
->delete_fs_state
= iris_delete_state
;
1193 ctx
->delete_rasterizer_state
= iris_delete_state
;
1194 ctx
->delete_sampler_state
= iris_delete_state
;
1195 ctx
->delete_vertex_elements_state
= iris_delete_state
;
1196 ctx
->delete_compute_state
= iris_delete_state
;
1197 ctx
->delete_tcs_state
= iris_delete_state
;
1198 ctx
->delete_tes_state
= iris_delete_state
;
1199 ctx
->delete_gs_state
= iris_delete_state
;
1200 ctx
->delete_vs_state
= iris_delete_state
;
1201 ctx
->set_blend_color
= iris_set_blend_color
;
1202 ctx
->set_clip_state
= iris_set_clip_state
;
1203 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
1204 ctx
->set_sampler_views
= iris_set_sampler_views
;
1205 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
1206 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
1207 ctx
->set_sample_mask
= iris_set_sample_mask
;
1208 ctx
->set_scissor_states
= iris_set_scissor_states
;
1209 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
1210 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
1211 ctx
->set_viewport_states
= iris_set_viewport_states
;
1212 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
1213 ctx
->surface_destroy
= iris_surface_destroy
;
1214 ctx
->draw_vbo
= iris_draw_vbo
;
1215 ctx
->launch_grid
= iris_launch_grid
;
1216 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
1217 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
1218 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;