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20 * DEALINGS IN THE SOFTWARE.
26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_pipe.h"
105 #include "iris_resource.h"
107 #define __gen_address_type struct iris_address
108 #define __gen_user_data struct iris_batch
110 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
113 __gen_combine_address(struct iris_batch
*batch
, void *location
,
114 struct iris_address addr
, uint32_t delta
)
116 uint64_t result
= addr
.offset
+ delta
;
119 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
120 /* Assume this is a general address, not relative to a base. */
121 result
+= addr
.bo
->gtt_offset
;
127 #define __genxml_cmd_length(cmd) cmd ## _length
128 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
129 #define __genxml_cmd_header(cmd) cmd ## _header
130 #define __genxml_cmd_pack(cmd) cmd ## _pack
132 #define _iris_pack_command(batch, cmd, dst, name) \
133 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
134 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
135 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
139 #define iris_pack_command(cmd, dst, name) \
140 _iris_pack_command(NULL, cmd, dst, name)
142 #define iris_pack_state(cmd, dst, name) \
143 for (struct cmd name = {}, \
144 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
145 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
148 #define iris_emit_cmd(batch, cmd, name) \
149 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
151 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
153 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
154 for (uint32_t i = 0; i < num_dwords; i++) \
155 dw[i] = (dwords0)[i] | (dwords1)[i]; \
156 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
159 #include "genxml/genX_pack.h"
160 #include "genxml/gen_macros.h"
161 #include "genxml/genX_bits.h"
163 #define MOCS_WB (2 << 1)
166 * Statically assert that PIPE_* enums match the hardware packets.
167 * (As long as they match, we don't need to translate them.)
169 UNUSED
static void pipe_asserts()
171 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
173 /* pipe_logicop happens to match the hardware. */
174 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
175 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
176 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
177 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
179 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
180 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
181 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
182 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
183 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
184 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
185 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
186 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
187 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
189 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
191 /* pipe_blend_func happens to match the hardware. */
192 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
193 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
212 /* pipe_blend_func happens to match the hardware. */
213 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
214 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
215 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
217 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
219 /* pipe_stencil_op happens to match the hardware. */
220 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
221 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
229 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
230 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
231 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
236 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
238 static const unsigned map
[] = {
239 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
240 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
241 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
242 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
243 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
244 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
245 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
246 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
247 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
248 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
249 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
250 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
251 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
252 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
253 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
256 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
260 translate_compare_func(enum pipe_compare_func pipe_func
)
262 static const unsigned map
[] = {
263 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
264 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
265 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
266 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
267 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
268 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
269 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
270 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
272 return map
[pipe_func
];
276 translate_shadow_func(enum pipe_compare_func pipe_func
)
278 /* Gallium specifies the result of shadow comparisons as:
280 * 1 if ref <op> texel,
285 * 0 if texel <op> ref,
288 * So we need to flip the operator and also negate.
290 static const unsigned map
[] = {
291 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
292 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
293 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
294 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
295 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
296 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
297 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
298 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
300 return map
[pipe_func
];
304 translate_cull_mode(unsigned pipe_face
)
306 static const unsigned map
[4] = {
307 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
308 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
309 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
310 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
312 return map
[pipe_face
];
316 translate_fill_mode(unsigned pipe_polymode
)
318 static const unsigned map
[4] = {
319 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
320 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
321 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
322 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
324 return map
[pipe_polymode
];
328 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
330 static const unsigned map
[] = {
331 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
332 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
333 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
335 return map
[pipe_mip
];
339 translate_wrap(unsigned pipe_wrap
)
341 static const unsigned map
[] = {
342 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
343 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
344 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
345 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
346 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
347 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
349 /* These are unsupported. */
350 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
351 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
353 return map
[pipe_wrap
];
356 static struct iris_address
357 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
359 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
360 * validation list at CSO creation time, instead of draw time.
362 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
365 static struct iris_address
366 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
368 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
369 * validation list at CSO creation time, instead of draw time.
371 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
375 * Allocate space for some indirect state.
377 * Return a pointer to the map (to fill it out) and a state ref (for
378 * referring to the state in GPU commands).
381 upload_state(struct u_upload_mgr
*uploader
,
382 struct iris_state_ref
*ref
,
387 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
392 * Stream out temporary/short-lived state.
394 * This allocates space, pins the BO, and includes the BO address in the
395 * returned offset (which works because all state lives in 32-bit memory
399 stream_state(struct iris_batch
*batch
,
400 struct u_upload_mgr
*uploader
,
401 struct pipe_resource
**out_res
,
404 uint32_t *out_offset
)
408 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
410 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
411 iris_use_pinned_bo(batch
, bo
, false);
413 *out_offset
+= iris_bo_offset_from_base_address(bo
);
419 * stream_state() + memcpy.
422 emit_state(struct iris_batch
*batch
,
423 struct u_upload_mgr
*uploader
,
424 struct pipe_resource
**out_res
,
431 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
434 memcpy(map
, data
, size
);
440 * Did field 'x' change between 'old_cso' and 'new_cso'?
442 * (If so, we may want to set some dirty flags.)
444 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
445 #define cso_changed_memcmp(x) \
446 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
449 * Upload the initial GPU state for a render context.
451 * This sets some invariant state that needs to be programmed a particular
452 * way, but we never actually change.
455 iris_init_render_context(struct iris_screen
*screen
,
456 struct iris_batch
*batch
,
457 struct iris_vtable
*vtbl
,
458 struct pipe_debug_callback
*dbg
)
460 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
462 /* XXX: PIPE_CONTROLs */
464 /* We program STATE_BASE_ADDRESS once at context initialization time.
465 * Each base address points at a 4GB memory zone, and never needs to
466 * change. See iris_bufmgr.h for a description of the memory zones.
468 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
470 // XXX: MOCS is stupid for this.
471 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
472 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
473 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
474 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
475 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
476 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
477 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
480 sba
.GeneralStateBaseAddressModifyEnable
= true;
481 sba
.SurfaceStateBaseAddressModifyEnable
= true;
482 sba
.DynamicStateBaseAddressModifyEnable
= true;
483 sba
.IndirectObjectBaseAddressModifyEnable
= true;
484 sba
.InstructionBaseAddressModifyEnable
= true;
485 sba
.GeneralStateBufferSizeModifyEnable
= true;
486 sba
.DynamicStateBufferSizeModifyEnable
= true;
487 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
488 sba
.IndirectObjectBufferSizeModifyEnable
= true;
489 sba
.InstructionBuffersizeModifyEnable
= true;
491 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
492 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
493 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
495 sba
.GeneralStateBufferSize
= 0xfffff;
496 sba
.IndirectObjectBufferSize
= 0xfffff;
497 sba
.InstructionBufferSize
= 0xfffff;
498 sba
.DynamicStateBufferSize
= 0xfffff;
501 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
502 * changing it dynamically. We set it to the maximum size here, and
503 * instead include the render target dimensions in the viewport, so
504 * viewport extents clipping takes care of pruning stray geometry.
506 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
507 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
508 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
511 /* Set the initial MSAA sample positions. */
512 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
513 GEN_SAMPLE_POS_1X(pat
._1xSample
);
514 GEN_SAMPLE_POS_2X(pat
._2xSample
);
515 GEN_SAMPLE_POS_4X(pat
._4xSample
);
516 GEN_SAMPLE_POS_8X(pat
._8xSample
);
517 GEN_SAMPLE_POS_16X(pat
._16xSample
);
520 /* Use the legacy AA line coverage computation. */
521 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
523 /* Disable chromakeying (it's for media) */
524 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
526 /* We want regular rendering, not special HiZ operations. */
527 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
529 /* No polygon stippling offsets are necessary. */
530 // XXX: may need to set an offset for origin-UL framebuffers
531 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
533 /* Set a static partitioning of the push constant area. */
534 // XXX: this may be a bad idea...could starve the push ringbuffers...
535 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
536 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
537 alloc
._3DCommandSubOpcode
= 18 + i
;
538 alloc
.ConstantBufferOffset
= 6 * i
;
539 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
544 struct iris_vertex_buffer_state
{
545 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
546 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
548 /** The resource to source vertex data from. */
549 struct pipe_resource
*resources
[33];
551 /** The number of bound vertex buffers. */
552 unsigned num_buffers
;
555 struct iris_depth_buffer_state
{
556 /* Depth/HiZ/Stencil related hardware packets. */
557 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
558 GENX(3DSTATE_STENCIL_BUFFER_length
) +
559 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
560 GENX(3DSTATE_CLEAR_PARAMS_length
)];
564 * Generation-specific context state (ice->state.genx->...).
566 * Most state can go in iris_context directly, but these encode hardware
567 * packets which vary by generation.
569 struct iris_genx_state
{
570 /** SF_CLIP_VIEWPORT */
571 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
573 struct iris_vertex_buffer_state vertex_buffers
;
574 struct iris_depth_buffer_state depth_buffer
;
576 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
577 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
580 // XXX: move this to iris_draw.c
582 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
587 * The pipe->set_blend_color() driver hook.
589 * This corresponds to our COLOR_CALC_STATE.
592 iris_set_blend_color(struct pipe_context
*ctx
,
593 const struct pipe_blend_color
*state
)
595 struct iris_context
*ice
= (struct iris_context
*) ctx
;
597 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
598 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
599 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
603 * Gallium CSO for blend state (see pipe_blend_state).
605 struct iris_blend_state
{
606 /** Partial 3DSTATE_PS_BLEND */
607 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
609 /** Partial BLEND_STATE */
610 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
611 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
613 bool alpha_to_coverage
; /* for shader key */
617 * The pipe->create_blend_state() driver hook.
619 * Translates a pipe_blend_state into iris_blend_state.
622 iris_create_blend_state(struct pipe_context
*ctx
,
623 const struct pipe_blend_state
*state
)
625 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
626 uint32_t *blend_state
= cso
->blend_state
;
628 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
630 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
631 /* pb.HasWriteableRT is filled in at draw time. */
632 /* pb.AlphaTestEnable is filled in at draw time. */
633 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
634 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
636 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
638 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
639 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
640 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
641 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
644 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
645 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
646 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
647 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
648 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
649 bs
.ColorDitherEnable
= state
->dither
;
650 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
653 blend_state
+= GENX(BLEND_STATE_length
);
655 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
656 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
657 be
.LogicOpEnable
= state
->logicop_enable
;
658 be
.LogicOpFunction
= state
->logicop_func
;
660 be
.PreBlendSourceOnlyClampEnable
= false;
661 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
662 be
.PreBlendColorClampEnable
= true;
663 be
.PostBlendColorClampEnable
= true;
665 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
667 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
668 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
669 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
670 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
671 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
672 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
674 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
675 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
676 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
677 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
679 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
686 * The pipe->bind_blend_state() driver hook.
688 * Bind a blending CSO and flag related dirty bits.
691 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
693 struct iris_context
*ice
= (struct iris_context
*) ctx
;
694 ice
->state
.cso_blend
= state
;
695 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
696 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
697 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
701 * Gallium CSO for depth, stencil, and alpha testing state.
703 struct iris_depth_stencil_alpha_state
{
704 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
705 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
707 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
708 struct pipe_alpha_state alpha
;
710 /** Outbound to resolve and cache set tracking. */
711 bool depth_writes_enabled
;
712 bool stencil_writes_enabled
;
716 * The pipe->create_depth_stencil_alpha_state() driver hook.
718 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
719 * testing state since we need pieces of it in a variety of places.
722 iris_create_zsa_state(struct pipe_context
*ctx
,
723 const struct pipe_depth_stencil_alpha_state
*state
)
725 struct iris_depth_stencil_alpha_state
*cso
=
726 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
728 bool two_sided_stencil
= state
->stencil
[1].enabled
;
730 cso
->alpha
= state
->alpha
;
731 cso
->depth_writes_enabled
= state
->depth
.writemask
;
732 cso
->stencil_writes_enabled
=
733 state
->stencil
[0].writemask
!= 0 ||
734 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
736 /* The state tracker needs to optimize away EQUAL writes for us. */
737 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
739 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
740 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
741 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
742 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
743 wmds
.StencilTestFunction
=
744 translate_compare_func(state
->stencil
[0].func
);
745 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
746 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
747 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
748 wmds
.BackfaceStencilTestFunction
=
749 translate_compare_func(state
->stencil
[1].func
);
750 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
751 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
752 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
753 wmds
.StencilBufferWriteEnable
=
754 state
->stencil
[0].writemask
!= 0 ||
755 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
756 wmds
.DepthTestEnable
= state
->depth
.enabled
;
757 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
758 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
759 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
760 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
761 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
762 /* wmds.[Backface]StencilReferenceValue are merged later */
769 * The pipe->bind_depth_stencil_alpha_state() driver hook.
771 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
774 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
776 struct iris_context
*ice
= (struct iris_context
*) ctx
;
777 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
778 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
781 if (cso_changed(alpha
.ref_value
))
782 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
784 if (cso_changed(alpha
.enabled
))
785 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
787 if (cso_changed(alpha
.func
))
788 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
790 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
791 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
794 ice
->state
.cso_zsa
= new_cso
;
795 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
796 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
797 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
801 * Gallium CSO for rasterizer state.
803 struct iris_rasterizer_state
{
804 uint32_t sf
[GENX(3DSTATE_SF_length
)];
805 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
806 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
807 uint32_t wm
[GENX(3DSTATE_WM_length
)];
808 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
810 bool clip_halfz
; /* for CC_VIEWPORT */
811 bool depth_clip_near
; /* for CC_VIEWPORT */
812 bool depth_clip_far
; /* for CC_VIEWPORT */
813 bool flatshade
; /* for shader state */
814 bool flatshade_first
; /* for stream output */
815 bool clamp_fragment_color
; /* for shader state */
816 bool light_twoside
; /* for shader state */
817 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
818 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
819 bool line_stipple_enable
;
820 bool poly_stipple_enable
;
822 bool force_persample_interp
;
823 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
824 uint16_t sprite_coord_enable
;
828 get_line_width(const struct pipe_rasterizer_state
*state
)
830 float line_width
= state
->line_width
;
832 /* From the OpenGL 4.4 spec:
834 * "The actual width of non-antialiased lines is determined by rounding
835 * the supplied width to the nearest integer, then clamping it to the
836 * implementation-dependent maximum non-antialiased line width."
838 if (!state
->multisample
&& !state
->line_smooth
)
839 line_width
= roundf(state
->line_width
);
841 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
842 /* For 1 pixel line thickness or less, the general anti-aliasing
843 * algorithm gives up, and a garbage line is generated. Setting a
844 * Line Width of 0.0 specifies the rasterization of the "thinnest"
845 * (one-pixel-wide), non-antialiased lines.
847 * Lines rendered with zero Line Width are rasterized using the
848 * "Grid Intersection Quantization" rules as specified by the
849 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
858 * The pipe->create_rasterizer_state() driver hook.
861 iris_create_rasterizer_state(struct pipe_context
*ctx
,
862 const struct pipe_rasterizer_state
*state
)
864 struct iris_rasterizer_state
*cso
=
865 malloc(sizeof(struct iris_rasterizer_state
));
868 point_quad_rasterization
-> SBE
?
873 force_persample_interp
- ?
876 offset_units_unscaled
- cap
not exposed
880 // XXX: it may make more sense just to store the pipe_rasterizer_state,
881 // we're copying a lot of booleans here. But we don't need all of them...
883 cso
->multisample
= state
->multisample
;
884 cso
->force_persample_interp
= state
->force_persample_interp
;
885 cso
->clip_halfz
= state
->clip_halfz
;
886 cso
->depth_clip_near
= state
->depth_clip_near
;
887 cso
->depth_clip_far
= state
->depth_clip_far
;
888 cso
->flatshade
= state
->flatshade
;
889 cso
->flatshade_first
= state
->flatshade_first
;
890 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
891 cso
->light_twoside
= state
->light_twoside
;
892 cso
->rasterizer_discard
= state
->rasterizer_discard
;
893 cso
->half_pixel_center
= state
->half_pixel_center
;
894 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
895 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
896 cso
->line_stipple_enable
= state
->line_stipple_enable
;
897 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
899 float line_width
= get_line_width(state
);
901 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
902 sf
.StatisticsEnable
= true;
903 sf
.ViewportTransformEnable
= true;
904 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
905 sf
.LineEndCapAntialiasingRegionWidth
=
906 state
->line_smooth
? _10pixels
: _05pixels
;
907 sf
.LastPixelEnable
= state
->line_last_pixel
;
908 sf
.LineWidth
= line_width
;
909 sf
.SmoothPointEnable
= state
->point_smooth
;
910 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
911 sf
.PointWidth
= state
->point_size
;
913 if (state
->flatshade_first
) {
914 sf
.TriangleFanProvokingVertexSelect
= 1;
916 sf
.TriangleStripListProvokingVertexSelect
= 2;
917 sf
.TriangleFanProvokingVertexSelect
= 2;
918 sf
.LineStripListProvokingVertexSelect
= 1;
922 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
923 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
924 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
925 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
926 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
927 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
928 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
929 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
930 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
931 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
932 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
933 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
934 rr
.SmoothPointEnable
= state
->point_smooth
;
935 rr
.AntialiasingEnable
= state
->line_smooth
;
936 rr
.ScissorRectangleEnable
= state
->scissor
;
937 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
938 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
939 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
942 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
943 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
944 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
946 cl
.StatisticsEnable
= true;
947 cl
.EarlyCullEnable
= true;
948 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
949 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
950 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
951 cl
.GuardbandClipTestEnable
= true;
952 cl
.ClipMode
= CLIPMODE_NORMAL
;
953 cl
.ClipEnable
= true;
954 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
955 cl
.MinimumPointWidth
= 0.125;
956 cl
.MaximumPointWidth
= 255.875;
958 if (state
->flatshade_first
) {
959 cl
.TriangleFanProvokingVertexSelect
= 1;
961 cl
.TriangleStripListProvokingVertexSelect
= 2;
962 cl
.TriangleFanProvokingVertexSelect
= 2;
963 cl
.LineStripListProvokingVertexSelect
= 1;
967 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
968 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
969 * filled in at draw time from the FS program.
971 wm
.LineAntialiasingRegionWidth
= _10pixels
;
972 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
973 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
974 wm
.StatisticsEnable
= true;
975 wm
.LineStippleEnable
= state
->line_stipple_enable
;
976 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
979 /* Remap from 0..255 back to 1..256 */
980 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
982 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
983 line
.LineStipplePattern
= state
->line_stipple_pattern
;
984 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
985 line
.LineStippleRepeatCount
= line_stipple_factor
;
992 * The pipe->bind_rasterizer_state() driver hook.
994 * Bind a rasterizer CSO and flag related dirty bits.
997 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
999 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1000 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1001 struct iris_rasterizer_state
*new_cso
= state
;
1004 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1005 if (cso_changed_memcmp(line_stipple
))
1006 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1008 if (cso_changed(half_pixel_center
))
1009 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1011 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1012 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1014 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
1015 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1017 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1018 cso_changed(clip_halfz
))
1019 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1021 if (cso_changed(sprite_coord_enable
) || cso_changed(light_twoside
))
1022 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1025 ice
->state
.cso_rast
= new_cso
;
1026 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1027 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1028 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1032 * Return true if the given wrap mode requires the border color to exist.
1034 * (We can skip uploading it if the sampler isn't going to use it.)
1037 wrap_mode_needs_border_color(unsigned wrap_mode
)
1039 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1043 * Gallium CSO for sampler state.
1045 struct iris_sampler_state
{
1046 // XXX: do we need this
1047 struct pipe_sampler_state base
;
1049 bool needs_border_color
;
1051 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1055 * The pipe->create_sampler_state() driver hook.
1057 * We fill out SAMPLER_STATE (except for the border color pointer), and
1058 * store that on the CPU. It doesn't make sense to upload it to a GPU
1059 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1060 * all bound sampler states to be in contiguous memor.
1063 iris_create_sampler_state(struct pipe_context
*ctx
,
1064 const struct pipe_sampler_state
*state
)
1066 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1071 memcpy(&cso
->base
, state
, sizeof(*state
));
1073 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1074 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1076 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1077 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1078 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1080 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1081 wrap_mode_needs_border_color(wrap_t
) ||
1082 wrap_mode_needs_border_color(wrap_r
);
1084 float min_lod
= state
->min_lod
;
1085 unsigned mag_img_filter
= state
->mag_img_filter
;
1087 // XXX: explain this code ported from ilo...I don't get it at all...
1088 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1089 state
->min_lod
> 0.0f
) {
1091 mag_img_filter
= state
->min_img_filter
;
1094 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1095 samp
.TCXAddressControlMode
= wrap_s
;
1096 samp
.TCYAddressControlMode
= wrap_t
;
1097 samp
.TCZAddressControlMode
= wrap_r
;
1098 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1099 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1100 samp
.MinModeFilter
= state
->min_img_filter
;
1101 samp
.MagModeFilter
= mag_img_filter
;
1102 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1103 samp
.MaximumAnisotropy
= RATIO21
;
1105 if (state
->max_anisotropy
>= 2) {
1106 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1107 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1108 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1111 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1112 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1114 samp
.MaximumAnisotropy
=
1115 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1118 /* Set address rounding bits if not using nearest filtering. */
1119 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1120 samp
.UAddressMinFilterRoundingEnable
= true;
1121 samp
.VAddressMinFilterRoundingEnable
= true;
1122 samp
.RAddressMinFilterRoundingEnable
= true;
1125 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1126 samp
.UAddressMagFilterRoundingEnable
= true;
1127 samp
.VAddressMagFilterRoundingEnable
= true;
1128 samp
.RAddressMagFilterRoundingEnable
= true;
1131 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1132 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1134 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1136 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1137 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1138 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1139 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1141 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1148 * The pipe->bind_sampler_states() driver hook.
1150 * Now that we know all the sampler states, we upload them all into a
1151 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1152 * We also fill out the border color state pointers at this point.
1154 * We could defer this work to draw time, but we assume that binding
1155 * will be less frequent than drawing.
1157 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1158 // XXX: with the complete set of shaders. If it makes multiple calls to
1159 // XXX: things one at a time, we could waste a lot of time assembling things.
1160 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1161 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1163 iris_bind_sampler_states(struct pipe_context
*ctx
,
1164 enum pipe_shader_type p_stage
,
1165 unsigned start
, unsigned count
,
1168 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1169 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1170 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1172 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1173 shs
->num_samplers
= MAX2(shs
->num_samplers
, start
+ count
);
1175 for (int i
= 0; i
< count
; i
++) {
1176 shs
->samplers
[start
+ i
] = states
[i
];
1179 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1180 * in the dynamic state memory zone, so we can point to it via the
1181 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1184 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1185 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1189 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1190 shs
->sampler_table
.offset
+=
1191 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1193 /* Make sure all land in the same BO */
1194 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1196 for (int i
= 0; i
< count
; i
++) {
1197 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1200 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1201 } else if (!state
->needs_border_color
) {
1202 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1204 ice
->state
.need_border_colors
= true;
1206 /* Stream out the border color and merge the pointer. */
1208 iris_upload_border_color(ice
, &state
->base
.border_color
);
1210 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1211 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1212 dyns
.BorderColorPointer
= offset
;
1215 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1216 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1219 map
+= GENX(SAMPLER_STATE_length
);
1222 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1226 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the HW's
1227 * "Shader Channel Select" enumerations (i.e. SCS_RED). The mappings are
1229 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
1232 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
1234 * which is simply adding 4 then modding by 8 (or anding with 7).
1236 static enum isl_channel_select
1237 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
1239 return (swizzle
+ 4) & 7;
1243 * The pipe->create_sampler_view() driver hook.
1245 static struct pipe_sampler_view
*
1246 iris_create_sampler_view(struct pipe_context
*ctx
,
1247 struct pipe_resource
*tex
,
1248 const struct pipe_sampler_view
*tmpl
)
1250 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1251 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1252 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1253 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1258 /* initialize base object */
1260 isv
->base
.context
= ctx
;
1261 isv
->base
.texture
= NULL
;
1262 pipe_reference_init(&isv
->base
.reference
, 1);
1263 pipe_resource_reference(&isv
->base
.texture
, tex
);
1265 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1266 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1270 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1271 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1273 /* XXX: do we need brw_get_texture_swizzle hacks here? */
1274 isv
->view
= (struct isl_view
) {
1275 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1276 .swizzle
= (struct isl_swizzle
) {
1277 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
1278 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
1279 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
1280 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
1282 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
1283 (itex
->surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
),
1286 /* Fill out SURFACE_STATE for this view. */
1287 if (tmpl
->target
!= PIPE_BUFFER
) {
1288 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1289 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1290 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1291 isv
->view
.array_len
=
1292 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1294 isl_surf_fill_state(&screen
->isl_dev
, map
,
1295 .surf
= &itex
->surf
, .view
= &isv
->view
,
1297 .address
= itex
->bo
->gtt_offset
);
1299 // .clear_color = clear_color,
1301 // XXX: what to do about isv->view? other drivers don't use it for bufs
1302 const struct isl_format_layout
*fmtl
=
1303 isl_format_get_layout(isv
->view
.format
);
1304 const unsigned cpp
= fmtl
->bpb
/ 8;
1306 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1307 .address
= itex
->bo
->gtt_offset
+
1309 // XXX: buffer_texture_range_size from i965?
1310 .size_B
= tmpl
->u
.buf
.size
,
1311 .format
= isv
->view
.format
,
1320 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1321 struct pipe_sampler_view
*state
)
1323 struct iris_sampler_view
*isv
= (void *) state
;
1324 pipe_resource_reference(&state
->texture
, NULL
);
1325 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1330 * The pipe->create_surface() driver hook.
1332 * In Gallium nomenclature, "surfaces" are a view of a resource that
1333 * can be bound as a render target or depth/stencil buffer.
1335 static struct pipe_surface
*
1336 iris_create_surface(struct pipe_context
*ctx
,
1337 struct pipe_resource
*tex
,
1338 const struct pipe_surface
*tmpl
)
1340 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1341 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1342 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1343 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1344 struct pipe_surface
*psurf
= &surf
->base
;
1345 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1350 pipe_reference_init(&psurf
->reference
, 1);
1351 pipe_resource_reference(&psurf
->texture
, tex
);
1352 psurf
->context
= ctx
;
1353 psurf
->format
= tmpl
->format
;
1354 psurf
->width
= tex
->width0
;
1355 psurf
->height
= tex
->height0
;
1356 psurf
->texture
= tex
;
1357 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1358 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1359 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1361 isl_surf_usage_flags_t usage
= 0;
1363 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1364 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1365 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1367 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1369 enum isl_format isl_format
=
1370 iris_isl_format_for_usage(devinfo
, psurf
->format
, usage
);
1372 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1373 !isl_format_supports_rendering(devinfo
, isl_format
)) {
1374 /* Framebuffer validation will reject this invalid case, but it
1375 * hasn't had the opportunity yet. In the meantime, we need to
1376 * avoid hitting ISL asserts about unsupported formats below.
1382 surf
->view
= (struct isl_view
) {
1383 .format
= isl_format
,
1384 .base_level
= tmpl
->u
.tex
.level
,
1386 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1387 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1388 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1392 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1393 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1394 ISL_SURF_USAGE_STENCIL_BIT
))
1398 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1399 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1403 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1404 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1406 isl_surf_fill_state(&screen
->isl_dev
, map
,
1407 .surf
= &res
->surf
, .view
= &surf
->view
,
1409 .address
= res
->bo
->gtt_offset
);
1411 // .clear_color = clear_color,
1417 * The pipe->set_sampler_views() driver hook.
1420 iris_set_sampler_views(struct pipe_context
*ctx
,
1421 enum pipe_shader_type p_stage
,
1422 unsigned start
, unsigned count
,
1423 struct pipe_sampler_view
**views
)
1425 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1426 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1427 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1430 for (i
= 0; i
< count
; i
++) {
1431 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1432 &shs
->textures
[i
], views
[i
]);
1434 for (; i
< shs
->num_textures
; i
++) {
1435 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1436 &shs
->textures
[i
], NULL
);
1439 shs
->num_textures
= count
;
1441 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1445 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1447 struct iris_surface
*surf
= (void *) p_surf
;
1448 pipe_resource_reference(&p_surf
->texture
, NULL
);
1449 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1453 // XXX: actually implement user clip planes
1455 iris_set_clip_state(struct pipe_context
*ctx
,
1456 const struct pipe_clip_state
*state
)
1461 * The pipe->set_polygon_stipple() driver hook.
1464 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1465 const struct pipe_poly_stipple
*state
)
1467 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1468 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1469 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1473 * The pipe->set_sample_mask() driver hook.
1476 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1478 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1480 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1481 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1483 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1484 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1488 * The pipe->set_scissor_states() driver hook.
1490 * This corresponds to our SCISSOR_RECT state structures. It's an
1491 * exact match, so we just store them, and memcpy them out later.
1494 iris_set_scissor_states(struct pipe_context
*ctx
,
1495 unsigned start_slot
,
1496 unsigned num_scissors
,
1497 const struct pipe_scissor_state
*states
)
1499 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1501 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1502 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1505 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1509 * The pipe->set_stencil_ref() driver hook.
1511 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1514 iris_set_stencil_ref(struct pipe_context
*ctx
,
1515 const struct pipe_stencil_ref
*state
)
1517 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1518 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1519 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1523 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1525 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1530 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1531 float m00
, float m11
, float m30
, float m31
,
1532 float *xmin
, float *xmax
,
1533 float *ymin
, float *ymax
)
1535 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1536 * Strips and Fans documentation:
1538 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1539 * fixed-point "guardband" range supported by the rasterization hardware"
1543 * "In almost all circumstances, if an object’s vertices are actually
1544 * modified by this clamping (i.e., had X or Y coordinates outside of
1545 * the guardband extent the rendered object will not match the intended
1546 * result. Therefore software should take steps to ensure that this does
1547 * not happen - e.g., by clipping objects such that they do not exceed
1548 * these limits after the Drawing Rectangle is applied."
1550 * I believe the fundamental restriction is that the rasterizer (in
1551 * the SF/WM stages) have a limit on the number of pixels that can be
1552 * rasterized. We need to ensure any coordinates beyond the rasterizer
1553 * limit are handled by the clipper. So effectively that limit becomes
1554 * the clipper's guardband size.
1556 * It goes on to say:
1558 * "In addition, in order to be correctly rendered, objects must have a
1559 * screenspace bounding box not exceeding 8K in the X or Y direction.
1560 * This additional restriction must also be comprehended by software,
1561 * i.e., enforced by use of clipping."
1563 * This makes no sense. Gen7+ hardware supports 16K render targets,
1564 * and you definitely need to be able to draw polygons that fill the
1565 * surface. Our assumption is that the rasterizer was limited to 8K
1566 * on Sandybridge, which only supports 8K surfaces, and it was actually
1567 * increased to 16K on Ivybridge and later.
1569 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1571 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1573 if (m00
!= 0 && m11
!= 0) {
1574 /* First, we compute the screen-space render area */
1575 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1576 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1577 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1578 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1580 /* We want the guardband to be centered on that */
1581 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1582 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1583 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1584 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1586 /* Now we need it in native device coordinates */
1587 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1588 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1589 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1590 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1592 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1593 * flipped upside-down. X should be fine though.
1595 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1596 *xmin
= ndc_gb_xmin
;
1597 *xmax
= ndc_gb_xmax
;
1598 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1599 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1601 /* The viewport scales to 0, so nothing will be rendered. */
1611 * The pipe->set_viewport_states() driver hook.
1613 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1614 * the guardband yet, as we need the framebuffer dimensions, but we can
1615 * at least fill out the rest.
1618 iris_set_viewport_states(struct pipe_context
*ctx
,
1619 unsigned start_slot
,
1621 const struct pipe_viewport_state
*states
)
1623 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1624 struct iris_genx_state
*genx
= ice
->state
.genx
;
1625 uint32_t *vp_map
= &genx
->sf_cl_vp
[start_slot
];
1627 for (unsigned i
= 0; i
< count
; i
++) {
1628 const struct pipe_viewport_state
*state
= &states
[i
];
1630 memcpy(&ice
->state
.viewports
[start_slot
+ i
], state
, sizeof(*state
));
1632 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1633 vp
.ViewportMatrixElementm00
= state
->scale
[0];
1634 vp
.ViewportMatrixElementm11
= state
->scale
[1];
1635 vp
.ViewportMatrixElementm22
= state
->scale
[2];
1636 vp
.ViewportMatrixElementm30
= state
->translate
[0];
1637 vp
.ViewportMatrixElementm31
= state
->translate
[1];
1638 vp
.ViewportMatrixElementm32
= state
->translate
[2];
1639 /* XXX: in i965 this is computed based on the drawbuffer size,
1640 * but we don't have that here...
1642 vp
.XMinClipGuardband
= -1.0;
1643 vp
.XMaxClipGuardband
= 1.0;
1644 vp
.YMinClipGuardband
= -1.0;
1645 vp
.YMaxClipGuardband
= 1.0;
1646 vp
.XMinViewPort
= viewport_extent(state
, 0, -1.0f
);
1647 vp
.XMaxViewPort
= viewport_extent(state
, 0, 1.0f
) - 1;
1648 vp
.YMinViewPort
= viewport_extent(state
, 1, -1.0f
);
1649 vp
.YMaxViewPort
= viewport_extent(state
, 1, 1.0f
) - 1;
1652 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1655 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1657 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1658 !ice
->state
.cso_rast
->depth_clip_far
))
1659 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1663 * The pipe->set_framebuffer_state() driver hook.
1665 * Sets the current draw FBO, including color render targets, depth,
1666 * and stencil buffers.
1669 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1670 const struct pipe_framebuffer_state
*state
)
1672 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1673 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1674 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1675 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1676 struct iris_resource
*zres
;
1677 struct iris_resource
*stencil_res
;
1679 unsigned samples
= util_framebuffer_get_num_samples(state
);
1681 if (cso
->samples
!= samples
) {
1682 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1685 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1686 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1689 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
1690 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1693 util_copy_framebuffer_state(cso
, state
);
1694 cso
->samples
= samples
;
1696 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
1698 struct isl_view view
= {
1701 .base_array_layer
= 0,
1703 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1706 struct isl_depth_stencil_hiz_emit_info info
= {
1712 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
1715 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1716 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1718 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1721 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1723 info
.depth_surf
= &zres
->surf
;
1724 info
.depth_address
= zres
->bo
->gtt_offset
;
1725 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1727 view
.format
= zres
->surf
.format
;
1731 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1732 info
.stencil_surf
= &stencil_res
->surf
;
1733 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
1735 view
.format
= stencil_res
->surf
.format
;
1739 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1741 /* Make a null surface for unbound buffers */
1742 void *null_surf_map
=
1743 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
1744 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1745 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(cso
->width
, cso
->height
, cso
->layers
? cso
->layers
: 1));
1747 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1749 /* Render target change */
1750 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
1752 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
1756 * The pipe->set_constant_buffer() driver hook.
1758 * This uploads any constant data in user buffers, and references
1759 * any UBO resources containing constant data.
1762 iris_set_constant_buffer(struct pipe_context
*ctx
,
1763 enum pipe_shader_type p_stage
, unsigned index
,
1764 const struct pipe_constant_buffer
*input
)
1766 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1767 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1768 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1769 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1770 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
1772 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1773 if (input
->user_buffer
) {
1774 u_upload_data(ctx
->const_uploader
, 0, input
->buffer_size
, 32,
1775 input
->user_buffer
, &cbuf
->data
.offset
,
1778 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
1781 // XXX: these are not retained forever, use a separate uploader?
1783 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
1784 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1785 if (!unlikely(map
)) {
1786 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1790 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
1791 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
1792 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
1794 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1795 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
1796 .size_B
= input
->buffer_size
,
1797 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
1801 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
1802 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
1805 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
1806 // XXX: maybe not necessary all the time...?
1807 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
1808 // XXX: pull model we may need actual new bindings...
1809 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1813 * The pipe->set_shader_buffers() driver hook.
1815 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
1816 * SURFACE_STATE here, as the buffer offset may change each time.
1819 iris_set_shader_buffers(struct pipe_context
*ctx
,
1820 enum pipe_shader_type p_stage
,
1821 unsigned start_slot
, unsigned count
,
1822 const struct pipe_shader_buffer
*buffers
)
1824 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1825 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1826 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1827 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1829 for (unsigned i
= 0; i
< count
; i
++) {
1830 if (buffers
&& buffers
[i
].buffer
) {
1831 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
1832 struct iris_resource
*res
= (void *) buffer
->buffer
;
1833 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
1835 // XXX: these are not retained forever, use a separate uploader?
1837 upload_state(ice
->state
.surface_uploader
,
1838 &shs
->ssbo_surface_state
[start_slot
+ i
],
1839 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1840 if (!unlikely(map
)) {
1841 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1845 struct iris_bo
*surf_state_bo
=
1846 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
1847 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
1848 iris_bo_offset_from_base_address(surf_state_bo
);
1850 isl_buffer_fill_state(&screen
->isl_dev
, map
,
1852 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
1853 .size_B
= buffer
->buffer_size
,
1854 .format
= ISL_FORMAT_RAW
,
1858 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
1859 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
1864 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1868 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1874 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1876 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1877 pipe_resource_reference(&cso
->resources
[i
], NULL
);
1881 * The pipe->set_vertex_buffers() driver hook.
1883 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
1886 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1887 unsigned start_slot
, unsigned count
,
1888 const struct pipe_vertex_buffer
*buffers
)
1890 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1891 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
1893 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
1898 cso
->num_buffers
= count
;
1900 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1901 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
1904 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1907 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1908 vb
.VertexBufferIndex
= start_slot
;
1909 vb
.NullVertexBuffer
= true;
1910 vb
.AddressModifyEnable
= true;
1914 for (unsigned i
= 0; i
< count
; i
++) {
1915 assert(!buffers
[i
].is_user_buffer
);
1917 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
1918 struct iris_resource
*res
= (void *) cso
->resources
[i
];
1920 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1921 vb
.VertexBufferIndex
= start_slot
+ i
;
1923 vb
.AddressModifyEnable
= true;
1924 vb
.BufferPitch
= buffers
[i
].stride
;
1925 vb
.BufferSize
= res
->bo
->size
;
1926 vb
.BufferStartingAddress
=
1927 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1930 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1933 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1937 * Gallium CSO for vertex elements.
1939 struct iris_vertex_element_state
{
1940 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1941 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
1946 * The pipe->create_vertex_elements() driver hook.
1948 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
1949 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
1952 iris_create_vertex_elements(struct pipe_context
*ctx
,
1954 const struct pipe_vertex_element
*state
)
1956 struct iris_vertex_element_state
*cso
=
1957 malloc(sizeof(struct iris_vertex_element_state
));
1962 * - create edge flag one
1964 * - if those are necessary, use count + 1/2/3... OR in the length
1966 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1968 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
1971 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1972 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
1975 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1977 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
1978 ve
.Component0Control
= VFCOMP_STORE_0
;
1979 ve
.Component1Control
= VFCOMP_STORE_0
;
1980 ve
.Component2Control
= VFCOMP_STORE_0
;
1981 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
1984 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
1988 for (int i
= 0; i
< count
; i
++) {
1989 enum isl_format isl_format
=
1990 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1991 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1992 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1994 switch (isl_format_get_num_channels(isl_format
)) {
1995 case 0: comp
[0] = VFCOMP_STORE_0
;
1996 case 1: comp
[1] = VFCOMP_STORE_0
;
1997 case 2: comp
[2] = VFCOMP_STORE_0
;
1999 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
2000 : VFCOMP_STORE_1_FP
;
2003 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2004 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2006 ve
.SourceElementOffset
= state
[i
].src_offset
;
2007 ve
.SourceElementFormat
= isl_format
;
2008 ve
.Component0Control
= comp
[0];
2009 ve
.Component1Control
= comp
[1];
2010 ve
.Component2Control
= comp
[2];
2011 ve
.Component3Control
= comp
[3];
2014 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2015 vi
.VertexElementIndex
= i
;
2016 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2017 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2020 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2021 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2028 * The pipe->bind_vertex_elements_state() driver hook.
2031 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2033 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2034 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2035 struct iris_vertex_element_state
*new_cso
= state
;
2037 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2038 * we need to re-emit it to ensure we're overriding the right one.
2040 if (new_cso
&& cso_changed(count
))
2041 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2043 ice
->state
.cso_vertex_elements
= state
;
2044 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2048 iris_create_compute_state(struct pipe_context
*ctx
,
2049 const struct pipe_compute_state
*state
)
2051 // XXX: actually do something
2056 * Gallium CSO for stream output (transform feedback) targets.
2058 struct iris_stream_output_target
{
2059 struct pipe_stream_output_target base
;
2061 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2063 /** Storage holding the offset where we're writing in the buffer */
2064 struct iris_state_ref offset
;
2068 * The pipe->create_stream_output_target() driver hook.
2070 * "Target" here refers to a destination buffer. We translate this into
2071 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2072 * know which buffer this represents, or whether we ought to zero the
2073 * write-offsets, or append. Those are handled in the set() hook.
2075 static struct pipe_stream_output_target
*
2076 iris_create_stream_output_target(struct pipe_context
*ctx
,
2077 struct pipe_resource
*res
,
2078 unsigned buffer_offset
,
2079 unsigned buffer_size
)
2081 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2085 pipe_reference_init(&cso
->base
.reference
, 1);
2086 pipe_resource_reference(&cso
->base
.buffer
, res
);
2087 cso
->base
.buffer_offset
= buffer_offset
;
2088 cso
->base
.buffer_size
= buffer_size
;
2089 cso
->base
.context
= ctx
;
2091 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4, 4);
2093 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2094 sob
.SurfaceBaseAddress
=
2095 rw_bo(NULL
, iris_resource_bo(res
)->gtt_offset
+ buffer_offset
);
2096 sob
.SOBufferEnable
= true;
2097 sob
.StreamOffsetWriteEnable
= true;
2098 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2099 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2101 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2102 sob
.StreamOutputBufferOffsetAddress
=
2103 rw_bo(NULL
, iris_resource_bo(cso
->offset
.res
)->gtt_offset
+ cso
->offset
.offset
);
2105 /* .SOBufferIndex and .StreamOffset are filled in later */
2112 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2113 struct pipe_stream_output_target
*state
)
2115 struct iris_stream_output_target
*cso
= (void *) state
;
2117 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2118 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2124 * The pipe->set_stream_output_targets() driver hook.
2126 * At this point, we know which targets are bound to a particular index,
2127 * and also whether we want to append or start over. We can finish the
2128 * 3DSTATE_SO_BUFFER packets we started earlier.
2131 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2132 unsigned num_targets
,
2133 struct pipe_stream_output_target
**targets
,
2134 const unsigned *offsets
)
2136 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2137 struct iris_genx_state
*genx
= ice
->state
.genx
;
2138 uint32_t *so_buffers
= genx
->so_buffers
;
2140 const bool active
= num_targets
> 0;
2141 if (ice
->state
.streamout_active
!= active
) {
2142 ice
->state
.streamout_active
= active
;
2143 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2146 for (int i
= 0; i
< 4; i
++) {
2147 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2148 i
< num_targets
? targets
[i
] : NULL
);
2151 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2155 for (unsigned i
= 0; i
< 4; i
++,
2156 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2158 if (i
>= num_targets
|| !targets
[i
]) {
2159 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2160 sob
.SOBufferIndex
= i
;
2164 /* Note that offsets[i] will either be 0, causing us to zero
2165 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2166 * "continue appending at the existing offset."
2168 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2170 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2171 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2172 dyns
.SOBufferIndex
= i
;
2173 dyns
.StreamOffset
= offsets
[i
];
2176 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2177 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2178 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2182 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2186 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2187 * 3DSTATE_STREAMOUT packets.
2189 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2190 * hardware to record. We can create it entirely based on the shader, with
2191 * no dynamic state dependencies.
2193 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2194 * state-based settings. We capture the shader-related ones here, and merge
2195 * the rest in at draw time.
2198 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2199 const struct brw_vue_map
*vue_map
)
2201 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2202 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2203 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2204 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2206 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2208 memset(so_decl
, 0, sizeof(so_decl
));
2210 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2211 * command feels strange -- each dword pair contains a SO_DECL per stream.
2213 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2214 const struct pipe_stream_output
*output
= &info
->output
[i
];
2215 const int buffer
= output
->output_buffer
;
2216 const int varying
= output
->register_index
;
2217 const unsigned stream_id
= output
->stream
;
2218 assert(stream_id
< MAX_VERTEX_STREAMS
);
2220 buffer_mask
[stream_id
] |= 1 << buffer
;
2222 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2224 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2225 * array. Instead, it simply increments DstOffset for the following
2226 * input by the number of components that should be skipped.
2228 * Our hardware is unusual in that it requires us to program SO_DECLs
2229 * for fake "hole" components, rather than simply taking the offset
2230 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2231 * program as many size = 4 holes as we can, then a final hole to
2232 * accommodate the final 1, 2, or 3 remaining.
2234 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2236 while (skip_components
> 0) {
2237 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2239 .OutputBufferSlot
= output
->output_buffer
,
2240 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2242 skip_components
-= 4;
2245 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2247 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2248 .OutputBufferSlot
= output
->output_buffer
,
2249 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2251 ((1 << output
->num_components
) - 1) << output
->start_component
,
2254 if (decls
[stream_id
] > max_decls
)
2255 max_decls
= decls
[stream_id
];
2258 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2259 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2260 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2262 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2263 int urb_entry_read_offset
= 0;
2264 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2265 urb_entry_read_offset
;
2267 /* We always read the whole vertex. This could be reduced at some
2268 * point by reading less and offsetting the register index in the
2271 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2272 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2273 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2274 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2275 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2276 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2277 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2278 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2280 /* Set buffer pitches; 0 means unbound. */
2281 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2282 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2283 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2284 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2287 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2288 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2289 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2290 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2291 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2292 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2293 list
.NumEntries0
= decls
[0];
2294 list
.NumEntries1
= decls
[1];
2295 list
.NumEntries2
= decls
[2];
2296 list
.NumEntries3
= decls
[3];
2299 for (int i
= 0; i
< max_decls
; i
++) {
2300 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2301 entry
.Stream0Decl
= so_decl
[0][i
];
2302 entry
.Stream1Decl
= so_decl
[1][i
];
2303 entry
.Stream2Decl
= so_decl
[2][i
];
2304 entry
.Stream3Decl
= so_decl
[3][i
];
2312 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2313 const struct brw_vue_map
*last_vue_map
,
2314 bool two_sided_color
,
2315 unsigned *out_offset
,
2316 unsigned *out_length
)
2318 /* The compiler computes the first URB slot without considering COL/BFC
2319 * swizzling (because it doesn't know whether it's enabled), so we need
2320 * to do that here too. This may result in a smaller offset, which
2323 const unsigned first_slot
=
2324 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2326 /* This becomes the URB read offset (counted in pairs of slots). */
2327 assert(first_slot
% 2 == 0);
2328 *out_offset
= first_slot
/ 2;
2330 /* We need to adjust the inputs read to account for front/back color
2331 * swizzling, as it can make the URB length longer.
2333 for (int c
= 0; c
<= 1; c
++) {
2334 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2335 /* If two sided color is enabled, the fragment shader's gl_Color
2336 * (COL0) input comes from either the gl_FrontColor (COL0) or
2337 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2339 if (two_sided_color
)
2340 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2342 /* If front color isn't written, we opt to give them back color
2343 * instead of an undefined value. Switch from COL to BFC.
2345 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2346 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2347 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2352 /* Compute the minimum URB Read Length necessary for the FS inputs.
2354 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2355 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2357 * "This field should be set to the minimum length required to read the
2358 * maximum source attribute. The maximum source attribute is indicated
2359 * by the maximum value of the enabled Attribute # Source Attribute if
2360 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2361 * enable is not set.
2362 * read_length = ceiling((max_source_attr + 1) / 2)
2364 * [errata] Corruption/Hang possible if length programmed larger than
2367 * Similar text exists for Ivy Bridge.
2369 * We find the last URB slot that's actually read by the FS.
2371 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2372 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2373 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2376 /* The URB read length is the difference of the two, counted in pairs. */
2377 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2381 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2382 const struct iris_context
*ice
,
2383 unsigned urb_read_offset
,
2384 unsigned sprite_coord_enables
)
2386 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2387 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2388 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2389 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2390 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2392 /* XXX: this should be generated when putting programs in place */
2394 // XXX: raster->sprite_coord_enable
2396 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2397 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2398 if (input_index
< 0 || input_index
>= 16)
2401 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2402 &attr_overrides
[input_index
];
2404 /* Viewport and Layer are stored in the VUE header. We need to override
2405 * them to zero if earlier stages didn't write them, as GL requires that
2406 * they read back as zero when not explicitly set.
2409 case VARYING_SLOT_VIEWPORT
:
2410 case VARYING_SLOT_LAYER
:
2411 attr
->ComponentOverrideX
= true;
2412 attr
->ComponentOverrideW
= true;
2413 attr
->ConstantSource
= CONST_0000
;
2415 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2416 attr
->ComponentOverrideY
= true;
2417 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2418 attr
->ComponentOverrideZ
= true;
2421 case VARYING_SLOT_PRIMITIVE_ID
:
2422 attr
->ComponentOverrideX
= true;
2423 attr
->ComponentOverrideY
= true;
2424 attr
->ComponentOverrideZ
= true;
2425 attr
->ComponentOverrideW
= true;
2426 attr
->ConstantSource
= PRIM_ID
;
2433 if (sprite_coord_enables
& (1 << input_index
))
2436 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2438 /* If there was only a back color written but not front, use back
2439 * as the color instead of undefined.
2441 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2442 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2443 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2444 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2446 /* Not written by the previous stage - undefined. */
2448 attr
->ComponentOverrideX
= true;
2449 attr
->ComponentOverrideY
= true;
2450 attr
->ComponentOverrideZ
= true;
2451 attr
->ComponentOverrideW
= true;
2452 attr
->ConstantSource
= CONST_0001_FLOAT
;
2456 /* Compute the location of the attribute relative to the read offset,
2457 * which is counted in 256-bit increments (two 128-bit VUE slots).
2459 const int source_attr
= slot
- 2 * urb_read_offset
;
2460 assert(source_attr
>= 0 && source_attr
<= 32);
2461 attr
->SourceAttribute
= source_attr
;
2463 /* If we are doing two-sided color, and the VUE slot following this one
2464 * represents a back-facing color, then we need to instruct the SF unit
2465 * to do back-facing swizzling.
2467 if (cso_rast
->light_twoside
&&
2468 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2469 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2470 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2471 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2472 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2475 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2476 for (int i
= 0; i
< 16; i
++)
2477 sbes
.Attribute
[i
] = attr_overrides
[i
];
2482 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2483 const struct iris_rasterizer_state
*cso
)
2485 unsigned overrides
= 0;
2487 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2488 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2490 for (int i
= 0; i
< 8; i
++) {
2491 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2492 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2493 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2500 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2502 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2503 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2504 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2505 const struct shader_info
*fs_info
=
2506 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2508 unsigned urb_read_offset
, urb_read_length
;
2509 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2510 ice
->shaders
.last_vue_map
,
2511 cso_rast
->light_twoside
,
2512 &urb_read_offset
, &urb_read_length
);
2514 unsigned sprite_coord_overrides
=
2515 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2517 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2518 sbe
.AttributeSwizzleEnable
= true;
2519 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2520 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2521 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2522 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2523 sbe
.ForceVertexURBEntryReadOffset
= true;
2524 sbe
.ForceVertexURBEntryReadLength
= true;
2525 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2526 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2528 for (int i
= 0; i
< 32; i
++) {
2529 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2533 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2537 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
2539 // XXX: do something
2542 /* ------------------------------------------------------------------- */
2545 * Set sampler-related program key fields based on the current state.
2548 iris_populate_sampler_key(const struct iris_context
*ice
,
2549 struct brw_sampler_prog_key_data
*key
)
2551 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
2552 key
->swizzles
[i
] = 0x688; /* XYZW */
2557 * Populate VS program key fields based on the current state.
2560 iris_populate_vs_key(const struct iris_context
*ice
,
2561 struct brw_vs_prog_key
*key
)
2563 iris_populate_sampler_key(ice
, &key
->tex
);
2567 * Populate TCS program key fields based on the current state.
2570 iris_populate_tcs_key(const struct iris_context
*ice
,
2571 struct brw_tcs_prog_key
*key
)
2573 iris_populate_sampler_key(ice
, &key
->tex
);
2577 * Populate TES program key fields based on the current state.
2580 iris_populate_tes_key(const struct iris_context
*ice
,
2581 struct brw_tes_prog_key
*key
)
2583 iris_populate_sampler_key(ice
, &key
->tex
);
2587 * Populate GS program key fields based on the current state.
2590 iris_populate_gs_key(const struct iris_context
*ice
,
2591 struct brw_gs_prog_key
*key
)
2593 iris_populate_sampler_key(ice
, &key
->tex
);
2597 * Populate FS program key fields based on the current state.
2600 iris_populate_fs_key(const struct iris_context
*ice
,
2601 struct brw_wm_prog_key
*key
)
2603 iris_populate_sampler_key(ice
, &key
->tex
);
2605 /* XXX: dirty flags? */
2606 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
2607 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
2608 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
2609 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
2611 key
->nr_color_regions
= fb
->nr_cbufs
;
2613 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
2615 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
2616 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
2618 /* XXX: only bother if COL0/1 are read */
2619 key
->flat_shade
= rast
->flatshade
;
2621 key
->persample_interp
= rast
->force_persample_interp
;
2622 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
2624 key
->coherent_fb_fetch
= true;
2626 // XXX: uint64_t input_slots_valid; - for >16 inputs
2628 // XXX: key->force_dual_color_blend for unigine
2629 // XXX: respect hint for high_quality_derivatives:1;
2633 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
2634 pkt
.SamplerCount
= \
2635 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
2636 pkt
.PerThreadScratchSpace
= prog_data
->total_scratch
== 0 ? 0 : \
2637 ffs(stage_state
->per_thread_scratch
) - 11; \
2642 KSP(const struct iris_compiled_shader
*shader
)
2644 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
2645 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
2648 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2649 pkt.KernelStartPointer = KSP(shader); \
2650 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
2651 pkt.FloatingPointMode = prog_data->use_alt_mode; \
2653 pkt.DispatchGRFStartRegisterForURBData = \
2654 prog_data->dispatch_grf_start_reg; \
2655 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2656 pkt.prefix##URBEntryReadOffset = 0; \
2658 pkt.StatisticsEnable = true; \
2662 * Encode most of 3DSTATE_VS based on the compiled shader.
2665 iris_store_vs_state(const struct gen_device_info
*devinfo
,
2666 struct iris_compiled_shader
*shader
)
2668 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2669 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2671 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
2672 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
2673 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
2674 vs
.SIMD8DispatchEnable
= true;
2675 vs
.UserClipDistanceCullTestEnableBitmask
=
2676 vue_prog_data
->cull_distance_mask
;
2681 * Encode most of 3DSTATE_HS based on the compiled shader.
2684 iris_store_tcs_state(const struct gen_device_info
*devinfo
,
2685 struct iris_compiled_shader
*shader
)
2687 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2688 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2689 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
2691 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
2692 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
2694 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
2695 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
2696 hs
.IncludeVertexHandles
= true;
2701 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
2704 iris_store_tes_state(const struct gen_device_info
*devinfo
,
2705 struct iris_compiled_shader
*shader
)
2707 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2708 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2709 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
2711 uint32_t *te_state
= (void *) shader
->derived_data
;
2712 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
2714 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
2715 te
.Partitioning
= tes_prog_data
->partitioning
;
2716 te
.OutputTopology
= tes_prog_data
->output_topology
;
2717 te
.TEDomain
= tes_prog_data
->domain
;
2719 te
.MaximumTessellationFactorOdd
= 63.0;
2720 te
.MaximumTessellationFactorNotOdd
= 64.0;
2723 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
2724 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
2726 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
2727 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
2728 ds
.ComputeWCoordinateEnable
=
2729 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
2731 ds
.UserClipDistanceCullTestEnableBitmask
=
2732 vue_prog_data
->cull_distance_mask
;
2738 * Encode most of 3DSTATE_GS based on the compiled shader.
2741 iris_store_gs_state(const struct gen_device_info
*devinfo
,
2742 struct iris_compiled_shader
*shader
)
2744 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2745 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
2746 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
2748 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
2749 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
2751 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
2752 gs
.OutputTopology
= gs_prog_data
->output_topology
;
2753 gs
.ControlDataHeaderSize
=
2754 gs_prog_data
->control_data_header_size_hwords
;
2755 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
2756 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
2757 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
2758 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
2759 gs
.ReorderMode
= TRAILING
;
2760 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
2761 gs
.MaximumNumberofThreads
=
2762 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
2763 : (devinfo
->max_gs_threads
- 1);
2765 if (gs_prog_data
->static_vertex_count
!= -1) {
2766 gs
.StaticOutput
= true;
2767 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
2769 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
2771 gs
.UserClipDistanceCullTestEnableBitmask
=
2772 vue_prog_data
->cull_distance_mask
;
2774 const int urb_entry_write_offset
= 1;
2775 const uint32_t urb_entry_output_length
=
2776 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
2777 urb_entry_write_offset
;
2779 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
2780 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
2785 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
2788 iris_store_fs_state(const struct gen_device_info
*devinfo
,
2789 struct iris_compiled_shader
*shader
)
2791 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
2792 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
2794 uint32_t *ps_state
= (void *) shader
->derived_data
;
2795 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
2797 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
2798 ps
.VectorMaskEnable
= true;
2799 //ps.SamplerCount = ...
2800 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
2801 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
2802 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
2804 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
2805 prog_data
->ubo_ranges
[0].length
> 0;
2807 /* From the documentation for this packet:
2808 * "If the PS kernel does not need the Position XY Offsets to
2809 * compute a Position Value, then this field should be programmed
2810 * to POSOFFSET_NONE."
2812 * "SW Recommendation: If the PS kernel needs the Position Offsets
2813 * to compute a Position XY value, this field should match Position
2814 * ZW Interpolation Mode to ensure a consistent position.xyzw
2817 * We only require XY sample offsets. So, this recommendation doesn't
2818 * look useful at the moment. We might need this in future.
2820 ps
.PositionXYOffsetSelect
=
2821 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2822 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
2823 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
2824 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
2826 // XXX: Disable SIMD32 with 16x MSAA
2828 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2829 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2830 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2831 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2832 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2833 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2835 ps
.KernelStartPointer0
=
2836 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2837 ps
.KernelStartPointer1
=
2838 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2839 ps
.KernelStartPointer2
=
2840 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2843 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
2844 psx
.PixelShaderValid
= true;
2845 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2846 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
2847 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
2848 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2849 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2850 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2852 if (wm_prog_data
->uses_sample_mask
) {
2853 /* TODO: conservative rasterization */
2854 if (wm_prog_data
->post_depth_coverage
)
2855 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2857 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
2860 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2861 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2862 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2869 * Compute the size of the derived data (shader command packets).
2871 * This must match the data written by the iris_store_xs_state() functions.
2874 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
2876 assert(cache_id
<= IRIS_CACHE_BLORP
);
2878 static const unsigned dwords
[] = {
2879 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
2880 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
2881 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
2882 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
2884 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
2885 [IRIS_CACHE_CS
] = 0,
2886 [IRIS_CACHE_BLORP
] = 0,
2889 return sizeof(uint32_t) * dwords
[cache_id
];
2893 * Create any state packets corresponding to the given shader stage
2894 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
2895 * This means that we can look up a program in the in-memory cache and
2896 * get most of the state packet without having to reconstruct it.
2899 iris_store_derived_program_state(const struct gen_device_info
*devinfo
,
2900 enum iris_program_cache_id cache_id
,
2901 struct iris_compiled_shader
*shader
)
2905 iris_store_vs_state(devinfo
, shader
);
2907 case IRIS_CACHE_TCS
:
2908 iris_store_tcs_state(devinfo
, shader
);
2910 case IRIS_CACHE_TES
:
2911 iris_store_tes_state(devinfo
, shader
);
2914 iris_store_gs_state(devinfo
, shader
);
2917 iris_store_fs_state(devinfo
, shader
);
2920 case IRIS_CACHE_BLORP
:
2927 /* ------------------------------------------------------------------- */
2930 * Configure the URB.
2932 * XXX: write a real comment.
2935 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2937 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2938 const unsigned push_size_kB
= 32;
2939 unsigned entries
[4];
2943 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2944 if (!ice
->shaders
.prog
[i
]) {
2947 struct brw_vue_prog_data
*vue_prog_data
=
2948 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2949 size
[i
] = vue_prog_data
->urb_entry_size
;
2951 assert(size
[i
] != 0);
2954 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2955 1024 * ice
->shaders
.urb_size
,
2956 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2957 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2958 size
, entries
, start
);
2960 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2961 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2962 urb
._3DCommandSubOpcode
+= i
;
2963 urb
.VSURBStartingAddress
= start
[i
];
2964 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2965 urb
.VSNumberofURBEntries
= entries
[i
];
2970 static const uint32_t push_constant_opcodes
[] = {
2971 [MESA_SHADER_VERTEX
] = 21,
2972 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2973 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2974 [MESA_SHADER_GEOMETRY
] = 22,
2975 [MESA_SHADER_FRAGMENT
] = 23,
2976 [MESA_SHADER_COMPUTE
] = 0,
2980 * Add a surface to the validation list, as well as the buffer containing
2981 * the corresponding SURFACE_STATE.
2983 * Returns the binding table entry (offset to SURFACE_STATE).
2986 use_surface(struct iris_batch
*batch
,
2987 struct pipe_surface
*p_surf
,
2990 struct iris_surface
*surf
= (void *) p_surf
;
2992 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
2993 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
2995 return surf
->surface_state
.offset
;
2999 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3001 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->base
.texture
), false);
3002 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3004 return isv
->surface_state
.offset
;
3008 use_const_buffer(struct iris_batch
*batch
, struct iris_const_buffer
*cbuf
)
3010 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3011 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3013 return cbuf
->surface_state
.offset
;
3017 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3019 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3021 iris_use_pinned_bo(batch
, state_bo
, false);
3023 return ice
->state
.unbound_tex
.offset
;
3027 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3029 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3031 iris_use_pinned_bo(batch
, state_bo
, false);
3033 return ice
->state
.null_fb
.offset
;
3037 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3038 struct iris_shader_state
*shs
, int i
)
3041 return use_null_surface(batch
, ice
);
3043 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3045 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3046 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3048 return surf_state
->offset
;
3052 * Populate the binding table for a given shader stage.
3054 * This fills out the table of pointers to surfaces required by the shader,
3055 * and also adds those buffers to the validation list so the kernel can make
3056 * resident before running our batch.
3059 iris_populate_binding_table(struct iris_context
*ice
,
3060 struct iris_batch
*batch
,
3061 gl_shader_stage stage
)
3063 const struct iris_binder
*binder
= &batch
->binder
;
3064 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3068 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3069 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3071 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3072 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3075 if (stage
== MESA_SHADER_FRAGMENT
) {
3076 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3077 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3078 if (cso_fb
->nr_cbufs
) {
3079 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3080 if (cso_fb
->cbufs
[i
])
3081 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
3083 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3086 bt_map
[s
++] = use_null_fb_surface(batch
, ice
);
3090 //assert(prog_data->binding_table.texture_start ==
3091 //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
3093 for (int i
= 0; i
< shs
->num_textures
; i
++) {
3094 struct iris_sampler_view
*view
= shs
->textures
[i
];
3095 bt_map
[s
++] = view
? use_sampler_view(batch
, view
)
3096 : use_null_surface(batch
, ice
);
3099 for (int i
= 0; i
< 1 + info
->num_ubos
; i
++) {
3100 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[i
];
3101 if (!cbuf
->surface_state
.res
)
3104 bt_map
[s
++] = use_const_buffer(batch
, cbuf
);
3107 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3108 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3109 * in st_atom_storagebuf.c so it'll compact them into one range, with
3110 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3112 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3113 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3114 bt_map
[s
++] = use_ssbo(batch
, ice
, shs
, i
);
3119 // XXX: not implemented yet
3120 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
3121 assert(prog_data
->binding_table
.plane_start
[1] == 0xd0d0d0d0);
3122 assert(prog_data
->binding_table
.plane_start
[2] == 0xd0d0d0d0);
3127 iris_use_optional_res(struct iris_batch
*batch
,
3128 struct pipe_resource
*res
,
3132 struct iris_bo
*bo
= iris_resource_bo(res
);
3133 iris_use_pinned_bo(batch
, bo
, writeable
);
3137 /* ------------------------------------------------------------------- */
3140 * Pin any BOs which were installed by a previous batch, and restored
3141 * via the hardware logical context mechanism.
3143 * We don't need to re-emit all state every batch - the hardware context
3144 * mechanism will save and restore it for us. This includes pointers to
3145 * various BOs...which won't exist unless we ask the kernel to pin them
3146 * by adding them to the validation list.
3148 * We can skip buffers if we've re-emitted those packets, as we're
3149 * overwriting those stale pointers with new ones, and don't actually
3150 * refer to the old BOs.
3153 iris_restore_context_saved_bos(struct iris_context
*ice
,
3154 struct iris_batch
*batch
,
3155 const struct pipe_draw_info
*draw
)
3157 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3159 const uint64_t clean
= ~ice
->state
.dirty
;
3161 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3162 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3165 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3166 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3169 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3170 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3173 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3174 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3177 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3178 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3181 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3182 if (clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
))
3185 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3186 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3191 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3193 for (int i
= 0; i
< 4; i
++) {
3194 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3196 if (range
->length
== 0)
3199 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3200 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3203 iris_use_pinned_bo(batch
, res
->bo
, false);
3205 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3209 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3210 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3211 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3213 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3216 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3217 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3218 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3220 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3221 iris_use_pinned_bo(batch
, bo
, false);
3224 // XXX: scratch buffer
3228 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3229 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3231 if (cso_fb
->zsbuf
) {
3232 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3233 // XXX: depth might not be writable...
3234 iris_use_pinned_bo(batch
, zres
->bo
, true);
3238 if (draw
->index_size
> 0) {
3239 // XXX: index buffer
3242 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3243 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3244 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3245 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3246 iris_use_pinned_bo(batch
, res
->bo
, false);
3252 iris_upload_render_state(struct iris_context
*ice
,
3253 struct iris_batch
*batch
,
3254 const struct pipe_draw_info
*draw
)
3256 const uint64_t dirty
= ice
->state
.dirty
;
3258 struct iris_genx_state
*genx
= ice
->state
.genx
;
3259 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3260 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3262 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3263 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3264 uint32_t cc_vp_address
;
3266 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3267 uint32_t *cc_vp_map
=
3268 stream_state(batch
, ice
->state
.dynamic_uploader
,
3269 &ice
->state
.last_res
.cc_vp
,
3270 4 * ice
->state
.num_viewports
*
3271 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3272 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3274 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3275 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3276 if (cso_rast
->depth_clip_near
)
3278 if (cso_rast
->depth_clip_far
)
3281 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3282 ccv
.MinimumDepth
= zmin
;
3283 ccv
.MaximumDepth
= zmax
;
3286 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3289 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3290 ptr
.CCViewportPointer
= cc_vp_address
;
3294 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3295 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3296 ptr
.SFClipViewportPointer
=
3297 emit_state(batch
, ice
->state
.dynamic_uploader
,
3298 &ice
->state
.last_res
.sf_cl_vp
,
3299 genx
->sf_cl_vp
, 4 * GENX(SF_CLIP_VIEWPORT_length
) *
3300 ice
->state
.num_viewports
, 64);
3306 // XXX: this is only flagged at setup, we assume a static configuration
3307 if (dirty
& IRIS_DIRTY_URB
) {
3308 iris_upload_urb_config(ice
, batch
);
3311 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3312 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3313 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3314 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3315 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
3316 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
3317 uint32_t blend_offset
;
3318 uint32_t *blend_map
=
3319 stream_state(batch
, ice
->state
.dynamic_uploader
,
3320 &ice
->state
.last_res
.blend
,
3321 4 * num_dwords
, 64, &blend_offset
);
3323 uint32_t blend_state_header
;
3324 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
3325 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3326 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
3329 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
3330 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
3331 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
3333 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
3334 ptr
.BlendStatePointer
= blend_offset
;
3335 ptr
.BlendStatePointerValid
= true;
3339 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3340 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3343 stream_state(batch
, ice
->state
.dynamic_uploader
,
3344 &ice
->state
.last_res
.color_calc
,
3345 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
3347 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
3348 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
3349 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
3350 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
3351 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
3352 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
3353 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
3355 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
3356 ptr
.ColorCalcStatePointer
= cc_offset
;
3357 ptr
.ColorCalcStatePointerValid
= true;
3361 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3362 // XXX: wrong dirty tracking...
3363 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3366 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3367 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3372 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3374 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
3375 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3377 /* The Skylake PRM contains the following restriction:
3379 * "The driver must ensure The following case does not occur
3380 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3381 * buffer 3 read length equal to zero committed followed by a
3382 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3385 * To avoid this, we program the buffers in the highest slots.
3386 * This way, slot 0 is only used if slot 3 is also used.
3390 for (int i
= 3; i
>= 0; i
--) {
3391 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3393 if (range
->length
== 0)
3396 // XXX: is range->block a constbuf index? it would be nice
3397 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3398 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3400 assert(cbuf
->data
.offset
% 32 == 0);
3402 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
3403 pkt
.ConstantBody
.Buffer
[n
] =
3404 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
3405 : ro_bo(batch
->screen
->workaround_bo
, 0);
3412 struct iris_binder
*binder
= &batch
->binder
;
3414 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3415 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3416 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
3417 ptr
._3DCommandSubOpcode
= 38 + stage
;
3418 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
3423 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3424 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3425 iris_populate_binding_table(ice
, batch
, stage
);
3429 if (ice
->state
.need_border_colors
)
3430 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
3432 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3433 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
3434 !ice
->shaders
.prog
[stage
])
3437 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3438 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3440 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3442 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
3443 ptr
._3DCommandSubOpcode
= 43 + stage
;
3444 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
3448 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
3449 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
3451 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
3452 if (ice
->state
.framebuffer
.samples
> 0)
3453 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
3457 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
3458 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
3459 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
3463 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3464 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
3467 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3470 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
3471 iris_use_pinned_bo(batch
, cache
->bo
, false);
3472 iris_batch_emit(batch
, shader
->derived_data
,
3473 iris_derived_program_state_size(stage
));
3475 if (stage
== MESA_SHADER_TESS_EVAL
) {
3476 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
3477 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
3478 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
3479 } else if (stage
== MESA_SHADER_GEOMETRY
) {
3480 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
3485 if (ice
->state
.streamout_active
) {
3486 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
3487 iris_batch_emit(batch
, genx
->so_buffers
,
3488 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
3489 for (int i
= 0; i
< 4; i
++) {
3490 struct iris_stream_output_target
*tgt
=
3491 (void *) ice
->state
.so_target
[i
];
3493 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3495 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3501 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
3502 uint32_t *decl_list
=
3503 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
3504 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
3507 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3508 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3510 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
3511 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
3512 sol
.SOFunctionEnable
= true;
3513 sol
.SOStatisticsEnable
= true;
3515 // XXX: GL_PRIMITIVES_GENERATED query
3516 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
;
3517 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
3520 assert(ice
->state
.streamout
);
3522 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
3523 GENX(3DSTATE_STREAMOUT_length
));
3526 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
3527 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
3531 if (dirty
& IRIS_DIRTY_CLIP
) {
3532 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3533 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3535 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
3536 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
3537 if (wm_prog_data
->barycentric_interp_modes
&
3538 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
3539 cl
.NonPerspectiveBarycentricEnable
= true;
3541 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
3542 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
3544 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
3545 ARRAY_SIZE(cso_rast
->clip
));
3548 if (dirty
& IRIS_DIRTY_RASTER
) {
3549 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3550 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
3551 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
3555 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
3556 if (dirty
& IRIS_DIRTY_WM
) {
3557 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3558 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
3560 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
3561 wm
.BarycentricInterpolationMode
=
3562 wm_prog_data
->barycentric_interp_modes
;
3564 if (wm_prog_data
->early_fragment_tests
)
3565 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
3566 else if (wm_prog_data
->has_side_effects
)
3567 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
3569 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
3572 if (dirty
& IRIS_DIRTY_SBE
) {
3573 iris_emit_sbe(batch
, ice
);
3576 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
3577 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3578 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
3579 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
3580 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
3581 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
3582 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
3585 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
3586 ARRAY_SIZE(cso_blend
->ps_blend
));
3589 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
3590 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
3591 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
3593 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
3594 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
3595 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
3596 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
3598 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
3601 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
3602 uint32_t scissor_offset
=
3603 emit_state(batch
, ice
->state
.dynamic_uploader
,
3604 &ice
->state
.last_res
.scissor
,
3605 ice
->state
.scissors
,
3606 sizeof(struct pipe_scissor_state
) *
3607 ice
->state
.num_viewports
, 32);
3609 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
3610 ptr
.ScissorRectPointer
= scissor_offset
;
3614 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
3615 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3616 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
3618 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
3620 if (cso_fb
->zsbuf
) {
3621 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
3622 // XXX: depth might not be writable...
3623 iris_use_pinned_bo(batch
, zres
->bo
, true);
3627 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
3628 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
3629 for (int i
= 0; i
< 32; i
++) {
3630 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
3635 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
3636 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
3637 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
3641 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
3642 topo
.PrimitiveTopologyType
=
3643 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
3647 if (draw
->index_size
> 0) {
3648 struct iris_resource
*res
= NULL
;
3651 if (draw
->has_user_indices
) {
3652 u_upload_data(ice
->ctx
.stream_uploader
, 0,
3653 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
3654 &offset
, (struct pipe_resource
**) &res
);
3656 res
= (struct iris_resource
*) draw
->index
.resource
;
3660 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
3661 ib
.IndexFormat
= draw
->index_size
>> 1;
3663 ib
.BufferSize
= res
->bo
->size
;
3664 ib
.BufferStartingAddress
= ro_bo(res
->bo
, offset
);
3668 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3669 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3670 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
3672 if (cso
->num_buffers
> 0) {
3673 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
3674 (1 + vb_dwords
* cso
->num_buffers
));
3676 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3677 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3678 iris_use_pinned_bo(batch
, res
->bo
, false);
3683 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
3684 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3685 const unsigned entries
= MAX2(cso
->count
, 1);
3686 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
3687 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
3688 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
3689 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
3692 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
3693 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
3694 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
3695 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
3697 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
3698 if (vs_prog_data
->uses_vertexid
) {
3699 sgv
.VertexIDEnable
= true;
3700 sgv
.VertexIDComponentNumber
= 2;
3701 sgv
.VertexIDElementOffset
= cso
->count
;
3704 if (vs_prog_data
->uses_instanceid
) {
3705 sgv
.InstanceIDEnable
= true;
3706 sgv
.InstanceIDComponentNumber
= 3;
3707 sgv
.InstanceIDElementOffset
= cso
->count
;
3713 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
3714 if (draw
->primitive_restart
) {
3715 vf
.IndexedDrawCutIndexEnable
= true;
3716 vf
.CutIndex
= draw
->restart_index
;
3721 // XXX: Gen8 - PMA fix
3723 #define _3DPRIM_END_OFFSET 0x2420
3724 #define _3DPRIM_START_VERTEX 0x2430
3725 #define _3DPRIM_VERTEX_COUNT 0x2434
3726 #define _3DPRIM_INSTANCE_COUNT 0x2438
3727 #define _3DPRIM_START_INSTANCE 0x243C
3728 #define _3DPRIM_BASE_VERTEX 0x2440
3730 if (draw
->indirect
) {
3731 /* We don't support this MultidrawIndirect. */
3732 assert(!draw
->indirect
->indirect_draw_count
);
3734 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
3737 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3738 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
3739 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
3741 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3742 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
3743 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
3745 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3746 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
3747 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
3749 if (draw
->index_size
) {
3750 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3751 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
3752 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3754 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3755 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3756 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
3759 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3760 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
3761 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
3763 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3764 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
3770 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
3771 prim
.StartInstanceLocation
= draw
->start_instance
;
3772 prim
.InstanceCount
= draw
->instance_count
;
3773 prim
.VertexCountPerInstance
= draw
->count
;
3774 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
3776 // XXX: this is probably bonkers.
3777 prim
.StartVertexLocation
= draw
->start
;
3779 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
3781 if (draw
->index_size
) {
3782 prim
.BaseVertexLocation
+= draw
->index_bias
;
3784 prim
.StartVertexLocation
+= draw
->index_bias
;
3787 //prim.BaseVertexLocation = ...;
3790 if (!batch
->contains_draw
) {
3791 iris_restore_context_saved_bos(ice
, batch
, draw
);
3792 batch
->contains_draw
= true;
3797 * State module teardown.
3800 iris_destroy_state(struct iris_context
*ice
)
3802 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
3804 // XXX: unreference resources/surfaces.
3805 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
3806 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
3808 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
3810 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
3811 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3812 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
3814 free(ice
->state
.genx
);
3816 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
3817 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
3818 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
3819 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
3820 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
3823 /* ------------------------------------------------------------------- */
3826 flags_to_post_sync_op(uint32_t flags
)
3828 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
3829 return WriteImmediateData
;
3831 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
3832 return WritePSDepthCount
;
3834 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
3835 return WriteTimestamp
;
3841 * Do the given flags have a Post Sync or LRI Post Sync operation?
3843 static enum pipe_control_flags
3844 get_post_sync_flags(enum pipe_control_flags flags
)
3846 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
3847 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3848 PIPE_CONTROL_WRITE_TIMESTAMP
|
3849 PIPE_CONTROL_LRI_POST_SYNC_OP
;
3851 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
3852 * "LRI Post Sync Operation". So more than one bit set would be illegal.
3854 assert(util_bitcount(flags
) <= 1);
3859 // XXX: compute support
3860 #define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
3863 * Emit a series of PIPE_CONTROL commands, taking into account any
3864 * workarounds necessary to actually accomplish the caller's request.
3866 * Unless otherwise noted, spec quotations in this function come from:
3868 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
3869 * Restrictions for PIPE_CONTROL.
3871 * You should not use this function directly. Use the helpers in
3872 * iris_pipe_control.c instead, which may split the pipe control further.
3875 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
3876 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
3878 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3879 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
3880 enum pipe_control_flags non_lri_post_sync_flags
=
3881 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
3883 /* Recursive PIPE_CONTROL workarounds --------------------------------
3884 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
3886 * We do these first because we want to look at the original operation,
3887 * rather than any workarounds we set.
3889 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
3890 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
3891 * lists several workarounds:
3893 * "Project: SKL, KBL, BXT
3895 * If the VF Cache Invalidation Enable is set to a 1 in a
3896 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
3897 * sets to 0, with the VF Cache Invalidation Enable set to 0
3898 * needs to be sent prior to the PIPE_CONTROL with VF Cache
3899 * Invalidation Enable set to a 1."
3901 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
3904 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
3905 /* Project: SKL / Argument: LRI Post Sync Operation [23]
3907 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
3908 * programmed prior to programming a PIPECONTROL command with "LRI
3909 * Post Sync Operation" in GPGPU mode of operation (i.e when
3910 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
3912 * The same text exists a few rows below for Post Sync Op.
3914 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
3917 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
3919 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
3920 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
3921 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
3923 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
3927 /* "Flush Types" workarounds ---------------------------------------------
3928 * We do these now because they may add post-sync operations or CS stalls.
3931 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
3932 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
3934 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
3935 * 'Write PS Depth Count' or 'Write Timestamp'."
3938 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3939 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3940 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
3941 bo
= batch
->screen
->workaround_bo
;
3945 /* #1130 from Gen10 workarounds page:
3947 * "Enable Depth Stall on every Post Sync Op if Render target Cache
3948 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
3949 * board stall if Render target cache flush is enabled."
3951 * Applicable to CNL B0 and C0 steppings only.
3953 * The wording here is unclear, and this workaround doesn't look anything
3954 * like the internal bug report recommendations, but leave it be for now...
3956 if (GEN_GEN
== 10) {
3957 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
3958 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
3959 } else if (flags
& non_lri_post_sync_flags
) {
3960 flags
|= PIPE_CONTROL_DEPTH_STALL
;
3964 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
3965 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
3967 * "This bit must be DISABLED for operations other than writing
3970 * This seems like nonsense. An Ivybridge workaround requires us to
3971 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
3972 * operation. Gen8+ requires us to emit depth stalls and depth cache
3973 * flushes together. So, it's hard to imagine this means anything other
3974 * than "we originally intended this to be used for PS_DEPTH_COUNT".
3976 * We ignore the supposed restriction and do nothing.
3980 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
3981 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
3982 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
3984 * "This bit must be DISABLED for End-of-pipe (Read) fences,
3985 * PS_DEPTH_COUNT or TIMESTAMP queries."
3987 * TODO: Implement end-of-pipe checking.
3989 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
3990 PIPE_CONTROL_WRITE_TIMESTAMP
)));
3993 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
3994 /* From the PIPE_CONTROL instruction table, bit 1:
3996 * "This bit is ignored if Depth Stall Enable is set.
3997 * Further, the render cache is not flushed even if Write Cache
3998 * Flush Enable bit is set."
4000 * We assert that the caller doesn't do this combination, to try and
4001 * prevent mistakes. It shouldn't hurt the GPU, though.
4003 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
4004 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
4007 /* PIPE_CONTROL page workarounds ------------------------------------- */
4009 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
4010 /* From the PIPE_CONTROL page itself:
4013 * Restriction: Pipe_control with CS-stall bit set must be issued
4014 * before a pipe-control command that has the State Cache
4015 * Invalidate bit set."
4017 flags
|= PIPE_CONTROL_CS_STALL
;
4020 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
4021 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
4024 * SW must always program Post-Sync Operation to "Write Immediate
4025 * Data" when Flush LLC is set."
4027 * For now, we just require the caller to do it.
4029 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
4032 /* "Post-Sync Operation" workarounds -------------------------------- */
4034 /* Project: All / Argument: Global Snapshot Count Reset [19]
4036 * "This bit must not be exercised on any product.
4037 * Requires stall bit ([20] of DW1) set."
4039 * We don't use this, so we just assert that it isn't used. The
4040 * PIPE_CONTROL instruction page indicates that they intended this
4041 * as a debug feature and don't think it is useful in production,
4042 * but it may actually be usable, should we ever want to.
4044 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
4046 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
4047 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
4048 /* Project: All / Arguments:
4050 * - Generic Media State Clear [16]
4051 * - Indirect State Pointers Disable [16]
4053 * "Requires stall bit ([20] of DW1) set."
4055 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
4056 * State Clear) says:
4058 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4059 * programmed prior to programming a PIPECONTROL command with "Media
4060 * State Clear" set in GPGPU mode of operation"
4062 * This is a subset of the earlier rule, so there's nothing to do.
4064 flags
|= PIPE_CONTROL_CS_STALL
;
4067 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
4068 /* Project: All / Argument: Store Data Index
4070 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4073 * For now, we just assert that the caller does this. We might want to
4074 * automatically add a write to the workaround BO...
4076 assert(non_lri_post_sync_flags
!= 0);
4079 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
4080 /* Project: All / Argument: Sync GFDT
4082 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
4083 * than '0' or 0x2520[13] must be set."
4085 * For now, we just assert that the caller does this.
4087 assert(non_lri_post_sync_flags
!= 0);
4090 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
4091 /* Project: IVB+ / Argument: TLB inv
4093 * "Requires stall bit ([20] of DW1) set."
4095 * Also, from the PIPE_CONTROL instruction table:
4098 * Post Sync Operation or CS stall must be set to ensure a TLB
4099 * invalidation occurs. Otherwise no cycle will occur to the TLB
4100 * cache to invalidate."
4102 * This is not a subset of the earlier rule, so there's nothing to do.
4104 flags
|= PIPE_CONTROL_CS_STALL
;
4107 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
4108 /* TODO: The big Skylake GT4 post sync op workaround */
4111 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
4113 if (IS_COMPUTE_PIPELINE(batch
)) {
4114 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
4115 /* Project: SKL+ / Argument: Tex Invalidate
4116 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
4118 flags
|= PIPE_CONTROL_CS_STALL
;
4121 if (GEN_GEN
== 8 && (post_sync_flags
||
4122 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
4123 PIPE_CONTROL_DEPTH_STALL
|
4124 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4125 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4126 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
4127 /* Project: BDW / Arguments:
4129 * - LRI Post Sync Operation [23]
4130 * - Post Sync Op [15:14]
4132 * - Depth Stall [13]
4133 * - Render Target Cache Flush [12]
4134 * - Depth Cache Flush [0]
4135 * - DC Flush Enable [5]
4137 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
4140 flags
|= PIPE_CONTROL_CS_STALL
;
4142 /* Also, from the PIPE_CONTROL instruction table, bit 20:
4145 * This bit must be always set when PIPE_CONTROL command is
4146 * programmed by GPGPU and MEDIA workloads, except for the cases
4147 * when only Read Only Cache Invalidation bits are set (State
4148 * Cache Invalidation Enable, Instruction cache Invalidation
4149 * Enable, Texture Cache Invalidation Enable, Constant Cache
4150 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
4151 * need not implemented when FF_DOP_CG is disable via "Fixed
4152 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
4154 * It sounds like we could avoid CS stalls in some cases, but we
4155 * don't currently bother. This list isn't exactly the list above,
4161 /* "Stall" workarounds ----------------------------------------------
4162 * These have to come after the earlier ones because we may have added
4163 * some additional CS stalls above.
4166 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
4167 /* Project: PRE-SKL, VLV, CHV
4169 * "[All Stepping][All SKUs]:
4171 * One of the following must also be set:
4173 * - Render Target Cache Flush Enable ([12] of DW1)
4174 * - Depth Cache Flush Enable ([0] of DW1)
4175 * - Stall at Pixel Scoreboard ([1] of DW1)
4176 * - Depth Stall ([13] of DW1)
4177 * - Post-Sync Operation ([13] of DW1)
4178 * - DC Flush Enable ([5] of DW1)"
4180 * If we don't already have one of those bits set, we choose to add
4181 * "Stall at Pixel Scoreboard". Some of the other bits require a
4182 * CS stall as a workaround (see above), which would send us into
4183 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
4184 * appears to be safe, so we choose that.
4186 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
4187 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
4188 PIPE_CONTROL_WRITE_IMMEDIATE
|
4189 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4190 PIPE_CONTROL_WRITE_TIMESTAMP
|
4191 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
4192 PIPE_CONTROL_DEPTH_STALL
|
4193 PIPE_CONTROL_DATA_CACHE_FLUSH
;
4194 if (!(flags
& wa_bits
))
4195 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4198 /* Emit --------------------------------------------------------------- */
4200 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
4201 pc
.LRIPostSyncOperation
= NoLRIOperation
;
4202 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
4203 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
4204 pc
.StoreDataIndex
= 0;
4205 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
4206 pc
.GlobalSnapshotCountReset
=
4207 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
4208 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
4209 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
4210 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
4211 pc
.RenderTargetCacheFlushEnable
=
4212 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
4213 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
4214 pc
.StateCacheInvalidationEnable
=
4215 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
4216 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4217 pc
.ConstantCacheInvalidationEnable
=
4218 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
4219 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
4220 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
4221 pc
.InstructionCacheInvalidateEnable
=
4222 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
4223 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
4224 pc
.IndirectStatePointersDisable
=
4225 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
4226 pc
.TextureCacheInvalidationEnable
=
4227 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
4228 pc
.Address
= ro_bo(bo
, offset
);
4229 pc
.ImmediateData
= imm
;
4234 genX(init_state
)(struct iris_context
*ice
)
4236 struct pipe_context
*ctx
= &ice
->ctx
;
4237 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
4239 ctx
->create_blend_state
= iris_create_blend_state
;
4240 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
4241 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
4242 ctx
->create_sampler_state
= iris_create_sampler_state
;
4243 ctx
->create_sampler_view
= iris_create_sampler_view
;
4244 ctx
->create_surface
= iris_create_surface
;
4245 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
4246 ctx
->create_compute_state
= iris_create_compute_state
;
4247 ctx
->bind_blend_state
= iris_bind_blend_state
;
4248 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
4249 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
4250 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
4251 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
4252 ctx
->bind_compute_state
= iris_bind_compute_state
;
4253 ctx
->delete_blend_state
= iris_delete_state
;
4254 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
4255 ctx
->delete_fs_state
= iris_delete_state
;
4256 ctx
->delete_rasterizer_state
= iris_delete_state
;
4257 ctx
->delete_sampler_state
= iris_delete_state
;
4258 ctx
->delete_vertex_elements_state
= iris_delete_state
;
4259 ctx
->delete_compute_state
= iris_delete_state
;
4260 ctx
->delete_tcs_state
= iris_delete_state
;
4261 ctx
->delete_tes_state
= iris_delete_state
;
4262 ctx
->delete_gs_state
= iris_delete_state
;
4263 ctx
->delete_vs_state
= iris_delete_state
;
4264 ctx
->set_blend_color
= iris_set_blend_color
;
4265 ctx
->set_clip_state
= iris_set_clip_state
;
4266 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
4267 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
4268 ctx
->set_sampler_views
= iris_set_sampler_views
;
4269 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
4270 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
4271 ctx
->set_sample_mask
= iris_set_sample_mask
;
4272 ctx
->set_scissor_states
= iris_set_scissor_states
;
4273 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
4274 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
4275 ctx
->set_viewport_states
= iris_set_viewport_states
;
4276 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
4277 ctx
->surface_destroy
= iris_surface_destroy
;
4278 ctx
->draw_vbo
= iris_draw_vbo
;
4279 ctx
->launch_grid
= iris_launch_grid
;
4280 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
4281 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
4282 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
4284 ice
->vtbl
.destroy_state
= iris_destroy_state
;
4285 ice
->vtbl
.init_render_context
= iris_init_render_context
;
4286 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
4287 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
4288 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
4289 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
4290 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
4291 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
4292 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
4293 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
4294 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
4295 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
4297 ice
->state
.dirty
= ~0ull;
4299 ice
->state
.sample_mask
= 0xffff;
4300 ice
->state
.num_viewports
= 1;
4301 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
4303 /* Make a 1x1x1 null surface for unbound textures */
4304 void *null_surf_map
=
4305 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
4306 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
4307 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));