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iris: VB fixes
[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "intel/compiler/brw_compiler.h"
42 #include "intel/common/gen_sample_positions.h"
43 #include "iris_batch.h"
44 #include "iris_context.h"
45 #include "iris_pipe.h"
46 #include "iris_resource.h"
47
48 #define __gen_address_type struct iris_address
49 #define __gen_user_data struct iris_batch
50
51 static uint64_t
52 __gen_combine_address(struct iris_batch *batch, void *location,
53 struct iris_address addr, uint32_t delta)
54 {
55 if (addr.bo == NULL)
56 return addr.offset + delta;
57
58 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
59 addr.offset + delta, addr.reloc_flags);
60 }
61
62 #define __genxml_cmd_length(cmd) cmd ## _length
63 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
64 #define __genxml_cmd_header(cmd) cmd ## _header
65 #define __genxml_cmd_pack(cmd) cmd ## _pack
66
67 #define iris_pack_command(cmd, dst, name) \
68 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
69 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
70 ({ __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name); \
71 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __genxml_cmd_length(cmd) * 4)); \
72 _dst = NULL; \
73 }))
74
75 #define iris_pack_state(cmd, dst, name) \
76 for (struct cmd name = {}, \
77 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
78 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
79 _dst = NULL)
80
81 #define iris_emit_cmd(batch, cmd, name) \
82 iris_require_command_space(batch, 4 * __genxml_cmd_length(cmd)); \
83 iris_pack_command(cmd, batch->cmdbuf.map_next, name)
84
85 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
86 do { \
87 iris_require_command_space(batch, 4 * num_dwords); \
88 uint32_t *dw = batch->cmdbuf.map_next; \
89 for (uint32_t i = 0; i < num_dwords; i++) \
90 dw[i] = (dwords0)[i] | (dwords1)[i]; \
91 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
92 } while (0)
93
94 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
95 do { \
96 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
97 assert(num_dw <= ARRAY_SIZE(dwords)); \
98 iris_require_command_space(batch, 4 * num_dw); \
99 int addr_idx = GENX(addr_field) / 32; \
100 uint32_t *dw = batch->cmdbuf.map_next; \
101 for (uint32_t i = 0; i < addr_idx; i++) { \
102 dw[i] = (dwords)[i]; \
103 } \
104 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
105 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
106 addr.offset + (dwords)[addr_idx + 1], \
107 addr.reloc_flags); \
108 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
109 dw[i] = (dwords)[i]; \
110 } \
111 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
112 } while (0)
113
114 #include "genxml/genX_pack.h"
115 #include "genxml/gen_macros.h"
116 #include "genxml/genX_bits.h"
117
118 #define MOCS_WB (2 << 1)
119
120 UNUSED static void pipe_asserts()
121 {
122 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
123
124 /* pipe_logicop happens to match the hardware. */
125 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
126 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
127 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
128 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
129 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
130 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
131 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
132 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
133 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
134 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
135 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
136 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
137 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
138 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
139 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
140 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
141
142 /* pipe_blend_func happens to match the hardware. */
143 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
162
163 /* pipe_blend_func happens to match the hardware. */
164 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
165 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
166 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
167 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
168 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
169
170 /* pipe_stencil_op happens to match the hardware. */
171 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
172 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
173 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
174 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
175 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
176 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
177 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
178 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
179 #undef PIPE_ASSERT
180 }
181
182 static unsigned
183 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
184 {
185 static const unsigned map[] = {
186 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
187 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
188 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
189 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
190 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
191 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
192 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
193 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
194 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
195 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
196 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
197 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
198 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
199 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
200 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
201 };
202
203 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
204 }
205
206 static unsigned
207 translate_compare_func(enum pipe_compare_func pipe_func)
208 {
209 static const unsigned map[] = {
210 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
211 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
212 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
213 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
214 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
215 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
216 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
217 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
218 };
219 return map[pipe_func];
220 }
221
222 static unsigned
223 translate_shadow_func(enum pipe_compare_func pipe_func)
224 {
225 /* Gallium specifies the result of shadow comparisons as:
226 *
227 * 1 if ref <op> texel,
228 * 0 otherwise.
229 *
230 * The hardware does:
231 *
232 * 0 if texel <op> ref,
233 * 1 otherwise.
234 *
235 * So we need to flip the operator and also negate.
236 */
237 static const unsigned map[] = {
238 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
239 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
240 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
241 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
242 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
243 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
244 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
245 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
246 };
247 return map[pipe_func];
248 }
249
250 static unsigned
251 translate_cull_mode(unsigned pipe_face)
252 {
253 static const unsigned map[4] = {
254 [PIPE_FACE_NONE] = CULLMODE_NONE,
255 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
256 [PIPE_FACE_BACK] = CULLMODE_BACK,
257 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
258 };
259 return map[pipe_face];
260 }
261
262 static unsigned
263 translate_fill_mode(unsigned pipe_polymode)
264 {
265 static const unsigned map[4] = {
266 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
267 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
268 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
269 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
270 };
271 return map[pipe_polymode];
272 }
273
274 static struct iris_address
275 ro_bo(struct iris_bo *bo, uint32_t offset)
276 {
277 return (struct iris_address) { .bo = bo, .offset = offset };
278 }
279
280 static void
281 iris_upload_initial_gpu_state(struct iris_context *ice,
282 struct iris_batch *batch)
283 {
284 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
285 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
286 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
287 }
288 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
289 GEN_SAMPLE_POS_1X(pat._1xSample);
290 GEN_SAMPLE_POS_2X(pat._2xSample);
291 GEN_SAMPLE_POS_4X(pat._4xSample);
292 GEN_SAMPLE_POS_8X(pat._8xSample);
293 GEN_SAMPLE_POS_16X(pat._16xSample);
294 }
295 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
296 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
297 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
298 /* XXX: may need to set an offset for origin-UL framebuffers */
299 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
300
301 /* Just assign a static partitioning. */
302 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
303 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
304 alloc._3DCommandSubOpcode = 18 + i;
305 alloc.ConstantBufferOffset = 6 * i;
306 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
307 }
308 }
309 }
310
311 static void
312 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
313 {
314 }
315
316 static void
317 iris_set_blend_color(struct pipe_context *ctx,
318 const struct pipe_blend_color *state)
319 {
320 struct iris_context *ice = (struct iris_context *) ctx;
321
322 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
323 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
324 }
325
326 struct iris_blend_state {
327 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
328 uint32_t blend_state[GENX(BLEND_STATE_length)];
329 uint32_t blend_entries[BRW_MAX_DRAW_BUFFERS *
330 GENX(BLEND_STATE_ENTRY_length)];
331 };
332
333 static void *
334 iris_create_blend_state(struct pipe_context *ctx,
335 const struct pipe_blend_state *state)
336 {
337 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
338
339 iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) {
340 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
341 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
342 bs.AlphaToOneEnable = state->alpha_to_one;
343 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
344 bs.ColorDitherEnable = state->dither;
345 //bs.AlphaTestEnable = <comes from alpha state> :(
346 //bs.AlphaTestFunction = <comes from alpha state> :(
347 }
348
349 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
350 //pb.HasWriteableRT = <comes from somewhere> :(
351 //pb.AlphaTestEnable = <comes from alpha state> :(
352 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
353 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
354
355 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
356
357 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
358 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
359 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
360 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
361 }
362
363 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
364 iris_pack_state(GENX(BLEND_STATE_ENTRY), &cso->blend_entries[i], be) {
365 be.LogicOpEnable = state->logicop_enable;
366 be.LogicOpFunction = state->logicop_func;
367
368 be.PreBlendSourceOnlyClampEnable = false;
369 be.ColorClampRange = COLORCLAMP_RTFORMAT;
370 be.PreBlendColorClampEnable = true;
371 be.PostBlendColorClampEnable = true;
372
373 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
374
375 be.ColorBlendFunction = state->rt[i].rgb_func;
376 be.AlphaBlendFunction = state->rt[i].alpha_func;
377 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
378 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
379 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
380 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
381
382 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
383 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
384 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
385 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
386 }
387 }
388
389 return cso;
390 }
391
392 static void
393 iris_bind_blend_state(struct pipe_context *ctx, void *state)
394 {
395 struct iris_context *ice = (struct iris_context *) ctx;
396 ice->state.cso_blend = state;
397 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
398 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
399 }
400
401 struct iris_depth_stencil_alpha_state {
402 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
403 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
404
405 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
406 };
407
408 static void *
409 iris_create_zsa_state(struct pipe_context *ctx,
410 const struct pipe_depth_stencil_alpha_state *state)
411 {
412 struct iris_depth_stencil_alpha_state *cso =
413 malloc(sizeof(struct iris_depth_stencil_alpha_state));
414
415 cso->alpha = state->alpha;
416
417 bool two_sided_stencil = state->stencil[1].enabled;
418
419 /* The state tracker needs to optimize away EQUAL writes for us. */
420 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
421
422 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
423 wmds.StencilFailOp = state->stencil[0].fail_op;
424 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
425 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
426 wmds.StencilTestFunction =
427 translate_compare_func(state->stencil[0].func);
428 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
429 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
430 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
431 wmds.BackfaceStencilTestFunction =
432 translate_compare_func(state->stencil[1].func);
433 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
434 wmds.DoubleSidedStencilEnable = two_sided_stencil;
435 wmds.StencilTestEnable = state->stencil[0].enabled;
436 wmds.StencilBufferWriteEnable =
437 state->stencil[0].writemask != 0 ||
438 (two_sided_stencil && state->stencil[1].writemask != 0);
439 wmds.DepthTestEnable = state->depth.enabled;
440 wmds.DepthBufferWriteEnable = state->depth.writemask;
441 wmds.StencilTestMask = state->stencil[0].valuemask;
442 wmds.StencilWriteMask = state->stencil[0].writemask;
443 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
444 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
445 /* wmds.[Backface]StencilReferenceValue are merged later */
446 }
447
448 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
449 ccvp.MinimumDepth = state->depth.bounds_min;
450 ccvp.MaximumDepth = state->depth.bounds_max;
451 }
452
453 return cso;
454 }
455
456 static void
457 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
458 {
459 struct iris_context *ice = (struct iris_context *) ctx;
460 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
461 struct iris_depth_stencil_alpha_state *new_cso = state;
462
463 if (new_cso) {
464 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
465 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
466 }
467 }
468
469 ice->state.cso_zsa = new_cso;
470 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
471 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
472 }
473
474 struct iris_rasterizer_state {
475 uint32_t sf[GENX(3DSTATE_SF_length)];
476 uint32_t clip[GENX(3DSTATE_CLIP_length)];
477 uint32_t raster[GENX(3DSTATE_RASTER_length)];
478 uint32_t wm[GENX(3DSTATE_WM_length)];
479 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
480
481 bool flatshade; /* for shader state */
482 bool light_twoside; /* for shader state */
483 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
484 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
485 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
486 };
487
488 static void *
489 iris_create_rasterizer_state(struct pipe_context *ctx,
490 const struct pipe_rasterizer_state *state)
491 {
492 struct iris_rasterizer_state *cso =
493 malloc(sizeof(struct iris_rasterizer_state));
494
495 #if 0
496 sprite_coord_mode -> SBE PointSpriteTextureCoordinateOrigin
497 sprite_coord_enable -> SBE PointSpriteTextureCoordinateEnable
498 point_quad_rasterization -> SBE?
499
500 not necessary?
501 {
502 poly_smooth
503 force_persample_interp - ?
504 bottom_edge_rule
505
506 offset_units_unscaled - cap not exposed
507 }
508 #endif
509
510 cso->flatshade = state->flatshade;
511 cso->light_twoside = state->light_twoside;
512 cso->rasterizer_discard = state->rasterizer_discard;
513 cso->half_pixel_center = state->half_pixel_center;
514
515 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
516 sf.StatisticsEnable = true;
517 sf.ViewportTransformEnable = true;
518 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
519 sf.LineEndCapAntialiasingRegionWidth =
520 state->line_smooth ? _10pixels : _05pixels;
521 sf.LastPixelEnable = state->line_last_pixel;
522 sf.LineWidth = state->line_width;
523 sf.SmoothPointEnable = state->point_smooth;
524 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
525 sf.PointWidth = state->point_size;
526
527 if (state->flatshade_first) {
528 sf.TriangleStripListProvokingVertexSelect = 2;
529 sf.TriangleFanProvokingVertexSelect = 2;
530 sf.LineStripListProvokingVertexSelect = 1;
531 } else {
532 sf.TriangleFanProvokingVertexSelect = 1;
533 }
534 }
535
536 /* COMPLETE! */
537 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
538 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
539 rr.CullMode = translate_cull_mode(state->cull_face);
540 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
541 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
542 rr.DXMultisampleRasterizationEnable = state->multisample;
543 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
544 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
545 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
546 rr.GlobalDepthOffsetConstant = state->offset_units;
547 rr.GlobalDepthOffsetScale = state->offset_scale;
548 rr.GlobalDepthOffsetClamp = state->offset_clamp;
549 rr.SmoothPointEnable = state->point_smooth;
550 rr.AntialiasingEnable = state->line_smooth;
551 rr.ScissorRectangleEnable = state->scissor;
552 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
553 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
554 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
555 }
556
557 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
558 cl.StatisticsEnable = true;
559 cl.EarlyCullEnable = true;
560 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
561 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
562 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
563 cl.GuardbandClipTestEnable = true;
564 cl.ClipMode = CLIPMODE_NORMAL;
565 cl.ClipEnable = true;
566 cl.ViewportXYClipTestEnable = state->point_tri_clip;
567 cl.MinimumPointWidth = 0.125;
568 cl.MaximumPointWidth = 255.875;
569 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
570 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
571
572 if (state->flatshade_first) {
573 cl.TriangleStripListProvokingVertexSelect = 2;
574 cl.TriangleFanProvokingVertexSelect = 2;
575 cl.LineStripListProvokingVertexSelect = 1;
576 } else {
577 cl.TriangleFanProvokingVertexSelect = 1;
578 }
579 }
580
581 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
582 wm.LineAntialiasingRegionWidth = _10pixels;
583 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
584 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
585 wm.StatisticsEnable = true;
586 wm.LineStippleEnable = state->line_stipple_enable;
587 wm.PolygonStippleEnable = state->poly_stipple_enable;
588 // wm.BarycentricInterpolationMode = <comes from FS program> :(
589 // wm.EarlyDepthStencilControl = <comes from FS program> :(
590 }
591
592 /* Remap from 0..255 back to 1..256 */
593 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
594
595 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
596 line.LineStipplePattern = state->line_stipple_pattern;
597 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
598 line.LineStippleRepeatCount = line_stipple_factor;
599 }
600
601 return cso;
602 }
603
604 static void
605 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
606 {
607 struct iris_context *ice = (struct iris_context *) ctx;
608 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
609 struct iris_rasterizer_state *new_cso = state;
610
611 if (new_cso) {
612 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
613 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
614 sizeof(old_cso->line_stipple)) != 0) {
615 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
616 }
617
618 if (!old_cso ||
619 old_cso->half_pixel_center != new_cso->half_pixel_center) {
620 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
621 }
622 }
623
624 ice->state.cso_rast = new_cso;
625 ice->state.dirty |= IRIS_DIRTY_RASTER;
626 }
627
628 static uint32_t
629 translate_wrap(unsigned pipe_wrap)
630 {
631 static const unsigned map[] = {
632 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
633 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
634 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
635 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
636 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
637 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
638 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
639 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
640 };
641 return map[pipe_wrap];
642 }
643
644 /**
645 * Return true if the given wrap mode requires the border color to exist.
646 */
647 static bool
648 wrap_mode_needs_border_color(unsigned wrap_mode)
649 {
650 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
651 }
652
653 static unsigned
654 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
655 {
656 static const unsigned map[] = {
657 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
658 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
659 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
660 };
661 return map[pipe_mip];
662 }
663
664 struct iris_sampler_state {
665 struct pipe_sampler_state base;
666
667 bool needs_border_color;
668
669 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
670 };
671
672 static void *
673 iris_create_sampler_state(struct pipe_context *pctx,
674 const struct pipe_sampler_state *state)
675 {
676 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
677
678 if (!cso)
679 return NULL;
680
681 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
682 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
683
684 unsigned wrap_s = translate_wrap(state->wrap_s);
685 unsigned wrap_t = translate_wrap(state->wrap_t);
686 unsigned wrap_r = translate_wrap(state->wrap_r);
687
688 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
689 wrap_mode_needs_border_color(wrap_t) ||
690 wrap_mode_needs_border_color(wrap_r);
691
692 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
693 samp.TCXAddressControlMode = wrap_s;
694 samp.TCYAddressControlMode = wrap_t;
695 samp.TCZAddressControlMode = wrap_r;
696 samp.CubeSurfaceControlMode = state->seamless_cube_map;
697 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
698 samp.MinModeFilter = state->min_img_filter;
699 samp.MagModeFilter = state->mag_img_filter;
700 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
701 samp.MaximumAnisotropy = RATIO21;
702
703 if (state->max_anisotropy >= 2) {
704 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
705 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
706 samp.AnisotropicAlgorithm = EWAApproximation;
707 }
708
709 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
710 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
711
712 samp.MaximumAnisotropy =
713 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
714 }
715
716 /* Set address rounding bits if not using nearest filtering. */
717 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
718 samp.UAddressMinFilterRoundingEnable = true;
719 samp.VAddressMinFilterRoundingEnable = true;
720 samp.RAddressMinFilterRoundingEnable = true;
721 }
722
723 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
724 samp.UAddressMagFilterRoundingEnable = true;
725 samp.VAddressMagFilterRoundingEnable = true;
726 samp.RAddressMagFilterRoundingEnable = true;
727 }
728
729 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
730 samp.ShadowFunction = translate_shadow_func(state->compare_func);
731
732 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
733
734 samp.LODPreClampMode = CLAMP_MODE_OGL;
735 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
736 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
737 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
738
739 //samp.BorderColorPointer = <<comes from elsewhere>>
740 }
741
742 return cso;
743 }
744
745 static void
746 iris_bind_sampler_states(struct pipe_context *ctx,
747 enum pipe_shader_type p_stage,
748 unsigned start, unsigned count,
749 void **states)
750 {
751 struct iris_context *ice = (struct iris_context *) ctx;
752 gl_shader_stage stage = stage_from_pipe(p_stage);
753
754 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
755
756 for (int i = 0; i < count; i++) {
757 ice->state.samplers[stage][start + i] = states[i];
758 }
759
760 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
761 }
762
763 struct iris_sampler_view {
764 struct pipe_sampler_view pipe;
765 struct isl_view view;
766 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
767 };
768
769 /**
770 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
771 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
772 *
773 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
774 * 0 1 2 3 4 5
775 * 4 5 6 7 0 1
776 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
777 *
778 * which is simply adding 4 then modding by 8 (or anding with 7).
779 *
780 * We then may need to apply workarounds for textureGather hardware bugs.
781 */
782 static enum isl_channel_select
783 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
784 {
785 return (swizzle + 4) & 7;
786 }
787
788 static struct pipe_sampler_view *
789 iris_create_sampler_view(struct pipe_context *ctx,
790 struct pipe_resource *tex,
791 const struct pipe_sampler_view *tmpl)
792 {
793 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
794 struct iris_resource *itex = (struct iris_resource *) tex;
795 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
796
797 if (!isv)
798 return NULL;
799
800 /* initialize base object */
801 isv->pipe = *tmpl;
802 isv->pipe.context = ctx;
803 isv->pipe.texture = NULL;
804 pipe_reference_init(&isv->pipe.reference, 1);
805 pipe_resource_reference(&isv->pipe.texture, tex);
806
807 /* XXX: do we need brw_get_texture_swizzle hacks here? */
808
809 isv->view = (struct isl_view) {
810 .format = iris_isl_format_for_pipe_format(tmpl->format),
811 .base_level = tmpl->u.tex.first_level,
812 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
813 .base_array_layer = tmpl->u.tex.first_layer,
814 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
815 .swizzle = (struct isl_swizzle) {
816 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
817 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
818 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
819 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
820 },
821 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
822 };
823
824 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
825 .surf = &itex->surf, .view = &isv->view,
826 .mocs = MOCS_WB);
827 // .address = ...
828 // .aux_surf =
829 // .clear_color = clear_color,
830
831 return &isv->pipe;
832 }
833
834 struct iris_surface {
835 struct pipe_surface pipe;
836 struct isl_view view;
837 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
838 };
839
840 static struct pipe_surface *
841 iris_create_surface(struct pipe_context *ctx,
842 struct pipe_resource *tex,
843 const struct pipe_surface *tmpl)
844 {
845 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
846 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
847 struct pipe_surface *psurf = &surf->pipe;
848 struct iris_resource *itex = (struct iris_resource *) tex;
849
850 if (!surf)
851 return NULL;
852
853 pipe_reference_init(&psurf->reference, 1);
854 pipe_resource_reference(&psurf->texture, tex);
855 psurf->context = ctx;
856 psurf->format = tmpl->format;
857 psurf->width = tex->width0;
858 psurf->height = tex->height0;
859 psurf->texture = tex;
860 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
861 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
862 psurf->u.tex.level = tmpl->u.tex.level;
863
864 surf->view = (struct isl_view) {
865 .format = iris_isl_format_for_pipe_format(tmpl->format),
866 .base_level = tmpl->u.tex.level,
867 .levels = 1,
868 .base_array_layer = tmpl->u.tex.first_layer,
869 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
870 .swizzle = ISL_SWIZZLE_IDENTITY,
871 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
872 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
873 };
874
875 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
876 .surf = &itex->surf, .view = &surf->view,
877 .mocs = MOCS_WB);
878 // .address = ...
879 // .aux_surf =
880 // .clear_color = clear_color,
881
882 return psurf;
883 }
884
885 static void
886 iris_set_sampler_views(struct pipe_context *ctx,
887 enum pipe_shader_type shader,
888 unsigned start, unsigned count,
889 struct pipe_sampler_view **views)
890 {
891 }
892
893 static void
894 iris_set_clip_state(struct pipe_context *ctx,
895 const struct pipe_clip_state *state)
896 {
897 }
898
899 static void
900 iris_set_polygon_stipple(struct pipe_context *ctx,
901 const struct pipe_poly_stipple *state)
902 {
903 struct iris_context *ice = (struct iris_context *) ctx;
904 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
905 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
906 }
907
908 static void
909 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
910 {
911 struct iris_context *ice = (struct iris_context *) ctx;
912
913 ice->state.sample_mask = sample_mask;
914 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
915 }
916
917 static void
918 iris_set_scissor_states(struct pipe_context *ctx,
919 unsigned start_slot,
920 unsigned num_scissors,
921 const struct pipe_scissor_state *state)
922 {
923 struct iris_context *ice = (struct iris_context *) ctx;
924
925 // XXX: start_slot
926 ice->state.num_scissors = num_scissors;
927
928 for (unsigned i = start_slot; i < start_slot + num_scissors; i++) {
929 ice->state.scissors[i] = *state;
930 }
931
932 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
933 }
934
935 static void
936 iris_set_stencil_ref(struct pipe_context *ctx,
937 const struct pipe_stencil_ref *state)
938 {
939 struct iris_context *ice = (struct iris_context *) ctx;
940 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
941 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
942 }
943
944
945 struct iris_viewport_state {
946 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
947 };
948
949 static float
950 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
951 {
952 return fabsf(state->scale[axis]) * state->translate[axis];
953 }
954
955 #if 0
956 static void
957 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
958 float m00, float m11, float m30, float m31,
959 float *xmin, float *xmax,
960 float *ymin, float *ymax)
961 {
962 /* According to the "Vertex X,Y Clamping and Quantization" section of the
963 * Strips and Fans documentation:
964 *
965 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
966 * fixed-point "guardband" range supported by the rasterization hardware"
967 *
968 * and
969 *
970 * "In almost all circumstances, if an object’s vertices are actually
971 * modified by this clamping (i.e., had X or Y coordinates outside of
972 * the guardband extent the rendered object will not match the intended
973 * result. Therefore software should take steps to ensure that this does
974 * not happen - e.g., by clipping objects such that they do not exceed
975 * these limits after the Drawing Rectangle is applied."
976 *
977 * I believe the fundamental restriction is that the rasterizer (in
978 * the SF/WM stages) have a limit on the number of pixels that can be
979 * rasterized. We need to ensure any coordinates beyond the rasterizer
980 * limit are handled by the clipper. So effectively that limit becomes
981 * the clipper's guardband size.
982 *
983 * It goes on to say:
984 *
985 * "In addition, in order to be correctly rendered, objects must have a
986 * screenspace bounding box not exceeding 8K in the X or Y direction.
987 * This additional restriction must also be comprehended by software,
988 * i.e., enforced by use of clipping."
989 *
990 * This makes no sense. Gen7+ hardware supports 16K render targets,
991 * and you definitely need to be able to draw polygons that fill the
992 * surface. Our assumption is that the rasterizer was limited to 8K
993 * on Sandybridge, which only supports 8K surfaces, and it was actually
994 * increased to 16K on Ivybridge and later.
995 *
996 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
997 */
998 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
999
1000 if (m00 != 0 && m11 != 0) {
1001 /* First, we compute the screen-space render area */
1002 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1003 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1004 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1005 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1006
1007 /* We want the guardband to be centered on that */
1008 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1009 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1010 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1011 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1012
1013 /* Now we need it in native device coordinates */
1014 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1015 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1016 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1017 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1018
1019 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1020 * flipped upside-down. X should be fine though.
1021 */
1022 assert(ndc_gb_xmin <= ndc_gb_xmax);
1023 *xmin = ndc_gb_xmin;
1024 *xmax = ndc_gb_xmax;
1025 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1026 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1027 } else {
1028 /* The viewport scales to 0, so nothing will be rendered. */
1029 *xmin = 0.0f;
1030 *xmax = 0.0f;
1031 *ymin = 0.0f;
1032 *ymax = 0.0f;
1033 }
1034 }
1035 #endif
1036
1037 static void
1038 iris_set_viewport_states(struct pipe_context *ctx,
1039 unsigned start_slot,
1040 unsigned num_viewports,
1041 const struct pipe_viewport_state *state)
1042 {
1043 struct iris_context *ice = (struct iris_context *) ctx;
1044 struct iris_viewport_state *cso =
1045 malloc(sizeof(struct iris_viewport_state));
1046
1047 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1048 float x_extent = extent_from_matrix(&state[i], 0);
1049 float y_extent = extent_from_matrix(&state[i], 1);
1050
1051 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1052 vp.ViewportMatrixElementm00 = state[i].scale[0];
1053 vp.ViewportMatrixElementm11 = state[i].scale[1];
1054 vp.ViewportMatrixElementm22 = state[i].scale[2];
1055 vp.ViewportMatrixElementm30 = state[i].translate[0];
1056 vp.ViewportMatrixElementm31 = state[i].translate[1];
1057 vp.ViewportMatrixElementm32 = state[i].translate[2];
1058 /* XXX: in i965 this is computed based on the drawbuffer size,
1059 * but we don't have that here...
1060 */
1061 vp.XMinClipGuardband = -1.0;
1062 vp.XMaxClipGuardband = 1.0;
1063 vp.YMinClipGuardband = -1.0;
1064 vp.YMaxClipGuardband = 1.0;
1065 vp.XMinViewPort = -x_extent;
1066 vp.XMaxViewPort = x_extent;
1067 vp.YMinViewPort = -y_extent;
1068 vp.YMaxViewPort = y_extent;
1069 }
1070 }
1071
1072 ice->state.cso_vp = cso;
1073 // XXX: start_slot
1074 ice->state.num_viewports = num_viewports;
1075 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1076 }
1077
1078 struct iris_depth_state
1079 {
1080 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1081 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1082 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1083 };
1084
1085 static void
1086 iris_set_framebuffer_state(struct pipe_context *ctx,
1087 const struct pipe_framebuffer_state *state)
1088 {
1089 struct iris_context *ice = (struct iris_context *) ctx;
1090 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1091
1092 if (cso->samples != state->samples) {
1093 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1094 }
1095
1096 cso->width = state->width;
1097 cso->height = state->height;
1098 cso->layers = state->layers;
1099 cso->samples = state->samples;
1100
1101 unsigned i;
1102 for (i = 0; i < state->nr_cbufs; i++)
1103 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1104 for (; i < cso->nr_cbufs; i++)
1105 pipe_surface_reference(&cso->cbufs[i], NULL);
1106
1107 cso->nr_cbufs = state->nr_cbufs;
1108
1109 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1110
1111 struct isl_depth_stencil_hiz_emit_info info = {
1112 .mocs = MOCS_WB,
1113 };
1114
1115 // XXX: depth buffers
1116 }
1117
1118 static void
1119 iris_set_constant_buffer(struct pipe_context *ctx,
1120 enum pipe_shader_type shader, uint index,
1121 const struct pipe_constant_buffer *cb)
1122 {
1123 }
1124
1125
1126 static void
1127 iris_sampler_view_destroy(struct pipe_context *ctx,
1128 struct pipe_sampler_view *state)
1129 {
1130 pipe_resource_reference(&state->texture, NULL);
1131 free(state);
1132 }
1133
1134
1135 static void
1136 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1137 {
1138 pipe_resource_reference(&surface->texture, NULL);
1139 free(surface);
1140 }
1141
1142 static void
1143 iris_delete_state(struct pipe_context *ctx, void *state)
1144 {
1145 free(state);
1146 }
1147
1148 struct iris_vertex_buffer_state {
1149 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1150 struct iris_address bos[33];
1151 unsigned num_buffers;
1152 };
1153
1154 static void
1155 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1156 {
1157 if (cso) {
1158 for (unsigned i = 0; i < cso->num_buffers; i++)
1159 iris_bo_unreference(cso->bos[i].bo);
1160 free(cso);
1161 }
1162 }
1163
1164 static void
1165 iris_set_vertex_buffers(struct pipe_context *ctx,
1166 unsigned start_slot, unsigned count,
1167 const struct pipe_vertex_buffer *buffers)
1168 {
1169 struct iris_context *ice = (struct iris_context *) ctx;
1170 struct iris_vertex_buffer_state *cso =
1171 malloc(sizeof(struct iris_vertex_buffer_state));
1172
1173 /* If there are no buffers, do nothing. We can leave the stale
1174 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1175 * elements that point to them, it should be fine.
1176 */
1177 if (!buffers)
1178 return;
1179
1180 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1181
1182 cso->num_buffers = count;
1183
1184 iris_pack_state(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1185 vb.DWordLength = 4 * cso->num_buffers - 1;
1186 }
1187
1188 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1189
1190 for (unsigned i = 0; i < count; i++) {
1191 assert(!buffers[i].is_user_buffer);
1192
1193 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1194 iris_bo_reference(res->bo);
1195 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1196
1197 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1198 vb.VertexBufferIndex = start_slot + i;
1199 vb.MOCS = MOCS_WB;
1200 vb.AddressModifyEnable = true;
1201 vb.BufferPitch = buffers[i].stride;
1202 //vb.BufferStartingAddress = ro_bo(bo, buffers[i].buffer_offset);
1203 //vb.BufferSize = bo->size;
1204 }
1205
1206 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1207 }
1208
1209 ice->state.cso_vertex_buffers = cso;
1210 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1211 }
1212
1213 struct iris_vertex_element_state {
1214 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1215 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1216 unsigned count;
1217 };
1218
1219 static void *
1220 iris_create_vertex_elements(struct pipe_context *ctx,
1221 unsigned count,
1222 const struct pipe_vertex_element *state)
1223 {
1224 struct iris_vertex_element_state *cso =
1225 malloc(sizeof(struct iris_vertex_element_state));
1226
1227 cso->count = count;
1228
1229 /* TODO:
1230 * - create edge flag one
1231 * - create SGV ones
1232 * - if those are necessary, use count + 1/2/3... OR in the length
1233 */
1234 iris_pack_state(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1235
1236 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1237
1238 for (int i = 0; i < count; i++) {
1239 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1240 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1241 ve.Valid = true;
1242 ve.SourceElementOffset = state[i].src_offset;
1243 ve.SourceElementFormat =
1244 iris_isl_format_for_pipe_format(state[i].src_format);
1245 }
1246
1247 iris_pack_state(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1248 vi.VertexElementIndex = i;
1249 vi.InstancingEnable = state[i].instance_divisor > 0;
1250 vi.InstanceDataStepRate = state[i].instance_divisor;
1251 }
1252
1253 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1254 }
1255
1256 return cso;
1257 }
1258
1259 static void
1260 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1261 {
1262 struct iris_context *ice = (struct iris_context *) ctx;
1263
1264 ice->state.cso_vertex_elements = state;
1265 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1266 }
1267
1268 static void *
1269 iris_create_compute_state(struct pipe_context *ctx,
1270 const struct pipe_compute_state *state)
1271 {
1272 return malloc(1);
1273 }
1274
1275 static struct pipe_stream_output_target *
1276 iris_create_stream_output_target(struct pipe_context *ctx,
1277 struct pipe_resource *res,
1278 unsigned buffer_offset,
1279 unsigned buffer_size)
1280 {
1281 struct pipe_stream_output_target *t =
1282 CALLOC_STRUCT(pipe_stream_output_target);
1283 if (!t)
1284 return NULL;
1285
1286 pipe_reference_init(&t->reference, 1);
1287 pipe_resource_reference(&t->buffer, res);
1288 t->buffer_offset = buffer_offset;
1289 t->buffer_size = buffer_size;
1290 return t;
1291 }
1292
1293 static void
1294 iris_stream_output_target_destroy(struct pipe_context *ctx,
1295 struct pipe_stream_output_target *t)
1296 {
1297 pipe_resource_reference(&t->buffer, NULL);
1298 free(t);
1299 }
1300
1301 static void
1302 iris_set_stream_output_targets(struct pipe_context *ctx,
1303 unsigned num_targets,
1304 struct pipe_stream_output_target **targets,
1305 const unsigned *offsets)
1306 {
1307 }
1308
1309 void
1310 iris_setup_state_base_address(struct iris_context *ice,
1311 struct iris_batch *batch,
1312 struct iris_bo *instruction_bo)
1313 {
1314 if (!(ice->state.dirty & IRIS_DIRTY_STATE_BASE_ADDRESS))
1315 return;
1316
1317 //iris_batchbuffer_flush(...)
1318
1319 ice->state.dirty &= ~IRIS_DIRTY_STATE_BASE_ADDRESS;
1320
1321 /* XXX: PIPE_CONTROLs */
1322
1323 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
1324 #if 0
1325 // XXX: MOCS is stupid for this.
1326 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
1327 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
1328 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
1329 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
1330 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
1331 sba.InstructionMemoryObjectControlState = MOCS_WB;
1332 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
1333 #endif
1334
1335 sba.GeneralStateBaseAddressModifyEnable = true;
1336 sba.SurfaceStateBaseAddressModifyEnable = true;
1337 sba.DynamicStateBaseAddressModifyEnable = true;
1338 sba.IndirectObjectBaseAddressModifyEnable = true;
1339 sba.InstructionBaseAddressModifyEnable = true;
1340 sba.GeneralStateBufferSizeModifyEnable = true;
1341 sba.DynamicStateBufferSizeModifyEnable = true;
1342 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
1343 sba.IndirectObjectBufferSizeModifyEnable = true;
1344 sba.InstructionBuffersizeModifyEnable = true;
1345
1346 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
1347 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
1348 sba.InstructionBaseAddress = ro_bo(instruction_bo, 0);
1349
1350 sba.GeneralStateBufferSize = 0xfffff000;
1351 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
1352 sba.IndirectObjectBufferSize = 0xfffff000;
1353 sba.InstructionBufferSize = ALIGN(ice->shaders.cache.bo->size, 4096);
1354 sba.BindlessSurfaceStateSize = 0;
1355 }
1356 }
1357
1358 void
1359 iris_upload_render_state(struct iris_context *ice,
1360 struct iris_batch *batch,
1361 const struct pipe_draw_info *draw)
1362 {
1363 const uint64_t dirty = ice->state.dirty;
1364
1365 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
1366 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1367 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
1368
1369 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1370 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
1371 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
1372 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
1373 }
1374 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
1375 }
1376
1377 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1378 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1379 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1380 ptr.CCViewportPointer =
1381 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1382 }
1383 }
1384
1385 if (dirty & IRIS_DIRTY_PS_BLEND) {
1386 struct iris_blend_state *cso = ice->state.cso_blend;
1387 iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
1388 }
1389
1390 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1391 //struct iris_blend_state *cso = ice->state.cso_blend;
1392 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1393 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1394 // (alpha test function/enable) + has writeable RT from ???????
1395 }
1396
1397 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1398 struct iris_viewport_state *cso = ice->state.cso_vp;
1399 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1400 ptr.SFClipViewportPointer =
1401 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1402 }
1403 }
1404
1405 if (dirty & IRIS_DIRTY_CLIP) {
1406 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1407
1408 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
1409 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
1410 //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
1411 //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
1412 // also userclip stuffs...
1413 }
1414 iris_emit_merge(batch, cso->clip, dynamic_clip, ARRAY_SIZE(cso->clip));
1415 }
1416
1417 if (dirty & IRIS_DIRTY_RASTER) {
1418 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1419 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
1420 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
1421 }
1422
1423 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
1424 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1425 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
1426 }
1427
1428 if (dirty & IRIS_DIRTY_SCISSOR) {
1429 uint32_t scissor_offset =
1430 iris_emit_state(batch, ice->state.scissors,
1431 sizeof(struct pipe_scissor_state) *
1432 ice->state.num_scissors, 32);
1433
1434 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
1435 ptr.ScissorRectPointer = scissor_offset;
1436 }
1437 }
1438
1439 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
1440 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
1441 for (int i = 0; i < 32; i++) {
1442 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
1443 }
1444 }
1445 }
1446
1447 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1448 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1449 uint32_t cc_offset;
1450 void *cc_map =
1451 iris_alloc_state(batch,
1452 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1453 64, &cc_offset);
1454 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1455 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1456 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1457 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1458 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1459 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1460 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1461 }
1462 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1463 ptr.ColorCalcStatePointer = cc_offset;
1464 ptr.ColorCalcStatePointerValid = true;
1465 }
1466 }
1467
1468 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
1469 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
1470
1471 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
1472
1473 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
1474 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32);
1475 uint32_t *delta = cso->vertex_buffers +
1476 (2 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32);
1477
1478 iris_batch_emit(batch, cso->vertex_buffers, sizeof(uint32_t) *
1479 (1 + 4 * cso->num_buffers));
1480
1481 for (unsigned i = 0; i < cso->num_buffers; i++) {
1482 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
1483 cso->bos[i].bo, cso->bos[i].offset +
1484 *delta, cso->bos[i].reloc_flags);
1485 addr = (void *) addr + 16;
1486 delta = (void *) delta + 16;
1487 }
1488 }
1489
1490 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
1491 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
1492 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
1493 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
1494 for (int i = 0; i < cso->count; i++) {
1495 iris_batch_emit(batch, cso->vf_instancing[i],
1496 sizeof(cso->vf_instancing[0]));
1497 }
1498 for (int i = 0; i < cso->count; i++) {
1499 /* TODO: vertexid, instanceid support */
1500 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
1501 }
1502 }
1503
1504 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1505 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1506 ms.PixelLocation =
1507 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1508 if (ice->state.framebuffer.samples > 0)
1509 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1510 }
1511 }
1512
1513 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
1514 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
1515 ms.SampleMask = ice->state.sample_mask;
1516 }
1517 }
1518
1519 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1520 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
1521 continue;
1522
1523 // XXX: get sampler count from shader; don't emit them all...
1524 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1525
1526 uint32_t offset;
1527 uint32_t *map = iris_alloc_state(batch,
1528 count * 4 * GENX(SAMPLER_STATE_length),
1529 32, &offset);
1530
1531 for (int i = 0; i < count; i++) {
1532 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1533 4 * GENX(SAMPLER_STATE_length));
1534 map += GENX(SAMPLER_STATE_length);
1535 }
1536
1537 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1538 ptr._3DCommandSubOpcode = 43 + stage;
1539 ptr.PointertoVSSamplerState = offset;
1540 }
1541 }
1542
1543 if (1) {
1544 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
1545 topo.PrimitiveTopologyType =
1546 translate_prim_type(draw->mode, draw->vertices_per_patch);
1547 }
1548 }
1549
1550 if (1) {
1551 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
1552 if (draw->primitive_restart) {
1553 vf.IndexedDrawCutIndexEnable = true;
1554 vf.CutIndex = draw->restart_index;
1555 }
1556 }
1557 }
1558
1559 // draw->index_size > 0
1560 if (draw->index_size > 0) {
1561 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
1562
1563 assert(!draw->has_user_indices);
1564
1565 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
1566 ib.IndexFormat = draw->index_size;
1567 ib.MOCS = MOCS_WB;
1568 ib.BufferSize = res->bo->size;
1569 // XXX: gah, addresses :( need two different combine address funcs
1570 // ib.BufferStartingAddress = res->bo;
1571 }
1572 }
1573
1574 assert(!draw->indirect); // XXX: indirect support
1575
1576 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
1577 prim.StartInstanceLocation = draw->start_instance;
1578 prim.InstanceCount = draw->instance_count;
1579
1580 // XXX: this is probably bonkers.
1581 prim.StartVertexLocation = draw->start;
1582
1583 if (draw->index_size) {
1584 prim.BaseVertexLocation += draw->index_bias;
1585 } else {
1586 prim.StartVertexLocation += draw->index_bias;
1587 }
1588
1589 //prim.BaseVertexLocation = ...;
1590 }
1591 #if 0
1592 l3 configuration
1593
1594 3DSTATE_URB_*
1595 -> TODO
1596
1597 3DSTATE_CONSTANT_* - push constants
1598 -> TODO
1599
1600 Surfaces:
1601 - pull constants
1602 - ubos/ssbos/abos
1603 - images
1604 - textures
1605 - render targets - write and read
1606 3DSTATE_BINDING_TABLE_POINTERS_*
1607 -> TODO
1608
1609 3DSTATE_VS
1610 3DSTATE_HS
1611 3DSTATE_TE
1612 3DSTATE_DS
1613 3DSTATE_GS
1614 3DSTATE_PS_EXTRA
1615 3DSTATE_PS
1616 3DSTATE_STREAMOUT
1617 3DSTATE_SO_BUFFER
1618 3DSTATE_SO_DECL_LIST
1619
1620 3DSTATE_WM
1621 -> iris_raster_state + FS state (barycentric, EDSC)
1622 3DSTATE_SBE
1623 -> iris_raster_state (point sprite texture coordinate origin)
1624 -> bunch of shader state...
1625 3DSTATE_SBE_SWIZ
1626 -> FS state
1627
1628 3DSTATE_DEPTH_BUFFER
1629 3DSTATE_HIER_DEPTH_BUFFER
1630 3DSTATE_STENCIL_BUFFER
1631 3DSTATE_CLEAR_PARAMS
1632 -> iris_framebuffer_state?
1633 #endif
1634 }
1635
1636 static void
1637 iris_bind_state(struct pipe_context *ctx, void *state)
1638 {
1639 }
1640
1641 void
1642 iris_destroy_state(struct iris_context *ice)
1643 {
1644 // XXX: unreference resources/surfaces.
1645 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
1646 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
1647 }
1648 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
1649 }
1650
1651 void
1652 iris_init_state_functions(struct pipe_context *ctx)
1653 {
1654 ctx->create_blend_state = iris_create_blend_state;
1655 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
1656 ctx->create_rasterizer_state = iris_create_rasterizer_state;
1657 ctx->create_sampler_state = iris_create_sampler_state;
1658 ctx->create_sampler_view = iris_create_sampler_view;
1659 ctx->create_surface = iris_create_surface;
1660 ctx->create_vertex_elements_state = iris_create_vertex_elements;
1661 ctx->create_compute_state = iris_create_compute_state;
1662 ctx->bind_blend_state = iris_bind_blend_state;
1663 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
1664 ctx->bind_sampler_states = iris_bind_sampler_states;
1665 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
1666 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
1667 ctx->bind_compute_state = iris_bind_state;
1668 ctx->delete_blend_state = iris_delete_state;
1669 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
1670 ctx->delete_fs_state = iris_delete_state;
1671 ctx->delete_rasterizer_state = iris_delete_state;
1672 ctx->delete_sampler_state = iris_delete_state;
1673 ctx->delete_vertex_elements_state = iris_delete_state;
1674 ctx->delete_compute_state = iris_delete_state;
1675 ctx->delete_tcs_state = iris_delete_state;
1676 ctx->delete_tes_state = iris_delete_state;
1677 ctx->delete_gs_state = iris_delete_state;
1678 ctx->delete_vs_state = iris_delete_state;
1679 ctx->set_blend_color = iris_set_blend_color;
1680 ctx->set_clip_state = iris_set_clip_state;
1681 ctx->set_constant_buffer = iris_set_constant_buffer;
1682 ctx->set_sampler_views = iris_set_sampler_views;
1683 ctx->set_framebuffer_state = iris_set_framebuffer_state;
1684 ctx->set_polygon_stipple = iris_set_polygon_stipple;
1685 ctx->set_sample_mask = iris_set_sample_mask;
1686 ctx->set_scissor_states = iris_set_scissor_states;
1687 ctx->set_stencil_ref = iris_set_stencil_ref;
1688 ctx->set_vertex_buffers = iris_set_vertex_buffers;
1689 ctx->set_viewport_states = iris_set_viewport_states;
1690 ctx->sampler_view_destroy = iris_sampler_view_destroy;
1691 ctx->surface_destroy = iris_surface_destroy;
1692 ctx->draw_vbo = iris_draw_vbo;
1693 ctx->launch_grid = iris_launch_grid;
1694 ctx->create_stream_output_target = iris_create_stream_output_target;
1695 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
1696 ctx->set_stream_output_targets = iris_set_stream_output_targets;
1697 }