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iris: move key pop to state module
[mesa.git] / src / gallium / drivers / iris / iris_state.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25
26 #ifdef HAVE_VALGRIND
27 #include <valgrind.h>
28 #include <memcheck.h>
29 #define VG(x) x
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
31 #else
32 #define VG(x)
33 #endif
34
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "i915_drm.h"
42 #include "intel/compiler/brw_compiler.h"
43 #include "intel/common/gen_sample_positions.h"
44 #include "iris_batch.h"
45 #include "iris_context.h"
46 #include "iris_pipe.h"
47 #include "iris_resource.h"
48
49 #define __gen_address_type struct iris_address
50 #define __gen_user_data struct iris_batch
51
52 static uint64_t
53 __gen_combine_address(struct iris_batch *batch, void *location,
54 struct iris_address addr, uint32_t delta)
55 {
56 if (addr.bo == NULL)
57 return addr.offset + delta;
58
59 return iris_batch_reloc(batch, location - batch->cmdbuf.map, addr.bo,
60 addr.offset + delta, addr.reloc_flags);
61 }
62
63 #define __genxml_cmd_length(cmd) cmd ## _length
64 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
65 #define __genxml_cmd_header(cmd) cmd ## _header
66 #define __genxml_cmd_pack(cmd) cmd ## _pack
67
68 static void *
69 get_command_space(struct iris_batch *batch, unsigned bytes)
70 {
71 iris_require_command_space(batch, bytes);
72 void *map = batch->cmdbuf.map_next;
73 batch->cmdbuf.map_next += bytes;
74 return map;
75 }
76
77 #define _iris_pack_command(batch, cmd, dst, name) \
78 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
79 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
80 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
81 _dst = NULL; \
82 }))
83
84 #define iris_pack_command(cmd, dst, name) \
85 _iris_pack_command(NULL, cmd, dst, name)
86
87 #define iris_pack_state(cmd, dst, name) \
88 for (struct cmd name = {}, \
89 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
90 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
91 _dst = NULL)
92
93 #define iris_emit_cmd(batch, cmd, name) \
94 _iris_pack_command(batch, cmd, get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
95
96 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
97 do { \
98 uint32_t *dw = get_command_space(batch, 4 * num_dwords); \
99 for (uint32_t i = 0; i < num_dwords; i++) \
100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
102 } while (0)
103
104 #define iris_emit_with_addr(batch, dwords, num_dw, addr_field, addr) \
105 do { \
106 STATIC_ASSERT((GENX(addr_field) % 64) == 0); \
107 assert(num_dw <= ARRAY_SIZE(dwords)); \
108 int addr_idx = GENX(addr_field) / 32; \
109 uint32_t *dw = get_command_space(batch, 4 * num_dw); \
110 for (uint32_t i = 0; i < addr_idx; i++) { \
111 dw[i] = (dwords)[i]; \
112 } \
113 uint64_t *qw = (uint64_t *) &dw[addr_idx]; \
114 qw = iris_batch_reloc(batch, qw - batch->cmdbuf.map, addr.bo, \
115 addr.offset + (dwords)[addr_idx + 1], \
116 addr.reloc_flags); \
117 for (uint32_t i = addr_idx + 1; i < num_dw; i++) { \
118 dw[i] = (dwords)[i]; \
119 } \
120 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dw * 4)); \
121 } while (0)
122
123 #include "genxml/genX_pack.h"
124 #include "genxml/gen_macros.h"
125 #include "genxml/genX_bits.h"
126
127 #define MOCS_WB (2 << 1)
128
129 UNUSED static void pipe_asserts()
130 {
131 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
132
133 /* pipe_logicop happens to match the hardware. */
134 PIPE_ASSERT(PIPE_LOGICOP_CLEAR == LOGICOP_CLEAR);
135 PIPE_ASSERT(PIPE_LOGICOP_NOR == LOGICOP_NOR);
136 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED == LOGICOP_AND_INVERTED);
137 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED == LOGICOP_COPY_INVERTED);
138 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE == LOGICOP_AND_REVERSE);
139 PIPE_ASSERT(PIPE_LOGICOP_INVERT == LOGICOP_INVERT);
140 PIPE_ASSERT(PIPE_LOGICOP_XOR == LOGICOP_XOR);
141 PIPE_ASSERT(PIPE_LOGICOP_NAND == LOGICOP_NAND);
142 PIPE_ASSERT(PIPE_LOGICOP_AND == LOGICOP_AND);
143 PIPE_ASSERT(PIPE_LOGICOP_EQUIV == LOGICOP_EQUIV);
144 PIPE_ASSERT(PIPE_LOGICOP_NOOP == LOGICOP_NOOP);
145 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED == LOGICOP_OR_INVERTED);
146 PIPE_ASSERT(PIPE_LOGICOP_COPY == LOGICOP_COPY);
147 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE == LOGICOP_OR_REVERSE);
148 PIPE_ASSERT(PIPE_LOGICOP_OR == LOGICOP_OR);
149 PIPE_ASSERT(PIPE_LOGICOP_SET == LOGICOP_SET);
150
151 /* pipe_blend_func happens to match the hardware. */
152 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE == BLENDFACTOR_ONE);
153 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR == BLENDFACTOR_SRC_COLOR);
154 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA == BLENDFACTOR_SRC_ALPHA);
155 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA == BLENDFACTOR_DST_ALPHA);
156 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR == BLENDFACTOR_DST_COLOR);
157 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE == BLENDFACTOR_SRC_ALPHA_SATURATE);
158 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR == BLENDFACTOR_CONST_COLOR);
159 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA == BLENDFACTOR_CONST_ALPHA);
160 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR == BLENDFACTOR_SRC1_COLOR);
161 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA == BLENDFACTOR_SRC1_ALPHA);
162 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO == BLENDFACTOR_ZERO);
163 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR == BLENDFACTOR_INV_SRC_COLOR);
164 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA == BLENDFACTOR_INV_SRC_ALPHA);
165 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA == BLENDFACTOR_INV_DST_ALPHA);
166 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR == BLENDFACTOR_INV_DST_COLOR);
167 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR == BLENDFACTOR_INV_CONST_COLOR);
168 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA == BLENDFACTOR_INV_CONST_ALPHA);
169 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR == BLENDFACTOR_INV_SRC1_COLOR);
170 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA == BLENDFACTOR_INV_SRC1_ALPHA);
171
172 /* pipe_blend_func happens to match the hardware. */
173 PIPE_ASSERT(PIPE_BLEND_ADD == BLENDFUNCTION_ADD);
174 PIPE_ASSERT(PIPE_BLEND_SUBTRACT == BLENDFUNCTION_SUBTRACT);
175 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT == BLENDFUNCTION_REVERSE_SUBTRACT);
176 PIPE_ASSERT(PIPE_BLEND_MIN == BLENDFUNCTION_MIN);
177 PIPE_ASSERT(PIPE_BLEND_MAX == BLENDFUNCTION_MAX);
178
179 /* pipe_stencil_op happens to match the hardware. */
180 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP == STENCILOP_KEEP);
181 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO == STENCILOP_ZERO);
182 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE == STENCILOP_REPLACE);
183 PIPE_ASSERT(PIPE_STENCIL_OP_INCR == STENCILOP_INCRSAT);
184 PIPE_ASSERT(PIPE_STENCIL_OP_DECR == STENCILOP_DECRSAT);
185 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP == STENCILOP_INCR);
186 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP == STENCILOP_DECR);
187 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT == STENCILOP_INVERT);
188 #undef PIPE_ASSERT
189 }
190
191 static unsigned
192 translate_prim_type(enum pipe_prim_type prim, uint8_t verts_per_patch)
193 {
194 static const unsigned map[] = {
195 [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST,
196 [PIPE_PRIM_LINES] = _3DPRIM_LINELIST,
197 [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP,
198 [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP,
199 [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST,
200 [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
201 [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
202 [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST,
203 [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP,
204 [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON,
205 [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
206 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
207 [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
208 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
209 [PIPE_PRIM_PATCHES] = _3DPRIM_PATCHLIST_1 - 1,
210 };
211
212 return map[prim] + (prim == PIPE_PRIM_PATCHES ? verts_per_patch : 0);
213 }
214
215 static unsigned
216 translate_compare_func(enum pipe_compare_func pipe_func)
217 {
218 static const unsigned map[] = {
219 [PIPE_FUNC_NEVER] = COMPAREFUNCTION_NEVER,
220 [PIPE_FUNC_LESS] = COMPAREFUNCTION_LESS,
221 [PIPE_FUNC_EQUAL] = COMPAREFUNCTION_EQUAL,
222 [PIPE_FUNC_LEQUAL] = COMPAREFUNCTION_LEQUAL,
223 [PIPE_FUNC_GREATER] = COMPAREFUNCTION_GREATER,
224 [PIPE_FUNC_NOTEQUAL] = COMPAREFUNCTION_NOTEQUAL,
225 [PIPE_FUNC_GEQUAL] = COMPAREFUNCTION_GEQUAL,
226 [PIPE_FUNC_ALWAYS] = COMPAREFUNCTION_ALWAYS,
227 };
228 return map[pipe_func];
229 }
230
231 static unsigned
232 translate_shadow_func(enum pipe_compare_func pipe_func)
233 {
234 /* Gallium specifies the result of shadow comparisons as:
235 *
236 * 1 if ref <op> texel,
237 * 0 otherwise.
238 *
239 * The hardware does:
240 *
241 * 0 if texel <op> ref,
242 * 1 otherwise.
243 *
244 * So we need to flip the operator and also negate.
245 */
246 static const unsigned map[] = {
247 [PIPE_FUNC_NEVER] = PREFILTEROPALWAYS,
248 [PIPE_FUNC_LESS] = PREFILTEROPLEQUAL,
249 [PIPE_FUNC_EQUAL] = PREFILTEROPNOTEQUAL,
250 [PIPE_FUNC_LEQUAL] = PREFILTEROPLESS,
251 [PIPE_FUNC_GREATER] = PREFILTEROPGEQUAL,
252 [PIPE_FUNC_NOTEQUAL] = PREFILTEROPEQUAL,
253 [PIPE_FUNC_GEQUAL] = PREFILTEROPGREATER,
254 [PIPE_FUNC_ALWAYS] = PREFILTEROPNEVER,
255 };
256 return map[pipe_func];
257 }
258
259 static unsigned
260 translate_cull_mode(unsigned pipe_face)
261 {
262 static const unsigned map[4] = {
263 [PIPE_FACE_NONE] = CULLMODE_NONE,
264 [PIPE_FACE_FRONT] = CULLMODE_FRONT,
265 [PIPE_FACE_BACK] = CULLMODE_BACK,
266 [PIPE_FACE_FRONT_AND_BACK] = CULLMODE_BOTH,
267 };
268 return map[pipe_face];
269 }
270
271 static unsigned
272 translate_fill_mode(unsigned pipe_polymode)
273 {
274 static const unsigned map[4] = {
275 [PIPE_POLYGON_MODE_FILL] = FILL_MODE_SOLID,
276 [PIPE_POLYGON_MODE_LINE] = FILL_MODE_WIREFRAME,
277 [PIPE_POLYGON_MODE_POINT] = FILL_MODE_POINT,
278 [PIPE_POLYGON_MODE_FILL_RECTANGLE] = FILL_MODE_SOLID,
279 };
280 return map[pipe_polymode];
281 }
282
283 static struct iris_address
284 ro_bo(struct iris_bo *bo, uint32_t offset)
285 {
286 return (struct iris_address) { .bo = bo, .offset = offset };
287 }
288
289 static void
290 iris_emit_state_base_address(struct iris_batch *batch)
291 {
292 /* XXX: PIPE_CONTROLs */
293
294 iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
295 #if 0
296 // XXX: MOCS is stupid for this.
297 sba.GeneralStateMemoryObjectControlState = MOCS_WB;
298 sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
299 sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
300 sba.DynamicStateMemoryObjectControlState = MOCS_WB;
301 sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
302 sba.InstructionMemoryObjectControlState = MOCS_WB;
303 sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
304 #endif
305
306 sba.GeneralStateBaseAddressModifyEnable = true;
307 sba.SurfaceStateBaseAddressModifyEnable = true;
308 sba.DynamicStateBaseAddressModifyEnable = true;
309 sba.IndirectObjectBaseAddressModifyEnable = true;
310 sba.InstructionBaseAddressModifyEnable = true;
311 sba.GeneralStateBufferSizeModifyEnable = true;
312 sba.DynamicStateBufferSizeModifyEnable = true;
313 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
314 sba.IndirectObjectBufferSizeModifyEnable = true;
315 sba.InstructionBuffersizeModifyEnable = true;
316
317 sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
318 sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
319
320 sba.GeneralStateBufferSize = 0xfffff;
321 sba.IndirectObjectBufferSize = 0xfffff;
322 sba.InstructionBufferSize = 0xfffff;
323 sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
324 }
325 }
326
327 static void
328 iris_init_render_context(struct iris_screen *screen,
329 struct iris_batch *batch,
330 struct pipe_debug_callback *dbg)
331 {
332 batch->emit_state_base_address = iris_emit_state_base_address;
333 iris_init_batch(batch, screen, dbg, I915_EXEC_RENDER);
334
335 iris_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
336 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
337 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
338 }
339 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
340 GEN_SAMPLE_POS_1X(pat._1xSample);
341 GEN_SAMPLE_POS_2X(pat._2xSample);
342 GEN_SAMPLE_POS_4X(pat._4xSample);
343 GEN_SAMPLE_POS_8X(pat._8xSample);
344 GEN_SAMPLE_POS_16X(pat._16xSample);
345 }
346 iris_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
347 iris_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
348 iris_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
349 /* XXX: may need to set an offset for origin-UL framebuffers */
350 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
351
352 /* Just assign a static partitioning. */
353 for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
354 iris_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
355 alloc._3DCommandSubOpcode = 18 + i;
356 alloc.ConstantBufferOffset = 6 * i;
357 alloc.ConstantBufferSize = i == MESA_SHADER_FRAGMENT ? 8 : 6;
358 }
359 }
360 }
361
362 static void
363 iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
364 {
365 }
366
367 static void
368 iris_set_blend_color(struct pipe_context *ctx,
369 const struct pipe_blend_color *state)
370 {
371 struct iris_context *ice = (struct iris_context *) ctx;
372
373 memcpy(&ice->state.blend_color, state, sizeof(struct pipe_blend_color));
374 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
375 }
376
377 struct iris_blend_state {
378 uint32_t ps_blend[GENX(3DSTATE_PS_BLEND_length)];
379 uint32_t blend_state[GENX(BLEND_STATE_length)];
380 uint32_t blend_entries[BRW_MAX_DRAW_BUFFERS *
381 GENX(BLEND_STATE_ENTRY_length)];
382 };
383
384 static void *
385 iris_create_blend_state(struct pipe_context *ctx,
386 const struct pipe_blend_state *state)
387 {
388 struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
389
390 iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) {
391 bs.AlphaToCoverageEnable = state->alpha_to_coverage;
392 bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
393 bs.AlphaToOneEnable = state->alpha_to_one;
394 bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
395 bs.ColorDitherEnable = state->dither;
396 //bs.AlphaTestEnable = <comes from alpha state> :(
397 //bs.AlphaTestFunction = <comes from alpha state> :(
398 }
399
400 iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
401 //pb.HasWriteableRT = <comes from somewhere> :(
402 //pb.AlphaTestEnable = <comes from alpha state> :(
403 pb.AlphaToCoverageEnable = state->alpha_to_coverage;
404 pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
405
406 pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
407
408 pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
409 pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
410 pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
411 pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
412 }
413
414 for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
415 iris_pack_state(GENX(BLEND_STATE_ENTRY), &cso->blend_entries[i], be) {
416 be.LogicOpEnable = state->logicop_enable;
417 be.LogicOpFunction = state->logicop_func;
418
419 be.PreBlendSourceOnlyClampEnable = false;
420 be.ColorClampRange = COLORCLAMP_RTFORMAT;
421 be.PreBlendColorClampEnable = true;
422 be.PostBlendColorClampEnable = true;
423
424 be.ColorBufferBlendEnable = state->rt[i].blend_enable;
425
426 be.ColorBlendFunction = state->rt[i].rgb_func;
427 be.AlphaBlendFunction = state->rt[i].alpha_func;
428 be.SourceBlendFactor = state->rt[i].rgb_src_factor;
429 be.SourceAlphaBlendFactor = state->rt[i].alpha_func;
430 be.DestinationBlendFactor = state->rt[i].rgb_dst_factor;
431 be.DestinationAlphaBlendFactor = state->rt[i].alpha_dst_factor;
432
433 be.WriteDisableRed = state->rt[i].colormask & PIPE_MASK_R;
434 be.WriteDisableGreen = state->rt[i].colormask & PIPE_MASK_G;
435 be.WriteDisableBlue = state->rt[i].colormask & PIPE_MASK_B;
436 be.WriteDisableAlpha = state->rt[i].colormask & PIPE_MASK_A;
437 }
438 }
439
440 return cso;
441 }
442
443 static void
444 iris_bind_blend_state(struct pipe_context *ctx, void *state)
445 {
446 struct iris_context *ice = (struct iris_context *) ctx;
447 ice->state.cso_blend = state;
448 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
449 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
450 }
451
452 struct iris_depth_stencil_alpha_state {
453 uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
454 uint32_t cc_vp[GENX(CC_VIEWPORT_length)];
455
456 struct pipe_alpha_state alpha; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
457 };
458
459 static void *
460 iris_create_zsa_state(struct pipe_context *ctx,
461 const struct pipe_depth_stencil_alpha_state *state)
462 {
463 struct iris_depth_stencil_alpha_state *cso =
464 malloc(sizeof(struct iris_depth_stencil_alpha_state));
465
466 cso->alpha = state->alpha;
467
468 bool two_sided_stencil = state->stencil[1].enabled;
469
470 /* The state tracker needs to optimize away EQUAL writes for us. */
471 assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
472
473 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
474 wmds.StencilFailOp = state->stencil[0].fail_op;
475 wmds.StencilPassDepthFailOp = state->stencil[0].zfail_op;
476 wmds.StencilPassDepthPassOp = state->stencil[0].zpass_op;
477 wmds.StencilTestFunction =
478 translate_compare_func(state->stencil[0].func);
479 wmds.BackfaceStencilFailOp = state->stencil[1].fail_op;
480 wmds.BackfaceStencilPassDepthFailOp = state->stencil[1].zfail_op;
481 wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
482 wmds.BackfaceStencilTestFunction =
483 translate_compare_func(state->stencil[1].func);
484 wmds.DepthTestFunction = translate_compare_func(state->depth.func);
485 wmds.DoubleSidedStencilEnable = two_sided_stencil;
486 wmds.StencilTestEnable = state->stencil[0].enabled;
487 wmds.StencilBufferWriteEnable =
488 state->stencil[0].writemask != 0 ||
489 (two_sided_stencil && state->stencil[1].writemask != 0);
490 wmds.DepthTestEnable = state->depth.enabled;
491 wmds.DepthBufferWriteEnable = state->depth.writemask;
492 wmds.StencilTestMask = state->stencil[0].valuemask;
493 wmds.StencilWriteMask = state->stencil[0].writemask;
494 wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
495 wmds.BackfaceStencilWriteMask = state->stencil[1].writemask;
496 /* wmds.[Backface]StencilReferenceValue are merged later */
497 }
498
499 iris_pack_state(GENX(CC_VIEWPORT), cso->cc_vp, ccvp) {
500 ccvp.MinimumDepth = state->depth.bounds_min;
501 ccvp.MaximumDepth = state->depth.bounds_max;
502 }
503
504 return cso;
505 }
506
507 static void
508 iris_bind_zsa_state(struct pipe_context *ctx, void *state)
509 {
510 struct iris_context *ice = (struct iris_context *) ctx;
511 struct iris_depth_stencil_alpha_state *old_cso = ice->state.cso_zsa;
512 struct iris_depth_stencil_alpha_state *new_cso = state;
513
514 if (new_cso) {
515 if (!old_cso || old_cso->alpha.ref_value != new_cso->alpha.ref_value) {
516 ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE;
517 }
518 }
519
520 ice->state.cso_zsa = new_cso;
521 ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
522 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
523 }
524
525 struct iris_rasterizer_state {
526 uint32_t sf[GENX(3DSTATE_SF_length)];
527 uint32_t clip[GENX(3DSTATE_CLIP_length)];
528 uint32_t raster[GENX(3DSTATE_RASTER_length)];
529 uint32_t wm[GENX(3DSTATE_WM_length)];
530 uint32_t line_stipple[GENX(3DSTATE_LINE_STIPPLE_length)];
531
532 bool flatshade; /* for shader state */
533 bool light_twoside; /* for shader state */
534 bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
535 bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
536 enum pipe_sprite_coord_mode sprite_coord_mode; /* PIPE_SPRITE_* */
537 };
538
539 static void *
540 iris_create_rasterizer_state(struct pipe_context *ctx,
541 const struct pipe_rasterizer_state *state)
542 {
543 struct iris_rasterizer_state *cso =
544 malloc(sizeof(struct iris_rasterizer_state));
545
546 #if 0
547 sprite_coord_mode -> SBE PointSpriteTextureCoordinateOrigin
548 sprite_coord_enable -> SBE PointSpriteTextureCoordinateEnable
549 point_quad_rasterization -> SBE?
550
551 not necessary?
552 {
553 poly_smooth
554 force_persample_interp - ?
555 bottom_edge_rule
556
557 offset_units_unscaled - cap not exposed
558 }
559 #endif
560
561 cso->flatshade = state->flatshade;
562 cso->light_twoside = state->light_twoside;
563 cso->rasterizer_discard = state->rasterizer_discard;
564 cso->half_pixel_center = state->half_pixel_center;
565
566 iris_pack_command(GENX(3DSTATE_SF), cso->sf, sf) {
567 sf.StatisticsEnable = true;
568 sf.ViewportTransformEnable = true;
569 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
570 sf.LineEndCapAntialiasingRegionWidth =
571 state->line_smooth ? _10pixels : _05pixels;
572 sf.LastPixelEnable = state->line_last_pixel;
573 sf.LineWidth = state->line_width;
574 sf.SmoothPointEnable = state->point_smooth;
575 sf.PointWidthSource = state->point_size_per_vertex ? Vertex : State;
576 sf.PointWidth = state->point_size;
577
578 if (state->flatshade_first) {
579 sf.TriangleStripListProvokingVertexSelect = 2;
580 sf.TriangleFanProvokingVertexSelect = 2;
581 sf.LineStripListProvokingVertexSelect = 1;
582 } else {
583 sf.TriangleFanProvokingVertexSelect = 1;
584 }
585 }
586
587 /* COMPLETE! */
588 iris_pack_command(GENX(3DSTATE_RASTER), cso->raster, rr) {
589 rr.FrontWinding = state->front_ccw ? CounterClockwise : Clockwise;
590 rr.CullMode = translate_cull_mode(state->cull_face);
591 rr.FrontFaceFillMode = translate_fill_mode(state->fill_front);
592 rr.BackFaceFillMode = translate_fill_mode(state->fill_back);
593 rr.DXMultisampleRasterizationEnable = state->multisample;
594 rr.GlobalDepthOffsetEnableSolid = state->offset_tri;
595 rr.GlobalDepthOffsetEnableWireframe = state->offset_line;
596 rr.GlobalDepthOffsetEnablePoint = state->offset_point;
597 rr.GlobalDepthOffsetConstant = state->offset_units;
598 rr.GlobalDepthOffsetScale = state->offset_scale;
599 rr.GlobalDepthOffsetClamp = state->offset_clamp;
600 rr.SmoothPointEnable = state->point_smooth;
601 rr.AntialiasingEnable = state->line_smooth;
602 rr.ScissorRectangleEnable = state->scissor;
603 rr.ViewportZNearClipTestEnable = state->depth_clip_near;
604 rr.ViewportZFarClipTestEnable = state->depth_clip_far;
605 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
606 }
607
608 iris_pack_command(GENX(3DSTATE_CLIP), cso->clip, cl) {
609 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
610 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
611 */
612 cl.StatisticsEnable = true;
613 cl.EarlyCullEnable = true;
614 cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
615 cl.ForceUserClipDistanceClipTestEnableBitmask = true;
616 cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
617 cl.GuardbandClipTestEnable = true;
618 cl.ClipMode = CLIPMODE_NORMAL;
619 cl.ClipEnable = true;
620 cl.ViewportXYClipTestEnable = state->point_tri_clip;
621 cl.MinimumPointWidth = 0.125;
622 cl.MaximumPointWidth = 255.875;
623
624 if (state->flatshade_first) {
625 cl.TriangleStripListProvokingVertexSelect = 2;
626 cl.TriangleFanProvokingVertexSelect = 2;
627 cl.LineStripListProvokingVertexSelect = 1;
628 } else {
629 cl.TriangleFanProvokingVertexSelect = 1;
630 }
631 }
632
633 iris_pack_command(GENX(3DSTATE_WM), cso->wm, wm) {
634 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
635 * filled in at draw time from the FS program.
636 */
637 wm.LineAntialiasingRegionWidth = _10pixels;
638 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
639 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
640 wm.StatisticsEnable = true;
641 wm.LineStippleEnable = state->line_stipple_enable;
642 wm.PolygonStippleEnable = state->poly_stipple_enable;
643 }
644
645 /* Remap from 0..255 back to 1..256 */
646 const unsigned line_stipple_factor = state->line_stipple_factor + 1;
647
648 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE), cso->line_stipple, line) {
649 line.LineStipplePattern = state->line_stipple_pattern;
650 line.LineStippleInverseRepeatCount = 1.0f / line_stipple_factor;
651 line.LineStippleRepeatCount = line_stipple_factor;
652 }
653
654 return cso;
655 }
656
657 static void
658 iris_bind_rasterizer_state(struct pipe_context *ctx, void *state)
659 {
660 struct iris_context *ice = (struct iris_context *) ctx;
661 struct iris_rasterizer_state *old_cso = ice->state.cso_rast;
662 struct iris_rasterizer_state *new_cso = state;
663
664 if (new_cso) {
665 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
666 if (!old_cso || memcmp(old_cso->line_stipple, new_cso->line_stipple,
667 sizeof(old_cso->line_stipple)) != 0) {
668 ice->state.dirty |= IRIS_DIRTY_LINE_STIPPLE;
669 }
670
671 if (!old_cso ||
672 old_cso->half_pixel_center != new_cso->half_pixel_center) {
673 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
674 }
675 }
676
677 ice->state.cso_rast = new_cso;
678 ice->state.dirty |= IRIS_DIRTY_RASTER;
679 }
680
681 static uint32_t
682 translate_wrap(unsigned pipe_wrap)
683 {
684 static const unsigned map[] = {
685 [PIPE_TEX_WRAP_REPEAT] = TCM_WRAP,
686 [PIPE_TEX_WRAP_CLAMP] = TCM_HALF_BORDER,
687 [PIPE_TEX_WRAP_CLAMP_TO_EDGE] = TCM_CLAMP,
688 [PIPE_TEX_WRAP_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
689 [PIPE_TEX_WRAP_MIRROR_REPEAT] = TCM_MIRROR,
690 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
691 [PIPE_TEX_WRAP_MIRROR_CLAMP] = -1, // XXX: ???
692 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER] = -1, // XXX: ???
693 };
694 return map[pipe_wrap];
695 }
696
697 /**
698 * Return true if the given wrap mode requires the border color to exist.
699 */
700 static bool
701 wrap_mode_needs_border_color(unsigned wrap_mode)
702 {
703 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER;
704 }
705
706 static unsigned
707 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip)
708 {
709 static const unsigned map[] = {
710 [PIPE_TEX_MIPFILTER_NEAREST] = MIPFILTER_NEAREST,
711 [PIPE_TEX_MIPFILTER_LINEAR] = MIPFILTER_LINEAR,
712 [PIPE_TEX_MIPFILTER_NONE] = MIPFILTER_NONE,
713 };
714 return map[pipe_mip];
715 }
716
717 struct iris_sampler_state {
718 struct pipe_sampler_state base;
719
720 bool needs_border_color;
721
722 uint32_t sampler_state[GENX(SAMPLER_STATE_length)];
723 };
724
725 static void *
726 iris_create_sampler_state(struct pipe_context *pctx,
727 const struct pipe_sampler_state *state)
728 {
729 struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
730
731 if (!cso)
732 return NULL;
733
734 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST == MAPFILTER_NEAREST);
735 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR == MAPFILTER_LINEAR);
736
737 unsigned wrap_s = translate_wrap(state->wrap_s);
738 unsigned wrap_t = translate_wrap(state->wrap_t);
739 unsigned wrap_r = translate_wrap(state->wrap_r);
740
741 cso->needs_border_color = wrap_mode_needs_border_color(wrap_s) ||
742 wrap_mode_needs_border_color(wrap_t) ||
743 wrap_mode_needs_border_color(wrap_r);
744
745 iris_pack_state(GENX(SAMPLER_STATE), cso->sampler_state, samp) {
746 samp.TCXAddressControlMode = wrap_s;
747 samp.TCYAddressControlMode = wrap_t;
748 samp.TCZAddressControlMode = wrap_r;
749 samp.CubeSurfaceControlMode = state->seamless_cube_map;
750 samp.NonnormalizedCoordinateEnable = !state->normalized_coords;
751 samp.MinModeFilter = state->min_img_filter;
752 samp.MagModeFilter = state->mag_img_filter;
753 samp.MipModeFilter = translate_mip_filter(state->min_mip_filter);
754 samp.MaximumAnisotropy = RATIO21;
755
756 if (state->max_anisotropy >= 2) {
757 if (state->min_img_filter == PIPE_TEX_FILTER_LINEAR) {
758 samp.MinModeFilter = MAPFILTER_ANISOTROPIC;
759 samp.AnisotropicAlgorithm = EWAApproximation;
760 }
761
762 if (state->mag_img_filter == PIPE_TEX_FILTER_LINEAR)
763 samp.MagModeFilter = MAPFILTER_ANISOTROPIC;
764
765 samp.MaximumAnisotropy =
766 MIN2((state->max_anisotropy - 2) / 2, RATIO161);
767 }
768
769 /* Set address rounding bits if not using nearest filtering. */
770 if (state->min_img_filter != PIPE_TEX_FILTER_NEAREST) {
771 samp.UAddressMinFilterRoundingEnable = true;
772 samp.VAddressMinFilterRoundingEnable = true;
773 samp.RAddressMinFilterRoundingEnable = true;
774 }
775
776 if (state->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
777 samp.UAddressMagFilterRoundingEnable = true;
778 samp.VAddressMagFilterRoundingEnable = true;
779 samp.RAddressMagFilterRoundingEnable = true;
780 }
781
782 if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
783 samp.ShadowFunction = translate_shadow_func(state->compare_func);
784
785 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
786
787 samp.LODPreClampMode = CLAMP_MODE_OGL;
788 samp.MinLOD = CLAMP(state->min_lod, 0, hw_max_lod);
789 samp.MaxLOD = CLAMP(state->max_lod, 0, hw_max_lod);
790 samp.TextureLODBias = CLAMP(state->lod_bias, -16, 15);
791
792 //samp.BorderColorPointer = <<comes from elsewhere>>
793 }
794
795 return cso;
796 }
797
798 static void
799 iris_bind_sampler_states(struct pipe_context *ctx,
800 enum pipe_shader_type p_stage,
801 unsigned start, unsigned count,
802 void **states)
803 {
804 struct iris_context *ice = (struct iris_context *) ctx;
805 gl_shader_stage stage = stage_from_pipe(p_stage);
806
807 assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
808
809 for (int i = 0; i < count; i++) {
810 ice->state.samplers[stage][start + i] = states[i];
811 }
812
813 ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
814 }
815
816 struct iris_sampler_view {
817 struct pipe_sampler_view pipe;
818 struct isl_view view;
819 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
820 };
821
822 /**
823 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
824 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
825 *
826 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
827 * 0 1 2 3 4 5
828 * 4 5 6 7 0 1
829 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
830 *
831 * which is simply adding 4 then modding by 8 (or anding with 7).
832 *
833 * We then may need to apply workarounds for textureGather hardware bugs.
834 */
835 static enum isl_channel_select
836 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle)
837 {
838 return (swizzle + 4) & 7;
839 }
840
841 static struct pipe_sampler_view *
842 iris_create_sampler_view(struct pipe_context *ctx,
843 struct pipe_resource *tex,
844 const struct pipe_sampler_view *tmpl)
845 {
846 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
847 struct iris_resource *itex = (struct iris_resource *) tex;
848 struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
849
850 if (!isv)
851 return NULL;
852
853 /* initialize base object */
854 isv->pipe = *tmpl;
855 isv->pipe.context = ctx;
856 isv->pipe.texture = NULL;
857 pipe_reference_init(&isv->pipe.reference, 1);
858 pipe_resource_reference(&isv->pipe.texture, tex);
859
860 /* XXX: do we need brw_get_texture_swizzle hacks here? */
861
862 isv->view = (struct isl_view) {
863 .format = iris_isl_format_for_pipe_format(tmpl->format),
864 .base_level = tmpl->u.tex.first_level,
865 .levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1,
866 .base_array_layer = tmpl->u.tex.first_layer,
867 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
868 .swizzle = (struct isl_swizzle) {
869 .r = pipe_swizzle_to_isl_channel(tmpl->swizzle_r),
870 .g = pipe_swizzle_to_isl_channel(tmpl->swizzle_g),
871 .b = pipe_swizzle_to_isl_channel(tmpl->swizzle_b),
872 .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
873 },
874 .usage = ISL_SURF_USAGE_TEXTURE_BIT,
875 };
876
877 isl_surf_fill_state(&screen->isl_dev, isv->surface_state,
878 .surf = &itex->surf, .view = &isv->view,
879 .mocs = MOCS_WB);
880 // .address = ...
881 // .aux_surf =
882 // .clear_color = clear_color,
883
884 return &isv->pipe;
885 }
886
887 struct iris_surface {
888 struct pipe_surface pipe;
889 struct isl_view view;
890 uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
891 };
892
893 static struct pipe_surface *
894 iris_create_surface(struct pipe_context *ctx,
895 struct pipe_resource *tex,
896 const struct pipe_surface *tmpl)
897 {
898 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
899 struct iris_surface *surf = calloc(1, sizeof(struct iris_surface));
900 struct pipe_surface *psurf = &surf->pipe;
901 struct iris_resource *itex = (struct iris_resource *) tex;
902
903 if (!surf)
904 return NULL;
905
906 pipe_reference_init(&psurf->reference, 1);
907 pipe_resource_reference(&psurf->texture, tex);
908 psurf->context = ctx;
909 psurf->format = tmpl->format;
910 psurf->width = tex->width0;
911 psurf->height = tex->height0;
912 psurf->texture = tex;
913 psurf->u.tex.first_layer = tmpl->u.tex.first_layer;
914 psurf->u.tex.last_layer = tmpl->u.tex.last_layer;
915 psurf->u.tex.level = tmpl->u.tex.level;
916
917 surf->view = (struct isl_view) {
918 .format = iris_isl_format_for_pipe_format(tmpl->format),
919 .base_level = tmpl->u.tex.level,
920 .levels = 1,
921 .base_array_layer = tmpl->u.tex.first_layer,
922 .array_len = tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1,
923 .swizzle = ISL_SWIZZLE_IDENTITY,
924 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
925 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT,
926 };
927
928 isl_surf_fill_state(&screen->isl_dev, surf->surface_state,
929 .surf = &itex->surf, .view = &surf->view,
930 .mocs = MOCS_WB);
931 // .address = ...
932 // .aux_surf =
933 // .clear_color = clear_color,
934
935 return psurf;
936 }
937
938 static void
939 iris_set_sampler_views(struct pipe_context *ctx,
940 enum pipe_shader_type shader,
941 unsigned start, unsigned count,
942 struct pipe_sampler_view **views)
943 {
944 }
945
946 static void
947 iris_set_clip_state(struct pipe_context *ctx,
948 const struct pipe_clip_state *state)
949 {
950 }
951
952 static void
953 iris_set_polygon_stipple(struct pipe_context *ctx,
954 const struct pipe_poly_stipple *state)
955 {
956 struct iris_context *ice = (struct iris_context *) ctx;
957 memcpy(&ice->state.poly_stipple, state, sizeof(*state));
958 ice->state.dirty |= IRIS_DIRTY_POLYGON_STIPPLE;
959 }
960
961 static void
962 iris_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
963 {
964 struct iris_context *ice = (struct iris_context *) ctx;
965
966 ice->state.sample_mask = sample_mask;
967 ice->state.dirty |= IRIS_DIRTY_SAMPLE_MASK;
968 }
969
970 static void
971 iris_set_scissor_states(struct pipe_context *ctx,
972 unsigned start_slot,
973 unsigned num_scissors,
974 const struct pipe_scissor_state *states)
975 {
976 struct iris_context *ice = (struct iris_context *) ctx;
977
978 ice->state.num_scissors = num_scissors;
979
980 for (unsigned i = 0; i < num_scissors; i++) {
981 ice->state.scissors[start_slot + i] = states[i];
982 }
983
984 ice->state.dirty |= IRIS_DIRTY_SCISSOR_RECT;
985 }
986
987 static void
988 iris_set_stencil_ref(struct pipe_context *ctx,
989 const struct pipe_stencil_ref *state)
990 {
991 struct iris_context *ice = (struct iris_context *) ctx;
992 memcpy(&ice->state.stencil_ref, state, sizeof(*state));
993 ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL;
994 }
995
996
997 struct iris_viewport_state {
998 uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length)];
999 };
1000
1001 static float
1002 extent_from_matrix(const struct pipe_viewport_state *state, int axis)
1003 {
1004 return fabsf(state->scale[axis]) * state->translate[axis];
1005 }
1006
1007 #if 0
1008 static void
1009 calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
1010 float m00, float m11, float m30, float m31,
1011 float *xmin, float *xmax,
1012 float *ymin, float *ymax)
1013 {
1014 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1015 * Strips and Fans documentation:
1016 *
1017 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1018 * fixed-point "guardband" range supported by the rasterization hardware"
1019 *
1020 * and
1021 *
1022 * "In almost all circumstances, if an object’s vertices are actually
1023 * modified by this clamping (i.e., had X or Y coordinates outside of
1024 * the guardband extent the rendered object will not match the intended
1025 * result. Therefore software should take steps to ensure that this does
1026 * not happen - e.g., by clipping objects such that they do not exceed
1027 * these limits after the Drawing Rectangle is applied."
1028 *
1029 * I believe the fundamental restriction is that the rasterizer (in
1030 * the SF/WM stages) have a limit on the number of pixels that can be
1031 * rasterized. We need to ensure any coordinates beyond the rasterizer
1032 * limit are handled by the clipper. So effectively that limit becomes
1033 * the clipper's guardband size.
1034 *
1035 * It goes on to say:
1036 *
1037 * "In addition, in order to be correctly rendered, objects must have a
1038 * screenspace bounding box not exceeding 8K in the X or Y direction.
1039 * This additional restriction must also be comprehended by software,
1040 * i.e., enforced by use of clipping."
1041 *
1042 * This makes no sense. Gen7+ hardware supports 16K render targets,
1043 * and you definitely need to be able to draw polygons that fill the
1044 * surface. Our assumption is that the rasterizer was limited to 8K
1045 * on Sandybridge, which only supports 8K surfaces, and it was actually
1046 * increased to 16K on Ivybridge and later.
1047 *
1048 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1049 */
1050 const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f;
1051
1052 if (m00 != 0 && m11 != 0) {
1053 /* First, we compute the screen-space render area */
1054 const float ss_ra_xmin = MIN3( 0, m30 + m00, m30 - m00);
1055 const float ss_ra_xmax = MAX3( fb_width, m30 + m00, m30 - m00);
1056 const float ss_ra_ymin = MIN3( 0, m31 + m11, m31 - m11);
1057 const float ss_ra_ymax = MAX3(fb_height, m31 + m11, m31 - m11);
1058
1059 /* We want the guardband to be centered on that */
1060 const float ss_gb_xmin = (ss_ra_xmin + ss_ra_xmax) / 2 - gb_size;
1061 const float ss_gb_xmax = (ss_ra_xmin + ss_ra_xmax) / 2 + gb_size;
1062 const float ss_gb_ymin = (ss_ra_ymin + ss_ra_ymax) / 2 - gb_size;
1063 const float ss_gb_ymax = (ss_ra_ymin + ss_ra_ymax) / 2 + gb_size;
1064
1065 /* Now we need it in native device coordinates */
1066 const float ndc_gb_xmin = (ss_gb_xmin - m30) / m00;
1067 const float ndc_gb_xmax = (ss_gb_xmax - m30) / m00;
1068 const float ndc_gb_ymin = (ss_gb_ymin - m31) / m11;
1069 const float ndc_gb_ymax = (ss_gb_ymax - m31) / m11;
1070
1071 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1072 * flipped upside-down. X should be fine though.
1073 */
1074 assert(ndc_gb_xmin <= ndc_gb_xmax);
1075 *xmin = ndc_gb_xmin;
1076 *xmax = ndc_gb_xmax;
1077 *ymin = MIN2(ndc_gb_ymin, ndc_gb_ymax);
1078 *ymax = MAX2(ndc_gb_ymin, ndc_gb_ymax);
1079 } else {
1080 /* The viewport scales to 0, so nothing will be rendered. */
1081 *xmin = 0.0f;
1082 *xmax = 0.0f;
1083 *ymin = 0.0f;
1084 *ymax = 0.0f;
1085 }
1086 }
1087 #endif
1088
1089 static void
1090 iris_set_viewport_states(struct pipe_context *ctx,
1091 unsigned start_slot,
1092 unsigned num_viewports,
1093 const struct pipe_viewport_state *state)
1094 {
1095 struct iris_context *ice = (struct iris_context *) ctx;
1096 struct iris_viewport_state *cso =
1097 malloc(sizeof(struct iris_viewport_state));
1098
1099 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1100 for (unsigned i = start_slot; i < start_slot + num_viewports; i++) {
1101 float x_extent = extent_from_matrix(&state[i], 0);
1102 float y_extent = extent_from_matrix(&state[i], 1);
1103
1104 iris_pack_state(GENX(SF_CLIP_VIEWPORT), cso->sf_cl_vp, vp) {
1105 vp.ViewportMatrixElementm00 = state[i].scale[0];
1106 vp.ViewportMatrixElementm11 = state[i].scale[1];
1107 vp.ViewportMatrixElementm22 = state[i].scale[2];
1108 vp.ViewportMatrixElementm30 = state[i].translate[0];
1109 vp.ViewportMatrixElementm31 = state[i].translate[1];
1110 vp.ViewportMatrixElementm32 = state[i].translate[2];
1111 /* XXX: in i965 this is computed based on the drawbuffer size,
1112 * but we don't have that here...
1113 */
1114 vp.XMinClipGuardband = -1.0;
1115 vp.XMaxClipGuardband = 1.0;
1116 vp.YMinClipGuardband = -1.0;
1117 vp.YMaxClipGuardband = 1.0;
1118 vp.XMinViewPort = -x_extent;
1119 vp.XMaxViewPort = x_extent;
1120 vp.YMinViewPort = -y_extent;
1121 vp.YMaxViewPort = y_extent;
1122 }
1123 }
1124
1125 ice->state.cso_vp = cso;
1126 // XXX: start_slot
1127 ice->state.num_viewports = num_viewports;
1128 ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
1129 }
1130
1131 struct iris_depth_state
1132 {
1133 uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
1134 uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
1135 uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
1136 };
1137
1138 static void
1139 iris_set_framebuffer_state(struct pipe_context *ctx,
1140 const struct pipe_framebuffer_state *state)
1141 {
1142 struct iris_context *ice = (struct iris_context *) ctx;
1143 struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
1144
1145 if (cso->samples != state->samples) {
1146 ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
1147 }
1148
1149 cso->width = state->width;
1150 cso->height = state->height;
1151 cso->layers = state->layers;
1152 cso->samples = state->samples;
1153
1154 unsigned i;
1155 for (i = 0; i < state->nr_cbufs; i++)
1156 pipe_surface_reference(&cso->cbufs[i], state->cbufs[i]);
1157 for (; i < cso->nr_cbufs; i++)
1158 pipe_surface_reference(&cso->cbufs[i], NULL);
1159
1160 cso->nr_cbufs = state->nr_cbufs;
1161
1162 pipe_surface_reference(&cso->zsbuf, state->zsbuf);
1163
1164 struct isl_depth_stencil_hiz_emit_info info = {
1165 .mocs = MOCS_WB,
1166 };
1167
1168 // XXX: depth buffers
1169 }
1170
1171 static void
1172 iris_set_constant_buffer(struct pipe_context *ctx,
1173 enum pipe_shader_type shader, uint index,
1174 const struct pipe_constant_buffer *cb)
1175 {
1176 }
1177
1178
1179 static void
1180 iris_sampler_view_destroy(struct pipe_context *ctx,
1181 struct pipe_sampler_view *state)
1182 {
1183 pipe_resource_reference(&state->texture, NULL);
1184 free(state);
1185 }
1186
1187
1188 static void
1189 iris_surface_destroy(struct pipe_context *ctx, struct pipe_surface *surface)
1190 {
1191 pipe_resource_reference(&surface->texture, NULL);
1192 free(surface);
1193 }
1194
1195 static void
1196 iris_delete_state(struct pipe_context *ctx, void *state)
1197 {
1198 free(state);
1199 }
1200
1201 struct iris_vertex_buffer_state {
1202 uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
1203 struct iris_address bos[33];
1204 unsigned num_buffers;
1205 };
1206
1207 static void
1208 iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
1209 {
1210 if (cso) {
1211 for (unsigned i = 0; i < cso->num_buffers; i++)
1212 iris_bo_unreference(cso->bos[i].bo);
1213 free(cso);
1214 }
1215 }
1216
1217 static void
1218 iris_set_vertex_buffers(struct pipe_context *ctx,
1219 unsigned start_slot, unsigned count,
1220 const struct pipe_vertex_buffer *buffers)
1221 {
1222 struct iris_context *ice = (struct iris_context *) ctx;
1223 struct iris_vertex_buffer_state *cso =
1224 malloc(sizeof(struct iris_vertex_buffer_state));
1225
1226 /* If there are no buffers, do nothing. We can leave the stale
1227 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1228 * elements that point to them, it should be fine.
1229 */
1230 if (!buffers)
1231 return;
1232
1233 iris_free_vertex_buffers(ice->state.cso_vertex_buffers);
1234
1235 cso->num_buffers = count;
1236
1237 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
1238 vb.DWordLength = 4 * cso->num_buffers - 1;
1239 }
1240
1241 uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
1242
1243 for (unsigned i = 0; i < count; i++) {
1244 assert(!buffers[i].is_user_buffer);
1245
1246 struct iris_resource *res = (void *) buffers[i].buffer.resource;
1247 iris_bo_reference(res->bo);
1248 cso->bos[i] = ro_bo(res->bo, buffers[i].buffer_offset);
1249
1250 iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
1251 vb.VertexBufferIndex = start_slot + i;
1252 vb.MOCS = MOCS_WB;
1253 vb.AddressModifyEnable = true;
1254 vb.BufferPitch = buffers[i].stride;
1255 vb.BufferSize = res->bo->size;
1256 /* vb.BufferStartingAddress is filled in at draw time */
1257 }
1258
1259 vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
1260 }
1261
1262 ice->state.cso_vertex_buffers = cso;
1263 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
1264 }
1265
1266 struct iris_vertex_element_state {
1267 uint32_t vertex_elements[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length)];
1268 uint32_t vf_instancing[GENX(3DSTATE_VF_INSTANCING_length)][33];
1269 unsigned count;
1270 };
1271
1272 static void *
1273 iris_create_vertex_elements(struct pipe_context *ctx,
1274 unsigned count,
1275 const struct pipe_vertex_element *state)
1276 {
1277 struct iris_vertex_element_state *cso =
1278 malloc(sizeof(struct iris_vertex_element_state));
1279
1280 cso->count = count;
1281
1282 /* TODO:
1283 * - create edge flag one
1284 * - create SGV ones
1285 * - if those are necessary, use count + 1/2/3... OR in the length
1286 */
1287 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS), cso->vertex_elements, ve);
1288
1289 uint32_t *ve_pack_dest = &cso->vertex_elements[1];
1290
1291 for (int i = 0; i < count; i++) {
1292 iris_pack_state(GENX(VERTEX_ELEMENT_STATE), ve_pack_dest, ve) {
1293 ve.VertexBufferIndex = state[i].vertex_buffer_index;
1294 ve.Valid = true;
1295 ve.SourceElementOffset = state[i].src_offset;
1296 ve.SourceElementFormat =
1297 iris_isl_format_for_pipe_format(state[i].src_format);
1298 }
1299
1300 iris_pack_command(GENX(3DSTATE_VF_INSTANCING), cso->vf_instancing[i], vi) {
1301 vi.VertexElementIndex = i;
1302 vi.InstancingEnable = state[i].instance_divisor > 0;
1303 vi.InstanceDataStepRate = state[i].instance_divisor;
1304 }
1305
1306 ve_pack_dest += GENX(VERTEX_ELEMENT_STATE_length);
1307 }
1308
1309 return cso;
1310 }
1311
1312 static void
1313 iris_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
1314 {
1315 struct iris_context *ice = (struct iris_context *) ctx;
1316
1317 ice->state.cso_vertex_elements = state;
1318 ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
1319 }
1320
1321 static void *
1322 iris_create_compute_state(struct pipe_context *ctx,
1323 const struct pipe_compute_state *state)
1324 {
1325 return malloc(1);
1326 }
1327
1328 static struct pipe_stream_output_target *
1329 iris_create_stream_output_target(struct pipe_context *ctx,
1330 struct pipe_resource *res,
1331 unsigned buffer_offset,
1332 unsigned buffer_size)
1333 {
1334 struct pipe_stream_output_target *t =
1335 CALLOC_STRUCT(pipe_stream_output_target);
1336 if (!t)
1337 return NULL;
1338
1339 pipe_reference_init(&t->reference, 1);
1340 pipe_resource_reference(&t->buffer, res);
1341 t->buffer_offset = buffer_offset;
1342 t->buffer_size = buffer_size;
1343 return t;
1344 }
1345
1346 static void
1347 iris_stream_output_target_destroy(struct pipe_context *ctx,
1348 struct pipe_stream_output_target *t)
1349 {
1350 pipe_resource_reference(&t->buffer, NULL);
1351 free(t);
1352 }
1353
1354 static void
1355 iris_set_stream_output_targets(struct pipe_context *ctx,
1356 unsigned num_targets,
1357 struct pipe_stream_output_target **targets,
1358 const unsigned *offsets)
1359 {
1360 }
1361
1362 static void
1363 iris_bind_compute_state(struct pipe_context *ctx, void *state)
1364 {
1365 }
1366
1367 static void
1368 iris_populate_vs_key(const struct iris_context *ice,
1369 struct brw_vs_prog_key *key)
1370 {
1371 memset(key, 0, sizeof(*key));
1372 }
1373
1374 static void
1375 iris_populate_tcs_key(const struct iris_context *ice,
1376 struct brw_tcs_prog_key *key)
1377 {
1378 memset(key, 0, sizeof(*key));
1379 }
1380
1381 static void
1382 iris_populate_tes_key(const struct iris_context *ice,
1383 struct brw_tes_prog_key *key)
1384 {
1385 memset(key, 0, sizeof(*key));
1386 }
1387
1388 static void
1389 iris_populate_gs_key(const struct iris_context *ice,
1390 struct brw_gs_prog_key *key)
1391 {
1392 memset(key, 0, sizeof(*key));
1393 }
1394
1395 static void
1396 iris_populate_fs_key(const struct iris_context *ice,
1397 struct brw_wm_prog_key *key)
1398 {
1399 memset(key, 0, sizeof(*key));
1400
1401 /* XXX: dirty flags? */
1402 struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
1403 //struct iris_depth_stencil_alpha_state *zsa = ice->state.framebuffer;
1404 // XXX: can't access iris structs outside iris_state.c :(
1405 // XXX: maybe just move these to iris_state.c, honestly...they're more
1406 // about state than programs...
1407
1408 key->nr_color_regions = fb->nr_cbufs;
1409
1410 // key->force_dual_color_blend for unigine
1411 #if 0
1412 //key->replicate_alpha = fb->nr_cbufs > 1 && alpha test or alpha to coverage
1413 if (cso_rast->multisample) {
1414 key->persample_interp =
1415 ctx->Multisample.SampleShading &&
1416 (ctx->Multisample.MinSampleShadingValue *
1417 _mesa_geometric_samples(ctx->DrawBuffer) > 1);
1418
1419 key->multisample_fbo = fb->samples > 1;
1420 }
1421 #endif
1422
1423 key->coherent_fb_fetch = true;
1424 }
1425
1426 //pkt.SamplerCount = \
1427 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1428 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1429 //ffs(stage_state->per_thread_scratch) - 11; \
1430
1431 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1432 pkt.KernelStartPointer = shader->prog_offset; \
1433 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1434 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1435 \
1436 pkt.DispatchGRFStartRegisterForURBData = \
1437 prog_data->dispatch_grf_start_reg; \
1438 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1439 pkt.prefix##URBEntryReadOffset = 0; \
1440 \
1441 pkt.StatisticsEnable = true; \
1442 pkt.Enable = true;
1443
1444 static void
1445 iris_set_vs_state(const struct gen_device_info *devinfo,
1446 struct iris_compiled_shader *shader)
1447 {
1448 struct brw_stage_prog_data *prog_data = shader->prog_data;
1449 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1450
1451 iris_pack_command(GENX(3DSTATE_VS), shader->derived_data, vs) {
1452 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
1453 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
1454 vs.SIMD8DispatchEnable = true;
1455 vs.UserClipDistanceCullTestEnableBitmask =
1456 vue_prog_data->cull_distance_mask;
1457 }
1458 }
1459
1460 static void
1461 iris_set_tcs_state(const struct gen_device_info *devinfo,
1462 struct iris_compiled_shader *shader)
1463 {
1464 struct brw_stage_prog_data *prog_data = shader->prog_data;
1465 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1466 struct brw_tcs_prog_data *tcs_prog_data = (void *) prog_data;
1467
1468 iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
1469 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
1470
1471 hs.InstanceCount = tcs_prog_data->instances - 1;
1472 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1473 hs.IncludeVertexHandles = true;
1474 }
1475 }
1476
1477 static void
1478 iris_set_tes_state(const struct gen_device_info *devinfo,
1479 struct iris_compiled_shader *shader)
1480 {
1481 struct brw_stage_prog_data *prog_data = shader->prog_data;
1482 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1483 struct brw_tes_prog_data *tes_prog_data = (void *) prog_data;
1484
1485 uint32_t *te_state = (void *) shader->derived_data;
1486 uint32_t *ds_state = te_state + GENX(3DSTATE_TE_length);
1487
1488 iris_pack_command(GENX(3DSTATE_TE), te_state, te) {
1489 te.Partitioning = tes_prog_data->partitioning;
1490 te.OutputTopology = tes_prog_data->output_topology;
1491 te.TEDomain = tes_prog_data->domain;
1492 te.TEEnable = true;
1493 te.MaximumTessellationFactorOdd = 63.0;
1494 te.MaximumTessellationFactorNotOdd = 64.0;
1495 }
1496
1497 iris_pack_command(GENX(3DSTATE_DS), ds_state, ds) {
1498 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
1499
1500 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
1501 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1502 ds.ComputeWCoordinateEnable =
1503 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
1504
1505 ds.UserClipDistanceCullTestEnableBitmask =
1506 vue_prog_data->cull_distance_mask;
1507 }
1508
1509 }
1510
1511 static void
1512 iris_set_gs_state(const struct gen_device_info *devinfo,
1513 struct iris_compiled_shader *shader)
1514 {
1515 struct brw_stage_prog_data *prog_data = shader->prog_data;
1516 struct brw_vue_prog_data *vue_prog_data = (void *) prog_data;
1517 struct brw_gs_prog_data *gs_prog_data = (void *) prog_data;
1518
1519 iris_pack_command(GENX(3DSTATE_GS), shader->derived_data, gs) {
1520 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
1521
1522 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
1523 gs.OutputTopology = gs_prog_data->output_topology;
1524 gs.ControlDataHeaderSize =
1525 gs_prog_data->control_data_header_size_hwords;
1526 gs.InstanceControl = gs_prog_data->invocations - 1;
1527 gs.DispatchMode = SIMD8;
1528 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
1529 gs.ControlDataFormat = gs_prog_data->control_data_format;
1530 gs.ReorderMode = TRAILING;
1531 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
1532 gs.MaximumNumberofThreads =
1533 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
1534 : (devinfo->max_gs_threads - 1);
1535
1536 if (gs_prog_data->static_vertex_count != -1) {
1537 gs.StaticOutput = true;
1538 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
1539 }
1540 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
1541
1542 gs.UserClipDistanceCullTestEnableBitmask =
1543 vue_prog_data->cull_distance_mask;
1544
1545 const int urb_entry_write_offset = 1;
1546 const uint32_t urb_entry_output_length =
1547 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
1548 urb_entry_write_offset;
1549
1550 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
1551 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
1552 }
1553 }
1554
1555 static void
1556 iris_set_fs_state(const struct gen_device_info *devinfo,
1557 struct iris_compiled_shader *shader)
1558 {
1559 struct brw_stage_prog_data *prog_data = shader->prog_data;
1560 struct brw_wm_prog_data *wm_prog_data = (void *) shader->prog_data;
1561
1562 uint32_t *ps_state = (void *) shader->derived_data;
1563 uint32_t *psx_state = ps_state + GENX(3DSTATE_PS_length);
1564
1565 iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
1566 ps.VectorMaskEnable = true;
1567 //ps.SamplerCount = ...
1568 ps.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4;
1569 ps.FloatingPointMode = prog_data->use_alt_mode;
1570 ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
1571
1572 ps.PushConstantEnable = prog_data->nr_params > 0 ||
1573 prog_data->ubo_ranges[0].length > 0;
1574
1575 /* From the documentation for this packet:
1576 * "If the PS kernel does not need the Position XY Offsets to
1577 * compute a Position Value, then this field should be programmed
1578 * to POSOFFSET_NONE."
1579 *
1580 * "SW Recommendation: If the PS kernel needs the Position Offsets
1581 * to compute a Position XY value, this field should match Position
1582 * ZW Interpolation Mode to ensure a consistent position.xyzw
1583 * computation."
1584 *
1585 * We only require XY sample offsets. So, this recommendation doesn't
1586 * look useful at the moment. We might need this in future.
1587 */
1588 ps.PositionXYOffsetSelect =
1589 wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE : POSOFFSET_NONE;
1590 ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1591 ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1592 ps._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1593
1594 // XXX: Disable SIMD32 with 16x MSAA
1595
1596 ps.DispatchGRFStartRegisterForConstantSetupData0 =
1597 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
1598 ps.DispatchGRFStartRegisterForConstantSetupData1 =
1599 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
1600 ps.DispatchGRFStartRegisterForConstantSetupData2 =
1601 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
1602
1603 ps.KernelStartPointer0 =
1604 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
1605 ps.KernelStartPointer1 =
1606 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
1607 ps.KernelStartPointer2 =
1608 shader->prog_offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
1609 }
1610
1611 iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
1612 psx.PixelShaderValid = true;
1613 psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
1614 psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
1615 psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
1616 psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
1617 psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1618 psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch;
1619
1620 if (wm_prog_data->uses_sample_mask) {
1621 /* TODO: conservative rasterization */
1622 if (wm_prog_data->post_depth_coverage)
1623 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
1624 else
1625 psx.InputCoverageMaskState = ICMS_NORMAL;
1626 }
1627
1628 psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1629 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary;
1630 psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
1631
1632 // XXX: UAV bit
1633 }
1634 }
1635
1636 static unsigned
1637 iris_derived_program_state_size(enum iris_program_cache_id cache_id)
1638 {
1639 assert(cache_id <= IRIS_CACHE_CS);
1640
1641 static const unsigned dwords[] = {
1642 [IRIS_CACHE_VS] = GENX(3DSTATE_VS_length),
1643 [IRIS_CACHE_TCS] = GENX(3DSTATE_HS_length),
1644 [IRIS_CACHE_TES] = GENX(3DSTATE_TE_length) + GENX(3DSTATE_DS_length),
1645 [IRIS_CACHE_GS] = GENX(3DSTATE_GS_length),
1646 [IRIS_CACHE_FS] =
1647 GENX(3DSTATE_PS_length) + GENX(3DSTATE_PS_EXTRA_length),
1648 [IRIS_CACHE_CS] = 0,
1649 [IRIS_CACHE_BLORP_BLIT] = 0,
1650 };
1651
1652 return sizeof(uint32_t) * dwords[cache_id];
1653 }
1654
1655 static void
1656 iris_set_derived_program_state(const struct gen_device_info *devinfo,
1657 enum iris_program_cache_id cache_id,
1658 struct iris_compiled_shader *shader)
1659 {
1660 switch (cache_id) {
1661 case IRIS_CACHE_VS:
1662 iris_set_vs_state(devinfo, shader);
1663 break;
1664 case IRIS_CACHE_TCS:
1665 iris_set_tcs_state(devinfo, shader);
1666 break;
1667 case IRIS_CACHE_TES:
1668 iris_set_tes_state(devinfo, shader);
1669 break;
1670 case IRIS_CACHE_GS:
1671 iris_set_gs_state(devinfo, shader);
1672 break;
1673 case IRIS_CACHE_FS:
1674 iris_set_fs_state(devinfo, shader);
1675 break;
1676 case IRIS_CACHE_CS:
1677 break;
1678 default:
1679 break;
1680 }
1681 }
1682
1683 static void
1684 iris_upload_render_state(struct iris_context *ice,
1685 struct iris_batch *batch,
1686 const struct pipe_draw_info *draw)
1687 {
1688 const uint64_t dirty = ice->state.dirty;
1689
1690 struct brw_wm_prog_data *wm_prog_data = (void *)
1691 ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
1692
1693 if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
1694 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1695 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
1696 ptr.CCViewportPointer =
1697 iris_emit_state(batch, cso->cc_vp, sizeof(cso->cc_vp), 32);
1698 }
1699 }
1700
1701 if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
1702 struct iris_viewport_state *cso = ice->state.cso_vp;
1703 iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
1704 ptr.SFClipViewportPointer =
1705 iris_emit_state(batch, cso->sf_cl_vp, sizeof(cso->sf_cl_vp), 64);
1706 }
1707 }
1708
1709 /* XXX: L3 State */
1710
1711 if (dirty & IRIS_DIRTY_URB) {
1712 /* XXX: URB */
1713 }
1714
1715 if (dirty & IRIS_DIRTY_BLEND_STATE) {
1716 struct iris_blend_state *cso = ice->state.cso_blend;
1717 // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
1718 // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
1719 // (alpha test function/enable) + has writeable RT from ???????
1720 }
1721
1722 if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
1723 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1724 uint32_t cc_offset;
1725 void *cc_map =
1726 iris_alloc_state(batch,
1727 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length),
1728 64, &cc_offset);
1729 iris_pack_state(GENX(COLOR_CALC_STATE), cc_map, cc) {
1730 cc.AlphaTestFormat = ALPHATEST_FLOAT32;
1731 cc.AlphaReferenceValueAsFLOAT32 = cso->alpha.ref_value;
1732 cc.BlendConstantColorRed = ice->state.blend_color.color[0];
1733 cc.BlendConstantColorGreen = ice->state.blend_color.color[1];
1734 cc.BlendConstantColorBlue = ice->state.blend_color.color[2];
1735 cc.BlendConstantColorAlpha = ice->state.blend_color.color[3];
1736 }
1737 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1738 ptr.ColorCalcStatePointer = cc_offset;
1739 ptr.ColorCalcStatePointerValid = true;
1740 }
1741 }
1742
1743 // XXX: 3DSTATE_CONSTANT_XS
1744 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
1745
1746 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1747 if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
1748 continue;
1749
1750 // XXX: get sampler count from shader; don't emit them all...
1751 const int count = IRIS_MAX_TEXTURE_SAMPLERS;
1752
1753 uint32_t offset;
1754 uint32_t *map = iris_alloc_state(batch,
1755 count * 4 * GENX(SAMPLER_STATE_length),
1756 32, &offset);
1757
1758 for (int i = 0; i < count; i++) {
1759 // XXX: when we have a correct count, these better be bound
1760 if (!ice->state.samplers[stage][i])
1761 continue;
1762 memcpy(map, ice->state.samplers[stage][i]->sampler_state,
1763 4 * GENX(SAMPLER_STATE_length));
1764 map += GENX(SAMPLER_STATE_length);
1765 }
1766
1767 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
1768 ptr._3DCommandSubOpcode = 43 + stage;
1769 ptr.PointertoVSSamplerState = offset;
1770 }
1771 }
1772
1773 if (dirty & IRIS_DIRTY_MULTISAMPLE) {
1774 iris_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
1775 ms.PixelLocation =
1776 ice->state.cso_rast->half_pixel_center ? CENTER : UL_CORNER;
1777 if (ice->state.framebuffer.samples > 0)
1778 ms.NumberofMultisamples = ffs(ice->state.framebuffer.samples) - 1;
1779 }
1780 }
1781
1782 if (dirty & IRIS_DIRTY_SAMPLE_MASK) {
1783 iris_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
1784 ms.SampleMask = ice->state.sample_mask;
1785 }
1786 }
1787
1788 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
1789 if (!(dirty & (IRIS_DIRTY_VS << stage)))
1790 continue;
1791
1792 if (ice->shaders.prog[stage]) {
1793 iris_batch_emit(batch, ice->shaders.prog[stage]->derived_data,
1794 iris_derived_program_state_size(stage));
1795 } else {
1796 if (stage == MESA_SHADER_TESS_EVAL) {
1797 iris_emit_cmd(batch, GENX(3DSTATE_HS), hs);
1798 iris_emit_cmd(batch, GENX(3DSTATE_TE), te);
1799 iris_emit_cmd(batch, GENX(3DSTATE_DS), ds);
1800 } else if (stage == MESA_SHADER_GEOMETRY) {
1801 iris_emit_cmd(batch, GENX(3DSTATE_GS), gs);
1802 }
1803 }
1804 }
1805
1806 // XXX: SOL and so on
1807
1808 if (dirty & IRIS_DIRTY_CLIP) {
1809 struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
1810 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
1811
1812 uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
1813 iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
1814 if (wm_prog_data->barycentric_interp_modes &
1815 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
1816 cl.NonPerspectiveBarycentricEnable = true;
1817
1818 cl.ForceZeroRTAIndexEnable = cso_fb->layers == 0;
1819 }
1820 iris_emit_merge(batch, cso_rast->clip, dynamic_clip,
1821 ARRAY_SIZE(cso_rast->clip));
1822 }
1823
1824 if (dirty & IRIS_DIRTY_RASTER) {
1825 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1826 iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
1827 iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
1828
1829 }
1830
1831 if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_FS)) {
1832 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1833 uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
1834
1835 iris_pack_command(GENX(3DSTATE_WM), &dynamic_wm, wm) {
1836 wm.BarycentricInterpolationMode =
1837 wm_prog_data->barycentric_interp_modes;
1838
1839 if (wm_prog_data->early_fragment_tests)
1840 wm.EarlyDepthStencilControl = EDSC_PREPS;
1841 else if (wm_prog_data->has_side_effects)
1842 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
1843 }
1844 iris_emit_merge(batch, cso->wm, dynamic_wm, ARRAY_SIZE(cso->wm));
1845 }
1846
1847 // XXX: SBE, SBE_SWIZ
1848
1849 if (dirty & IRIS_DIRTY_PS_BLEND) {
1850 struct iris_blend_state *cso = ice->state.cso_blend;
1851 iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
1852 }
1853
1854 if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
1855 struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
1856 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
1857
1858 uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
1859 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
1860 wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
1861 wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
1862 }
1863 iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
1864 }
1865
1866 if (dirty & IRIS_DIRTY_SCISSOR) {
1867 uint32_t scissor_offset =
1868 iris_emit_state(batch, ice->state.scissors,
1869 sizeof(struct pipe_scissor_state) *
1870 ice->state.num_scissors, 32);
1871
1872 iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
1873 ptr.ScissorRectPointer = scissor_offset;
1874 }
1875 }
1876
1877 // XXX: 3DSTATE_DEPTH_BUFFER and friends
1878
1879 if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
1880 iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
1881 for (int i = 0; i < 32; i++) {
1882 poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
1883 }
1884 }
1885 }
1886
1887 if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
1888 struct iris_rasterizer_state *cso = ice->state.cso_rast;
1889 iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
1890 }
1891
1892 if (1) {
1893 iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
1894 topo.PrimitiveTopologyType =
1895 translate_prim_type(draw->mode, draw->vertices_per_patch);
1896 }
1897 }
1898
1899 if (draw->index_size > 0) {
1900 struct iris_resource *res = (struct iris_resource *)draw->index.resource;
1901
1902 assert(!draw->has_user_indices);
1903
1904 iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
1905 ib.IndexFormat = draw->index_size;
1906 ib.MOCS = MOCS_WB;
1907 ib.BufferSize = res->bo->size;
1908 ib.BufferStartingAddress = ro_bo(res->bo, 0);
1909 }
1910 }
1911
1912 if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
1913 struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
1914
1915 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
1916 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
1917
1918 uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
1919 (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1920 uint32_t *delta = cso->vertex_buffers +
1921 (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
1922
1923 iris_batch_emit(batch, cso->vertex_buffers,
1924 sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
1925
1926 for (unsigned i = 0; i < cso->num_buffers; i++) {
1927 *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
1928 cso->bos[i].bo, cso->bos[i].offset +
1929 *delta, cso->bos[i].reloc_flags);
1930 addr = (void *) addr + 16;
1931 delta = (void *) delta + 16;
1932 }
1933 }
1934
1935 if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
1936 struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
1937 iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
1938 (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
1939 for (int i = 0; i < cso->count; i++) {
1940 iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
1941 (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
1942 }
1943 for (int i = 0; i < cso->count; i++) {
1944 /* TODO: vertexid, instanceid support */
1945 iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
1946 }
1947 }
1948
1949 if (1) {
1950 iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
1951 if (draw->primitive_restart) {
1952 vf.IndexedDrawCutIndexEnable = true;
1953 vf.CutIndex = draw->restart_index;
1954 }
1955 }
1956 }
1957
1958 // XXX: Gen8 - PMA fix
1959
1960 assert(!draw->indirect); // XXX: indirect support
1961
1962 iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
1963 prim.StartInstanceLocation = draw->start_instance;
1964 prim.InstanceCount = draw->instance_count;
1965 prim.VertexCountPerInstance = draw->count;
1966 prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
1967
1968 // XXX: this is probably bonkers.
1969 prim.StartVertexLocation = draw->start;
1970
1971 if (draw->index_size) {
1972 prim.BaseVertexLocation += draw->index_bias;
1973 } else {
1974 prim.StartVertexLocation += draw->index_bias;
1975 }
1976
1977 //prim.BaseVertexLocation = ...;
1978 }
1979 #if 0
1980 l3 configuration
1981
1982 3DSTATE_URB_*
1983 -> TODO
1984
1985 3DSTATE_CONSTANT_* - push constants
1986 -> TODO
1987
1988 Surfaces:
1989 - pull constants
1990 - ubos/ssbos/abos
1991 - images
1992 - textures
1993 - render targets - write and read
1994 3DSTATE_BINDING_TABLE_POINTERS_*
1995 -> TODO
1996
1997 3DSTATE_STREAMOUT
1998 3DSTATE_SO_BUFFER
1999 3DSTATE_SO_DECL_LIST
2000
2001 3DSTATE_SBE
2002 -> iris_raster_state (point sprite texture coordinate origin)
2003 -> bunch of shader state...
2004 3DSTATE_SBE_SWIZ
2005 -> FS state
2006
2007 3DSTATE_DEPTH_BUFFER
2008 3DSTATE_HIER_DEPTH_BUFFER
2009 3DSTATE_STENCIL_BUFFER
2010 3DSTATE_CLEAR_PARAMS
2011 -> iris_framebuffer_state?
2012 #endif
2013 }
2014
2015
2016
2017 static void
2018 iris_destroy_state(struct iris_context *ice)
2019 {
2020 // XXX: unreference resources/surfaces.
2021 for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
2022 pipe_surface_reference(&ice->state.framebuffer.cbufs[i], NULL);
2023 }
2024 pipe_surface_reference(&ice->state.framebuffer.zsbuf, NULL);
2025 }
2026
2027 void
2028 genX(init_state)(struct iris_context *ice)
2029 {
2030 struct pipe_context *ctx = &ice->ctx;
2031
2032 ctx->create_blend_state = iris_create_blend_state;
2033 ctx->create_depth_stencil_alpha_state = iris_create_zsa_state;
2034 ctx->create_rasterizer_state = iris_create_rasterizer_state;
2035 ctx->create_sampler_state = iris_create_sampler_state;
2036 ctx->create_sampler_view = iris_create_sampler_view;
2037 ctx->create_surface = iris_create_surface;
2038 ctx->create_vertex_elements_state = iris_create_vertex_elements;
2039 ctx->create_compute_state = iris_create_compute_state;
2040 ctx->bind_blend_state = iris_bind_blend_state;
2041 ctx->bind_depth_stencil_alpha_state = iris_bind_zsa_state;
2042 ctx->bind_sampler_states = iris_bind_sampler_states;
2043 ctx->bind_rasterizer_state = iris_bind_rasterizer_state;
2044 ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
2045 ctx->bind_compute_state = iris_bind_compute_state;
2046 ctx->delete_blend_state = iris_delete_state;
2047 ctx->delete_depth_stencil_alpha_state = iris_delete_state;
2048 ctx->delete_fs_state = iris_delete_state;
2049 ctx->delete_rasterizer_state = iris_delete_state;
2050 ctx->delete_sampler_state = iris_delete_state;
2051 ctx->delete_vertex_elements_state = iris_delete_state;
2052 ctx->delete_compute_state = iris_delete_state;
2053 ctx->delete_tcs_state = iris_delete_state;
2054 ctx->delete_tes_state = iris_delete_state;
2055 ctx->delete_gs_state = iris_delete_state;
2056 ctx->delete_vs_state = iris_delete_state;
2057 ctx->set_blend_color = iris_set_blend_color;
2058 ctx->set_clip_state = iris_set_clip_state;
2059 ctx->set_constant_buffer = iris_set_constant_buffer;
2060 ctx->set_sampler_views = iris_set_sampler_views;
2061 ctx->set_framebuffer_state = iris_set_framebuffer_state;
2062 ctx->set_polygon_stipple = iris_set_polygon_stipple;
2063 ctx->set_sample_mask = iris_set_sample_mask;
2064 ctx->set_scissor_states = iris_set_scissor_states;
2065 ctx->set_stencil_ref = iris_set_stencil_ref;
2066 ctx->set_vertex_buffers = iris_set_vertex_buffers;
2067 ctx->set_viewport_states = iris_set_viewport_states;
2068 ctx->sampler_view_destroy = iris_sampler_view_destroy;
2069 ctx->surface_destroy = iris_surface_destroy;
2070 ctx->draw_vbo = iris_draw_vbo;
2071 ctx->launch_grid = iris_launch_grid;
2072 ctx->create_stream_output_target = iris_create_stream_output_target;
2073 ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
2074 ctx->set_stream_output_targets = iris_set_stream_output_targets;
2075
2076 ice->state.destroy_state = iris_destroy_state;
2077 ice->state.init_render_context = iris_init_render_context;
2078 ice->state.upload_render_state = iris_upload_render_state;
2079 ice->state.derived_program_state_size = iris_derived_program_state_size;
2080 ice->state.set_derived_program_state = iris_set_derived_program_state;
2081 ice->state.populate_vs_key = iris_populate_vs_key;
2082 ice->state.populate_tcs_key = iris_populate_tcs_key;
2083 ice->state.populate_tes_key = iris_populate_tes_key;
2084 ice->state.populate_gs_key = iris_populate_gs_key;
2085 ice->state.populate_fs_key = iris_populate_fs_key;
2086
2087
2088 ice->state.dirty = ~0ull;
2089 }