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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #define __gen_address_type struct iris_address
110 #define __gen_user_data struct iris_batch
112 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
115 __gen_combine_address(struct iris_batch
*batch
, void *location
,
116 struct iris_address addr
, uint32_t delta
)
118 uint64_t result
= addr
.offset
+ delta
;
121 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
122 /* Assume this is a general address, not relative to a base. */
123 result
+= addr
.bo
->gtt_offset
;
129 #define __genxml_cmd_length(cmd) cmd ## _length
130 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
131 #define __genxml_cmd_header(cmd) cmd ## _header
132 #define __genxml_cmd_pack(cmd) cmd ## _pack
134 #define _iris_pack_command(batch, cmd, dst, name) \
135 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
136 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
137 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
141 #define iris_pack_command(cmd, dst, name) \
142 _iris_pack_command(NULL, cmd, dst, name)
144 #define iris_pack_state(cmd, dst, name) \
145 for (struct cmd name = {}, \
146 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
147 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
150 #define iris_emit_cmd(batch, cmd, name) \
151 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
153 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
155 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
156 for (uint32_t i = 0; i < num_dwords; i++) \
157 dw[i] = (dwords0)[i] | (dwords1)[i]; \
158 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
161 #include "genxml/genX_pack.h"
162 #include "genxml/gen_macros.h"
163 #include "genxml/genX_bits.h"
164 #include "intel/common/gen_guardband.h"
167 #define MOCS_PTE 0x18
170 #define MOCS_PTE (1 << 1)
171 #define MOCS_WB (2 << 1)
175 mocs(const struct iris_bo
*bo
)
177 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
181 * Statically assert that PIPE_* enums match the hardware packets.
182 * (As long as they match, we don't need to translate them.)
184 UNUSED
static void pipe_asserts()
186 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
188 /* pipe_logicop happens to match the hardware. */
189 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
190 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
191 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
192 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
193 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
194 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
195 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
196 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
197 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
198 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
199 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
200 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
201 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
202 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
203 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
204 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
206 /* pipe_blend_func happens to match the hardware. */
207 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
224 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
225 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
227 /* pipe_blend_func happens to match the hardware. */
228 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
229 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
230 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
231 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
232 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
234 /* pipe_stencil_op happens to match the hardware. */
235 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
241 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
242 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
244 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
245 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
246 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
251 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
253 static const unsigned map
[] = {
254 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
255 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
256 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
257 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
258 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
259 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
260 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
261 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
262 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
263 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
264 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
265 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
266 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
267 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
268 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
271 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
275 translate_compare_func(enum pipe_compare_func pipe_func
)
277 static const unsigned map
[] = {
278 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
279 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
280 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
281 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
282 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
283 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
284 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
285 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
287 return map
[pipe_func
];
291 translate_shadow_func(enum pipe_compare_func pipe_func
)
293 /* Gallium specifies the result of shadow comparisons as:
295 * 1 if ref <op> texel,
300 * 0 if texel <op> ref,
303 * So we need to flip the operator and also negate.
305 static const unsigned map
[] = {
306 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
307 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
308 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
309 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
310 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
311 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
312 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
313 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
315 return map
[pipe_func
];
319 translate_cull_mode(unsigned pipe_face
)
321 static const unsigned map
[4] = {
322 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
323 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
324 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
325 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
327 return map
[pipe_face
];
331 translate_fill_mode(unsigned pipe_polymode
)
333 static const unsigned map
[4] = {
334 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
335 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
336 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
337 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
339 return map
[pipe_polymode
];
343 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
345 static const unsigned map
[] = {
346 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
347 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
348 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
350 return map
[pipe_mip
];
354 translate_wrap(unsigned pipe_wrap
)
356 static const unsigned map
[] = {
357 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
358 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
359 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
360 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
361 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
362 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
364 /* These are unsupported. */
365 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
366 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
368 return map
[pipe_wrap
];
371 static struct iris_address
372 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
374 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
375 * validation list at CSO creation time, instead of draw time.
377 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
380 static struct iris_address
381 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
383 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
384 * validation list at CSO creation time, instead of draw time.
386 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
390 * Allocate space for some indirect state.
392 * Return a pointer to the map (to fill it out) and a state ref (for
393 * referring to the state in GPU commands).
396 upload_state(struct u_upload_mgr
*uploader
,
397 struct iris_state_ref
*ref
,
402 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
407 * Stream out temporary/short-lived state.
409 * This allocates space, pins the BO, and includes the BO address in the
410 * returned offset (which works because all state lives in 32-bit memory
414 stream_state(struct iris_batch
*batch
,
415 struct u_upload_mgr
*uploader
,
416 struct pipe_resource
**out_res
,
419 uint32_t *out_offset
)
423 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
425 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
426 iris_use_pinned_bo(batch
, bo
, false);
428 *out_offset
+= iris_bo_offset_from_base_address(bo
);
430 iris_record_state_size(batch
->state_sizes
, *out_offset
, size
);
436 * stream_state() + memcpy.
439 emit_state(struct iris_batch
*batch
,
440 struct u_upload_mgr
*uploader
,
441 struct pipe_resource
**out_res
,
448 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
451 memcpy(map
, data
, size
);
457 * Did field 'x' change between 'old_cso' and 'new_cso'?
459 * (If so, we may want to set some dirty flags.)
461 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
462 #define cso_changed_memcmp(x) \
463 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
466 flush_for_state_base_change(struct iris_batch
*batch
)
468 /* Flush before emitting STATE_BASE_ADDRESS.
470 * This isn't documented anywhere in the PRM. However, it seems to be
471 * necessary prior to changing the surface state base adress. We've
472 * seen issues in Vulkan where we get GPU hangs when using multi-level
473 * command buffers which clear depth, reset state base address, and then
476 * Normally, in GL, we would trust the kernel to do sufficient stalls
477 * and flushes prior to executing our batch. However, it doesn't seem
478 * as if the kernel's flushing is always sufficient and we don't want to
481 * We make this an end-of-pipe sync instead of a normal flush because we
482 * do not know the current status of the GPU. On Haswell at least,
483 * having a fast-clear operation in flight at the same time as a normal
484 * rendering operation can cause hangs. Since the kernel's flushing is
485 * insufficient, we need to ensure that any rendering operations from
486 * other processes are definitely complete before we try to do our own
487 * rendering. It's a bit of a big hammer but it appears to work.
489 iris_emit_end_of_pipe_sync(batch
,
490 "change STATE_BASE_ADDRESS",
491 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
492 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
493 PIPE_CONTROL_DATA_CACHE_FLUSH
);
497 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
499 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
500 lri
.RegisterOffset
= reg
;
504 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
507 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
509 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
510 lrr
.SourceRegisterAddress
= src
;
511 lrr
.DestinationRegisterAddress
= dst
;
516 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
518 #if GEN_GEN >= 8 && GEN_GEN < 10
519 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
521 * Software must clear the COLOR_CALC_STATE Valid field in
522 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
523 * with Pipeline Select set to GPGPU.
525 * The internal hardware docs recommend the same workaround for Gen9
528 if (pipeline
== GPGPU
)
529 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
533 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
534 * PIPELINE_SELECT [DevBWR+]":
538 * Software must ensure all the write caches are flushed through a
539 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
540 * command to invalidate read only caches prior to programming
541 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
543 iris_emit_pipe_control_flush(batch
,
544 "workaround: PIPELINE_SELECT flushes (1/2)",
545 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
546 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
547 PIPE_CONTROL_DATA_CACHE_FLUSH
|
548 PIPE_CONTROL_CS_STALL
);
550 iris_emit_pipe_control_flush(batch
,
551 "workaround: PIPELINE_SELECT flushes (2/2)",
552 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
553 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
554 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
555 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
557 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
561 sel
.PipelineSelection
= pipeline
;
566 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
571 * "This chicken bit works around a hardware issue with barrier
572 * logic encountered when switching between GPGPU and 3D pipelines.
573 * To workaround the issue, this mode bit should be set after a
574 * pipeline is selected."
577 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
578 reg
.GLKBarrierMode
= value
;
579 reg
.GLKBarrierModeMask
= 1;
581 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
586 init_state_base_address(struct iris_batch
*batch
)
588 flush_for_state_base_change(batch
);
590 /* We program most base addresses once at context initialization time.
591 * Each base address points at a 4GB memory zone, and never needs to
592 * change. See iris_bufmgr.h for a description of the memory zones.
594 * The one exception is Surface State Base Address, which needs to be
595 * updated occasionally. See iris_binder.c for the details there.
597 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
598 sba
.GeneralStateMOCS
= MOCS_WB
;
599 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
600 sba
.DynamicStateMOCS
= MOCS_WB
;
601 sba
.IndirectObjectMOCS
= MOCS_WB
;
602 sba
.InstructionMOCS
= MOCS_WB
;
604 sba
.GeneralStateBaseAddressModifyEnable
= true;
605 sba
.DynamicStateBaseAddressModifyEnable
= true;
606 sba
.IndirectObjectBaseAddressModifyEnable
= true;
607 sba
.InstructionBaseAddressModifyEnable
= true;
608 sba
.GeneralStateBufferSizeModifyEnable
= true;
609 sba
.DynamicStateBufferSizeModifyEnable
= true;
611 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
612 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
614 sba
.IndirectObjectBufferSizeModifyEnable
= true;
615 sba
.InstructionBuffersizeModifyEnable
= true;
617 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
618 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
620 sba
.GeneralStateBufferSize
= 0xfffff;
621 sba
.IndirectObjectBufferSize
= 0xfffff;
622 sba
.InstructionBufferSize
= 0xfffff;
623 sba
.DynamicStateBufferSize
= 0xfffff;
628 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
629 bool has_slm
, bool wants_dc_cache
)
632 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
633 reg
.SLMEnable
= has_slm
;
635 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
636 * in L3CNTLREG register. The default setting of the bit is not the
637 * desirable behavior.
639 reg
.ErrorDetectionBehaviorControl
= true;
640 reg
.UseFullWays
= true;
642 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
643 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
644 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
645 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
647 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
651 iris_emit_default_l3_config(struct iris_batch
*batch
,
652 const struct gen_device_info
*devinfo
,
655 bool wants_dc_cache
= true;
656 bool has_slm
= compute
;
657 const struct gen_l3_weights w
=
658 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
659 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
660 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
663 #if GEN_GEN == 9 || GEN_GEN == 10
665 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
669 /* A fixed function pipe flush is required before modifying this field */
670 iris_emit_end_of_pipe_sync(batch
, enable
? "enable preemption"
671 : "disable preemption",
672 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
674 /* enable object level preemption */
675 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
676 reg
.ReplayMode
= enable
;
677 reg
.ReplayModeMask
= true;
679 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
684 * Upload the initial GPU state for a render context.
686 * This sets some invariant state that needs to be programmed a particular
687 * way, but we never actually change.
690 iris_init_render_context(struct iris_screen
*screen
,
691 struct iris_batch
*batch
,
692 struct iris_vtable
*vtbl
,
693 struct pipe_debug_callback
*dbg
)
695 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
698 emit_pipeline_select(batch
, _3D
);
700 iris_emit_default_l3_config(batch
, devinfo
, false);
702 init_state_base_address(batch
);
705 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
706 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
707 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
709 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
711 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
712 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
713 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
715 iris_emit_lri(batch
, INSTPM
, reg_val
);
719 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
720 reg
.FloatBlendOptimizationEnable
= true;
721 reg
.FloatBlendOptimizationEnableMask
= true;
722 reg
.PartialResolveDisableInVC
= true;
723 reg
.PartialResolveDisableInVCMask
= true;
725 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
727 if (devinfo
->is_geminilake
)
728 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
732 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
733 reg
.HeaderlessMessageforPreemptableContexts
= 1;
734 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
736 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
738 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
739 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
740 reg
.EnabledTexelOffsetPrecisionFix
= 1;
741 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
743 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
745 /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. */
746 iris_pack_state(GENX(COMMON_SLICE_CHICKEN3
), ®_val
, reg
) {
747 reg
.PSThreadPanicDispatch
= 0x3;
748 reg
.PSThreadPanicDispatchMask
= 0x3;
750 iris_emit_lri(batch
, COMMON_SLICE_CHICKEN3
, reg_val
);
752 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
753 reg
.StateCacheRedirectToCSSectionEnable
= true;
754 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
756 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
762 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
763 * changing it dynamically. We set it to the maximum size here, and
764 * instead include the render target dimensions in the viewport, so
765 * viewport extents clipping takes care of pruning stray geometry.
767 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
768 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
769 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
772 /* Set the initial MSAA sample positions. */
773 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
774 GEN_SAMPLE_POS_1X(pat
._1xSample
);
775 GEN_SAMPLE_POS_2X(pat
._2xSample
);
776 GEN_SAMPLE_POS_4X(pat
._4xSample
);
777 GEN_SAMPLE_POS_8X(pat
._8xSample
);
779 GEN_SAMPLE_POS_16X(pat
._16xSample
);
783 /* Use the legacy AA line coverage computation. */
784 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
786 /* Disable chromakeying (it's for media) */
787 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
789 /* We want regular rendering, not special HiZ operations. */
790 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
792 /* No polygon stippling offsets are necessary. */
793 /* TODO: may need to set an offset for origin-UL framebuffers */
794 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
796 /* Set a static partitioning of the push constant area. */
797 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
798 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
799 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
800 alloc
._3DCommandSubOpcode
= 18 + i
;
801 alloc
.ConstantBufferOffset
= 6 * i
;
802 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
807 /* Gen11+ is enabled for us by the kernel. */
808 iris_enable_obj_preemption(batch
, true);
813 iris_init_compute_context(struct iris_screen
*screen
,
814 struct iris_batch
*batch
,
815 struct iris_vtable
*vtbl
,
816 struct pipe_debug_callback
*dbg
)
818 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
820 emit_pipeline_select(batch
, GPGPU
);
822 iris_emit_default_l3_config(batch
, devinfo
, true);
824 init_state_base_address(batch
);
827 if (devinfo
->is_geminilake
)
828 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
832 struct iris_vertex_buffer_state
{
833 /** The VERTEX_BUFFER_STATE hardware structure. */
834 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
836 /** The resource to source vertex data from. */
837 struct pipe_resource
*resource
;
840 struct iris_depth_buffer_state
{
841 /* Depth/HiZ/Stencil related hardware packets. */
842 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
843 GENX(3DSTATE_STENCIL_BUFFER_length
) +
844 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
845 GENX(3DSTATE_CLEAR_PARAMS_length
)];
849 * Generation-specific context state (ice->state.genx->...).
851 * Most state can go in iris_context directly, but these encode hardware
852 * packets which vary by generation.
854 struct iris_genx_state
{
855 struct iris_vertex_buffer_state vertex_buffers
[33];
857 struct iris_depth_buffer_state depth_buffer
;
859 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
862 /* Is object level preemption enabled? */
863 bool object_preemption
;
868 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
870 } shaders
[MESA_SHADER_STAGES
];
874 * The pipe->set_blend_color() driver hook.
876 * This corresponds to our COLOR_CALC_STATE.
879 iris_set_blend_color(struct pipe_context
*ctx
,
880 const struct pipe_blend_color
*state
)
882 struct iris_context
*ice
= (struct iris_context
*) ctx
;
884 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
885 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
886 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
890 * Gallium CSO for blend state (see pipe_blend_state).
892 struct iris_blend_state
{
893 /** Partial 3DSTATE_PS_BLEND */
894 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
896 /** Partial BLEND_STATE */
897 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
898 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
900 bool alpha_to_coverage
; /* for shader key */
902 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
903 uint8_t blend_enables
;
905 /** Bitfield of whether color writes are enabled for RT[i] */
906 uint8_t color_write_enables
;
908 /** Does RT[0] use dual color blending? */
909 bool dual_color_blending
;
912 static enum pipe_blendfactor
913 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
916 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
917 return PIPE_BLENDFACTOR_ONE
;
919 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
920 return PIPE_BLENDFACTOR_ZERO
;
927 * The pipe->create_blend_state() driver hook.
929 * Translates a pipe_blend_state into iris_blend_state.
932 iris_create_blend_state(struct pipe_context
*ctx
,
933 const struct pipe_blend_state
*state
)
935 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
936 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
938 cso
->blend_enables
= 0;
939 cso
->color_write_enables
= 0;
940 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
942 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
944 bool indep_alpha_blend
= false;
946 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
947 const struct pipe_rt_blend_state
*rt
=
948 &state
->rt
[state
->independent_blend_enable
? i
: 0];
950 enum pipe_blendfactor src_rgb
=
951 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
952 enum pipe_blendfactor src_alpha
=
953 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
954 enum pipe_blendfactor dst_rgb
=
955 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
956 enum pipe_blendfactor dst_alpha
=
957 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
959 if (rt
->rgb_func
!= rt
->alpha_func
||
960 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
961 indep_alpha_blend
= true;
963 if (rt
->blend_enable
)
964 cso
->blend_enables
|= 1u << i
;
967 cso
->color_write_enables
|= 1u << i
;
969 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
970 be
.LogicOpEnable
= state
->logicop_enable
;
971 be
.LogicOpFunction
= state
->logicop_func
;
973 be
.PreBlendSourceOnlyClampEnable
= false;
974 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
975 be
.PreBlendColorClampEnable
= true;
976 be
.PostBlendColorClampEnable
= true;
978 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
980 be
.ColorBlendFunction
= rt
->rgb_func
;
981 be
.AlphaBlendFunction
= rt
->alpha_func
;
982 be
.SourceBlendFactor
= src_rgb
;
983 be
.SourceAlphaBlendFactor
= src_alpha
;
984 be
.DestinationBlendFactor
= dst_rgb
;
985 be
.DestinationAlphaBlendFactor
= dst_alpha
;
987 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
988 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
989 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
990 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
992 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
995 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
996 /* pb.HasWriteableRT is filled in at draw time.
997 * pb.AlphaTestEnable is filled in at draw time.
999 * pb.ColorBufferBlendEnable is filled in at draw time so we can avoid
1000 * setting it when dual color blending without an appropriate shader.
1003 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1004 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1006 pb
.SourceBlendFactor
=
1007 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
1008 pb
.SourceAlphaBlendFactor
=
1009 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
1010 pb
.DestinationBlendFactor
=
1011 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1012 pb
.DestinationAlphaBlendFactor
=
1013 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1016 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1017 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1018 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1019 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1020 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1021 bs
.ColorDitherEnable
= state
->dither
;
1022 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1025 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1031 * The pipe->bind_blend_state() driver hook.
1033 * Bind a blending CSO and flag related dirty bits.
1036 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1038 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1039 struct iris_blend_state
*cso
= state
;
1041 ice
->state
.cso_blend
= cso
;
1042 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1044 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1045 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1046 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1047 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1051 * Return true if the FS writes to any color outputs which are not disabled
1052 * via color masking.
1055 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1056 const struct shader_info
*fs_info
)
1061 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1063 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1064 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1066 return cso_blend
->color_write_enables
& rt_outputs
;
1070 * Gallium CSO for depth, stencil, and alpha testing state.
1072 struct iris_depth_stencil_alpha_state
{
1073 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1074 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1076 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1077 struct pipe_alpha_state alpha
;
1079 /** Outbound to resolve and cache set tracking. */
1080 bool depth_writes_enabled
;
1081 bool stencil_writes_enabled
;
1085 * The pipe->create_depth_stencil_alpha_state() driver hook.
1087 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1088 * testing state since we need pieces of it in a variety of places.
1091 iris_create_zsa_state(struct pipe_context
*ctx
,
1092 const struct pipe_depth_stencil_alpha_state
*state
)
1094 struct iris_depth_stencil_alpha_state
*cso
=
1095 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1097 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1099 cso
->alpha
= state
->alpha
;
1100 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1101 cso
->stencil_writes_enabled
=
1102 state
->stencil
[0].writemask
!= 0 ||
1103 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1105 /* The state tracker needs to optimize away EQUAL writes for us. */
1106 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1108 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1109 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1110 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1111 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1112 wmds
.StencilTestFunction
=
1113 translate_compare_func(state
->stencil
[0].func
);
1114 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1115 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1116 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1117 wmds
.BackfaceStencilTestFunction
=
1118 translate_compare_func(state
->stencil
[1].func
);
1119 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1120 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1121 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1122 wmds
.StencilBufferWriteEnable
=
1123 state
->stencil
[0].writemask
!= 0 ||
1124 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1125 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1126 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1127 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1128 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1129 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1130 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1131 /* wmds.[Backface]StencilReferenceValue are merged later */
1138 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1140 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1143 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1145 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1146 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1147 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1150 if (cso_changed(alpha
.ref_value
))
1151 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1153 if (cso_changed(alpha
.enabled
))
1154 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1156 if (cso_changed(alpha
.func
))
1157 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1159 if (cso_changed(depth_writes_enabled
))
1160 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1162 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1163 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1166 ice
->state
.cso_zsa
= new_cso
;
1167 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1168 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1169 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1173 * Gallium CSO for rasterizer state.
1175 struct iris_rasterizer_state
{
1176 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1177 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1178 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1179 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1180 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1182 uint8_t num_clip_plane_consts
;
1183 bool clip_halfz
; /* for CC_VIEWPORT */
1184 bool depth_clip_near
; /* for CC_VIEWPORT */
1185 bool depth_clip_far
; /* for CC_VIEWPORT */
1186 bool flatshade
; /* for shader state */
1187 bool flatshade_first
; /* for stream output */
1188 bool clamp_fragment_color
; /* for shader state */
1189 bool light_twoside
; /* for shader state */
1190 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1191 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1192 bool line_stipple_enable
;
1193 bool poly_stipple_enable
;
1195 bool force_persample_interp
;
1196 bool conservative_rasterization
;
1197 bool fill_mode_point_or_line
;
1198 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1199 uint16_t sprite_coord_enable
;
1203 get_line_width(const struct pipe_rasterizer_state
*state
)
1205 float line_width
= state
->line_width
;
1207 /* From the OpenGL 4.4 spec:
1209 * "The actual width of non-antialiased lines is determined by rounding
1210 * the supplied width to the nearest integer, then clamping it to the
1211 * implementation-dependent maximum non-antialiased line width."
1213 if (!state
->multisample
&& !state
->line_smooth
)
1214 line_width
= roundf(state
->line_width
);
1216 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1217 /* For 1 pixel line thickness or less, the general anti-aliasing
1218 * algorithm gives up, and a garbage line is generated. Setting a
1219 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1220 * (one-pixel-wide), non-antialiased lines.
1222 * Lines rendered with zero Line Width are rasterized using the
1223 * "Grid Intersection Quantization" rules as specified by the
1224 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1233 * The pipe->create_rasterizer_state() driver hook.
1236 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1237 const struct pipe_rasterizer_state
*state
)
1239 struct iris_rasterizer_state
*cso
=
1240 malloc(sizeof(struct iris_rasterizer_state
));
1242 cso
->multisample
= state
->multisample
;
1243 cso
->force_persample_interp
= state
->force_persample_interp
;
1244 cso
->clip_halfz
= state
->clip_halfz
;
1245 cso
->depth_clip_near
= state
->depth_clip_near
;
1246 cso
->depth_clip_far
= state
->depth_clip_far
;
1247 cso
->flatshade
= state
->flatshade
;
1248 cso
->flatshade_first
= state
->flatshade_first
;
1249 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1250 cso
->light_twoside
= state
->light_twoside
;
1251 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1252 cso
->half_pixel_center
= state
->half_pixel_center
;
1253 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1254 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1255 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1256 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1257 cso
->conservative_rasterization
=
1258 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1260 cso
->fill_mode_point_or_line
=
1261 state
->fill_front
== PIPE_POLYGON_MODE_LINE
||
1262 state
->fill_front
== PIPE_POLYGON_MODE_POINT
||
1263 state
->fill_back
== PIPE_POLYGON_MODE_LINE
||
1264 state
->fill_back
== PIPE_POLYGON_MODE_POINT
;
1266 if (state
->clip_plane_enable
!= 0)
1267 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1269 cso
->num_clip_plane_consts
= 0;
1271 float line_width
= get_line_width(state
);
1273 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1274 sf
.StatisticsEnable
= true;
1275 sf
.ViewportTransformEnable
= true;
1276 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1277 sf
.LineEndCapAntialiasingRegionWidth
=
1278 state
->line_smooth
? _10pixels
: _05pixels
;
1279 sf
.LastPixelEnable
= state
->line_last_pixel
;
1280 sf
.LineWidth
= line_width
;
1281 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1282 !state
->point_quad_rasterization
;
1283 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1284 sf
.PointWidth
= state
->point_size
;
1286 if (state
->flatshade_first
) {
1287 sf
.TriangleFanProvokingVertexSelect
= 1;
1289 sf
.TriangleStripListProvokingVertexSelect
= 2;
1290 sf
.TriangleFanProvokingVertexSelect
= 2;
1291 sf
.LineStripListProvokingVertexSelect
= 1;
1295 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1296 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1297 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1298 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1299 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1300 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1301 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1302 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1303 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1304 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1305 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1306 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1307 rr
.SmoothPointEnable
= state
->point_smooth
;
1308 rr
.AntialiasingEnable
= state
->line_smooth
;
1309 rr
.ScissorRectangleEnable
= state
->scissor
;
1311 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1312 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1313 rr
.ConservativeRasterizationEnable
=
1314 cso
->conservative_rasterization
;
1316 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1320 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1321 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1322 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1324 cl
.EarlyCullEnable
= true;
1325 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1326 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1327 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1328 cl
.GuardbandClipTestEnable
= true;
1329 cl
.ClipEnable
= true;
1330 cl
.MinimumPointWidth
= 0.125;
1331 cl
.MaximumPointWidth
= 255.875;
1333 if (state
->flatshade_first
) {
1334 cl
.TriangleFanProvokingVertexSelect
= 1;
1336 cl
.TriangleStripListProvokingVertexSelect
= 2;
1337 cl
.TriangleFanProvokingVertexSelect
= 2;
1338 cl
.LineStripListProvokingVertexSelect
= 1;
1342 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1343 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1344 * filled in at draw time from the FS program.
1346 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1347 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1348 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1349 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1350 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1353 /* Remap from 0..255 back to 1..256 */
1354 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1356 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1357 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1358 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1359 line
.LineStippleRepeatCount
= line_stipple_factor
;
1366 * The pipe->bind_rasterizer_state() driver hook.
1368 * Bind a rasterizer CSO and flag related dirty bits.
1371 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1373 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1374 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1375 struct iris_rasterizer_state
*new_cso
= state
;
1378 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1379 if (cso_changed_memcmp(line_stipple
))
1380 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1382 if (cso_changed(half_pixel_center
))
1383 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1385 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1386 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1388 if (cso_changed(rasterizer_discard
))
1389 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1391 if (cso_changed(flatshade_first
))
1392 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1394 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1395 cso_changed(clip_halfz
))
1396 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1398 if (cso_changed(sprite_coord_enable
) ||
1399 cso_changed(sprite_coord_mode
) ||
1400 cso_changed(light_twoside
))
1401 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1403 if (cso_changed(conservative_rasterization
))
1404 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1407 ice
->state
.cso_rast
= new_cso
;
1408 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1409 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1410 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1414 * Return true if the given wrap mode requires the border color to exist.
1416 * (We can skip uploading it if the sampler isn't going to use it.)
1419 wrap_mode_needs_border_color(unsigned wrap_mode
)
1421 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1425 * Gallium CSO for sampler state.
1427 struct iris_sampler_state
{
1428 union pipe_color_union border_color
;
1429 bool needs_border_color
;
1431 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1435 * The pipe->create_sampler_state() driver hook.
1437 * We fill out SAMPLER_STATE (except for the border color pointer), and
1438 * store that on the CPU. It doesn't make sense to upload it to a GPU
1439 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1440 * all bound sampler states to be in contiguous memor.
1443 iris_create_sampler_state(struct pipe_context
*ctx
,
1444 const struct pipe_sampler_state
*state
)
1446 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1451 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1452 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1454 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1455 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1456 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1458 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1460 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1461 wrap_mode_needs_border_color(wrap_t
) ||
1462 wrap_mode_needs_border_color(wrap_r
);
1464 float min_lod
= state
->min_lod
;
1465 unsigned mag_img_filter
= state
->mag_img_filter
;
1467 // XXX: explain this code ported from ilo...I don't get it at all...
1468 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1469 state
->min_lod
> 0.0f
) {
1471 mag_img_filter
= state
->min_img_filter
;
1474 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1475 samp
.TCXAddressControlMode
= wrap_s
;
1476 samp
.TCYAddressControlMode
= wrap_t
;
1477 samp
.TCZAddressControlMode
= wrap_r
;
1478 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1479 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1480 samp
.MinModeFilter
= state
->min_img_filter
;
1481 samp
.MagModeFilter
= mag_img_filter
;
1482 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1483 samp
.MaximumAnisotropy
= RATIO21
;
1485 if (state
->max_anisotropy
>= 2) {
1486 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1487 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1488 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1491 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1492 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1494 samp
.MaximumAnisotropy
=
1495 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1498 /* Set address rounding bits if not using nearest filtering. */
1499 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1500 samp
.UAddressMinFilterRoundingEnable
= true;
1501 samp
.VAddressMinFilterRoundingEnable
= true;
1502 samp
.RAddressMinFilterRoundingEnable
= true;
1505 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1506 samp
.UAddressMagFilterRoundingEnable
= true;
1507 samp
.VAddressMagFilterRoundingEnable
= true;
1508 samp
.RAddressMagFilterRoundingEnable
= true;
1511 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1512 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1514 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1516 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1517 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1518 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1519 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1521 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1528 * The pipe->bind_sampler_states() driver hook.
1531 iris_bind_sampler_states(struct pipe_context
*ctx
,
1532 enum pipe_shader_type p_stage
,
1533 unsigned start
, unsigned count
,
1536 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1537 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1538 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1540 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1542 for (int i
= 0; i
< count
; i
++) {
1543 shs
->samplers
[start
+ i
] = states
[i
];
1546 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1550 * Upload the sampler states into a contiguous area of GPU memory, for
1551 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1553 * Also fill out the border color state pointers.
1556 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1558 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1559 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1561 /* We assume the state tracker will call pipe->bind_sampler_states()
1562 * if the program's number of textures changes.
1564 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1569 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1570 * in the dynamic state memory zone, so we can point to it via the
1571 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1573 unsigned size
= count
* 4 * GENX(SAMPLER_STATE_length
);
1575 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
, size
, 32);
1579 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1580 shs
->sampler_table
.offset
+=
1581 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1583 iris_record_state_size(ice
->state
.sizes
, shs
->sampler_table
.offset
, size
);
1585 /* Make sure all land in the same BO */
1586 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1588 ice
->state
.need_border_colors
&= ~(1 << stage
);
1590 for (int i
= 0; i
< count
; i
++) {
1591 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1592 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1595 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1596 } else if (!state
->needs_border_color
) {
1597 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1599 ice
->state
.need_border_colors
|= 1 << stage
;
1601 /* We may need to swizzle the border color for format faking.
1602 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1603 * This means we need to move the border color's A channel into
1604 * the R or G channels so that those read swizzles will move it
1607 union pipe_color_union
*color
= &state
->border_color
;
1608 union pipe_color_union tmp
;
1610 enum pipe_format internal_format
= tex
->res
->internal_format
;
1612 if (util_format_is_alpha(internal_format
)) {
1613 unsigned char swz
[4] = {
1614 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1615 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1617 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1619 } else if (util_format_is_luminance_alpha(internal_format
) &&
1620 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1621 unsigned char swz
[4] = {
1622 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1623 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1625 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1630 /* Stream out the border color and merge the pointer. */
1631 uint32_t offset
= iris_upload_border_color(ice
, color
);
1633 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1634 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1635 dyns
.BorderColorPointer
= offset
;
1638 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1639 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1642 map
+= GENX(SAMPLER_STATE_length
);
1646 static enum isl_channel_select
1647 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1650 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1651 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1652 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1653 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1654 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1655 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1656 default: unreachable("invalid swizzle");
1661 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1662 struct iris_resource
*res
,
1664 enum isl_format format
,
1665 struct isl_swizzle swizzle
,
1669 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1670 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1672 /* The ARB_texture_buffer_specification says:
1674 * "The number of texels in the buffer texture's texel array is given by
1676 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1678 * where <buffer_size> is the size of the buffer object, in basic
1679 * machine units and <components> and <base_type> are the element count
1680 * and base data type for elements, as specified in Table X.1. The
1681 * number of texels in the texel array is then clamped to the
1682 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1684 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1685 * so that when ISL divides by stride to obtain the number of texels, that
1686 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1688 unsigned final_size
=
1689 MIN3(size
, res
->bo
->size
- res
->offset
- offset
,
1690 IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1692 isl_buffer_fill_state(isl_dev
, map
,
1693 .address
= res
->bo
->gtt_offset
+ res
->offset
+ offset
,
1694 .size_B
= final_size
,
1698 .mocs
= mocs(res
->bo
));
1701 #define SURFACE_STATE_ALIGNMENT 64
1704 * Allocate several contiguous SURFACE_STATE structures, one for each
1705 * supported auxiliary surface mode.
1708 alloc_surface_states(struct u_upload_mgr
*mgr
,
1709 struct iris_state_ref
*ref
,
1710 unsigned aux_usages
)
1712 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1714 /* If this changes, update this to explicitly align pointers */
1715 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1717 assert(aux_usages
!= 0);
1720 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1721 SURFACE_STATE_ALIGNMENT
);
1723 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1729 fill_surface_state(struct isl_device
*isl_dev
,
1731 struct iris_resource
*res
,
1732 struct isl_view
*view
,
1735 struct isl_surf_fill_state_info f
= {
1738 .mocs
= mocs(res
->bo
),
1739 .address
= res
->bo
->gtt_offset
+ res
->offset
,
1742 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1743 f
.aux_surf
= &res
->aux
.surf
;
1744 f
.aux_usage
= aux_usage
;
1745 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1747 struct iris_bo
*clear_bo
= NULL
;
1748 uint64_t clear_offset
= 0;
1750 iris_resource_get_clear_color(res
, &clear_bo
, &clear_offset
);
1752 f
.clear_address
= clear_bo
->gtt_offset
+ clear_offset
;
1753 f
.use_clear_address
= isl_dev
->info
->gen
> 9;
1757 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1761 * The pipe->create_sampler_view() driver hook.
1763 static struct pipe_sampler_view
*
1764 iris_create_sampler_view(struct pipe_context
*ctx
,
1765 struct pipe_resource
*tex
,
1766 const struct pipe_sampler_view
*tmpl
)
1768 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1769 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1770 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1771 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1776 /* initialize base object */
1778 isv
->base
.context
= ctx
;
1779 isv
->base
.texture
= NULL
;
1780 pipe_reference_init(&isv
->base
.reference
, 1);
1781 pipe_resource_reference(&isv
->base
.texture
, tex
);
1783 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1784 struct iris_resource
*zres
, *sres
;
1785 const struct util_format_description
*desc
=
1786 util_format_description(tmpl
->format
);
1788 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1790 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1793 isv
->res
= (struct iris_resource
*) tex
;
1795 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1796 &isv
->surface_state
,
1797 isv
->res
->aux
.sampler_usages
);
1801 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1803 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1804 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1805 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1807 const struct iris_format_info fmt
=
1808 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1810 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1812 isv
->view
= (struct isl_view
) {
1814 .swizzle
= (struct isl_swizzle
) {
1815 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1816 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1817 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1818 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1823 /* Fill out SURFACE_STATE for this view. */
1824 if (tmpl
->target
!= PIPE_BUFFER
) {
1825 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1826 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1827 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1828 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1829 isv
->view
.array_len
=
1830 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1832 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1834 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1836 /* If we have a multisampled depth buffer, do not create a sampler
1837 * surface state with HiZ.
1839 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1842 map
+= SURFACE_STATE_ALIGNMENT
;
1845 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
1846 isv
->view
.format
, isv
->view
.swizzle
,
1847 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1854 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1855 struct pipe_sampler_view
*state
)
1857 struct iris_sampler_view
*isv
= (void *) state
;
1858 pipe_resource_reference(&state
->texture
, NULL
);
1859 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1864 * The pipe->create_surface() driver hook.
1866 * In Gallium nomenclature, "surfaces" are a view of a resource that
1867 * can be bound as a render target or depth/stencil buffer.
1869 static struct pipe_surface
*
1870 iris_create_surface(struct pipe_context
*ctx
,
1871 struct pipe_resource
*tex
,
1872 const struct pipe_surface
*tmpl
)
1874 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1875 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1876 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1877 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1878 struct pipe_surface
*psurf
= &surf
->base
;
1879 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1884 pipe_reference_init(&psurf
->reference
, 1);
1885 pipe_resource_reference(&psurf
->texture
, tex
);
1886 psurf
->context
= ctx
;
1887 psurf
->format
= tmpl
->format
;
1888 psurf
->width
= tex
->width0
;
1889 psurf
->height
= tex
->height0
;
1890 psurf
->texture
= tex
;
1891 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1892 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1893 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1895 isl_surf_usage_flags_t usage
= 0;
1897 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1898 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1899 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1901 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1903 const struct iris_format_info fmt
=
1904 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1906 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1907 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1908 /* Framebuffer validation will reject this invalid case, but it
1909 * hasn't had the opportunity yet. In the meantime, we need to
1910 * avoid hitting ISL asserts about unsupported formats below.
1916 struct isl_view
*view
= &surf
->view
;
1917 *view
= (struct isl_view
) {
1919 .base_level
= tmpl
->u
.tex
.level
,
1921 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1922 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1923 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1927 surf
->clear_color
= res
->aux
.clear_color
;
1929 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1930 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1931 ISL_SURF_USAGE_STENCIL_BIT
))
1935 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1936 &surf
->surface_state
,
1937 res
->aux
.possible_usages
);
1941 if (!isl_format_is_compressed(res
->surf
.format
)) {
1942 /* This is a normal surface. Fill out a SURFACE_STATE for each possible
1943 * auxiliary surface mode and return the pipe_surface.
1945 unsigned aux_modes
= res
->aux
.possible_usages
;
1947 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1949 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
1951 map
+= SURFACE_STATE_ALIGNMENT
;
1957 /* The resource has a compressed format, which is not renderable, but we
1958 * have a renderable view format. We must be attempting to upload blocks
1959 * of compressed data via an uncompressed view.
1961 * In this case, we can assume there are no auxiliary buffers, a single
1962 * miplevel, and that the resource is single-sampled. Gallium may try
1963 * and create an uncompressed view with multiple layers, however.
1965 assert(!isl_format_is_compressed(fmt
.fmt
));
1966 assert(res
->aux
.possible_usages
== 1 << ISL_AUX_USAGE_NONE
);
1967 assert(res
->surf
.samples
== 1);
1968 assert(view
->levels
== 1);
1970 struct isl_surf isl_surf
;
1971 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1973 if (view
->base_level
> 0) {
1974 /* We can't rely on the hardware's miplevel selection with such
1975 * a substantial lie about the format, so we select a single image
1976 * using the Tile X/Y Offset fields. In this case, we can't handle
1977 * multiple array slices.
1979 * On Broadwell, HALIGN and VALIGN are specified in pixels and are
1980 * hard-coded to align to exactly the block size of the compressed
1981 * texture. This means that, when reinterpreted as a non-compressed
1982 * texture, the tile offsets may be anything and we can't rely on
1985 * Return NULL to force the state tracker to take fallback paths.
1987 if (view
->array_len
> 1 || GEN_GEN
== 8)
1990 const bool is_3d
= res
->surf
.dim
== ISL_SURF_DIM_3D
;
1991 isl_surf_get_image_surf(&screen
->isl_dev
, &res
->surf
,
1993 is_3d
? 0 : view
->base_array_layer
,
1994 is_3d
? view
->base_array_layer
: 0,
1996 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1998 /* We use address and tile offsets to access a single level/layer
1999 * as a subimage, so reset level/layer so it doesn't offset again.
2001 view
->base_array_layer
= 0;
2002 view
->base_level
= 0;
2004 /* Level 0 doesn't require tile offsets, and the hardware can find
2005 * array slices using QPitch even with the format override, so we
2006 * can allow layers in this case. Copy the original ISL surface.
2008 memcpy(&isl_surf
, &res
->surf
, sizeof(isl_surf
));
2011 /* Scale down the image dimensions by the block size. */
2012 const struct isl_format_layout
*fmtl
=
2013 isl_format_get_layout(res
->surf
.format
);
2014 isl_surf
.format
= fmt
.fmt
;
2015 isl_surf
.logical_level0_px
= isl_surf_get_logical_level0_el(&isl_surf
);
2016 isl_surf
.phys_level0_sa
= isl_surf_get_phys_level0_el(&isl_surf
);
2017 tile_x_sa
/= fmtl
->bw
;
2018 tile_y_sa
/= fmtl
->bh
;
2020 psurf
->width
= isl_surf
.logical_level0_px
.width
;
2021 psurf
->height
= isl_surf
.logical_level0_px
.height
;
2023 struct isl_surf_fill_state_info f
= {
2026 .mocs
= mocs(res
->bo
),
2027 .address
= res
->bo
->gtt_offset
+ offset_B
,
2028 .x_offset_sa
= tile_x_sa
,
2029 .y_offset_sa
= tile_y_sa
,
2032 isl_surf_fill_state_s(&screen
->isl_dev
, map
, &f
);
2038 fill_default_image_param(struct brw_image_param
*param
)
2040 memset(param
, 0, sizeof(*param
));
2041 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
2042 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
2043 * detailed explanation of these parameters.
2045 param
->swizzling
[0] = 0xff;
2046 param
->swizzling
[1] = 0xff;
2050 fill_buffer_image_param(struct brw_image_param
*param
,
2051 enum pipe_format pfmt
,
2054 const unsigned cpp
= util_format_get_blocksize(pfmt
);
2056 fill_default_image_param(param
);
2057 param
->size
[0] = size
/ cpp
;
2058 param
->stride
[0] = cpp
;
2061 #define isl_surf_fill_image_param(x, ...)
2062 #define fill_default_image_param(x, ...)
2063 #define fill_buffer_image_param(x, ...)
2067 * The pipe->set_shader_images() driver hook.
2070 iris_set_shader_images(struct pipe_context
*ctx
,
2071 enum pipe_shader_type p_stage
,
2072 unsigned start_slot
, unsigned count
,
2073 const struct pipe_image_view
*p_images
)
2075 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2076 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2077 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2078 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2079 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2081 struct iris_genx_state
*genx
= ice
->state
.genx
;
2082 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
2085 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
2087 for (unsigned i
= 0; i
< count
; i
++) {
2088 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
2090 if (p_images
&& p_images
[i
].resource
) {
2091 const struct pipe_image_view
*img
= &p_images
[i
];
2092 struct iris_resource
*res
= (void *) img
->resource
;
2094 // XXX: these are not retained forever, use a separate uploader?
2096 alloc_surface_states(ice
->state
.surface_uploader
,
2097 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
2101 util_copy_image_view(&iv
->base
, img
);
2103 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
2105 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
2107 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
2108 enum isl_format isl_fmt
=
2109 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2111 bool untyped_fallback
= false;
2113 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2114 /* On Gen8, try to use typed surfaces reads (which support a
2115 * limited number of formats), and if not possible, fall back
2118 untyped_fallback
= GEN_GEN
== 8 &&
2119 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2121 if (untyped_fallback
)
2122 isl_fmt
= ISL_FORMAT_RAW
;
2124 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2127 if (res
->base
.target
!= PIPE_BUFFER
) {
2128 struct isl_view view
= {
2130 .base_level
= img
->u
.tex
.level
,
2132 .base_array_layer
= img
->u
.tex
.first_layer
,
2133 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2134 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2138 if (untyped_fallback
) {
2139 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2140 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2143 /* Images don't support compression */
2144 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2146 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2148 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
2150 map
+= SURFACE_STATE_ALIGNMENT
;
2154 isl_surf_fill_image_param(&screen
->isl_dev
,
2155 &image_params
[start_slot
+ i
],
2158 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2159 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2161 fill_buffer_surface_state(&screen
->isl_dev
, res
, map
,
2162 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2163 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2164 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2165 img
->format
, img
->u
.buf
.size
);
2168 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2169 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2170 fill_default_image_param(&image_params
[start_slot
+ i
]);
2174 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2176 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2177 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2179 /* Broadwell also needs brw_image_params re-uploaded */
2181 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2182 shs
->sysvals_need_upload
= true;
2188 * The pipe->set_sampler_views() driver hook.
2191 iris_set_sampler_views(struct pipe_context
*ctx
,
2192 enum pipe_shader_type p_stage
,
2193 unsigned start
, unsigned count
,
2194 struct pipe_sampler_view
**views
)
2196 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2197 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2198 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2200 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2202 for (unsigned i
= 0; i
< count
; i
++) {
2203 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2204 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2205 &shs
->textures
[start
+ i
], pview
);
2206 struct iris_sampler_view
*view
= (void *) pview
;
2208 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2209 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2213 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2215 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2216 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2220 * The pipe->set_tess_state() driver hook.
2223 iris_set_tess_state(struct pipe_context
*ctx
,
2224 const float default_outer_level
[4],
2225 const float default_inner_level
[2])
2227 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2228 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2230 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2231 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2233 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2234 shs
->sysvals_need_upload
= true;
2238 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2240 struct iris_surface
*surf
= (void *) p_surf
;
2241 pipe_resource_reference(&p_surf
->texture
, NULL
);
2242 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2247 iris_set_clip_state(struct pipe_context
*ctx
,
2248 const struct pipe_clip_state
*state
)
2250 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2251 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2253 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2255 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2256 shs
->sysvals_need_upload
= true;
2260 * The pipe->set_polygon_stipple() driver hook.
2263 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2264 const struct pipe_poly_stipple
*state
)
2266 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2267 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2268 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2272 * The pipe->set_sample_mask() driver hook.
2275 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2277 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2279 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2280 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2282 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2283 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2287 * The pipe->set_scissor_states() driver hook.
2289 * This corresponds to our SCISSOR_RECT state structures. It's an
2290 * exact match, so we just store them, and memcpy them out later.
2293 iris_set_scissor_states(struct pipe_context
*ctx
,
2294 unsigned start_slot
,
2295 unsigned num_scissors
,
2296 const struct pipe_scissor_state
*rects
)
2298 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2300 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2301 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2302 /* If the scissor was out of bounds and got clamped to 0 width/height
2303 * at the bounds, the subtraction of 1 from maximums could produce a
2304 * negative number and thus not clip anything. Instead, just provide
2305 * a min > max scissor inside the bounds, which produces the expected
2308 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2309 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2312 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2313 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2314 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2319 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2323 * The pipe->set_stencil_ref() driver hook.
2325 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2328 iris_set_stencil_ref(struct pipe_context
*ctx
,
2329 const struct pipe_stencil_ref
*state
)
2331 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2332 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2334 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2336 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2340 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2342 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2346 * The pipe->set_viewport_states() driver hook.
2348 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2349 * the guardband yet, as we need the framebuffer dimensions, but we can
2350 * at least fill out the rest.
2353 iris_set_viewport_states(struct pipe_context
*ctx
,
2354 unsigned start_slot
,
2356 const struct pipe_viewport_state
*states
)
2358 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2360 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2362 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2364 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2365 !ice
->state
.cso_rast
->depth_clip_far
))
2366 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2370 * The pipe->set_framebuffer_state() driver hook.
2372 * Sets the current draw FBO, including color render targets, depth,
2373 * and stencil buffers.
2376 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2377 const struct pipe_framebuffer_state
*state
)
2379 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2380 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2381 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2382 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2383 struct iris_resource
*zres
;
2384 struct iris_resource
*stencil_res
;
2386 unsigned samples
= util_framebuffer_get_num_samples(state
);
2387 unsigned layers
= util_framebuffer_get_num_layers(state
);
2389 if (cso
->samples
!= samples
) {
2390 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2393 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2394 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2397 if ((cso
->layers
== 0) != (layers
== 0)) {
2398 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2401 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2402 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2405 util_copy_framebuffer_state(cso
, state
);
2406 cso
->samples
= samples
;
2407 cso
->layers
= layers
;
2409 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2411 struct isl_view view
= {
2414 .base_array_layer
= 0,
2416 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2419 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2422 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2425 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2426 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2428 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2431 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2433 info
.depth_surf
= &zres
->surf
;
2434 info
.depth_address
= zres
->bo
->gtt_offset
+ zres
->offset
;
2435 info
.mocs
= mocs(zres
->bo
);
2437 view
.format
= zres
->surf
.format
;
2439 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2440 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2441 info
.hiz_surf
= &zres
->aux
.surf
;
2442 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2447 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2448 info
.stencil_surf
= &stencil_res
->surf
;
2449 info
.stencil_address
= stencil_res
->bo
->gtt_offset
+ stencil_res
->offset
;
2451 view
.format
= stencil_res
->surf
.format
;
2452 info
.mocs
= mocs(stencil_res
->bo
);
2457 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2459 /* Make a null surface for unbound buffers */
2460 void *null_surf_map
=
2461 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2462 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2463 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2464 isl_extent3d(MAX2(cso
->width
, 1),
2465 MAX2(cso
->height
, 1),
2466 cso
->layers
? cso
->layers
: 1));
2467 ice
->state
.null_fb
.offset
+=
2468 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2470 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2472 /* Render target change */
2473 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2475 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2477 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2480 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2481 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2483 /* The PIPE_CONTROL command description says:
2485 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2486 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2487 * Target Cache Flush by enabling this bit. When render target flush
2488 * is set due to new association of BTI, PS Scoreboard Stall bit must
2489 * be set in this packet."
2491 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2492 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2493 "workaround: RT BTI change [draw]",
2494 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2495 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2500 * The pipe->set_constant_buffer() driver hook.
2502 * This uploads any constant data in user buffers, and references
2503 * any UBO resources containing constant data.
2506 iris_set_constant_buffer(struct pipe_context
*ctx
,
2507 enum pipe_shader_type p_stage
, unsigned index
,
2508 const struct pipe_constant_buffer
*input
)
2510 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2511 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2512 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2513 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2515 if (input
&& input
->buffer_size
&& (input
->buffer
|| input
->user_buffer
)) {
2516 shs
->bound_cbufs
|= 1u << index
;
2518 if (input
->user_buffer
) {
2520 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2521 u_upload_alloc(ice
->ctx
.const_uploader
, 0, input
->buffer_size
, 64,
2522 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2524 if (!cbuf
->buffer
) {
2525 /* Allocation was unsuccessful - just unbind */
2526 iris_set_constant_buffer(ctx
, p_stage
, index
, NULL
);
2531 memcpy(map
, input
->user_buffer
, input
->buffer_size
);
2532 } else if (input
->buffer
) {
2533 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2535 cbuf
->buffer_offset
= input
->buffer_offset
;
2537 MIN2(input
->buffer_size
,
2538 iris_resource_bo(cbuf
->buffer
)->size
- cbuf
->buffer_offset
);
2541 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2542 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2544 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2545 &shs
->constbuf_surf_state
[index
],
2548 shs
->bound_cbufs
&= ~(1u << index
);
2549 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2550 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2553 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2554 // XXX: maybe not necessary all the time...?
2555 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2556 // XXX: pull model we may need actual new bindings...
2557 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2561 upload_sysvals(struct iris_context
*ice
,
2562 gl_shader_stage stage
)
2564 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2565 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2567 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2568 if (!shader
|| shader
->num_system_values
== 0)
2571 assert(shader
->num_cbufs
> 0);
2573 unsigned sysval_cbuf_index
= shader
->num_cbufs
- 1;
2574 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[sysval_cbuf_index
];
2575 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t);
2576 uint32_t *map
= NULL
;
2578 assert(sysval_cbuf_index
< PIPE_MAX_CONSTANT_BUFFERS
);
2579 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2580 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2582 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2583 uint32_t sysval
= shader
->system_values
[i
];
2586 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2588 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2589 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2590 struct brw_image_param
*param
=
2591 &genx
->shaders
[stage
].image_param
[img
];
2593 assert(offset
< sizeof(struct brw_image_param
));
2594 value
= ((uint32_t *) param
)[offset
];
2596 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2598 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2599 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2600 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2601 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2602 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2603 if (stage
== MESA_SHADER_TESS_CTRL
) {
2604 value
= ice
->state
.vertices_per_patch
;
2606 assert(stage
== MESA_SHADER_TESS_EVAL
);
2607 const struct shader_info
*tcs_info
=
2608 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2610 value
= tcs_info
->tess
.tcs_vertices_out
;
2612 value
= ice
->state
.vertices_per_patch
;
2614 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2615 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2616 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2617 value
= fui(ice
->state
.default_outer_level
[i
]);
2618 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2619 value
= fui(ice
->state
.default_inner_level
[0]);
2620 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2621 value
= fui(ice
->state
.default_inner_level
[1]);
2623 assert(!"unhandled system value");
2629 cbuf
->buffer_size
= upload_size
;
2630 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
,
2631 &shs
->constbuf_surf_state
[sysval_cbuf_index
], false);
2633 shs
->sysvals_need_upload
= false;
2637 * The pipe->set_shader_buffers() driver hook.
2639 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2640 * SURFACE_STATE here, as the buffer offset may change each time.
2643 iris_set_shader_buffers(struct pipe_context
*ctx
,
2644 enum pipe_shader_type p_stage
,
2645 unsigned start_slot
, unsigned count
,
2646 const struct pipe_shader_buffer
*buffers
,
2647 unsigned writable_bitmask
)
2649 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2650 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2651 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2653 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2655 shs
->bound_ssbos
&= ~modified_bits
;
2656 shs
->writable_ssbos
&= ~modified_bits
;
2657 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2659 for (unsigned i
= 0; i
< count
; i
++) {
2660 if (buffers
&& buffers
[i
].buffer
) {
2661 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2662 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2663 struct iris_state_ref
*surf_state
=
2664 &shs
->ssbo_surf_state
[start_slot
+ i
];
2665 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2666 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2668 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2670 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2672 iris_upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2674 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2676 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2677 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2679 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2680 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2685 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2689 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2695 * The pipe->set_vertex_buffers() driver hook.
2697 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2700 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2701 unsigned start_slot
, unsigned count
,
2702 const struct pipe_vertex_buffer
*buffers
)
2704 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2705 struct iris_genx_state
*genx
= ice
->state
.genx
;
2707 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2709 for (unsigned i
= 0; i
< count
; i
++) {
2710 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2711 struct iris_vertex_buffer_state
*state
=
2712 &genx
->vertex_buffers
[start_slot
+ i
];
2715 pipe_resource_reference(&state
->resource
, NULL
);
2719 /* We may see user buffers that are NULL bindings. */
2720 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2722 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2723 struct iris_resource
*res
= (void *) state
->resource
;
2726 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2727 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2730 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2731 vb
.VertexBufferIndex
= start_slot
+ i
;
2732 vb
.AddressModifyEnable
= true;
2733 vb
.BufferPitch
= buffer
->stride
;
2735 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2736 vb
.BufferStartingAddress
=
2737 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2738 vb
.MOCS
= mocs(res
->bo
);
2740 vb
.NullVertexBuffer
= true;
2745 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2749 * Gallium CSO for vertex elements.
2751 struct iris_vertex_element_state
{
2752 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2753 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2754 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2755 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2760 * The pipe->create_vertex_elements() driver hook.
2762 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2763 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2764 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2765 * needed. In these cases we will need information available at draw time.
2766 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2767 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2768 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2771 iris_create_vertex_elements(struct pipe_context
*ctx
,
2773 const struct pipe_vertex_element
*state
)
2775 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2776 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2777 struct iris_vertex_element_state
*cso
=
2778 malloc(sizeof(struct iris_vertex_element_state
));
2782 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2784 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2787 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2788 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2791 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2793 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2794 ve
.Component0Control
= VFCOMP_STORE_0
;
2795 ve
.Component1Control
= VFCOMP_STORE_0
;
2796 ve
.Component2Control
= VFCOMP_STORE_0
;
2797 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2800 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2804 for (int i
= 0; i
< count
; i
++) {
2805 const struct iris_format_info fmt
=
2806 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2807 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2808 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2810 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2811 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2812 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2813 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2815 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2816 : VFCOMP_STORE_1_FP
;
2819 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2820 ve
.EdgeFlagEnable
= false;
2821 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2823 ve
.SourceElementOffset
= state
[i
].src_offset
;
2824 ve
.SourceElementFormat
= fmt
.fmt
;
2825 ve
.Component0Control
= comp
[0];
2826 ve
.Component1Control
= comp
[1];
2827 ve
.Component2Control
= comp
[2];
2828 ve
.Component3Control
= comp
[3];
2831 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2832 vi
.VertexElementIndex
= i
;
2833 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2834 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2837 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2838 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2841 /* An alternative version of the last VE and VFI is stored so it
2842 * can be used at draw time in case Vertex Shader uses EdgeFlag
2845 const unsigned edgeflag_index
= count
- 1;
2846 const struct iris_format_info fmt
=
2847 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2848 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2849 ve
.EdgeFlagEnable
= true ;
2850 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2852 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2853 ve
.SourceElementFormat
= fmt
.fmt
;
2854 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2855 ve
.Component1Control
= VFCOMP_STORE_0
;
2856 ve
.Component2Control
= VFCOMP_STORE_0
;
2857 ve
.Component3Control
= VFCOMP_STORE_0
;
2859 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2860 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2861 * at draw time, as it should change if SGVs are emitted.
2863 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2864 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2872 * The pipe->bind_vertex_elements_state() driver hook.
2875 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2877 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2878 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2879 struct iris_vertex_element_state
*new_cso
= state
;
2881 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2882 * we need to re-emit it to ensure we're overriding the right one.
2884 if (new_cso
&& cso_changed(count
))
2885 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2887 ice
->state
.cso_vertex_elements
= state
;
2888 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2892 * The pipe->create_stream_output_target() driver hook.
2894 * "Target" here refers to a destination buffer. We translate this into
2895 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2896 * know which buffer this represents, or whether we ought to zero the
2897 * write-offsets, or append. Those are handled in the set() hook.
2899 static struct pipe_stream_output_target
*
2900 iris_create_stream_output_target(struct pipe_context
*ctx
,
2901 struct pipe_resource
*p_res
,
2902 unsigned buffer_offset
,
2903 unsigned buffer_size
)
2905 struct iris_resource
*res
= (void *) p_res
;
2906 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2910 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2912 pipe_reference_init(&cso
->base
.reference
, 1);
2913 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2914 cso
->base
.buffer_offset
= buffer_offset
;
2915 cso
->base
.buffer_size
= buffer_size
;
2916 cso
->base
.context
= ctx
;
2918 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
2919 buffer_offset
+ buffer_size
);
2921 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2927 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2928 struct pipe_stream_output_target
*state
)
2930 struct iris_stream_output_target
*cso
= (void *) state
;
2932 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2933 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2939 * The pipe->set_stream_output_targets() driver hook.
2941 * At this point, we know which targets are bound to a particular index,
2942 * and also whether we want to append or start over. We can finish the
2943 * 3DSTATE_SO_BUFFER packets we started earlier.
2946 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2947 unsigned num_targets
,
2948 struct pipe_stream_output_target
**targets
,
2949 const unsigned *offsets
)
2951 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2952 struct iris_genx_state
*genx
= ice
->state
.genx
;
2953 uint32_t *so_buffers
= genx
->so_buffers
;
2955 const bool active
= num_targets
> 0;
2956 if (ice
->state
.streamout_active
!= active
) {
2957 ice
->state
.streamout_active
= active
;
2958 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2960 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2961 * it's a non-pipelined command. If we're switching streamout on, we
2962 * may have missed emitting it earlier, so do so now. (We're already
2963 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2966 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2969 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2970 struct iris_stream_output_target
*tgt
=
2971 (void *) ice
->state
.so_target
[i
];
2973 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2975 flush
|= iris_flush_bits_for_history(res
);
2976 iris_dirty_for_history(ice
, res
);
2979 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2980 "make streamout results visible", flush
);
2984 for (int i
= 0; i
< 4; i
++) {
2985 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2986 i
< num_targets
? targets
[i
] : NULL
);
2989 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2993 for (unsigned i
= 0; i
< 4; i
++,
2994 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2996 struct iris_stream_output_target
*tgt
= (void *) ice
->state
.so_target
[i
];
2997 unsigned offset
= offsets
[i
];
3000 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
3001 sob
.SOBufferIndex
= i
;
3005 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
3007 /* Note that offsets[i] will either be 0, causing us to zero
3008 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
3009 * "continue appending at the existing offset."
3011 assert(offset
== 0 || offset
== 0xFFFFFFFF);
3013 /* We might be called by Begin (offset = 0), Pause, then Resume
3014 * (offset = 0xFFFFFFFF) before ever drawing (where these commands
3015 * will actually be sent to the GPU). In this case, we don't want
3016 * to append - we still want to do our initial zeroing.
3021 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3022 sob
.SurfaceBaseAddress
=
3023 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3024 sob
.SOBufferEnable
= true;
3025 sob
.StreamOffsetWriteEnable
= true;
3026 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3027 sob
.MOCS
= mocs(res
->bo
);
3029 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3031 sob
.SOBufferIndex
= i
;
3032 sob
.StreamOffset
= offset
;
3033 sob
.StreamOutputBufferOffsetAddress
=
3034 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3035 tgt
->offset
.offset
);
3039 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3043 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3044 * 3DSTATE_STREAMOUT packets.
3046 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3047 * hardware to record. We can create it entirely based on the shader, with
3048 * no dynamic state dependencies.
3050 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3051 * state-based settings. We capture the shader-related ones here, and merge
3052 * the rest in at draw time.
3055 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3056 const struct brw_vue_map
*vue_map
)
3058 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3059 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3060 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3061 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3063 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3065 memset(so_decl
, 0, sizeof(so_decl
));
3067 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3068 * command feels strange -- each dword pair contains a SO_DECL per stream.
3070 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3071 const struct pipe_stream_output
*output
= &info
->output
[i
];
3072 const int buffer
= output
->output_buffer
;
3073 const int varying
= output
->register_index
;
3074 const unsigned stream_id
= output
->stream
;
3075 assert(stream_id
< MAX_VERTEX_STREAMS
);
3077 buffer_mask
[stream_id
] |= 1 << buffer
;
3079 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3081 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3082 * array. Instead, it simply increments DstOffset for the following
3083 * input by the number of components that should be skipped.
3085 * Our hardware is unusual in that it requires us to program SO_DECLs
3086 * for fake "hole" components, rather than simply taking the offset
3087 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3088 * program as many size = 4 holes as we can, then a final hole to
3089 * accommodate the final 1, 2, or 3 remaining.
3091 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3093 while (skip_components
> 0) {
3094 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3096 .OutputBufferSlot
= output
->output_buffer
,
3097 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3099 skip_components
-= 4;
3102 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3104 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3105 .OutputBufferSlot
= output
->output_buffer
,
3106 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3108 ((1 << output
->num_components
) - 1) << output
->start_component
,
3111 if (decls
[stream_id
] > max_decls
)
3112 max_decls
= decls
[stream_id
];
3115 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3116 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3117 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3119 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3120 int urb_entry_read_offset
= 0;
3121 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3122 urb_entry_read_offset
;
3124 /* We always read the whole vertex. This could be reduced at some
3125 * point by reading less and offsetting the register index in the
3128 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3129 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3130 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3131 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3132 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3133 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3134 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3135 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3137 /* Set buffer pitches; 0 means unbound. */
3138 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3139 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3140 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3141 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3144 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3145 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3146 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3147 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3148 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3149 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3150 list
.NumEntries0
= decls
[0];
3151 list
.NumEntries1
= decls
[1];
3152 list
.NumEntries2
= decls
[2];
3153 list
.NumEntries3
= decls
[3];
3156 for (int i
= 0; i
< max_decls
; i
++) {
3157 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3158 entry
.Stream0Decl
= so_decl
[0][i
];
3159 entry
.Stream1Decl
= so_decl
[1][i
];
3160 entry
.Stream2Decl
= so_decl
[2][i
];
3161 entry
.Stream3Decl
= so_decl
[3][i
];
3169 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3170 const struct brw_vue_map
*last_vue_map
,
3171 bool two_sided_color
,
3172 unsigned *out_offset
,
3173 unsigned *out_length
)
3175 /* The compiler computes the first URB slot without considering COL/BFC
3176 * swizzling (because it doesn't know whether it's enabled), so we need
3177 * to do that here too. This may result in a smaller offset, which
3180 const unsigned first_slot
=
3181 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3183 /* This becomes the URB read offset (counted in pairs of slots). */
3184 assert(first_slot
% 2 == 0);
3185 *out_offset
= first_slot
/ 2;
3187 /* We need to adjust the inputs read to account for front/back color
3188 * swizzling, as it can make the URB length longer.
3190 for (int c
= 0; c
<= 1; c
++) {
3191 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3192 /* If two sided color is enabled, the fragment shader's gl_Color
3193 * (COL0) input comes from either the gl_FrontColor (COL0) or
3194 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3196 if (two_sided_color
)
3197 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3199 /* If front color isn't written, we opt to give them back color
3200 * instead of an undefined value. Switch from COL to BFC.
3202 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3203 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3204 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3209 /* Compute the minimum URB Read Length necessary for the FS inputs.
3211 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3212 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3214 * "This field should be set to the minimum length required to read the
3215 * maximum source attribute. The maximum source attribute is indicated
3216 * by the maximum value of the enabled Attribute # Source Attribute if
3217 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3218 * enable is not set.
3219 * read_length = ceiling((max_source_attr + 1) / 2)
3221 * [errata] Corruption/Hang possible if length programmed larger than
3224 * Similar text exists for Ivy Bridge.
3226 * We find the last URB slot that's actually read by the FS.
3228 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3229 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3230 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3233 /* The URB read length is the difference of the two, counted in pairs. */
3234 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3238 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3239 const struct iris_context
*ice
,
3240 unsigned urb_read_offset
,
3241 unsigned sprite_coord_enables
)
3243 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3244 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3245 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3246 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3247 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3249 /* XXX: this should be generated when putting programs in place */
3251 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3252 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3253 if (input_index
< 0 || input_index
>= 16)
3256 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3257 &attr_overrides
[input_index
];
3258 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3260 /* Viewport and Layer are stored in the VUE header. We need to override
3261 * them to zero if earlier stages didn't write them, as GL requires that
3262 * they read back as zero when not explicitly set.
3265 case VARYING_SLOT_VIEWPORT
:
3266 case VARYING_SLOT_LAYER
:
3267 attr
->ComponentOverrideX
= true;
3268 attr
->ComponentOverrideW
= true;
3269 attr
->ConstantSource
= CONST_0000
;
3271 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3272 attr
->ComponentOverrideY
= true;
3273 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3274 attr
->ComponentOverrideZ
= true;
3277 case VARYING_SLOT_PRIMITIVE_ID
:
3278 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3280 attr
->ComponentOverrideX
= true;
3281 attr
->ComponentOverrideY
= true;
3282 attr
->ComponentOverrideZ
= true;
3283 attr
->ComponentOverrideW
= true;
3284 attr
->ConstantSource
= PRIM_ID
;
3292 if (sprite_coord_enables
& (1 << input_index
))
3295 /* If there was only a back color written but not front, use back
3296 * as the color instead of undefined.
3298 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3299 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3300 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3301 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3303 /* Not written by the previous stage - undefined. */
3305 attr
->ComponentOverrideX
= true;
3306 attr
->ComponentOverrideY
= true;
3307 attr
->ComponentOverrideZ
= true;
3308 attr
->ComponentOverrideW
= true;
3309 attr
->ConstantSource
= CONST_0001_FLOAT
;
3313 /* Compute the location of the attribute relative to the read offset,
3314 * which is counted in 256-bit increments (two 128-bit VUE slots).
3316 const int source_attr
= slot
- 2 * urb_read_offset
;
3317 assert(source_attr
>= 0 && source_attr
<= 32);
3318 attr
->SourceAttribute
= source_attr
;
3320 /* If we are doing two-sided color, and the VUE slot following this one
3321 * represents a back-facing color, then we need to instruct the SF unit
3322 * to do back-facing swizzling.
3324 if (cso_rast
->light_twoside
&&
3325 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3326 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3327 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3328 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3329 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3332 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3333 for (int i
= 0; i
< 16; i
++)
3334 sbes
.Attribute
[i
] = attr_overrides
[i
];
3339 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3340 const struct iris_rasterizer_state
*cso
)
3342 unsigned overrides
= 0;
3344 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3345 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3347 for (int i
= 0; i
< 8; i
++) {
3348 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3349 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3350 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3357 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3359 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3360 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3361 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3362 const struct shader_info
*fs_info
=
3363 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3365 unsigned urb_read_offset
, urb_read_length
;
3366 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3367 ice
->shaders
.last_vue_map
,
3368 cso_rast
->light_twoside
,
3369 &urb_read_offset
, &urb_read_length
);
3371 unsigned sprite_coord_overrides
=
3372 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3374 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3375 sbe
.AttributeSwizzleEnable
= true;
3376 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3377 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3378 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3379 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3380 sbe
.ForceVertexURBEntryReadOffset
= true;
3381 sbe
.ForceVertexURBEntryReadLength
= true;
3382 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3383 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3385 for (int i
= 0; i
< 32; i
++) {
3386 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3391 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3394 /* ------------------------------------------------------------------- */
3397 * Populate VS program key fields based on the current state.
3400 iris_populate_vs_key(const struct iris_context
*ice
,
3401 const struct shader_info
*info
,
3402 struct brw_vs_prog_key
*key
)
3404 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3406 if (info
->clip_distance_array_size
== 0 &&
3407 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3408 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3412 * Populate TCS program key fields based on the current state.
3415 iris_populate_tcs_key(const struct iris_context
*ice
,
3416 struct brw_tcs_prog_key
*key
)
3421 * Populate TES program key fields based on the current state.
3424 iris_populate_tes_key(const struct iris_context
*ice
,
3425 struct brw_tes_prog_key
*key
)
3430 * Populate GS program key fields based on the current state.
3433 iris_populate_gs_key(const struct iris_context
*ice
,
3434 struct brw_gs_prog_key
*key
)
3439 * Populate FS program key fields based on the current state.
3442 iris_populate_fs_key(const struct iris_context
*ice
,
3443 struct brw_wm_prog_key
*key
)
3445 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3446 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3447 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3448 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3449 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3451 key
->nr_color_regions
= fb
->nr_cbufs
;
3453 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3455 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3457 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3459 /* XXX: only bother if COL0/1 are read */
3460 key
->flat_shade
= rast
->flatshade
;
3462 key
->persample_interp
= rast
->force_persample_interp
;
3463 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3465 key
->coherent_fb_fetch
= true;
3467 key
->force_dual_color_blend
=
3468 screen
->driconf
.dual_color_blend_by_location
&&
3469 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3471 /* TODO: support key->force_dual_color_blend for Unigine */
3472 /* TODO: Respect glHint for key->high_quality_derivatives */
3476 iris_populate_cs_key(const struct iris_context
*ice
,
3477 struct brw_cs_prog_key
*key
)
3482 KSP(const struct iris_compiled_shader
*shader
)
3484 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3485 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3488 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3489 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3490 * this WA on C0 stepping.
3492 * TODO: Fill out SamplerCount for prefetching?
3495 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3496 pkt.KernelStartPointer = KSP(shader); \
3497 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3498 shader->bt.size_bytes / 4; \
3499 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3501 pkt.DispatchGRFStartRegisterForURBData = \
3502 prog_data->dispatch_grf_start_reg; \
3503 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3504 pkt.prefix##URBEntryReadOffset = 0; \
3506 pkt.StatisticsEnable = true; \
3507 pkt.Enable = true; \
3509 if (prog_data->total_scratch) { \
3510 struct iris_bo *bo = \
3511 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3512 uint32_t scratch_addr = bo->gtt_offset; \
3513 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3514 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3518 * Encode most of 3DSTATE_VS based on the compiled shader.
3521 iris_store_vs_state(struct iris_context
*ice
,
3522 const struct gen_device_info
*devinfo
,
3523 struct iris_compiled_shader
*shader
)
3525 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3526 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3528 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3529 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3530 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3531 vs
.SIMD8DispatchEnable
= true;
3532 vs
.UserClipDistanceCullTestEnableBitmask
=
3533 vue_prog_data
->cull_distance_mask
;
3538 * Encode most of 3DSTATE_HS based on the compiled shader.
3541 iris_store_tcs_state(struct iris_context
*ice
,
3542 const struct gen_device_info
*devinfo
,
3543 struct iris_compiled_shader
*shader
)
3545 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3546 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3547 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3549 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3550 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3552 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3553 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3554 hs
.IncludeVertexHandles
= true;
3557 hs
.DispatchMode
= vue_prog_data
->dispatch_mode
;
3558 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
3564 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3567 iris_store_tes_state(struct iris_context
*ice
,
3568 const struct gen_device_info
*devinfo
,
3569 struct iris_compiled_shader
*shader
)
3571 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3572 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3573 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3575 uint32_t *te_state
= (void *) shader
->derived_data
;
3576 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3578 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3579 te
.Partitioning
= tes_prog_data
->partitioning
;
3580 te
.OutputTopology
= tes_prog_data
->output_topology
;
3581 te
.TEDomain
= tes_prog_data
->domain
;
3583 te
.MaximumTessellationFactorOdd
= 63.0;
3584 te
.MaximumTessellationFactorNotOdd
= 64.0;
3587 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3588 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3590 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3591 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3592 ds
.ComputeWCoordinateEnable
=
3593 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3595 ds
.UserClipDistanceCullTestEnableBitmask
=
3596 vue_prog_data
->cull_distance_mask
;
3602 * Encode most of 3DSTATE_GS based on the compiled shader.
3605 iris_store_gs_state(struct iris_context
*ice
,
3606 const struct gen_device_info
*devinfo
,
3607 struct iris_compiled_shader
*shader
)
3609 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3610 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3611 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3613 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3614 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3616 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3617 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3618 gs
.ControlDataHeaderSize
=
3619 gs_prog_data
->control_data_header_size_hwords
;
3620 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3621 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3622 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3623 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3624 gs
.ReorderMode
= TRAILING
;
3625 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3626 gs
.MaximumNumberofThreads
=
3627 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3628 : (devinfo
->max_gs_threads
- 1);
3630 if (gs_prog_data
->static_vertex_count
!= -1) {
3631 gs
.StaticOutput
= true;
3632 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3634 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3636 gs
.UserClipDistanceCullTestEnableBitmask
=
3637 vue_prog_data
->cull_distance_mask
;
3639 const int urb_entry_write_offset
= 1;
3640 const uint32_t urb_entry_output_length
=
3641 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3642 urb_entry_write_offset
;
3644 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3645 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3650 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3653 iris_store_fs_state(struct iris_context
*ice
,
3654 const struct gen_device_info
*devinfo
,
3655 struct iris_compiled_shader
*shader
)
3657 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3658 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3660 uint32_t *ps_state
= (void *) shader
->derived_data
;
3661 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3663 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3664 ps
.VectorMaskEnable
= true;
3665 // XXX: WABTPPrefetchDisable, see above, drop at C0
3666 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3667 shader
->bt
.size_bytes
/ 4;
3668 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3669 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3671 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3673 /* From the documentation for this packet:
3674 * "If the PS kernel does not need the Position XY Offsets to
3675 * compute a Position Value, then this field should be programmed
3676 * to POSOFFSET_NONE."
3678 * "SW Recommendation: If the PS kernel needs the Position Offsets
3679 * to compute a Position XY value, this field should match Position
3680 * ZW Interpolation Mode to ensure a consistent position.xyzw
3683 * We only require XY sample offsets. So, this recommendation doesn't
3684 * look useful at the moment. We might need this in future.
3686 ps
.PositionXYOffsetSelect
=
3687 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3688 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3689 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3690 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3692 // XXX: Disable SIMD32 with 16x MSAA
3694 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3695 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3696 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3697 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3698 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3699 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3701 ps
.KernelStartPointer0
=
3702 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3703 ps
.KernelStartPointer1
=
3704 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3705 ps
.KernelStartPointer2
=
3706 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3708 if (prog_data
->total_scratch
) {
3709 struct iris_bo
*bo
=
3710 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3711 MESA_SHADER_FRAGMENT
);
3712 uint32_t scratch_addr
= bo
->gtt_offset
;
3713 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3714 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3718 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3719 psx
.PixelShaderValid
= true;
3720 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3721 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3722 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3723 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3724 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3725 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3726 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3729 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3730 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3732 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3739 * Compute the size of the derived data (shader command packets).
3741 * This must match the data written by the iris_store_xs_state() functions.
3744 iris_store_cs_state(struct iris_context
*ice
,
3745 const struct gen_device_info
*devinfo
,
3746 struct iris_compiled_shader
*shader
)
3748 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3749 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3750 void *map
= shader
->derived_data
;
3752 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3753 desc
.KernelStartPointer
= KSP(shader
);
3754 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3755 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3756 desc
.SharedLocalMemorySize
=
3757 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3758 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3759 desc
.CrossThreadConstantDataReadLength
=
3760 cs_prog_data
->push
.cross_thread
.regs
;
3765 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3767 assert(cache_id
<= IRIS_CACHE_BLORP
);
3769 static const unsigned dwords
[] = {
3770 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3771 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3772 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3773 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3775 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3776 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3777 [IRIS_CACHE_BLORP
] = 0,
3780 return sizeof(uint32_t) * dwords
[cache_id
];
3784 * Create any state packets corresponding to the given shader stage
3785 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3786 * This means that we can look up a program in the in-memory cache and
3787 * get most of the state packet without having to reconstruct it.
3790 iris_store_derived_program_state(struct iris_context
*ice
,
3791 enum iris_program_cache_id cache_id
,
3792 struct iris_compiled_shader
*shader
)
3794 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3795 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3799 iris_store_vs_state(ice
, devinfo
, shader
);
3801 case IRIS_CACHE_TCS
:
3802 iris_store_tcs_state(ice
, devinfo
, shader
);
3804 case IRIS_CACHE_TES
:
3805 iris_store_tes_state(ice
, devinfo
, shader
);
3808 iris_store_gs_state(ice
, devinfo
, shader
);
3811 iris_store_fs_state(ice
, devinfo
, shader
);
3814 iris_store_cs_state(ice
, devinfo
, shader
);
3815 case IRIS_CACHE_BLORP
:
3822 /* ------------------------------------------------------------------- */
3824 static const uint32_t push_constant_opcodes
[] = {
3825 [MESA_SHADER_VERTEX
] = 21,
3826 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3827 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3828 [MESA_SHADER_GEOMETRY
] = 22,
3829 [MESA_SHADER_FRAGMENT
] = 23,
3830 [MESA_SHADER_COMPUTE
] = 0,
3834 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3836 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3838 iris_use_pinned_bo(batch
, state_bo
, false);
3840 return ice
->state
.unbound_tex
.offset
;
3844 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3846 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3847 if (!ice
->state
.null_fb
.res
)
3848 return use_null_surface(batch
, ice
);
3850 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3852 iris_use_pinned_bo(batch
, state_bo
, false);
3854 return ice
->state
.null_fb
.offset
;
3858 surf_state_offset_for_aux(struct iris_resource
*res
,
3860 enum isl_aux_usage aux_usage
)
3862 return SURFACE_STATE_ALIGNMENT
*
3863 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3867 surf_state_update_clear_value(struct iris_batch
*batch
,
3868 struct iris_resource
*res
,
3869 struct iris_state_ref
*state
,
3871 enum isl_aux_usage aux_usage
)
3873 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
3874 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
3875 uint64_t real_offset
= state
->offset
+
3876 IRIS_MEMZONE_BINDER_START
;
3877 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
3878 uint32_t clear_offset
= offset_into_bo
+
3879 isl_dev
->ss
.clear_value_offset
+
3880 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
3882 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
3883 res
->aux
.clear_color_bo
,
3884 res
->aux
.clear_color_offset
,
3885 isl_dev
->ss
.clear_value_size
);
3889 update_clear_value(struct iris_context
*ice
,
3890 struct iris_batch
*batch
,
3891 struct iris_resource
*res
,
3892 struct iris_state_ref
*state
,
3894 struct isl_view
*view
)
3896 struct iris_screen
*screen
= batch
->screen
;
3897 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3899 /* We only need to update the clear color in the surface state for gen8 and
3900 * gen9. Newer gens can read it directly from the clear color state buffer.
3902 if (devinfo
->gen
> 9)
3905 if (devinfo
->gen
== 9) {
3906 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
3907 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
3910 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3912 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
3915 } else if (devinfo
->gen
== 8) {
3916 pipe_resource_reference(&state
->res
, NULL
);
3917 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
3918 state
, res
->aux
.possible_usages
);
3920 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3921 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
3922 map
+= SURFACE_STATE_ALIGNMENT
;
3928 * Add a surface to the validation list, as well as the buffer containing
3929 * the corresponding SURFACE_STATE.
3931 * Returns the binding table entry (offset to SURFACE_STATE).
3934 use_surface(struct iris_context
*ice
,
3935 struct iris_batch
*batch
,
3936 struct pipe_surface
*p_surf
,
3938 enum isl_aux_usage aux_usage
)
3940 struct iris_surface
*surf
= (void *) p_surf
;
3941 struct iris_resource
*res
= (void *) p_surf
->texture
;
3943 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3944 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3947 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
3948 if (res
->aux
.clear_color_bo
)
3949 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
3951 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
3952 sizeof(surf
->clear_color
)) != 0) {
3953 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
3954 res
->aux
.possible_usages
, &surf
->view
);
3955 surf
->clear_color
= res
->aux
.clear_color
;
3959 return surf
->surface_state
.offset
+
3960 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
3964 use_sampler_view(struct iris_context
*ice
,
3965 struct iris_batch
*batch
,
3966 struct iris_sampler_view
*isv
)
3969 enum isl_aux_usage aux_usage
=
3970 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
3972 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3973 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3975 if (isv
->res
->aux
.bo
) {
3976 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
3977 if (isv
->res
->aux
.clear_color_bo
)
3978 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
3979 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
3980 sizeof(isv
->clear_color
)) != 0) {
3981 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
3982 isv
->res
->aux
.sampler_usages
, &isv
->view
);
3983 isv
->clear_color
= isv
->res
->aux
.clear_color
;
3987 return isv
->surface_state
.offset
+
3988 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
3993 use_ubo_ssbo(struct iris_batch
*batch
,
3994 struct iris_context
*ice
,
3995 struct pipe_shader_buffer
*buf
,
3996 struct iris_state_ref
*surf_state
,
4000 return use_null_surface(batch
, ice
);
4002 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
4003 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
4005 return surf_state
->offset
;
4009 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
4010 struct iris_shader_state
*shs
, int i
)
4012 struct iris_image_view
*iv
= &shs
->image
[i
];
4013 struct iris_resource
*res
= (void *) iv
->base
.resource
;
4016 return use_null_surface(batch
, ice
);
4018 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
4020 iris_use_pinned_bo(batch
, res
->bo
, write
);
4021 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4024 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4026 return iv
->surface_state
.offset
;
4029 #define push_bt_entry(addr) \
4030 assert(addr >= binder_addr); \
4031 assert(s < shader->bt.size_bytes / sizeof(uint32_t)); \
4032 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4034 #define bt_assert(section) \
4035 if (!pin_only && shader->bt.used_mask[section] != 0) \
4036 assert(shader->bt.offsets[section] == s);
4039 * Populate the binding table for a given shader stage.
4041 * This fills out the table of pointers to surfaces required by the shader,
4042 * and also adds those buffers to the validation list so the kernel can make
4043 * resident before running our batch.
4046 iris_populate_binding_table(struct iris_context
*ice
,
4047 struct iris_batch
*batch
,
4048 gl_shader_stage stage
,
4051 const struct iris_binder
*binder
= &ice
->state
.binder
;
4052 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
4053 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4057 struct iris_binding_table
*bt
= &shader
->bt
;
4058 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4059 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4060 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4062 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
4063 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4066 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4068 /* TCS passthrough doesn't need a binding table. */
4069 assert(stage
== MESA_SHADER_TESS_CTRL
);
4073 if (stage
== MESA_SHADER_COMPUTE
&&
4074 shader
->bt
.used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
]) {
4075 /* surface for gl_NumWorkGroups */
4076 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4077 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4078 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4079 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4080 push_bt_entry(grid_state
->offset
);
4083 if (stage
== MESA_SHADER_FRAGMENT
) {
4084 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4085 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4086 if (cso_fb
->nr_cbufs
) {
4087 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4089 if (cso_fb
->cbufs
[i
]) {
4090 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4091 ice
->state
.draw_aux_usage
[i
]);
4093 addr
= use_null_fb_surface(batch
, ice
);
4095 push_bt_entry(addr
);
4098 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4099 push_bt_entry(addr
);
4103 #define foreach_surface_used(index, group) \
4105 for (int index = 0; index < bt->sizes[group]; index++) \
4106 if (iris_group_index_to_bti(bt, group, index) != \
4107 IRIS_SURFACE_NOT_USED)
4109 foreach_surface_used(i
, IRIS_SURFACE_GROUP_TEXTURE
) {
4110 struct iris_sampler_view
*view
= shs
->textures
[i
];
4111 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4112 : use_null_surface(batch
, ice
);
4113 push_bt_entry(addr
);
4116 foreach_surface_used(i
, IRIS_SURFACE_GROUP_IMAGE
) {
4117 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4118 push_bt_entry(addr
);
4121 foreach_surface_used(i
, IRIS_SURFACE_GROUP_UBO
) {
4124 if (i
== bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] - 1) {
4125 if (ish
->const_data
) {
4126 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data
), false);
4127 iris_use_pinned_bo(batch
, iris_resource_bo(ish
->const_data_state
.res
),
4129 addr
= ish
->const_data_state
.offset
;
4131 /* This can only happen with INTEL_DISABLE_COMPACT_BINDING_TABLE=1. */
4132 addr
= use_null_surface(batch
, ice
);
4135 addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4136 &shs
->constbuf_surf_state
[i
], false);
4139 push_bt_entry(addr
);
4142 foreach_surface_used(i
, IRIS_SURFACE_GROUP_SSBO
) {
4144 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4145 shs
->writable_ssbos
& (1u << i
));
4146 push_bt_entry(addr
);
4150 /* XXX: YUV surfaces not implemented yet */
4151 bt_assert(plane_start
[1], ...);
4152 bt_assert(plane_start
[2], ...);
4157 iris_use_optional_res(struct iris_batch
*batch
,
4158 struct pipe_resource
*res
,
4162 struct iris_bo
*bo
= iris_resource_bo(res
);
4163 iris_use_pinned_bo(batch
, bo
, writeable
);
4168 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4169 struct pipe_surface
*zsbuf
,
4170 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4175 struct iris_resource
*zres
, *sres
;
4176 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4179 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4181 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4182 cso_zsa
->depth_writes_enabled
);
4187 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4191 /* ------------------------------------------------------------------- */
4194 * Pin any BOs which were installed by a previous batch, and restored
4195 * via the hardware logical context mechanism.
4197 * We don't need to re-emit all state every batch - the hardware context
4198 * mechanism will save and restore it for us. This includes pointers to
4199 * various BOs...which won't exist unless we ask the kernel to pin them
4200 * by adding them to the validation list.
4202 * We can skip buffers if we've re-emitted those packets, as we're
4203 * overwriting those stale pointers with new ones, and don't actually
4204 * refer to the old BOs.
4207 iris_restore_render_saved_bos(struct iris_context
*ice
,
4208 struct iris_batch
*batch
,
4209 const struct pipe_draw_info
*draw
)
4211 struct iris_genx_state
*genx
= ice
->state
.genx
;
4213 const uint64_t clean
= ~ice
->state
.dirty
;
4215 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4216 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4219 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4220 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4223 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4224 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4227 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4228 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4231 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4232 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4235 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4236 for (int i
= 0; i
< 4; i
++) {
4237 struct iris_stream_output_target
*tgt
=
4238 (void *) ice
->state
.so_target
[i
];
4240 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4242 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4248 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4249 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4252 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4253 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4258 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4260 for (int i
= 0; i
< 4; i
++) {
4261 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4263 if (range
->length
== 0)
4266 /* Range block is a binding table index, map back to UBO index. */
4267 unsigned block_index
= iris_bti_to_group_index(
4268 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4269 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4271 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4272 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4275 iris_use_pinned_bo(batch
, res
->bo
, false);
4277 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4281 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4282 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4283 /* Re-pin any buffers referred to by the binding table. */
4284 iris_populate_binding_table(ice
, batch
, stage
, true);
4288 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4289 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4290 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4292 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4295 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4296 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4297 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4300 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4301 iris_use_pinned_bo(batch
, bo
, false);
4303 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4305 if (prog_data
->total_scratch
> 0) {
4306 struct iris_bo
*bo
=
4307 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4308 iris_use_pinned_bo(batch
, bo
, true);
4314 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4315 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4316 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4317 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4320 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4321 /* This draw didn't emit a new index buffer, so we are inheriting the
4322 * older index buffer. This draw didn't need it, but future ones may.
4324 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4325 iris_use_pinned_bo(batch
, bo
, false);
4328 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4329 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4331 const int i
= u_bit_scan64(&bound
);
4332 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4333 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4339 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4340 struct iris_batch
*batch
,
4341 const struct pipe_grid_info
*grid
)
4343 const uint64_t clean
= ~ice
->state
.dirty
;
4345 const int stage
= MESA_SHADER_COMPUTE
;
4346 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4348 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4349 /* Re-pin any buffers referred to by the binding table. */
4350 iris_populate_binding_table(ice
, batch
, stage
, true);
4353 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4355 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4357 if ((clean
& IRIS_DIRTY_SAMPLER_STATES_CS
) &&
4358 (clean
& IRIS_DIRTY_BINDINGS_CS
) &&
4359 (clean
& IRIS_DIRTY_CONSTANTS_CS
) &&
4360 (clean
& IRIS_DIRTY_CS
)) {
4361 iris_use_optional_res(batch
, ice
->state
.last_res
.cs_desc
, false);
4364 if (clean
& IRIS_DIRTY_CS
) {
4365 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4368 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4369 iris_use_pinned_bo(batch
, bo
, false);
4371 struct iris_bo
*curbe_bo
=
4372 iris_resource_bo(ice
->state
.last_res
.cs_thread_ids
);
4373 iris_use_pinned_bo(batch
, curbe_bo
, false);
4375 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4377 if (prog_data
->total_scratch
> 0) {
4378 struct iris_bo
*bo
=
4379 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4380 iris_use_pinned_bo(batch
, bo
, true);
4387 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4390 iris_update_surface_base_address(struct iris_batch
*batch
,
4391 struct iris_binder
*binder
)
4393 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4396 flush_for_state_base_change(batch
);
4398 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4399 sba
.SurfaceStateMOCS
= MOCS_WB
;
4400 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4401 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4404 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4408 iris_upload_dirty_render_state(struct iris_context
*ice
,
4409 struct iris_batch
*batch
,
4410 const struct pipe_draw_info
*draw
)
4412 const uint64_t dirty
= ice
->state
.dirty
;
4414 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4417 struct iris_genx_state
*genx
= ice
->state
.genx
;
4418 struct iris_binder
*binder
= &ice
->state
.binder
;
4419 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4420 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4422 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4423 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4424 uint32_t cc_vp_address
;
4426 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4427 uint32_t *cc_vp_map
=
4428 stream_state(batch
, ice
->state
.dynamic_uploader
,
4429 &ice
->state
.last_res
.cc_vp
,
4430 4 * ice
->state
.num_viewports
*
4431 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4432 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4434 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4435 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4436 if (cso_rast
->depth_clip_near
)
4438 if (cso_rast
->depth_clip_far
)
4441 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4442 ccv
.MinimumDepth
= zmin
;
4443 ccv
.MaximumDepth
= zmax
;
4446 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4449 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4450 ptr
.CCViewportPointer
= cc_vp_address
;
4454 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4455 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4456 uint32_t sf_cl_vp_address
;
4458 stream_state(batch
, ice
->state
.dynamic_uploader
,
4459 &ice
->state
.last_res
.sf_cl_vp
,
4460 4 * ice
->state
.num_viewports
*
4461 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4463 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4464 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4465 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4467 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4468 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4469 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4470 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4472 gen_calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4473 state
->scale
[0], state
->scale
[1],
4474 state
->translate
[0], state
->translate
[1],
4475 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4477 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4478 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4479 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4480 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4481 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4482 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4483 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4484 vp
.XMinClipGuardband
= gb_xmin
;
4485 vp
.XMaxClipGuardband
= gb_xmax
;
4486 vp
.YMinClipGuardband
= gb_ymin
;
4487 vp
.YMaxClipGuardband
= gb_ymax
;
4488 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4489 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4490 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4491 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4494 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4497 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4498 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4502 if (dirty
& IRIS_DIRTY_URB
) {
4505 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4506 if (!ice
->shaders
.prog
[i
]) {
4509 struct brw_vue_prog_data
*vue_prog_data
=
4510 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4511 size
[i
] = vue_prog_data
->urb_entry_size
;
4513 assert(size
[i
] != 0);
4516 genX(emit_urb_setup
)(ice
, batch
, size
,
4517 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4518 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4521 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4522 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4523 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4524 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4525 const int header_dwords
= GENX(BLEND_STATE_length
);
4527 /* Always write at least one BLEND_STATE - the final RT message will
4528 * reference BLEND_STATE[0] even if there aren't color writes. There
4529 * may still be alpha testing, computed depth, and so on.
4531 const int rt_dwords
=
4532 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4534 uint32_t blend_offset
;
4535 uint32_t *blend_map
=
4536 stream_state(batch
, ice
->state
.dynamic_uploader
,
4537 &ice
->state
.last_res
.blend
,
4538 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4540 uint32_t blend_state_header
;
4541 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4542 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4543 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4546 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4547 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4549 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4550 ptr
.BlendStatePointer
= blend_offset
;
4551 ptr
.BlendStatePointerValid
= true;
4555 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4556 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4558 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4562 stream_state(batch
, ice
->state
.dynamic_uploader
,
4563 &ice
->state
.last_res
.color_calc
,
4564 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4566 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4567 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4568 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4569 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4570 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4571 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4572 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4574 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4575 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4578 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4579 ptr
.ColorCalcStatePointer
= cc_offset
;
4580 ptr
.ColorCalcStatePointerValid
= true;
4584 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4585 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4588 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4589 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4594 if (shs
->sysvals_need_upload
)
4595 upload_sysvals(ice
, stage
);
4597 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4599 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4600 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4602 /* The Skylake PRM contains the following restriction:
4604 * "The driver must ensure The following case does not occur
4605 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4606 * buffer 3 read length equal to zero committed followed by a
4607 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4610 * To avoid this, we program the buffers in the highest slots.
4611 * This way, slot 0 is only used if slot 3 is also used.
4615 for (int i
= 3; i
>= 0; i
--) {
4616 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4618 if (range
->length
== 0)
4621 /* Range block is a binding table index, map back to UBO index. */
4622 unsigned block_index
= iris_bti_to_group_index(
4623 &shader
->bt
, IRIS_SURFACE_GROUP_UBO
, range
->block
);
4624 assert(block_index
!= IRIS_SURFACE_NOT_USED
);
4626 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[block_index
];
4627 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4629 assert(cbuf
->buffer_offset
% 32 == 0);
4631 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4632 pkt
.ConstantBody
.Buffer
[n
] =
4633 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4634 : ro_bo(batch
->screen
->workaround_bo
, 0);
4641 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4642 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4643 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4644 ptr
._3DCommandSubOpcode
= 38 + stage
;
4645 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4650 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4651 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4652 iris_populate_binding_table(ice
, batch
, stage
, false);
4656 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4657 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4658 !ice
->shaders
.prog
[stage
])
4661 iris_upload_sampler_states(ice
, stage
);
4663 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4664 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4666 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4668 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4669 ptr
._3DCommandSubOpcode
= 43 + stage
;
4670 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4674 if (ice
->state
.need_border_colors
)
4675 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4677 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4678 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4680 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4681 if (ice
->state
.framebuffer
.samples
> 0)
4682 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4686 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4687 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4688 ms
.SampleMask
= ice
->state
.sample_mask
;
4692 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4693 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4696 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4699 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4700 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4701 iris_use_pinned_bo(batch
, cache
->bo
, false);
4703 if (prog_data
->total_scratch
> 0) {
4704 struct iris_bo
*bo
=
4705 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4706 iris_use_pinned_bo(batch
, bo
, true);
4709 if (stage
== MESA_SHADER_FRAGMENT
&& wm_prog_data
->uses_sample_mask
) {
4710 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4711 uint32_t *shader_psx
= ((uint32_t*)shader
->derived_data
) +
4712 GENX(3DSTATE_PS_length
);
4713 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4715 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), &psx_state
, psx
) {
4716 if (wm_prog_data
->post_depth_coverage
)
4717 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4718 else if (wm_prog_data
->inner_coverage
&& cso
->conservative_rasterization
)
4719 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4721 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4724 iris_batch_emit(batch
, shader
->derived_data
,
4725 sizeof(uint32_t) * GENX(3DSTATE_PS_length
));
4726 iris_emit_merge(batch
,
4729 GENX(3DSTATE_PS_EXTRA_length
));
4732 iris_batch_emit(batch
, shader
->derived_data
,
4733 iris_derived_program_state_size(stage
));
4735 if (stage
== MESA_SHADER_TESS_EVAL
) {
4736 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4737 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4738 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4739 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4740 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4745 if (ice
->state
.streamout_active
) {
4746 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4747 iris_batch_emit(batch
, genx
->so_buffers
,
4748 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4749 for (int i
= 0; i
< 4; i
++) {
4750 struct iris_stream_output_target
*tgt
=
4751 (void *) ice
->state
.so_target
[i
];
4754 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4756 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4762 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4763 uint32_t *decl_list
=
4764 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4765 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4768 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4769 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4771 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4772 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4773 sol
.SOFunctionEnable
= true;
4774 sol
.SOStatisticsEnable
= true;
4776 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4777 !ice
->state
.prims_generated_query_active
;
4778 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4781 assert(ice
->state
.streamout
);
4783 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4784 GENX(3DSTATE_STREAMOUT_length
));
4787 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4788 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4792 if (dirty
& IRIS_DIRTY_CLIP
) {
4793 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4794 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4796 bool gs_or_tes
= ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] ||
4797 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4798 bool points_or_lines
= cso_rast
->fill_mode_point_or_line
||
4799 (gs_or_tes
? ice
->shaders
.output_topology_is_points_or_lines
4800 : ice
->state
.prim_is_points_or_lines
);
4802 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4803 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4804 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4805 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4807 cl
.ViewportXYClipTestEnable
= !points_or_lines
;
4809 if (wm_prog_data
->barycentric_interp_modes
&
4810 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4811 cl
.NonPerspectiveBarycentricEnable
= true;
4813 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4814 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4816 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4817 ARRAY_SIZE(cso_rast
->clip
));
4820 if (dirty
& IRIS_DIRTY_RASTER
) {
4821 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4822 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4823 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4827 if (dirty
& IRIS_DIRTY_WM
) {
4828 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4829 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4831 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4832 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4834 wm
.BarycentricInterpolationMode
=
4835 wm_prog_data
->barycentric_interp_modes
;
4837 if (wm_prog_data
->early_fragment_tests
)
4838 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4839 else if (wm_prog_data
->has_side_effects
)
4840 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4842 /* We could skip this bit if color writes are enabled. */
4843 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4844 wm
.ForceThreadDispatchEnable
= ForceON
;
4846 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4849 if (dirty
& IRIS_DIRTY_SBE
) {
4850 iris_emit_sbe(batch
, ice
);
4853 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4854 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4855 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4856 const struct shader_info
*fs_info
=
4857 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4859 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4860 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4861 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4862 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4864 /* The dual source blending docs caution against using SRC1 factors
4865 * when the shader doesn't use a dual source render target write.
4866 * Empirically, this can lead to GPU hangs, and the results are
4867 * undefined anyway, so simply disable blending to avoid the hang.
4869 pb
.ColorBufferBlendEnable
= (cso_blend
->blend_enables
& 1) &&
4870 (!cso_blend
->dual_color_blending
|| wm_prog_data
->dual_src_blend
);
4873 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4874 ARRAY_SIZE(cso_blend
->ps_blend
));
4877 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4878 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4880 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4881 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4882 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4883 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4884 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4886 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4888 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4892 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4893 uint32_t scissor_offset
=
4894 emit_state(batch
, ice
->state
.dynamic_uploader
,
4895 &ice
->state
.last_res
.scissor
,
4896 ice
->state
.scissors
,
4897 sizeof(struct pipe_scissor_state
) *
4898 ice
->state
.num_viewports
, 32);
4900 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4901 ptr
.ScissorRectPointer
= scissor_offset
;
4905 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4906 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4908 /* Do not emit the clear params yets. We need to update the clear value
4911 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
4912 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
4913 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
4915 union isl_color_value clear_value
= { .f32
= { 0, } };
4917 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4918 if (cso_fb
->zsbuf
) {
4919 struct iris_resource
*zres
, *sres
;
4920 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4922 if (zres
&& zres
->aux
.bo
)
4923 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
4926 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
4927 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
4928 clear
.DepthClearValueValid
= true;
4929 clear
.DepthClearValue
= clear_value
.f32
[0];
4931 iris_batch_emit(batch
, clear_params
, clear_length
);
4934 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4935 /* Listen for buffer changes, and also write enable changes. */
4936 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4937 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4940 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4941 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4942 for (int i
= 0; i
< 32; i
++) {
4943 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4948 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4949 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4950 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4953 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4954 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4955 topo
.PrimitiveTopologyType
=
4956 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4960 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4961 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4962 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
4964 if (ice
->state
.vs_uses_draw_params
) {
4965 if (ice
->draw
.draw_params_offset
== 0) {
4966 u_upload_data(ice
->ctx
.stream_uploader
, 0, sizeof(ice
->draw
.params
),
4967 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
4968 &ice
->draw
.draw_params_res
);
4970 assert(ice
->draw
.draw_params_res
);
4972 struct iris_vertex_buffer_state
*state
=
4973 &(ice
->state
.genx
->vertex_buffers
[count
]);
4974 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
4975 struct iris_resource
*res
= (void *) state
->resource
;
4977 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4978 vb
.VertexBufferIndex
= count
;
4979 vb
.AddressModifyEnable
= true;
4981 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
4982 vb
.BufferStartingAddress
=
4983 ro_bo(NULL
, res
->bo
->gtt_offset
+
4984 (int) ice
->draw
.draw_params_offset
);
4985 vb
.MOCS
= mocs(res
->bo
);
4987 dynamic_bound
|= 1ull << count
;
4991 if (ice
->state
.vs_uses_derived_draw_params
) {
4992 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4993 sizeof(ice
->draw
.derived_params
), 4,
4994 &ice
->draw
.derived_params
,
4995 &ice
->draw
.derived_draw_params_offset
,
4996 &ice
->draw
.derived_draw_params_res
);
4998 struct iris_vertex_buffer_state
*state
=
4999 &(ice
->state
.genx
->vertex_buffers
[count
]);
5000 pipe_resource_reference(&state
->resource
,
5001 ice
->draw
.derived_draw_params_res
);
5002 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
5004 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
5005 vb
.VertexBufferIndex
= count
;
5006 vb
.AddressModifyEnable
= true;
5009 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
5010 vb
.BufferStartingAddress
=
5011 ro_bo(NULL
, res
->bo
->gtt_offset
+
5012 (int) ice
->draw
.derived_draw_params_offset
);
5013 vb
.MOCS
= mocs(res
->bo
);
5015 dynamic_bound
|= 1ull << count
;
5020 /* The VF cache designers cut corners, and made the cache key's
5021 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
5022 * 32 bits of the address. If you have two vertex buffers which get
5023 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
5024 * you can get collisions (even within a single batch).
5026 * So, we need to do a VF cache invalidate if the buffer for a VB
5027 * slot slot changes [48:32] address bits from the previous time.
5029 unsigned flush_flags
= 0;
5031 uint64_t bound
= dynamic_bound
;
5033 const int i
= u_bit_scan64(&bound
);
5034 uint16_t high_bits
= 0;
5036 struct iris_resource
*res
=
5037 (void *) genx
->vertex_buffers
[i
].resource
;
5039 iris_use_pinned_bo(batch
, res
->bo
, false);
5041 high_bits
= res
->bo
->gtt_offset
>> 32ull;
5042 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
5043 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5044 PIPE_CONTROL_CS_STALL
;
5045 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5051 iris_emit_pipe_control_flush(batch
,
5052 "workaround: VF cache 32-bit key [VB]",
5056 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5059 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5060 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5061 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5065 bound
= dynamic_bound
;
5067 const int i
= u_bit_scan64(&bound
);
5068 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5069 sizeof(uint32_t) * vb_dwords
);
5075 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5076 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5077 const unsigned entries
= MAX2(cso
->count
, 1);
5078 if (!(ice
->state
.vs_needs_sgvs_element
||
5079 ice
->state
.vs_uses_derived_draw_params
||
5080 ice
->state
.vs_needs_edge_flag
)) {
5081 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5082 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5084 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5085 const unsigned dyn_count
= cso
->count
+
5086 ice
->state
.vs_needs_sgvs_element
+
5087 ice
->state
.vs_uses_derived_draw_params
;
5089 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5092 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5094 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5095 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5096 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5097 uint32_t *ve_pack_dest
=
5098 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5099 GENX(VERTEX_ELEMENT_STATE_length
)];
5101 if (ice
->state
.vs_needs_sgvs_element
) {
5102 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5103 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5104 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5106 ve
.VertexBufferIndex
=
5107 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5108 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5109 ve
.Component0Control
= base_ctrl
;
5110 ve
.Component1Control
= base_ctrl
;
5111 ve
.Component2Control
= VFCOMP_STORE_0
;
5112 ve
.Component3Control
= VFCOMP_STORE_0
;
5114 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5116 if (ice
->state
.vs_uses_derived_draw_params
) {
5117 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5119 ve
.VertexBufferIndex
=
5120 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5121 ice
->state
.vs_uses_draw_params
;
5122 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5123 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5124 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5125 ve
.Component2Control
= VFCOMP_STORE_0
;
5126 ve
.Component3Control
= VFCOMP_STORE_0
;
5128 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5130 if (ice
->state
.vs_needs_edge_flag
) {
5131 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5132 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5135 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5136 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5139 if (!ice
->state
.vs_needs_edge_flag
) {
5140 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5141 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5143 assert(cso
->count
> 0);
5144 const unsigned edgeflag_index
= cso
->count
- 1;
5145 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5146 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5147 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5149 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5150 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5151 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5152 vi
.VertexElementIndex
= edgeflag_index
+
5153 ice
->state
.vs_needs_sgvs_element
+
5154 ice
->state
.vs_uses_derived_draw_params
;
5156 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5157 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5159 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5160 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5164 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5165 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5166 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5167 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5169 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5170 if (vs_prog_data
->uses_vertexid
) {
5171 sgv
.VertexIDEnable
= true;
5172 sgv
.VertexIDComponentNumber
= 2;
5173 sgv
.VertexIDElementOffset
=
5174 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5177 if (vs_prog_data
->uses_instanceid
) {
5178 sgv
.InstanceIDEnable
= true;
5179 sgv
.InstanceIDComponentNumber
= 3;
5180 sgv
.InstanceIDElementOffset
=
5181 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5186 if (dirty
& IRIS_DIRTY_VF
) {
5187 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5188 if (draw
->primitive_restart
) {
5189 vf
.IndexedDrawCutIndexEnable
= true;
5190 vf
.CutIndex
= draw
->restart_index
;
5195 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5196 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5197 vf
.StatisticsEnable
= true;
5201 /* TODO: Gen8 PMA fix */
5205 iris_upload_render_state(struct iris_context
*ice
,
5206 struct iris_batch
*batch
,
5207 const struct pipe_draw_info
*draw
)
5209 bool use_predicate
= ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5211 /* Always pin the binder. If we're emitting new binding table pointers,
5212 * we need it. If not, we're probably inheriting old tables via the
5213 * context, and need it anyway. Since true zero-bindings cases are
5214 * practically non-existent, just pin it and avoid last_res tracking.
5216 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5218 if (!batch
->contains_draw
) {
5219 iris_restore_render_saved_bos(ice
, batch
, draw
);
5220 batch
->contains_draw
= true;
5223 iris_upload_dirty_render_state(ice
, batch
, draw
);
5225 if (draw
->index_size
> 0) {
5228 if (draw
->has_user_indices
) {
5229 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5230 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5231 &offset
, &ice
->state
.last_res
.index_buffer
);
5233 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5234 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5236 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5237 draw
->index
.resource
);
5241 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5243 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
5244 ib
.IndexFormat
= draw
->index_size
>> 1;
5246 ib
.BufferSize
= bo
->size
- offset
;
5247 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
5250 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5251 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5252 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5253 iris_emit_pipe_control_flush(batch
,
5254 "workaround: VF cache 32-bit key [IB]",
5255 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5256 PIPE_CONTROL_CS_STALL
);
5257 ice
->state
.last_index_bo_high_bits
= high_bits
;
5261 #define _3DPRIM_END_OFFSET 0x2420
5262 #define _3DPRIM_START_VERTEX 0x2430
5263 #define _3DPRIM_VERTEX_COUNT 0x2434
5264 #define _3DPRIM_INSTANCE_COUNT 0x2438
5265 #define _3DPRIM_START_INSTANCE 0x243C
5266 #define _3DPRIM_BASE_VERTEX 0x2440
5268 if (draw
->indirect
) {
5269 if (draw
->indirect
->indirect_draw_count
) {
5270 use_predicate
= true;
5272 struct iris_bo
*draw_count_bo
=
5273 iris_resource_bo(draw
->indirect
->indirect_draw_count
);
5274 unsigned draw_count_offset
=
5275 draw
->indirect
->indirect_draw_count_offset
;
5277 iris_emit_pipe_control_flush(batch
,
5278 "ensure indirect draw buffer is flushed",
5279 PIPE_CONTROL_FLUSH_ENABLE
);
5281 if (ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
) {
5282 static const uint32_t math
[] = {
5284 /* Compute (draw index < draw count).
5285 * We do this by subtracting and storing the carry bit.
5287 MI_ALU2(LOAD
, SRCA
, R0
),
5288 MI_ALU2(LOAD
, SRCB
, R1
),
5290 MI_ALU2(STORE
, R3
, CF
),
5291 /* Compute (subtracting result & MI_PREDICATE). */
5292 MI_ALU2(LOAD
, SRCA
, R3
),
5293 MI_ALU2(LOAD
, SRCB
, R2
),
5295 MI_ALU2(STORE
, R3
, ACCU
),
5298 /* Upload the current draw count from the draw parameters
5301 ice
->vtbl
.load_register_mem32(batch
, CS_GPR(1), draw_count_bo
,
5303 /* Zero the top 32-bits of GPR1. */
5304 ice
->vtbl
.load_register_imm32(batch
, CS_GPR(1) + 4, 0);
5305 /* Upload the id of the current primitive to GPR0. */
5306 ice
->vtbl
.load_register_imm64(batch
, CS_GPR(0), draw
->drawid
);
5308 iris_batch_emit(batch
, math
, sizeof(math
));
5310 /* Store result of MI_MATH computations to MI_PREDICATE_RESULT. */
5311 ice
->vtbl
.load_register_reg64(batch
,
5312 MI_PREDICATE_RESULT
, CS_GPR(3));
5314 uint32_t mi_predicate
;
5316 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
5317 ice
->vtbl
.load_register_imm64(batch
, MI_PREDICATE_SRC1
,
5319 /* Upload the current draw count from the draw parameters buffer
5320 * to MI_PREDICATE_SRC0.
5322 ice
->vtbl
.load_register_mem32(batch
, MI_PREDICATE_SRC0
,
5323 draw_count_bo
, draw_count_offset
);
5324 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
5325 ice
->vtbl
.load_register_imm32(batch
, MI_PREDICATE_SRC0
+ 4, 0);
5327 if (draw
->drawid
== 0) {
5328 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
5329 MI_PREDICATE_COMBINEOP_SET
|
5330 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5332 /* While draw_index < draw_count the predicate's result will be
5333 * (draw_index == draw_count) ^ TRUE = TRUE
5334 * When draw_index == draw_count the result is
5335 * (TRUE) ^ TRUE = FALSE
5336 * After this all results will be:
5337 * (FALSE) ^ FALSE = FALSE
5339 mi_predicate
= MI_PREDICATE
| MI_PREDICATE_LOADOP_LOAD
|
5340 MI_PREDICATE_COMBINEOP_XOR
|
5341 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
;
5343 iris_batch_emit(batch
, &mi_predicate
, sizeof(uint32_t));
5346 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5349 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5350 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5351 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5353 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5354 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5355 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5357 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5358 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5359 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5361 if (draw
->index_size
) {
5362 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5363 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5364 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5366 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5367 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5368 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5371 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5372 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5373 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5375 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5376 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5380 } else if (draw
->count_from_stream_output
) {
5381 struct iris_stream_output_target
*so
=
5382 (void *) draw
->count_from_stream_output
;
5384 /* XXX: Replace with actual cache tracking */
5385 iris_emit_pipe_control_flush(batch
,
5386 "draw count from stream output stall",
5387 PIPE_CONTROL_CS_STALL
);
5389 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5390 lrm
.RegisterAddress
= CS_GPR(0);
5392 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5394 if (so
->base
.buffer_offset
)
5395 iris_math_add32_gpr0(ice
, batch
, -so
->base
.buffer_offset
);
5396 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
5397 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
5399 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5400 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5401 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5402 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5405 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5406 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5407 prim
.PredicateEnable
= use_predicate
;
5409 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5410 prim
.IndirectParameterEnable
= true;
5412 prim
.StartInstanceLocation
= draw
->start_instance
;
5413 prim
.InstanceCount
= draw
->instance_count
;
5414 prim
.VertexCountPerInstance
= draw
->count
;
5416 // XXX: this is probably bonkers.
5417 prim
.StartVertexLocation
= draw
->start
;
5419 if (draw
->index_size
) {
5420 prim
.BaseVertexLocation
+= draw
->index_bias
;
5422 prim
.StartVertexLocation
+= draw
->index_bias
;
5425 //prim.BaseVertexLocation = ...;
5431 iris_upload_compute_state(struct iris_context
*ice
,
5432 struct iris_batch
*batch
,
5433 const struct pipe_grid_info
*grid
)
5435 const uint64_t dirty
= ice
->state
.dirty
;
5436 struct iris_screen
*screen
= batch
->screen
;
5437 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5438 struct iris_binder
*binder
= &ice
->state
.binder
;
5439 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5440 struct iris_compiled_shader
*shader
=
5441 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5442 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5443 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5445 /* Always pin the binder. If we're emitting new binding table pointers,
5446 * we need it. If not, we're probably inheriting old tables via the
5447 * context, and need it anyway. Since true zero-bindings cases are
5448 * practically non-existent, just pin it and avoid last_res tracking.
5450 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5452 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->sysvals_need_upload
)
5453 upload_sysvals(ice
, MESA_SHADER_COMPUTE
);
5455 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5456 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5458 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5459 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5461 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5462 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5464 if (ice
->state
.need_border_colors
)
5465 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5467 if (dirty
& IRIS_DIRTY_CS
) {
5468 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5470 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5471 * the only bits that are changed are scoreboard related: Scoreboard
5472 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5473 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5476 iris_emit_pipe_control_flush(batch
,
5477 "workaround: stall before MEDIA_VFE_STATE",
5478 PIPE_CONTROL_CS_STALL
);
5480 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5481 if (prog_data
->total_scratch
) {
5482 struct iris_bo
*bo
=
5483 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5484 MESA_SHADER_COMPUTE
);
5485 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5486 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5489 vfe
.MaximumNumberofThreads
=
5490 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5492 vfe
.ResetGatewayTimer
=
5493 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5496 vfe
.BypassGatewayControl
= true;
5498 vfe
.NumberofURBEntries
= 2;
5499 vfe
.URBEntryAllocationSize
= 2;
5501 vfe
.CURBEAllocationSize
=
5502 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5503 cs_prog_data
->push
.cross_thread
.regs
, 2);
5507 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5508 if (dirty
& IRIS_DIRTY_CS
) {
5509 uint32_t curbe_data_offset
= 0;
5510 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5511 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5512 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5513 uint32_t *curbe_data_map
=
5514 stream_state(batch
, ice
->state
.dynamic_uploader
,
5515 &ice
->state
.last_res
.cs_thread_ids
,
5516 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5517 &curbe_data_offset
);
5518 assert(curbe_data_map
);
5519 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5520 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5522 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5523 curbe
.CURBETotalDataLength
=
5524 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5525 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5529 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5530 IRIS_DIRTY_BINDINGS_CS
|
5531 IRIS_DIRTY_CONSTANTS_CS
|
5533 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5535 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5536 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5537 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5540 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5541 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5543 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5544 load
.InterfaceDescriptorTotalLength
=
5545 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5546 load
.InterfaceDescriptorDataStartAddress
=
5547 emit_state(batch
, ice
->state
.dynamic_uploader
,
5548 &ice
->state
.last_res
.cs_desc
, desc
, sizeof(desc
), 64);
5552 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5553 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5554 uint32_t right_mask
;
5557 right_mask
= ~0u >> (32 - remainder
);
5559 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5561 #define GPGPU_DISPATCHDIMX 0x2500
5562 #define GPGPU_DISPATCHDIMY 0x2504
5563 #define GPGPU_DISPATCHDIMZ 0x2508
5565 if (grid
->indirect
) {
5566 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5567 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5568 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5569 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5570 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5572 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5573 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5574 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5576 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5577 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5578 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5582 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5583 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5584 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5585 ggw
.ThreadDepthCounterMaximum
= 0;
5586 ggw
.ThreadHeightCounterMaximum
= 0;
5587 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5588 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5589 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5590 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5591 ggw
.RightExecutionMask
= right_mask
;
5592 ggw
.BottomExecutionMask
= 0xffffffff;
5595 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5597 if (!batch
->contains_draw
) {
5598 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5599 batch
->contains_draw
= true;
5604 * State module teardown.
5607 iris_destroy_state(struct iris_context
*ice
)
5609 struct iris_genx_state
*genx
= ice
->state
.genx
;
5611 pipe_resource_reference(&ice
->draw
.draw_params_res
, NULL
);
5612 pipe_resource_reference(&ice
->draw
.derived_draw_params_res
, NULL
);
5614 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5616 const int i
= u_bit_scan64(&bound_vbs
);
5617 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5619 free(ice
->state
.genx
);
5621 for (int i
= 0; i
< 4; i
++) {
5622 pipe_so_target_reference(&ice
->state
.so_target
[i
], NULL
);
5625 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5626 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5628 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5630 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5631 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5632 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5633 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5634 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5635 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5637 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5638 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5639 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5641 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5642 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5643 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5645 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5646 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5647 &shs
->textures
[i
], NULL
);
5651 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5652 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5654 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5655 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5657 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5658 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5659 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5660 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5661 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5662 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5663 pipe_resource_reference(&ice
->state
.last_res
.cs_thread_ids
, NULL
);
5664 pipe_resource_reference(&ice
->state
.last_res
.cs_desc
, NULL
);
5667 /* ------------------------------------------------------------------- */
5670 iris_rebind_buffer(struct iris_context
*ice
,
5671 struct iris_resource
*res
,
5672 uint64_t old_address
)
5674 struct pipe_context
*ctx
= &ice
->ctx
;
5675 struct iris_screen
*screen
= (void *) ctx
->screen
;
5676 struct iris_genx_state
*genx
= ice
->state
.genx
;
5678 assert(res
->base
.target
== PIPE_BUFFER
);
5680 /* Buffers can't be framebuffer attachments, nor display related,
5681 * and we don't have upstream Clover support.
5683 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5684 PIPE_BIND_RENDER_TARGET
|
5685 PIPE_BIND_BLENDABLE
|
5686 PIPE_BIND_DISPLAY_TARGET
|
5688 PIPE_BIND_COMPUTE_RESOURCE
|
5689 PIPE_BIND_GLOBAL
)));
5691 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5692 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5694 const int i
= u_bit_scan64(&bound_vbs
);
5695 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5697 /* Update the CPU struct */
5698 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5699 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5700 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5702 if (*addr
== old_address
) {
5703 *addr
= res
->bo
->gtt_offset
;
5704 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5709 /* No need to handle these:
5710 * - PIPE_BIND_INDEX_BUFFER (emitted for every indexed draw)
5711 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5712 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5715 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5716 /* XXX: be careful about resetting vs appending... */
5720 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5721 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5722 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5724 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5725 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5726 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5727 while (bound_cbufs
) {
5728 const int i
= u_bit_scan(&bound_cbufs
);
5729 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5730 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5732 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5733 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5734 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5739 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5740 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5741 while (bound_ssbos
) {
5742 const int i
= u_bit_scan(&bound_ssbos
);
5743 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5745 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5746 struct pipe_shader_buffer buf
= {
5747 .buffer
= &res
->base
,
5748 .buffer_offset
= ssbo
->buffer_offset
,
5749 .buffer_size
= ssbo
->buffer_size
,
5751 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5752 (shs
->writable_ssbos
>> i
) & 1);
5757 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5758 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5759 while (bound_sampler_views
) {
5760 const int i
= u_bit_scan(&bound_sampler_views
);
5761 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5763 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5764 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5765 &isv
->surface_state
,
5766 isv
->res
->aux
.sampler_usages
);
5768 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
, map
,
5769 isv
->view
.format
, isv
->view
.swizzle
,
5770 isv
->base
.u
.buf
.offset
,
5771 isv
->base
.u
.buf
.size
);
5772 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5777 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5778 uint32_t bound_image_views
= shs
->bound_image_views
;
5779 while (bound_image_views
) {
5780 const int i
= u_bit_scan(&bound_image_views
);
5781 struct iris_image_view
*iv
= &shs
->image
[i
];
5783 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5784 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
5791 /* ------------------------------------------------------------------- */
5794 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5797 _iris_emit_lrr(batch
, dst
, src
);
5801 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5804 _iris_emit_lrr(batch
, dst
, src
);
5805 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5809 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5812 _iris_emit_lri(batch
, reg
, val
);
5816 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5819 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5820 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5824 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5827 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5828 struct iris_bo
*bo
, uint32_t offset
)
5830 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5831 lrm
.RegisterAddress
= reg
;
5832 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5837 * Load a 64-bit value from a buffer into a MMIO register via
5838 * two MI_LOAD_REGISTER_MEM commands.
5841 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5842 struct iris_bo
*bo
, uint32_t offset
)
5844 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5845 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5849 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5850 struct iris_bo
*bo
, uint32_t offset
,
5853 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5854 srm
.RegisterAddress
= reg
;
5855 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5856 srm
.PredicateEnable
= predicated
;
5861 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5862 struct iris_bo
*bo
, uint32_t offset
,
5865 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5866 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5870 iris_store_data_imm32(struct iris_batch
*batch
,
5871 struct iris_bo
*bo
, uint32_t offset
,
5874 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5875 sdi
.Address
= rw_bo(bo
, offset
);
5876 sdi
.ImmediateData
= imm
;
5881 iris_store_data_imm64(struct iris_batch
*batch
,
5882 struct iris_bo
*bo
, uint32_t offset
,
5885 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5886 * 2 in genxml but it's actually variable length and we need 5 DWords.
5888 void *map
= iris_get_command_space(batch
, 4 * 5);
5889 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5890 sdi
.DWordLength
= 5 - 2;
5891 sdi
.Address
= rw_bo(bo
, offset
);
5892 sdi
.ImmediateData
= imm
;
5897 iris_copy_mem_mem(struct iris_batch
*batch
,
5898 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5899 struct iris_bo
*src_bo
, uint32_t src_offset
,
5902 /* MI_COPY_MEM_MEM operates on DWords. */
5903 assert(bytes
% 4 == 0);
5904 assert(dst_offset
% 4 == 0);
5905 assert(src_offset
% 4 == 0);
5907 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5908 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5909 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5910 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5915 /* ------------------------------------------------------------------- */
5918 flags_to_post_sync_op(uint32_t flags
)
5920 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5921 return WriteImmediateData
;
5923 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5924 return WritePSDepthCount
;
5926 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5927 return WriteTimestamp
;
5933 * Do the given flags have a Post Sync or LRI Post Sync operation?
5935 static enum pipe_control_flags
5936 get_post_sync_flags(enum pipe_control_flags flags
)
5938 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5939 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5940 PIPE_CONTROL_WRITE_TIMESTAMP
|
5941 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5943 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5944 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5946 assert(util_bitcount(flags
) <= 1);
5951 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5954 * Emit a series of PIPE_CONTROL commands, taking into account any
5955 * workarounds necessary to actually accomplish the caller's request.
5957 * Unless otherwise noted, spec quotations in this function come from:
5959 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5960 * Restrictions for PIPE_CONTROL.
5962 * You should not use this function directly. Use the helpers in
5963 * iris_pipe_control.c instead, which may split the pipe control further.
5966 iris_emit_raw_pipe_control(struct iris_batch
*batch
,
5973 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5974 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5975 enum pipe_control_flags non_lri_post_sync_flags
=
5976 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5978 /* Recursive PIPE_CONTROL workarounds --------------------------------
5979 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5981 * We do these first because we want to look at the original operation,
5982 * rather than any workarounds we set.
5984 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5985 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5986 * lists several workarounds:
5988 * "Project: SKL, KBL, BXT
5990 * If the VF Cache Invalidation Enable is set to a 1 in a
5991 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5992 * sets to 0, with the VF Cache Invalidation Enable set to 0
5993 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5994 * Invalidation Enable set to a 1."
5996 iris_emit_raw_pipe_control(batch
,
5997 "workaround: recursive VF cache invalidate",
6001 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
6002 /* Project: SKL / Argument: LRI Post Sync Operation [23]
6004 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6005 * programmed prior to programming a PIPECONTROL command with "LRI
6006 * Post Sync Operation" in GPGPU mode of operation (i.e when
6007 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
6009 * The same text exists a few rows below for Post Sync Op.
6011 iris_emit_raw_pipe_control(batch
,
6012 "workaround: CS stall before gpgpu post-sync",
6013 PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
6016 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
6018 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
6019 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
6020 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
6022 iris_emit_raw_pipe_control(batch
,
6023 "workaround: PC flush before RT flush",
6024 PIPE_CONTROL_FLUSH_ENABLE
, bo
, offset
, imm
);
6027 /* "Flush Types" workarounds ---------------------------------------------
6028 * We do these now because they may add post-sync operations or CS stalls.
6031 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
6032 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
6034 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
6035 * 'Write PS Depth Count' or 'Write Timestamp'."
6038 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6039 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6040 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
6041 bo
= batch
->screen
->workaround_bo
;
6045 /* #1130 from Gen10 workarounds page:
6047 * "Enable Depth Stall on every Post Sync Op if Render target Cache
6048 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
6049 * board stall if Render target cache flush is enabled."
6051 * Applicable to CNL B0 and C0 steppings only.
6053 * The wording here is unclear, and this workaround doesn't look anything
6054 * like the internal bug report recommendations, but leave it be for now...
6056 if (GEN_GEN
== 10) {
6057 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
6058 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6059 } else if (flags
& non_lri_post_sync_flags
) {
6060 flags
|= PIPE_CONTROL_DEPTH_STALL
;
6064 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
6065 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
6067 * "This bit must be DISABLED for operations other than writing
6070 * This seems like nonsense. An Ivybridge workaround requires us to
6071 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
6072 * operation. Gen8+ requires us to emit depth stalls and depth cache
6073 * flushes together. So, it's hard to imagine this means anything other
6074 * than "we originally intended this to be used for PS_DEPTH_COUNT".
6076 * We ignore the supposed restriction and do nothing.
6080 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6081 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6082 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
6084 * "This bit must be DISABLED for End-of-pipe (Read) fences,
6085 * PS_DEPTH_COUNT or TIMESTAMP queries."
6087 * TODO: Implement end-of-pipe checking.
6089 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6090 PIPE_CONTROL_WRITE_TIMESTAMP
)));
6093 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
6094 /* From the PIPE_CONTROL instruction table, bit 1:
6096 * "This bit is ignored if Depth Stall Enable is set.
6097 * Further, the render cache is not flushed even if Write Cache
6098 * Flush Enable bit is set."
6100 * We assert that the caller doesn't do this combination, to try and
6101 * prevent mistakes. It shouldn't hurt the GPU, though.
6103 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
6104 * and "Render Target Flush" combo is explicitly required for BTI
6105 * update workarounds.
6107 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
6108 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
6111 /* PIPE_CONTROL page workarounds ------------------------------------- */
6113 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
6114 /* From the PIPE_CONTROL page itself:
6117 * Restriction: Pipe_control with CS-stall bit set must be issued
6118 * before a pipe-control command that has the State Cache
6119 * Invalidate bit set."
6121 flags
|= PIPE_CONTROL_CS_STALL
;
6124 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
6125 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
6128 * SW must always program Post-Sync Operation to "Write Immediate
6129 * Data" when Flush LLC is set."
6131 * For now, we just require the caller to do it.
6133 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
6136 /* "Post-Sync Operation" workarounds -------------------------------- */
6138 /* Project: All / Argument: Global Snapshot Count Reset [19]
6140 * "This bit must not be exercised on any product.
6141 * Requires stall bit ([20] of DW1) set."
6143 * We don't use this, so we just assert that it isn't used. The
6144 * PIPE_CONTROL instruction page indicates that they intended this
6145 * as a debug feature and don't think it is useful in production,
6146 * but it may actually be usable, should we ever want to.
6148 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6150 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6151 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6152 /* Project: All / Arguments:
6154 * - Generic Media State Clear [16]
6155 * - Indirect State Pointers Disable [16]
6157 * "Requires stall bit ([20] of DW1) set."
6159 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6160 * State Clear) says:
6162 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6163 * programmed prior to programming a PIPECONTROL command with "Media
6164 * State Clear" set in GPGPU mode of operation"
6166 * This is a subset of the earlier rule, so there's nothing to do.
6168 flags
|= PIPE_CONTROL_CS_STALL
;
6171 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6172 /* Project: All / Argument: Store Data Index
6174 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6177 * For now, we just assert that the caller does this. We might want to
6178 * automatically add a write to the workaround BO...
6180 assert(non_lri_post_sync_flags
!= 0);
6183 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6184 /* Project: All / Argument: Sync GFDT
6186 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6187 * than '0' or 0x2520[13] must be set."
6189 * For now, we just assert that the caller does this.
6191 assert(non_lri_post_sync_flags
!= 0);
6194 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6195 /* Project: IVB+ / Argument: TLB inv
6197 * "Requires stall bit ([20] of DW1) set."
6199 * Also, from the PIPE_CONTROL instruction table:
6202 * Post Sync Operation or CS stall must be set to ensure a TLB
6203 * invalidation occurs. Otherwise no cycle will occur to the TLB
6204 * cache to invalidate."
6206 * This is not a subset of the earlier rule, so there's nothing to do.
6208 flags
|= PIPE_CONTROL_CS_STALL
;
6211 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6212 /* TODO: The big Skylake GT4 post sync op workaround */
6215 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6217 if (IS_COMPUTE_PIPELINE(batch
)) {
6218 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6219 /* Project: SKL+ / Argument: Tex Invalidate
6220 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6222 flags
|= PIPE_CONTROL_CS_STALL
;
6225 if (GEN_GEN
== 8 && (post_sync_flags
||
6226 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6227 PIPE_CONTROL_DEPTH_STALL
|
6228 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6229 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6230 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6231 /* Project: BDW / Arguments:
6233 * - LRI Post Sync Operation [23]
6234 * - Post Sync Op [15:14]
6236 * - Depth Stall [13]
6237 * - Render Target Cache Flush [12]
6238 * - Depth Cache Flush [0]
6239 * - DC Flush Enable [5]
6241 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6244 flags
|= PIPE_CONTROL_CS_STALL
;
6246 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6249 * This bit must be always set when PIPE_CONTROL command is
6250 * programmed by GPGPU and MEDIA workloads, except for the cases
6251 * when only Read Only Cache Invalidation bits are set (State
6252 * Cache Invalidation Enable, Instruction cache Invalidation
6253 * Enable, Texture Cache Invalidation Enable, Constant Cache
6254 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6255 * need not implemented when FF_DOP_CG is disable via "Fixed
6256 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6258 * It sounds like we could avoid CS stalls in some cases, but we
6259 * don't currently bother. This list isn't exactly the list above,
6265 /* "Stall" workarounds ----------------------------------------------
6266 * These have to come after the earlier ones because we may have added
6267 * some additional CS stalls above.
6270 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6271 /* Project: PRE-SKL, VLV, CHV
6273 * "[All Stepping][All SKUs]:
6275 * One of the following must also be set:
6277 * - Render Target Cache Flush Enable ([12] of DW1)
6278 * - Depth Cache Flush Enable ([0] of DW1)
6279 * - Stall at Pixel Scoreboard ([1] of DW1)
6280 * - Depth Stall ([13] of DW1)
6281 * - Post-Sync Operation ([13] of DW1)
6282 * - DC Flush Enable ([5] of DW1)"
6284 * If we don't already have one of those bits set, we choose to add
6285 * "Stall at Pixel Scoreboard". Some of the other bits require a
6286 * CS stall as a workaround (see above), which would send us into
6287 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6288 * appears to be safe, so we choose that.
6290 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6291 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6292 PIPE_CONTROL_WRITE_IMMEDIATE
|
6293 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6294 PIPE_CONTROL_WRITE_TIMESTAMP
|
6295 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6296 PIPE_CONTROL_DEPTH_STALL
|
6297 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6298 if (!(flags
& wa_bits
))
6299 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6302 /* Emit --------------------------------------------------------------- */
6304 if (INTEL_DEBUG
& DEBUG_PIPE_CONTROL
) {
6306 " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64
"]: %s\n",
6307 (flags
& PIPE_CONTROL_FLUSH_ENABLE
) ? "PipeCon " : "",
6308 (flags
& PIPE_CONTROL_CS_STALL
) ? "CS " : "",
6309 (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) ? "Scoreboard " : "",
6310 (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) ? "VF " : "",
6311 (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) ? "RT " : "",
6312 (flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
) ? "Const " : "",
6313 (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
) ? "TC " : "",
6314 (flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
) ? "DC " : "",
6315 (flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
) ? "ZFlush " : "",
6316 (flags
& PIPE_CONTROL_DEPTH_STALL
) ? "ZStall " : "",
6317 (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
) ? "State " : "",
6318 (flags
& PIPE_CONTROL_TLB_INVALIDATE
) ? "TLB " : "",
6319 (flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
) ? "Inst " : "",
6320 (flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
) ? "MediaClear " : "",
6321 (flags
& PIPE_CONTROL_NOTIFY_ENABLE
) ? "Notify " : "",
6322 (flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) ?
6324 (flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
) ?
6326 (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
) ? "WriteImm " : "",
6327 (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
) ? "WriteZCount " : "",
6328 (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
) ? "WriteTimestamp " : "",
6332 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6333 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6334 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6335 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6336 pc
.StoreDataIndex
= 0;
6337 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6338 pc
.GlobalSnapshotCountReset
=
6339 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6340 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6341 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6342 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6343 pc
.RenderTargetCacheFlushEnable
=
6344 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6345 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6346 pc
.StateCacheInvalidationEnable
=
6347 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6348 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6349 pc
.ConstantCacheInvalidationEnable
=
6350 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6351 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6352 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6353 pc
.InstructionCacheInvalidateEnable
=
6354 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6355 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6356 pc
.IndirectStatePointersDisable
=
6357 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6358 pc
.TextureCacheInvalidationEnable
=
6359 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6360 pc
.Address
= rw_bo(bo
, offset
);
6361 pc
.ImmediateData
= imm
;
6366 genX(emit_urb_setup
)(struct iris_context
*ice
,
6367 struct iris_batch
*batch
,
6368 const unsigned size
[4],
6369 bool tess_present
, bool gs_present
)
6371 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6372 const unsigned push_size_kB
= 32;
6373 unsigned entries
[4];
6376 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6378 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6379 1024 * ice
->shaders
.urb_size
,
6380 tess_present
, gs_present
,
6381 size
, entries
, start
);
6383 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6384 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6385 urb
._3DCommandSubOpcode
+= i
;
6386 urb
.VSURBStartingAddress
= start
[i
];
6387 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6388 urb
.VSNumberofURBEntries
= entries
[i
];
6395 * Preemption on Gen9 has to be enabled or disabled in various cases.
6397 * See these workarounds for preemption:
6398 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6399 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6400 * - WaDisableMidObjectPreemptionForLineLoop
6403 * We don't put this in the vtable because it's only used on Gen9.
6406 gen9_toggle_preemption(struct iris_context
*ice
,
6407 struct iris_batch
*batch
,
6408 const struct pipe_draw_info
*draw
)
6410 struct iris_genx_state
*genx
= ice
->state
.genx
;
6411 bool object_preemption
= true;
6413 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6415 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6416 * and GS is enabled."
6418 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6419 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6420 object_preemption
= false;
6422 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6424 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6425 * on a previous context. End the previous, the resume another context
6426 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6427 * prempt again we will cause corruption.
6429 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6431 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6432 object_preemption
= false;
6434 /* WaDisableMidObjectPreemptionForLineLoop
6436 * "VF Stats Counters Missing a vertex when preemption enabled.
6438 * WA: Disable mid-draw preemption when the draw uses a lineloop
6441 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6442 object_preemption
= false;
6446 * "VF is corrupting GAFS data when preempted on an instance boundary
6447 * and replayed with instancing enabled.
6449 * WA: Disable preemption when using instanceing."
6451 if (draw
->instance_count
> 1)
6452 object_preemption
= false;
6454 if (genx
->object_preemption
!= object_preemption
) {
6455 iris_enable_obj_preemption(batch
, object_preemption
);
6456 genx
->object_preemption
= object_preemption
;
6462 genX(init_state
)(struct iris_context
*ice
)
6464 struct pipe_context
*ctx
= &ice
->ctx
;
6465 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6467 ctx
->create_blend_state
= iris_create_blend_state
;
6468 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6469 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6470 ctx
->create_sampler_state
= iris_create_sampler_state
;
6471 ctx
->create_sampler_view
= iris_create_sampler_view
;
6472 ctx
->create_surface
= iris_create_surface
;
6473 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6474 ctx
->bind_blend_state
= iris_bind_blend_state
;
6475 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6476 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6477 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6478 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6479 ctx
->delete_blend_state
= iris_delete_state
;
6480 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6481 ctx
->delete_rasterizer_state
= iris_delete_state
;
6482 ctx
->delete_sampler_state
= iris_delete_state
;
6483 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6484 ctx
->set_blend_color
= iris_set_blend_color
;
6485 ctx
->set_clip_state
= iris_set_clip_state
;
6486 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6487 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6488 ctx
->set_shader_images
= iris_set_shader_images
;
6489 ctx
->set_sampler_views
= iris_set_sampler_views
;
6490 ctx
->set_tess_state
= iris_set_tess_state
;
6491 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6492 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6493 ctx
->set_sample_mask
= iris_set_sample_mask
;
6494 ctx
->set_scissor_states
= iris_set_scissor_states
;
6495 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6496 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6497 ctx
->set_viewport_states
= iris_set_viewport_states
;
6498 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6499 ctx
->surface_destroy
= iris_surface_destroy
;
6500 ctx
->draw_vbo
= iris_draw_vbo
;
6501 ctx
->launch_grid
= iris_launch_grid
;
6502 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6503 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6504 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6506 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6507 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6508 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6509 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6510 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6511 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6512 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6513 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6514 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6515 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6516 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6517 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6518 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6519 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6520 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6521 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6522 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6523 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6524 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6525 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6526 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6527 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6528 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6529 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6530 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6531 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6532 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6533 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6534 ice
->vtbl
.mocs
= mocs
;
6536 ice
->state
.dirty
= ~0ull;
6538 ice
->state
.statistics_counters_enabled
= true;
6540 ice
->state
.sample_mask
= 0xffff;
6541 ice
->state
.num_viewports
= 1;
6542 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6544 /* Make a 1x1x1 null surface for unbound textures */
6545 void *null_surf_map
=
6546 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6547 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6548 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6549 ice
->state
.unbound_tex
.offset
+=
6550 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6552 /* Default all scissor rectangles to be empty regions. */
6553 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6554 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6555 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,