2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "util/u_upload_mgr.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/common/gen_l3_config.h"
46 #include "intel/common/gen_sample_positions.h"
47 #include "iris_batch.h"
48 #include "iris_context.h"
49 #include "iris_pipe.h"
50 #include "iris_resource.h"
52 #define __gen_address_type struct iris_address
53 #define __gen_user_data struct iris_batch
55 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
58 __gen_combine_address(struct iris_batch
*batch
, void *location
,
59 struct iris_address addr
, uint32_t delta
)
61 uint64_t result
= addr
.offset
+ delta
;
64 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
65 /* Assume this is a general address, not relative to a base. */
66 result
+= addr
.bo
->gtt_offset
;
72 #define __genxml_cmd_length(cmd) cmd ## _length
73 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
74 #define __genxml_cmd_header(cmd) cmd ## _header
75 #define __genxml_cmd_pack(cmd) cmd ## _pack
77 #define _iris_pack_command(batch, cmd, dst, name) \
78 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
79 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
80 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
84 #define iris_pack_command(cmd, dst, name) \
85 _iris_pack_command(NULL, cmd, dst, name)
87 #define iris_pack_state(cmd, dst, name) \
88 for (struct cmd name = {}, \
89 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
90 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
93 #define iris_emit_cmd(batch, cmd, name) \
94 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
96 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
98 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
99 for (uint32_t i = 0; i < num_dwords; i++) \
100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
104 #include "genxml/genX_pack.h"
105 #include "genxml/gen_macros.h"
106 #include "genxml/genX_bits.h"
108 #define MOCS_WB (2 << 1)
110 UNUSED
static void pipe_asserts()
112 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
114 /* pipe_logicop happens to match the hardware. */
115 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
116 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
117 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
118 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
119 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
120 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
121 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
122 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
124 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
125 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
126 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
128 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
129 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
130 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
132 /* pipe_blend_func happens to match the hardware. */
133 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
153 /* pipe_blend_func happens to match the hardware. */
154 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
155 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
156 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
157 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
158 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
160 /* pipe_stencil_op happens to match the hardware. */
161 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
162 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
163 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
164 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
165 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
170 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
171 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
172 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
177 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
179 static const unsigned map
[] = {
180 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
181 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
182 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
183 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
184 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
185 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
186 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
187 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
188 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
189 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
190 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
191 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
192 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
193 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
194 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
197 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
201 translate_compare_func(enum pipe_compare_func pipe_func
)
203 static const unsigned map
[] = {
204 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
205 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
206 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
207 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
208 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
209 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
210 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
211 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
213 return map
[pipe_func
];
217 translate_shadow_func(enum pipe_compare_func pipe_func
)
219 /* Gallium specifies the result of shadow comparisons as:
221 * 1 if ref <op> texel,
226 * 0 if texel <op> ref,
229 * So we need to flip the operator and also negate.
231 static const unsigned map
[] = {
232 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
233 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
234 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
235 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
236 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
237 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
238 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
239 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
241 return map
[pipe_func
];
245 translate_cull_mode(unsigned pipe_face
)
247 static const unsigned map
[4] = {
248 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
249 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
250 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
251 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
253 return map
[pipe_face
];
257 translate_fill_mode(unsigned pipe_polymode
)
259 static const unsigned map
[4] = {
260 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
261 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
262 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
263 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
265 return map
[pipe_polymode
];
268 static struct iris_address
269 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
272 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
276 * Returns the BO's address relative to the appropriate base address.
278 * All of our base addresses are programmed to the start of a 4GB region,
279 * so simply returning the bottom 32 bits of the BO address will give us
280 * the offset from whatever base address corresponds to that memory region.
283 bo_offset_from_base_address(struct pipe_resource
*res
)
285 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
287 /* This only works for buffers in the memory zones corresponding to a
288 * base address - the top, unbounded memory zone doesn't have a base.
290 assert(bo
->gtt_offset
< 3 * (1ull << 32));
291 return bo
->gtt_offset
;
295 stream_state(struct iris_batch
*batch
,
296 struct u_upload_mgr
*uploader
,
299 uint32_t *out_offset
)
301 struct pipe_resource
*res
= NULL
;
304 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
306 struct iris_bo
*bo
= ((struct iris_resource
*) res
)->bo
;
307 iris_use_pinned_bo(batch
, bo
, false);
309 *out_offset
+= bo_offset_from_base_address(res
);
311 pipe_resource_reference(&res
, NULL
);
317 emit_state(struct iris_batch
*batch
,
318 struct u_upload_mgr
*uploader
,
324 uint32_t *map
= stream_state(batch
, uploader
, size
, alignment
, &offset
);
327 memcpy(map
, data
, size
);
333 iris_init_render_context(struct iris_screen
*screen
,
334 struct iris_batch
*batch
,
335 struct pipe_debug_callback
*dbg
)
337 iris_init_batch(batch
, screen
, dbg
, I915_EXEC_RENDER
);
339 /* XXX: PIPE_CONTROLs */
341 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
343 // XXX: MOCS is stupid for this.
344 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
345 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
346 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
347 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
348 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
349 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
350 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
353 sba
.GeneralStateBaseAddressModifyEnable
= true;
354 sba
.SurfaceStateBaseAddressModifyEnable
= true;
355 sba
.DynamicStateBaseAddressModifyEnable
= true;
356 sba
.IndirectObjectBaseAddressModifyEnable
= true;
357 sba
.InstructionBaseAddressModifyEnable
= true;
358 sba
.GeneralStateBufferSizeModifyEnable
= true;
359 sba
.DynamicStateBufferSizeModifyEnable
= true;
360 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
361 sba
.IndirectObjectBufferSizeModifyEnable
= true;
362 sba
.InstructionBuffersizeModifyEnable
= true;
364 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, 1ull << 32);
365 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, 2 * (1ull << 32));
367 sba
.GeneralStateBufferSize
= 0xfffff;
368 sba
.IndirectObjectBufferSize
= 0xfffff;
369 sba
.InstructionBufferSize
= 0xfffff;
370 sba
.DynamicStateBufferSize
= 0xfffff;
373 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
374 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
375 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
377 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
378 GEN_SAMPLE_POS_1X(pat
._1xSample
);
379 GEN_SAMPLE_POS_2X(pat
._2xSample
);
380 GEN_SAMPLE_POS_4X(pat
._4xSample
);
381 GEN_SAMPLE_POS_8X(pat
._8xSample
);
382 GEN_SAMPLE_POS_16X(pat
._16xSample
);
384 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
385 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
386 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
387 /* XXX: may need to set an offset for origin-UL framebuffers */
388 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
390 /* Just assign a static partitioning. */
391 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
392 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
393 alloc
._3DCommandSubOpcode
= 18 + i
;
394 alloc
.ConstantBufferOffset
= 6 * i
;
395 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
401 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
406 iris_set_blend_color(struct pipe_context
*ctx
,
407 const struct pipe_blend_color
*state
)
409 struct iris_context
*ice
= (struct iris_context
*) ctx
;
411 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
412 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
415 struct iris_blend_state
{
416 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
417 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
418 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
420 bool alpha_to_coverage
; /* for shader key */
424 iris_create_blend_state(struct pipe_context
*ctx
,
425 const struct pipe_blend_state
*state
)
427 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
428 uint32_t *blend_state
= cso
->blend_state
;
430 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
432 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
433 /* pb.HasWriteableRT is filled in at draw time. */
434 /* pb.AlphaTestEnable is filled in at draw time. */
435 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
436 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
438 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
440 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
441 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
442 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
443 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
446 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
447 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
448 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
449 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
450 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
451 bs
.ColorDitherEnable
= state
->dither
;
452 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
455 blend_state
+= GENX(BLEND_STATE_length
);
457 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
458 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
459 be
.LogicOpEnable
= state
->logicop_enable
;
460 be
.LogicOpFunction
= state
->logicop_func
;
462 be
.PreBlendSourceOnlyClampEnable
= false;
463 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
464 be
.PreBlendColorClampEnable
= true;
465 be
.PostBlendColorClampEnable
= true;
467 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
469 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
470 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
471 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
472 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
473 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
474 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
476 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
477 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
478 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
479 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
481 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
488 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
490 struct iris_context
*ice
= (struct iris_context
*) ctx
;
491 ice
->state
.cso_blend
= state
;
492 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
493 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
496 struct iris_depth_stencil_alpha_state
{
497 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
498 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
500 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
504 iris_create_zsa_state(struct pipe_context
*ctx
,
505 const struct pipe_depth_stencil_alpha_state
*state
)
507 struct iris_depth_stencil_alpha_state
*cso
=
508 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
510 cso
->alpha
= state
->alpha
;
512 bool two_sided_stencil
= state
->stencil
[1].enabled
;
514 /* The state tracker needs to optimize away EQUAL writes for us. */
515 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
517 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
518 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
519 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
520 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
521 wmds
.StencilTestFunction
=
522 translate_compare_func(state
->stencil
[0].func
);
523 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
524 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
525 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
526 wmds
.BackfaceStencilTestFunction
=
527 translate_compare_func(state
->stencil
[1].func
);
528 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
529 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
530 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
531 wmds
.StencilBufferWriteEnable
=
532 state
->stencil
[0].writemask
!= 0 ||
533 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
534 wmds
.DepthTestEnable
= state
->depth
.enabled
;
535 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
536 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
537 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
538 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
539 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
540 /* wmds.[Backface]StencilReferenceValue are merged later */
543 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
544 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
545 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
552 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
554 struct iris_context
*ice
= (struct iris_context
*) ctx
;
555 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
556 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
559 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
560 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
564 ice
->state
.cso_zsa
= new_cso
;
565 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
566 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
569 struct iris_rasterizer_state
{
570 uint32_t sf
[GENX(3DSTATE_SF_length
)];
571 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
572 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
573 uint32_t wm
[GENX(3DSTATE_WM_length
)];
574 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
576 bool flatshade
; /* for shader state */
577 bool clamp_fragment_color
; /* for shader state */
578 bool light_twoside
; /* for shader state */
579 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
580 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
581 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
582 uint16_t sprite_coord_enable
;
586 iris_create_rasterizer_state(struct pipe_context
*ctx
,
587 const struct pipe_rasterizer_state
*state
)
589 struct iris_rasterizer_state
*cso
=
590 malloc(sizeof(struct iris_rasterizer_state
));
593 point_quad_rasterization
-> SBE
?
598 force_persample_interp
- ?
601 offset_units_unscaled
- cap
not exposed
605 cso
->flatshade
= state
->flatshade
;
606 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
607 cso
->light_twoside
= state
->light_twoside
;
608 cso
->rasterizer_discard
= state
->rasterizer_discard
;
609 cso
->half_pixel_center
= state
->half_pixel_center
;
610 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
611 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
613 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
614 sf
.StatisticsEnable
= true;
615 sf
.ViewportTransformEnable
= true;
616 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
617 sf
.LineEndCapAntialiasingRegionWidth
=
618 state
->line_smooth
? _10pixels
: _05pixels
;
619 sf
.LastPixelEnable
= state
->line_last_pixel
;
620 sf
.LineWidth
= state
->line_width
;
621 sf
.SmoothPointEnable
= state
->point_smooth
;
622 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
623 sf
.PointWidth
= state
->point_size
;
625 if (state
->flatshade_first
) {
626 sf
.TriangleStripListProvokingVertexSelect
= 2;
627 sf
.TriangleFanProvokingVertexSelect
= 2;
628 sf
.LineStripListProvokingVertexSelect
= 1;
630 sf
.TriangleFanProvokingVertexSelect
= 1;
635 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
636 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
637 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
638 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
639 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
640 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
641 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
642 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
643 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
644 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
645 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
646 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
647 rr
.SmoothPointEnable
= state
->point_smooth
;
648 rr
.AntialiasingEnable
= state
->line_smooth
;
649 rr
.ScissorRectangleEnable
= state
->scissor
;
650 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
651 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
652 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
655 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
656 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
657 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
659 cl
.StatisticsEnable
= true;
660 cl
.EarlyCullEnable
= true;
661 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
662 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
663 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
664 cl
.GuardbandClipTestEnable
= true;
665 cl
.ClipMode
= CLIPMODE_NORMAL
;
666 cl
.ClipEnable
= true;
667 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
668 cl
.MinimumPointWidth
= 0.125;
669 cl
.MaximumPointWidth
= 255.875;
671 if (state
->flatshade_first
) {
672 cl
.TriangleStripListProvokingVertexSelect
= 2;
673 cl
.TriangleFanProvokingVertexSelect
= 2;
674 cl
.LineStripListProvokingVertexSelect
= 1;
676 cl
.TriangleFanProvokingVertexSelect
= 1;
680 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
681 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
682 * filled in at draw time from the FS program.
684 wm
.LineAntialiasingRegionWidth
= _10pixels
;
685 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
686 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
687 wm
.StatisticsEnable
= true;
688 wm
.LineStippleEnable
= state
->line_stipple_enable
;
689 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
692 /* Remap from 0..255 back to 1..256 */
693 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
695 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
696 line
.LineStipplePattern
= state
->line_stipple_pattern
;
697 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
698 line
.LineStippleRepeatCount
= line_stipple_factor
;
705 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
707 struct iris_context
*ice
= (struct iris_context
*) ctx
;
708 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
709 struct iris_rasterizer_state
*new_cso
= state
;
712 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
713 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
714 sizeof(old_cso
->line_stipple
)) != 0) {
715 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
719 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
720 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
724 ice
->state
.cso_rast
= new_cso
;
725 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
729 translate_wrap(unsigned pipe_wrap
)
731 static const unsigned map
[] = {
732 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
733 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
734 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
735 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
736 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
737 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
738 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
739 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
741 return map
[pipe_wrap
];
745 * Return true if the given wrap mode requires the border color to exist.
748 wrap_mode_needs_border_color(unsigned wrap_mode
)
750 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
754 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
756 static const unsigned map
[] = {
757 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
758 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
759 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
761 return map
[pipe_mip
];
764 struct iris_sampler_state
{
765 struct pipe_sampler_state base
;
767 bool needs_border_color
;
769 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
773 iris_create_sampler_state(struct pipe_context
*pctx
,
774 const struct pipe_sampler_state
*state
)
776 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
781 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
782 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
784 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
785 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
786 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
788 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
789 wrap_mode_needs_border_color(wrap_t
) ||
790 wrap_mode_needs_border_color(wrap_r
);
792 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
793 samp
.TCXAddressControlMode
= wrap_s
;
794 samp
.TCYAddressControlMode
= wrap_t
;
795 samp
.TCZAddressControlMode
= wrap_r
;
796 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
797 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
798 samp
.MinModeFilter
= state
->min_img_filter
;
799 samp
.MagModeFilter
= state
->mag_img_filter
;
800 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
801 samp
.MaximumAnisotropy
= RATIO21
;
803 if (state
->max_anisotropy
>= 2) {
804 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
805 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
806 samp
.AnisotropicAlgorithm
= EWAApproximation
;
809 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
810 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
812 samp
.MaximumAnisotropy
=
813 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
816 /* Set address rounding bits if not using nearest filtering. */
817 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
818 samp
.UAddressMinFilterRoundingEnable
= true;
819 samp
.VAddressMinFilterRoundingEnable
= true;
820 samp
.RAddressMinFilterRoundingEnable
= true;
823 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
824 samp
.UAddressMagFilterRoundingEnable
= true;
825 samp
.VAddressMagFilterRoundingEnable
= true;
826 samp
.RAddressMagFilterRoundingEnable
= true;
829 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
830 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
832 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
834 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
835 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
836 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
837 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
839 //samp.BorderColorPointer = <<comes from elsewhere>>
846 iris_bind_sampler_states(struct pipe_context
*ctx
,
847 enum pipe_shader_type p_stage
,
848 unsigned start
, unsigned count
,
851 struct iris_context
*ice
= (struct iris_context
*) ctx
;
852 gl_shader_stage stage
= stage_from_pipe(p_stage
);
854 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
856 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
857 * relative to Dynamic State Base Address.
860 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
861 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
862 &ice
->state
.sampler_table_offset
[stage
],
863 &ice
->state
.sampler_table_resource
[stage
],
868 ice
->state
.sampler_table_offset
[stage
] +=
869 bo_offset_from_base_address(ice
->state
.sampler_table_resource
[stage
]);
871 for (int i
= 0; i
< count
; i
++) {
872 struct iris_sampler_state
*state
= states
[i
];
874 /* Save a pointer to the iris_sampler_state, a few fields need
875 * to inform draw-time decisions.
877 ice
->state
.samplers
[stage
][start
+ i
] = state
;
880 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
882 map
+= GENX(SAMPLER_STATE_length
);
885 ice
->state
.num_samplers
[stage
] = count
;
887 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
890 struct iris_sampler_view
{
891 struct pipe_sampler_view pipe
;
892 struct isl_view view
;
894 /** The resource (BO) holding our SURFACE_STATE. */
895 struct pipe_resource
*surface_state_resource
;
896 unsigned surface_state_offset
;
898 //uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
902 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
903 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
905 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
908 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
910 * which is simply adding 4 then modding by 8 (or anding with 7).
912 * We then may need to apply workarounds for textureGather hardware bugs.
914 static enum isl_channel_select
915 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
917 return (swizzle
+ 4) & 7;
920 static struct pipe_sampler_view
*
921 iris_create_sampler_view(struct pipe_context
*ctx
,
922 struct pipe_resource
*tex
,
923 const struct pipe_sampler_view
*tmpl
)
925 struct iris_context
*ice
= (struct iris_context
*) ctx
;
926 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
927 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
928 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
933 /* initialize base object */
935 isv
->pipe
.context
= ctx
;
936 isv
->pipe
.texture
= NULL
;
937 pipe_reference_init(&isv
->pipe
.reference
, 1);
938 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
940 /* XXX: do we need brw_get_texture_swizzle hacks here? */
942 isv
->view
= (struct isl_view
) {
943 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
944 .base_level
= tmpl
->u
.tex
.first_level
,
945 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
946 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
947 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
948 .swizzle
= (struct isl_swizzle
) {
949 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
950 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
951 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
952 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
954 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
958 u_upload_alloc(ice
->state
.surface_uploader
, 0,
959 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
960 &isv
->surface_state_offset
,
961 &isv
->surface_state_resource
,
966 isv
->surface_state_offset
+=
967 bo_offset_from_base_address(isv
->surface_state_resource
);
969 isl_surf_fill_state(&screen
->isl_dev
, map
,
970 .surf
= &itex
->surf
, .view
= &isv
->view
,
972 .address
= itex
->bo
->gtt_offset
);
974 // .clear_color = clear_color,
979 struct iris_surface
{
980 struct pipe_surface pipe
;
981 struct isl_view view
;
983 /** The resource (BO) holding our SURFACE_STATE. */
984 struct pipe_resource
*surface_state_resource
;
985 unsigned surface_state_offset
;
987 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
990 static struct pipe_surface
*
991 iris_create_surface(struct pipe_context
*ctx
,
992 struct pipe_resource
*tex
,
993 const struct pipe_surface
*tmpl
)
995 struct iris_context
*ice
= (struct iris_context
*) ctx
;
996 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
997 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
998 struct pipe_surface
*psurf
= &surf
->pipe
;
999 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
1004 pipe_reference_init(&psurf
->reference
, 1);
1005 pipe_resource_reference(&psurf
->texture
, tex
);
1006 psurf
->context
= ctx
;
1007 psurf
->format
= tmpl
->format
;
1008 psurf
->width
= tex
->width0
;
1009 psurf
->height
= tex
->height0
;
1010 psurf
->texture
= tex
;
1011 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1012 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1013 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1015 surf
->view
= (struct isl_view
) {
1016 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1017 .base_level
= tmpl
->u
.tex
.level
,
1019 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1020 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1021 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1022 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
1023 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1027 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1028 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1029 &surf
->surface_state_offset
,
1030 &surf
->surface_state_resource
,
1035 surf
->surface_state_offset
+=
1036 bo_offset_from_base_address(surf
->surface_state_resource
);
1038 isl_surf_fill_state(&screen
->isl_dev
, map
,
1039 .surf
= &itex
->surf
, .view
= &surf
->view
,
1041 .address
= itex
->bo
->gtt_offset
);
1043 // .clear_color = clear_color,
1049 iris_set_sampler_views(struct pipe_context
*ctx
,
1050 enum pipe_shader_type p_stage
,
1051 unsigned start
, unsigned count
,
1052 struct pipe_sampler_view
**views
)
1054 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1055 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1058 for (i
= 0; i
< count
; i
++) {
1059 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1060 &ice
->state
.textures
[stage
][i
], views
[i
]);
1062 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1063 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1064 &ice
->state
.textures
[stage
][i
], NULL
);
1067 ice
->state
.num_textures
[stage
] = count
;
1069 // XXX: ice->state.dirty |= (IRIS_DIRTY_BINDING_TABLE_VS << stage);
1073 iris_set_clip_state(struct pipe_context
*ctx
,
1074 const struct pipe_clip_state
*state
)
1079 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1080 const struct pipe_poly_stipple
*state
)
1082 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1083 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1084 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1088 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1090 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1092 ice
->state
.sample_mask
= sample_mask
;
1093 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1097 iris_set_scissor_states(struct pipe_context
*ctx
,
1098 unsigned start_slot
,
1099 unsigned num_scissors
,
1100 const struct pipe_scissor_state
*states
)
1102 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1104 ice
->state
.num_scissors
= num_scissors
;
1106 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1107 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1110 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1114 iris_set_stencil_ref(struct pipe_context
*ctx
,
1115 const struct pipe_stencil_ref
*state
)
1117 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1118 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1119 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1123 struct iris_viewport_state
{
1124 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1128 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1130 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1135 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1136 float m00
, float m11
, float m30
, float m31
,
1137 float *xmin
, float *xmax
,
1138 float *ymin
, float *ymax
)
1140 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1141 * Strips and Fans documentation:
1143 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1144 * fixed-point "guardband" range supported by the rasterization hardware"
1148 * "In almost all circumstances, if an object’s vertices are actually
1149 * modified by this clamping (i.e., had X or Y coordinates outside of
1150 * the guardband extent the rendered object will not match the intended
1151 * result. Therefore software should take steps to ensure that this does
1152 * not happen - e.g., by clipping objects such that they do not exceed
1153 * these limits after the Drawing Rectangle is applied."
1155 * I believe the fundamental restriction is that the rasterizer (in
1156 * the SF/WM stages) have a limit on the number of pixels that can be
1157 * rasterized. We need to ensure any coordinates beyond the rasterizer
1158 * limit are handled by the clipper. So effectively that limit becomes
1159 * the clipper's guardband size.
1161 * It goes on to say:
1163 * "In addition, in order to be correctly rendered, objects must have a
1164 * screenspace bounding box not exceeding 8K in the X or Y direction.
1165 * This additional restriction must also be comprehended by software,
1166 * i.e., enforced by use of clipping."
1168 * This makes no sense. Gen7+ hardware supports 16K render targets,
1169 * and you definitely need to be able to draw polygons that fill the
1170 * surface. Our assumption is that the rasterizer was limited to 8K
1171 * on Sandybridge, which only supports 8K surfaces, and it was actually
1172 * increased to 16K on Ivybridge and later.
1174 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1176 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1178 if (m00
!= 0 && m11
!= 0) {
1179 /* First, we compute the screen-space render area */
1180 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1181 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1182 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1183 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1185 /* We want the guardband to be centered on that */
1186 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1187 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1188 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1189 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1191 /* Now we need it in native device coordinates */
1192 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1193 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1194 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1195 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1197 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1198 * flipped upside-down. X should be fine though.
1200 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1201 *xmin
= ndc_gb_xmin
;
1202 *xmax
= ndc_gb_xmax
;
1203 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1204 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1206 /* The viewport scales to 0, so nothing will be rendered. */
1216 iris_set_viewport_states(struct pipe_context
*ctx
,
1217 unsigned start_slot
,
1218 unsigned num_viewports
,
1219 const struct pipe_viewport_state
*state
)
1221 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1222 struct iris_viewport_state
*cso
=
1223 malloc(sizeof(struct iris_viewport_state
));
1224 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1226 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1227 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1228 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1229 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1230 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1231 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1232 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1233 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1234 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1235 /* XXX: in i965 this is computed based on the drawbuffer size,
1236 * but we don't have that here...
1238 vp
.XMinClipGuardband
= -1.0;
1239 vp
.XMaxClipGuardband
= 1.0;
1240 vp
.YMinClipGuardband
= -1.0;
1241 vp
.YMaxClipGuardband
= 1.0;
1242 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1243 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1244 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1245 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1248 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1251 ice
->state
.cso_vp
= cso
;
1252 ice
->state
.num_viewports
= num_viewports
;
1253 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1256 struct iris_depth_state
1258 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1259 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1260 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1264 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1265 const struct pipe_framebuffer_state
*state
)
1267 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1268 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1270 if (cso
->samples
!= state
->samples
) {
1271 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1274 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1275 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1278 cso
->width
= state
->width
;
1279 cso
->height
= state
->height
;
1280 cso
->layers
= state
->layers
;
1281 cso
->samples
= state
->samples
;
1284 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1285 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1286 for (; i
< cso
->nr_cbufs
; i
++)
1287 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1289 cso
->nr_cbufs
= state
->nr_cbufs
;
1291 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1293 //struct isl_depth_stencil_hiz_emit_info info = {
1297 // XXX: depth buffers
1301 iris_set_constant_buffer(struct pipe_context
*ctx
,
1302 enum pipe_shader_type p_stage
, unsigned index
,
1303 const struct pipe_constant_buffer
*cb
)
1305 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1306 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1308 util_copy_constant_buffer(&ice
->shaders
.state
[stage
].constbuf
[index
], cb
);
1312 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1313 struct pipe_sampler_view
*state
)
1315 struct iris_surface
*isv
= (void *) state
;
1316 pipe_resource_reference(&state
->texture
, NULL
);
1317 pipe_resource_reference(&isv
->surface_state_resource
, NULL
);
1323 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1325 struct iris_surface
*surf
= (void *) p_surf
;
1326 pipe_resource_reference(&p_surf
->texture
, NULL
);
1327 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1332 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1337 struct iris_vertex_buffer_state
{
1338 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1339 struct iris_bo
*bos
[33];
1340 unsigned num_buffers
;
1344 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1347 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1348 iris_bo_unreference(cso
->bos
[i
]);
1354 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1355 unsigned start_slot
, unsigned count
,
1356 const struct pipe_vertex_buffer
*buffers
)
1358 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1359 struct iris_vertex_buffer_state
*cso
=
1360 malloc(sizeof(struct iris_vertex_buffer_state
));
1362 /* If there are no buffers, do nothing. We can leave the stale
1363 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1364 * elements that point to them, it should be fine.
1369 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1371 cso
->num_buffers
= count
;
1373 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1374 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1377 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1379 for (unsigned i
= 0; i
< count
; i
++) {
1380 assert(!buffers
[i
].is_user_buffer
);
1382 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1383 iris_bo_reference(res
->bo
);
1384 cso
->bos
[i
] = res
->bo
;
1386 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1387 vb
.VertexBufferIndex
= start_slot
+ i
;
1389 vb
.AddressModifyEnable
= true;
1390 vb
.BufferPitch
= buffers
[i
].stride
;
1391 vb
.BufferSize
= res
->bo
->size
;
1392 vb
.BufferStartingAddress
=
1393 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1396 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1399 ice
->state
.cso_vertex_buffers
= cso
;
1400 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1403 struct iris_vertex_element_state
{
1404 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1405 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1410 iris_create_vertex_elements(struct pipe_context
*ctx
,
1412 const struct pipe_vertex_element
*state
)
1414 struct iris_vertex_element_state
*cso
=
1415 malloc(sizeof(struct iris_vertex_element_state
));
1420 * - create edge flag one
1422 * - if those are necessary, use count + 1/2/3... OR in the length
1424 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1426 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1428 for (int i
= 0; i
< count
; i
++) {
1429 enum isl_format isl_format
=
1430 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1431 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1432 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1434 switch (isl_format_get_num_channels(isl_format
)) {
1435 case 0: comp
[0] = VFCOMP_STORE_0
;
1436 case 1: comp
[1] = VFCOMP_STORE_0
;
1437 case 2: comp
[2] = VFCOMP_STORE_0
;
1439 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1440 : VFCOMP_STORE_1_FP
;
1443 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1444 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1446 ve
.SourceElementOffset
= state
[i
].src_offset
;
1447 ve
.SourceElementFormat
= isl_format
;
1448 ve
.Component0Control
= comp
[0];
1449 ve
.Component1Control
= comp
[1];
1450 ve
.Component2Control
= comp
[2];
1451 ve
.Component3Control
= comp
[3];
1454 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1455 vi
.VertexElementIndex
= i
;
1456 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1457 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1460 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1467 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1469 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1471 ice
->state
.cso_vertex_elements
= state
;
1472 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1476 iris_create_compute_state(struct pipe_context
*ctx
,
1477 const struct pipe_compute_state
*state
)
1482 static struct pipe_stream_output_target
*
1483 iris_create_stream_output_target(struct pipe_context
*ctx
,
1484 struct pipe_resource
*res
,
1485 unsigned buffer_offset
,
1486 unsigned buffer_size
)
1488 struct pipe_stream_output_target
*t
=
1489 CALLOC_STRUCT(pipe_stream_output_target
);
1493 pipe_reference_init(&t
->reference
, 1);
1494 pipe_resource_reference(&t
->buffer
, res
);
1495 t
->buffer_offset
= buffer_offset
;
1496 t
->buffer_size
= buffer_size
;
1501 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1502 struct pipe_stream_output_target
*t
)
1504 pipe_resource_reference(&t
->buffer
, NULL
);
1509 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1510 unsigned num_targets
,
1511 struct pipe_stream_output_target
**targets
,
1512 const unsigned *offsets
)
1517 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1518 const struct brw_vue_map
*last_vue_map
,
1519 bool two_sided_color
,
1520 unsigned *out_offset
,
1521 unsigned *out_length
)
1523 /* The compiler computes the first URB slot without considering COL/BFC
1524 * swizzling (because it doesn't know whether it's enabled), so we need
1525 * to do that here too. This may result in a smaller offset, which
1528 const unsigned first_slot
=
1529 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1531 /* This becomes the URB read offset (counted in pairs of slots). */
1532 assert(first_slot
% 2 == 0);
1533 *out_offset
= first_slot
/ 2;
1535 /* We need to adjust the inputs read to account for front/back color
1536 * swizzling, as it can make the URB length longer.
1538 for (int c
= 0; c
<= 1; c
++) {
1539 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1540 /* If two sided color is enabled, the fragment shader's gl_Color
1541 * (COL0) input comes from either the gl_FrontColor (COL0) or
1542 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1544 if (two_sided_color
)
1545 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1547 /* If front color isn't written, we opt to give them back color
1548 * instead of an undefined value. Switch from COL to BFC.
1550 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1551 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1552 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1557 /* Compute the minimum URB Read Length necessary for the FS inputs.
1559 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1560 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1562 * "This field should be set to the minimum length required to read the
1563 * maximum source attribute. The maximum source attribute is indicated
1564 * by the maximum value of the enabled Attribute # Source Attribute if
1565 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1566 * enable is not set.
1567 * read_length = ceiling((max_source_attr + 1) / 2)
1569 * [errata] Corruption/Hang possible if length programmed larger than
1572 * Similar text exists for Ivy Bridge.
1574 * We find the last URB slot that's actually read by the FS.
1576 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1577 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1578 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1581 /* The URB read length is the difference of the two, counted in pairs. */
1582 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1586 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1588 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1589 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1590 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1591 struct pipe_shader_state
*p_fs
=
1592 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1593 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1594 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1596 unsigned urb_read_offset
, urb_read_length
;
1597 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1598 ice
->shaders
.last_vue_map
,
1599 cso_rast
->light_twoside
,
1600 &urb_read_offset
, &urb_read_length
);
1602 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1603 sbe
.AttributeSwizzleEnable
= true;
1604 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1605 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1606 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1607 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1608 sbe
.ForceVertexURBEntryReadOffset
= true;
1609 sbe
.ForceVertexURBEntryReadLength
= true;
1610 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1612 for (int i
= 0; i
< 32; i
++) {
1613 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1619 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1624 iris_populate_sampler_key(const struct iris_context
*ice
,
1625 struct brw_sampler_prog_key_data
*key
)
1627 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1628 key
->swizzles
[i
] = 0x688; /* XYZW */
1633 iris_populate_vs_key(const struct iris_context
*ice
,
1634 struct brw_vs_prog_key
*key
)
1636 memset(key
, 0, sizeof(*key
));
1637 iris_populate_sampler_key(ice
, &key
->tex
);
1641 iris_populate_tcs_key(const struct iris_context
*ice
,
1642 struct brw_tcs_prog_key
*key
)
1644 memset(key
, 0, sizeof(*key
));
1645 iris_populate_sampler_key(ice
, &key
->tex
);
1649 iris_populate_tes_key(const struct iris_context
*ice
,
1650 struct brw_tes_prog_key
*key
)
1652 memset(key
, 0, sizeof(*key
));
1653 iris_populate_sampler_key(ice
, &key
->tex
);
1657 iris_populate_gs_key(const struct iris_context
*ice
,
1658 struct brw_gs_prog_key
*key
)
1660 memset(key
, 0, sizeof(*key
));
1661 iris_populate_sampler_key(ice
, &key
->tex
);
1665 iris_populate_fs_key(const struct iris_context
*ice
,
1666 struct brw_wm_prog_key
*key
)
1668 memset(key
, 0, sizeof(*key
));
1669 iris_populate_sampler_key(ice
, &key
->tex
);
1671 /* XXX: dirty flags? */
1672 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1673 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1674 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1675 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1677 key
->nr_color_regions
= fb
->nr_cbufs
;
1679 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1681 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1682 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1684 // key->force_dual_color_blend for unigine
1686 if (cso_rast
->multisample
) {
1687 key
->persample_interp
=
1688 ctx
->Multisample
.SampleShading
&&
1689 (ctx
->Multisample
.MinSampleShadingValue
*
1690 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1692 key
->multisample_fbo
= fb
->samples
> 1;
1696 key
->coherent_fb_fetch
= true;
1699 //pkt.SamplerCount = \
1700 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1701 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1702 //ffs(stage_state->per_thread_scratch) - 11; \
1705 KSP(const struct iris_compiled_shader
*shader
)
1707 struct iris_resource
*res
= (void *) shader
->buffer
;
1708 return res
->bo
->gtt_offset
+ shader
->offset
;
1711 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1712 pkt.KernelStartPointer = KSP(shader); \
1713 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1714 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1716 pkt.DispatchGRFStartRegisterForURBData = \
1717 prog_data->dispatch_grf_start_reg; \
1718 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1719 pkt.prefix##URBEntryReadOffset = 0; \
1721 pkt.StatisticsEnable = true; \
1725 iris_set_vs_state(const struct gen_device_info
*devinfo
,
1726 struct iris_compiled_shader
*shader
)
1728 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1729 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1731 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1732 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1733 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1734 vs
.SIMD8DispatchEnable
= true;
1735 vs
.UserClipDistanceCullTestEnableBitmask
=
1736 vue_prog_data
->cull_distance_mask
;
1741 iris_set_tcs_state(const struct gen_device_info
*devinfo
,
1742 struct iris_compiled_shader
*shader
)
1744 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1745 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1746 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1748 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1749 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1751 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1752 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1753 hs
.IncludeVertexHandles
= true;
1758 iris_set_tes_state(const struct gen_device_info
*devinfo
,
1759 struct iris_compiled_shader
*shader
)
1761 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1762 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1763 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1765 uint32_t *te_state
= (void *) shader
->derived_data
;
1766 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1768 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1769 te
.Partitioning
= tes_prog_data
->partitioning
;
1770 te
.OutputTopology
= tes_prog_data
->output_topology
;
1771 te
.TEDomain
= tes_prog_data
->domain
;
1773 te
.MaximumTessellationFactorOdd
= 63.0;
1774 te
.MaximumTessellationFactorNotOdd
= 64.0;
1777 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1778 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1780 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1781 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1782 ds
.ComputeWCoordinateEnable
=
1783 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1785 ds
.UserClipDistanceCullTestEnableBitmask
=
1786 vue_prog_data
->cull_distance_mask
;
1792 iris_set_gs_state(const struct gen_device_info
*devinfo
,
1793 struct iris_compiled_shader
*shader
)
1795 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1796 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1797 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1799 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1800 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1802 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1803 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1804 gs
.ControlDataHeaderSize
=
1805 gs_prog_data
->control_data_header_size_hwords
;
1806 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1807 gs
.DispatchMode
= SIMD8
;
1808 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1809 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1810 gs
.ReorderMode
= TRAILING
;
1811 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1812 gs
.MaximumNumberofThreads
=
1813 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1814 : (devinfo
->max_gs_threads
- 1);
1816 if (gs_prog_data
->static_vertex_count
!= -1) {
1817 gs
.StaticOutput
= true;
1818 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1820 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1822 gs
.UserClipDistanceCullTestEnableBitmask
=
1823 vue_prog_data
->cull_distance_mask
;
1825 const int urb_entry_write_offset
= 1;
1826 const uint32_t urb_entry_output_length
=
1827 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1828 urb_entry_write_offset
;
1830 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1831 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1836 iris_set_fs_state(const struct gen_device_info
*devinfo
,
1837 struct iris_compiled_shader
*shader
)
1839 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1840 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1842 uint32_t *ps_state
= (void *) shader
->derived_data
;
1843 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1845 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1846 ps
.VectorMaskEnable
= true;
1847 //ps.SamplerCount = ...
1848 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1849 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1850 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1852 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1853 prog_data
->ubo_ranges
[0].length
> 0;
1855 /* From the documentation for this packet:
1856 * "If the PS kernel does not need the Position XY Offsets to
1857 * compute a Position Value, then this field should be programmed
1858 * to POSOFFSET_NONE."
1860 * "SW Recommendation: If the PS kernel needs the Position Offsets
1861 * to compute a Position XY value, this field should match Position
1862 * ZW Interpolation Mode to ensure a consistent position.xyzw
1865 * We only require XY sample offsets. So, this recommendation doesn't
1866 * look useful at the moment. We might need this in future.
1868 ps
.PositionXYOffsetSelect
=
1869 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1870 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1871 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1872 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1874 // XXX: Disable SIMD32 with 16x MSAA
1876 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1877 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1878 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1879 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1880 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1881 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1883 ps
.KernelStartPointer0
=
1884 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1885 ps
.KernelStartPointer1
=
1886 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1887 ps
.KernelStartPointer2
=
1888 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1891 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1892 psx
.PixelShaderValid
= true;
1893 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1894 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1895 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1896 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1897 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1898 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1900 if (wm_prog_data
->uses_sample_mask
) {
1901 /* TODO: conservative rasterization */
1902 if (wm_prog_data
->post_depth_coverage
)
1903 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1905 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
1908 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1909 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1910 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1917 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
1919 assert(cache_id
<= IRIS_CACHE_CS
);
1921 static const unsigned dwords
[] = {
1922 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
1923 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
1924 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
1925 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
1927 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
1928 [IRIS_CACHE_CS
] = 0,
1929 [IRIS_CACHE_BLORP_BLIT
] = 0,
1932 return sizeof(uint32_t) * dwords
[cache_id
];
1936 iris_set_derived_program_state(const struct gen_device_info
*devinfo
,
1937 enum iris_program_cache_id cache_id
,
1938 struct iris_compiled_shader
*shader
)
1942 iris_set_vs_state(devinfo
, shader
);
1944 case IRIS_CACHE_TCS
:
1945 iris_set_tcs_state(devinfo
, shader
);
1947 case IRIS_CACHE_TES
:
1948 iris_set_tes_state(devinfo
, shader
);
1951 iris_set_gs_state(devinfo
, shader
);
1954 iris_set_fs_state(devinfo
, shader
);
1964 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
1966 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1967 const unsigned push_size_kB
= 32;
1968 unsigned entries
[4];
1972 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1973 if (!ice
->shaders
.prog
[i
]) {
1976 struct brw_vue_prog_data
*vue_prog_data
=
1977 (void *) ice
->shaders
.prog
[i
]->prog_data
;
1978 size
[i
] = vue_prog_data
->urb_entry_size
;
1980 assert(size
[i
] != 0);
1983 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
1984 1024 * ice
->shaders
.urb_size
,
1985 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
1986 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
1987 size
, entries
, start
);
1989 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1990 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
1991 urb
._3DCommandSubOpcode
+= i
;
1992 urb
.VSURBStartingAddress
= start
[i
];
1993 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
1994 urb
.VSNumberofURBEntries
= entries
[i
];
1999 static const uint32_t push_constant_opcodes
[] = {
2000 [MESA_SHADER_VERTEX
] = 21,
2001 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2002 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2003 [MESA_SHADER_GEOMETRY
] = 22,
2004 [MESA_SHADER_FRAGMENT
] = 23,
2005 [MESA_SHADER_COMPUTE
] = 0,
2009 * Add a surface to the validation list, as well as the buffer containing
2010 * the corresponding SURFACE_STATE.
2012 * Returns the binding table entry (offset to SURFACE_STATE).
2015 use_surface(struct iris_batch
*batch
,
2016 struct pipe_surface
*p_surf
,
2019 struct iris_surface
*surf
= (void *) p_surf
;
2020 struct iris_resource
*res
= (void *) p_surf
->texture
;
2021 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
2022 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
2023 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2025 return surf
->surface_state_offset
;
2029 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2031 struct iris_resource
*res
= (void *) isv
->pipe
.texture
;
2032 struct iris_resource
*state_res
= (void *) isv
->surface_state_resource
;
2033 iris_use_pinned_bo(batch
, res
->bo
, false);
2034 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2036 return isv
->surface_state_offset
;
2040 iris_upload_render_state(struct iris_context
*ice
,
2041 struct iris_batch
*batch
,
2042 const struct pipe_draw_info
*draw
)
2044 const uint64_t dirty
= ice
->state
.dirty
;
2046 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2047 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2049 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2050 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2051 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2052 ptr
.CCViewportPointer
=
2053 emit_state(batch
, ice
->state
.dynamic_uploader
,
2054 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2058 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2059 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2060 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2061 ptr
.SFClipViewportPointer
=
2062 emit_state(batch
, ice
->state
.dynamic_uploader
, cso
->sf_cl_vp
,
2063 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2064 ice
->state
.num_viewports
, 64);
2070 if (dirty
& IRIS_DIRTY_URB
) {
2071 iris_upload_urb_config(ice
, batch
);
2074 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2075 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2076 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2077 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2078 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2079 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2080 uint32_t blend_offset
;
2081 uint32_t *blend_map
=
2082 stream_state(batch
, ice
->state
.dynamic_uploader
, 4 * num_dwords
, 64,
2085 uint32_t blend_state_header
;
2086 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2087 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2088 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2091 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2092 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2093 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2095 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2096 ptr
.BlendStatePointer
= blend_offset
;
2097 ptr
.BlendStatePointerValid
= true;
2101 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2102 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2105 stream_state(batch
, ice
->state
.dynamic_uploader
,
2106 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2108 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2109 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2110 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2111 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2112 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2113 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2114 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2116 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2117 ptr
.ColorCalcStatePointer
= cc_offset
;
2118 ptr
.ColorCalcStatePointerValid
= true;
2122 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2123 // XXX: wrong dirty tracking...
2124 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2127 struct pipe_constant_buffer
*cbuf0
=
2128 &ice
->shaders
.state
[stage
].constbuf
[0];
2130 if (!ice
->shaders
.prog
[stage
] || cbuf0
->buffer
|| !cbuf0
->buffer_size
)
2133 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2134 shs
->const_size
= cbuf0
->buffer_size
;
2135 u_upload_data(ice
->ctx
.const_uploader
, 0, shs
->const_size
, 32,
2136 cbuf0
->user_buffer
, &shs
->const_offset
,
2137 &shs
->push_resource
);
2140 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2141 // XXX: wrong dirty tracking...
2142 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2145 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2146 struct iris_resource
*res
= (void *) shs
->push_resource
;
2148 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2149 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2151 pkt
.ConstantBody
.ReadLength
[3] = shs
->const_size
;
2152 pkt
.ConstantBody
.Buffer
[3] = ro_bo(res
->bo
, shs
->const_offset
);
2159 // - ubos/ssbos/abos
2162 // - render targets - write and read
2163 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
2165 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2166 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2167 if (!shader
) // XXX: dirty bits...also, emit a disable maybe?
2170 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2171 uint32_t bt_offset
= 0;
2172 uint32_t *bt_map
= NULL
;
2175 if (prog_data
->binding_table
.size_bytes
!= 0) {
2176 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
2177 bt_map
= iris_binder_reserve(&ice
->state
.binder
,
2178 prog_data
->binding_table
.size_bytes
,
2182 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2183 ptr
._3DCommandSubOpcode
= 38 + stage
;
2184 ptr
.PointertoVSBindingTable
= bt_offset
;
2187 if (stage
== MESA_SHADER_FRAGMENT
) {
2188 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2189 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2190 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2194 assert(prog_data
->binding_table
.texture_start
==
2195 (ice
->state
.num_textures
[stage
] ? s
: 0xd0d0d0d0));
2197 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2198 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2199 bt_map
[s
++] = use_sampler_view(batch
, view
);
2203 // XXX: not implemented yet
2204 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2205 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2206 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2207 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2208 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2209 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2210 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2214 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2215 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2216 !ice
->shaders
.prog
[stage
])
2219 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2220 ptr
._3DCommandSubOpcode
= 43 + stage
;
2221 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2225 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2226 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2228 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2229 if (ice
->state
.framebuffer
.samples
> 0)
2230 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2234 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2235 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2236 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2240 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2241 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2244 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2247 struct iris_resource
*cache
= (void *) shader
->buffer
;
2248 iris_use_pinned_bo(batch
, cache
->bo
, false);
2249 iris_batch_emit(batch
, shader
->derived_data
,
2250 iris_derived_program_state_size(stage
));
2252 if (stage
== MESA_SHADER_TESS_EVAL
) {
2253 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2254 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2255 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2256 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2257 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2263 // 3DSTATE_STREAMOUT
2264 // 3DSTATE_SO_BUFFER
2265 // 3DSTATE_SO_DECL_LIST
2267 if (dirty
& IRIS_DIRTY_CLIP
) {
2268 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2269 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2271 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2272 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2273 if (wm_prog_data
->barycentric_interp_modes
&
2274 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2275 cl
.NonPerspectiveBarycentricEnable
= true;
2277 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2279 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2280 ARRAY_SIZE(cso_rast
->clip
));
2283 if (dirty
& IRIS_DIRTY_RASTER
) {
2284 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2285 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2286 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2290 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_FS
)) {
2291 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2292 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2294 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2295 wm
.BarycentricInterpolationMode
=
2296 wm_prog_data
->barycentric_interp_modes
;
2298 if (wm_prog_data
->early_fragment_tests
)
2299 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2300 else if (wm_prog_data
->has_side_effects
)
2301 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2303 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2307 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2308 // -> iris_raster_state (point sprite texture coordinate origin)
2309 // -> bunch of shader state...
2310 iris_emit_sbe(batch
, ice
);
2311 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2315 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2316 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2317 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2318 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2319 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2320 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2321 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2324 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2325 ARRAY_SIZE(cso_blend
->ps_blend
));
2328 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2329 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2330 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2332 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2333 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2334 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2335 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2337 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2340 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2341 // XXX: allocate at set_scissor time?
2342 uint32_t scissor_offset
= ice
->state
.num_scissors
== 0 ? 0 :
2343 emit_state(batch
, ice
->state
.dynamic_uploader
, ice
->state
.scissors
,
2344 sizeof(struct pipe_scissor_state
) *
2345 ice
->state
.num_scissors
, 32);
2347 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2348 ptr
.ScissorRectPointer
= scissor_offset
;
2352 // XXX: 3DSTATE_DEPTH_BUFFER
2353 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
2354 // XXX: 3DSTATE_STENCIL_BUFFER
2355 // XXX: 3DSTATE_CLEAR_PARAMS
2357 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2358 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2359 for (int i
= 0; i
< 32; i
++) {
2360 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2365 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2366 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2367 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2371 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2372 topo
.PrimitiveTopologyType
=
2373 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2377 if (draw
->index_size
> 0) {
2378 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
2380 assert(!draw
->has_user_indices
);
2382 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2383 ib
.IndexFormat
= draw
->index_size
;
2385 ib
.BufferSize
= res
->bo
->size
;
2386 ib
.BufferStartingAddress
= ro_bo(res
->bo
, 0);
2390 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2391 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2393 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
2394 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
2396 iris_batch_emit(batch
, cso
->vertex_buffers
,
2397 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
2399 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2400 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2404 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2405 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2406 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2407 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2408 for (int i
= 0; i
< cso
->count
; i
++) {
2409 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
2410 (cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
)));
2412 for (int i
= 0; i
< cso
->count
; i
++) {
2413 /* TODO: vertexid, instanceid support */
2414 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2419 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2420 if (draw
->primitive_restart
) {
2421 vf
.IndexedDrawCutIndexEnable
= true;
2422 vf
.CutIndex
= draw
->restart_index
;
2427 // XXX: Gen8 - PMA fix
2429 assert(!draw
->indirect
); // XXX: indirect support
2431 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2432 prim
.StartInstanceLocation
= draw
->start_instance
;
2433 prim
.InstanceCount
= draw
->instance_count
;
2434 prim
.VertexCountPerInstance
= draw
->count
;
2435 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2437 // XXX: this is probably bonkers.
2438 prim
.StartVertexLocation
= draw
->start
;
2440 if (draw
->index_size
) {
2441 prim
.BaseVertexLocation
+= draw
->index_bias
;
2443 prim
.StartVertexLocation
+= draw
->index_bias
;
2446 //prim.BaseVertexLocation = ...;
2451 iris_destroy_state(struct iris_context
*ice
)
2453 // XXX: unreference resources/surfaces.
2454 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2455 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2457 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2461 flags_to_post_sync_op(uint32_t flags
)
2463 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2464 return WriteImmediateData
;
2466 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2467 return WritePSDepthCount
;
2469 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2470 return WriteTimestamp
;
2476 * Do the given flags have a Post Sync or LRI Post Sync operation?
2478 static enum pipe_control_flags
2479 get_post_sync_flags(enum pipe_control_flags flags
)
2481 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2482 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2483 PIPE_CONTROL_WRITE_TIMESTAMP
|
2484 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2486 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2487 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2489 assert(util_bitcount(flags
) <= 1);
2494 // XXX: compute support
2495 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2498 * Emit a series of PIPE_CONTROL commands, taking into account any
2499 * workarounds necessary to actually accomplish the caller's request.
2501 * Unless otherwise noted, spec quotations in this function come from:
2503 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2504 * Restrictions for PIPE_CONTROL.
2507 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2508 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2510 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2511 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2512 enum pipe_control_flags non_lri_post_sync_flags
=
2513 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2515 /* Recursive PIPE_CONTROL workarounds --------------------------------
2516 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2518 * We do these first because we want to look at the original operation,
2519 * rather than any workarounds we set.
2521 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2522 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2523 * lists several workarounds:
2525 * "Project: SKL, KBL, BXT
2527 * If the VF Cache Invalidation Enable is set to a 1 in a
2528 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2529 * sets to 0, with the VF Cache Invalidation Enable set to 0
2530 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2531 * Invalidation Enable set to a 1."
2533 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2536 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2537 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2539 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2540 * programmed prior to programming a PIPECONTROL command with "LRI
2541 * Post Sync Operation" in GPGPU mode of operation (i.e when
2542 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2544 * The same text exists a few rows below for Post Sync Op.
2546 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2549 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2551 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2552 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2553 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2555 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2559 /* "Flush Types" workarounds ---------------------------------------------
2560 * We do these now because they may add post-sync operations or CS stalls.
2563 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2564 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2566 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
2567 * 'Write PS Depth Count' or 'Write Timestamp'."
2570 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2571 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2572 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2573 bo
= batch
->screen
->workaround_bo
;
2577 /* #1130 from Gen10 workarounds page:
2579 * "Enable Depth Stall on every Post Sync Op if Render target Cache
2580 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
2581 * board stall if Render target cache flush is enabled."
2583 * Applicable to CNL B0 and C0 steppings only.
2585 * The wording here is unclear, and this workaround doesn't look anything
2586 * like the internal bug report recommendations, but leave it be for now...
2588 if (GEN_GEN
== 10) {
2589 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
2590 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2591 } else if (flags
& non_lri_post_sync_flags
) {
2592 flags
|= PIPE_CONTROL_DEPTH_STALL
;
2596 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
2597 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
2599 * "This bit must be DISABLED for operations other than writing
2602 * This seems like nonsense. An Ivybridge workaround requires us to
2603 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
2604 * operation. Gen8+ requires us to emit depth stalls and depth cache
2605 * flushes together. So, it's hard to imagine this means anything other
2606 * than "we originally intended this to be used for PS_DEPTH_COUNT".
2608 * We ignore the supposed restriction and do nothing.
2612 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2613 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
2614 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
2616 * "This bit must be DISABLED for End-of-pipe (Read) fences,
2617 * PS_DEPTH_COUNT or TIMESTAMP queries."
2619 * TODO: Implement end-of-pipe checking.
2621 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2622 PIPE_CONTROL_WRITE_TIMESTAMP
)));
2625 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
2626 /* From the PIPE_CONTROL instruction table, bit 1:
2628 * "This bit is ignored if Depth Stall Enable is set.
2629 * Further, the render cache is not flushed even if Write Cache
2630 * Flush Enable bit is set."
2632 * We assert that the caller doesn't do this combination, to try and
2633 * prevent mistakes. It shouldn't hurt the GPU, though.
2635 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
2636 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
2639 /* PIPE_CONTROL page workarounds ------------------------------------- */
2641 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
2642 /* From the PIPE_CONTROL page itself:
2645 * Restriction: Pipe_control with CS-stall bit set must be issued
2646 * before a pipe-control command that has the State Cache
2647 * Invalidate bit set."
2649 flags
|= PIPE_CONTROL_CS_STALL
;
2652 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
2653 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
2656 * SW must always program Post-Sync Operation to "Write Immediate
2657 * Data" when Flush LLC is set."
2659 * For now, we just require the caller to do it.
2661 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
2664 /* "Post-Sync Operation" workarounds -------------------------------- */
2666 /* Project: All / Argument: Global Snapshot Count Reset [19]
2668 * "This bit must not be exercised on any product.
2669 * Requires stall bit ([20] of DW1) set."
2671 * We don't use this, so we just assert that it isn't used. The
2672 * PIPE_CONTROL instruction page indicates that they intended this
2673 * as a debug feature and don't think it is useful in production,
2674 * but it may actually be usable, should we ever want to.
2676 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
2678 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
2679 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
2680 /* Project: All / Arguments:
2682 * - Generic Media State Clear [16]
2683 * - Indirect State Pointers Disable [16]
2685 * "Requires stall bit ([20] of DW1) set."
2687 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
2688 * State Clear) says:
2690 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2691 * programmed prior to programming a PIPECONTROL command with "Media
2692 * State Clear" set in GPGPU mode of operation"
2694 * This is a subset of the earlier rule, so there's nothing to do.
2696 flags
|= PIPE_CONTROL_CS_STALL
;
2699 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
2700 /* Project: All / Argument: Store Data Index
2702 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2705 * For now, we just assert that the caller does this. We might want to
2706 * automatically add a write to the workaround BO...
2708 assert(non_lri_post_sync_flags
!= 0);
2711 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
2712 /* Project: All / Argument: Sync GFDT
2714 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2715 * than '0' or 0x2520[13] must be set."
2717 * For now, we just assert that the caller does this.
2719 assert(non_lri_post_sync_flags
!= 0);
2722 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
2723 /* Project: IVB+ / Argument: TLB inv
2725 * "Requires stall bit ([20] of DW1) set."
2727 * Also, from the PIPE_CONTROL instruction table:
2730 * Post Sync Operation or CS stall must be set to ensure a TLB
2731 * invalidation occurs. Otherwise no cycle will occur to the TLB
2732 * cache to invalidate."
2734 * This is not a subset of the earlier rule, so there's nothing to do.
2736 flags
|= PIPE_CONTROL_CS_STALL
;
2739 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
2740 /* TODO: The big Skylake GT4 post sync op workaround */
2743 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
2745 if (IS_COMPUTE_PIPELINE(batch
)) {
2746 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
2747 /* Project: SKL+ / Argument: Tex Invalidate
2748 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
2750 flags
|= PIPE_CONTROL_CS_STALL
;
2753 if (GEN_GEN
== 8 && (post_sync_flags
||
2754 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
2755 PIPE_CONTROL_DEPTH_STALL
|
2756 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2757 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2758 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
2759 /* Project: BDW / Arguments:
2761 * - LRI Post Sync Operation [23]
2762 * - Post Sync Op [15:14]
2764 * - Depth Stall [13]
2765 * - Render Target Cache Flush [12]
2766 * - Depth Cache Flush [0]
2767 * - DC Flush Enable [5]
2769 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
2772 flags
|= PIPE_CONTROL_CS_STALL
;
2774 /* Also, from the PIPE_CONTROL instruction table, bit 20:
2777 * This bit must be always set when PIPE_CONTROL command is
2778 * programmed by GPGPU and MEDIA workloads, except for the cases
2779 * when only Read Only Cache Invalidation bits are set (State
2780 * Cache Invalidation Enable, Instruction cache Invalidation
2781 * Enable, Texture Cache Invalidation Enable, Constant Cache
2782 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
2783 * need not implemented when FF_DOP_CG is disable via "Fixed
2784 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
2786 * It sounds like we could avoid CS stalls in some cases, but we
2787 * don't currently bother. This list isn't exactly the list above,
2793 /* "Stall" workarounds ----------------------------------------------
2794 * These have to come after the earlier ones because we may have added
2795 * some additional CS stalls above.
2798 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
2799 /* Project: PRE-SKL, VLV, CHV
2801 * "[All Stepping][All SKUs]:
2803 * One of the following must also be set:
2805 * - Render Target Cache Flush Enable ([12] of DW1)
2806 * - Depth Cache Flush Enable ([0] of DW1)
2807 * - Stall at Pixel Scoreboard ([1] of DW1)
2808 * - Depth Stall ([13] of DW1)
2809 * - Post-Sync Operation ([13] of DW1)
2810 * - DC Flush Enable ([5] of DW1)"
2812 * If we don't already have one of those bits set, we choose to add
2813 * "Stall at Pixel Scoreboard". Some of the other bits require a
2814 * CS stall as a workaround (see above), which would send us into
2815 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
2816 * appears to be safe, so we choose that.
2818 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2819 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2820 PIPE_CONTROL_WRITE_IMMEDIATE
|
2821 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2822 PIPE_CONTROL_WRITE_TIMESTAMP
|
2823 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
2824 PIPE_CONTROL_DEPTH_STALL
|
2825 PIPE_CONTROL_DATA_CACHE_FLUSH
;
2826 if (!(flags
& wa_bits
))
2827 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2830 /* Emit --------------------------------------------------------------- */
2832 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
2833 pc
.LRIPostSyncOperation
= NoLRIOperation
;
2834 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
2835 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
2836 pc
.StoreDataIndex
= 0;
2837 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
2838 pc
.GlobalSnapshotCountReset
=
2839 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
2840 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
2841 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
2842 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2843 pc
.RenderTargetCacheFlushEnable
=
2844 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2845 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
2846 pc
.StateCacheInvalidationEnable
=
2847 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
2848 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2849 pc
.ConstantCacheInvalidationEnable
=
2850 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
2851 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
2852 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
2853 pc
.InstructionCacheInvalidateEnable
=
2854 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
2855 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
2856 pc
.IndirectStatePointersDisable
=
2857 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
2858 pc
.TextureCacheInvalidationEnable
=
2859 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2860 pc
.Address
= ro_bo(bo
, offset
);
2861 pc
.ImmediateData
= imm
;
2866 genX(init_state
)(struct iris_context
*ice
)
2868 struct pipe_context
*ctx
= &ice
->ctx
;
2870 ctx
->create_blend_state
= iris_create_blend_state
;
2871 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
2872 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
2873 ctx
->create_sampler_state
= iris_create_sampler_state
;
2874 ctx
->create_sampler_view
= iris_create_sampler_view
;
2875 ctx
->create_surface
= iris_create_surface
;
2876 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
2877 ctx
->create_compute_state
= iris_create_compute_state
;
2878 ctx
->bind_blend_state
= iris_bind_blend_state
;
2879 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
2880 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
2881 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
2882 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
2883 ctx
->bind_compute_state
= iris_bind_compute_state
;
2884 ctx
->delete_blend_state
= iris_delete_state
;
2885 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
2886 ctx
->delete_fs_state
= iris_delete_state
;
2887 ctx
->delete_rasterizer_state
= iris_delete_state
;
2888 ctx
->delete_sampler_state
= iris_delete_state
;
2889 ctx
->delete_vertex_elements_state
= iris_delete_state
;
2890 ctx
->delete_compute_state
= iris_delete_state
;
2891 ctx
->delete_tcs_state
= iris_delete_state
;
2892 ctx
->delete_tes_state
= iris_delete_state
;
2893 ctx
->delete_gs_state
= iris_delete_state
;
2894 ctx
->delete_vs_state
= iris_delete_state
;
2895 ctx
->set_blend_color
= iris_set_blend_color
;
2896 ctx
->set_clip_state
= iris_set_clip_state
;
2897 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
2898 ctx
->set_sampler_views
= iris_set_sampler_views
;
2899 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
2900 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
2901 ctx
->set_sample_mask
= iris_set_sample_mask
;
2902 ctx
->set_scissor_states
= iris_set_scissor_states
;
2903 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
2904 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
2905 ctx
->set_viewport_states
= iris_set_viewport_states
;
2906 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
2907 ctx
->surface_destroy
= iris_surface_destroy
;
2908 ctx
->draw_vbo
= iris_draw_vbo
;
2909 ctx
->launch_grid
= iris_launch_grid
;
2910 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
2911 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
2912 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
2914 ice
->state
.destroy_state
= iris_destroy_state
;
2915 ice
->state
.init_render_context
= iris_init_render_context
;
2916 ice
->state
.upload_render_state
= iris_upload_render_state
;
2917 ice
->state
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
2918 ice
->state
.derived_program_state_size
= iris_derived_program_state_size
;
2919 ice
->state
.set_derived_program_state
= iris_set_derived_program_state
;
2920 ice
->state
.populate_vs_key
= iris_populate_vs_key
;
2921 ice
->state
.populate_tcs_key
= iris_populate_tcs_key
;
2922 ice
->state
.populate_tes_key
= iris_populate_tes_key
;
2923 ice
->state
.populate_gs_key
= iris_populate_gs_key
;
2924 ice
->state
.populate_fs_key
= iris_populate_fs_key
;
2926 ice
->state
.dirty
= ~0ull;