2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_transfer.h"
41 #include "util/u_upload_mgr.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/common/gen_l3_config.h"
46 #include "intel/common/gen_sample_positions.h"
47 #include "iris_batch.h"
48 #include "iris_context.h"
49 #include "iris_pipe.h"
50 #include "iris_resource.h"
52 #define __gen_address_type struct iris_address
53 #define __gen_user_data struct iris_batch
55 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
58 __gen_combine_address(struct iris_batch
*batch
, void *location
,
59 struct iris_address addr
, uint32_t delta
)
61 uint64_t result
= addr
.offset
+ delta
;
64 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
65 /* Assume this is a general address, not relative to a base. */
66 result
+= addr
.bo
->gtt_offset
;
72 #define __genxml_cmd_length(cmd) cmd ## _length
73 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
74 #define __genxml_cmd_header(cmd) cmd ## _header
75 #define __genxml_cmd_pack(cmd) cmd ## _pack
77 #define _iris_pack_command(batch, cmd, dst, name) \
78 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
79 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
80 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
84 #define iris_pack_command(cmd, dst, name) \
85 _iris_pack_command(NULL, cmd, dst, name)
87 #define iris_pack_state(cmd, dst, name) \
88 for (struct cmd name = {}, \
89 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
90 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
93 #define iris_emit_cmd(batch, cmd, name) \
94 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
96 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
98 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
99 for (uint32_t i = 0; i < num_dwords; i++) \
100 dw[i] = (dwords0)[i] | (dwords1)[i]; \
101 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
104 #include "genxml/genX_pack.h"
105 #include "genxml/gen_macros.h"
106 #include "genxml/genX_bits.h"
108 #define MOCS_WB (2 << 1)
110 UNUSED
static void pipe_asserts()
112 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
114 /* pipe_logicop happens to match the hardware. */
115 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
116 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
117 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
118 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
119 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
120 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
121 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
122 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
123 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
124 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
125 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
126 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
127 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
128 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
129 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
130 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
132 /* pipe_blend_func happens to match the hardware. */
133 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
134 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
153 /* pipe_blend_func happens to match the hardware. */
154 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
155 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
156 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
157 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
158 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
160 /* pipe_stencil_op happens to match the hardware. */
161 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
162 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
163 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
164 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
165 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
170 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
171 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
172 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
177 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
179 static const unsigned map
[] = {
180 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
181 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
182 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
183 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
184 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
185 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
186 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
187 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
188 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
189 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
190 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
191 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
192 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
193 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
194 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
197 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
201 translate_compare_func(enum pipe_compare_func pipe_func
)
203 static const unsigned map
[] = {
204 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
205 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
206 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
207 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
208 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
209 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
210 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
211 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
213 return map
[pipe_func
];
217 translate_shadow_func(enum pipe_compare_func pipe_func
)
219 /* Gallium specifies the result of shadow comparisons as:
221 * 1 if ref <op> texel,
226 * 0 if texel <op> ref,
229 * So we need to flip the operator and also negate.
231 static const unsigned map
[] = {
232 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
233 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
234 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
235 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
236 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
237 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
238 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
239 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
241 return map
[pipe_func
];
245 translate_cull_mode(unsigned pipe_face
)
247 static const unsigned map
[4] = {
248 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
249 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
250 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
251 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
253 return map
[pipe_face
];
257 translate_fill_mode(unsigned pipe_polymode
)
259 static const unsigned map
[4] = {
260 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
261 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
262 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
263 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
265 return map
[pipe_polymode
];
268 static struct iris_address
269 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
272 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
276 stream_state(struct iris_batch
*batch
,
277 struct u_upload_mgr
*uploader
,
280 uint32_t *out_offset
)
282 struct pipe_resource
*res
= NULL
;
285 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
287 struct iris_bo
*bo
= iris_resource_bo(res
);
288 iris_use_pinned_bo(batch
, bo
, false);
290 *out_offset
+= iris_bo_offset_from_base_address(bo
);
292 pipe_resource_reference(&res
, NULL
);
298 emit_state(struct iris_batch
*batch
,
299 struct u_upload_mgr
*uploader
,
305 uint32_t *map
= stream_state(batch
, uploader
, size
, alignment
, &offset
);
308 memcpy(map
, data
, size
);
314 iris_init_render_context(struct iris_screen
*screen
,
315 struct iris_batch
*batch
,
316 struct iris_vtable
*vtbl
,
317 struct pipe_debug_callback
*dbg
)
319 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
321 /* XXX: PIPE_CONTROLs */
323 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
325 // XXX: MOCS is stupid for this.
326 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
327 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
328 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
329 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
330 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
331 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
332 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
335 sba
.GeneralStateBaseAddressModifyEnable
= true;
336 sba
.SurfaceStateBaseAddressModifyEnable
= true;
337 sba
.DynamicStateBaseAddressModifyEnable
= true;
338 sba
.IndirectObjectBaseAddressModifyEnable
= true;
339 sba
.InstructionBaseAddressModifyEnable
= true;
340 sba
.GeneralStateBufferSizeModifyEnable
= true;
341 sba
.DynamicStateBufferSizeModifyEnable
= true;
342 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
343 sba
.IndirectObjectBufferSizeModifyEnable
= true;
344 sba
.InstructionBuffersizeModifyEnable
= true;
346 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
347 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
348 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
350 sba
.GeneralStateBufferSize
= 0xfffff;
351 sba
.IndirectObjectBufferSize
= 0xfffff;
352 sba
.InstructionBufferSize
= 0xfffff;
353 sba
.DynamicStateBufferSize
= 0xfffff;
356 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
357 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
358 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
360 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
361 GEN_SAMPLE_POS_1X(pat
._1xSample
);
362 GEN_SAMPLE_POS_2X(pat
._2xSample
);
363 GEN_SAMPLE_POS_4X(pat
._4xSample
);
364 GEN_SAMPLE_POS_8X(pat
._8xSample
);
365 GEN_SAMPLE_POS_16X(pat
._16xSample
);
367 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
368 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
369 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
370 /* XXX: may need to set an offset for origin-UL framebuffers */
371 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
373 /* Just assign a static partitioning. */
374 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
375 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
376 alloc
._3DCommandSubOpcode
= 18 + i
;
377 alloc
.ConstantBufferOffset
= 6 * i
;
378 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
384 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
389 iris_set_blend_color(struct pipe_context
*ctx
,
390 const struct pipe_blend_color
*state
)
392 struct iris_context
*ice
= (struct iris_context
*) ctx
;
394 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
395 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
398 struct iris_blend_state
{
399 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
400 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
401 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
403 bool alpha_to_coverage
; /* for shader key */
407 iris_create_blend_state(struct pipe_context
*ctx
,
408 const struct pipe_blend_state
*state
)
410 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
411 uint32_t *blend_state
= cso
->blend_state
;
413 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
415 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
416 /* pb.HasWriteableRT is filled in at draw time. */
417 /* pb.AlphaTestEnable is filled in at draw time. */
418 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
419 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
421 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
423 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
424 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
425 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
426 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
429 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
430 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
431 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
432 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
433 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
434 bs
.ColorDitherEnable
= state
->dither
;
435 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
438 blend_state
+= GENX(BLEND_STATE_length
);
440 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
441 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
442 be
.LogicOpEnable
= state
->logicop_enable
;
443 be
.LogicOpFunction
= state
->logicop_func
;
445 be
.PreBlendSourceOnlyClampEnable
= false;
446 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
447 be
.PreBlendColorClampEnable
= true;
448 be
.PostBlendColorClampEnable
= true;
450 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
452 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
453 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
454 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
455 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
456 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
457 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
459 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
460 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
461 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
462 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
464 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
471 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
473 struct iris_context
*ice
= (struct iris_context
*) ctx
;
474 ice
->state
.cso_blend
= state
;
475 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
476 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
479 struct iris_depth_stencil_alpha_state
{
480 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
481 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
483 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
487 iris_create_zsa_state(struct pipe_context
*ctx
,
488 const struct pipe_depth_stencil_alpha_state
*state
)
490 struct iris_depth_stencil_alpha_state
*cso
=
491 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
493 cso
->alpha
= state
->alpha
;
495 bool two_sided_stencil
= state
->stencil
[1].enabled
;
497 /* The state tracker needs to optimize away EQUAL writes for us. */
498 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
500 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
501 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
502 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
503 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
504 wmds
.StencilTestFunction
=
505 translate_compare_func(state
->stencil
[0].func
);
506 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
507 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
508 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
509 wmds
.BackfaceStencilTestFunction
=
510 translate_compare_func(state
->stencil
[1].func
);
511 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
512 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
513 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
514 wmds
.StencilBufferWriteEnable
=
515 state
->stencil
[0].writemask
!= 0 ||
516 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
517 wmds
.DepthTestEnable
= state
->depth
.enabled
;
518 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
519 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
520 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
521 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
522 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
523 /* wmds.[Backface]StencilReferenceValue are merged later */
526 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
527 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
528 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
535 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
537 struct iris_context
*ice
= (struct iris_context
*) ctx
;
538 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
539 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
542 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
543 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
547 ice
->state
.cso_zsa
= new_cso
;
548 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
549 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
552 struct iris_rasterizer_state
{
553 uint32_t sf
[GENX(3DSTATE_SF_length
)];
554 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
555 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
556 uint32_t wm
[GENX(3DSTATE_WM_length
)];
557 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
559 bool flatshade
; /* for shader state */
560 bool clamp_fragment_color
; /* for shader state */
561 bool light_twoside
; /* for shader state */
562 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
563 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
564 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
565 uint16_t sprite_coord_enable
;
569 iris_create_rasterizer_state(struct pipe_context
*ctx
,
570 const struct pipe_rasterizer_state
*state
)
572 struct iris_rasterizer_state
*cso
=
573 malloc(sizeof(struct iris_rasterizer_state
));
576 point_quad_rasterization
-> SBE
?
581 force_persample_interp
- ?
584 offset_units_unscaled
- cap
not exposed
588 cso
->flatshade
= state
->flatshade
;
589 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
590 cso
->light_twoside
= state
->light_twoside
;
591 cso
->rasterizer_discard
= state
->rasterizer_discard
;
592 cso
->half_pixel_center
= state
->half_pixel_center
;
593 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
594 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
596 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
597 sf
.StatisticsEnable
= true;
598 sf
.ViewportTransformEnable
= true;
599 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
600 sf
.LineEndCapAntialiasingRegionWidth
=
601 state
->line_smooth
? _10pixels
: _05pixels
;
602 sf
.LastPixelEnable
= state
->line_last_pixel
;
603 sf
.LineWidth
= state
->line_width
;
604 sf
.SmoothPointEnable
= state
->point_smooth
;
605 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
606 sf
.PointWidth
= state
->point_size
;
608 if (state
->flatshade_first
) {
609 sf
.TriangleStripListProvokingVertexSelect
= 2;
610 sf
.TriangleFanProvokingVertexSelect
= 2;
611 sf
.LineStripListProvokingVertexSelect
= 1;
613 sf
.TriangleFanProvokingVertexSelect
= 1;
618 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
619 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
620 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
621 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
622 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
623 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
624 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
625 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
626 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
627 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
628 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
629 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
630 rr
.SmoothPointEnable
= state
->point_smooth
;
631 rr
.AntialiasingEnable
= state
->line_smooth
;
632 rr
.ScissorRectangleEnable
= state
->scissor
;
633 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
634 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
635 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
638 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
639 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
640 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
642 cl
.StatisticsEnable
= true;
643 cl
.EarlyCullEnable
= true;
644 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
645 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
646 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
647 cl
.GuardbandClipTestEnable
= true;
648 cl
.ClipMode
= CLIPMODE_NORMAL
;
649 cl
.ClipEnable
= true;
650 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
651 cl
.MinimumPointWidth
= 0.125;
652 cl
.MaximumPointWidth
= 255.875;
654 if (state
->flatshade_first
) {
655 cl
.TriangleStripListProvokingVertexSelect
= 2;
656 cl
.TriangleFanProvokingVertexSelect
= 2;
657 cl
.LineStripListProvokingVertexSelect
= 1;
659 cl
.TriangleFanProvokingVertexSelect
= 1;
663 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
664 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
665 * filled in at draw time from the FS program.
667 wm
.LineAntialiasingRegionWidth
= _10pixels
;
668 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
669 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
670 wm
.StatisticsEnable
= true;
671 wm
.LineStippleEnable
= state
->line_stipple_enable
;
672 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
675 /* Remap from 0..255 back to 1..256 */
676 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
678 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
679 line
.LineStipplePattern
= state
->line_stipple_pattern
;
680 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
681 line
.LineStippleRepeatCount
= line_stipple_factor
;
688 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
690 struct iris_context
*ice
= (struct iris_context
*) ctx
;
691 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
692 struct iris_rasterizer_state
*new_cso
= state
;
695 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
696 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
697 sizeof(old_cso
->line_stipple
)) != 0) {
698 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
702 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
703 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
707 ice
->state
.cso_rast
= new_cso
;
708 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
712 translate_wrap(unsigned pipe_wrap
)
714 static const unsigned map
[] = {
715 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
716 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
717 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
718 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
719 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
720 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
721 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
722 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
724 return map
[pipe_wrap
];
728 * Return true if the given wrap mode requires the border color to exist.
731 wrap_mode_needs_border_color(unsigned wrap_mode
)
733 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
737 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
739 static const unsigned map
[] = {
740 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
741 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
742 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
744 return map
[pipe_mip
];
747 struct iris_sampler_state
{
748 struct pipe_sampler_state base
;
750 bool needs_border_color
;
752 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
756 iris_create_sampler_state(struct pipe_context
*pctx
,
757 const struct pipe_sampler_state
*state
)
759 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
764 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
765 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
767 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
768 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
769 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
771 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
772 wrap_mode_needs_border_color(wrap_t
) ||
773 wrap_mode_needs_border_color(wrap_r
);
775 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
776 samp
.TCXAddressControlMode
= wrap_s
;
777 samp
.TCYAddressControlMode
= wrap_t
;
778 samp
.TCZAddressControlMode
= wrap_r
;
779 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
780 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
781 samp
.MinModeFilter
= state
->min_img_filter
;
782 samp
.MagModeFilter
= state
->mag_img_filter
;
783 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
784 samp
.MaximumAnisotropy
= RATIO21
;
786 if (state
->max_anisotropy
>= 2) {
787 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
788 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
789 samp
.AnisotropicAlgorithm
= EWAApproximation
;
792 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
793 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
795 samp
.MaximumAnisotropy
=
796 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
799 /* Set address rounding bits if not using nearest filtering. */
800 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
801 samp
.UAddressMinFilterRoundingEnable
= true;
802 samp
.VAddressMinFilterRoundingEnable
= true;
803 samp
.RAddressMinFilterRoundingEnable
= true;
806 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
807 samp
.UAddressMagFilterRoundingEnable
= true;
808 samp
.VAddressMagFilterRoundingEnable
= true;
809 samp
.RAddressMagFilterRoundingEnable
= true;
812 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
813 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
815 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
817 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
818 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
819 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
820 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
822 //samp.BorderColorPointer = <<comes from elsewhere>>
829 iris_bind_sampler_states(struct pipe_context
*ctx
,
830 enum pipe_shader_type p_stage
,
831 unsigned start
, unsigned count
,
834 struct iris_context
*ice
= (struct iris_context
*) ctx
;
835 gl_shader_stage stage
= stage_from_pipe(p_stage
);
837 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
839 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
840 * relative to Dynamic State Base Address.
843 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
844 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
845 &ice
->state
.sampler_table_offset
[stage
],
846 &ice
->state
.sampler_table_resource
[stage
],
851 struct pipe_resource
*res
= ice
->state
.sampler_table_resource
[stage
];
852 ice
->state
.sampler_table_offset
[stage
] +=
853 iris_bo_offset_from_base_address(iris_resource_bo(res
));
855 for (int i
= 0; i
< count
; i
++) {
856 struct iris_sampler_state
*state
= states
[i
];
858 /* Save a pointer to the iris_sampler_state, a few fields need
859 * to inform draw-time decisions.
861 ice
->state
.samplers
[stage
][start
+ i
] = state
;
864 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
866 map
+= GENX(SAMPLER_STATE_length
);
869 ice
->state
.num_samplers
[stage
] = count
;
871 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
874 struct iris_sampler_view
{
875 struct pipe_sampler_view pipe
;
876 struct isl_view view
;
878 /** The resource (BO) holding our SURFACE_STATE. */
879 struct pipe_resource
*surface_state_resource
;
880 unsigned surface_state_offset
;
882 //uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
886 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
887 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
889 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
892 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
894 * which is simply adding 4 then modding by 8 (or anding with 7).
896 * We then may need to apply workarounds for textureGather hardware bugs.
898 static enum isl_channel_select
899 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
901 return (swizzle
+ 4) & 7;
904 static struct pipe_sampler_view
*
905 iris_create_sampler_view(struct pipe_context
*ctx
,
906 struct pipe_resource
*tex
,
907 const struct pipe_sampler_view
*tmpl
)
909 struct iris_context
*ice
= (struct iris_context
*) ctx
;
910 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
911 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
912 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
917 /* initialize base object */
919 isv
->pipe
.context
= ctx
;
920 isv
->pipe
.texture
= NULL
;
921 pipe_reference_init(&isv
->pipe
.reference
, 1);
922 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
924 /* XXX: do we need brw_get_texture_swizzle hacks here? */
926 isv
->view
= (struct isl_view
) {
927 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
928 .base_level
= tmpl
->u
.tex
.first_level
,
929 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
930 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
931 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
932 .swizzle
= (struct isl_swizzle
) {
933 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
934 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
935 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
936 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
938 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
942 u_upload_alloc(ice
->state
.surface_uploader
, 0,
943 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
944 &isv
->surface_state_offset
,
945 &isv
->surface_state_resource
,
950 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state_resource
);
951 isv
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
953 isl_surf_fill_state(&screen
->isl_dev
, map
,
954 .surf
= &itex
->surf
, .view
= &isv
->view
,
956 .address
= itex
->bo
->gtt_offset
);
958 // .clear_color = clear_color,
963 struct iris_surface
{
964 struct pipe_surface pipe
;
965 struct isl_view view
;
967 /** The resource (BO) holding our SURFACE_STATE. */
968 struct pipe_resource
*surface_state_resource
;
969 unsigned surface_state_offset
;
971 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
974 static struct pipe_surface
*
975 iris_create_surface(struct pipe_context
*ctx
,
976 struct pipe_resource
*tex
,
977 const struct pipe_surface
*tmpl
)
979 struct iris_context
*ice
= (struct iris_context
*) ctx
;
980 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
981 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
982 struct pipe_surface
*psurf
= &surf
->pipe
;
983 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
988 pipe_reference_init(&psurf
->reference
, 1);
989 pipe_resource_reference(&psurf
->texture
, tex
);
990 psurf
->context
= ctx
;
991 psurf
->format
= tmpl
->format
;
992 psurf
->width
= tex
->width0
;
993 psurf
->height
= tex
->height0
;
994 psurf
->texture
= tex
;
995 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
996 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
997 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
999 surf
->view
= (struct isl_view
) {
1000 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1001 .base_level
= tmpl
->u
.tex
.level
,
1003 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1004 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1005 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1006 // XXX: DEPTH_BIt, STENCIL_BIT...CUBE_BIT? Other bits?!
1007 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1011 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1012 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1013 &surf
->surface_state_offset
,
1014 &surf
->surface_state_resource
,
1019 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state_resource
);
1020 surf
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
1022 isl_surf_fill_state(&screen
->isl_dev
, map
,
1023 .surf
= &itex
->surf
, .view
= &surf
->view
,
1025 .address
= itex
->bo
->gtt_offset
);
1027 // .clear_color = clear_color,
1033 iris_set_sampler_views(struct pipe_context
*ctx
,
1034 enum pipe_shader_type p_stage
,
1035 unsigned start
, unsigned count
,
1036 struct pipe_sampler_view
**views
)
1038 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1039 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1042 for (i
= 0; i
< count
; i
++) {
1043 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1044 &ice
->state
.textures
[stage
][i
], views
[i
]);
1046 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1047 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1048 &ice
->state
.textures
[stage
][i
], NULL
);
1051 ice
->state
.num_textures
[stage
] = count
;
1053 // XXX: ice->state.dirty |= (IRIS_DIRTY_BINDING_TABLE_VS << stage);
1057 iris_set_clip_state(struct pipe_context
*ctx
,
1058 const struct pipe_clip_state
*state
)
1063 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1064 const struct pipe_poly_stipple
*state
)
1066 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1067 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1068 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1072 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1074 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1076 ice
->state
.sample_mask
= sample_mask
;
1077 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1081 iris_set_scissor_states(struct pipe_context
*ctx
,
1082 unsigned start_slot
,
1083 unsigned num_scissors
,
1084 const struct pipe_scissor_state
*states
)
1086 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1088 ice
->state
.num_scissors
= num_scissors
;
1090 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1091 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1094 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1098 iris_set_stencil_ref(struct pipe_context
*ctx
,
1099 const struct pipe_stencil_ref
*state
)
1101 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1102 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1103 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1107 struct iris_viewport_state
{
1108 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1112 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1114 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1119 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1120 float m00
, float m11
, float m30
, float m31
,
1121 float *xmin
, float *xmax
,
1122 float *ymin
, float *ymax
)
1124 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1125 * Strips and Fans documentation:
1127 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1128 * fixed-point "guardband" range supported by the rasterization hardware"
1132 * "In almost all circumstances, if an object’s vertices are actually
1133 * modified by this clamping (i.e., had X or Y coordinates outside of
1134 * the guardband extent the rendered object will not match the intended
1135 * result. Therefore software should take steps to ensure that this does
1136 * not happen - e.g., by clipping objects such that they do not exceed
1137 * these limits after the Drawing Rectangle is applied."
1139 * I believe the fundamental restriction is that the rasterizer (in
1140 * the SF/WM stages) have a limit on the number of pixels that can be
1141 * rasterized. We need to ensure any coordinates beyond the rasterizer
1142 * limit are handled by the clipper. So effectively that limit becomes
1143 * the clipper's guardband size.
1145 * It goes on to say:
1147 * "In addition, in order to be correctly rendered, objects must have a
1148 * screenspace bounding box not exceeding 8K in the X or Y direction.
1149 * This additional restriction must also be comprehended by software,
1150 * i.e., enforced by use of clipping."
1152 * This makes no sense. Gen7+ hardware supports 16K render targets,
1153 * and you definitely need to be able to draw polygons that fill the
1154 * surface. Our assumption is that the rasterizer was limited to 8K
1155 * on Sandybridge, which only supports 8K surfaces, and it was actually
1156 * increased to 16K on Ivybridge and later.
1158 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1160 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1162 if (m00
!= 0 && m11
!= 0) {
1163 /* First, we compute the screen-space render area */
1164 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1165 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1166 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1167 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1169 /* We want the guardband to be centered on that */
1170 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1171 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1172 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1173 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1175 /* Now we need it in native device coordinates */
1176 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1177 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1178 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1179 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1181 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1182 * flipped upside-down. X should be fine though.
1184 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1185 *xmin
= ndc_gb_xmin
;
1186 *xmax
= ndc_gb_xmax
;
1187 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1188 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1190 /* The viewport scales to 0, so nothing will be rendered. */
1200 iris_set_viewport_states(struct pipe_context
*ctx
,
1201 unsigned start_slot
,
1202 unsigned num_viewports
,
1203 const struct pipe_viewport_state
*state
)
1205 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1206 struct iris_viewport_state
*cso
=
1207 malloc(sizeof(struct iris_viewport_state
));
1208 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1210 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1211 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1212 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1213 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1214 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1215 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1216 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1217 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1218 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1219 /* XXX: in i965 this is computed based on the drawbuffer size,
1220 * but we don't have that here...
1222 vp
.XMinClipGuardband
= -1.0;
1223 vp
.XMaxClipGuardband
= 1.0;
1224 vp
.YMinClipGuardband
= -1.0;
1225 vp
.YMaxClipGuardband
= 1.0;
1226 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1227 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1228 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1229 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1232 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1235 ice
->state
.cso_vp
= cso
;
1236 ice
->state
.num_viewports
= num_viewports
;
1237 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1240 struct iris_depth_state
1242 uint32_t depth_buffer
[GENX(3DSTATE_DEPTH_BUFFER_length
)];
1243 uint32_t hier_depth_buffer
[GENX(3DSTATE_HIER_DEPTH_BUFFER_length
)];
1244 uint32_t stencil_buffer
[GENX(3DSTATE_STENCIL_BUFFER_length
)];
1248 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1249 const struct pipe_framebuffer_state
*state
)
1251 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1252 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1254 if (cso
->samples
!= state
->samples
) {
1255 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1258 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1259 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1262 cso
->width
= state
->width
;
1263 cso
->height
= state
->height
;
1264 cso
->layers
= state
->layers
;
1265 cso
->samples
= state
->samples
;
1268 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1269 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1270 for (; i
< cso
->nr_cbufs
; i
++)
1271 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1273 cso
->nr_cbufs
= state
->nr_cbufs
;
1275 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1277 //struct isl_depth_stencil_hiz_emit_info info = {
1281 // XXX: depth buffers
1285 iris_set_constant_buffer(struct pipe_context
*ctx
,
1286 enum pipe_shader_type p_stage
, unsigned index
,
1287 const struct pipe_constant_buffer
*cb
)
1289 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1290 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1292 util_copy_constant_buffer(&ice
->shaders
.state
[stage
].constbuf
[index
], cb
);
1296 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1297 struct pipe_sampler_view
*state
)
1299 struct iris_sampler_view
*isv
= (void *) state
;
1300 pipe_resource_reference(&state
->texture
, NULL
);
1301 pipe_resource_reference(&isv
->surface_state_resource
, NULL
);
1307 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1309 struct iris_surface
*surf
= (void *) p_surf
;
1310 pipe_resource_reference(&p_surf
->texture
, NULL
);
1311 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1316 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1321 struct iris_vertex_buffer_state
{
1322 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1323 struct iris_bo
*bos
[33];
1324 unsigned num_buffers
;
1328 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1331 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1332 iris_bo_unreference(cso
->bos
[i
]);
1338 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1339 unsigned start_slot
, unsigned count
,
1340 const struct pipe_vertex_buffer
*buffers
)
1342 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1343 struct iris_vertex_buffer_state
*cso
=
1344 malloc(sizeof(struct iris_vertex_buffer_state
));
1346 /* If there are no buffers, do nothing. We can leave the stale
1347 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1348 * elements that point to them, it should be fine.
1353 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1355 cso
->num_buffers
= count
;
1357 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1358 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1361 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1363 for (unsigned i
= 0; i
< count
; i
++) {
1364 assert(!buffers
[i
].is_user_buffer
);
1366 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1367 iris_bo_reference(res
->bo
);
1368 cso
->bos
[i
] = res
->bo
;
1370 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1371 vb
.VertexBufferIndex
= start_slot
+ i
;
1373 vb
.AddressModifyEnable
= true;
1374 vb
.BufferPitch
= buffers
[i
].stride
;
1375 vb
.BufferSize
= res
->bo
->size
;
1376 vb
.BufferStartingAddress
=
1377 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1380 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1383 ice
->state
.cso_vertex_buffers
= cso
;
1384 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1387 struct iris_vertex_element_state
{
1388 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1389 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1394 iris_create_vertex_elements(struct pipe_context
*ctx
,
1396 const struct pipe_vertex_element
*state
)
1398 struct iris_vertex_element_state
*cso
=
1399 malloc(sizeof(struct iris_vertex_element_state
));
1404 * - create edge flag one
1406 * - if those are necessary, use count + 1/2/3... OR in the length
1408 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
);
1410 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1412 for (int i
= 0; i
< count
; i
++) {
1413 enum isl_format isl_format
=
1414 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1415 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1416 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1418 switch (isl_format_get_num_channels(isl_format
)) {
1419 case 0: comp
[0] = VFCOMP_STORE_0
;
1420 case 1: comp
[1] = VFCOMP_STORE_0
;
1421 case 2: comp
[2] = VFCOMP_STORE_0
;
1423 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1424 : VFCOMP_STORE_1_FP
;
1427 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1428 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1430 ve
.SourceElementOffset
= state
[i
].src_offset
;
1431 ve
.SourceElementFormat
= isl_format
;
1432 ve
.Component0Control
= comp
[0];
1433 ve
.Component1Control
= comp
[1];
1434 ve
.Component2Control
= comp
[2];
1435 ve
.Component3Control
= comp
[3];
1438 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->vf_instancing
[i
], vi
) {
1439 vi
.VertexElementIndex
= i
;
1440 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1441 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1444 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1451 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1453 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1455 ice
->state
.cso_vertex_elements
= state
;
1456 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1460 iris_create_compute_state(struct pipe_context
*ctx
,
1461 const struct pipe_compute_state
*state
)
1466 static struct pipe_stream_output_target
*
1467 iris_create_stream_output_target(struct pipe_context
*ctx
,
1468 struct pipe_resource
*res
,
1469 unsigned buffer_offset
,
1470 unsigned buffer_size
)
1472 struct pipe_stream_output_target
*t
=
1473 CALLOC_STRUCT(pipe_stream_output_target
);
1477 pipe_reference_init(&t
->reference
, 1);
1478 pipe_resource_reference(&t
->buffer
, res
);
1479 t
->buffer_offset
= buffer_offset
;
1480 t
->buffer_size
= buffer_size
;
1485 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1486 struct pipe_stream_output_target
*t
)
1488 pipe_resource_reference(&t
->buffer
, NULL
);
1493 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1494 unsigned num_targets
,
1495 struct pipe_stream_output_target
**targets
,
1496 const unsigned *offsets
)
1501 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1502 const struct brw_vue_map
*last_vue_map
,
1503 bool two_sided_color
,
1504 unsigned *out_offset
,
1505 unsigned *out_length
)
1507 /* The compiler computes the first URB slot without considering COL/BFC
1508 * swizzling (because it doesn't know whether it's enabled), so we need
1509 * to do that here too. This may result in a smaller offset, which
1512 const unsigned first_slot
=
1513 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1515 /* This becomes the URB read offset (counted in pairs of slots). */
1516 assert(first_slot
% 2 == 0);
1517 *out_offset
= first_slot
/ 2;
1519 /* We need to adjust the inputs read to account for front/back color
1520 * swizzling, as it can make the URB length longer.
1522 for (int c
= 0; c
<= 1; c
++) {
1523 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1524 /* If two sided color is enabled, the fragment shader's gl_Color
1525 * (COL0) input comes from either the gl_FrontColor (COL0) or
1526 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1528 if (two_sided_color
)
1529 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1531 /* If front color isn't written, we opt to give them back color
1532 * instead of an undefined value. Switch from COL to BFC.
1534 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1535 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1536 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1541 /* Compute the minimum URB Read Length necessary for the FS inputs.
1543 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1544 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1546 * "This field should be set to the minimum length required to read the
1547 * maximum source attribute. The maximum source attribute is indicated
1548 * by the maximum value of the enabled Attribute # Source Attribute if
1549 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1550 * enable is not set.
1551 * read_length = ceiling((max_source_attr + 1) / 2)
1553 * [errata] Corruption/Hang possible if length programmed larger than
1556 * Similar text exists for Ivy Bridge.
1558 * We find the last URB slot that's actually read by the FS.
1560 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1561 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1562 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1565 /* The URB read length is the difference of the two, counted in pairs. */
1566 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1570 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1572 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1573 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1574 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1575 struct pipe_shader_state
*p_fs
=
1576 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1577 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1578 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1580 unsigned urb_read_offset
, urb_read_length
;
1581 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1582 ice
->shaders
.last_vue_map
,
1583 cso_rast
->light_twoside
,
1584 &urb_read_offset
, &urb_read_length
);
1586 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1587 sbe
.AttributeSwizzleEnable
= true;
1588 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1589 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1590 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1591 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1592 sbe
.ForceVertexURBEntryReadOffset
= true;
1593 sbe
.ForceVertexURBEntryReadLength
= true;
1594 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1596 for (int i
= 0; i
< 32; i
++) {
1597 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1603 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1608 iris_populate_sampler_key(const struct iris_context
*ice
,
1609 struct brw_sampler_prog_key_data
*key
)
1611 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1612 key
->swizzles
[i
] = 0x688; /* XYZW */
1617 iris_populate_vs_key(const struct iris_context
*ice
,
1618 struct brw_vs_prog_key
*key
)
1620 memset(key
, 0, sizeof(*key
));
1621 iris_populate_sampler_key(ice
, &key
->tex
);
1625 iris_populate_tcs_key(const struct iris_context
*ice
,
1626 struct brw_tcs_prog_key
*key
)
1628 memset(key
, 0, sizeof(*key
));
1629 iris_populate_sampler_key(ice
, &key
->tex
);
1633 iris_populate_tes_key(const struct iris_context
*ice
,
1634 struct brw_tes_prog_key
*key
)
1636 memset(key
, 0, sizeof(*key
));
1637 iris_populate_sampler_key(ice
, &key
->tex
);
1641 iris_populate_gs_key(const struct iris_context
*ice
,
1642 struct brw_gs_prog_key
*key
)
1644 memset(key
, 0, sizeof(*key
));
1645 iris_populate_sampler_key(ice
, &key
->tex
);
1649 iris_populate_fs_key(const struct iris_context
*ice
,
1650 struct brw_wm_prog_key
*key
)
1652 memset(key
, 0, sizeof(*key
));
1653 iris_populate_sampler_key(ice
, &key
->tex
);
1655 /* XXX: dirty flags? */
1656 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1657 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1658 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1659 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1661 key
->nr_color_regions
= fb
->nr_cbufs
;
1663 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1665 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1666 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1668 // key->force_dual_color_blend for unigine
1670 if (cso_rast
->multisample
) {
1671 key
->persample_interp
=
1672 ctx
->Multisample
.SampleShading
&&
1673 (ctx
->Multisample
.MinSampleShadingValue
*
1674 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1676 key
->multisample_fbo
= fb
->samples
> 1;
1680 key
->coherent_fb_fetch
= true;
1683 //pkt.SamplerCount = \
1684 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1685 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1686 //ffs(stage_state->per_thread_scratch) - 11; \
1689 KSP(const struct iris_compiled_shader
*shader
)
1691 struct iris_resource
*res
= (void *) shader
->buffer
;
1692 return res
->bo
->gtt_offset
+ shader
->offset
;
1695 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1696 pkt.KernelStartPointer = KSP(shader); \
1697 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1698 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1700 pkt.DispatchGRFStartRegisterForURBData = \
1701 prog_data->dispatch_grf_start_reg; \
1702 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1703 pkt.prefix##URBEntryReadOffset = 0; \
1705 pkt.StatisticsEnable = true; \
1709 iris_set_vs_state(const struct gen_device_info
*devinfo
,
1710 struct iris_compiled_shader
*shader
)
1712 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1713 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1715 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1716 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1717 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1718 vs
.SIMD8DispatchEnable
= true;
1719 vs
.UserClipDistanceCullTestEnableBitmask
=
1720 vue_prog_data
->cull_distance_mask
;
1725 iris_set_tcs_state(const struct gen_device_info
*devinfo
,
1726 struct iris_compiled_shader
*shader
)
1728 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1729 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1730 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1732 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1733 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1735 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1736 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1737 hs
.IncludeVertexHandles
= true;
1742 iris_set_tes_state(const struct gen_device_info
*devinfo
,
1743 struct iris_compiled_shader
*shader
)
1745 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1746 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1747 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1749 uint32_t *te_state
= (void *) shader
->derived_data
;
1750 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1752 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1753 te
.Partitioning
= tes_prog_data
->partitioning
;
1754 te
.OutputTopology
= tes_prog_data
->output_topology
;
1755 te
.TEDomain
= tes_prog_data
->domain
;
1757 te
.MaximumTessellationFactorOdd
= 63.0;
1758 te
.MaximumTessellationFactorNotOdd
= 64.0;
1761 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1762 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1764 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1765 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1766 ds
.ComputeWCoordinateEnable
=
1767 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1769 ds
.UserClipDistanceCullTestEnableBitmask
=
1770 vue_prog_data
->cull_distance_mask
;
1776 iris_set_gs_state(const struct gen_device_info
*devinfo
,
1777 struct iris_compiled_shader
*shader
)
1779 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1780 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1781 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1783 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1784 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1786 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1787 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1788 gs
.ControlDataHeaderSize
=
1789 gs_prog_data
->control_data_header_size_hwords
;
1790 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1791 gs
.DispatchMode
= SIMD8
;
1792 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1793 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1794 gs
.ReorderMode
= TRAILING
;
1795 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1796 gs
.MaximumNumberofThreads
=
1797 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1798 : (devinfo
->max_gs_threads
- 1);
1800 if (gs_prog_data
->static_vertex_count
!= -1) {
1801 gs
.StaticOutput
= true;
1802 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1804 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1806 gs
.UserClipDistanceCullTestEnableBitmask
=
1807 vue_prog_data
->cull_distance_mask
;
1809 const int urb_entry_write_offset
= 1;
1810 const uint32_t urb_entry_output_length
=
1811 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1812 urb_entry_write_offset
;
1814 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1815 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1820 iris_set_fs_state(const struct gen_device_info
*devinfo
,
1821 struct iris_compiled_shader
*shader
)
1823 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1824 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1826 uint32_t *ps_state
= (void *) shader
->derived_data
;
1827 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1829 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1830 ps
.VectorMaskEnable
= true;
1831 //ps.SamplerCount = ...
1832 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1833 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1834 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1836 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1837 prog_data
->ubo_ranges
[0].length
> 0;
1839 /* From the documentation for this packet:
1840 * "If the PS kernel does not need the Position XY Offsets to
1841 * compute a Position Value, then this field should be programmed
1842 * to POSOFFSET_NONE."
1844 * "SW Recommendation: If the PS kernel needs the Position Offsets
1845 * to compute a Position XY value, this field should match Position
1846 * ZW Interpolation Mode to ensure a consistent position.xyzw
1849 * We only require XY sample offsets. So, this recommendation doesn't
1850 * look useful at the moment. We might need this in future.
1852 ps
.PositionXYOffsetSelect
=
1853 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1854 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1855 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1856 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1858 // XXX: Disable SIMD32 with 16x MSAA
1860 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1861 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1862 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1863 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1864 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1865 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1867 ps
.KernelStartPointer0
=
1868 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1869 ps
.KernelStartPointer1
=
1870 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1871 ps
.KernelStartPointer2
=
1872 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1875 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1876 psx
.PixelShaderValid
= true;
1877 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1878 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1879 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1880 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1881 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1882 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1884 if (wm_prog_data
->uses_sample_mask
) {
1885 /* TODO: conservative rasterization */
1886 if (wm_prog_data
->post_depth_coverage
)
1887 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1889 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
1892 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1893 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1894 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1901 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
1903 assert(cache_id
<= IRIS_CACHE_BLORP
);
1905 static const unsigned dwords
[] = {
1906 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
1907 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
1908 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
1909 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
1911 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
1912 [IRIS_CACHE_CS
] = 0,
1913 [IRIS_CACHE_BLORP
] = 0,
1916 return sizeof(uint32_t) * dwords
[cache_id
];
1920 iris_set_derived_program_state(const struct gen_device_info
*devinfo
,
1921 enum iris_program_cache_id cache_id
,
1922 struct iris_compiled_shader
*shader
)
1926 iris_set_vs_state(devinfo
, shader
);
1928 case IRIS_CACHE_TCS
:
1929 iris_set_tcs_state(devinfo
, shader
);
1931 case IRIS_CACHE_TES
:
1932 iris_set_tes_state(devinfo
, shader
);
1935 iris_set_gs_state(devinfo
, shader
);
1938 iris_set_fs_state(devinfo
, shader
);
1941 case IRIS_CACHE_BLORP
:
1949 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
1951 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
1952 const unsigned push_size_kB
= 32;
1953 unsigned entries
[4];
1957 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1958 if (!ice
->shaders
.prog
[i
]) {
1961 struct brw_vue_prog_data
*vue_prog_data
=
1962 (void *) ice
->shaders
.prog
[i
]->prog_data
;
1963 size
[i
] = vue_prog_data
->urb_entry_size
;
1965 assert(size
[i
] != 0);
1968 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
1969 1024 * ice
->shaders
.urb_size
,
1970 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
1971 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
1972 size
, entries
, start
);
1974 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1975 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
1976 urb
._3DCommandSubOpcode
+= i
;
1977 urb
.VSURBStartingAddress
= start
[i
];
1978 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
1979 urb
.VSNumberofURBEntries
= entries
[i
];
1984 static const uint32_t push_constant_opcodes
[] = {
1985 [MESA_SHADER_VERTEX
] = 21,
1986 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1987 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1988 [MESA_SHADER_GEOMETRY
] = 22,
1989 [MESA_SHADER_FRAGMENT
] = 23,
1990 [MESA_SHADER_COMPUTE
] = 0,
1994 * Add a surface to the validation list, as well as the buffer containing
1995 * the corresponding SURFACE_STATE.
1997 * Returns the binding table entry (offset to SURFACE_STATE).
2000 use_surface(struct iris_batch
*batch
,
2001 struct pipe_surface
*p_surf
,
2004 struct iris_surface
*surf
= (void *) p_surf
;
2005 struct iris_resource
*res
= (void *) p_surf
->texture
;
2006 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
2007 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
2008 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2010 return surf
->surface_state_offset
;
2014 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2016 struct iris_resource
*res
= (void *) isv
->pipe
.texture
;
2017 struct iris_resource
*state_res
= (void *) isv
->surface_state_resource
;
2018 iris_use_pinned_bo(batch
, res
->bo
, false);
2019 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2021 return isv
->surface_state_offset
;
2025 iris_upload_render_state(struct iris_context
*ice
,
2026 struct iris_batch
*batch
,
2027 const struct pipe_draw_info
*draw
)
2029 const uint64_t dirty
= ice
->state
.dirty
;
2031 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2032 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2034 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2035 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2036 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2037 ptr
.CCViewportPointer
=
2038 emit_state(batch
, ice
->state
.dynamic_uploader
,
2039 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2043 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2044 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2045 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2046 ptr
.SFClipViewportPointer
=
2047 emit_state(batch
, ice
->state
.dynamic_uploader
, cso
->sf_cl_vp
,
2048 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2049 ice
->state
.num_viewports
, 64);
2055 if (dirty
& IRIS_DIRTY_URB
) {
2056 iris_upload_urb_config(ice
, batch
);
2059 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2060 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2061 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2062 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2063 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2064 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2065 uint32_t blend_offset
;
2066 uint32_t *blend_map
=
2067 stream_state(batch
, ice
->state
.dynamic_uploader
, 4 * num_dwords
, 64,
2070 uint32_t blend_state_header
;
2071 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2072 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2073 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2076 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2077 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2078 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2080 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2081 ptr
.BlendStatePointer
= blend_offset
;
2082 ptr
.BlendStatePointerValid
= true;
2086 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2087 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2090 stream_state(batch
, ice
->state
.dynamic_uploader
,
2091 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2093 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2094 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2095 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2096 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2097 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2098 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2099 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2101 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2102 ptr
.ColorCalcStatePointer
= cc_offset
;
2103 ptr
.ColorCalcStatePointerValid
= true;
2107 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2108 // XXX: wrong dirty tracking...
2109 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2112 struct pipe_constant_buffer
*cbuf0
=
2113 &ice
->shaders
.state
[stage
].constbuf
[0];
2115 if (!ice
->shaders
.prog
[stage
] || cbuf0
->buffer
|| !cbuf0
->buffer_size
)
2118 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2119 shs
->const_size
= cbuf0
->buffer_size
;
2120 u_upload_data(ice
->ctx
.const_uploader
, 0, shs
->const_size
, 32,
2121 cbuf0
->user_buffer
, &shs
->const_offset
,
2122 &shs
->push_resource
);
2125 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2126 // XXX: wrong dirty tracking...
2127 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2130 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2131 struct iris_resource
*res
= (void *) shs
->push_resource
;
2133 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2134 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2136 pkt
.ConstantBody
.ReadLength
[3] = shs
->const_size
;
2137 pkt
.ConstantBody
.Buffer
[3] = ro_bo(res
->bo
, shs
->const_offset
);
2144 // - ubos/ssbos/abos
2147 // - render targets - write and read
2148 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
2150 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2151 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2152 if (!shader
) // XXX: dirty bits...also, emit a disable maybe?
2155 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2156 uint32_t bt_offset
= 0;
2157 uint32_t *bt_map
= NULL
;
2160 if (prog_data
->binding_table
.size_bytes
!= 0) {
2161 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
2162 bt_map
= iris_binder_reserve(&ice
->state
.binder
,
2163 prog_data
->binding_table
.size_bytes
,
2167 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2168 ptr
._3DCommandSubOpcode
= 38 + stage
;
2169 ptr
.PointertoVSBindingTable
= bt_offset
;
2172 if (stage
== MESA_SHADER_FRAGMENT
) {
2173 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2174 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2175 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2179 assert(prog_data
->binding_table
.texture_start
==
2180 (ice
->state
.num_textures
[stage
] ? s
: 0xd0d0d0d0));
2182 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2183 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2184 bt_map
[s
++] = use_sampler_view(batch
, view
);
2188 // XXX: not implemented yet
2189 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2190 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2191 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2192 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2193 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2194 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2195 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2199 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2200 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2201 !ice
->shaders
.prog
[stage
])
2204 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2205 ptr
._3DCommandSubOpcode
= 43 + stage
;
2206 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2210 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2211 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2213 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2214 if (ice
->state
.framebuffer
.samples
> 0)
2215 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2219 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2220 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2221 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2225 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2226 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2229 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2232 struct iris_resource
*cache
= (void *) shader
->buffer
;
2233 iris_use_pinned_bo(batch
, cache
->bo
, false);
2234 iris_batch_emit(batch
, shader
->derived_data
,
2235 iris_derived_program_state_size(stage
));
2237 if (stage
== MESA_SHADER_TESS_EVAL
) {
2238 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2239 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2240 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2241 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2242 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2248 // 3DSTATE_STREAMOUT
2249 // 3DSTATE_SO_BUFFER
2250 // 3DSTATE_SO_DECL_LIST
2252 if (dirty
& IRIS_DIRTY_CLIP
) {
2253 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2254 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2256 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2257 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2258 if (wm_prog_data
->barycentric_interp_modes
&
2259 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2260 cl
.NonPerspectiveBarycentricEnable
= true;
2262 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2264 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2265 ARRAY_SIZE(cso_rast
->clip
));
2268 if (dirty
& IRIS_DIRTY_RASTER
) {
2269 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2270 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2271 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2275 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_FS
)) {
2276 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2277 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2279 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2280 wm
.BarycentricInterpolationMode
=
2281 wm_prog_data
->barycentric_interp_modes
;
2283 if (wm_prog_data
->early_fragment_tests
)
2284 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2285 else if (wm_prog_data
->has_side_effects
)
2286 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2288 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2292 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2293 // -> iris_raster_state (point sprite texture coordinate origin)
2294 // -> bunch of shader state...
2295 iris_emit_sbe(batch
, ice
);
2296 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2300 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2301 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2302 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2303 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2304 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2305 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2306 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2309 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2310 ARRAY_SIZE(cso_blend
->ps_blend
));
2313 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2314 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2315 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2317 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2318 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2319 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2320 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2322 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2325 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2326 // XXX: allocate at set_scissor time?
2327 uint32_t scissor_offset
= ice
->state
.num_scissors
== 0 ? 0 :
2328 emit_state(batch
, ice
->state
.dynamic_uploader
, ice
->state
.scissors
,
2329 sizeof(struct pipe_scissor_state
) *
2330 ice
->state
.num_scissors
, 32);
2332 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2333 ptr
.ScissorRectPointer
= scissor_offset
;
2337 // XXX: 3DSTATE_DEPTH_BUFFER
2338 // XXX: 3DSTATE_HIER_DEPTH_BUFFER
2339 // XXX: 3DSTATE_STENCIL_BUFFER
2340 // XXX: 3DSTATE_CLEAR_PARAMS
2342 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2343 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2344 for (int i
= 0; i
< 32; i
++) {
2345 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2350 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2351 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2352 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2356 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2357 topo
.PrimitiveTopologyType
=
2358 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2362 if (draw
->index_size
> 0) {
2363 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
2365 assert(!draw
->has_user_indices
);
2367 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2368 ib
.IndexFormat
= draw
->index_size
;
2370 ib
.BufferSize
= res
->bo
->size
;
2371 ib
.BufferStartingAddress
= ro_bo(res
->bo
, 0);
2375 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2376 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2378 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
2379 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
2381 iris_batch_emit(batch
, cso
->vertex_buffers
,
2382 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
2384 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2385 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2389 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2390 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2391 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2392 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2393 for (int i
= 0; i
< cso
->count
; i
++) {
2394 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
2395 (cso
->count
* GENX(3DSTATE_VF_INSTANCING_length
)));
2397 for (int i
= 0; i
< cso
->count
; i
++) {
2398 /* TODO: vertexid, instanceid support */
2399 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2404 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2405 if (draw
->primitive_restart
) {
2406 vf
.IndexedDrawCutIndexEnable
= true;
2407 vf
.CutIndex
= draw
->restart_index
;
2412 // XXX: Gen8 - PMA fix
2414 assert(!draw
->indirect
); // XXX: indirect support
2416 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2417 prim
.StartInstanceLocation
= draw
->start_instance
;
2418 prim
.InstanceCount
= draw
->instance_count
;
2419 prim
.VertexCountPerInstance
= draw
->count
;
2420 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2422 // XXX: this is probably bonkers.
2423 prim
.StartVertexLocation
= draw
->start
;
2425 if (draw
->index_size
) {
2426 prim
.BaseVertexLocation
+= draw
->index_bias
;
2428 prim
.StartVertexLocation
+= draw
->index_bias
;
2431 //prim.BaseVertexLocation = ...;
2436 iris_destroy_state(struct iris_context
*ice
)
2438 // XXX: unreference resources/surfaces.
2439 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2440 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2442 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2446 flags_to_post_sync_op(uint32_t flags
)
2448 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2449 return WriteImmediateData
;
2451 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2452 return WritePSDepthCount
;
2454 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2455 return WriteTimestamp
;
2461 * Do the given flags have a Post Sync or LRI Post Sync operation?
2463 static enum pipe_control_flags
2464 get_post_sync_flags(enum pipe_control_flags flags
)
2466 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2467 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2468 PIPE_CONTROL_WRITE_TIMESTAMP
|
2469 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2471 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2472 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2474 assert(util_bitcount(flags
) <= 1);
2479 // XXX: compute support
2480 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2483 * Emit a series of PIPE_CONTROL commands, taking into account any
2484 * workarounds necessary to actually accomplish the caller's request.
2486 * Unless otherwise noted, spec quotations in this function come from:
2488 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2489 * Restrictions for PIPE_CONTROL.
2492 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2493 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2495 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2496 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2497 enum pipe_control_flags non_lri_post_sync_flags
=
2498 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2500 /* Recursive PIPE_CONTROL workarounds --------------------------------
2501 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2503 * We do these first because we want to look at the original operation,
2504 * rather than any workarounds we set.
2506 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2507 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2508 * lists several workarounds:
2510 * "Project: SKL, KBL, BXT
2512 * If the VF Cache Invalidation Enable is set to a 1 in a
2513 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2514 * sets to 0, with the VF Cache Invalidation Enable set to 0
2515 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2516 * Invalidation Enable set to a 1."
2518 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2521 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2522 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2524 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2525 * programmed prior to programming a PIPECONTROL command with "LRI
2526 * Post Sync Operation" in GPGPU mode of operation (i.e when
2527 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2529 * The same text exists a few rows below for Post Sync Op.
2531 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2534 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2536 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2537 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2538 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2540 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2544 /* "Flush Types" workarounds ---------------------------------------------
2545 * We do these now because they may add post-sync operations or CS stalls.
2548 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2549 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2551 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
2552 * 'Write PS Depth Count' or 'Write Timestamp'."
2555 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2556 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2557 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2558 bo
= batch
->screen
->workaround_bo
;
2562 /* #1130 from Gen10 workarounds page:
2564 * "Enable Depth Stall on every Post Sync Op if Render target Cache
2565 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
2566 * board stall if Render target cache flush is enabled."
2568 * Applicable to CNL B0 and C0 steppings only.
2570 * The wording here is unclear, and this workaround doesn't look anything
2571 * like the internal bug report recommendations, but leave it be for now...
2573 if (GEN_GEN
== 10) {
2574 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
2575 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2576 } else if (flags
& non_lri_post_sync_flags
) {
2577 flags
|= PIPE_CONTROL_DEPTH_STALL
;
2581 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
2582 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
2584 * "This bit must be DISABLED for operations other than writing
2587 * This seems like nonsense. An Ivybridge workaround requires us to
2588 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
2589 * operation. Gen8+ requires us to emit depth stalls and depth cache
2590 * flushes together. So, it's hard to imagine this means anything other
2591 * than "we originally intended this to be used for PS_DEPTH_COUNT".
2593 * We ignore the supposed restriction and do nothing.
2597 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2598 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
2599 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
2601 * "This bit must be DISABLED for End-of-pipe (Read) fences,
2602 * PS_DEPTH_COUNT or TIMESTAMP queries."
2604 * TODO: Implement end-of-pipe checking.
2606 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2607 PIPE_CONTROL_WRITE_TIMESTAMP
)));
2610 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
2611 /* From the PIPE_CONTROL instruction table, bit 1:
2613 * "This bit is ignored if Depth Stall Enable is set.
2614 * Further, the render cache is not flushed even if Write Cache
2615 * Flush Enable bit is set."
2617 * We assert that the caller doesn't do this combination, to try and
2618 * prevent mistakes. It shouldn't hurt the GPU, though.
2620 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
2621 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
2624 /* PIPE_CONTROL page workarounds ------------------------------------- */
2626 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
2627 /* From the PIPE_CONTROL page itself:
2630 * Restriction: Pipe_control with CS-stall bit set must be issued
2631 * before a pipe-control command that has the State Cache
2632 * Invalidate bit set."
2634 flags
|= PIPE_CONTROL_CS_STALL
;
2637 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
2638 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
2641 * SW must always program Post-Sync Operation to "Write Immediate
2642 * Data" when Flush LLC is set."
2644 * For now, we just require the caller to do it.
2646 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
2649 /* "Post-Sync Operation" workarounds -------------------------------- */
2651 /* Project: All / Argument: Global Snapshot Count Reset [19]
2653 * "This bit must not be exercised on any product.
2654 * Requires stall bit ([20] of DW1) set."
2656 * We don't use this, so we just assert that it isn't used. The
2657 * PIPE_CONTROL instruction page indicates that they intended this
2658 * as a debug feature and don't think it is useful in production,
2659 * but it may actually be usable, should we ever want to.
2661 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
2663 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
2664 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
2665 /* Project: All / Arguments:
2667 * - Generic Media State Clear [16]
2668 * - Indirect State Pointers Disable [16]
2670 * "Requires stall bit ([20] of DW1) set."
2672 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
2673 * State Clear) says:
2675 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2676 * programmed prior to programming a PIPECONTROL command with "Media
2677 * State Clear" set in GPGPU mode of operation"
2679 * This is a subset of the earlier rule, so there's nothing to do.
2681 flags
|= PIPE_CONTROL_CS_STALL
;
2684 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
2685 /* Project: All / Argument: Store Data Index
2687 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2690 * For now, we just assert that the caller does this. We might want to
2691 * automatically add a write to the workaround BO...
2693 assert(non_lri_post_sync_flags
!= 0);
2696 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
2697 /* Project: All / Argument: Sync GFDT
2699 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2700 * than '0' or 0x2520[13] must be set."
2702 * For now, we just assert that the caller does this.
2704 assert(non_lri_post_sync_flags
!= 0);
2707 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
2708 /* Project: IVB+ / Argument: TLB inv
2710 * "Requires stall bit ([20] of DW1) set."
2712 * Also, from the PIPE_CONTROL instruction table:
2715 * Post Sync Operation or CS stall must be set to ensure a TLB
2716 * invalidation occurs. Otherwise no cycle will occur to the TLB
2717 * cache to invalidate."
2719 * This is not a subset of the earlier rule, so there's nothing to do.
2721 flags
|= PIPE_CONTROL_CS_STALL
;
2724 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
2725 /* TODO: The big Skylake GT4 post sync op workaround */
2728 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
2730 if (IS_COMPUTE_PIPELINE(batch
)) {
2731 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
2732 /* Project: SKL+ / Argument: Tex Invalidate
2733 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
2735 flags
|= PIPE_CONTROL_CS_STALL
;
2738 if (GEN_GEN
== 8 && (post_sync_flags
||
2739 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
2740 PIPE_CONTROL_DEPTH_STALL
|
2741 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2742 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2743 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
2744 /* Project: BDW / Arguments:
2746 * - LRI Post Sync Operation [23]
2747 * - Post Sync Op [15:14]
2749 * - Depth Stall [13]
2750 * - Render Target Cache Flush [12]
2751 * - Depth Cache Flush [0]
2752 * - DC Flush Enable [5]
2754 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
2757 flags
|= PIPE_CONTROL_CS_STALL
;
2759 /* Also, from the PIPE_CONTROL instruction table, bit 20:
2762 * This bit must be always set when PIPE_CONTROL command is
2763 * programmed by GPGPU and MEDIA workloads, except for the cases
2764 * when only Read Only Cache Invalidation bits are set (State
2765 * Cache Invalidation Enable, Instruction cache Invalidation
2766 * Enable, Texture Cache Invalidation Enable, Constant Cache
2767 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
2768 * need not implemented when FF_DOP_CG is disable via "Fixed
2769 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
2771 * It sounds like we could avoid CS stalls in some cases, but we
2772 * don't currently bother. This list isn't exactly the list above,
2778 /* "Stall" workarounds ----------------------------------------------
2779 * These have to come after the earlier ones because we may have added
2780 * some additional CS stalls above.
2783 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
2784 /* Project: PRE-SKL, VLV, CHV
2786 * "[All Stepping][All SKUs]:
2788 * One of the following must also be set:
2790 * - Render Target Cache Flush Enable ([12] of DW1)
2791 * - Depth Cache Flush Enable ([0] of DW1)
2792 * - Stall at Pixel Scoreboard ([1] of DW1)
2793 * - Depth Stall ([13] of DW1)
2794 * - Post-Sync Operation ([13] of DW1)
2795 * - DC Flush Enable ([5] of DW1)"
2797 * If we don't already have one of those bits set, we choose to add
2798 * "Stall at Pixel Scoreboard". Some of the other bits require a
2799 * CS stall as a workaround (see above), which would send us into
2800 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
2801 * appears to be safe, so we choose that.
2803 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2804 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2805 PIPE_CONTROL_WRITE_IMMEDIATE
|
2806 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2807 PIPE_CONTROL_WRITE_TIMESTAMP
|
2808 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
2809 PIPE_CONTROL_DEPTH_STALL
|
2810 PIPE_CONTROL_DATA_CACHE_FLUSH
;
2811 if (!(flags
& wa_bits
))
2812 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2815 /* Emit --------------------------------------------------------------- */
2817 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
2818 pc
.LRIPostSyncOperation
= NoLRIOperation
;
2819 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
2820 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
2821 pc
.StoreDataIndex
= 0;
2822 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
2823 pc
.GlobalSnapshotCountReset
=
2824 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
2825 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
2826 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
2827 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2828 pc
.RenderTargetCacheFlushEnable
=
2829 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2830 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
2831 pc
.StateCacheInvalidationEnable
=
2832 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
2833 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2834 pc
.ConstantCacheInvalidationEnable
=
2835 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
2836 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
2837 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
2838 pc
.InstructionCacheInvalidateEnable
=
2839 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
2840 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
2841 pc
.IndirectStatePointersDisable
=
2842 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
2843 pc
.TextureCacheInvalidationEnable
=
2844 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2845 pc
.Address
= ro_bo(bo
, offset
);
2846 pc
.ImmediateData
= imm
;
2851 genX(init_state
)(struct iris_context
*ice
)
2853 struct pipe_context
*ctx
= &ice
->ctx
;
2855 ctx
->create_blend_state
= iris_create_blend_state
;
2856 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
2857 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
2858 ctx
->create_sampler_state
= iris_create_sampler_state
;
2859 ctx
->create_sampler_view
= iris_create_sampler_view
;
2860 ctx
->create_surface
= iris_create_surface
;
2861 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
2862 ctx
->create_compute_state
= iris_create_compute_state
;
2863 ctx
->bind_blend_state
= iris_bind_blend_state
;
2864 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
2865 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
2866 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
2867 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
2868 ctx
->bind_compute_state
= iris_bind_compute_state
;
2869 ctx
->delete_blend_state
= iris_delete_state
;
2870 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
2871 ctx
->delete_fs_state
= iris_delete_state
;
2872 ctx
->delete_rasterizer_state
= iris_delete_state
;
2873 ctx
->delete_sampler_state
= iris_delete_state
;
2874 ctx
->delete_vertex_elements_state
= iris_delete_state
;
2875 ctx
->delete_compute_state
= iris_delete_state
;
2876 ctx
->delete_tcs_state
= iris_delete_state
;
2877 ctx
->delete_tes_state
= iris_delete_state
;
2878 ctx
->delete_gs_state
= iris_delete_state
;
2879 ctx
->delete_vs_state
= iris_delete_state
;
2880 ctx
->set_blend_color
= iris_set_blend_color
;
2881 ctx
->set_clip_state
= iris_set_clip_state
;
2882 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
2883 ctx
->set_sampler_views
= iris_set_sampler_views
;
2884 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
2885 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
2886 ctx
->set_sample_mask
= iris_set_sample_mask
;
2887 ctx
->set_scissor_states
= iris_set_scissor_states
;
2888 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
2889 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
2890 ctx
->set_viewport_states
= iris_set_viewport_states
;
2891 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
2892 ctx
->surface_destroy
= iris_surface_destroy
;
2893 ctx
->draw_vbo
= iris_draw_vbo
;
2894 ctx
->launch_grid
= iris_launch_grid
;
2895 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
2896 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
2897 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
2899 ice
->vtbl
.destroy_state
= iris_destroy_state
;
2900 ice
->vtbl
.init_render_context
= iris_init_render_context
;
2901 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
2902 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
2903 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
2904 ice
->vtbl
.set_derived_program_state
= iris_set_derived_program_state
;
2905 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
2906 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
2907 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
2908 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
2909 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
2911 ice
->state
.dirty
= ~0ull;