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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_inlines.h"
92 #include "util/u_format.h"
93 #include "util/u_framebuffer.h"
94 #include "util/u_transfer.h"
95 #include "util/u_upload_mgr.h"
96 #include "util/u_viewport.h"
99 #include "intel/compiler/brw_compiler.h"
100 #include "intel/common/gen_l3_config.h"
101 #include "intel/common/gen_sample_positions.h"
102 #include "iris_batch.h"
103 #include "iris_context.h"
104 #include "iris_pipe.h"
105 #include "iris_resource.h"
107 #define __gen_address_type struct iris_address
108 #define __gen_user_data struct iris_batch
110 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
113 __gen_combine_address(struct iris_batch
*batch
, void *location
,
114 struct iris_address addr
, uint32_t delta
)
116 uint64_t result
= addr
.offset
+ delta
;
119 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
120 /* Assume this is a general address, not relative to a base. */
121 result
+= addr
.bo
->gtt_offset
;
127 #define __genxml_cmd_length(cmd) cmd ## _length
128 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
129 #define __genxml_cmd_header(cmd) cmd ## _header
130 #define __genxml_cmd_pack(cmd) cmd ## _pack
132 #define _iris_pack_command(batch, cmd, dst, name) \
133 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
134 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
135 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
139 #define iris_pack_command(cmd, dst, name) \
140 _iris_pack_command(NULL, cmd, dst, name)
142 #define iris_pack_state(cmd, dst, name) \
143 for (struct cmd name = {}, \
144 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
145 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
148 #define iris_emit_cmd(batch, cmd, name) \
149 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
151 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
153 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
154 for (uint32_t i = 0; i < num_dwords; i++) \
155 dw[i] = (dwords0)[i] | (dwords1)[i]; \
156 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
159 #include "genxml/genX_pack.h"
160 #include "genxml/gen_macros.h"
161 #include "genxml/genX_bits.h"
163 #define MOCS_WB (2 << 1)
166 * Statically assert that PIPE_* enums match the hardware packets.
167 * (As long as they match, we don't need to translate them.)
169 UNUSED
static void pipe_asserts()
171 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
173 /* pipe_logicop happens to match the hardware. */
174 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
175 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
176 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
177 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
178 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
179 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
180 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
181 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
182 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
183 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
184 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
185 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
186 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
187 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
188 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
189 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
191 /* pipe_blend_func happens to match the hardware. */
192 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
193 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
194 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
195 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
196 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
197 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
198 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
199 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
200 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
201 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
202 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
203 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
204 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
205 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
206 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
212 /* pipe_blend_func happens to match the hardware. */
213 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
214 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
215 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
216 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
217 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
219 /* pipe_stencil_op happens to match the hardware. */
220 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
221 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
222 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
223 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
224 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
225 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
226 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
227 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
229 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
230 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
231 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
236 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
238 static const unsigned map
[] = {
239 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
240 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
241 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
242 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
243 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
244 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
245 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
246 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
247 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
248 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
249 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
250 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
251 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
252 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
253 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
256 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
260 translate_compare_func(enum pipe_compare_func pipe_func
)
262 static const unsigned map
[] = {
263 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
264 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
265 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
266 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
267 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
268 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
269 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
270 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
272 return map
[pipe_func
];
276 translate_shadow_func(enum pipe_compare_func pipe_func
)
278 /* Gallium specifies the result of shadow comparisons as:
280 * 1 if ref <op> texel,
285 * 0 if texel <op> ref,
288 * So we need to flip the operator and also negate.
290 static const unsigned map
[] = {
291 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
292 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
293 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
294 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
295 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
296 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
297 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
298 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
300 return map
[pipe_func
];
304 translate_cull_mode(unsigned pipe_face
)
306 static const unsigned map
[4] = {
307 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
308 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
309 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
310 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
312 return map
[pipe_face
];
316 translate_fill_mode(unsigned pipe_polymode
)
318 static const unsigned map
[4] = {
319 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
320 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
321 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
322 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
324 return map
[pipe_polymode
];
328 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
330 static const unsigned map
[] = {
331 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
332 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
333 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
335 return map
[pipe_mip
];
339 translate_wrap(unsigned pipe_wrap
)
341 static const unsigned map
[] = {
342 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
343 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
344 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
345 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
346 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
347 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
349 /* These are unsupported. */
350 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
351 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
353 return map
[pipe_wrap
];
356 static struct iris_address
357 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
359 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
360 * validation list at CSO creation time, instead of draw time.
362 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
365 static struct iris_address
366 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
368 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
369 * validation list at CSO creation time, instead of draw time.
371 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
375 * Allocate space for some indirect state.
377 * Return a pointer to the map (to fill it out) and a state ref (for
378 * referring to the state in GPU commands).
381 upload_state(struct u_upload_mgr
*uploader
,
382 struct iris_state_ref
*ref
,
387 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
392 * Stream out temporary/short-lived state.
394 * This allocates space, pins the BO, and includes the BO address in the
395 * returned offset (which works because all state lives in 32-bit memory
399 stream_state(struct iris_batch
*batch
,
400 struct u_upload_mgr
*uploader
,
401 struct pipe_resource
**out_res
,
404 uint32_t *out_offset
)
408 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
410 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
411 iris_use_pinned_bo(batch
, bo
, false);
413 *out_offset
+= iris_bo_offset_from_base_address(bo
);
419 * stream_state() + memcpy.
422 emit_state(struct iris_batch
*batch
,
423 struct u_upload_mgr
*uploader
,
424 struct pipe_resource
**out_res
,
431 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
434 memcpy(map
, data
, size
);
440 * Did field 'x' change between 'old_cso' and 'new_cso'?
442 * (If so, we may want to set some dirty flags.)
444 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
445 #define cso_changed_memcmp(x) \
446 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
449 flush_for_state_base_change(struct iris_batch
*batch
)
451 /* Flush before emitting STATE_BASE_ADDRESS.
453 * This isn't documented anywhere in the PRM. However, it seems to be
454 * necessary prior to changing the surface state base adress. We've
455 * seen issues in Vulkan where we get GPU hangs when using multi-level
456 * command buffers which clear depth, reset state base address, and then
459 * Normally, in GL, we would trust the kernel to do sufficient stalls
460 * and flushes prior to executing our batch. However, it doesn't seem
461 * as if the kernel's flushing is always sufficient and we don't want to
464 * We make this an end-of-pipe sync instead of a normal flush because we
465 * do not know the current status of the GPU. On Haswell at least,
466 * having a fast-clear operation in flight at the same time as a normal
467 * rendering operation can cause hangs. Since the kernel's flushing is
468 * insufficient, we need to ensure that any rendering operations from
469 * other processes are definitely complete before we try to do our own
470 * rendering. It's a bit of a big hammer but it appears to work.
472 iris_emit_end_of_pipe_sync(batch
,
473 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
474 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
475 PIPE_CONTROL_DATA_CACHE_FLUSH
);
479 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
481 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
482 lri
.RegisterOffset
= reg
;
486 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
489 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t src
, uint32_t dst
)
491 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
492 lrr
.SourceRegisterAddress
= src
;
493 lrr
.DestinationRegisterAddress
= dst
;
498 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
500 #if GEN_GEN >= 8 && GEN_GEN < 10
501 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
503 * Software must clear the COLOR_CALC_STATE Valid field in
504 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
505 * with Pipeline Select set to GPGPU.
507 * The internal hardware docs recommend the same workaround for Gen9
510 if (pipeline
== GPGPU
)
511 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
515 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
516 * PIPELINE_SELECT [DevBWR+]":
520 * Software must ensure all the write caches are flushed through a
521 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
522 * command to invalidate read only caches prior to programming
523 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
525 iris_emit_pipe_control_flush(batch
,
526 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
527 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
528 PIPE_CONTROL_DATA_CACHE_FLUSH
|
529 PIPE_CONTROL_CS_STALL
);
531 iris_emit_pipe_control_flush(batch
,
532 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
533 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
534 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
535 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
537 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
541 sel
.PipelineSelection
= pipeline
;
546 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
551 * "This chicken bit works around a hardware issue with barrier
552 * logic encountered when switching between GPGPU and 3D pipelines.
553 * To workaround the issue, this mode bit should be set after a
554 * pipeline is selected."
557 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
558 reg
.GLKBarrierMode
= value
;
559 reg
.GLKBarrierModeMask
= 1;
561 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
566 init_state_base_address(struct iris_batch
*batch
)
568 flush_for_state_base_change(batch
);
570 /* We program most base addresses once at context initialization time.
571 * Each base address points at a 4GB memory zone, and never needs to
572 * change. See iris_bufmgr.h for a description of the memory zones.
574 * The one exception is Surface State Base Address, which needs to be
575 * updated occasionally. See iris_binder.c for the details there.
577 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
579 // XXX: MOCS is stupid for this.
580 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
581 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
582 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
583 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
584 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
585 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
588 sba
.GeneralStateBaseAddressModifyEnable
= true;
589 sba
.DynamicStateBaseAddressModifyEnable
= true;
590 sba
.IndirectObjectBaseAddressModifyEnable
= true;
591 sba
.InstructionBaseAddressModifyEnable
= true;
592 sba
.GeneralStateBufferSizeModifyEnable
= true;
593 sba
.DynamicStateBufferSizeModifyEnable
= true;
594 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
595 sba
.IndirectObjectBufferSizeModifyEnable
= true;
596 sba
.InstructionBuffersizeModifyEnable
= true;
598 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
599 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
601 sba
.GeneralStateBufferSize
= 0xfffff;
602 sba
.IndirectObjectBufferSize
= 0xfffff;
603 sba
.InstructionBufferSize
= 0xfffff;
604 sba
.DynamicStateBufferSize
= 0xfffff;
609 * Upload the initial GPU state for a render context.
611 * This sets some invariant state that needs to be programmed a particular
612 * way, but we never actually change.
615 iris_init_render_context(struct iris_screen
*screen
,
616 struct iris_batch
*batch
,
617 struct iris_vtable
*vtbl
,
618 struct pipe_debug_callback
*dbg
)
620 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
623 emit_pipeline_select(batch
, _3D
);
625 init_state_base_address(batch
);
627 // XXX: INSTPM on Gen8
628 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
629 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
630 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
632 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
635 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
636 reg
.FloatBlendOptimizationEnable
= true;
637 reg
.FloatBlendOptimizationEnableMask
= true;
638 reg
.PartialResolveDisableInVC
= true;
639 reg
.PartialResolveDisableInVCMask
= true;
641 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
643 if (devinfo
->is_geminilake
)
644 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
648 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
649 reg
.HeaderlessMessageforPreemptableContexts
= 1;
650 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
652 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
657 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
658 * changing it dynamically. We set it to the maximum size here, and
659 * instead include the render target dimensions in the viewport, so
660 * viewport extents clipping takes care of pruning stray geometry.
662 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
663 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
664 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
667 /* Set the initial MSAA sample positions. */
668 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
669 GEN_SAMPLE_POS_1X(pat
._1xSample
);
670 GEN_SAMPLE_POS_2X(pat
._2xSample
);
671 GEN_SAMPLE_POS_4X(pat
._4xSample
);
672 GEN_SAMPLE_POS_8X(pat
._8xSample
);
673 GEN_SAMPLE_POS_16X(pat
._16xSample
);
676 /* Use the legacy AA line coverage computation. */
677 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
679 /* Disable chromakeying (it's for media) */
680 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
682 /* We want regular rendering, not special HiZ operations. */
683 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
685 /* No polygon stippling offsets are necessary. */
686 // XXX: may need to set an offset for origin-UL framebuffers
687 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
689 /* Set a static partitioning of the push constant area. */
690 // XXX: this may be a bad idea...could starve the push ringbuffers...
691 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
692 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
693 alloc
._3DCommandSubOpcode
= 18 + i
;
694 alloc
.ConstantBufferOffset
= 6 * i
;
695 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
701 iris_init_compute_context(struct iris_screen
*screen
,
702 struct iris_batch
*batch
,
703 struct iris_vtable
*vtbl
,
704 struct pipe_debug_callback
*dbg
)
706 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
708 emit_pipeline_select(batch
, GPGPU
);
710 const bool has_slm
= true;
711 const bool wants_dc_cache
= true;
713 const struct gen_l3_weights w
=
714 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
715 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
718 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
719 reg
.SLMEnable
= has_slm
;
721 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
722 * in L3CNTLREG register. The default setting of the bit is not the
723 * desirable behavior.
725 reg
.ErrorDetectionBehaviorControl
= true;
727 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
728 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
729 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
730 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
732 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
734 init_state_base_address(batch
);
737 if (devinfo
->is_geminilake
)
738 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
742 struct iris_vertex_buffer_state
{
743 /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
744 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
746 /** The resource to source vertex data from. */
747 struct pipe_resource
*resources
[33];
749 /** The number of bound vertex buffers. */
750 unsigned num_buffers
;
753 struct iris_depth_buffer_state
{
754 /* Depth/HiZ/Stencil related hardware packets. */
755 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
756 GENX(3DSTATE_STENCIL_BUFFER_length
) +
757 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
758 GENX(3DSTATE_CLEAR_PARAMS_length
)];
762 * Generation-specific context state (ice->state.genx->...).
764 * Most state can go in iris_context directly, but these encode hardware
765 * packets which vary by generation.
767 struct iris_genx_state
{
768 struct iris_vertex_buffer_state vertex_buffers
;
769 struct iris_depth_buffer_state depth_buffer
;
771 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
772 uint32_t streamout
[4 * GENX(3DSTATE_STREAMOUT_length
)];
776 * The pipe->set_blend_color() driver hook.
778 * This corresponds to our COLOR_CALC_STATE.
781 iris_set_blend_color(struct pipe_context
*ctx
,
782 const struct pipe_blend_color
*state
)
784 struct iris_context
*ice
= (struct iris_context
*) ctx
;
786 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
787 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
788 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
792 * Gallium CSO for blend state (see pipe_blend_state).
794 struct iris_blend_state
{
795 /** Partial 3DSTATE_PS_BLEND */
796 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
798 /** Partial BLEND_STATE */
799 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
800 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
802 bool alpha_to_coverage
; /* for shader key */
806 * The pipe->create_blend_state() driver hook.
808 * Translates a pipe_blend_state into iris_blend_state.
811 iris_create_blend_state(struct pipe_context
*ctx
,
812 const struct pipe_blend_state
*state
)
814 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
815 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
817 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
819 bool indep_alpha_blend
= false;
821 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
822 const struct pipe_rt_blend_state
*rt
=
823 &state
->rt
[state
->independent_blend_enable
? i
: 0];
825 if (rt
->rgb_func
!= rt
->alpha_func
||
826 rt
->rgb_src_factor
!= rt
->alpha_src_factor
||
827 rt
->rgb_dst_factor
!= rt
->alpha_dst_factor
)
828 indep_alpha_blend
= true;
830 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
831 be
.LogicOpEnable
= state
->logicop_enable
;
832 be
.LogicOpFunction
= state
->logicop_func
;
834 be
.PreBlendSourceOnlyClampEnable
= false;
835 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
836 be
.PreBlendColorClampEnable
= true;
837 be
.PostBlendColorClampEnable
= true;
839 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
841 be
.ColorBlendFunction
= rt
->rgb_func
;
842 be
.AlphaBlendFunction
= rt
->alpha_func
;
843 be
.SourceBlendFactor
= rt
->rgb_src_factor
;
844 be
.SourceAlphaBlendFactor
= rt
->alpha_src_factor
;
845 be
.DestinationBlendFactor
= rt
->rgb_dst_factor
;
846 be
.DestinationAlphaBlendFactor
= rt
->alpha_dst_factor
;
848 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
849 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
850 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
851 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
853 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
856 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
857 /* pb.HasWriteableRT is filled in at draw time. */
858 /* pb.AlphaTestEnable is filled in at draw time. */
859 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
860 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
862 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
864 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
865 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_src_factor
;
866 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
867 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
870 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
871 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
872 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
873 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
874 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
875 bs
.ColorDitherEnable
= state
->dither
;
876 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
884 * The pipe->bind_blend_state() driver hook.
886 * Bind a blending CSO and flag related dirty bits.
889 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
891 struct iris_context
*ice
= (struct iris_context
*) ctx
;
892 ice
->state
.cso_blend
= state
;
893 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
894 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
895 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
899 * Gallium CSO for depth, stencil, and alpha testing state.
901 struct iris_depth_stencil_alpha_state
{
902 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
903 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
905 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
906 struct pipe_alpha_state alpha
;
908 /** Outbound to resolve and cache set tracking. */
909 bool depth_writes_enabled
;
910 bool stencil_writes_enabled
;
914 * The pipe->create_depth_stencil_alpha_state() driver hook.
916 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
917 * testing state since we need pieces of it in a variety of places.
920 iris_create_zsa_state(struct pipe_context
*ctx
,
921 const struct pipe_depth_stencil_alpha_state
*state
)
923 struct iris_depth_stencil_alpha_state
*cso
=
924 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
926 bool two_sided_stencil
= state
->stencil
[1].enabled
;
928 cso
->alpha
= state
->alpha
;
929 cso
->depth_writes_enabled
= state
->depth
.writemask
;
930 cso
->stencil_writes_enabled
=
931 state
->stencil
[0].writemask
!= 0 ||
932 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 1);
934 /* The state tracker needs to optimize away EQUAL writes for us. */
935 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
937 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
938 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
939 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
940 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
941 wmds
.StencilTestFunction
=
942 translate_compare_func(state
->stencil
[0].func
);
943 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
944 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
945 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
946 wmds
.BackfaceStencilTestFunction
=
947 translate_compare_func(state
->stencil
[1].func
);
948 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
949 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
950 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
951 wmds
.StencilBufferWriteEnable
=
952 state
->stencil
[0].writemask
!= 0 ||
953 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
954 wmds
.DepthTestEnable
= state
->depth
.enabled
;
955 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
956 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
957 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
958 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
959 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
960 /* wmds.[Backface]StencilReferenceValue are merged later */
967 * The pipe->bind_depth_stencil_alpha_state() driver hook.
969 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
972 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
974 struct iris_context
*ice
= (struct iris_context
*) ctx
;
975 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
976 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
979 if (cso_changed(alpha
.ref_value
))
980 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
982 if (cso_changed(alpha
.enabled
))
983 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
985 if (cso_changed(alpha
.func
))
986 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
988 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
989 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
992 ice
->state
.cso_zsa
= new_cso
;
993 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
994 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
995 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
999 * Gallium CSO for rasterizer state.
1001 struct iris_rasterizer_state
{
1002 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1003 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1004 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1005 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1006 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1008 uint8_t num_clip_plane_consts
;
1009 bool clip_halfz
; /* for CC_VIEWPORT */
1010 bool depth_clip_near
; /* for CC_VIEWPORT */
1011 bool depth_clip_far
; /* for CC_VIEWPORT */
1012 bool flatshade
; /* for shader state */
1013 bool flatshade_first
; /* for stream output */
1014 bool clamp_fragment_color
; /* for shader state */
1015 bool light_twoside
; /* for shader state */
1016 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
1017 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1018 bool line_stipple_enable
;
1019 bool poly_stipple_enable
;
1021 bool force_persample_interp
;
1022 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1023 uint16_t sprite_coord_enable
;
1027 get_line_width(const struct pipe_rasterizer_state
*state
)
1029 float line_width
= state
->line_width
;
1031 /* From the OpenGL 4.4 spec:
1033 * "The actual width of non-antialiased lines is determined by rounding
1034 * the supplied width to the nearest integer, then clamping it to the
1035 * implementation-dependent maximum non-antialiased line width."
1037 if (!state
->multisample
&& !state
->line_smooth
)
1038 line_width
= roundf(state
->line_width
);
1040 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1041 /* For 1 pixel line thickness or less, the general anti-aliasing
1042 * algorithm gives up, and a garbage line is generated. Setting a
1043 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1044 * (one-pixel-wide), non-antialiased lines.
1046 * Lines rendered with zero Line Width are rasterized using the
1047 * "Grid Intersection Quantization" rules as specified by the
1048 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1057 * The pipe->create_rasterizer_state() driver hook.
1060 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1061 const struct pipe_rasterizer_state
*state
)
1063 struct iris_rasterizer_state
*cso
=
1064 malloc(sizeof(struct iris_rasterizer_state
));
1067 point_quad_rasterization
-> SBE
?
1074 offset_units_unscaled
- cap
not exposed
1078 // XXX: it may make more sense just to store the pipe_rasterizer_state,
1079 // we're copying a lot of booleans here. But we don't need all of them...
1081 cso
->multisample
= state
->multisample
;
1082 cso
->force_persample_interp
= state
->force_persample_interp
;
1083 cso
->clip_halfz
= state
->clip_halfz
;
1084 cso
->depth_clip_near
= state
->depth_clip_near
;
1085 cso
->depth_clip_far
= state
->depth_clip_far
;
1086 cso
->flatshade
= state
->flatshade
;
1087 cso
->flatshade_first
= state
->flatshade_first
;
1088 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1089 cso
->light_twoside
= state
->light_twoside
;
1090 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1091 cso
->half_pixel_center
= state
->half_pixel_center
;
1092 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1093 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1094 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1095 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1097 if (state
->clip_plane_enable
!= 0)
1098 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1100 cso
->num_clip_plane_consts
= 0;
1102 float line_width
= get_line_width(state
);
1104 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1105 sf
.StatisticsEnable
= true;
1106 sf
.ViewportTransformEnable
= true;
1107 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1108 sf
.LineEndCapAntialiasingRegionWidth
=
1109 state
->line_smooth
? _10pixels
: _05pixels
;
1110 sf
.LastPixelEnable
= state
->line_last_pixel
;
1111 sf
.LineWidth
= line_width
;
1112 sf
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1113 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1114 sf
.PointWidth
= state
->point_size
;
1116 if (state
->flatshade_first
) {
1117 sf
.TriangleFanProvokingVertexSelect
= 1;
1119 sf
.TriangleStripListProvokingVertexSelect
= 2;
1120 sf
.TriangleFanProvokingVertexSelect
= 2;
1121 sf
.LineStripListProvokingVertexSelect
= 1;
1125 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1126 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1127 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1128 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1129 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1130 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1131 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1132 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1133 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1134 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1135 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1136 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1137 rr
.SmoothPointEnable
= state
->point_smooth
|| state
->multisample
;
1138 rr
.AntialiasingEnable
= state
->line_smooth
;
1139 rr
.ScissorRectangleEnable
= state
->scissor
;
1140 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1141 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1142 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
1145 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1146 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1147 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1149 cl
.EarlyCullEnable
= true;
1150 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1151 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1152 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1153 cl
.GuardbandClipTestEnable
= true;
1154 cl
.ClipEnable
= true;
1155 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1156 cl
.MinimumPointWidth
= 0.125;
1157 cl
.MaximumPointWidth
= 255.875;
1159 if (state
->flatshade_first
) {
1160 cl
.TriangleFanProvokingVertexSelect
= 1;
1162 cl
.TriangleStripListProvokingVertexSelect
= 2;
1163 cl
.TriangleFanProvokingVertexSelect
= 2;
1164 cl
.LineStripListProvokingVertexSelect
= 1;
1168 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1169 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1170 * filled in at draw time from the FS program.
1172 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1173 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1174 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1175 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1176 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1179 /* Remap from 0..255 back to 1..256 */
1180 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1182 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1183 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1184 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1185 line
.LineStippleRepeatCount
= line_stipple_factor
;
1192 * The pipe->bind_rasterizer_state() driver hook.
1194 * Bind a rasterizer CSO and flag related dirty bits.
1197 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1199 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1200 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1201 struct iris_rasterizer_state
*new_cso
= state
;
1204 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1205 if (cso_changed_memcmp(line_stipple
))
1206 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1208 if (cso_changed(half_pixel_center
))
1209 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1211 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1212 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1214 if (cso_changed(rasterizer_discard
) || cso_changed(flatshade_first
))
1215 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1217 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1218 cso_changed(clip_halfz
))
1219 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1221 if (cso_changed(sprite_coord_enable
) ||
1222 cso_changed(sprite_coord_mode
) ||
1223 cso_changed(light_twoside
))
1224 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1227 ice
->state
.cso_rast
= new_cso
;
1228 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1229 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1230 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1234 * Return true if the given wrap mode requires the border color to exist.
1236 * (We can skip uploading it if the sampler isn't going to use it.)
1239 wrap_mode_needs_border_color(unsigned wrap_mode
)
1241 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1245 * Gallium CSO for sampler state.
1247 struct iris_sampler_state
{
1248 union pipe_color_union border_color
;
1249 bool needs_border_color
;
1251 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1255 * The pipe->create_sampler_state() driver hook.
1257 * We fill out SAMPLER_STATE (except for the border color pointer), and
1258 * store that on the CPU. It doesn't make sense to upload it to a GPU
1259 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1260 * all bound sampler states to be in contiguous memor.
1263 iris_create_sampler_state(struct pipe_context
*ctx
,
1264 const struct pipe_sampler_state
*state
)
1266 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1271 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1272 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1274 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1275 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1276 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1278 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1280 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1281 wrap_mode_needs_border_color(wrap_t
) ||
1282 wrap_mode_needs_border_color(wrap_r
);
1284 float min_lod
= state
->min_lod
;
1285 unsigned mag_img_filter
= state
->mag_img_filter
;
1287 // XXX: explain this code ported from ilo...I don't get it at all...
1288 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1289 state
->min_lod
> 0.0f
) {
1291 mag_img_filter
= state
->min_img_filter
;
1294 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1295 samp
.TCXAddressControlMode
= wrap_s
;
1296 samp
.TCYAddressControlMode
= wrap_t
;
1297 samp
.TCZAddressControlMode
= wrap_r
;
1298 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1299 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1300 samp
.MinModeFilter
= state
->min_img_filter
;
1301 samp
.MagModeFilter
= mag_img_filter
;
1302 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1303 samp
.MaximumAnisotropy
= RATIO21
;
1305 if (state
->max_anisotropy
>= 2) {
1306 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1307 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1308 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1311 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1312 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1314 samp
.MaximumAnisotropy
=
1315 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1318 /* Set address rounding bits if not using nearest filtering. */
1319 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1320 samp
.UAddressMinFilterRoundingEnable
= true;
1321 samp
.VAddressMinFilterRoundingEnable
= true;
1322 samp
.RAddressMinFilterRoundingEnable
= true;
1325 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1326 samp
.UAddressMagFilterRoundingEnable
= true;
1327 samp
.VAddressMagFilterRoundingEnable
= true;
1328 samp
.RAddressMagFilterRoundingEnable
= true;
1331 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1332 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1334 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1336 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1337 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1338 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1339 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1341 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1348 * The pipe->bind_sampler_states() driver hook.
1350 * Now that we know all the sampler states, we upload them all into a
1351 * contiguous area of GPU memory, for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1352 * We also fill out the border color state pointers at this point.
1354 * We could defer this work to draw time, but we assume that binding
1355 * will be less frequent than drawing.
1357 // XXX: this may be a bad idea, need to make sure that st/mesa calls us
1358 // XXX: with the complete set of shaders. If it makes multiple calls to
1359 // XXX: things one at a time, we could waste a lot of time assembling things.
1360 // XXX: it doesn't even BUY us anything to do it here, because we only flag
1361 // XXX: IRIS_DIRTY_SAMPLER_STATE when this is called...
1363 iris_bind_sampler_states(struct pipe_context
*ctx
,
1364 enum pipe_shader_type p_stage
,
1365 unsigned start
, unsigned count
,
1368 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1369 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1370 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1372 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1374 for (int i
= 0; i
< count
; i
++) {
1375 shs
->samplers
[start
+ i
] = states
[i
];
1378 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1379 * in the dynamic state memory zone, so we can point to it via the
1380 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1383 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1384 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1388 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1389 shs
->sampler_table
.offset
+=
1390 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1392 /* Make sure all land in the same BO */
1393 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1395 for (int i
= 0; i
< count
; i
++) {
1396 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1399 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1400 } else if (!state
->needs_border_color
) {
1401 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1403 ice
->state
.need_border_colors
= true;
1405 /* Stream out the border color and merge the pointer. */
1407 iris_upload_border_color(ice
, &state
->border_color
);
1409 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1410 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1411 dyns
.BorderColorPointer
= offset
;
1414 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1415 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1418 map
+= GENX(SAMPLER_STATE_length
);
1421 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1424 static enum isl_channel_select
1425 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1428 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1429 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1430 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1431 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1432 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1433 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1434 default: unreachable("invalid swizzle");
1439 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1442 enum isl_format format
,
1446 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1447 const unsigned cpp
= fmtl
->bpb
/ 8;
1449 /* The ARB_texture_buffer_specification says:
1451 * "The number of texels in the buffer texture's texel array is given by
1453 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1455 * where <buffer_size> is the size of the buffer object, in basic
1456 * machine units and <components> and <base_type> are the element count
1457 * and base data type for elements, as specified in Table X.1. The
1458 * number of texels in the texel array is then clamped to the
1459 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1461 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1462 * so that when ISL divides by stride to obtain the number of texels, that
1463 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1465 unsigned final_size
=
1466 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1468 isl_buffer_fill_state(isl_dev
, map
,
1469 .address
= bo
->gtt_offset
+ offset
,
1470 .size_B
= final_size
,
1477 * The pipe->create_sampler_view() driver hook.
1479 static struct pipe_sampler_view
*
1480 iris_create_sampler_view(struct pipe_context
*ctx
,
1481 struct pipe_resource
*tex
,
1482 const struct pipe_sampler_view
*tmpl
)
1484 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1485 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1486 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1487 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1492 /* initialize base object */
1494 isv
->base
.context
= ctx
;
1495 isv
->base
.texture
= NULL
;
1496 pipe_reference_init(&isv
->base
.reference
, 1);
1497 pipe_resource_reference(&isv
->base
.texture
, tex
);
1499 void *map
= upload_state(ice
->state
.surface_uploader
, &isv
->surface_state
,
1500 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1504 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state
.res
);
1505 isv
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1507 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1508 struct iris_resource
*zres
, *sres
;
1509 const struct util_format_description
*desc
=
1510 util_format_description(tmpl
->format
);
1512 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1514 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1517 isv
->res
= (struct iris_resource
*) tex
;
1519 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1521 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1522 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1523 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1525 const struct iris_format_info fmt
=
1526 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1528 isv
->view
= (struct isl_view
) {
1530 .swizzle
= (struct isl_swizzle
) {
1531 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1532 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1533 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1534 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1539 /* Fill out SURFACE_STATE for this view. */
1540 if (tmpl
->target
!= PIPE_BUFFER
) {
1541 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1542 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1543 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1544 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1545 isv
->view
.array_len
=
1546 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1548 isl_surf_fill_state(&screen
->isl_dev
, map
,
1549 .surf
= &isv
->res
->surf
, .view
= &isv
->view
,
1551 .address
= isv
->res
->bo
->gtt_offset
);
1553 // .clear_color = clear_color,
1555 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1556 isv
->view
.format
, tmpl
->u
.buf
.offset
,
1564 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1565 struct pipe_sampler_view
*state
)
1567 struct iris_sampler_view
*isv
= (void *) state
;
1568 pipe_resource_reference(&state
->texture
, NULL
);
1569 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1574 * The pipe->create_surface() driver hook.
1576 * In Gallium nomenclature, "surfaces" are a view of a resource that
1577 * can be bound as a render target or depth/stencil buffer.
1579 static struct pipe_surface
*
1580 iris_create_surface(struct pipe_context
*ctx
,
1581 struct pipe_resource
*tex
,
1582 const struct pipe_surface
*tmpl
)
1584 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1585 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1586 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1587 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1588 struct pipe_surface
*psurf
= &surf
->base
;
1589 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1594 pipe_reference_init(&psurf
->reference
, 1);
1595 pipe_resource_reference(&psurf
->texture
, tex
);
1596 psurf
->context
= ctx
;
1597 psurf
->format
= tmpl
->format
;
1598 psurf
->width
= tex
->width0
;
1599 psurf
->height
= tex
->height0
;
1600 psurf
->texture
= tex
;
1601 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1602 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1603 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1605 isl_surf_usage_flags_t usage
= 0;
1607 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1608 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1609 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1611 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1613 const struct iris_format_info fmt
=
1614 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1616 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1617 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1618 /* Framebuffer validation will reject this invalid case, but it
1619 * hasn't had the opportunity yet. In the meantime, we need to
1620 * avoid hitting ISL asserts about unsupported formats below.
1626 surf
->view
= (struct isl_view
) {
1628 .base_level
= tmpl
->u
.tex
.level
,
1630 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1631 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1632 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1636 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1637 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1638 ISL_SURF_USAGE_STENCIL_BIT
))
1642 void *map
= upload_state(ice
->state
.surface_uploader
, &surf
->surface_state
,
1643 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1647 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state
.res
);
1648 surf
->surface_state
.offset
+= iris_bo_offset_from_base_address(state_bo
);
1650 isl_surf_fill_state(&screen
->isl_dev
, map
,
1651 .surf
= &res
->surf
, .view
= &surf
->view
,
1653 .address
= res
->bo
->gtt_offset
);
1655 // .clear_color = clear_color,
1661 * The pipe->set_shader_images() driver hook.
1664 iris_set_shader_images(struct pipe_context
*ctx
,
1665 enum pipe_shader_type p_stage
,
1666 unsigned start_slot
, unsigned count
,
1667 const struct pipe_image_view
*p_images
)
1669 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1670 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1671 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1672 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1673 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1675 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1677 for (unsigned i
= 0; i
< count
; i
++) {
1678 if (p_images
&& p_images
[i
].resource
) {
1679 const struct pipe_image_view
*img
= &p_images
[i
];
1680 struct iris_resource
*res
= (void *) img
->resource
;
1681 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, &res
->base
);
1683 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1685 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1687 // XXX: these are not retained forever, use a separate uploader?
1689 upload_state(ice
->state
.surface_uploader
,
1690 &shs
->image
[start_slot
+ i
].surface_state
,
1691 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
1692 if (!unlikely(map
)) {
1693 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1697 struct iris_bo
*surf_state_bo
=
1698 iris_resource_bo(shs
->image
[start_slot
+ i
].surface_state
.res
);
1699 shs
->image
[start_slot
+ i
].surface_state
.offset
+=
1700 iris_bo_offset_from_base_address(surf_state_bo
);
1702 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1703 enum isl_format isl_format
=
1704 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
1706 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
)
1707 isl_format
= isl_lower_storage_image_format(devinfo
, isl_format
);
1709 shs
->image
[start_slot
+ i
].access
= img
->shader_access
;
1711 if (res
->base
.target
!= PIPE_BUFFER
) {
1712 struct isl_view view
= {
1713 .format
= isl_format
,
1714 .base_level
= img
->u
.tex
.level
,
1716 .base_array_layer
= img
->u
.tex
.first_layer
,
1717 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
1718 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1722 isl_surf_fill_state(&screen
->isl_dev
, map
,
1723 .surf
= &res
->surf
, .view
= &view
,
1725 .address
= res
->bo
->gtt_offset
);
1727 // .clear_color = clear_color,
1729 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
1730 isl_format
, img
->u
.buf
.offset
,
1734 pipe_resource_reference(&shs
->image
[start_slot
+ i
].res
, NULL
);
1735 pipe_resource_reference(&shs
->image
[start_slot
+ i
].surface_state
.res
,
1740 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1745 * The pipe->set_sampler_views() driver hook.
1748 iris_set_sampler_views(struct pipe_context
*ctx
,
1749 enum pipe_shader_type p_stage
,
1750 unsigned start
, unsigned count
,
1751 struct pipe_sampler_view
**views
)
1753 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1754 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1755 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1757 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
1759 for (unsigned i
= 0; i
< count
; i
++) {
1760 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1761 &shs
->textures
[start
+ i
], views
[i
]);
1762 struct iris_sampler_view
*view
= (void *) views
[i
];
1764 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
1765 shs
->bound_sampler_views
|= 1 << (start
+ i
);
1769 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
1773 * The pipe->set_tess_state() driver hook.
1776 iris_set_tess_state(struct pipe_context
*ctx
,
1777 const float default_outer_level
[4],
1778 const float default_inner_level
[2])
1780 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1782 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
1783 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
1785 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
1789 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1791 struct iris_surface
*surf
= (void *) p_surf
;
1792 pipe_resource_reference(&p_surf
->texture
, NULL
);
1793 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
1798 iris_set_clip_state(struct pipe_context
*ctx
,
1799 const struct pipe_clip_state
*state
)
1801 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1802 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1804 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
1806 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
1807 shs
->cbuf0_needs_upload
= true;
1811 * The pipe->set_polygon_stipple() driver hook.
1814 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1815 const struct pipe_poly_stipple
*state
)
1817 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1818 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1819 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1823 * The pipe->set_sample_mask() driver hook.
1826 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1828 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1830 /* We only support 16x MSAA, so we have 16 bits of sample maks.
1831 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
1833 ice
->state
.sample_mask
= sample_mask
& 0xffff;
1834 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1838 * The pipe->set_scissor_states() driver hook.
1840 * This corresponds to our SCISSOR_RECT state structures. It's an
1841 * exact match, so we just store them, and memcpy them out later.
1844 iris_set_scissor_states(struct pipe_context
*ctx
,
1845 unsigned start_slot
,
1846 unsigned num_scissors
,
1847 const struct pipe_scissor_state
*rects
)
1849 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1851 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1852 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
1853 /* If the scissor was out of bounds and got clamped to 0 width/height
1854 * at the bounds, the subtraction of 1 from maximums could produce a
1855 * negative number and thus not clip anything. Instead, just provide
1856 * a min > max scissor inside the bounds, which produces the expected
1859 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1860 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
1863 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
1864 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
1865 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
1870 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1874 * The pipe->set_stencil_ref() driver hook.
1876 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
1879 iris_set_stencil_ref(struct pipe_context
*ctx
,
1880 const struct pipe_stencil_ref
*state
)
1882 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1883 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1884 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1888 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1890 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1895 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1896 float m00
, float m11
, float m30
, float m31
,
1897 float *xmin
, float *xmax
,
1898 float *ymin
, float *ymax
)
1900 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1901 * Strips and Fans documentation:
1903 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1904 * fixed-point "guardband" range supported by the rasterization hardware"
1908 * "In almost all circumstances, if an object’s vertices are actually
1909 * modified by this clamping (i.e., had X or Y coordinates outside of
1910 * the guardband extent the rendered object will not match the intended
1911 * result. Therefore software should take steps to ensure that this does
1912 * not happen - e.g., by clipping objects such that they do not exceed
1913 * these limits after the Drawing Rectangle is applied."
1915 * I believe the fundamental restriction is that the rasterizer (in
1916 * the SF/WM stages) have a limit on the number of pixels that can be
1917 * rasterized. We need to ensure any coordinates beyond the rasterizer
1918 * limit are handled by the clipper. So effectively that limit becomes
1919 * the clipper's guardband size.
1921 * It goes on to say:
1923 * "In addition, in order to be correctly rendered, objects must have a
1924 * screenspace bounding box not exceeding 8K in the X or Y direction.
1925 * This additional restriction must also be comprehended by software,
1926 * i.e., enforced by use of clipping."
1928 * This makes no sense. Gen7+ hardware supports 16K render targets,
1929 * and you definitely need to be able to draw polygons that fill the
1930 * surface. Our assumption is that the rasterizer was limited to 8K
1931 * on Sandybridge, which only supports 8K surfaces, and it was actually
1932 * increased to 16K on Ivybridge and later.
1934 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1936 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1938 if (m00
!= 0 && m11
!= 0) {
1939 /* First, we compute the screen-space render area */
1940 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1941 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1942 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1943 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1945 /* We want the guardband to be centered on that */
1946 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1947 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1948 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1949 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1951 /* Now we need it in native device coordinates */
1952 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1953 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1954 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1955 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1957 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1958 * flipped upside-down. X should be fine though.
1960 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1961 *xmin
= ndc_gb_xmin
;
1962 *xmax
= ndc_gb_xmax
;
1963 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1964 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1966 /* The viewport scales to 0, so nothing will be rendered. */
1976 * The pipe->set_viewport_states() driver hook.
1978 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
1979 * the guardband yet, as we need the framebuffer dimensions, but we can
1980 * at least fill out the rest.
1983 iris_set_viewport_states(struct pipe_context
*ctx
,
1984 unsigned start_slot
,
1986 const struct pipe_viewport_state
*states
)
1988 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1990 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
1992 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1994 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
1995 !ice
->state
.cso_rast
->depth_clip_far
))
1996 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2000 * The pipe->set_framebuffer_state() driver hook.
2002 * Sets the current draw FBO, including color render targets, depth,
2003 * and stencil buffers.
2006 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2007 const struct pipe_framebuffer_state
*state
)
2009 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2010 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2011 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2012 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2013 struct iris_resource
*zres
;
2014 struct iris_resource
*stencil_res
;
2016 unsigned samples
= util_framebuffer_get_num_samples(state
);
2018 if (cso
->samples
!= samples
) {
2019 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2022 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2023 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2026 if ((cso
->layers
== 0) != (state
->layers
== 0)) {
2027 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2030 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2031 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2034 util_copy_framebuffer_state(cso
, state
);
2035 cso
->samples
= samples
;
2037 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2039 struct isl_view view
= {
2042 .base_array_layer
= 0,
2044 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2047 struct isl_depth_stencil_hiz_emit_info info
= {
2053 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2056 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2057 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2059 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2062 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2064 info
.depth_surf
= &zres
->surf
;
2065 info
.depth_address
= zres
->bo
->gtt_offset
;
2066 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
2068 view
.format
= zres
->surf
.format
;
2072 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2073 info
.stencil_surf
= &stencil_res
->surf
;
2074 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2076 view
.format
= stencil_res
->surf
.format
;
2080 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2082 /* Make a null surface for unbound buffers */
2083 void *null_surf_map
=
2084 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2085 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2086 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2087 isl_extent3d(MAX2(cso
->width
, 1),
2088 MAX2(cso
->height
, 1),
2089 cso
->layers
? cso
->layers
: 1));
2090 ice
->state
.null_fb
.offset
+=
2091 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2093 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2095 /* Render target change */
2096 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2098 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2101 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2102 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2104 /* The PIPE_CONTROL command description says:
2106 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2107 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2108 * Target Cache Flush by enabling this bit. When render target flush
2109 * is set due to new association of BTI, PS Scoreboard Stall bit must
2110 * be set in this packet."
2112 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2113 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2114 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2115 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2120 upload_ubo_surf_state(struct iris_context
*ice
,
2121 struct iris_const_buffer
*cbuf
,
2122 unsigned buffer_size
)
2124 struct pipe_context
*ctx
= &ice
->ctx
;
2125 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2127 // XXX: these are not retained forever, use a separate uploader?
2129 upload_state(ice
->state
.surface_uploader
, &cbuf
->surface_state
,
2130 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2131 if (!unlikely(map
)) {
2132 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2136 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2137 struct iris_bo
*surf_bo
= iris_resource_bo(cbuf
->surface_state
.res
);
2138 cbuf
->surface_state
.offset
+= iris_bo_offset_from_base_address(surf_bo
);
2140 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2141 .address
= res
->bo
->gtt_offset
+ cbuf
->data
.offset
,
2142 .size_B
= MIN2(buffer_size
,
2143 res
->bo
->size
- cbuf
->data
.offset
),
2144 .format
= ISL_FORMAT_R32G32B32A32_FLOAT
,
2150 * The pipe->set_constant_buffer() driver hook.
2152 * This uploads any constant data in user buffers, and references
2153 * any UBO resources containing constant data.
2156 iris_set_constant_buffer(struct pipe_context
*ctx
,
2157 enum pipe_shader_type p_stage
, unsigned index
,
2158 const struct pipe_constant_buffer
*input
)
2160 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2161 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2162 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2163 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[index
];
2165 if (input
&& input
->buffer
) {
2168 pipe_resource_reference(&cbuf
->data
.res
, input
->buffer
);
2169 cbuf
->data
.offset
= input
->buffer_offset
;
2171 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
2172 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2174 upload_ubo_surf_state(ice
, cbuf
, input
->buffer_size
);
2176 pipe_resource_reference(&cbuf
->data
.res
, NULL
);
2177 pipe_resource_reference(&cbuf
->surface_state
.res
, NULL
);
2182 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2184 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2186 shs
->cbuf0_needs_upload
= true;
2189 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2190 // XXX: maybe not necessary all the time...?
2191 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2192 // XXX: pull model we may need actual new bindings...
2193 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2197 upload_uniforms(struct iris_context
*ice
,
2198 gl_shader_stage stage
)
2200 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2201 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
2202 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2204 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2205 shs
->cbuf0
.buffer_size
;
2207 if (upload_size
== 0)
2211 upload_state(ice
->ctx
.const_uploader
, &cbuf
->data
, upload_size
, 64);
2213 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2214 uint32_t sysval
= shader
->system_values
[i
];
2217 if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2218 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2219 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2220 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2222 assert(!"unhandled system value");
2228 if (shs
->cbuf0
.user_buffer
) {
2229 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2232 upload_ubo_surf_state(ice
, cbuf
, upload_size
);
2236 * The pipe->set_shader_buffers() driver hook.
2238 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2239 * SURFACE_STATE here, as the buffer offset may change each time.
2242 iris_set_shader_buffers(struct pipe_context
*ctx
,
2243 enum pipe_shader_type p_stage
,
2244 unsigned start_slot
, unsigned count
,
2245 const struct pipe_shader_buffer
*buffers
)
2247 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2248 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2249 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2250 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2252 for (unsigned i
= 0; i
< count
; i
++) {
2253 if (buffers
&& buffers
[i
].buffer
) {
2254 const struct pipe_shader_buffer
*buffer
= &buffers
[i
];
2255 struct iris_resource
*res
= (void *) buffer
->buffer
;
2256 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], &res
->base
);
2258 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2260 // XXX: these are not retained forever, use a separate uploader?
2262 upload_state(ice
->state
.surface_uploader
,
2263 &shs
->ssbo_surface_state
[start_slot
+ i
],
2264 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2265 if (!unlikely(map
)) {
2266 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2270 struct iris_bo
*surf_state_bo
=
2271 iris_resource_bo(shs
->ssbo_surface_state
[start_slot
+ i
].res
);
2272 shs
->ssbo_surface_state
[start_slot
+ i
].offset
+=
2273 iris_bo_offset_from_base_address(surf_state_bo
);
2275 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2277 res
->bo
->gtt_offset
+ buffer
->buffer_offset
,
2279 MIN2(buffer
->buffer_size
,
2280 res
->bo
->size
- buffer
->buffer_offset
),
2281 .format
= ISL_FORMAT_RAW
,
2285 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
], NULL
);
2286 pipe_resource_reference(&shs
->ssbo_surface_state
[start_slot
+ i
].res
,
2291 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2295 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2301 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
2303 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
2304 pipe_resource_reference(&cso
->resources
[i
], NULL
);
2308 * The pipe->set_vertex_buffers() driver hook.
2310 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2313 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2314 unsigned start_slot
, unsigned count
,
2315 const struct pipe_vertex_buffer
*buffers
)
2317 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2318 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
2320 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
2325 cso
->num_buffers
= count
;
2327 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
2328 vb
.DWordLength
= 4 * MAX2(cso
->num_buffers
, 1) - 1;
2331 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
2334 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2335 vb
.VertexBufferIndex
= start_slot
;
2336 vb
.NullVertexBuffer
= true;
2337 vb
.AddressModifyEnable
= true;
2341 for (unsigned i
= 0; i
< count
; i
++) {
2342 assert(!buffers
[i
].is_user_buffer
);
2344 pipe_resource_reference(&cso
->resources
[i
], buffers
[i
].buffer
.resource
);
2345 struct iris_resource
*res
= (void *) cso
->resources
[i
];
2348 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2350 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
2351 vb
.VertexBufferIndex
= start_slot
+ i
;
2353 vb
.AddressModifyEnable
= true;
2354 vb
.BufferPitch
= buffers
[i
].stride
;
2356 vb
.BufferSize
= res
->bo
->size
;
2357 vb
.BufferStartingAddress
=
2358 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
2360 vb
.NullVertexBuffer
= true;
2364 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
2367 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2371 * Gallium CSO for vertex elements.
2373 struct iris_vertex_element_state
{
2374 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2375 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2380 * The pipe->create_vertex_elements() driver hook.
2382 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2383 * and 3DSTATE_VF_INSTANCING commands. SGVs are handled at draw time.
2386 iris_create_vertex_elements(struct pipe_context
*ctx
,
2388 const struct pipe_vertex_element
*state
)
2390 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2391 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2392 struct iris_vertex_element_state
*cso
=
2393 malloc(sizeof(struct iris_vertex_element_state
));
2398 * - create edge flag one
2400 * - if those are necessary, use count + 1/2/3... OR in the length
2402 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2404 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2407 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2408 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2411 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2413 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2414 ve
.Component0Control
= VFCOMP_STORE_0
;
2415 ve
.Component1Control
= VFCOMP_STORE_0
;
2416 ve
.Component2Control
= VFCOMP_STORE_0
;
2417 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2420 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2424 for (int i
= 0; i
< count
; i
++) {
2425 const struct iris_format_info fmt
=
2426 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2427 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2428 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2430 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2431 case 0: comp
[0] = VFCOMP_STORE_0
;
2432 case 1: comp
[1] = VFCOMP_STORE_0
;
2433 case 2: comp
[2] = VFCOMP_STORE_0
;
2435 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2436 : VFCOMP_STORE_1_FP
;
2439 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2440 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2442 ve
.SourceElementOffset
= state
[i
].src_offset
;
2443 ve
.SourceElementFormat
= fmt
.fmt
;
2444 ve
.Component0Control
= comp
[0];
2445 ve
.Component1Control
= comp
[1];
2446 ve
.Component2Control
= comp
[2];
2447 ve
.Component3Control
= comp
[3];
2450 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2451 vi
.VertexElementIndex
= i
;
2452 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2453 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2456 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2457 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2464 * The pipe->bind_vertex_elements_state() driver hook.
2467 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2469 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2470 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2471 struct iris_vertex_element_state
*new_cso
= state
;
2473 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2474 * we need to re-emit it to ensure we're overriding the right one.
2476 if (new_cso
&& cso_changed(count
))
2477 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2479 ice
->state
.cso_vertex_elements
= state
;
2480 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2484 * Gallium CSO for stream output (transform feedback) targets.
2486 struct iris_stream_output_target
{
2487 struct pipe_stream_output_target base
;
2489 uint32_t so_buffer
[GENX(3DSTATE_SO_BUFFER_length
)];
2491 /** Storage holding the offset where we're writing in the buffer */
2492 struct iris_state_ref offset
;
2496 * The pipe->create_stream_output_target() driver hook.
2498 * "Target" here refers to a destination buffer. We translate this into
2499 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2500 * know which buffer this represents, or whether we ought to zero the
2501 * write-offsets, or append. Those are handled in the set() hook.
2503 static struct pipe_stream_output_target
*
2504 iris_create_stream_output_target(struct pipe_context
*ctx
,
2505 struct pipe_resource
*p_res
,
2506 unsigned buffer_offset
,
2507 unsigned buffer_size
)
2509 struct iris_resource
*res
= (void *) p_res
;
2510 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2514 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2516 pipe_reference_init(&cso
->base
.reference
, 1);
2517 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2518 cso
->base
.buffer_offset
= buffer_offset
;
2519 cso
->base
.buffer_size
= buffer_size
;
2520 cso
->base
.context
= ctx
;
2522 upload_state(ctx
->stream_uploader
, &cso
->offset
, 4 * sizeof(uint32_t), 4);
2524 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), cso
->so_buffer
, sob
) {
2525 sob
.SurfaceBaseAddress
=
2526 rw_bo(NULL
, res
->bo
->gtt_offset
+ buffer_offset
);
2527 sob
.SOBufferEnable
= true;
2528 sob
.StreamOffsetWriteEnable
= true;
2529 sob
.StreamOutputBufferOffsetAddressEnable
= true;
2530 sob
.MOCS
= MOCS_WB
; // XXX: MOCS
2532 sob
.SurfaceSize
= MAX2(buffer_size
/ 4, 1) - 1;
2534 /* .SOBufferIndex, .StreamOffset, and .StreamOutputBufferOffsetAddress
2535 * are filled in later when we have stream IDs.
2543 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2544 struct pipe_stream_output_target
*state
)
2546 struct iris_stream_output_target
*cso
= (void *) state
;
2548 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2549 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2555 * The pipe->set_stream_output_targets() driver hook.
2557 * At this point, we know which targets are bound to a particular index,
2558 * and also whether we want to append or start over. We can finish the
2559 * 3DSTATE_SO_BUFFER packets we started earlier.
2562 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2563 unsigned num_targets
,
2564 struct pipe_stream_output_target
**targets
,
2565 const unsigned *offsets
)
2567 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2568 struct iris_genx_state
*genx
= ice
->state
.genx
;
2569 uint32_t *so_buffers
= genx
->so_buffers
;
2571 const bool active
= num_targets
> 0;
2572 if (ice
->state
.streamout_active
!= active
) {
2573 ice
->state
.streamout_active
= active
;
2574 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2576 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2577 * it's a non-pipelined command. If we're switching streamout on, we
2578 * may have missed emitting it earlier, so do so now. (We're already
2579 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2582 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2585 for (int i
= 0; i
< 4; i
++) {
2586 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2587 i
< num_targets
? targets
[i
] : NULL
);
2590 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2594 for (unsigned i
= 0; i
< 4; i
++,
2595 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2597 if (i
>= num_targets
|| !targets
[i
]) {
2598 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2599 sob
.SOBufferIndex
= i
;
2603 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2605 /* Note that offsets[i] will either be 0, causing us to zero
2606 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2607 * "continue appending at the existing offset."
2609 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
2611 uint32_t dynamic
[GENX(3DSTATE_SO_BUFFER_length
)];
2612 iris_pack_state(GENX(3DSTATE_SO_BUFFER
), dynamic
, dyns
) {
2613 dyns
.SOBufferIndex
= i
;
2614 dyns
.StreamOffset
= offsets
[i
];
2615 dyns
.StreamOutputBufferOffsetAddress
=
2616 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+ tgt
->offset
.offset
+ i
* sizeof(uint32_t));
2619 for (uint32_t j
= 0; j
< GENX(3DSTATE_SO_BUFFER_length
); j
++) {
2620 so_buffers
[j
] = tgt
->so_buffer
[j
] | dynamic
[j
];
2624 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
2628 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
2629 * 3DSTATE_STREAMOUT packets.
2631 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
2632 * hardware to record. We can create it entirely based on the shader, with
2633 * no dynamic state dependencies.
2635 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
2636 * state-based settings. We capture the shader-related ones here, and merge
2637 * the rest in at draw time.
2640 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
2641 const struct brw_vue_map
*vue_map
)
2643 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
2644 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2645 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2646 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
2648 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
2650 memset(so_decl
, 0, sizeof(so_decl
));
2652 /* Construct the list of SO_DECLs to be emitted. The formatting of the
2653 * command feels strange -- each dword pair contains a SO_DECL per stream.
2655 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
2656 const struct pipe_stream_output
*output
= &info
->output
[i
];
2657 const int buffer
= output
->output_buffer
;
2658 const int varying
= output
->register_index
;
2659 const unsigned stream_id
= output
->stream
;
2660 assert(stream_id
< MAX_VERTEX_STREAMS
);
2662 buffer_mask
[stream_id
] |= 1 << buffer
;
2664 assert(vue_map
->varying_to_slot
[varying
] >= 0);
2666 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
2667 * array. Instead, it simply increments DstOffset for the following
2668 * input by the number of components that should be skipped.
2670 * Our hardware is unusual in that it requires us to program SO_DECLs
2671 * for fake "hole" components, rather than simply taking the offset
2672 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
2673 * program as many size = 4 holes as we can, then a final hole to
2674 * accommodate the final 1, 2, or 3 remaining.
2676 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
2678 while (skip_components
> 0) {
2679 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2681 .OutputBufferSlot
= output
->output_buffer
,
2682 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
2684 skip_components
-= 4;
2687 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
2689 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
2690 .OutputBufferSlot
= output
->output_buffer
,
2691 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
2693 ((1 << output
->num_components
) - 1) << output
->start_component
,
2696 if (decls
[stream_id
] > max_decls
)
2697 max_decls
= decls
[stream_id
];
2700 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
2701 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
2702 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
2704 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
2705 int urb_entry_read_offset
= 0;
2706 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
2707 urb_entry_read_offset
;
2709 /* We always read the whole vertex. This could be reduced at some
2710 * point by reading less and offsetting the register index in the
2713 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
2714 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
2715 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
2716 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
2717 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
2718 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
2719 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
2720 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
2722 /* Set buffer pitches; 0 means unbound. */
2723 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
2724 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
2725 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
2726 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
2729 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
2730 list
.DWordLength
= 3 + 2 * max_decls
- 2;
2731 list
.StreamtoBufferSelects0
= buffer_mask
[0];
2732 list
.StreamtoBufferSelects1
= buffer_mask
[1];
2733 list
.StreamtoBufferSelects2
= buffer_mask
[2];
2734 list
.StreamtoBufferSelects3
= buffer_mask
[3];
2735 list
.NumEntries0
= decls
[0];
2736 list
.NumEntries1
= decls
[1];
2737 list
.NumEntries2
= decls
[2];
2738 list
.NumEntries3
= decls
[3];
2741 for (int i
= 0; i
< max_decls
; i
++) {
2742 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
2743 entry
.Stream0Decl
= so_decl
[0][i
];
2744 entry
.Stream1Decl
= so_decl
[1][i
];
2745 entry
.Stream2Decl
= so_decl
[2][i
];
2746 entry
.Stream3Decl
= so_decl
[3][i
];
2754 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
2755 const struct brw_vue_map
*last_vue_map
,
2756 bool two_sided_color
,
2757 unsigned *out_offset
,
2758 unsigned *out_length
)
2760 /* The compiler computes the first URB slot without considering COL/BFC
2761 * swizzling (because it doesn't know whether it's enabled), so we need
2762 * to do that here too. This may result in a smaller offset, which
2765 const unsigned first_slot
=
2766 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
2768 /* This becomes the URB read offset (counted in pairs of slots). */
2769 assert(first_slot
% 2 == 0);
2770 *out_offset
= first_slot
/ 2;
2772 /* We need to adjust the inputs read to account for front/back color
2773 * swizzling, as it can make the URB length longer.
2775 for (int c
= 0; c
<= 1; c
++) {
2776 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
2777 /* If two sided color is enabled, the fragment shader's gl_Color
2778 * (COL0) input comes from either the gl_FrontColor (COL0) or
2779 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
2781 if (two_sided_color
)
2782 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2784 /* If front color isn't written, we opt to give them back color
2785 * instead of an undefined value. Switch from COL to BFC.
2787 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
2788 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
2789 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
2794 /* Compute the minimum URB Read Length necessary for the FS inputs.
2796 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
2797 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
2799 * "This field should be set to the minimum length required to read the
2800 * maximum source attribute. The maximum source attribute is indicated
2801 * by the maximum value of the enabled Attribute # Source Attribute if
2802 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
2803 * enable is not set.
2804 * read_length = ceiling((max_source_attr + 1) / 2)
2806 * [errata] Corruption/Hang possible if length programmed larger than
2809 * Similar text exists for Ivy Bridge.
2811 * We find the last URB slot that's actually read by the FS.
2813 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
2814 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
2815 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
2818 /* The URB read length is the difference of the two, counted in pairs. */
2819 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
2823 iris_emit_sbe_swiz(struct iris_batch
*batch
,
2824 const struct iris_context
*ice
,
2825 unsigned urb_read_offset
,
2826 unsigned sprite_coord_enables
)
2828 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
2829 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2830 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2831 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
2832 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2834 /* XXX: this should be generated when putting programs in place */
2836 // XXX: raster->sprite_coord_enable
2838 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
2839 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
2840 if (input_index
< 0 || input_index
>= 16)
2843 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
2844 &attr_overrides
[input_index
];
2845 int slot
= vue_map
->varying_to_slot
[fs_attr
];
2847 /* Viewport and Layer are stored in the VUE header. We need to override
2848 * them to zero if earlier stages didn't write them, as GL requires that
2849 * they read back as zero when not explicitly set.
2852 case VARYING_SLOT_VIEWPORT
:
2853 case VARYING_SLOT_LAYER
:
2854 attr
->ComponentOverrideX
= true;
2855 attr
->ComponentOverrideW
= true;
2856 attr
->ConstantSource
= CONST_0000
;
2858 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
2859 attr
->ComponentOverrideY
= true;
2860 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
2861 attr
->ComponentOverrideZ
= true;
2864 case VARYING_SLOT_PRIMITIVE_ID
:
2865 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
2867 attr
->ComponentOverrideX
= true;
2868 attr
->ComponentOverrideY
= true;
2869 attr
->ComponentOverrideZ
= true;
2870 attr
->ComponentOverrideW
= true;
2871 attr
->ConstantSource
= PRIM_ID
;
2879 if (sprite_coord_enables
& (1 << input_index
))
2882 /* If there was only a back color written but not front, use back
2883 * as the color instead of undefined.
2885 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
2886 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
2887 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
2888 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
2890 /* Not written by the previous stage - undefined. */
2892 attr
->ComponentOverrideX
= true;
2893 attr
->ComponentOverrideY
= true;
2894 attr
->ComponentOverrideZ
= true;
2895 attr
->ComponentOverrideW
= true;
2896 attr
->ConstantSource
= CONST_0001_FLOAT
;
2900 /* Compute the location of the attribute relative to the read offset,
2901 * which is counted in 256-bit increments (two 128-bit VUE slots).
2903 const int source_attr
= slot
- 2 * urb_read_offset
;
2904 assert(source_attr
>= 0 && source_attr
<= 32);
2905 attr
->SourceAttribute
= source_attr
;
2907 /* If we are doing two-sided color, and the VUE slot following this one
2908 * represents a back-facing color, then we need to instruct the SF unit
2909 * to do back-facing swizzling.
2911 if (cso_rast
->light_twoside
&&
2912 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
2913 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
2914 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
2915 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
2916 attr
->SwizzleSelect
= INPUTATTR_FACING
;
2919 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
2920 for (int i
= 0; i
< 16; i
++)
2921 sbes
.Attribute
[i
] = attr_overrides
[i
];
2926 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
2927 const struct iris_rasterizer_state
*cso
)
2929 unsigned overrides
= 0;
2931 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
2932 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
2934 for (int i
= 0; i
< 8; i
++) {
2935 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
2936 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
2937 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
2944 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
2946 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2947 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
2948 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2949 const struct shader_info
*fs_info
=
2950 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
2952 unsigned urb_read_offset
, urb_read_length
;
2953 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
2954 ice
->shaders
.last_vue_map
,
2955 cso_rast
->light_twoside
,
2956 &urb_read_offset
, &urb_read_length
);
2958 unsigned sprite_coord_overrides
=
2959 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
2961 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
2962 sbe
.AttributeSwizzleEnable
= true;
2963 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
2964 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
2965 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
2966 sbe
.VertexURBEntryReadLength
= urb_read_length
;
2967 sbe
.ForceVertexURBEntryReadOffset
= true;
2968 sbe
.ForceVertexURBEntryReadLength
= true;
2969 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
2970 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
2972 for (int i
= 0; i
< 32; i
++) {
2973 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
2977 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
2980 /* ------------------------------------------------------------------- */
2983 * Populate VS program key fields based on the current state.
2986 iris_populate_vs_key(const struct iris_context
*ice
,
2987 const struct shader_info
*info
,
2988 struct brw_vs_prog_key
*key
)
2990 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2992 if (info
->clip_distance_array_size
== 0 &&
2993 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
2994 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
2998 * Populate TCS program key fields based on the current state.
3001 iris_populate_tcs_key(const struct iris_context
*ice
,
3002 struct brw_tcs_prog_key
*key
)
3007 * Populate TES program key fields based on the current state.
3010 iris_populate_tes_key(const struct iris_context
*ice
,
3011 struct brw_tes_prog_key
*key
)
3016 * Populate GS program key fields based on the current state.
3019 iris_populate_gs_key(const struct iris_context
*ice
,
3020 struct brw_gs_prog_key
*key
)
3025 * Populate FS program key fields based on the current state.
3028 iris_populate_fs_key(const struct iris_context
*ice
,
3029 struct brw_wm_prog_key
*key
)
3031 /* XXX: dirty flags? */
3032 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3033 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3034 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3035 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3037 key
->nr_color_regions
= fb
->nr_cbufs
;
3039 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3041 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
3042 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
3044 /* XXX: only bother if COL0/1 are read */
3045 key
->flat_shade
= rast
->flatshade
;
3047 key
->persample_interp
= rast
->force_persample_interp
;
3048 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3050 key
->coherent_fb_fetch
= true;
3052 // XXX: uint64_t input_slots_valid; - for >16 inputs
3054 // XXX: key->force_dual_color_blend for unigine
3055 // XXX: respect hint for high_quality_derivatives:1;
3059 iris_populate_cs_key(const struct iris_context
*ice
,
3060 struct brw_cs_prog_key
*key
)
3065 // XXX: these need to go in INIT_THREAD_DISPATCH_FIELDS
3066 pkt
.SamplerCount
= \
3067 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4); \
3072 KSP(const struct iris_compiled_shader
*shader
)
3074 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3075 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3078 // Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3079 // prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3080 // this WA on C0 stepping.
3082 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3083 pkt.KernelStartPointer = KSP(shader); \
3084 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3085 prog_data->binding_table.size_bytes / 4; \
3086 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3088 pkt.DispatchGRFStartRegisterForURBData = \
3089 prog_data->dispatch_grf_start_reg; \
3090 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3091 pkt.prefix##URBEntryReadOffset = 0; \
3093 pkt.StatisticsEnable = true; \
3094 pkt.Enable = true; \
3096 if (prog_data->total_scratch) { \
3097 uint32_t scratch_addr = \
3098 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3099 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3100 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3104 * Encode most of 3DSTATE_VS based on the compiled shader.
3107 iris_store_vs_state(struct iris_context
*ice
,
3108 const struct gen_device_info
*devinfo
,
3109 struct iris_compiled_shader
*shader
)
3111 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3112 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3114 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3115 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3116 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3117 vs
.SIMD8DispatchEnable
= true;
3118 vs
.UserClipDistanceCullTestEnableBitmask
=
3119 vue_prog_data
->cull_distance_mask
;
3124 * Encode most of 3DSTATE_HS based on the compiled shader.
3127 iris_store_tcs_state(struct iris_context
*ice
,
3128 const struct gen_device_info
*devinfo
,
3129 struct iris_compiled_shader
*shader
)
3131 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3132 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3133 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3135 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3136 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3138 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3139 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3140 hs
.IncludeVertexHandles
= true;
3145 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3148 iris_store_tes_state(struct iris_context
*ice
,
3149 const struct gen_device_info
*devinfo
,
3150 struct iris_compiled_shader
*shader
)
3152 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3153 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3154 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3156 uint32_t *te_state
= (void *) shader
->derived_data
;
3157 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3159 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3160 te
.Partitioning
= tes_prog_data
->partitioning
;
3161 te
.OutputTopology
= tes_prog_data
->output_topology
;
3162 te
.TEDomain
= tes_prog_data
->domain
;
3164 te
.MaximumTessellationFactorOdd
= 63.0;
3165 te
.MaximumTessellationFactorNotOdd
= 64.0;
3168 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3169 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3171 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3172 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3173 ds
.ComputeWCoordinateEnable
=
3174 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3176 ds
.UserClipDistanceCullTestEnableBitmask
=
3177 vue_prog_data
->cull_distance_mask
;
3183 * Encode most of 3DSTATE_GS based on the compiled shader.
3186 iris_store_gs_state(struct iris_context
*ice
,
3187 const struct gen_device_info
*devinfo
,
3188 struct iris_compiled_shader
*shader
)
3190 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3191 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3192 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3194 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3195 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3197 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3198 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3199 gs
.ControlDataHeaderSize
=
3200 gs_prog_data
->control_data_header_size_hwords
;
3201 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3202 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3203 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3204 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3205 gs
.ReorderMode
= TRAILING
;
3206 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3207 gs
.MaximumNumberofThreads
=
3208 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3209 : (devinfo
->max_gs_threads
- 1);
3211 if (gs_prog_data
->static_vertex_count
!= -1) {
3212 gs
.StaticOutput
= true;
3213 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3215 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3217 gs
.UserClipDistanceCullTestEnableBitmask
=
3218 vue_prog_data
->cull_distance_mask
;
3220 const int urb_entry_write_offset
= 1;
3221 const uint32_t urb_entry_output_length
=
3222 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3223 urb_entry_write_offset
;
3225 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3226 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3231 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3234 iris_store_fs_state(struct iris_context
*ice
,
3235 const struct gen_device_info
*devinfo
,
3236 struct iris_compiled_shader
*shader
)
3238 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3239 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3241 uint32_t *ps_state
= (void *) shader
->derived_data
;
3242 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3244 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3245 ps
.VectorMaskEnable
= true;
3246 //ps.SamplerCount = ...
3247 // XXX: WABTPPrefetchDisable, see above, drop at C0
3248 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3249 prog_data
->binding_table
.size_bytes
/ 4;
3250 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3251 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3253 ps
.PushConstantEnable
= shader
->num_system_values
> 0 ||
3254 prog_data
->ubo_ranges
[0].length
> 0;
3256 /* From the documentation for this packet:
3257 * "If the PS kernel does not need the Position XY Offsets to
3258 * compute a Position Value, then this field should be programmed
3259 * to POSOFFSET_NONE."
3261 * "SW Recommendation: If the PS kernel needs the Position Offsets
3262 * to compute a Position XY value, this field should match Position
3263 * ZW Interpolation Mode to ensure a consistent position.xyzw
3266 * We only require XY sample offsets. So, this recommendation doesn't
3267 * look useful at the moment. We might need this in future.
3269 ps
.PositionXYOffsetSelect
=
3270 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3271 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3272 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3273 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3275 // XXX: Disable SIMD32 with 16x MSAA
3277 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3278 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3279 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3280 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3281 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3282 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3284 ps
.KernelStartPointer0
=
3285 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3286 ps
.KernelStartPointer1
=
3287 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3288 ps
.KernelStartPointer2
=
3289 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3291 if (prog_data
->total_scratch
) {
3292 uint32_t scratch_addr
=
3293 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3294 MESA_SHADER_FRAGMENT
);
3295 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3296 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3300 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3301 psx
.PixelShaderValid
= true;
3302 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3303 // XXX: alpha test / alpha to coverage :/
3304 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
||
3305 wm_prog_data
->uses_omask
;
3306 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3307 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3308 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3309 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3311 if (wm_prog_data
->uses_sample_mask
) {
3312 /* TODO: conservative rasterization */
3313 if (wm_prog_data
->post_depth_coverage
)
3314 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
3316 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
3319 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3320 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3321 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3328 * Compute the size of the derived data (shader command packets).
3330 * This must match the data written by the iris_store_xs_state() functions.
3333 iris_store_cs_state(struct iris_context
*ice
,
3334 const struct gen_device_info
*devinfo
,
3335 struct iris_compiled_shader
*shader
)
3337 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3338 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3339 void *map
= shader
->derived_data
;
3341 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3342 desc
.KernelStartPointer
= KSP(shader
);
3343 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3344 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3345 desc
.SharedLocalMemorySize
=
3346 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3347 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3348 desc
.CrossThreadConstantDataReadLength
=
3349 cs_prog_data
->push
.cross_thread
.regs
;
3354 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3356 assert(cache_id
<= IRIS_CACHE_BLORP
);
3358 static const unsigned dwords
[] = {
3359 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3360 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3361 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3362 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3364 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3365 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3366 [IRIS_CACHE_BLORP
] = 0,
3369 return sizeof(uint32_t) * dwords
[cache_id
];
3373 * Create any state packets corresponding to the given shader stage
3374 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3375 * This means that we can look up a program in the in-memory cache and
3376 * get most of the state packet without having to reconstruct it.
3379 iris_store_derived_program_state(struct iris_context
*ice
,
3380 enum iris_program_cache_id cache_id
,
3381 struct iris_compiled_shader
*shader
)
3383 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3384 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3388 iris_store_vs_state(ice
, devinfo
, shader
);
3390 case IRIS_CACHE_TCS
:
3391 iris_store_tcs_state(ice
, devinfo
, shader
);
3393 case IRIS_CACHE_TES
:
3394 iris_store_tes_state(ice
, devinfo
, shader
);
3397 iris_store_gs_state(ice
, devinfo
, shader
);
3400 iris_store_fs_state(ice
, devinfo
, shader
);
3403 iris_store_cs_state(ice
, devinfo
, shader
);
3404 case IRIS_CACHE_BLORP
:
3411 /* ------------------------------------------------------------------- */
3414 * Configure the URB.
3416 * XXX: write a real comment.
3419 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
3421 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
3422 const unsigned push_size_kB
= 32;
3423 unsigned entries
[4];
3427 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3428 if (!ice
->shaders
.prog
[i
]) {
3431 struct brw_vue_prog_data
*vue_prog_data
=
3432 (void *) ice
->shaders
.prog
[i
]->prog_data
;
3433 size
[i
] = vue_prog_data
->urb_entry_size
;
3435 assert(size
[i
] != 0);
3438 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
3439 1024 * ice
->shaders
.urb_size
,
3440 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
3441 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
3442 size
, entries
, start
);
3444 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
3445 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
3446 urb
._3DCommandSubOpcode
+= i
;
3447 urb
.VSURBStartingAddress
= start
[i
];
3448 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
3449 urb
.VSNumberofURBEntries
= entries
[i
];
3454 static const uint32_t push_constant_opcodes
[] = {
3455 [MESA_SHADER_VERTEX
] = 21,
3456 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3457 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3458 [MESA_SHADER_GEOMETRY
] = 22,
3459 [MESA_SHADER_FRAGMENT
] = 23,
3460 [MESA_SHADER_COMPUTE
] = 0,
3464 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3466 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3468 iris_use_pinned_bo(batch
, state_bo
, false);
3470 return ice
->state
.unbound_tex
.offset
;
3474 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3476 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3477 if (!ice
->state
.null_fb
.res
)
3478 return use_null_surface(batch
, ice
);
3480 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3482 iris_use_pinned_bo(batch
, state_bo
, false);
3484 return ice
->state
.null_fb
.offset
;
3488 * Add a surface to the validation list, as well as the buffer containing
3489 * the corresponding SURFACE_STATE.
3491 * Returns the binding table entry (offset to SURFACE_STATE).
3494 use_surface(struct iris_batch
*batch
,
3495 struct pipe_surface
*p_surf
,
3498 struct iris_surface
*surf
= (void *) p_surf
;
3500 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3501 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3503 return surf
->surface_state
.offset
;
3507 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
3509 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3510 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3512 return isv
->surface_state
.offset
;
3516 use_const_buffer(struct iris_batch
*batch
,
3517 struct iris_context
*ice
,
3518 struct iris_const_buffer
*cbuf
)
3520 if (!cbuf
->surface_state
.res
)
3521 return use_null_surface(batch
, ice
);
3523 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->data
.res
), false);
3524 iris_use_pinned_bo(batch
, iris_resource_bo(cbuf
->surface_state
.res
), false);
3526 return cbuf
->surface_state
.offset
;
3530 use_ssbo(struct iris_batch
*batch
, struct iris_context
*ice
,
3531 struct iris_shader_state
*shs
, int i
)
3534 return use_null_surface(batch
, ice
);
3536 struct iris_state_ref
*surf_state
= &shs
->ssbo_surface_state
[i
];
3538 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->ssbo
[i
]), true);
3539 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3541 return surf_state
->offset
;
3545 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3546 struct iris_shader_state
*shs
, int i
)
3548 if (!shs
->image
[i
].res
)
3549 return use_null_surface(batch
, ice
);
3551 struct iris_state_ref
*surf_state
= &shs
->image
[i
].surface_state
;
3553 iris_use_pinned_bo(batch
, iris_resource_bo(shs
->image
[i
].res
),
3554 shs
->image
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
);
3555 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3557 return surf_state
->offset
;
3560 #define push_bt_entry(addr) \
3561 assert(addr >= binder_addr); \
3562 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
3563 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
3565 #define bt_assert(section, exists) \
3566 if (!pin_only) assert(prog_data->binding_table.section == \
3567 (exists) ? s : 0xd0d0d0d0)
3570 * Populate the binding table for a given shader stage.
3572 * This fills out the table of pointers to surfaces required by the shader,
3573 * and also adds those buffers to the validation list so the kernel can make
3574 * resident before running our batch.
3577 iris_populate_binding_table(struct iris_context
*ice
,
3578 struct iris_batch
*batch
,
3579 gl_shader_stage stage
,
3582 const struct iris_binder
*binder
= &ice
->state
.binder
;
3583 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3587 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3588 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3589 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
3591 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
3592 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
3595 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
3597 /* TCS passthrough doesn't need a binding table. */
3598 assert(stage
== MESA_SHADER_TESS_CTRL
);
3602 if (stage
== MESA_SHADER_COMPUTE
) {
3603 /* surface for gl_NumWorkGroups */
3604 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
3605 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
3606 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
3607 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
3608 push_bt_entry(grid_state
->offset
);
3611 if (stage
== MESA_SHADER_FRAGMENT
) {
3612 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3613 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
3614 if (cso_fb
->nr_cbufs
) {
3615 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
3617 cso_fb
->cbufs
[i
] ? use_surface(batch
, cso_fb
->cbufs
[i
], true)
3618 : use_null_fb_surface(batch
, ice
);
3619 push_bt_entry(addr
);
3622 uint32_t addr
= use_null_fb_surface(batch
, ice
);
3623 push_bt_entry(addr
);
3627 bt_assert(texture_start
, info
->num_textures
> 0);
3629 for (int i
= 0; i
< info
->num_textures
; i
++) {
3630 struct iris_sampler_view
*view
= shs
->textures
[i
];
3631 uint32_t addr
= view
? use_sampler_view(batch
, view
)
3632 : use_null_surface(batch
, ice
);
3633 push_bt_entry(addr
);
3636 bt_assert(image_start
, info
->num_images
> 0);
3638 for (int i
= 0; i
< info
->num_images
; i
++) {
3639 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
3640 push_bt_entry(addr
);
3643 const int num_ubos
= iris_get_shader_num_ubos(ice
, stage
);
3645 bt_assert(ubo_start
, num_ubos
> 0);
3647 for (int i
= 0; i
< num_ubos
; i
++) {
3648 uint32_t addr
= use_const_buffer(batch
, ice
, &shs
->constbuf
[i
]);
3649 push_bt_entry(addr
);
3652 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
3654 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
3655 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
3656 * in st_atom_storagebuf.c so it'll compact them into one range, with
3657 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
3659 if (info
->num_abos
+ info
->num_ssbos
> 0) {
3660 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
3661 uint32_t addr
= use_ssbo(batch
, ice
, shs
, i
);
3662 push_bt_entry(addr
);
3667 // XXX: not implemented yet
3668 bt_assert(plane_start
[1], ...);
3669 bt_assert(plane_start
[2], ...);
3674 iris_use_optional_res(struct iris_batch
*batch
,
3675 struct pipe_resource
*res
,
3679 struct iris_bo
*bo
= iris_resource_bo(res
);
3680 iris_use_pinned_bo(batch
, bo
, writeable
);
3684 /* ------------------------------------------------------------------- */
3687 * Pin any BOs which were installed by a previous batch, and restored
3688 * via the hardware logical context mechanism.
3690 * We don't need to re-emit all state every batch - the hardware context
3691 * mechanism will save and restore it for us. This includes pointers to
3692 * various BOs...which won't exist unless we ask the kernel to pin them
3693 * by adding them to the validation list.
3695 * We can skip buffers if we've re-emitted those packets, as we're
3696 * overwriting those stale pointers with new ones, and don't actually
3697 * refer to the old BOs.
3700 iris_restore_render_saved_bos(struct iris_context
*ice
,
3701 struct iris_batch
*batch
,
3702 const struct pipe_draw_info
*draw
)
3704 // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
3706 const uint64_t clean
= ~ice
->state
.dirty
;
3708 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
3709 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
3712 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3713 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
3716 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
3717 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
3720 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
3721 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
3724 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
3725 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
3728 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
3729 for (int i
= 0; i
< 4; i
++) {
3730 struct iris_stream_output_target
*tgt
=
3731 (void *) ice
->state
.so_target
[i
];
3733 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
3735 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
3741 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3742 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
3745 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3746 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3751 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3753 for (int i
= 0; i
< 4; i
++) {
3754 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3756 if (range
->length
== 0)
3759 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3760 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3763 iris_use_pinned_bo(batch
, res
->bo
, false);
3765 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3769 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3770 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
3771 /* Re-pin any buffers referred to by the binding table. */
3772 iris_populate_binding_table(ice
, batch
, stage
, true);
3776 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3777 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3778 struct pipe_resource
*res
= shs
->sampler_table
.res
;
3780 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
3783 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
3784 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
3785 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3787 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3788 iris_use_pinned_bo(batch
, bo
, false);
3791 // XXX: scratch buffer
3795 if (clean
& IRIS_DIRTY_DEPTH_BUFFER
) {
3796 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3798 if (cso_fb
->zsbuf
) {
3799 struct iris_resource
*zres
, *sres
;
3800 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
3802 // XXX: might not be writable...
3804 iris_use_pinned_bo(batch
, zres
->bo
, true);
3806 iris_use_pinned_bo(batch
, sres
->bo
, true);
3810 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
3811 /* This draw didn't emit a new index buffer, so we are inheriting the
3812 * older index buffer. This draw didn't need it, but future ones may.
3814 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
3815 iris_use_pinned_bo(batch
, bo
, false);
3818 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
3819 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
3820 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
3821 struct iris_resource
*res
= (void *) cso
->resources
[i
];
3822 iris_use_pinned_bo(batch
, res
->bo
, false);
3828 iris_restore_compute_saved_bos(struct iris_context
*ice
,
3829 struct iris_batch
*batch
,
3830 const struct pipe_grid_info
*grid
)
3832 const uint64_t clean
= ~ice
->state
.dirty
;
3834 const int stage
= MESA_SHADER_COMPUTE
;
3835 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
3837 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
3838 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3841 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
3842 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
3844 if (range
->length
> 0) {
3845 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
3846 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
3849 iris_use_pinned_bo(batch
, res
->bo
, false);
3851 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
3856 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
3857 /* Re-pin any buffers referred to by the binding table. */
3858 iris_populate_binding_table(ice
, batch
, stage
, true);
3861 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
3863 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
3865 if (clean
& IRIS_DIRTY_CS
) {
3866 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
3868 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
3869 iris_use_pinned_bo(batch
, bo
, false);
3872 // XXX: scratch buffer
3877 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
3880 iris_update_surface_base_address(struct iris_batch
*batch
,
3881 struct iris_binder
*binder
)
3883 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
3886 flush_for_state_base_change(batch
);
3888 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
3889 // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
3890 sba
.SurfaceStateBaseAddressModifyEnable
= true;
3891 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
3894 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
3898 iris_upload_dirty_render_state(struct iris_context
*ice
,
3899 struct iris_batch
*batch
,
3900 const struct pipe_draw_info
*draw
)
3902 const uint64_t dirty
= ice
->state
.dirty
;
3904 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
3907 struct iris_genx_state
*genx
= ice
->state
.genx
;
3908 struct iris_binder
*binder
= &ice
->state
.binder
;
3909 struct brw_wm_prog_data
*wm_prog_data
= (void *)
3910 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3912 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
3913 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3914 uint32_t cc_vp_address
;
3916 /* XXX: could avoid streaming for depth_clip [0,1] case. */
3917 uint32_t *cc_vp_map
=
3918 stream_state(batch
, ice
->state
.dynamic_uploader
,
3919 &ice
->state
.last_res
.cc_vp
,
3920 4 * ice
->state
.num_viewports
*
3921 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
3922 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3924 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
3925 cso_rast
->clip_halfz
, &zmin
, &zmax
);
3926 if (cso_rast
->depth_clip_near
)
3928 if (cso_rast
->depth_clip_far
)
3931 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
3932 ccv
.MinimumDepth
= zmin
;
3933 ccv
.MaximumDepth
= zmax
;
3936 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
3939 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
3940 ptr
.CCViewportPointer
= cc_vp_address
;
3944 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
3945 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3946 uint32_t sf_cl_vp_address
;
3948 stream_state(batch
, ice
->state
.dynamic_uploader
,
3949 &ice
->state
.last_res
.sf_cl_vp
,
3950 4 * ice
->state
.num_viewports
*
3951 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
3953 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
3954 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
3956 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
3957 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
3958 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
3959 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
3961 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
3962 vp
.ViewportMatrixElementm00
= state
->scale
[0];
3963 vp
.ViewportMatrixElementm11
= state
->scale
[1];
3964 vp
.ViewportMatrixElementm22
= state
->scale
[2];
3965 vp
.ViewportMatrixElementm30
= state
->translate
[0];
3966 vp
.ViewportMatrixElementm31
= state
->translate
[1];
3967 vp
.ViewportMatrixElementm32
= state
->translate
[2];
3968 /* XXX: in i965 this is computed based on the drawbuffer size,
3969 * but we don't have that here...
3971 vp
.XMinClipGuardband
= -1.0;
3972 vp
.XMaxClipGuardband
= 1.0;
3973 vp
.YMinClipGuardband
= -1.0;
3974 vp
.YMaxClipGuardband
= 1.0;
3975 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
3976 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
3977 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
3978 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
3981 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
3984 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
3985 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
3991 // XXX: this is only flagged at setup, we assume a static configuration
3992 if (dirty
& IRIS_DIRTY_URB
) {
3993 iris_upload_urb_config(ice
, batch
);
3996 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
3997 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
3998 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
3999 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4000 const int header_dwords
= GENX(BLEND_STATE_length
);
4001 const int rt_dwords
= cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
);
4002 uint32_t blend_offset
;
4003 uint32_t *blend_map
=
4004 stream_state(batch
, ice
->state
.dynamic_uploader
,
4005 &ice
->state
.last_res
.blend
,
4006 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4008 uint32_t blend_state_header
;
4009 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4010 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4011 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4014 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4015 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4017 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4018 ptr
.BlendStatePointer
= blend_offset
;
4019 ptr
.BlendStatePointerValid
= true;
4023 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4024 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4027 stream_state(batch
, ice
->state
.dynamic_uploader
,
4028 &ice
->state
.last_res
.color_calc
,
4029 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4031 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4032 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4033 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4034 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4035 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4036 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4037 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4039 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4040 ptr
.ColorCalcStatePointer
= cc_offset
;
4041 ptr
.ColorCalcStatePointerValid
= true;
4045 /* Upload constants for TCS passthrough. */
4046 if ((dirty
& IRIS_DIRTY_CONSTANTS_TCS
) &&
4047 ice
->shaders
.prog
[MESA_SHADER_TESS_CTRL
] &&
4048 !ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
]) {
4049 struct iris_compiled_shader
*tes_shader
= ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
4052 /* Passthrough always copies 2 vec4s, so when uploading data we ensure
4053 * it is in the right layout for TES.
4056 struct brw_tes_prog_data
*tes_prog_data
= (void *) tes_shader
->prog_data
;
4057 switch (tes_prog_data
->domain
) {
4058 case BRW_TESS_DOMAIN_QUAD
:
4059 for (int i
= 0; i
< 4; i
++)
4060 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4061 hdr
[3] = ice
->state
.default_inner_level
[0];
4062 hdr
[2] = ice
->state
.default_inner_level
[1];
4064 case BRW_TESS_DOMAIN_TRI
:
4065 for (int i
= 0; i
< 3; i
++)
4066 hdr
[7 - i
] = ice
->state
.default_outer_level
[i
];
4067 hdr
[4] = ice
->state
.default_inner_level
[0];
4069 case BRW_TESS_DOMAIN_ISOLINE
:
4070 hdr
[7] = ice
->state
.default_outer_level
[1];
4071 hdr
[6] = ice
->state
.default_outer_level
[0];
4075 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
4076 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[0];
4077 u_upload_data(ice
->ctx
.const_uploader
, 0, sizeof(hdr
), 32,
4078 &hdr
[0], &cbuf
->data
.offset
,
4082 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4083 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4086 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4087 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4092 if (shs
->cbuf0_needs_upload
)
4093 upload_uniforms(ice
, stage
);
4095 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4097 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4098 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4100 /* The Skylake PRM contains the following restriction:
4102 * "The driver must ensure The following case does not occur
4103 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4104 * buffer 3 read length equal to zero committed followed by a
4105 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4108 * To avoid this, we program the buffers in the highest slots.
4109 * This way, slot 0 is only used if slot 3 is also used.
4113 for (int i
= 3; i
>= 0; i
--) {
4114 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4116 if (range
->length
== 0)
4119 struct iris_const_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4120 struct iris_resource
*res
= (void *) cbuf
->data
.res
;
4122 assert(cbuf
->data
.offset
% 32 == 0);
4124 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4125 pkt
.ConstantBody
.Buffer
[n
] =
4126 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->data
.offset
)
4127 : ro_bo(batch
->screen
->workaround_bo
, 0);
4134 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4135 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4136 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4137 ptr
._3DCommandSubOpcode
= 38 + stage
;
4138 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4143 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4144 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4145 iris_populate_binding_table(ice
, batch
, stage
, false);
4149 if (ice
->state
.need_border_colors
)
4150 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4152 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4153 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4154 !ice
->shaders
.prog
[stage
])
4157 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4158 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4160 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4162 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4163 ptr
._3DCommandSubOpcode
= 43 + stage
;
4164 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4168 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4169 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4171 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4172 if (ice
->state
.framebuffer
.samples
> 0)
4173 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4177 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4178 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4179 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
4183 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4184 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4187 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4190 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4191 iris_use_pinned_bo(batch
, cache
->bo
, false);
4192 iris_batch_emit(batch
, shader
->derived_data
,
4193 iris_derived_program_state_size(stage
));
4195 if (stage
== MESA_SHADER_TESS_EVAL
) {
4196 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4197 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4198 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4199 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4200 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4205 if (ice
->state
.streamout_active
) {
4206 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4207 iris_batch_emit(batch
, genx
->so_buffers
,
4208 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4209 for (int i
= 0; i
< 4; i
++) {
4210 struct iris_stream_output_target
*tgt
=
4211 (void *) ice
->state
.so_target
[i
];
4213 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4215 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4221 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4222 uint32_t *decl_list
=
4223 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4224 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4227 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4228 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4230 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4231 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4232 sol
.SOFunctionEnable
= true;
4233 sol
.SOStatisticsEnable
= true;
4235 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4236 !ice
->state
.prims_generated_query_active
;
4237 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4240 assert(ice
->state
.streamout
);
4242 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4243 GENX(3DSTATE_STREAMOUT_length
));
4246 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4247 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4251 if (dirty
& IRIS_DIRTY_CLIP
) {
4252 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4253 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4255 bool reject
= cso_rast
->rasterizer_discard
&&
4256 ice
->state
.prims_generated_query_active
;
4258 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4259 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4260 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4261 cl
.ClipMode
= reject
? CLIPMODE_REJECT_ALL
: CLIPMODE_NORMAL
;
4262 if (wm_prog_data
->barycentric_interp_modes
&
4263 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4264 cl
.NonPerspectiveBarycentricEnable
= true;
4266 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4267 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4269 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4270 ARRAY_SIZE(cso_rast
->clip
));
4273 if (dirty
& IRIS_DIRTY_RASTER
) {
4274 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4275 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4276 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4280 /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
4281 if (dirty
& IRIS_DIRTY_WM
) {
4282 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4283 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4285 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4286 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4288 wm
.BarycentricInterpolationMode
=
4289 wm_prog_data
->barycentric_interp_modes
;
4291 if (wm_prog_data
->early_fragment_tests
)
4292 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4293 else if (wm_prog_data
->has_side_effects
)
4294 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4296 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4299 if (dirty
& IRIS_DIRTY_SBE
) {
4300 iris_emit_sbe(batch
, ice
);
4303 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4304 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4305 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4306 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4307 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4308 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
4309 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4312 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4313 ARRAY_SIZE(cso_blend
->ps_blend
));
4316 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4317 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4318 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4320 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4321 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4322 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4323 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4325 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4328 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4329 uint32_t scissor_offset
=
4330 emit_state(batch
, ice
->state
.dynamic_uploader
,
4331 &ice
->state
.last_res
.scissor
,
4332 ice
->state
.scissors
,
4333 sizeof(struct pipe_scissor_state
) *
4334 ice
->state
.num_viewports
, 32);
4336 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4337 ptr
.ScissorRectPointer
= scissor_offset
;
4341 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4342 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4343 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4345 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
4347 if (cso_fb
->zsbuf
) {
4348 struct iris_resource
*zres
, *sres
;
4349 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4351 // XXX: might not be writable...
4353 iris_use_pinned_bo(batch
, zres
->bo
, true);
4355 iris_use_pinned_bo(batch
, sres
->bo
, true);
4359 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4360 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4361 for (int i
= 0; i
< 32; i
++) {
4362 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4367 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4368 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4369 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4372 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4373 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4374 topo
.PrimitiveTopologyType
=
4375 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4379 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4380 struct iris_vertex_buffer_state
*cso
= &ice
->state
.genx
->vertex_buffers
;
4381 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
4383 if (cso
->num_buffers
> 0) {
4384 /* The VF cache designers cut corners, and made the cache key's
4385 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4386 * 32 bits of the address. If you have two vertex buffers which get
4387 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4388 * you can get collisions (even within a single batch).
4390 * So, we need to do a VF cache invalidate if the buffer for a VB
4391 * slot slot changes [48:32] address bits from the previous time.
4393 unsigned flush_flags
= 0;
4395 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
4396 uint16_t high_bits
= 0;
4398 struct iris_resource
*res
= (void *) cso
->resources
[i
];
4400 iris_use_pinned_bo(batch
, res
->bo
, false);
4402 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4403 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4404 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
4405 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
4408 /* If the buffer was written to by streamout, we may need
4409 * to stall so those writes land and become visible to the
4412 * TODO: This may stall more than necessary.
4414 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
4415 flush_flags
|= PIPE_CONTROL_CS_STALL
;
4420 iris_emit_pipe_control_flush(batch
, flush_flags
);
4422 iris_batch_emit(batch
, cso
->vertex_buffers
, sizeof(uint32_t) *
4423 (1 + vb_dwords
* cso
->num_buffers
));
4427 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
4428 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4429 const unsigned entries
= MAX2(cso
->count
, 1);
4430 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
4431 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
4432 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
4433 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
4436 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
4437 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
4438 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
4439 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
4441 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
4442 if (vs_prog_data
->uses_vertexid
) {
4443 sgv
.VertexIDEnable
= true;
4444 sgv
.VertexIDComponentNumber
= 2;
4445 sgv
.VertexIDElementOffset
= cso
->count
;
4448 if (vs_prog_data
->uses_instanceid
) {
4449 sgv
.InstanceIDEnable
= true;
4450 sgv
.InstanceIDComponentNumber
= 3;
4451 sgv
.InstanceIDElementOffset
= cso
->count
;
4456 if (dirty
& IRIS_DIRTY_VF
) {
4457 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
4458 if (draw
->primitive_restart
) {
4459 vf
.IndexedDrawCutIndexEnable
= true;
4460 vf
.CutIndex
= draw
->restart_index
;
4465 // XXX: Gen8 - PMA fix
4469 iris_upload_render_state(struct iris_context
*ice
,
4470 struct iris_batch
*batch
,
4471 const struct pipe_draw_info
*draw
)
4473 /* Always pin the binder. If we're emitting new binding table pointers,
4474 * we need it. If not, we're probably inheriting old tables via the
4475 * context, and need it anyway. Since true zero-bindings cases are
4476 * practically non-existent, just pin it and avoid last_res tracking.
4478 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
4480 if (!batch
->contains_draw
) {
4481 iris_restore_render_saved_bos(ice
, batch
, draw
);
4482 batch
->contains_draw
= true;
4485 iris_upload_dirty_render_state(ice
, batch
, draw
);
4487 if (draw
->index_size
> 0) {
4490 if (draw
->has_user_indices
) {
4491 u_upload_data(ice
->ctx
.stream_uploader
, 0,
4492 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
4493 &offset
, &ice
->state
.last_res
.index_buffer
);
4495 struct iris_resource
*res
= (void *) draw
->index
.resource
;
4496 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
4498 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
4499 draw
->index
.resource
);
4503 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4505 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
4506 ib
.IndexFormat
= draw
->index_size
>> 1;
4508 ib
.BufferSize
= bo
->size
;
4509 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
4512 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
4513 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
4514 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
4515 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
);
4516 ice
->state
.last_index_bo_high_bits
= high_bits
;
4520 #define _3DPRIM_END_OFFSET 0x2420
4521 #define _3DPRIM_START_VERTEX 0x2430
4522 #define _3DPRIM_VERTEX_COUNT 0x2434
4523 #define _3DPRIM_INSTANCE_COUNT 0x2438
4524 #define _3DPRIM_START_INSTANCE 0x243C
4525 #define _3DPRIM_BASE_VERTEX 0x2440
4527 if (draw
->indirect
) {
4528 /* We don't support this MultidrawIndirect. */
4529 assert(!draw
->indirect
->indirect_draw_count
);
4531 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
4534 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4535 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
4536 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
4538 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4539 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
4540 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
4542 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4543 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
4544 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
4546 if (draw
->index_size
) {
4547 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4548 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
4549 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4551 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4552 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4553 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
4556 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4557 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
4558 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
4560 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4561 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
4567 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
4568 prim
.StartInstanceLocation
= draw
->start_instance
;
4569 prim
.InstanceCount
= draw
->instance_count
;
4570 prim
.VertexCountPerInstance
= draw
->count
;
4571 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
4572 prim
.PredicateEnable
=
4573 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
4575 // XXX: this is probably bonkers.
4576 prim
.StartVertexLocation
= draw
->start
;
4578 prim
.IndirectParameterEnable
= draw
->indirect
!= NULL
;
4580 if (draw
->index_size
) {
4581 prim
.BaseVertexLocation
+= draw
->index_bias
;
4583 prim
.StartVertexLocation
+= draw
->index_bias
;
4586 //prim.BaseVertexLocation = ...;
4591 iris_upload_compute_state(struct iris_context
*ice
,
4592 struct iris_batch
*batch
,
4593 const struct pipe_grid_info
*grid
)
4595 const uint64_t dirty
= ice
->state
.dirty
;
4596 struct iris_screen
*screen
= batch
->screen
;
4597 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
4598 struct iris_binder
*binder
= &ice
->state
.binder
;
4599 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
4600 struct iris_compiled_shader
*shader
=
4601 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
4602 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4603 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
4605 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
4606 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
4608 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
4609 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
4611 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
4612 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
4614 if (ice
->state
.need_border_colors
)
4615 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4617 if (dirty
& IRIS_DIRTY_CS
) {
4618 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4620 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4621 * the only bits that are changed are scoreboard related: Scoreboard
4622 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
4623 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4626 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
4628 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4629 if (prog_data
->total_scratch
) {
4630 uint32_t scratch_addr
=
4631 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
4632 MESA_SHADER_COMPUTE
);
4633 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
4634 vfe
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
4637 vfe
.MaximumNumberofThreads
=
4638 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
4640 vfe
.ResetGatewayTimer
=
4641 Resettingrelativetimerandlatchingtheglobaltimestamp
;
4644 vfe
.NumberofURBEntries
= 2;
4645 vfe
.URBEntryAllocationSize
= 2;
4647 // XXX: Use Indirect Payload Storage?
4648 vfe
.CURBEAllocationSize
=
4649 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
4650 cs_prog_data
->push
.cross_thread
.regs
, 2);
4654 // XXX: hack iris_set_constant_buffers to upload these thread counts
4655 // XXX: along with regular uniforms for compute shaders, somehow.
4657 uint32_t curbe_data_offset
= 0;
4658 // TODO: Move subgroup-id into uniforms ubo so we can push uniforms
4659 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
4660 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
4661 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
4662 struct pipe_resource
*curbe_data_res
= NULL
;
4663 uint32_t *curbe_data_map
=
4664 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
4665 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
4666 &curbe_data_offset
);
4667 assert(curbe_data_map
);
4668 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
4669 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
4671 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
4672 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4673 curbe
.CURBETotalDataLength
=
4674 ALIGN(cs_prog_data
->push
.total
.size
, 64);
4675 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
4679 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
4680 IRIS_DIRTY_BINDINGS_CS
|
4681 IRIS_DIRTY_CONSTANTS_CS
|
4683 struct pipe_resource
*desc_res
= NULL
;
4684 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4686 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
4687 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
4688 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
4691 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
4692 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
4694 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
4695 load
.InterfaceDescriptorTotalLength
=
4696 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4697 load
.InterfaceDescriptorDataStartAddress
=
4698 emit_state(batch
, ice
->state
.dynamic_uploader
,
4699 &desc_res
, desc
, sizeof(desc
), 32);
4702 pipe_resource_reference(&desc_res
, NULL
);
4705 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
4706 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
4707 uint32_t right_mask
;
4710 right_mask
= ~0u >> (32 - remainder
);
4712 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
4714 #define GPGPU_DISPATCHDIMX 0x2500
4715 #define GPGPU_DISPATCHDIMY 0x2504
4716 #define GPGPU_DISPATCHDIMZ 0x2508
4718 if (grid
->indirect
) {
4719 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
4720 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
4721 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4722 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
4723 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
4725 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4726 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
4727 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
4729 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4730 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
4731 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
4735 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
4736 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
4737 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
4738 ggw
.ThreadDepthCounterMaximum
= 0;
4739 ggw
.ThreadHeightCounterMaximum
= 0;
4740 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
4741 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
4742 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
4743 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
4744 ggw
.RightExecutionMask
= right_mask
;
4745 ggw
.BottomExecutionMask
= 0xffffffff;
4748 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4750 if (!batch
->contains_draw
) {
4751 iris_restore_compute_saved_bos(ice
, batch
, grid
);
4752 batch
->contains_draw
= true;
4757 * State module teardown.
4760 iris_destroy_state(struct iris_context
*ice
)
4762 iris_free_vertex_buffers(&ice
->state
.genx
->vertex_buffers
);
4764 // XXX: unreference resources/surfaces.
4765 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
4766 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
4768 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
4770 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
4771 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4772 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
4774 free(ice
->state
.genx
);
4776 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
4778 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
4779 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
4780 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
4781 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
4782 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
4783 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
4786 /* ------------------------------------------------------------------- */
4789 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t src
,
4792 _iris_emit_lrr(batch
, src
, dst
);
4796 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t src
,
4799 _iris_emit_lrr(batch
, src
, dst
);
4800 _iris_emit_lrr(batch
, src
+ 4, dst
+ 4);
4804 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
4807 _iris_emit_lri(batch
, reg
, val
);
4811 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
4814 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
4815 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
4819 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
4822 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4823 struct iris_bo
*bo
, uint32_t offset
)
4825 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4826 lrm
.RegisterAddress
= reg
;
4827 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
4832 * Load a 64-bit value from a buffer into a MMIO register via
4833 * two MI_LOAD_REGISTER_MEM commands.
4836 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4837 struct iris_bo
*bo
, uint32_t offset
)
4839 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
4840 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
4844 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
4845 struct iris_bo
*bo
, uint32_t offset
,
4848 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4849 srm
.RegisterAddress
= reg
;
4850 srm
.MemoryAddress
= rw_bo(bo
, offset
);
4851 srm
.PredicateEnable
= predicated
;
4856 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
4857 struct iris_bo
*bo
, uint32_t offset
,
4860 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
4861 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
4865 iris_store_data_imm32(struct iris_batch
*batch
,
4866 struct iris_bo
*bo
, uint32_t offset
,
4869 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
4870 sdi
.Address
= rw_bo(bo
, offset
);
4871 sdi
.ImmediateData
= imm
;
4876 iris_store_data_imm64(struct iris_batch
*batch
,
4877 struct iris_bo
*bo
, uint32_t offset
,
4880 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
4881 * 2 in genxml but it's actually variable length and we need 5 DWords.
4883 void *map
= iris_get_command_space(batch
, 4 * 5);
4884 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
4885 sdi
.DWordLength
= 5 - 2;
4886 sdi
.Address
= rw_bo(bo
, offset
);
4887 sdi
.ImmediateData
= imm
;
4892 iris_copy_mem_mem(struct iris_batch
*batch
,
4893 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
4894 struct iris_bo
*src_bo
, uint32_t src_offset
,
4897 /* MI_COPY_MEM_MEM operates on DWords. */
4898 assert(bytes
% 4 == 0);
4899 assert(dst_offset
% 4 == 0);
4900 assert(src_offset
% 4 == 0);
4902 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
4903 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
4904 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
4905 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
4910 /* ------------------------------------------------------------------- */
4913 flags_to_post_sync_op(uint32_t flags
)
4915 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
4916 return WriteImmediateData
;
4918 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
4919 return WritePSDepthCount
;
4921 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
4922 return WriteTimestamp
;
4928 * Do the given flags have a Post Sync or LRI Post Sync operation?
4930 static enum pipe_control_flags
4931 get_post_sync_flags(enum pipe_control_flags flags
)
4933 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
4934 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
4935 PIPE_CONTROL_WRITE_TIMESTAMP
|
4936 PIPE_CONTROL_LRI_POST_SYNC_OP
;
4938 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
4939 * "LRI Post Sync Operation". So more than one bit set would be illegal.
4941 assert(util_bitcount(flags
) <= 1);
4946 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
4949 * Emit a series of PIPE_CONTROL commands, taking into account any
4950 * workarounds necessary to actually accomplish the caller's request.
4952 * Unless otherwise noted, spec quotations in this function come from:
4954 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
4955 * Restrictions for PIPE_CONTROL.
4957 * You should not use this function directly. Use the helpers in
4958 * iris_pipe_control.c instead, which may split the pipe control further.
4961 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
4962 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
4964 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
4965 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
4966 enum pipe_control_flags non_lri_post_sync_flags
=
4967 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
4969 /* Recursive PIPE_CONTROL workarounds --------------------------------
4970 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
4972 * We do these first because we want to look at the original operation,
4973 * rather than any workarounds we set.
4975 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
4976 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
4977 * lists several workarounds:
4979 * "Project: SKL, KBL, BXT
4981 * If the VF Cache Invalidation Enable is set to a 1 in a
4982 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
4983 * sets to 0, with the VF Cache Invalidation Enable set to 0
4984 * needs to be sent prior to the PIPE_CONTROL with VF Cache
4985 * Invalidation Enable set to a 1."
4987 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
4990 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
4991 /* Project: SKL / Argument: LRI Post Sync Operation [23]
4993 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
4994 * programmed prior to programming a PIPECONTROL command with "LRI
4995 * Post Sync Operation" in GPGPU mode of operation (i.e when
4996 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
4998 * The same text exists a few rows below for Post Sync Op.
5000 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5003 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5005 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5006 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5007 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5009 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5013 /* "Flush Types" workarounds ---------------------------------------------
5014 * We do these now because they may add post-sync operations or CS stalls.
5017 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5018 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5020 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5021 * 'Write PS Depth Count' or 'Write Timestamp'."
5024 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5025 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5026 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5027 bo
= batch
->screen
->workaround_bo
;
5031 /* #1130 from Gen10 workarounds page:
5033 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5034 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5035 * board stall if Render target cache flush is enabled."
5037 * Applicable to CNL B0 and C0 steppings only.
5039 * The wording here is unclear, and this workaround doesn't look anything
5040 * like the internal bug report recommendations, but leave it be for now...
5042 if (GEN_GEN
== 10) {
5043 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5044 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5045 } else if (flags
& non_lri_post_sync_flags
) {
5046 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5050 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5051 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5053 * "This bit must be DISABLED for operations other than writing
5056 * This seems like nonsense. An Ivybridge workaround requires us to
5057 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5058 * operation. Gen8+ requires us to emit depth stalls and depth cache
5059 * flushes together. So, it's hard to imagine this means anything other
5060 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5062 * We ignore the supposed restriction and do nothing.
5066 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5067 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5068 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5070 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5071 * PS_DEPTH_COUNT or TIMESTAMP queries."
5073 * TODO: Implement end-of-pipe checking.
5075 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5076 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5079 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5080 /* From the PIPE_CONTROL instruction table, bit 1:
5082 * "This bit is ignored if Depth Stall Enable is set.
5083 * Further, the render cache is not flushed even if Write Cache
5084 * Flush Enable bit is set."
5086 * We assert that the caller doesn't do this combination, to try and
5087 * prevent mistakes. It shouldn't hurt the GPU, though.
5089 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5090 * and "Render Target Flush" combo is explicitly required for BTI
5091 * update workarounds.
5093 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5094 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5097 /* PIPE_CONTROL page workarounds ------------------------------------- */
5099 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5100 /* From the PIPE_CONTROL page itself:
5103 * Restriction: Pipe_control with CS-stall bit set must be issued
5104 * before a pipe-control command that has the State Cache
5105 * Invalidate bit set."
5107 flags
|= PIPE_CONTROL_CS_STALL
;
5110 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5111 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5114 * SW must always program Post-Sync Operation to "Write Immediate
5115 * Data" when Flush LLC is set."
5117 * For now, we just require the caller to do it.
5119 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5122 /* "Post-Sync Operation" workarounds -------------------------------- */
5124 /* Project: All / Argument: Global Snapshot Count Reset [19]
5126 * "This bit must not be exercised on any product.
5127 * Requires stall bit ([20] of DW1) set."
5129 * We don't use this, so we just assert that it isn't used. The
5130 * PIPE_CONTROL instruction page indicates that they intended this
5131 * as a debug feature and don't think it is useful in production,
5132 * but it may actually be usable, should we ever want to.
5134 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
5136 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
5137 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
5138 /* Project: All / Arguments:
5140 * - Generic Media State Clear [16]
5141 * - Indirect State Pointers Disable [16]
5143 * "Requires stall bit ([20] of DW1) set."
5145 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
5146 * State Clear) says:
5148 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5149 * programmed prior to programming a PIPECONTROL command with "Media
5150 * State Clear" set in GPGPU mode of operation"
5152 * This is a subset of the earlier rule, so there's nothing to do.
5154 flags
|= PIPE_CONTROL_CS_STALL
;
5157 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
5158 /* Project: All / Argument: Store Data Index
5160 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5163 * For now, we just assert that the caller does this. We might want to
5164 * automatically add a write to the workaround BO...
5166 assert(non_lri_post_sync_flags
!= 0);
5169 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
5170 /* Project: All / Argument: Sync GFDT
5172 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
5173 * than '0' or 0x2520[13] must be set."
5175 * For now, we just assert that the caller does this.
5177 assert(non_lri_post_sync_flags
!= 0);
5180 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
5181 /* Project: IVB+ / Argument: TLB inv
5183 * "Requires stall bit ([20] of DW1) set."
5185 * Also, from the PIPE_CONTROL instruction table:
5188 * Post Sync Operation or CS stall must be set to ensure a TLB
5189 * invalidation occurs. Otherwise no cycle will occur to the TLB
5190 * cache to invalidate."
5192 * This is not a subset of the earlier rule, so there's nothing to do.
5194 flags
|= PIPE_CONTROL_CS_STALL
;
5197 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
5198 /* TODO: The big Skylake GT4 post sync op workaround */
5201 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
5203 if (IS_COMPUTE_PIPELINE(batch
)) {
5204 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
5205 /* Project: SKL+ / Argument: Tex Invalidate
5206 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
5208 flags
|= PIPE_CONTROL_CS_STALL
;
5211 if (GEN_GEN
== 8 && (post_sync_flags
||
5212 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
5213 PIPE_CONTROL_DEPTH_STALL
|
5214 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5215 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5216 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
5217 /* Project: BDW / Arguments:
5219 * - LRI Post Sync Operation [23]
5220 * - Post Sync Op [15:14]
5222 * - Depth Stall [13]
5223 * - Render Target Cache Flush [12]
5224 * - Depth Cache Flush [0]
5225 * - DC Flush Enable [5]
5227 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
5230 flags
|= PIPE_CONTROL_CS_STALL
;
5232 /* Also, from the PIPE_CONTROL instruction table, bit 20:
5235 * This bit must be always set when PIPE_CONTROL command is
5236 * programmed by GPGPU and MEDIA workloads, except for the cases
5237 * when only Read Only Cache Invalidation bits are set (State
5238 * Cache Invalidation Enable, Instruction cache Invalidation
5239 * Enable, Texture Cache Invalidation Enable, Constant Cache
5240 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
5241 * need not implemented when FF_DOP_CG is disable via "Fixed
5242 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
5244 * It sounds like we could avoid CS stalls in some cases, but we
5245 * don't currently bother. This list isn't exactly the list above,
5251 /* "Stall" workarounds ----------------------------------------------
5252 * These have to come after the earlier ones because we may have added
5253 * some additional CS stalls above.
5256 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
5257 /* Project: PRE-SKL, VLV, CHV
5259 * "[All Stepping][All SKUs]:
5261 * One of the following must also be set:
5263 * - Render Target Cache Flush Enable ([12] of DW1)
5264 * - Depth Cache Flush Enable ([0] of DW1)
5265 * - Stall at Pixel Scoreboard ([1] of DW1)
5266 * - Depth Stall ([13] of DW1)
5267 * - Post-Sync Operation ([13] of DW1)
5268 * - DC Flush Enable ([5] of DW1)"
5270 * If we don't already have one of those bits set, we choose to add
5271 * "Stall at Pixel Scoreboard". Some of the other bits require a
5272 * CS stall as a workaround (see above), which would send us into
5273 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
5274 * appears to be safe, so we choose that.
5276 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5277 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
5278 PIPE_CONTROL_WRITE_IMMEDIATE
|
5279 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5280 PIPE_CONTROL_WRITE_TIMESTAMP
|
5281 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
5282 PIPE_CONTROL_DEPTH_STALL
|
5283 PIPE_CONTROL_DATA_CACHE_FLUSH
;
5284 if (!(flags
& wa_bits
))
5285 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5288 /* Emit --------------------------------------------------------------- */
5290 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
5291 pc
.LRIPostSyncOperation
= NoLRIOperation
;
5292 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
5293 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
5294 pc
.StoreDataIndex
= 0;
5295 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
5296 pc
.GlobalSnapshotCountReset
=
5297 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
5298 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
5299 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
5300 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5301 pc
.RenderTargetCacheFlushEnable
=
5302 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
5303 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
5304 pc
.StateCacheInvalidationEnable
=
5305 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
5306 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
5307 pc
.ConstantCacheInvalidationEnable
=
5308 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
5309 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
5310 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
5311 pc
.InstructionCacheInvalidateEnable
=
5312 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
5313 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
5314 pc
.IndirectStatePointersDisable
=
5315 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
5316 pc
.TextureCacheInvalidationEnable
=
5317 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
5318 pc
.Address
= rw_bo(bo
, offset
);
5319 pc
.ImmediateData
= imm
;
5324 genX(init_state
)(struct iris_context
*ice
)
5326 struct pipe_context
*ctx
= &ice
->ctx
;
5327 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
5329 ctx
->create_blend_state
= iris_create_blend_state
;
5330 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
5331 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
5332 ctx
->create_sampler_state
= iris_create_sampler_state
;
5333 ctx
->create_sampler_view
= iris_create_sampler_view
;
5334 ctx
->create_surface
= iris_create_surface
;
5335 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
5336 ctx
->bind_blend_state
= iris_bind_blend_state
;
5337 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
5338 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
5339 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
5340 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
5341 ctx
->delete_blend_state
= iris_delete_state
;
5342 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
5343 ctx
->delete_rasterizer_state
= iris_delete_state
;
5344 ctx
->delete_sampler_state
= iris_delete_state
;
5345 ctx
->delete_vertex_elements_state
= iris_delete_state
;
5346 ctx
->set_blend_color
= iris_set_blend_color
;
5347 ctx
->set_clip_state
= iris_set_clip_state
;
5348 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
5349 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
5350 ctx
->set_shader_images
= iris_set_shader_images
;
5351 ctx
->set_sampler_views
= iris_set_sampler_views
;
5352 ctx
->set_tess_state
= iris_set_tess_state
;
5353 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
5354 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
5355 ctx
->set_sample_mask
= iris_set_sample_mask
;
5356 ctx
->set_scissor_states
= iris_set_scissor_states
;
5357 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
5358 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
5359 ctx
->set_viewport_states
= iris_set_viewport_states
;
5360 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
5361 ctx
->surface_destroy
= iris_surface_destroy
;
5362 ctx
->draw_vbo
= iris_draw_vbo
;
5363 ctx
->launch_grid
= iris_launch_grid
;
5364 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
5365 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
5366 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
5368 ice
->vtbl
.destroy_state
= iris_destroy_state
;
5369 ice
->vtbl
.init_render_context
= iris_init_render_context
;
5370 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
5371 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
5372 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
5373 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
5374 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
5375 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
5376 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
5377 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
5378 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
5379 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
5380 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
5381 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
5382 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
5383 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
5384 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
5385 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
5386 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
5387 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
5388 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
5389 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
5390 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
5391 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
5392 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
5393 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
5394 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
5396 ice
->state
.dirty
= ~0ull;
5398 ice
->state
.statistics_counters_enabled
= true;
5400 ice
->state
.sample_mask
= 0xffff;
5401 ice
->state
.num_viewports
= 1;
5402 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
5404 /* Make a 1x1x1 null surface for unbound textures */
5405 void *null_surf_map
=
5406 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
5407 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
5408 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
5409 ice
->state
.unbound_tex
.offset
+=
5410 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
5412 /* Default all scissor rectangles to be empty regions. */
5413 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
5414 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
5415 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,