2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
35 #include "pipe/p_defines.h"
36 #include "pipe/p_state.h"
37 #include "pipe/p_context.h"
38 #include "pipe/p_screen.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_transfer.h"
42 #include "util/u_upload_mgr.h"
45 #include "intel/compiler/brw_compiler.h"
46 #include "intel/common/gen_l3_config.h"
47 #include "intel/common/gen_sample_positions.h"
48 #include "iris_batch.h"
49 #include "iris_context.h"
50 #include "iris_pipe.h"
51 #include "iris_resource.h"
53 #define __gen_address_type struct iris_address
54 #define __gen_user_data struct iris_batch
56 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
59 __gen_combine_address(struct iris_batch
*batch
, void *location
,
60 struct iris_address addr
, uint32_t delta
)
62 uint64_t result
= addr
.offset
+ delta
;
65 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
66 /* Assume this is a general address, not relative to a base. */
67 result
+= addr
.bo
->gtt_offset
;
73 #define __genxml_cmd_length(cmd) cmd ## _length
74 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
75 #define __genxml_cmd_header(cmd) cmd ## _header
76 #define __genxml_cmd_pack(cmd) cmd ## _pack
78 #define _iris_pack_command(batch, cmd, dst, name) \
79 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
80 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
81 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
85 #define iris_pack_command(cmd, dst, name) \
86 _iris_pack_command(NULL, cmd, dst, name)
88 #define iris_pack_state(cmd, dst, name) \
89 for (struct cmd name = {}, \
90 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
91 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
94 #define iris_emit_cmd(batch, cmd, name) \
95 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
97 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
99 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
100 for (uint32_t i = 0; i < num_dwords; i++) \
101 dw[i] = (dwords0)[i] | (dwords1)[i]; \
102 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
105 #include "genxml/genX_pack.h"
106 #include "genxml/gen_macros.h"
107 #include "genxml/genX_bits.h"
109 #define MOCS_WB (2 << 1)
111 UNUSED
static void pipe_asserts()
113 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
115 /* pipe_logicop happens to match the hardware. */
116 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
117 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
118 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
119 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
120 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
121 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
122 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
123 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
124 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
125 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
126 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
127 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
128 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
129 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
130 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
131 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
133 /* pipe_blend_func happens to match the hardware. */
134 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
135 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
136 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
137 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
138 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
139 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
140 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
141 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
142 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
143 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
144 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
145 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
146 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
147 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
148 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
149 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
150 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
151 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
152 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
154 /* pipe_blend_func happens to match the hardware. */
155 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
156 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
157 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
158 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
159 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
161 /* pipe_stencil_op happens to match the hardware. */
162 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
163 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
164 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
165 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
166 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
167 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
168 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
169 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
171 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
172 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
173 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
178 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
180 static const unsigned map
[] = {
181 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
182 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
183 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
184 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
185 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
186 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
187 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
188 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
189 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
190 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
191 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
192 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
193 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
194 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
195 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
198 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
202 translate_compare_func(enum pipe_compare_func pipe_func
)
204 static const unsigned map
[] = {
205 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
206 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
207 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
208 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
209 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
210 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
211 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
212 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
214 return map
[pipe_func
];
218 translate_shadow_func(enum pipe_compare_func pipe_func
)
220 /* Gallium specifies the result of shadow comparisons as:
222 * 1 if ref <op> texel,
227 * 0 if texel <op> ref,
230 * So we need to flip the operator and also negate.
232 static const unsigned map
[] = {
233 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
234 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
235 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
236 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
237 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
238 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
239 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
240 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
242 return map
[pipe_func
];
246 translate_cull_mode(unsigned pipe_face
)
248 static const unsigned map
[4] = {
249 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
250 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
251 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
252 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
254 return map
[pipe_face
];
258 translate_fill_mode(unsigned pipe_polymode
)
260 static const unsigned map
[4] = {
261 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
262 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
263 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
264 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
266 return map
[pipe_polymode
];
269 static struct iris_address
270 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
273 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
277 stream_state(struct iris_batch
*batch
,
278 struct u_upload_mgr
*uploader
,
281 uint32_t *out_offset
)
283 struct pipe_resource
*res
= NULL
;
286 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, &res
, &ptr
);
288 struct iris_bo
*bo
= iris_resource_bo(res
);
289 iris_use_pinned_bo(batch
, bo
, false);
291 *out_offset
+= iris_bo_offset_from_base_address(bo
);
293 pipe_resource_reference(&res
, NULL
);
299 emit_state(struct iris_batch
*batch
,
300 struct u_upload_mgr
*uploader
,
306 uint32_t *map
= stream_state(batch
, uploader
, size
, alignment
, &offset
);
309 memcpy(map
, data
, size
);
315 iris_init_render_context(struct iris_screen
*screen
,
316 struct iris_batch
*batch
,
317 struct iris_vtable
*vtbl
,
318 struct pipe_debug_callback
*dbg
)
320 iris_init_batch(batch
, screen
, vtbl
, dbg
, I915_EXEC_RENDER
);
322 /* XXX: PIPE_CONTROLs */
324 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
326 // XXX: MOCS is stupid for this.
327 sba
.GeneralStateMemoryObjectControlState
= MOCS_WB
;
328 sba
.StatelessDataPortAccessMemoryObjectControlState
= MOCS_WB
;
329 sba
.SurfaceStateMemoryObjectControlState
= MOCS_WB
;
330 sba
.DynamicStateMemoryObjectControlState
= MOCS_WB
;
331 sba
.IndirectObjectMemoryObjectControlState
= MOCS_WB
;
332 sba
.InstructionMemoryObjectControlState
= MOCS_WB
;
333 sba
.BindlessSurfaceStateMemoryObjectControlState
= MOCS_WB
;
336 sba
.GeneralStateBaseAddressModifyEnable
= true;
337 sba
.SurfaceStateBaseAddressModifyEnable
= true;
338 sba
.DynamicStateBaseAddressModifyEnable
= true;
339 sba
.IndirectObjectBaseAddressModifyEnable
= true;
340 sba
.InstructionBaseAddressModifyEnable
= true;
341 sba
.GeneralStateBufferSizeModifyEnable
= true;
342 sba
.DynamicStateBufferSizeModifyEnable
= true;
343 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
344 sba
.IndirectObjectBufferSizeModifyEnable
= true;
345 sba
.InstructionBuffersizeModifyEnable
= true;
347 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
348 sba
.SurfaceStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SURFACE_START
);
349 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
351 sba
.GeneralStateBufferSize
= 0xfffff;
352 sba
.IndirectObjectBufferSize
= 0xfffff;
353 sba
.InstructionBufferSize
= 0xfffff;
354 sba
.DynamicStateBufferSize
= 0xfffff;
357 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
358 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
359 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
361 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
362 GEN_SAMPLE_POS_1X(pat
._1xSample
);
363 GEN_SAMPLE_POS_2X(pat
._2xSample
);
364 GEN_SAMPLE_POS_4X(pat
._4xSample
);
365 GEN_SAMPLE_POS_8X(pat
._8xSample
);
366 GEN_SAMPLE_POS_16X(pat
._16xSample
);
368 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
369 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
370 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
371 /* XXX: may need to set an offset for origin-UL framebuffers */
372 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
374 /* Just assign a static partitioning. */
375 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
376 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
377 alloc
._3DCommandSubOpcode
= 18 + i
;
378 alloc
.ConstantBufferOffset
= 6 * i
;
379 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
385 iris_launch_grid(struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
390 iris_set_blend_color(struct pipe_context
*ctx
,
391 const struct pipe_blend_color
*state
)
393 struct iris_context
*ice
= (struct iris_context
*) ctx
;
395 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
396 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
399 struct iris_blend_state
{
400 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
401 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
402 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
404 bool alpha_to_coverage
; /* for shader key */
408 iris_create_blend_state(struct pipe_context
*ctx
,
409 const struct pipe_blend_state
*state
)
411 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
412 uint32_t *blend_state
= cso
->blend_state
;
414 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
416 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
417 /* pb.HasWriteableRT is filled in at draw time. */
418 /* pb.AlphaTestEnable is filled in at draw time. */
419 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
420 pb
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
422 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
424 pb
.SourceBlendFactor
= state
->rt
[0].rgb_src_factor
;
425 pb
.SourceAlphaBlendFactor
= state
->rt
[0].alpha_func
;
426 pb
.DestinationBlendFactor
= state
->rt
[0].rgb_dst_factor
;
427 pb
.DestinationAlphaBlendFactor
= state
->rt
[0].alpha_dst_factor
;
430 iris_pack_state(GENX(BLEND_STATE
), blend_state
, bs
) {
431 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
432 bs
.IndependentAlphaBlendEnable
= state
->independent_blend_enable
;
433 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
434 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
435 bs
.ColorDitherEnable
= state
->dither
;
436 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
439 blend_state
+= GENX(BLEND_STATE_length
);
441 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
442 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_state
, be
) {
443 be
.LogicOpEnable
= state
->logicop_enable
;
444 be
.LogicOpFunction
= state
->logicop_func
;
446 be
.PreBlendSourceOnlyClampEnable
= false;
447 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
448 be
.PreBlendColorClampEnable
= true;
449 be
.PostBlendColorClampEnable
= true;
451 be
.ColorBufferBlendEnable
= state
->rt
[i
].blend_enable
;
453 be
.ColorBlendFunction
= state
->rt
[i
].rgb_func
;
454 be
.AlphaBlendFunction
= state
->rt
[i
].alpha_func
;
455 be
.SourceBlendFactor
= state
->rt
[i
].rgb_src_factor
;
456 be
.SourceAlphaBlendFactor
= state
->rt
[i
].alpha_func
;
457 be
.DestinationBlendFactor
= state
->rt
[i
].rgb_dst_factor
;
458 be
.DestinationAlphaBlendFactor
= state
->rt
[i
].alpha_dst_factor
;
460 be
.WriteDisableRed
= !(state
->rt
[i
].colormask
& PIPE_MASK_R
);
461 be
.WriteDisableGreen
= !(state
->rt
[i
].colormask
& PIPE_MASK_G
);
462 be
.WriteDisableBlue
= !(state
->rt
[i
].colormask
& PIPE_MASK_B
);
463 be
.WriteDisableAlpha
= !(state
->rt
[i
].colormask
& PIPE_MASK_A
);
465 blend_state
+= GENX(BLEND_STATE_ENTRY_length
);
472 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
474 struct iris_context
*ice
= (struct iris_context
*) ctx
;
475 ice
->state
.cso_blend
= state
;
476 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
477 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
480 struct iris_depth_stencil_alpha_state
{
481 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
482 uint32_t cc_vp
[GENX(CC_VIEWPORT_length
)];
484 struct pipe_alpha_state alpha
; /* to BLEND_STATE, 3DSTATE_PS_BLEND */
488 iris_create_zsa_state(struct pipe_context
*ctx
,
489 const struct pipe_depth_stencil_alpha_state
*state
)
491 struct iris_depth_stencil_alpha_state
*cso
=
492 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
494 cso
->alpha
= state
->alpha
;
496 bool two_sided_stencil
= state
->stencil
[1].enabled
;
498 /* The state tracker needs to optimize away EQUAL writes for us. */
499 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
501 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
502 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
503 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
504 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
505 wmds
.StencilTestFunction
=
506 translate_compare_func(state
->stencil
[0].func
);
507 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
508 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
509 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
510 wmds
.BackfaceStencilTestFunction
=
511 translate_compare_func(state
->stencil
[1].func
);
512 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
513 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
514 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
515 wmds
.StencilBufferWriteEnable
=
516 state
->stencil
[0].writemask
!= 0 ||
517 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
518 wmds
.DepthTestEnable
= state
->depth
.enabled
;
519 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
520 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
521 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
522 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
523 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
524 /* wmds.[Backface]StencilReferenceValue are merged later */
527 iris_pack_state(GENX(CC_VIEWPORT
), cso
->cc_vp
, ccvp
) {
528 ccvp
.MinimumDepth
= state
->depth
.bounds_min
;
529 ccvp
.MaximumDepth
= state
->depth
.bounds_max
;
536 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
538 struct iris_context
*ice
= (struct iris_context
*) ctx
;
539 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
540 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
543 if (!old_cso
|| old_cso
->alpha
.ref_value
!= new_cso
->alpha
.ref_value
) {
544 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
548 ice
->state
.cso_zsa
= new_cso
;
549 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
550 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
553 struct iris_rasterizer_state
{
554 uint32_t sf
[GENX(3DSTATE_SF_length
)];
555 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
556 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
557 uint32_t wm
[GENX(3DSTATE_WM_length
)];
558 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
560 bool flatshade
; /* for shader state */
561 bool clamp_fragment_color
; /* for shader state */
562 bool light_twoside
; /* for shader state */
563 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT */
564 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
565 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
566 uint16_t sprite_coord_enable
;
570 iris_create_rasterizer_state(struct pipe_context
*ctx
,
571 const struct pipe_rasterizer_state
*state
)
573 struct iris_rasterizer_state
*cso
=
574 malloc(sizeof(struct iris_rasterizer_state
));
577 point_quad_rasterization
-> SBE
?
582 force_persample_interp
- ?
585 offset_units_unscaled
- cap
not exposed
589 cso
->flatshade
= state
->flatshade
;
590 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
591 cso
->light_twoside
= state
->light_twoside
;
592 cso
->rasterizer_discard
= state
->rasterizer_discard
;
593 cso
->half_pixel_center
= state
->half_pixel_center
;
594 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
595 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
597 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
598 sf
.StatisticsEnable
= true;
599 sf
.ViewportTransformEnable
= true;
600 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
601 sf
.LineEndCapAntialiasingRegionWidth
=
602 state
->line_smooth
? _10pixels
: _05pixels
;
603 sf
.LastPixelEnable
= state
->line_last_pixel
;
604 sf
.LineWidth
= state
->line_width
;
605 sf
.SmoothPointEnable
= state
->point_smooth
;
606 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
607 sf
.PointWidth
= state
->point_size
;
609 if (state
->flatshade_first
) {
610 sf
.TriangleStripListProvokingVertexSelect
= 2;
611 sf
.TriangleFanProvokingVertexSelect
= 2;
612 sf
.LineStripListProvokingVertexSelect
= 1;
614 sf
.TriangleFanProvokingVertexSelect
= 1;
619 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
620 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
621 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
622 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
623 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
624 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
625 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
626 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
627 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
628 rr
.GlobalDepthOffsetConstant
= state
->offset_units
;
629 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
630 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
631 rr
.SmoothPointEnable
= state
->point_smooth
;
632 rr
.AntialiasingEnable
= state
->line_smooth
;
633 rr
.ScissorRectangleEnable
= state
->scissor
;
634 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
635 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
636 //rr.ConservativeRasterizationEnable = not yet supported by Gallium...
639 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
640 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
641 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
643 cl
.StatisticsEnable
= true;
644 cl
.EarlyCullEnable
= true;
645 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
646 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
647 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
648 cl
.GuardbandClipTestEnable
= true;
649 cl
.ClipMode
= CLIPMODE_NORMAL
;
650 cl
.ClipEnable
= true;
651 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
652 cl
.MinimumPointWidth
= 0.125;
653 cl
.MaximumPointWidth
= 255.875;
655 if (state
->flatshade_first
) {
656 cl
.TriangleStripListProvokingVertexSelect
= 2;
657 cl
.TriangleFanProvokingVertexSelect
= 2;
658 cl
.LineStripListProvokingVertexSelect
= 1;
660 cl
.TriangleFanProvokingVertexSelect
= 1;
664 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
665 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
666 * filled in at draw time from the FS program.
668 wm
.LineAntialiasingRegionWidth
= _10pixels
;
669 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
670 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
671 wm
.StatisticsEnable
= true;
672 wm
.LineStippleEnable
= state
->line_stipple_enable
;
673 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
676 /* Remap from 0..255 back to 1..256 */
677 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
679 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
680 line
.LineStipplePattern
= state
->line_stipple_pattern
;
681 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
682 line
.LineStippleRepeatCount
= line_stipple_factor
;
689 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
691 struct iris_context
*ice
= (struct iris_context
*) ctx
;
692 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
693 struct iris_rasterizer_state
*new_cso
= state
;
696 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
697 if (!old_cso
|| memcmp(old_cso
->line_stipple
, new_cso
->line_stipple
,
698 sizeof(old_cso
->line_stipple
)) != 0) {
699 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
703 old_cso
->half_pixel_center
!= new_cso
->half_pixel_center
) {
704 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
708 ice
->state
.cso_rast
= new_cso
;
709 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
713 translate_wrap(unsigned pipe_wrap
)
715 static const unsigned map
[] = {
716 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
717 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
718 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
719 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
720 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
721 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
722 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1, // XXX: ???
723 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1, // XXX: ???
725 return map
[pipe_wrap
];
729 * Return true if the given wrap mode requires the border color to exist.
732 wrap_mode_needs_border_color(unsigned wrap_mode
)
734 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
738 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
740 static const unsigned map
[] = {
741 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
742 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
743 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
745 return map
[pipe_mip
];
748 struct iris_sampler_state
{
749 struct pipe_sampler_state base
;
751 bool needs_border_color
;
753 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
757 iris_create_sampler_state(struct pipe_context
*pctx
,
758 const struct pipe_sampler_state
*state
)
760 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
765 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
766 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
768 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
769 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
770 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
772 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
773 wrap_mode_needs_border_color(wrap_t
) ||
774 wrap_mode_needs_border_color(wrap_r
);
776 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
777 samp
.TCXAddressControlMode
= wrap_s
;
778 samp
.TCYAddressControlMode
= wrap_t
;
779 samp
.TCZAddressControlMode
= wrap_r
;
780 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
781 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
782 samp
.MinModeFilter
= state
->min_img_filter
;
783 samp
.MagModeFilter
= state
->mag_img_filter
;
784 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
785 samp
.MaximumAnisotropy
= RATIO21
;
787 if (state
->max_anisotropy
>= 2) {
788 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
789 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
790 samp
.AnisotropicAlgorithm
= EWAApproximation
;
793 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
794 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
796 samp
.MaximumAnisotropy
=
797 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
800 /* Set address rounding bits if not using nearest filtering. */
801 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
802 samp
.UAddressMinFilterRoundingEnable
= true;
803 samp
.VAddressMinFilterRoundingEnable
= true;
804 samp
.RAddressMinFilterRoundingEnable
= true;
807 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
808 samp
.UAddressMagFilterRoundingEnable
= true;
809 samp
.VAddressMagFilterRoundingEnable
= true;
810 samp
.RAddressMagFilterRoundingEnable
= true;
813 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
814 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
816 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
818 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
819 samp
.MinLOD
= CLAMP(state
->min_lod
, 0, hw_max_lod
);
820 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
821 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
823 //samp.BorderColorPointer = <<comes from elsewhere>>
830 iris_bind_sampler_states(struct pipe_context
*ctx
,
831 enum pipe_shader_type p_stage
,
832 unsigned start
, unsigned count
,
835 struct iris_context
*ice
= (struct iris_context
*) ctx
;
836 gl_shader_stage stage
= stage_from_pipe(p_stage
);
838 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
840 /* Assemble the SAMPLER_STATEs into a contiguous chunk of memory
841 * relative to Dynamic State Base Address.
844 u_upload_alloc(ice
->state
.dynamic_uploader
, 0,
845 count
* 4 * GENX(SAMPLER_STATE_length
), 32,
846 &ice
->state
.sampler_table_offset
[stage
],
847 &ice
->state
.sampler_table_resource
[stage
],
852 struct pipe_resource
*res
= ice
->state
.sampler_table_resource
[stage
];
853 ice
->state
.sampler_table_offset
[stage
] +=
854 iris_bo_offset_from_base_address(iris_resource_bo(res
));
856 for (int i
= 0; i
< count
; i
++) {
857 struct iris_sampler_state
*state
= states
[i
];
859 /* Save a pointer to the iris_sampler_state, a few fields need
860 * to inform draw-time decisions.
862 ice
->state
.samplers
[stage
][start
+ i
] = state
;
865 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
867 map
+= GENX(SAMPLER_STATE_length
);
870 ice
->state
.num_samplers
[stage
] = count
;
872 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
875 struct iris_sampler_view
{
876 struct pipe_sampler_view pipe
;
877 struct isl_view view
;
879 /** The resource (BO) holding our SURFACE_STATE. */
880 struct pipe_resource
*surface_state_resource
;
881 unsigned surface_state_offset
;
883 //uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
887 * Convert an swizzle enumeration (i.e. PIPE_SWIZZLE_X) to one of the Gen7.5+
888 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
890 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
893 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
895 * which is simply adding 4 then modding by 8 (or anding with 7).
897 * We then may need to apply workarounds for textureGather hardware bugs.
899 static enum isl_channel_select
900 pipe_swizzle_to_isl_channel(enum pipe_swizzle swizzle
)
902 return (swizzle
+ 4) & 7;
905 static struct pipe_sampler_view
*
906 iris_create_sampler_view(struct pipe_context
*ctx
,
907 struct pipe_resource
*tex
,
908 const struct pipe_sampler_view
*tmpl
)
910 struct iris_context
*ice
= (struct iris_context
*) ctx
;
911 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
912 struct iris_resource
*itex
= (struct iris_resource
*) tex
;
913 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
918 /* initialize base object */
920 isv
->pipe
.context
= ctx
;
921 isv
->pipe
.texture
= NULL
;
922 pipe_reference_init(&isv
->pipe
.reference
, 1);
923 pipe_resource_reference(&isv
->pipe
.texture
, tex
);
925 /* XXX: do we need brw_get_texture_swizzle hacks here? */
927 isv
->view
= (struct isl_view
) {
928 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
929 .base_level
= tmpl
->u
.tex
.first_level
,
930 .levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1,
931 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
932 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
933 .swizzle
= (struct isl_swizzle
) {
934 .r
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_r
),
935 .g
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_g
),
936 .b
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_b
),
937 .a
= pipe_swizzle_to_isl_channel(tmpl
->swizzle_a
),
939 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
943 u_upload_alloc(ice
->state
.surface_uploader
, 0,
944 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
945 &isv
->surface_state_offset
,
946 &isv
->surface_state_resource
,
951 struct iris_bo
*state_bo
= iris_resource_bo(isv
->surface_state_resource
);
952 isv
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
954 isl_surf_fill_state(&screen
->isl_dev
, map
,
955 .surf
= &itex
->surf
, .view
= &isv
->view
,
957 .address
= itex
->bo
->gtt_offset
);
959 // .clear_color = clear_color,
964 struct iris_surface
{
965 struct pipe_surface pipe
;
966 struct isl_view view
;
968 /** The resource (BO) holding our SURFACE_STATE. */
969 struct pipe_resource
*surface_state_resource
;
970 unsigned surface_state_offset
;
972 // uint32_t surface_state[GENX(RENDER_SURFACE_STATE_length)];
975 static struct pipe_surface
*
976 iris_create_surface(struct pipe_context
*ctx
,
977 struct pipe_resource
*tex
,
978 const struct pipe_surface
*tmpl
)
980 struct iris_context
*ice
= (struct iris_context
*) ctx
;
981 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
982 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
983 struct pipe_surface
*psurf
= &surf
->pipe
;
984 struct iris_resource
*res
= (struct iris_resource
*) tex
;
989 pipe_reference_init(&psurf
->reference
, 1);
990 pipe_resource_reference(&psurf
->texture
, tex
);
991 psurf
->context
= ctx
;
992 psurf
->format
= tmpl
->format
;
993 psurf
->width
= tex
->width0
;
994 psurf
->height
= tex
->height0
;
995 psurf
->texture
= tex
;
996 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
997 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
998 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1002 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1003 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1004 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1006 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1008 surf
->view
= (struct isl_view
) {
1009 .format
= iris_isl_format_for_pipe_format(tmpl
->format
),
1010 .base_level
= tmpl
->u
.tex
.level
,
1012 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1013 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1014 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1018 /* Bail early for depth/stencil */
1019 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1020 ISL_SURF_USAGE_STENCIL_BIT
))
1024 u_upload_alloc(ice
->state
.surface_uploader
, 0,
1025 4 * GENX(RENDER_SURFACE_STATE_length
), 64,
1026 &surf
->surface_state_offset
,
1027 &surf
->surface_state_resource
,
1032 struct iris_bo
*state_bo
= iris_resource_bo(surf
->surface_state_resource
);
1033 surf
->surface_state_offset
+= iris_bo_offset_from_base_address(state_bo
);
1035 isl_surf_fill_state(&screen
->isl_dev
, map
,
1036 .surf
= &res
->surf
, .view
= &surf
->view
,
1038 .address
= res
->bo
->gtt_offset
);
1040 // .clear_color = clear_color,
1046 iris_set_sampler_views(struct pipe_context
*ctx
,
1047 enum pipe_shader_type p_stage
,
1048 unsigned start
, unsigned count
,
1049 struct pipe_sampler_view
**views
)
1051 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1052 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1055 for (i
= 0; i
< count
; i
++) {
1056 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1057 &ice
->state
.textures
[stage
][i
], views
[i
]);
1059 for (; i
< ice
->state
.num_textures
[stage
]; i
++) {
1060 pipe_sampler_view_reference((struct pipe_sampler_view
**)
1061 &ice
->state
.textures
[stage
][i
], NULL
);
1064 ice
->state
.num_textures
[stage
] = count
;
1066 // XXX: ice->state.dirty |= (IRIS_DIRTY_BINDING_TABLE_VS << stage);
1070 iris_set_clip_state(struct pipe_context
*ctx
,
1071 const struct pipe_clip_state
*state
)
1076 iris_set_polygon_stipple(struct pipe_context
*ctx
,
1077 const struct pipe_poly_stipple
*state
)
1079 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1080 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
1081 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
1085 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
1087 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1089 ice
->state
.sample_mask
= sample_mask
;
1090 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
1094 iris_set_scissor_states(struct pipe_context
*ctx
,
1095 unsigned start_slot
,
1096 unsigned num_scissors
,
1097 const struct pipe_scissor_state
*states
)
1099 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1101 ice
->state
.num_scissors
= num_scissors
;
1103 for (unsigned i
= 0; i
< num_scissors
; i
++) {
1104 ice
->state
.scissors
[start_slot
+ i
] = states
[i
];
1107 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
1111 iris_set_stencil_ref(struct pipe_context
*ctx
,
1112 const struct pipe_stencil_ref
*state
)
1114 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1115 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
1116 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1120 struct iris_viewport_state
{
1121 uint32_t sf_cl_vp
[GENX(SF_CLIP_VIEWPORT_length
) * IRIS_MAX_VIEWPORTS
];
1125 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
1127 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
1132 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
1133 float m00
, float m11
, float m30
, float m31
,
1134 float *xmin
, float *xmax
,
1135 float *ymin
, float *ymax
)
1137 /* According to the "Vertex X,Y Clamping and Quantization" section of the
1138 * Strips and Fans documentation:
1140 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
1141 * fixed-point "guardband" range supported by the rasterization hardware"
1145 * "In almost all circumstances, if an object’s vertices are actually
1146 * modified by this clamping (i.e., had X or Y coordinates outside of
1147 * the guardband extent the rendered object will not match the intended
1148 * result. Therefore software should take steps to ensure that this does
1149 * not happen - e.g., by clipping objects such that they do not exceed
1150 * these limits after the Drawing Rectangle is applied."
1152 * I believe the fundamental restriction is that the rasterizer (in
1153 * the SF/WM stages) have a limit on the number of pixels that can be
1154 * rasterized. We need to ensure any coordinates beyond the rasterizer
1155 * limit are handled by the clipper. So effectively that limit becomes
1156 * the clipper's guardband size.
1158 * It goes on to say:
1160 * "In addition, in order to be correctly rendered, objects must have a
1161 * screenspace bounding box not exceeding 8K in the X or Y direction.
1162 * This additional restriction must also be comprehended by software,
1163 * i.e., enforced by use of clipping."
1165 * This makes no sense. Gen7+ hardware supports 16K render targets,
1166 * and you definitely need to be able to draw polygons that fill the
1167 * surface. Our assumption is that the rasterizer was limited to 8K
1168 * on Sandybridge, which only supports 8K surfaces, and it was actually
1169 * increased to 16K on Ivybridge and later.
1171 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
1173 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
1175 if (m00
!= 0 && m11
!= 0) {
1176 /* First, we compute the screen-space render area */
1177 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
1178 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
1179 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
1180 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
1182 /* We want the guardband to be centered on that */
1183 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
1184 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
1185 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
1186 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
1188 /* Now we need it in native device coordinates */
1189 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
1190 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
1191 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
1192 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
1194 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
1195 * flipped upside-down. X should be fine though.
1197 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
1198 *xmin
= ndc_gb_xmin
;
1199 *xmax
= ndc_gb_xmax
;
1200 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
1201 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
1203 /* The viewport scales to 0, so nothing will be rendered. */
1213 iris_set_viewport_states(struct pipe_context
*ctx
,
1214 unsigned start_slot
,
1215 unsigned num_viewports
,
1216 const struct pipe_viewport_state
*state
)
1218 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1219 struct iris_viewport_state
*cso
=
1220 malloc(sizeof(struct iris_viewport_state
));
1221 uint32_t *vp_map
= &cso
->sf_cl_vp
[start_slot
];
1223 // XXX: sf_cl_vp is only big enough for one slot, we don't iterate right
1224 for (unsigned i
= 0; i
< num_viewports
; i
++) {
1225 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
1226 vp
.ViewportMatrixElementm00
= state
[i
].scale
[0];
1227 vp
.ViewportMatrixElementm11
= state
[i
].scale
[1];
1228 vp
.ViewportMatrixElementm22
= state
[i
].scale
[2];
1229 vp
.ViewportMatrixElementm30
= state
[i
].translate
[0];
1230 vp
.ViewportMatrixElementm31
= state
[i
].translate
[1];
1231 vp
.ViewportMatrixElementm32
= state
[i
].translate
[2];
1232 /* XXX: in i965 this is computed based on the drawbuffer size,
1233 * but we don't have that here...
1235 vp
.XMinClipGuardband
= -1.0;
1236 vp
.XMaxClipGuardband
= 1.0;
1237 vp
.YMinClipGuardband
= -1.0;
1238 vp
.YMaxClipGuardband
= 1.0;
1239 vp
.XMinViewPort
= viewport_extent(&state
[i
], 0, -1.0f
);
1240 vp
.XMaxViewPort
= viewport_extent(&state
[i
], 0, 1.0f
) - 1;
1241 vp
.YMinViewPort
= viewport_extent(&state
[i
], 1, -1.0f
);
1242 vp
.YMaxViewPort
= viewport_extent(&state
[i
], 1, 1.0f
) - 1;
1245 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
1248 ice
->state
.cso_vp
= cso
;
1249 ice
->state
.num_viewports
= num_viewports
;
1250 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
1253 struct iris_depth_buffer_state
1255 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
1256 GENX(3DSTATE_STENCIL_BUFFER_length
) +
1257 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
1258 GENX(3DSTATE_CLEAR_PARAMS_length
)];
1262 iris_set_framebuffer_state(struct pipe_context
*ctx
,
1263 const struct pipe_framebuffer_state
*state
)
1265 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1266 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1267 struct isl_device
*isl_dev
= &screen
->isl_dev
;
1268 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
1270 if (cso
->samples
!= state
->samples
) {
1271 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1274 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
1275 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1278 cso
->width
= state
->width
;
1279 cso
->height
= state
->height
;
1280 cso
->layers
= state
->layers
;
1281 cso
->samples
= state
->samples
;
1284 for (i
= 0; i
< state
->nr_cbufs
; i
++)
1285 pipe_surface_reference(&cso
->cbufs
[i
], state
->cbufs
[i
]);
1286 for (; i
< cso
->nr_cbufs
; i
++)
1287 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
1289 cso
->nr_cbufs
= state
->nr_cbufs
;
1291 pipe_surface_reference(&cso
->zsbuf
, state
->zsbuf
);
1293 struct iris_depth_buffer_state
*cso_z
=
1294 malloc(sizeof(struct iris_depth_buffer_state
));
1296 struct isl_view view
= {
1297 /* Some nice defaults */
1300 .base_array_layer
= 0,
1302 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1305 struct isl_depth_stencil_hiz_emit_info info
= {
1310 struct iris_resource
*zres
=
1311 (void *) (cso
->zsbuf
? cso
->zsbuf
->texture
: NULL
);
1314 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
1316 info
.depth_surf
= &zres
->surf
;
1317 info
.depth_address
= zres
->bo
->gtt_offset
;
1319 view
.format
= zres
->surf
.format
;
1321 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
1322 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
1324 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
1326 info
.hiz_usage
= ISL_AUX_USAGE_NONE
;
1331 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
1332 info
.stencil_surf
= &stencil_mt
->surf
;
1335 view
.base_level
= stencil_irb
->mt_level
- stencil_irb
->mt
->first_level
;
1336 view
.base_array_layer
= stencil_irb
->mt_layer
;
1337 view
.array_len
= MAX2(stencil_irb
->layer_count
, 1);
1338 view
.format
= stencil_mt
->surf
.format
;
1341 uint32_t stencil_offset
= 0;
1342 info
.stencil_address
= stencil_mt
->bo
->gtt_offset
+ stencil_mt
->offset
;
1346 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
1348 ice
->state
.cso_depthbuffer
= cso_z
;
1349 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
1353 iris_set_constant_buffer(struct pipe_context
*ctx
,
1354 enum pipe_shader_type p_stage
, unsigned index
,
1355 const struct pipe_constant_buffer
*cb
)
1357 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1358 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1360 util_copy_constant_buffer(&ice
->shaders
.state
[stage
].constbuf
[index
], cb
);
1364 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1365 struct pipe_sampler_view
*state
)
1367 struct iris_sampler_view
*isv
= (void *) state
;
1368 pipe_resource_reference(&state
->texture
, NULL
);
1369 pipe_resource_reference(&isv
->surface_state_resource
, NULL
);
1375 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
1377 struct iris_surface
*surf
= (void *) p_surf
;
1378 pipe_resource_reference(&p_surf
->texture
, NULL
);
1379 pipe_resource_reference(&surf
->surface_state_resource
, NULL
);
1384 iris_delete_state(struct pipe_context
*ctx
, void *state
)
1389 struct iris_vertex_buffer_state
{
1390 uint32_t vertex_buffers
[1 + 33 * GENX(VERTEX_BUFFER_STATE_length
)];
1391 struct iris_bo
*bos
[33];
1392 unsigned num_buffers
;
1396 iris_free_vertex_buffers(struct iris_vertex_buffer_state
*cso
)
1399 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++)
1400 iris_bo_unreference(cso
->bos
[i
]);
1406 iris_set_vertex_buffers(struct pipe_context
*ctx
,
1407 unsigned start_slot
, unsigned count
,
1408 const struct pipe_vertex_buffer
*buffers
)
1410 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1411 struct iris_vertex_buffer_state
*cso
=
1412 malloc(sizeof(struct iris_vertex_buffer_state
));
1414 /* If there are no buffers, do nothing. We can leave the stale
1415 * 3DSTATE_VERTEX_BUFFERS in place - as long as there are no vertex
1416 * elements that point to them, it should be fine.
1421 iris_free_vertex_buffers(ice
->state
.cso_vertex_buffers
);
1423 cso
->num_buffers
= count
;
1425 iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS
), cso
->vertex_buffers
, vb
) {
1426 vb
.DWordLength
= 4 * cso
->num_buffers
- 1;
1429 uint32_t *vb_pack_dest
= &cso
->vertex_buffers
[1];
1431 for (unsigned i
= 0; i
< count
; i
++) {
1432 assert(!buffers
[i
].is_user_buffer
);
1434 struct iris_resource
*res
= (void *) buffers
[i
].buffer
.resource
;
1435 iris_bo_reference(res
->bo
);
1436 cso
->bos
[i
] = res
->bo
;
1438 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), vb_pack_dest
, vb
) {
1439 vb
.VertexBufferIndex
= start_slot
+ i
;
1441 vb
.AddressModifyEnable
= true;
1442 vb
.BufferPitch
= buffers
[i
].stride
;
1443 vb
.BufferSize
= res
->bo
->size
;
1444 vb
.BufferStartingAddress
=
1445 ro_bo(NULL
, res
->bo
->gtt_offset
+ buffers
[i
].buffer_offset
);
1448 vb_pack_dest
+= GENX(VERTEX_BUFFER_STATE_length
);
1451 ice
->state
.cso_vertex_buffers
= cso
;
1452 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
1455 struct iris_vertex_element_state
{
1456 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
1457 uint32_t vf_instancing
[GENX(3DSTATE_VF_INSTANCING_length
)][33];
1462 iris_create_vertex_elements(struct pipe_context
*ctx
,
1464 const struct pipe_vertex_element
*state
)
1466 struct iris_vertex_element_state
*cso
=
1467 malloc(sizeof(struct iris_vertex_element_state
));
1472 * - create edge flag one
1474 * - if those are necessary, use count + 1/2/3... OR in the length
1476 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
1478 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
1481 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
1483 for (int i
= 0; i
< count
; i
++) {
1484 enum isl_format isl_format
=
1485 iris_isl_format_for_pipe_format(state
[i
].src_format
);
1486 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
1487 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
1489 switch (isl_format_get_num_channels(isl_format
)) {
1490 case 0: comp
[0] = VFCOMP_STORE_0
;
1491 case 1: comp
[1] = VFCOMP_STORE_0
;
1492 case 2: comp
[2] = VFCOMP_STORE_0
;
1494 comp
[3] = isl_format_has_int_channel(isl_format
) ? VFCOMP_STORE_1_INT
1495 : VFCOMP_STORE_1_FP
;
1498 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
1499 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
1501 ve
.SourceElementOffset
= state
[i
].src_offset
;
1502 ve
.SourceElementFormat
= isl_format
;
1503 ve
.Component0Control
= comp
[0];
1504 ve
.Component1Control
= comp
[1];
1505 ve
.Component2Control
= comp
[2];
1506 ve
.Component3Control
= comp
[3];
1509 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
),
1510 cso
->vf_instancing
[i
], vi
) {
1511 vi
.VertexElementIndex
= i
;
1512 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
1513 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
1516 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
1523 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
1525 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1527 ice
->state
.cso_vertex_elements
= state
;
1528 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
1532 iris_create_compute_state(struct pipe_context
*ctx
,
1533 const struct pipe_compute_state
*state
)
1538 static struct pipe_stream_output_target
*
1539 iris_create_stream_output_target(struct pipe_context
*ctx
,
1540 struct pipe_resource
*res
,
1541 unsigned buffer_offset
,
1542 unsigned buffer_size
)
1544 struct pipe_stream_output_target
*t
=
1545 CALLOC_STRUCT(pipe_stream_output_target
);
1549 pipe_reference_init(&t
->reference
, 1);
1550 pipe_resource_reference(&t
->buffer
, res
);
1551 t
->buffer_offset
= buffer_offset
;
1552 t
->buffer_size
= buffer_size
;
1557 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
1558 struct pipe_stream_output_target
*t
)
1560 pipe_resource_reference(&t
->buffer
, NULL
);
1565 iris_set_stream_output_targets(struct pipe_context
*ctx
,
1566 unsigned num_targets
,
1567 struct pipe_stream_output_target
**targets
,
1568 const unsigned *offsets
)
1573 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
1574 const struct brw_vue_map
*last_vue_map
,
1575 bool two_sided_color
,
1576 unsigned *out_offset
,
1577 unsigned *out_length
)
1579 /* The compiler computes the first URB slot without considering COL/BFC
1580 * swizzling (because it doesn't know whether it's enabled), so we need
1581 * to do that here too. This may result in a smaller offset, which
1584 const unsigned first_slot
=
1585 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
1587 /* This becomes the URB read offset (counted in pairs of slots). */
1588 assert(first_slot
% 2 == 0);
1589 *out_offset
= first_slot
/ 2;
1591 /* We need to adjust the inputs read to account for front/back color
1592 * swizzling, as it can make the URB length longer.
1594 for (int c
= 0; c
<= 1; c
++) {
1595 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
1596 /* If two sided color is enabled, the fragment shader's gl_Color
1597 * (COL0) input comes from either the gl_FrontColor (COL0) or
1598 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
1600 if (two_sided_color
)
1601 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1603 /* If front color isn't written, we opt to give them back color
1604 * instead of an undefined value. Switch from COL to BFC.
1606 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
1607 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
1608 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
1613 /* Compute the minimum URB Read Length necessary for the FS inputs.
1615 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1616 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1618 * "This field should be set to the minimum length required to read the
1619 * maximum source attribute. The maximum source attribute is indicated
1620 * by the maximum value of the enabled Attribute # Source Attribute if
1621 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1622 * enable is not set.
1623 * read_length = ceiling((max_source_attr + 1) / 2)
1625 * [errata] Corruption/Hang possible if length programmed larger than
1628 * Similar text exists for Ivy Bridge.
1630 * We find the last URB slot that's actually read by the FS.
1632 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
1633 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
1634 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
1637 /* The URB read length is the difference of the two, counted in pairs. */
1638 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
1642 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
1644 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
1645 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
1646 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
1647 struct pipe_shader_state
*p_fs
=
1648 (void *) ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1649 assert(p_fs
->type
== PIPE_SHADER_IR_NIR
);
1650 nir_shader
*fs_nir
= p_fs
->ir
.nir
;
1652 unsigned urb_read_offset
, urb_read_length
;
1653 iris_compute_sbe_urb_read_interval(fs_nir
->info
.inputs_read
,
1654 ice
->shaders
.last_vue_map
,
1655 cso_rast
->light_twoside
,
1656 &urb_read_offset
, &urb_read_length
);
1658 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
1659 sbe
.AttributeSwizzleEnable
= true;
1660 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
1661 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
1662 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
1663 sbe
.VertexURBEntryReadLength
= urb_read_length
;
1664 sbe
.ForceVertexURBEntryReadOffset
= true;
1665 sbe
.ForceVertexURBEntryReadLength
= true;
1666 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
1668 for (int i
= 0; i
< 32; i
++) {
1669 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
1675 iris_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1680 iris_populate_sampler_key(const struct iris_context
*ice
,
1681 struct brw_sampler_prog_key_data
*key
)
1683 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
1684 key
->swizzles
[i
] = 0x688; /* XYZW */
1689 iris_populate_vs_key(const struct iris_context
*ice
,
1690 struct brw_vs_prog_key
*key
)
1692 memset(key
, 0, sizeof(*key
));
1693 iris_populate_sampler_key(ice
, &key
->tex
);
1697 iris_populate_tcs_key(const struct iris_context
*ice
,
1698 struct brw_tcs_prog_key
*key
)
1700 memset(key
, 0, sizeof(*key
));
1701 iris_populate_sampler_key(ice
, &key
->tex
);
1705 iris_populate_tes_key(const struct iris_context
*ice
,
1706 struct brw_tes_prog_key
*key
)
1708 memset(key
, 0, sizeof(*key
));
1709 iris_populate_sampler_key(ice
, &key
->tex
);
1713 iris_populate_gs_key(const struct iris_context
*ice
,
1714 struct brw_gs_prog_key
*key
)
1716 memset(key
, 0, sizeof(*key
));
1717 iris_populate_sampler_key(ice
, &key
->tex
);
1721 iris_populate_fs_key(const struct iris_context
*ice
,
1722 struct brw_wm_prog_key
*key
)
1724 memset(key
, 0, sizeof(*key
));
1725 iris_populate_sampler_key(ice
, &key
->tex
);
1727 /* XXX: dirty flags? */
1728 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
1729 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
1730 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
1731 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
1733 key
->nr_color_regions
= fb
->nr_cbufs
;
1735 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
1737 key
->replicate_alpha
= fb
->nr_cbufs
> 1 &&
1738 (zsa
->alpha
.enabled
|| blend
->alpha_to_coverage
);
1740 // key->force_dual_color_blend for unigine
1742 if (cso_rast
->multisample
) {
1743 key
->persample_interp
=
1744 ctx
->Multisample
.SampleShading
&&
1745 (ctx
->Multisample
.MinSampleShadingValue
*
1746 _mesa_geometric_samples(ctx
->DrawBuffer
) > 1);
1748 key
->multisample_fbo
= fb
->samples
> 1;
1752 key
->coherent_fb_fetch
= true;
1755 //pkt.SamplerCount = \
1756 //DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
1757 //pkt.PerThreadScratchSpace = prog_data->total_scratch == 0 ? 0 : \
1758 //ffs(stage_state->per_thread_scratch) - 11; \
1761 KSP(const struct iris_compiled_shader
*shader
)
1763 struct iris_resource
*res
= (void *) shader
->buffer
;
1764 return res
->bo
->gtt_offset
+ shader
->offset
;
1767 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
1768 pkt.KernelStartPointer = KSP(shader); \
1769 pkt.BindingTableEntryCount = prog_data->binding_table.size_bytes / 4; \
1770 pkt.FloatingPointMode = prog_data->use_alt_mode; \
1772 pkt.DispatchGRFStartRegisterForURBData = \
1773 prog_data->dispatch_grf_start_reg; \
1774 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
1775 pkt.prefix##URBEntryReadOffset = 0; \
1777 pkt.StatisticsEnable = true; \
1781 iris_set_vs_state(const struct gen_device_info
*devinfo
,
1782 struct iris_compiled_shader
*shader
)
1784 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1785 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1787 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
1788 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
);
1789 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1790 vs
.SIMD8DispatchEnable
= true;
1791 vs
.UserClipDistanceCullTestEnableBitmask
=
1792 vue_prog_data
->cull_distance_mask
;
1797 iris_set_tcs_state(const struct gen_device_info
*devinfo
,
1798 struct iris_compiled_shader
*shader
)
1800 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1801 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1802 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
1804 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
1805 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
);
1807 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1808 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1809 hs
.IncludeVertexHandles
= true;
1814 iris_set_tes_state(const struct gen_device_info
*devinfo
,
1815 struct iris_compiled_shader
*shader
)
1817 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1818 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1819 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
1821 uint32_t *te_state
= (void *) shader
->derived_data
;
1822 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
1824 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
1825 te
.Partitioning
= tes_prog_data
->partitioning
;
1826 te
.OutputTopology
= tes_prog_data
->output_topology
;
1827 te
.TEDomain
= tes_prog_data
->domain
;
1829 te
.MaximumTessellationFactorOdd
= 63.0;
1830 te
.MaximumTessellationFactorNotOdd
= 64.0;
1833 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
1834 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
);
1836 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1837 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1838 ds
.ComputeWCoordinateEnable
=
1839 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1841 ds
.UserClipDistanceCullTestEnableBitmask
=
1842 vue_prog_data
->cull_distance_mask
;
1848 iris_set_gs_state(const struct gen_device_info
*devinfo
,
1849 struct iris_compiled_shader
*shader
)
1851 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1852 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1853 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
1855 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
1856 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
);
1858 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1859 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1860 gs
.ControlDataHeaderSize
=
1861 gs_prog_data
->control_data_header_size_hwords
;
1862 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
1863 gs
.DispatchMode
= SIMD8
;
1864 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1865 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1866 gs
.ReorderMode
= TRAILING
;
1867 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1868 gs
.MaximumNumberofThreads
=
1869 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
1870 : (devinfo
->max_gs_threads
- 1);
1872 if (gs_prog_data
->static_vertex_count
!= -1) {
1873 gs
.StaticOutput
= true;
1874 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
1876 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
1878 gs
.UserClipDistanceCullTestEnableBitmask
=
1879 vue_prog_data
->cull_distance_mask
;
1881 const int urb_entry_write_offset
= 1;
1882 const uint32_t urb_entry_output_length
=
1883 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
1884 urb_entry_write_offset
;
1886 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
1887 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
1892 iris_set_fs_state(const struct gen_device_info
*devinfo
,
1893 struct iris_compiled_shader
*shader
)
1895 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
1896 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
1898 uint32_t *ps_state
= (void *) shader
->derived_data
;
1899 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
1901 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
1902 ps
.VectorMaskEnable
= true;
1903 //ps.SamplerCount = ...
1904 ps
.BindingTableEntryCount
= prog_data
->binding_table
.size_bytes
/ 4;
1905 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
1906 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
1908 ps
.PushConstantEnable
= prog_data
->nr_params
> 0 ||
1909 prog_data
->ubo_ranges
[0].length
> 0;
1911 /* From the documentation for this packet:
1912 * "If the PS kernel does not need the Position XY Offsets to
1913 * compute a Position Value, then this field should be programmed
1914 * to POSOFFSET_NONE."
1916 * "SW Recommendation: If the PS kernel needs the Position Offsets
1917 * to compute a Position XY value, this field should match Position
1918 * ZW Interpolation Mode to ensure a consistent position.xyzw
1921 * We only require XY sample offsets. So, this recommendation doesn't
1922 * look useful at the moment. We might need this in future.
1924 ps
.PositionXYOffsetSelect
=
1925 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1926 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1927 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1928 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1930 // XXX: Disable SIMD32 with 16x MSAA
1932 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1933 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1934 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1935 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1936 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1937 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1939 ps
.KernelStartPointer0
=
1940 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1941 ps
.KernelStartPointer1
=
1942 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1943 ps
.KernelStartPointer2
=
1944 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1947 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
1948 psx
.PixelShaderValid
= true;
1949 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1950 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
1951 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
1952 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1953 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1954 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1956 if (wm_prog_data
->uses_sample_mask
) {
1957 /* TODO: conservative rasterization */
1958 if (wm_prog_data
->post_depth_coverage
)
1959 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1961 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
1964 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1965 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1966 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1973 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
1975 assert(cache_id
<= IRIS_CACHE_BLORP
);
1977 static const unsigned dwords
[] = {
1978 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
1979 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
1980 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
1981 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
1983 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
1984 [IRIS_CACHE_CS
] = 0,
1985 [IRIS_CACHE_BLORP
] = 0,
1988 return sizeof(uint32_t) * dwords
[cache_id
];
1992 iris_set_derived_program_state(const struct gen_device_info
*devinfo
,
1993 enum iris_program_cache_id cache_id
,
1994 struct iris_compiled_shader
*shader
)
1998 iris_set_vs_state(devinfo
, shader
);
2000 case IRIS_CACHE_TCS
:
2001 iris_set_tcs_state(devinfo
, shader
);
2003 case IRIS_CACHE_TES
:
2004 iris_set_tes_state(devinfo
, shader
);
2007 iris_set_gs_state(devinfo
, shader
);
2010 iris_set_fs_state(devinfo
, shader
);
2013 case IRIS_CACHE_BLORP
:
2021 iris_upload_urb_config(struct iris_context
*ice
, struct iris_batch
*batch
)
2023 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2024 const unsigned push_size_kB
= 32;
2025 unsigned entries
[4];
2029 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2030 if (!ice
->shaders
.prog
[i
]) {
2033 struct brw_vue_prog_data
*vue_prog_data
=
2034 (void *) ice
->shaders
.prog
[i
]->prog_data
;
2035 size
[i
] = vue_prog_data
->urb_entry_size
;
2037 assert(size
[i
] != 0);
2040 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
2041 1024 * ice
->shaders
.urb_size
,
2042 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
2043 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
,
2044 size
, entries
, start
);
2046 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2047 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
2048 urb
._3DCommandSubOpcode
+= i
;
2049 urb
.VSURBStartingAddress
= start
[i
];
2050 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
2051 urb
.VSNumberofURBEntries
= entries
[i
];
2056 static const uint32_t push_constant_opcodes
[] = {
2057 [MESA_SHADER_VERTEX
] = 21,
2058 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2059 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2060 [MESA_SHADER_GEOMETRY
] = 22,
2061 [MESA_SHADER_FRAGMENT
] = 23,
2062 [MESA_SHADER_COMPUTE
] = 0,
2066 * Add a surface to the validation list, as well as the buffer containing
2067 * the corresponding SURFACE_STATE.
2069 * Returns the binding table entry (offset to SURFACE_STATE).
2072 use_surface(struct iris_batch
*batch
,
2073 struct pipe_surface
*p_surf
,
2076 struct iris_surface
*surf
= (void *) p_surf
;
2077 struct iris_resource
*res
= (void *) p_surf
->texture
;
2078 struct iris_resource
*state_res
= (void *) surf
->surface_state_resource
;
2079 iris_use_pinned_bo(batch
, res
->bo
, writeable
);
2080 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2082 return surf
->surface_state_offset
;
2086 use_sampler_view(struct iris_batch
*batch
, struct iris_sampler_view
*isv
)
2088 struct iris_resource
*res
= (void *) isv
->pipe
.texture
;
2089 struct iris_resource
*state_res
= (void *) isv
->surface_state_resource
;
2090 iris_use_pinned_bo(batch
, res
->bo
, false);
2091 iris_use_pinned_bo(batch
, state_res
->bo
, false);
2093 return isv
->surface_state_offset
;
2097 iris_upload_render_state(struct iris_context
*ice
,
2098 struct iris_batch
*batch
,
2099 const struct pipe_draw_info
*draw
)
2101 const uint64_t dirty
=
2102 unlikely(INTEL_DEBUG
& DEBUG_REEMIT
) ? ~0ull : ice
->state
.dirty
;
2104 struct brw_wm_prog_data
*wm_prog_data
= (void *)
2105 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
2107 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
2108 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2109 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
2110 ptr
.CCViewportPointer
=
2111 emit_state(batch
, ice
->state
.dynamic_uploader
,
2112 cso
->cc_vp
, sizeof(cso
->cc_vp
), 32);
2116 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
2117 struct iris_viewport_state
*cso
= ice
->state
.cso_vp
;
2118 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
2119 ptr
.SFClipViewportPointer
=
2120 emit_state(batch
, ice
->state
.dynamic_uploader
, cso
->sf_cl_vp
,
2121 4 * GENX(SF_CLIP_VIEWPORT_length
) *
2122 ice
->state
.num_viewports
, 64);
2128 if (dirty
& IRIS_DIRTY_URB
) {
2129 iris_upload_urb_config(ice
, batch
);
2132 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
2133 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2134 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2135 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2136 const int num_dwords
= 4 * (GENX(BLEND_STATE_length
) +
2137 cso_fb
->nr_cbufs
* GENX(BLEND_STATE_ENTRY_length
));
2138 uint32_t blend_offset
;
2139 uint32_t *blend_map
=
2140 stream_state(batch
, ice
->state
.dynamic_uploader
, 4 * num_dwords
, 64,
2143 uint32_t blend_state_header
;
2144 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
2145 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2146 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
2149 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
2150 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1],
2151 sizeof(cso_blend
->blend_state
) - sizeof(uint32_t));
2153 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
2154 ptr
.BlendStatePointer
= blend_offset
;
2155 ptr
.BlendStatePointerValid
= true;
2159 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
2160 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2163 stream_state(batch
, ice
->state
.dynamic_uploader
,
2164 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
2166 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
2167 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
2168 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
2169 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
2170 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
2171 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
2172 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
2174 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
2175 ptr
.ColorCalcStatePointer
= cc_offset
;
2176 ptr
.ColorCalcStatePointerValid
= true;
2180 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2181 // XXX: wrong dirty tracking...
2182 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2185 struct pipe_constant_buffer
*cbuf0
=
2186 &ice
->shaders
.state
[stage
].constbuf
[0];
2188 if (!ice
->shaders
.prog
[stage
] || cbuf0
->buffer
|| !cbuf0
->buffer_size
)
2191 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2192 // XXX: DIV_ROUND_UP(prog_data->nr_params, 8)?
2193 shs
->const_size
= DIV_ROUND_UP(cbuf0
->buffer_size
, 32);
2194 u_upload_data(ice
->ctx
.const_uploader
, 0, 32 * shs
->const_size
, 32,
2195 cbuf0
->user_buffer
, &shs
->const_offset
,
2196 &shs
->push_resource
);
2199 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2200 // XXX: wrong dirty tracking...
2201 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
2204 struct iris_shader_state
*shs
= &ice
->shaders
.state
[stage
];
2205 struct iris_resource
*res
= (void *) shs
->push_resource
;
2207 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
2208 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2210 pkt
.ConstantBody
.ReadLength
[3] = shs
->const_size
;
2211 pkt
.ConstantBody
.Buffer
[3] = ro_bo(res
->bo
, shs
->const_offset
);
2218 // - ubos/ssbos/abos
2221 // - render targets - write and read
2222 // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
2224 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2225 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2226 if (!shader
) // XXX: dirty bits...also, emit a disable maybe?
2229 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
2230 uint32_t bt_offset
= 0;
2231 uint32_t *bt_map
= NULL
;
2234 if (prog_data
->binding_table
.size_bytes
!= 0) {
2235 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
2236 bt_map
= iris_binder_reserve(&ice
->state
.binder
,
2237 prog_data
->binding_table
.size_bytes
,
2241 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
2242 ptr
._3DCommandSubOpcode
= 38 + stage
;
2243 ptr
.PointertoVSBindingTable
= bt_offset
;
2246 if (stage
== MESA_SHADER_FRAGMENT
) {
2247 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2248 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
2249 bt_map
[s
++] = use_surface(batch
, cso_fb
->cbufs
[i
], true);
2253 assert(prog_data
->binding_table
.texture_start
==
2254 (ice
->state
.num_textures
[stage
] ? s
: 0xd0d0d0d0));
2256 for (int i
= 0; i
< ice
->state
.num_textures
[stage
]; i
++) {
2257 struct iris_sampler_view
*view
= ice
->state
.textures
[stage
][i
];
2258 bt_map
[s
++] = use_sampler_view(batch
, view
);
2262 // XXX: not implemented yet
2263 assert(prog_data
->binding_table
.pull_constants_start
== 0xd0d0d0d0);
2264 assert(prog_data
->binding_table
.ubo_start
== 0xd0d0d0d0);
2265 assert(prog_data
->binding_table
.ssbo_start
== 0xd0d0d0d0);
2266 assert(prog_data
->binding_table
.image_start
== 0xd0d0d0d0);
2267 assert(prog_data
->binding_table
.shader_time_start
== 0xd0d0d0d0);
2268 //assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
2269 //assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
2273 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2274 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
2275 !ice
->shaders
.prog
[stage
])
2278 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
2279 ptr
._3DCommandSubOpcode
= 43 + stage
;
2280 ptr
.PointertoVSSamplerState
= ice
->state
.sampler_table_offset
[stage
];
2284 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
2285 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
2287 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
2288 if (ice
->state
.framebuffer
.samples
> 0)
2289 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
2293 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
2294 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
2295 ms
.SampleMask
= MAX2(ice
->state
.sample_mask
, 1);
2299 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
2300 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
2303 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2306 struct iris_resource
*cache
= (void *) shader
->buffer
;
2307 iris_use_pinned_bo(batch
, cache
->bo
, false);
2308 iris_batch_emit(batch
, shader
->derived_data
,
2309 iris_derived_program_state_size(stage
));
2311 if (stage
== MESA_SHADER_TESS_EVAL
) {
2312 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
2313 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
2314 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
2315 } else if (stage
== MESA_SHADER_GEOMETRY
) {
2316 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
2322 // 3DSTATE_STREAMOUT
2323 // 3DSTATE_SO_BUFFER
2324 // 3DSTATE_SO_DECL_LIST
2326 if (dirty
& IRIS_DIRTY_CLIP
) {
2327 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
2328 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2330 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
2331 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
2332 if (wm_prog_data
->barycentric_interp_modes
&
2333 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
2334 cl
.NonPerspectiveBarycentricEnable
= true;
2336 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
2338 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
2339 ARRAY_SIZE(cso_rast
->clip
));
2342 if (dirty
& IRIS_DIRTY_RASTER
) {
2343 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2344 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
2345 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
2349 if (dirty
& (IRIS_DIRTY_RASTER
| IRIS_DIRTY_FS
)) {
2350 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2351 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
2353 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
2354 wm
.BarycentricInterpolationMode
=
2355 wm_prog_data
->barycentric_interp_modes
;
2357 if (wm_prog_data
->early_fragment_tests
)
2358 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
2359 else if (wm_prog_data
->has_side_effects
)
2360 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
2362 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
2366 // XXX: 3DSTATE_SBE, 3DSTATE_SBE_SWIZ
2367 // -> iris_raster_state (point sprite texture coordinate origin)
2368 // -> bunch of shader state...
2369 iris_emit_sbe(batch
, ice
);
2370 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
) {
2374 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
2375 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
2376 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
2377 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
2378 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
2379 pb
.HasWriteableRT
= true; // XXX: comes from somewhere :(
2380 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
2383 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
2384 ARRAY_SIZE(cso_blend
->ps_blend
));
2387 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
2388 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
2389 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
2391 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
2392 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
2393 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
2394 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
2396 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
2399 if (dirty
& IRIS_DIRTY_SCISSOR
) {
2400 // XXX: allocate at set_scissor time?
2401 uint32_t scissor_offset
= ice
->state
.num_scissors
== 0 ? 0 :
2402 emit_state(batch
, ice
->state
.dynamic_uploader
, ice
->state
.scissors
,
2403 sizeof(struct pipe_scissor_state
) *
2404 ice
->state
.num_scissors
, 32);
2406 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
2407 ptr
.ScissorRectPointer
= scissor_offset
;
2411 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
2412 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
2413 struct iris_depth_buffer_state
*cso_z
= ice
->state
.cso_depthbuffer
;
2415 iris_batch_emit(batch
, cso_z
->packets
, sizeof(cso_z
->packets
));
2417 if (cso_fb
->zsbuf
) {
2418 struct iris_resource
*zres
= (void *) cso_fb
->zsbuf
->texture
;
2419 // XXX: depth might not be writable...
2420 iris_use_pinned_bo(batch
, zres
->bo
, true);
2424 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
2425 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
2426 for (int i
= 0; i
< 32; i
++) {
2427 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
2432 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
2433 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
2434 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
2438 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
2439 topo
.PrimitiveTopologyType
=
2440 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
2444 if (draw
->index_size
> 0) {
2445 struct iris_resource
*res
= (struct iris_resource
*)draw
->index
.resource
;
2447 assert(!draw
->has_user_indices
);
2449 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
2450 ib
.IndexFormat
= draw
->index_size
;
2452 ib
.BufferSize
= res
->bo
->size
;
2453 ib
.BufferStartingAddress
= ro_bo(res
->bo
, 0);
2457 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
2458 struct iris_vertex_buffer_state
*cso
= ice
->state
.cso_vertex_buffers
;
2460 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length
) == 4);
2461 STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) % 32) == 0);
2463 iris_batch_emit(batch
, cso
->vertex_buffers
,
2464 sizeof(uint32_t) * (1 + 4 * cso
->num_buffers
));
2466 for (unsigned i
= 0; i
< cso
->num_buffers
; i
++) {
2467 iris_use_pinned_bo(batch
, cso
->bos
[i
], false);
2471 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
2472 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
2473 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
2474 (1 + cso
->count
* GENX(VERTEX_ELEMENT_STATE_length
)));
2475 for (int i
= 0; i
< cso
->count
; i
++) {
2476 iris_batch_emit(batch
, cso
->vf_instancing
[i
], sizeof(uint32_t) *
2477 GENX(3DSTATE_VF_INSTANCING_length
));
2479 for (int i
= 0; i
< cso
->count
; i
++) {
2480 /* TODO: vertexid, instanceid support */
2481 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
);
2486 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
2487 if (draw
->primitive_restart
) {
2488 vf
.IndexedDrawCutIndexEnable
= true;
2489 vf
.CutIndex
= draw
->restart_index
;
2494 // XXX: Gen8 - PMA fix
2496 assert(!draw
->indirect
); // XXX: indirect support
2498 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
2499 prim
.StartInstanceLocation
= draw
->start_instance
;
2500 prim
.InstanceCount
= draw
->instance_count
;
2501 prim
.VertexCountPerInstance
= draw
->count
;
2502 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
2504 // XXX: this is probably bonkers.
2505 prim
.StartVertexLocation
= draw
->start
;
2507 if (draw
->index_size
) {
2508 prim
.BaseVertexLocation
+= draw
->index_bias
;
2510 prim
.StartVertexLocation
+= draw
->index_bias
;
2513 //prim.BaseVertexLocation = ...;
2518 iris_destroy_state(struct iris_context
*ice
)
2520 // XXX: unreference resources/surfaces.
2521 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
2522 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
2524 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
2528 flags_to_post_sync_op(uint32_t flags
)
2530 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
2531 return WriteImmediateData
;
2533 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
2534 return WritePSDepthCount
;
2536 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
2537 return WriteTimestamp
;
2543 * Do the given flags have a Post Sync or LRI Post Sync operation?
2545 static enum pipe_control_flags
2546 get_post_sync_flags(enum pipe_control_flags flags
)
2548 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
2549 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2550 PIPE_CONTROL_WRITE_TIMESTAMP
|
2551 PIPE_CONTROL_LRI_POST_SYNC_OP
;
2553 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
2554 * "LRI Post Sync Operation". So more than one bit set would be illegal.
2556 assert(util_bitcount(flags
) <= 1);
2561 // XXX: compute support
2562 #define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
2565 * Emit a series of PIPE_CONTROL commands, taking into account any
2566 * workarounds necessary to actually accomplish the caller's request.
2568 * Unless otherwise noted, spec quotations in this function come from:
2570 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
2571 * Restrictions for PIPE_CONTROL.
2574 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
2575 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
2577 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
2578 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
2579 enum pipe_control_flags non_lri_post_sync_flags
=
2580 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
2582 /* Recursive PIPE_CONTROL workarounds --------------------------------
2583 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
2585 * We do these first because we want to look at the original operation,
2586 * rather than any workarounds we set.
2588 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
2589 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
2590 * lists several workarounds:
2592 * "Project: SKL, KBL, BXT
2594 * If the VF Cache Invalidation Enable is set to a 1 in a
2595 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
2596 * sets to 0, with the VF Cache Invalidation Enable set to 0
2597 * needs to be sent prior to the PIPE_CONTROL with VF Cache
2598 * Invalidation Enable set to a 1."
2600 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
2603 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
2604 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2606 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2607 * programmed prior to programming a PIPECONTROL command with "LRI
2608 * Post Sync Operation" in GPGPU mode of operation (i.e when
2609 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2611 * The same text exists a few rows below for Post Sync Op.
2613 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
2616 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
2618 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
2619 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
2620 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
2622 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
2626 /* "Flush Types" workarounds ---------------------------------------------
2627 * We do these now because they may add post-sync operations or CS stalls.
2630 if (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
2631 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
2633 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
2634 * 'Write PS Depth Count' or 'Write Timestamp'."
2637 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2638 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2639 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
2640 bo
= batch
->screen
->workaround_bo
;
2644 /* #1130 from Gen10 workarounds page:
2646 * "Enable Depth Stall on every Post Sync Op if Render target Cache
2647 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
2648 * board stall if Render target cache flush is enabled."
2650 * Applicable to CNL B0 and C0 steppings only.
2652 * The wording here is unclear, and this workaround doesn't look anything
2653 * like the internal bug report recommendations, but leave it be for now...
2655 if (GEN_GEN
== 10) {
2656 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
2657 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2658 } else if (flags
& non_lri_post_sync_flags
) {
2659 flags
|= PIPE_CONTROL_DEPTH_STALL
;
2663 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
2664 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
2666 * "This bit must be DISABLED for operations other than writing
2669 * This seems like nonsense. An Ivybridge workaround requires us to
2670 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
2671 * operation. Gen8+ requires us to emit depth stalls and depth cache
2672 * flushes together. So, it's hard to imagine this means anything other
2673 * than "we originally intended this to be used for PS_DEPTH_COUNT".
2675 * We ignore the supposed restriction and do nothing.
2679 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2680 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
2681 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
2683 * "This bit must be DISABLED for End-of-pipe (Read) fences,
2684 * PS_DEPTH_COUNT or TIMESTAMP queries."
2686 * TODO: Implement end-of-pipe checking.
2688 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2689 PIPE_CONTROL_WRITE_TIMESTAMP
)));
2692 if (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
) {
2693 /* From the PIPE_CONTROL instruction table, bit 1:
2695 * "This bit is ignored if Depth Stall Enable is set.
2696 * Further, the render cache is not flushed even if Write Cache
2697 * Flush Enable bit is set."
2699 * We assert that the caller doesn't do this combination, to try and
2700 * prevent mistakes. It shouldn't hurt the GPU, though.
2702 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
2703 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
2706 /* PIPE_CONTROL page workarounds ------------------------------------- */
2708 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
2709 /* From the PIPE_CONTROL page itself:
2712 * Restriction: Pipe_control with CS-stall bit set must be issued
2713 * before a pipe-control command that has the State Cache
2714 * Invalidate bit set."
2716 flags
|= PIPE_CONTROL_CS_STALL
;
2719 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
2720 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
2723 * SW must always program Post-Sync Operation to "Write Immediate
2724 * Data" when Flush LLC is set."
2726 * For now, we just require the caller to do it.
2728 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
2731 /* "Post-Sync Operation" workarounds -------------------------------- */
2733 /* Project: All / Argument: Global Snapshot Count Reset [19]
2735 * "This bit must not be exercised on any product.
2736 * Requires stall bit ([20] of DW1) set."
2738 * We don't use this, so we just assert that it isn't used. The
2739 * PIPE_CONTROL instruction page indicates that they intended this
2740 * as a debug feature and don't think it is useful in production,
2741 * but it may actually be usable, should we ever want to.
2743 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
2745 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
2746 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
2747 /* Project: All / Arguments:
2749 * - Generic Media State Clear [16]
2750 * - Indirect State Pointers Disable [16]
2752 * "Requires stall bit ([20] of DW1) set."
2754 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
2755 * State Clear) says:
2757 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2758 * programmed prior to programming a PIPECONTROL command with "Media
2759 * State Clear" set in GPGPU mode of operation"
2761 * This is a subset of the earlier rule, so there's nothing to do.
2763 flags
|= PIPE_CONTROL_CS_STALL
;
2766 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
2767 /* Project: All / Argument: Store Data Index
2769 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2772 * For now, we just assert that the caller does this. We might want to
2773 * automatically add a write to the workaround BO...
2775 assert(non_lri_post_sync_flags
!= 0);
2778 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
2779 /* Project: All / Argument: Sync GFDT
2781 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
2782 * than '0' or 0x2520[13] must be set."
2784 * For now, we just assert that the caller does this.
2786 assert(non_lri_post_sync_flags
!= 0);
2789 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
2790 /* Project: IVB+ / Argument: TLB inv
2792 * "Requires stall bit ([20] of DW1) set."
2794 * Also, from the PIPE_CONTROL instruction table:
2797 * Post Sync Operation or CS stall must be set to ensure a TLB
2798 * invalidation occurs. Otherwise no cycle will occur to the TLB
2799 * cache to invalidate."
2801 * This is not a subset of the earlier rule, so there's nothing to do.
2803 flags
|= PIPE_CONTROL_CS_STALL
;
2806 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
2807 /* TODO: The big Skylake GT4 post sync op workaround */
2810 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
2812 if (IS_COMPUTE_PIPELINE(batch
)) {
2813 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
2814 /* Project: SKL+ / Argument: Tex Invalidate
2815 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
2817 flags
|= PIPE_CONTROL_CS_STALL
;
2820 if (GEN_GEN
== 8 && (post_sync_flags
||
2821 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
2822 PIPE_CONTROL_DEPTH_STALL
|
2823 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2824 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2825 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
2826 /* Project: BDW / Arguments:
2828 * - LRI Post Sync Operation [23]
2829 * - Post Sync Op [15:14]
2831 * - Depth Stall [13]
2832 * - Render Target Cache Flush [12]
2833 * - Depth Cache Flush [0]
2834 * - DC Flush Enable [5]
2836 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
2839 flags
|= PIPE_CONTROL_CS_STALL
;
2841 /* Also, from the PIPE_CONTROL instruction table, bit 20:
2844 * This bit must be always set when PIPE_CONTROL command is
2845 * programmed by GPGPU and MEDIA workloads, except for the cases
2846 * when only Read Only Cache Invalidation bits are set (State
2847 * Cache Invalidation Enable, Instruction cache Invalidation
2848 * Enable, Texture Cache Invalidation Enable, Constant Cache
2849 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
2850 * need not implemented when FF_DOP_CG is disable via "Fixed
2851 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
2853 * It sounds like we could avoid CS stalls in some cases, but we
2854 * don't currently bother. This list isn't exactly the list above,
2860 /* "Stall" workarounds ----------------------------------------------
2861 * These have to come after the earlier ones because we may have added
2862 * some additional CS stalls above.
2865 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
2866 /* Project: PRE-SKL, VLV, CHV
2868 * "[All Stepping][All SKUs]:
2870 * One of the following must also be set:
2872 * - Render Target Cache Flush Enable ([12] of DW1)
2873 * - Depth Cache Flush Enable ([0] of DW1)
2874 * - Stall at Pixel Scoreboard ([1] of DW1)
2875 * - Depth Stall ([13] of DW1)
2876 * - Post-Sync Operation ([13] of DW1)
2877 * - DC Flush Enable ([5] of DW1)"
2879 * If we don't already have one of those bits set, we choose to add
2880 * "Stall at Pixel Scoreboard". Some of the other bits require a
2881 * CS stall as a workaround (see above), which would send us into
2882 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
2883 * appears to be safe, so we choose that.
2885 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2886 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
2887 PIPE_CONTROL_WRITE_IMMEDIATE
|
2888 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
2889 PIPE_CONTROL_WRITE_TIMESTAMP
|
2890 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
2891 PIPE_CONTROL_DEPTH_STALL
|
2892 PIPE_CONTROL_DATA_CACHE_FLUSH
;
2893 if (!(flags
& wa_bits
))
2894 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2897 /* Emit --------------------------------------------------------------- */
2899 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
2900 pc
.LRIPostSyncOperation
= NoLRIOperation
;
2901 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
2902 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
2903 pc
.StoreDataIndex
= 0;
2904 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
2905 pc
.GlobalSnapshotCountReset
=
2906 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
2907 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
2908 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
2909 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
2910 pc
.RenderTargetCacheFlushEnable
=
2911 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
2912 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
2913 pc
.StateCacheInvalidationEnable
=
2914 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
2915 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2916 pc
.ConstantCacheInvalidationEnable
=
2917 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
2918 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
2919 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
2920 pc
.InstructionCacheInvalidateEnable
=
2921 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
2922 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
2923 pc
.IndirectStatePointersDisable
=
2924 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
2925 pc
.TextureCacheInvalidationEnable
=
2926 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2927 pc
.Address
= ro_bo(bo
, offset
);
2928 pc
.ImmediateData
= imm
;
2933 genX(init_state
)(struct iris_context
*ice
)
2935 struct pipe_context
*ctx
= &ice
->ctx
;
2937 ctx
->create_blend_state
= iris_create_blend_state
;
2938 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
2939 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
2940 ctx
->create_sampler_state
= iris_create_sampler_state
;
2941 ctx
->create_sampler_view
= iris_create_sampler_view
;
2942 ctx
->create_surface
= iris_create_surface
;
2943 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
2944 ctx
->create_compute_state
= iris_create_compute_state
;
2945 ctx
->bind_blend_state
= iris_bind_blend_state
;
2946 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
2947 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
2948 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
2949 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
2950 ctx
->bind_compute_state
= iris_bind_compute_state
;
2951 ctx
->delete_blend_state
= iris_delete_state
;
2952 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
2953 ctx
->delete_fs_state
= iris_delete_state
;
2954 ctx
->delete_rasterizer_state
= iris_delete_state
;
2955 ctx
->delete_sampler_state
= iris_delete_state
;
2956 ctx
->delete_vertex_elements_state
= iris_delete_state
;
2957 ctx
->delete_compute_state
= iris_delete_state
;
2958 ctx
->delete_tcs_state
= iris_delete_state
;
2959 ctx
->delete_tes_state
= iris_delete_state
;
2960 ctx
->delete_gs_state
= iris_delete_state
;
2961 ctx
->delete_vs_state
= iris_delete_state
;
2962 ctx
->set_blend_color
= iris_set_blend_color
;
2963 ctx
->set_clip_state
= iris_set_clip_state
;
2964 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
2965 ctx
->set_sampler_views
= iris_set_sampler_views
;
2966 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
2967 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
2968 ctx
->set_sample_mask
= iris_set_sample_mask
;
2969 ctx
->set_scissor_states
= iris_set_scissor_states
;
2970 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
2971 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
2972 ctx
->set_viewport_states
= iris_set_viewport_states
;
2973 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
2974 ctx
->surface_destroy
= iris_surface_destroy
;
2975 ctx
->draw_vbo
= iris_draw_vbo
;
2976 ctx
->launch_grid
= iris_launch_grid
;
2977 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
2978 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
2979 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
2981 ice
->vtbl
.destroy_state
= iris_destroy_state
;
2982 ice
->vtbl
.init_render_context
= iris_init_render_context
;
2983 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
2984 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
2985 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
2986 ice
->vtbl
.set_derived_program_state
= iris_set_derived_program_state
;
2987 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
2988 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
2989 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
2990 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
2991 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
2993 ice
->state
.dirty
= ~0ull;