src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_sum3] = {
  64       .name = "sum3",
  65       .slots = (int []) {
  66          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  67       },
  68    },
  69    [ppir_op_sum4] = {
  70       .name = "sum4",
  71       .slots = (int []) {
  72          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  73       },
  74    },
  75    [ppir_op_rsqrt] = {
  76       .name = "rsqrt",
  77       .slots = (int []) {
  78          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  79       },
  80    },
  81    [ppir_op_log2] = {
  82       .name = "log2",
  83       .slots = (int []) {
  84          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  85       },
  86    },
  87    [ppir_op_exp2] = {
  88       .name = "exp2",
  89       .slots = (int []) {
  90          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  91       },
  92    },
  93    [ppir_op_sqrt] = {
  94       .name = "sqrt",
  95       .slots = (int []) {
  96          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  97       },
  98    },
  99    [ppir_op_sin] = {
 100       .name = "sin",
 101       .slots = (int []) {
 102          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 103       },
 104    },
 105    [ppir_op_cos] = {
 106       .name = "cos",
 107       .slots = (int []) {
 108          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 109       },
 110    },
 111    [ppir_op_max] = {
 112       .name = "max",
 113       .slots = (int []) {
 114          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 115          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 116          PPIR_INSTR_SLOT_END
 117       },
 118    },
 119    [ppir_op_min] = {
 120       .name = "min",
 121       .slots = (int []) {
 122          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 123          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 124          PPIR_INSTR_SLOT_END
 125       },
 126    },
 127    [ppir_op_floor] = {
 128       .name = "floor",
 129       .slots = (int []) {
 130          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 131          PPIR_INSTR_SLOT_END
 132       },
 133    },
 134    [ppir_op_ceil] = {
 135       .name = "ceil",
 136       .slots = (int []) {
 137          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 138          PPIR_INSTR_SLOT_END
 139       },
 140    },
 141    [ppir_op_fract] = {
 142       .name = "fract",
 143       .slots = (int []) {
 144          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 145          PPIR_INSTR_SLOT_END
 146       },
 147    },
 148    [ppir_op_ddx] = {
 149       .name = "ddx",
 150       .slots = (int []) {
 151          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 152          PPIR_INSTR_SLOT_END
 153       },
 154    },
 155    [ppir_op_ddy] = {
 156       .name = "ddy",
 157       .slots = (int []) {
 158          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 159          PPIR_INSTR_SLOT_END
 160       },
 161    },
 162    [ppir_op_and] = {
 163       .name = "and",
 164       .slots = (int []) {
 165          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 166          PPIR_INSTR_SLOT_END
 167       },
 168    },
 169    [ppir_op_or] = {
 170       .name = "or",
 171       .slots = (int []) {
 172          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 173          PPIR_INSTR_SLOT_END
 174       },
 175    },
 176    [ppir_op_xor] = {
 177       .name = "xor",
 178       .slots = (int []) {
 179          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 180          PPIR_INSTR_SLOT_END
 181       },
 182    },
 183    [ppir_op_not] = {
 184       .name = "not",
 185       .slots = (int []) {
 186          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 187          PPIR_INSTR_SLOT_END
 188       },
 189    },
 190    [ppir_op_lt] = {
 191       .name = "lt",
 192    },
 193    [ppir_op_le] = {
 194       .name = "le",
 195    },
 196    [ppir_op_gt] = {
 197       .name = "gt",
 198       .slots = (int []) {
 199          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 200          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 201          PPIR_INSTR_SLOT_END
 202       },
 203    },
 204    [ppir_op_ge] = {
 205       .name = "ge",
 206       .slots = (int []) {
 207          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 208          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 209          PPIR_INSTR_SLOT_END
 210       },
 211    },
 212    [ppir_op_eq] = {
 213       .name = "eq",
 214       .slots = (int []) {
 215          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 216          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 217          PPIR_INSTR_SLOT_END
 218       },
 219    },
 220    [ppir_op_ne] = {
 221       .name = "ne",
 222       .slots = (int []) {
 223          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 224          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 225          PPIR_INSTR_SLOT_END
 226       },
 227    },
 228    [ppir_op_sel_cond] = {
 229       /* effectively mov, but must be scheduled only to
 230        * PPIR_INSTR_SLOT_ALU_SCL_MUL */
 231       .name = "sel_cond",
 232       .slots = (int []) {
 233          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
 234       },
 235    },
 236    [ppir_op_select] = {
 237       .name = "select",
 238       .slots = (int []) {
 239          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 240          PPIR_INSTR_SLOT_END
 241       },
 242    },
 243    [ppir_op_rcp] = {
 244       .name = "rcp",
 245       .slots = (int []) {
 246          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 247       },
 248    },
 249    [ppir_op_load_varying] = {
 250       .name = "ld_var",
 251       .type = ppir_node_type_load,
 252       .slots = (int []) {
 253          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 254       },
 255    },
 256    [ppir_op_load_coords] = {
 257       .name = "ld_coords",
 258       .type = ppir_node_type_load,
 259       .slots = (int []) {
 260          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 261       },
 262    },
 263    [ppir_op_load_fragcoord] = {
 264       .name = "ld_fragcoord",
 265       .type = ppir_node_type_load,
 266       .slots = (int []) {
 267          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 268       },
 269    },
 270    [ppir_op_load_pointcoord] = {
 271       .name = "ld_pointcoord",
 272       .type = ppir_node_type_load,
 273       .slots = (int []) {
 274          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 275       },
 276    },
 277    [ppir_op_load_frontface] = {
 278       .name = "ld_frontface",
 279       .type = ppir_node_type_load,
 280       .slots = (int []) {
 281          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 282       },
 283    },
 284    [ppir_op_load_uniform] = {
 285       .name = "ld_uni",
 286       .type = ppir_node_type_load,
 287       .slots = (int []) {
 288          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 289       },
 290    },
 291    [ppir_op_load_texture] = {
 292       .name = "ld_tex",
 293       .type = ppir_node_type_load_texture,
 294       .slots = (int []) {
 295          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 296       },
 297    },
 298    [ppir_op_load_temp] = {
 299       .name = "ld_temp",
 300       .type = ppir_node_type_load,
 301       .slots = (int []) {
 302          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 303       },
 304    },
 305    [ppir_op_const] = {
 306       .name = "const",
 307       .type = ppir_node_type_const,
 308    },
 309    [ppir_op_store_color] = {
 310       .name = "st_col",
 311       .type = ppir_node_type_store,
 312    },
 313    [ppir_op_store_temp] = {
 314       .name = "st_temp",
 315       .type = ppir_node_type_store,
 316       .slots = (int []) {
 317          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 318       },
 319    },
 320    [ppir_op_discard] = {
 321       .name = "discard",
 322       .type = ppir_node_type_discard,
 323       .slots = (int []) {
 324          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 325       },
 326    },
 327    [ppir_op_branch] = {
 328       .name = "branch",
 329       .type = ppir_node_type_branch,
 330       .slots = (int []) {
 331          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 332       },
 333    },
 334    [ppir_op_dummy] = {
 335       .name = "dummy",
 336       .type = ppir_node_type_alu,
 337       .slots = (int []) {
 338       },
 339    },
 340 };
 341
 342 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 343 {
 344    ppir_compiler *comp = block->comp;
 345    static const int node_size[] = {
 346       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 347       [ppir_node_type_const] = sizeof(ppir_const_node),
 348       [ppir_node_type_load] = sizeof(ppir_load_node),
 349       [ppir_node_type_store] = sizeof(ppir_store_node),
 350       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 351       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 352       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 353    };
 354
 355    ppir_node_type type = ppir_op_infos[op].type;
 356    int size = node_size[type];
 357    ppir_node *node = rzalloc_size(block, size);
 358    if (!node)
 359       return NULL;
 360
 361    list_inithead(&node->succ_list);
 362    list_inithead(&node->pred_list);
 363
 364    if (index >= 0) {
 365       if (mask) {
 366          /* reg has 4 slots for each componemt write node */
 367          while (mask)
 368             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 369          snprintf(node->name, sizeof(node->name), "reg%d", index);
 370       } else {
 371          comp->var_nodes[index] = node;
 372          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 373       }
 374    }
 375    else
 376       snprintf(node->name, sizeof(node->name), "new");
 377
 378    node->op = op;
 379    node->type = type;
 380    node->index = comp->cur_index++;
 381    node->block = block;
 382
 383    return node;
 384 }
 385
 386 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred)
 387 {
 388    /* don't add dep for two nodes from different block */
 389    if (succ->block != pred->block)
 390       return;
 391
 392    /* don't add duplicated dep */
 393    ppir_node_foreach_pred(succ, dep) {
 394       if (dep->pred == pred)
 395          return;
 396    }
 397
 398    ppir_dep *dep = ralloc(succ, ppir_dep);
 399    dep->pred = pred;
 400    dep->succ = succ;
 401    list_addtail(&dep->pred_link, &succ->pred_list);
 402    list_addtail(&dep->succ_link, &pred->succ_list);
 403 }
 404
 405 void ppir_node_remove_dep(ppir_dep *dep)
 406 {
 407    list_del(&dep->succ_link);
 408    list_del(&dep->pred_link);
 409    ralloc_free(dep);
 410 }
 411
 412 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 413 {
 414    ppir_dest *od = ppir_node_get_dest(old_child);
 415    if (ppir_node_target_equal(src, od)) {
 416       ppir_node_target_assign(src, new_child);
 417    }
 418 }
 419
 420 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 421 {
 422    switch (parent->type) {
 423    case ppir_node_type_alu:
 424    {
 425       ppir_alu_node *alu = ppir_node_to_alu(parent);
 426       for (int i = 0; i < alu->num_src; i++)
 427          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 428       break;
 429    }
 430    case ppir_node_type_branch:
 431    {
 432       ppir_branch_node *branch = ppir_node_to_branch(parent);
 433       for (int i = 0; i < 2; i++)
 434          _ppir_node_replace_child(branch->src + i, old_child, new_child);
 435       break;
 436    }
 437    case ppir_node_type_load:
 438    {
 439       ppir_load_node *load = ppir_node_to_load(parent);
 440       _ppir_node_replace_child(&load->src, old_child, new_child);
 441       break;
 442    }
 443    case ppir_node_type_load_texture:
 444    {
 445       ppir_load_texture_node *load_texture = ppir_node_to_load_texture(parent);
 446       _ppir_node_replace_child(&load_texture->src_coords, old_child, new_child);
 447       break;
 448    }
 449    case ppir_node_type_store:
 450    {
 451       ppir_store_node *store = ppir_node_to_store(parent);
 452       _ppir_node_replace_child(&store->src, old_child, new_child);
 453       break;
 454    }
 455    default:
 456       ppir_debug("unknown node type in %s\n", __func__);
 457       break;
 458    }
 459 }
 460
 461 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 462 {
 463    list_del(&dep->succ_link);
 464    dep->pred = new_pred;
 465    list_addtail(&dep->succ_link, &new_pred->succ_list);
 466 }
 467
 468 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 469 {
 470    ppir_node_foreach_succ_safe(src, dep) {
 471       ppir_node_replace_pred(dep, dst);
 472       ppir_node_replace_child(dep->succ, src, dst);
 473    }
 474 }
 475
 476 void ppir_node_delete(ppir_node *node)
 477 {
 478    ppir_node_foreach_succ_safe(node, dep)
 479       ppir_node_remove_dep(dep);
 480
 481    ppir_node_foreach_pred_safe(node, dep)
 482       ppir_node_remove_dep(dep);
 483
 484    list_del(&node->list);
 485    ralloc_free(node);
 486 }
 487
 488 static void ppir_node_print_dest(ppir_dest *dest)
 489 {
 490    switch (dest->type) {
 491    case ppir_target_ssa:
 492       printf("ssa%d", dest->ssa.index);
 493       break;
 494    case ppir_target_pipeline:
 495       printf("pipeline %d", dest->pipeline);
 496       break;
 497    case ppir_target_register:
 498       printf("reg %d", dest->reg->index);
 499       break;
 500    }
 501 }
 502
 503 static void ppir_node_print_src(ppir_src *src)
 504 {
 505    switch (src->type) {
 506    case ppir_target_ssa: {
 507       if (src->node)
 508          printf("ssa node %d", src->node->index);
 509       else
 510          printf("ssa idx %d", src->ssa ? src->ssa->index : -1);
 511       break;
 512    }
 513    case ppir_target_pipeline:
 514       if (src->node)
 515          printf("pipeline %d node %d", src->pipeline, src->node->index);
 516       else
 517          printf("pipeline %d", src->pipeline);
 518       break;
 519    case ppir_target_register:
 520       printf("reg %d", src->reg->index);
 521       break;
 522    }
 523 }
 524
 525 static void ppir_node_print_node(ppir_node *node, int space)
 526 {
 527    for (int i = 0; i < space; i++)
 528       printf(" ");
 529
 530    printf("%s%d: %s %s: ", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 531           node->index, ppir_op_infos[node->op].name, node->name);
 532
 533    ppir_dest *dest = ppir_node_get_dest(node);
 534    if (dest) {
 535       printf("dest: ");
 536       ppir_node_print_dest(dest);
 537    }
 538
 539    if (ppir_node_get_src_num(node) > 0) {
 540       printf(" src: ");
 541    }
 542    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 543       ppir_node_print_src(ppir_node_get_src(node, i));
 544       if (i != (ppir_node_get_src_num(node) - 1))
 545          printf(", ");
 546    }
 547    printf("\n");
 548
 549    if (!node->printed) {
 550       ppir_node_foreach_pred(node, dep) {
 551          ppir_node *pred = dep->pred;
 552          ppir_node_print_node(pred, space + 2);
 553       }
 554
 555       node->printed = true;
 556    }
 557 }
 558
 559 void ppir_node_print_prog(ppir_compiler *comp)
 560 {
 561    if (!(lima_debug & LIMA_DEBUG_PP))
 562       return;
 563
 564    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 565       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 566          node->printed = false;
 567       }
 568    }
 569
 570    printf("========prog========\n");
 571    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 572       printf("-------block------\n");
 573       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 574          if (ppir_node_is_root(node))
 575             ppir_node_print_node(node, 0);
 576       }
 577    }
 578    printf("====================\n");
 579 }
 580
 581 static ppir_node *ppir_node_clone_const(ppir_block *block, ppir_node *node)
 582 {
 583    ppir_const_node *cnode = ppir_node_to_const(node);
 584    ppir_const_node *new_cnode = ppir_node_create(block, ppir_op_const, -1, 0);
 585
 586    if (!new_cnode)
 587       return NULL;
 588
 589    list_addtail(&new_cnode->node.list, &block->node_list);
 590
 591    new_cnode->constant.num = cnode->constant.num;
 592    for (int i = 0; i < cnode->constant.num; i++) {
 593       new_cnode->constant.value[i] = cnode->constant.value[i];
 594    }
 595    new_cnode->dest.type = ppir_target_ssa;
 596    new_cnode->dest.ssa.num_components = cnode->dest.ssa.num_components;
 597    new_cnode->dest.ssa.live_in = INT_MAX;
 598    new_cnode->dest.ssa.live_out = 0;
 599    new_cnode->dest.write_mask = cnode->dest.write_mask;
 600
 601    return &new_cnode->node;
 602 }
 603
 604 static ppir_node *
 605 ppir_node_clone_tex(ppir_block *block, ppir_node *node)
 606 {
 607    ppir_load_texture_node *tex_node = ppir_node_to_load_texture(node);
 608    ppir_load_texture_node *new_tnode = ppir_node_create(block, ppir_op_load_texture, -1, 0);
 609
 610    if (!new_tnode)
 611       return NULL;
 612
 613    list_addtail(&new_tnode->node.list, &block->node_list);
 614
 615    ppir_dest *dest = ppir_node_get_dest(node);
 616    new_tnode->dest = *dest;
 617
 618    new_tnode->sampler_dim = tex_node->sampler_dim;
 619
 620    for (int i = 0; i < 4; i++)
 621       new_tnode->src_coords.swizzle[i] = tex_node->src_coords.swizzle[i];
 622
 623    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 624       ppir_src *src = ppir_node_get_src(node, i);
 625       ppir_src *new_src = ppir_node_get_src(&new_tnode->node, i);
 626       switch (src->type) {
 627       case ppir_target_ssa: {
 628          ppir_node_target_assign(new_src, src->node);
 629          ppir_node_add_dep(&new_tnode->node, src->node);
 630          break;
 631       }
 632       case ppir_target_register: {
 633          new_src->type = src->type;
 634          new_src->reg = src->reg;
 635          new_src->node = NULL;
 636          break;
 637       }
 638       default:
 639          /* pipeline is not expected here */
 640          assert(0);
 641       }
 642    }
 643
 644    return &new_tnode->node;
 645 }
 646
 647 static ppir_node *
 648 ppir_node_clone_load(ppir_block *block, ppir_node *node)
 649 {
 650    ppir_load_node *load_node = ppir_node_to_load(node);
 651    ppir_load_node *new_lnode = ppir_node_create(block, node->op, -1, 0);
 652
 653    if (!new_lnode)
 654       return NULL;
 655
 656    list_addtail(&new_lnode->node.list, &block->node_list);
 657
 658    new_lnode->num_components = load_node->num_components;
 659    new_lnode->index = load_node->index;
 660
 661    ppir_dest *dest = ppir_node_get_dest(node);
 662    new_lnode->dest = *dest;
 663
 664    return &new_lnode->node;
 665 }
 666
 667 ppir_node *ppir_node_clone(ppir_block *block, ppir_node *node)
 668 {
 669    switch (node->op) {
 670    case ppir_op_const:
 671       return ppir_node_clone_const(block, node);
 672    case ppir_op_load_texture:
 673       return ppir_node_clone_tex(block, node);
 674    case ppir_op_load_uniform:
 675    case ppir_op_load_varying:
 676    case ppir_op_load_temp:
 677       return ppir_node_clone_load(block, node);
 678    default:
 679       return NULL;
 680    }
 681 }