src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_sum3] = {
  64       .name = "sum3",
  65       .slots = (int []) {
  66          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  67       },
  68    },
  69    [ppir_op_sum4] = {
  70       .name = "sum4",
  71       .slots = (int []) {
  72          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  73       },
  74    },
  75    [ppir_op_rsqrt] = {
  76       .name = "rsqrt",
  77       .slots = (int []) {
  78          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  79       },
  80    },
  81    [ppir_op_log2] = {
  82       .name = "log2",
  83       .slots = (int []) {
  84          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  85       },
  86    },
  87    [ppir_op_exp2] = {
  88       .name = "exp2",
  89       .slots = (int []) {
  90          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  91       },
  92    },
  93    [ppir_op_sqrt] = {
  94       .name = "sqrt",
  95       .slots = (int []) {
  96          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  97       },
  98    },
  99    [ppir_op_sin] = {
 100       .name = "sin",
 101       .slots = (int []) {
 102          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 103       },
 104    },
 105    [ppir_op_cos] = {
 106       .name = "cos",
 107       .slots = (int []) {
 108          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 109       },
 110    },
 111    [ppir_op_max] = {
 112       .name = "max",
 113       .slots = (int []) {
 114          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 115          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 116          PPIR_INSTR_SLOT_END
 117       },
 118    },
 119    [ppir_op_min] = {
 120       .name = "min",
 121       .slots = (int []) {
 122          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 123          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 124          PPIR_INSTR_SLOT_END
 125       },
 126    },
 127    [ppir_op_floor] = {
 128       .name = "floor",
 129       .slots = (int []) {
 130          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 131          PPIR_INSTR_SLOT_END
 132       },
 133    },
 134    [ppir_op_ceil] = {
 135       .name = "ceil",
 136       .slots = (int []) {
 137          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 138          PPIR_INSTR_SLOT_END
 139       },
 140    },
 141    [ppir_op_fract] = {
 142       .name = "fract",
 143       .slots = (int []) {
 144          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 145          PPIR_INSTR_SLOT_END
 146       },
 147    },
 148    [ppir_op_and] = {
 149       .name = "and",
 150       .slots = (int []) {
 151          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 152          PPIR_INSTR_SLOT_END
 153       },
 154    },
 155    [ppir_op_or] = {
 156       .name = "or",
 157       .slots = (int []) {
 158          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 159          PPIR_INSTR_SLOT_END
 160       },
 161    },
 162    [ppir_op_xor] = {
 163       .name = "xor",
 164       .slots = (int []) {
 165          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 166          PPIR_INSTR_SLOT_END
 167       },
 168    },
 169    [ppir_op_not] = {
 170       .name = "not",
 171       .slots = (int []) {
 172          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 173          PPIR_INSTR_SLOT_END
 174       },
 175    },
 176    [ppir_op_lt] = {
 177       .name = "lt",
 178    },
 179    [ppir_op_le] = {
 180       .name = "le",
 181    },
 182    [ppir_op_gt] = {
 183       .name = "gt",
 184       .slots = (int []) {
 185          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 186          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 187          PPIR_INSTR_SLOT_END
 188       },
 189    },
 190    [ppir_op_ge] = {
 191       .name = "ge",
 192       .slots = (int []) {
 193          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 194          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 195          PPIR_INSTR_SLOT_END
 196       },
 197    },
 198    [ppir_op_eq] = {
 199       .name = "eq",
 200       .slots = (int []) {
 201          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 202          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 203          PPIR_INSTR_SLOT_END
 204       },
 205    },
 206    [ppir_op_ne] = {
 207       .name = "ne",
 208       .slots = (int []) {
 209          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 210          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 211          PPIR_INSTR_SLOT_END
 212       },
 213    },
 214    [ppir_op_sel_cond] = {
 215       /* effectively mov, but must be scheduled only to
 216        * PPIR_INSTR_SLOT_ALU_SCL_MUL */
 217       .name = "sel_cond",
 218       .slots = (int []) {
 219          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
 220       },
 221    },
 222    [ppir_op_select] = {
 223       .name = "select",
 224       .slots = (int []) {
 225          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 226          PPIR_INSTR_SLOT_END
 227       },
 228    },
 229    [ppir_op_rcp] = {
 230       .name = "rcp",
 231       .slots = (int []) {
 232          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 233       },
 234    },
 235    [ppir_op_load_varying] = {
 236       .name = "ld_var",
 237       .type = ppir_node_type_load,
 238       .slots = (int []) {
 239          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 240       },
 241    },
 242    [ppir_op_load_coords] = {
 243       .name = "ld_coords",
 244       .type = ppir_node_type_load,
 245       .slots = (int []) {
 246          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 247       },
 248    },
 249    [ppir_op_load_fragcoord] = {
 250       .name = "ld_fragcoord",
 251       .type = ppir_node_type_load,
 252       .slots = (int []) {
 253          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 254       },
 255    },
 256    [ppir_op_load_pointcoord] = {
 257       .name = "ld_pointcoord",
 258       .type = ppir_node_type_load,
 259       .slots = (int []) {
 260          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 261       },
 262    },
 263    [ppir_op_load_frontface] = {
 264       .name = "ld_frontface",
 265       .type = ppir_node_type_load,
 266       .slots = (int []) {
 267          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 268       },
 269    },
 270    [ppir_op_load_uniform] = {
 271       .name = "ld_uni",
 272       .type = ppir_node_type_load,
 273       .slots = (int []) {
 274          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 275       },
 276    },
 277    [ppir_op_load_texture] = {
 278       .name = "ld_tex",
 279       .type = ppir_node_type_load_texture,
 280       .slots = (int []) {
 281          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 282       },
 283    },
 284    [ppir_op_load_temp] = {
 285       .name = "ld_temp",
 286       .type = ppir_node_type_load,
 287       .slots = (int []) {
 288          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 289       },
 290    },
 291    [ppir_op_const] = {
 292       .name = "const",
 293       .type = ppir_node_type_const,
 294    },
 295    [ppir_op_store_color] = {
 296       .name = "st_col",
 297       .type = ppir_node_type_store,
 298    },
 299    [ppir_op_store_temp] = {
 300       .name = "st_temp",
 301       .type = ppir_node_type_store,
 302       .slots = (int []) {
 303          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 304       },
 305    },
 306    [ppir_op_discard] = {
 307       .name = "discard",
 308       .type = ppir_node_type_discard,
 309       .slots = (int []) {
 310          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 311       },
 312    },
 313    [ppir_op_branch] = {
 314       .name = "branch",
 315       .type = ppir_node_type_branch,
 316       .slots = (int []) {
 317          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 318       },
 319    },
 320 };
 321
 322 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 323 {
 324    ppir_compiler *comp = block->comp;
 325    static const int node_size[] = {
 326       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 327       [ppir_node_type_const] = sizeof(ppir_const_node),
 328       [ppir_node_type_load] = sizeof(ppir_load_node),
 329       [ppir_node_type_store] = sizeof(ppir_store_node),
 330       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 331       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 332       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 333    };
 334
 335    ppir_node_type type = ppir_op_infos[op].type;
 336    int size = node_size[type];
 337    ppir_node *node = rzalloc_size(block, size);
 338    if (!node)
 339       return NULL;
 340
 341    list_inithead(&node->succ_list);
 342    list_inithead(&node->pred_list);
 343
 344    if (index >= 0) {
 345       if (mask) {
 346          /* reg has 4 slots for each componemt write node */
 347          while (mask)
 348             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 349          snprintf(node->name, sizeof(node->name), "reg%d", index);
 350       } else {
 351          comp->var_nodes[index] = node;
 352          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 353       }
 354    }
 355    else
 356       snprintf(node->name, sizeof(node->name), "new");
 357
 358    node->op = op;
 359    node->type = type;
 360    node->index = comp->cur_index++;
 361    node->block = block;
 362
 363    return node;
 364 }
 365
 366 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred)
 367 {
 368    /* don't add dep for two nodes from different block */
 369    if (succ->block != pred->block)
 370       return;
 371
 372    /* don't add duplicated dep */
 373    ppir_node_foreach_pred(succ, dep) {
 374       if (dep->pred == pred)
 375          return;
 376    }
 377
 378    ppir_dep *dep = ralloc(succ, ppir_dep);
 379    dep->pred = pred;
 380    dep->succ = succ;
 381    list_addtail(&dep->pred_link, &succ->pred_list);
 382    list_addtail(&dep->succ_link, &pred->succ_list);
 383 }
 384
 385 void ppir_node_remove_dep(ppir_dep *dep)
 386 {
 387    list_del(&dep->succ_link);
 388    list_del(&dep->pred_link);
 389    ralloc_free(dep);
 390 }
 391
 392 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 393 {
 394    ppir_dest *od = ppir_node_get_dest(old_child);
 395    if (ppir_node_target_equal(src, od)) {
 396       ppir_dest *nd = ppir_node_get_dest(new_child);
 397       ppir_node_target_assign(src, nd);
 398    }
 399 }
 400
 401 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 402 {
 403    switch (parent->type) {
 404    case ppir_node_type_alu:
 405    {
 406       ppir_alu_node *alu = ppir_node_to_alu(parent);
 407       for (int i = 0; i < alu->num_src; i++)
 408          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 409       break;
 410    }
 411    case ppir_node_type_branch:
 412    {
 413       ppir_branch_node *branch = ppir_node_to_branch(parent);
 414       for (int i = 0; i < 2; i++)
 415          _ppir_node_replace_child(branch->src + i, old_child, new_child);
 416       break;
 417    }
 418    case ppir_node_type_load:
 419    {
 420       ppir_load_node *load = ppir_node_to_load(parent);
 421       _ppir_node_replace_child(&load->src, old_child, new_child);
 422       break;
 423    }
 424    case ppir_node_type_load_texture:
 425    {
 426       ppir_load_texture_node *load_texture = ppir_node_to_load_texture(parent);
 427       _ppir_node_replace_child(&load_texture->src_coords, old_child, new_child);
 428       break;
 429    }
 430    case ppir_node_type_store:
 431    {
 432       ppir_store_node *store = ppir_node_to_store(parent);
 433       _ppir_node_replace_child(&store->src, old_child, new_child);
 434       break;
 435    }
 436    default:
 437       ppir_debug("unknown node type in %s\n", __func__);
 438       break;
 439    }
 440 }
 441
 442 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 443 {
 444    list_del(&dep->succ_link);
 445    dep->pred = new_pred;
 446    list_addtail(&dep->succ_link, &new_pred->succ_list);
 447 }
 448
 449 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 450 {
 451    ppir_node_foreach_succ_safe(src, dep) {
 452       ppir_node_replace_pred(dep, dst);
 453       ppir_node_replace_child(dep->succ, src, dst);
 454    }
 455 }
 456
 457 void ppir_node_delete(ppir_node *node)
 458 {
 459    ppir_node_foreach_succ_safe(node, dep)
 460       ppir_node_remove_dep(dep);
 461
 462    ppir_node_foreach_pred_safe(node, dep)
 463       ppir_node_remove_dep(dep);
 464
 465    list_del(&node->list);
 466    ralloc_free(node);
 467 }
 468
 469 static void ppir_node_print_node(ppir_node *node, int space)
 470 {
 471    for (int i = 0; i < space; i++)
 472       printf(" ");
 473    printf("%s%s %d %s\n", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 474           ppir_op_infos[node->op].name, node->index, node->name);
 475
 476    if (!node->printed) {
 477       ppir_node_foreach_pred(node, dep) {
 478          ppir_node *pred = dep->pred;
 479          ppir_node_print_node(pred, space + 2);
 480       }
 481
 482       node->printed = true;
 483    }
 484 }
 485
 486 void ppir_node_print_prog(ppir_compiler *comp)
 487 {
 488    if (!(lima_debug & LIMA_DEBUG_PP))
 489       return;
 490
 491    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 492       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 493          node->printed = false;
 494       }
 495    }
 496
 497    printf("========prog========\n");
 498    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 499       printf("-------block------\n");
 500       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 501          if (ppir_node_is_root(node))
 502             ppir_node_print_node(node, 0);
 503       }
 504    }
 505    printf("====================\n");
 506 }