src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_sum3] = {
  64       .name = "sum3",
  65       .slots = (int []) {
  66          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  67       },
  68    },
  69    [ppir_op_sum4] = {
  70       .name = "sum4",
  71       .slots = (int []) {
  72          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  73       },
  74    },
  75    [ppir_op_rsqrt] = {
  76       .name = "rsqrt",
  77       .slots = (int []) {
  78          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  79       },
  80    },
  81    [ppir_op_log2] = {
  82       .name = "log2",
  83       .slots = (int []) {
  84          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  85       },
  86    },
  87    [ppir_op_exp2] = {
  88       .name = "exp2",
  89       .slots = (int []) {
  90          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  91       },
  92    },
  93    [ppir_op_sqrt] = {
  94       .name = "sqrt",
  95       .slots = (int []) {
  96          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  97       },
  98    },
  99    [ppir_op_sin] = {
 100       .name = "sin",
 101       .slots = (int []) {
 102          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 103       },
 104    },
 105    [ppir_op_cos] = {
 106       .name = "cos",
 107       .slots = (int []) {
 108          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 109       },
 110    },
 111    [ppir_op_max] = {
 112       .name = "max",
 113       .slots = (int []) {
 114          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 115          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 116          PPIR_INSTR_SLOT_END
 117       },
 118    },
 119    [ppir_op_min] = {
 120       .name = "min",
 121       .slots = (int []) {
 122          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 123          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 124          PPIR_INSTR_SLOT_END
 125       },
 126    },
 127    [ppir_op_floor] = {
 128       .name = "floor",
 129       .slots = (int []) {
 130          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 131          PPIR_INSTR_SLOT_END
 132       },
 133    },
 134    [ppir_op_ceil] = {
 135       .name = "ceil",
 136       .slots = (int []) {
 137          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 138          PPIR_INSTR_SLOT_END
 139       },
 140    },
 141    [ppir_op_fract] = {
 142       .name = "fract",
 143       .slots = (int []) {
 144          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 145          PPIR_INSTR_SLOT_END
 146       },
 147    },
 148    [ppir_op_ddx] = {
 149       .name = "ddx",
 150       .slots = (int []) {
 151          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 152          PPIR_INSTR_SLOT_END
 153       },
 154    },
 155    [ppir_op_ddy] = {
 156       .name = "ddy",
 157       .slots = (int []) {
 158          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 159          PPIR_INSTR_SLOT_END
 160       },
 161    },
 162    [ppir_op_and] = {
 163       .name = "and",
 164       .slots = (int []) {
 165          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 166          PPIR_INSTR_SLOT_END
 167       },
 168    },
 169    [ppir_op_or] = {
 170       .name = "or",
 171       .slots = (int []) {
 172          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 173          PPIR_INSTR_SLOT_END
 174       },
 175    },
 176    [ppir_op_xor] = {
 177       .name = "xor",
 178       .slots = (int []) {
 179          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 180          PPIR_INSTR_SLOT_END
 181       },
 182    },
 183    [ppir_op_not] = {
 184       .name = "not",
 185       .slots = (int []) {
 186          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 187          PPIR_INSTR_SLOT_END
 188       },
 189    },
 190    [ppir_op_lt] = {
 191       .name = "lt",
 192    },
 193    [ppir_op_le] = {
 194       .name = "le",
 195    },
 196    [ppir_op_gt] = {
 197       .name = "gt",
 198       .slots = (int []) {
 199          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 200          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 201          PPIR_INSTR_SLOT_END
 202       },
 203    },
 204    [ppir_op_ge] = {
 205       .name = "ge",
 206       .slots = (int []) {
 207          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 208          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 209          PPIR_INSTR_SLOT_END
 210       },
 211    },
 212    [ppir_op_eq] = {
 213       .name = "eq",
 214       .slots = (int []) {
 215          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 216          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 217          PPIR_INSTR_SLOT_END
 218       },
 219    },
 220    [ppir_op_ne] = {
 221       .name = "ne",
 222       .slots = (int []) {
 223          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 224          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 225          PPIR_INSTR_SLOT_END
 226       },
 227    },
 228    [ppir_op_sel_cond] = {
 229       /* effectively mov, but must be scheduled only to
 230        * PPIR_INSTR_SLOT_ALU_SCL_MUL */
 231       .name = "sel_cond",
 232       .slots = (int []) {
 233          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
 234       },
 235    },
 236    [ppir_op_select] = {
 237       .name = "select",
 238       .slots = (int []) {
 239          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 240          PPIR_INSTR_SLOT_END
 241       },
 242    },
 243    [ppir_op_rcp] = {
 244       .name = "rcp",
 245       .slots = (int []) {
 246          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 247       },
 248    },
 249    [ppir_op_load_varying] = {
 250       .name = "ld_var",
 251       .type = ppir_node_type_load,
 252       .slots = (int []) {
 253          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 254       },
 255    },
 256    [ppir_op_load_coords] = {
 257       .name = "ld_coords",
 258       .type = ppir_node_type_load,
 259       .slots = (int []) {
 260          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 261       },
 262    },
 263    [ppir_op_load_coords_reg] = {
 264       .name = "ld_coords_reg",
 265       .type = ppir_node_type_load,
 266       .slots = (int []) {
 267          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 268       },
 269    },
 270    [ppir_op_load_fragcoord] = {
 271       .name = "ld_fragcoord",
 272       .type = ppir_node_type_load,
 273       .slots = (int []) {
 274          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 275       },
 276    },
 277    [ppir_op_load_pointcoord] = {
 278       .name = "ld_pointcoord",
 279       .type = ppir_node_type_load,
 280       .slots = (int []) {
 281          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 282       },
 283    },
 284    [ppir_op_load_frontface] = {
 285       .name = "ld_frontface",
 286       .type = ppir_node_type_load,
 287       .slots = (int []) {
 288          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 289       },
 290    },
 291    [ppir_op_load_uniform] = {
 292       .name = "ld_uni",
 293       .type = ppir_node_type_load,
 294       .slots = (int []) {
 295          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 296       },
 297    },
 298    [ppir_op_load_texture] = {
 299       .name = "ld_tex",
 300       .type = ppir_node_type_load_texture,
 301       .slots = (int []) {
 302          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 303       },
 304    },
 305    [ppir_op_load_temp] = {
 306       .name = "ld_temp",
 307       .type = ppir_node_type_load,
 308       .slots = (int []) {
 309          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 310       },
 311    },
 312    [ppir_op_const] = {
 313       .name = "const",
 314       .type = ppir_node_type_const,
 315    },
 316    [ppir_op_store_temp] = {
 317       .name = "st_temp",
 318       .type = ppir_node_type_store,
 319       .slots = (int []) {
 320          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 321       },
 322    },
 323    [ppir_op_discard] = {
 324       .name = "discard",
 325       .type = ppir_node_type_discard,
 326       .slots = (int []) {
 327          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 328       },
 329    },
 330    [ppir_op_branch] = {
 331       .name = "branch",
 332       .type = ppir_node_type_branch,
 333       .slots = (int []) {
 334          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 335       },
 336    },
 337    [ppir_op_undef] = {
 338       .name = "undef",
 339       .type = ppir_node_type_alu,
 340       .slots = (int []) {
 341       },
 342    },
 343    [ppir_op_dummy] = {
 344       .name = "dummy",
 345       .type = ppir_node_type_alu,
 346       .slots = (int []) {
 347       },
 348    },
 349 };
 350
 351 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 352 {
 353    ppir_compiler *comp = block->comp;
 354    static const int node_size[] = {
 355       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 356       [ppir_node_type_const] = sizeof(ppir_const_node),
 357       [ppir_node_type_load] = sizeof(ppir_load_node),
 358       [ppir_node_type_store] = sizeof(ppir_store_node),
 359       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 360       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 361       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 362    };
 363
 364    ppir_node_type type = ppir_op_infos[op].type;
 365    int size = node_size[type];
 366    ppir_node *node = rzalloc_size(block, size);
 367    if (!node)
 368       return NULL;
 369
 370    list_inithead(&node->succ_list);
 371    list_inithead(&node->pred_list);
 372
 373    if (index >= 0) {
 374       if (mask) {
 375          /* reg has 4 slots for each componemt write node */
 376          while (mask)
 377             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 378          snprintf(node->name, sizeof(node->name), "reg%d", index);
 379       } else {
 380          comp->var_nodes[index] = node;
 381          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 382       }
 383    }
 384    else
 385       snprintf(node->name, sizeof(node->name), "new");
 386
 387    node->op = op;
 388    node->type = type;
 389    node->index = comp->cur_index++;
 390    node->block = block;
 391
 392    return node;
 393 }
 394
 395 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred,
 396                        ppir_dep_type type)
 397 {
 398    /* don't add dep for two nodes from different block */
 399    if (succ->block != pred->block)
 400       return;
 401
 402    /* don't add duplicated dep */
 403    ppir_node_foreach_pred(succ, dep) {
 404       if (dep->pred == pred)
 405          return;
 406    }
 407
 408    ppir_dep *dep = ralloc(succ, ppir_dep);
 409    dep->pred = pred;
 410    dep->succ = succ;
 411    dep->type = type;
 412    list_addtail(&dep->pred_link, &succ->pred_list);
 413    list_addtail(&dep->succ_link, &pred->succ_list);
 414 }
 415
 416 void ppir_node_remove_dep(ppir_dep *dep)
 417 {
 418    list_del(&dep->succ_link);
 419    list_del(&dep->pred_link);
 420    ralloc_free(dep);
 421 }
 422
 423 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 424 {
 425    ppir_dest *od = ppir_node_get_dest(old_child);
 426    if (ppir_node_target_equal(src, od)) {
 427       ppir_node_target_assign(src, new_child);
 428    }
 429 }
 430
 431 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 432 {
 433    switch (parent->type) {
 434    case ppir_node_type_alu:
 435    {
 436       ppir_alu_node *alu = ppir_node_to_alu(parent);
 437       for (int i = 0; i < alu->num_src; i++)
 438          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 439       break;
 440    }
 441    case ppir_node_type_branch:
 442    {
 443       ppir_branch_node *branch = ppir_node_to_branch(parent);
 444       for (int i = 0; i < 2; i++)
 445          _ppir_node_replace_child(branch->src + i, old_child, new_child);
 446       break;
 447    }
 448    case ppir_node_type_load:
 449    {
 450       ppir_load_node *load = ppir_node_to_load(parent);
 451       _ppir_node_replace_child(&load->src, old_child, new_child);
 452       break;
 453    }
 454    case ppir_node_type_load_texture:
 455    {
 456       ppir_load_texture_node *load_texture = ppir_node_to_load_texture(parent);
 457       for (int i = 0; i < load_texture->num_src; i++)
 458          _ppir_node_replace_child(ppir_node_get_src(parent, i), old_child, new_child);
 459       break;
 460    }
 461    case ppir_node_type_store:
 462    {
 463       ppir_store_node *store = ppir_node_to_store(parent);
 464       _ppir_node_replace_child(&store->src, old_child, new_child);
 465       break;
 466    }
 467    default:
 468       ppir_debug("unknown node type in %s\n", __func__);
 469       break;
 470    }
 471 }
 472
 473 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 474 {
 475    list_del(&dep->succ_link);
 476    dep->pred = new_pred;
 477    list_addtail(&dep->succ_link, &new_pred->succ_list);
 478 }
 479
 480 ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred)
 481 {
 482    if (!pred)
 483       return NULL;
 484
 485    if (node->block != pred->block)
 486       return NULL;
 487
 488    ppir_node_foreach_pred(node, dep) {
 489       if (dep->pred == pred)
 490          return dep;
 491    }
 492    return NULL;
 493 }
 494
 495 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 496 {
 497    ppir_node_foreach_succ_safe(src, dep) {
 498       ppir_node_replace_pred(dep, dst);
 499       ppir_node_replace_child(dep->succ, src, dst);
 500    }
 501 }
 502
 503 void ppir_node_delete(ppir_node *node)
 504 {
 505    ppir_node_foreach_succ_safe(node, dep)
 506       ppir_node_remove_dep(dep);
 507
 508    ppir_node_foreach_pred_safe(node, dep)
 509       ppir_node_remove_dep(dep);
 510
 511    list_del(&node->list);
 512    ralloc_free(node);
 513 }
 514
 515 static void ppir_node_print_dest(ppir_dest *dest)
 516 {
 517    switch (dest->type) {
 518    case ppir_target_ssa:
 519       printf("ssa%d", dest->ssa.index);
 520       break;
 521    case ppir_target_pipeline:
 522       printf("pipeline %d", dest->pipeline);
 523       break;
 524    case ppir_target_register:
 525       printf("reg %d", dest->reg->index);
 526       break;
 527    }
 528 }
 529
 530 static void ppir_node_print_src(ppir_src *src)
 531 {
 532    switch (src->type) {
 533    case ppir_target_ssa: {
 534       if (src->node)
 535          printf("ssa node %d", src->node->index);
 536       else
 537          printf("ssa idx %d", src->ssa ? src->ssa->index : -1);
 538       break;
 539    }
 540    case ppir_target_pipeline:
 541       if (src->node)
 542          printf("pipeline %d node %d", src->pipeline, src->node->index);
 543       else
 544          printf("pipeline %d", src->pipeline);
 545       break;
 546    case ppir_target_register:
 547       printf("reg %d", src->reg->index);
 548       break;
 549    }
 550 }
 551
 552 static void ppir_node_print_node(ppir_node *node, int space)
 553 {
 554    for (int i = 0; i < space; i++)
 555       printf(" ");
 556
 557    printf("%s%d: %s %s: ", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 558           node->index, ppir_op_infos[node->op].name, node->name);
 559
 560    ppir_dest *dest = ppir_node_get_dest(node);
 561    if (dest) {
 562       printf("dest: ");
 563       ppir_node_print_dest(dest);
 564    }
 565
 566    if (ppir_node_get_src_num(node) > 0) {
 567       printf(" src: ");
 568    }
 569    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 570       ppir_node_print_src(ppir_node_get_src(node, i));
 571       if (i != (ppir_node_get_src_num(node) - 1))
 572          printf(", ");
 573    }
 574    printf("\n");
 575
 576    if (!node->printed) {
 577       ppir_node_foreach_pred(node, dep) {
 578          ppir_node *pred = dep->pred;
 579          ppir_node_print_node(pred, space + 2);
 580       }
 581
 582       node->printed = true;
 583    }
 584 }
 585
 586 void ppir_node_print_prog(ppir_compiler *comp)
 587 {
 588    if (!(lima_debug & LIMA_DEBUG_PP))
 589       return;
 590
 591    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 592       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 593          node->printed = false;
 594       }
 595    }
 596
 597    printf("========prog========\n");
 598    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 599       printf("-------block %3d-------\n", block->index);
 600       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 601          if (ppir_node_is_root(node))
 602             ppir_node_print_node(node, 0);
 603       }
 604    }
 605    printf("====================\n");
 606 }
 607
 608 ppir_node *ppir_node_insert_mov(ppir_node *node)
 609 {
 610    ppir_node *move = ppir_node_create(node->block, ppir_op_mov, -1, 0);
 611    if (unlikely(!move))
 612       return NULL;
 613
 614    ppir_dest *dest = ppir_node_get_dest(node);
 615    ppir_alu_node *alu = ppir_node_to_alu(move);
 616    alu->dest = *dest;
 617    alu->num_src = 1;
 618    ppir_node_target_assign(alu->src, node);
 619
 620    for (int s = 0; s < 4; s++)
 621       alu->src->swizzle[s] = s;
 622
 623    ppir_node_replace_all_succ(move, node);
 624    ppir_node_add_dep(move, node, ppir_dep_src);
 625    list_addtail(&move->list, &node->list);
 626
 627    if (node->is_end) {
 628       node->is_end = false;
 629       move->is_end = true;
 630    }
 631
 632    return move;
 633 }
 634
 635 ppir_node *ppir_node_insert_mov_all_blocks(ppir_node *old)
 636 {
 637    ppir_node *move = ppir_node_insert_mov(old);
 638    ppir_compiler *comp = old->block->comp;
 639
 640    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 641       if (old->block == block)
 642          continue;
 643       list_for_each_entry_safe(ppir_node, node, &block->node_list, list) {
 644          for (int i = 0; i < ppir_node_get_src_num(node); i++){
 645             ppir_src *src = ppir_node_get_src(node, i);
 646             if (!src)
 647                continue;
 648             if (src->node == old)
 649                ppir_node_target_assign(src, move);
 650          }
 651       }
 652    }
 653
 654    return move;
 655 }
 656 bool ppir_node_has_single_src_succ(ppir_node *node)
 657 {
 658    if (list_is_singular(&node->succ_list) &&
 659        list_first_entry(&node->succ_list,
 660                         ppir_dep, succ_link)->type == ppir_dep_src)
 661       return true;
 662
 663    int cnt = 0;
 664    ppir_node_foreach_succ(node, dep) {
 665       if (dep->type != ppir_dep_src)
 666          continue;
 667       cnt++;
 668    }
 669
 670    return cnt == 1;
 671 }