src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_sum3] = {
  64       .name = "sum3",
  65       .slots = (int []) {
  66          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  67       },
  68    },
  69    [ppir_op_sum4] = {
  70       .name = "sum4",
  71       .slots = (int []) {
  72          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  73       },
  74    },
  75    [ppir_op_rsqrt] = {
  76       .name = "rsqrt",
  77       .slots = (int []) {
  78          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  79       },
  80    },
  81    [ppir_op_log2] = {
  82       .name = "log2",
  83       .slots = (int []) {
  84          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  85       },
  86    },
  87    [ppir_op_exp2] = {
  88       .name = "exp2",
  89       .slots = (int []) {
  90          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  91       },
  92    },
  93    [ppir_op_sqrt] = {
  94       .name = "sqrt",
  95       .slots = (int []) {
  96          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  97       },
  98    },
  99    [ppir_op_sin] = {
 100       .name = "sin",
 101       .slots = (int []) {
 102          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 103       },
 104    },
 105    [ppir_op_cos] = {
 106       .name = "cos",
 107       .slots = (int []) {
 108          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 109       },
 110    },
 111    [ppir_op_max] = {
 112       .name = "max",
 113       .slots = (int []) {
 114          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 115          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 116          PPIR_INSTR_SLOT_END
 117       },
 118    },
 119    [ppir_op_min] = {
 120       .name = "min",
 121       .slots = (int []) {
 122          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 123          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 124          PPIR_INSTR_SLOT_END
 125       },
 126    },
 127    [ppir_op_floor] = {
 128       .name = "floor",
 129       .slots = (int []) {
 130          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 131          PPIR_INSTR_SLOT_END
 132       },
 133    },
 134    [ppir_op_ceil] = {
 135       .name = "ceil",
 136       .slots = (int []) {
 137          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 138          PPIR_INSTR_SLOT_END
 139       },
 140    },
 141    [ppir_op_fract] = {
 142       .name = "fract",
 143       .slots = (int []) {
 144          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 145          PPIR_INSTR_SLOT_END
 146       },
 147    },
 148    [ppir_op_ddx] = {
 149       .name = "ddx",
 150       .slots = (int []) {
 151          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 152          PPIR_INSTR_SLOT_END
 153       },
 154    },
 155    [ppir_op_ddy] = {
 156       .name = "ddy",
 157       .slots = (int []) {
 158          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 159          PPIR_INSTR_SLOT_END
 160       },
 161    },
 162    [ppir_op_and] = {
 163       .name = "and",
 164       .slots = (int []) {
 165          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 166          PPIR_INSTR_SLOT_END
 167       },
 168    },
 169    [ppir_op_or] = {
 170       .name = "or",
 171       .slots = (int []) {
 172          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 173          PPIR_INSTR_SLOT_END
 174       },
 175    },
 176    [ppir_op_xor] = {
 177       .name = "xor",
 178       .slots = (int []) {
 179          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 180          PPIR_INSTR_SLOT_END
 181       },
 182    },
 183    [ppir_op_not] = {
 184       .name = "not",
 185       .slots = (int []) {
 186          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 187          PPIR_INSTR_SLOT_END
 188       },
 189    },
 190    [ppir_op_lt] = {
 191       .name = "lt",
 192    },
 193    [ppir_op_le] = {
 194       .name = "le",
 195    },
 196    [ppir_op_gt] = {
 197       .name = "gt",
 198       .slots = (int []) {
 199          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 200          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 201          PPIR_INSTR_SLOT_END
 202       },
 203    },
 204    [ppir_op_ge] = {
 205       .name = "ge",
 206       .slots = (int []) {
 207          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 208          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 209          PPIR_INSTR_SLOT_END
 210       },
 211    },
 212    [ppir_op_eq] = {
 213       .name = "eq",
 214       .slots = (int []) {
 215          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 216          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 217          PPIR_INSTR_SLOT_END
 218       },
 219    },
 220    [ppir_op_ne] = {
 221       .name = "ne",
 222       .slots = (int []) {
 223          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 224          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 225          PPIR_INSTR_SLOT_END
 226       },
 227    },
 228    [ppir_op_sel_cond] = {
 229       /* effectively mov, but must be scheduled only to
 230        * PPIR_INSTR_SLOT_ALU_SCL_MUL */
 231       .name = "sel_cond",
 232       .slots = (int []) {
 233          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
 234       },
 235    },
 236    [ppir_op_select] = {
 237       .name = "select",
 238       .slots = (int []) {
 239          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 240          PPIR_INSTR_SLOT_END
 241       },
 242    },
 243    [ppir_op_rcp] = {
 244       .name = "rcp",
 245       .slots = (int []) {
 246          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 247       },
 248    },
 249    [ppir_op_load_varying] = {
 250       .name = "ld_var",
 251       .type = ppir_node_type_load,
 252       .slots = (int []) {
 253          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 254       },
 255    },
 256    [ppir_op_load_coords] = {
 257       .name = "ld_coords",
 258       .type = ppir_node_type_load,
 259       .slots = (int []) {
 260          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 261       },
 262    },
 263    [ppir_op_load_fragcoord] = {
 264       .name = "ld_fragcoord",
 265       .type = ppir_node_type_load,
 266       .slots = (int []) {
 267          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 268       },
 269    },
 270    [ppir_op_load_pointcoord] = {
 271       .name = "ld_pointcoord",
 272       .type = ppir_node_type_load,
 273       .slots = (int []) {
 274          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 275       },
 276    },
 277    [ppir_op_load_frontface] = {
 278       .name = "ld_frontface",
 279       .type = ppir_node_type_load,
 280       .slots = (int []) {
 281          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 282       },
 283    },
 284    [ppir_op_load_uniform] = {
 285       .name = "ld_uni",
 286       .type = ppir_node_type_load,
 287       .slots = (int []) {
 288          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 289       },
 290    },
 291    [ppir_op_load_texture] = {
 292       .name = "ld_tex",
 293       .type = ppir_node_type_load_texture,
 294       .slots = (int []) {
 295          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 296       },
 297    },
 298    [ppir_op_load_temp] = {
 299       .name = "ld_temp",
 300       .type = ppir_node_type_load,
 301       .slots = (int []) {
 302          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 303       },
 304    },
 305    [ppir_op_const] = {
 306       .name = "const",
 307       .type = ppir_node_type_const,
 308    },
 309    [ppir_op_store_color] = {
 310       .name = "st_col",
 311       .type = ppir_node_type_alu,
 312       .slots = (int []) {
 313          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 314          PPIR_INSTR_SLOT_END
 315       },
 316    },
 317    [ppir_op_store_temp] = {
 318       .name = "st_temp",
 319       .type = ppir_node_type_store,
 320       .slots = (int []) {
 321          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 322       },
 323    },
 324    [ppir_op_discard] = {
 325       .name = "discard",
 326       .type = ppir_node_type_discard,
 327       .slots = (int []) {
 328          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 329       },
 330    },
 331    [ppir_op_branch] = {
 332       .name = "branch",
 333       .type = ppir_node_type_branch,
 334       .slots = (int []) {
 335          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 336       },
 337    },
 338    [ppir_op_dummy] = {
 339       .name = "dummy",
 340       .type = ppir_node_type_alu,
 341       .slots = (int []) {
 342       },
 343    },
 344 };
 345
 346 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 347 {
 348    ppir_compiler *comp = block->comp;
 349    static const int node_size[] = {
 350       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 351       [ppir_node_type_const] = sizeof(ppir_const_node),
 352       [ppir_node_type_load] = sizeof(ppir_load_node),
 353       [ppir_node_type_store] = sizeof(ppir_store_node),
 354       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 355       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 356       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 357    };
 358
 359    ppir_node_type type = ppir_op_infos[op].type;
 360    int size = node_size[type];
 361    ppir_node *node = rzalloc_size(block, size);
 362    if (!node)
 363       return NULL;
 364
 365    list_inithead(&node->succ_list);
 366    list_inithead(&node->pred_list);
 367
 368    if (index >= 0) {
 369       if (mask) {
 370          /* reg has 4 slots for each componemt write node */
 371          while (mask)
 372             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 373          snprintf(node->name, sizeof(node->name), "reg%d", index);
 374       } else {
 375          comp->var_nodes[index] = node;
 376          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 377       }
 378    }
 379    else
 380       snprintf(node->name, sizeof(node->name), "new");
 381
 382    node->op = op;
 383    node->type = type;
 384    node->index = comp->cur_index++;
 385    node->block = block;
 386
 387    return node;
 388 }
 389
 390 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred)
 391 {
 392    /* don't add dep for two nodes from different block */
 393    if (succ->block != pred->block)
 394       return;
 395
 396    /* don't add duplicated dep */
 397    ppir_node_foreach_pred(succ, dep) {
 398       if (dep->pred == pred)
 399          return;
 400    }
 401
 402    ppir_dep *dep = ralloc(succ, ppir_dep);
 403    dep->pred = pred;
 404    dep->succ = succ;
 405    list_addtail(&dep->pred_link, &succ->pred_list);
 406    list_addtail(&dep->succ_link, &pred->succ_list);
 407 }
 408
 409 void ppir_node_remove_dep(ppir_dep *dep)
 410 {
 411    list_del(&dep->succ_link);
 412    list_del(&dep->pred_link);
 413    ralloc_free(dep);
 414 }
 415
 416 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 417 {
 418    ppir_dest *od = ppir_node_get_dest(old_child);
 419    if (ppir_node_target_equal(src, od)) {
 420       ppir_node_target_assign(src, new_child);
 421    }
 422 }
 423
 424 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 425 {
 426    switch (parent->type) {
 427    case ppir_node_type_alu:
 428    {
 429       ppir_alu_node *alu = ppir_node_to_alu(parent);
 430       for (int i = 0; i < alu->num_src; i++)
 431          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 432       break;
 433    }
 434    case ppir_node_type_branch:
 435    {
 436       ppir_branch_node *branch = ppir_node_to_branch(parent);
 437       for (int i = 0; i < 2; i++)
 438          _ppir_node_replace_child(branch->src + i, old_child, new_child);
 439       break;
 440    }
 441    case ppir_node_type_load:
 442    {
 443       ppir_load_node *load = ppir_node_to_load(parent);
 444       _ppir_node_replace_child(&load->src, old_child, new_child);
 445       break;
 446    }
 447    case ppir_node_type_load_texture:
 448    {
 449       ppir_load_texture_node *load_texture = ppir_node_to_load_texture(parent);
 450       _ppir_node_replace_child(&load_texture->src_coords, old_child, new_child);
 451       break;
 452    }
 453    case ppir_node_type_store:
 454    {
 455       ppir_store_node *store = ppir_node_to_store(parent);
 456       _ppir_node_replace_child(&store->src, old_child, new_child);
 457       break;
 458    }
 459    default:
 460       ppir_debug("unknown node type in %s\n", __func__);
 461       break;
 462    }
 463 }
 464
 465 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 466 {
 467    list_del(&dep->succ_link);
 468    dep->pred = new_pred;
 469    list_addtail(&dep->succ_link, &new_pred->succ_list);
 470 }
 471
 472 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 473 {
 474    ppir_node_foreach_succ_safe(src, dep) {
 475       ppir_node_replace_pred(dep, dst);
 476       ppir_node_replace_child(dep->succ, src, dst);
 477    }
 478 }
 479
 480 void ppir_node_delete(ppir_node *node)
 481 {
 482    ppir_node_foreach_succ_safe(node, dep)
 483       ppir_node_remove_dep(dep);
 484
 485    ppir_node_foreach_pred_safe(node, dep)
 486       ppir_node_remove_dep(dep);
 487
 488    list_del(&node->list);
 489    ralloc_free(node);
 490 }
 491
 492 static void ppir_node_print_dest(ppir_dest *dest)
 493 {
 494    switch (dest->type) {
 495    case ppir_target_ssa:
 496       printf("ssa%d", dest->ssa.index);
 497       break;
 498    case ppir_target_pipeline:
 499       printf("pipeline %d", dest->pipeline);
 500       break;
 501    case ppir_target_register:
 502       printf("reg %d", dest->reg->index);
 503       break;
 504    }
 505 }
 506
 507 static void ppir_node_print_src(ppir_src *src)
 508 {
 509    switch (src->type) {
 510    case ppir_target_ssa: {
 511       if (src->node)
 512          printf("ssa node %d", src->node->index);
 513       else
 514          printf("ssa idx %d", src->ssa ? src->ssa->index : -1);
 515       break;
 516    }
 517    case ppir_target_pipeline:
 518       if (src->node)
 519          printf("pipeline %d node %d", src->pipeline, src->node->index);
 520       else
 521          printf("pipeline %d", src->pipeline);
 522       break;
 523    case ppir_target_register:
 524       printf("reg %d", src->reg->index);
 525       break;
 526    }
 527 }
 528
 529 static void ppir_node_print_node(ppir_node *node, int space)
 530 {
 531    for (int i = 0; i < space; i++)
 532       printf(" ");
 533
 534    printf("%s%d: %s %s: ", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 535           node->index, ppir_op_infos[node->op].name, node->name);
 536
 537    ppir_dest *dest = ppir_node_get_dest(node);
 538    if (dest) {
 539       printf("dest: ");
 540       ppir_node_print_dest(dest);
 541    }
 542
 543    if (ppir_node_get_src_num(node) > 0) {
 544       printf(" src: ");
 545    }
 546    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 547       ppir_node_print_src(ppir_node_get_src(node, i));
 548       if (i != (ppir_node_get_src_num(node) - 1))
 549          printf(", ");
 550    }
 551    printf("\n");
 552
 553    if (!node->printed) {
 554       ppir_node_foreach_pred(node, dep) {
 555          ppir_node *pred = dep->pred;
 556          ppir_node_print_node(pred, space + 2);
 557       }
 558
 559       node->printed = true;
 560    }
 561 }
 562
 563 void ppir_node_print_prog(ppir_compiler *comp)
 564 {
 565    if (!(lima_debug & LIMA_DEBUG_PP))
 566       return;
 567
 568    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 569       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 570          node->printed = false;
 571       }
 572    }
 573
 574    printf("========prog========\n");
 575    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 576       printf("-------block------\n");
 577       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 578          if (ppir_node_is_root(node))
 579             ppir_node_print_node(node, 0);
 580       }
 581    }
 582    printf("====================\n");
 583 }
 584
 585 static ppir_node *ppir_node_clone_const(ppir_block *block, ppir_node *node)
 586 {
 587    ppir_const_node *cnode = ppir_node_to_const(node);
 588    ppir_const_node *new_cnode = ppir_node_create(block, ppir_op_const, -1, 0);
 589
 590    if (!new_cnode)
 591       return NULL;
 592
 593    list_addtail(&new_cnode->node.list, &block->node_list);
 594
 595    new_cnode->constant.num = cnode->constant.num;
 596    for (int i = 0; i < cnode->constant.num; i++) {
 597       new_cnode->constant.value[i] = cnode->constant.value[i];
 598    }
 599    new_cnode->dest.type = ppir_target_ssa;
 600    new_cnode->dest.ssa.num_components = cnode->dest.ssa.num_components;
 601    new_cnode->dest.ssa.live_in = INT_MAX;
 602    new_cnode->dest.ssa.live_out = 0;
 603    new_cnode->dest.write_mask = cnode->dest.write_mask;
 604
 605    return &new_cnode->node;
 606 }
 607
 608 static ppir_node *
 609 ppir_node_clone_tex(ppir_block *block, ppir_node *node)
 610 {
 611    ppir_load_texture_node *tex_node = ppir_node_to_load_texture(node);
 612    ppir_load_texture_node *new_tnode = ppir_node_create(block, ppir_op_load_texture, -1, 0);
 613
 614    if (!new_tnode)
 615       return NULL;
 616
 617    list_addtail(&new_tnode->node.list, &block->node_list);
 618
 619    ppir_dest *dest = ppir_node_get_dest(node);
 620    new_tnode->dest = *dest;
 621
 622    new_tnode->sampler_dim = tex_node->sampler_dim;
 623
 624    for (int i = 0; i < 4; i++)
 625       new_tnode->src_coords.swizzle[i] = tex_node->src_coords.swizzle[i];
 626
 627    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 628       ppir_src *src = ppir_node_get_src(node, i);
 629       ppir_src *new_src = ppir_node_get_src(&new_tnode->node, i);
 630       switch (src->type) {
 631       case ppir_target_ssa: {
 632          ppir_node_target_assign(new_src, src->node);
 633          ppir_node_add_dep(&new_tnode->node, src->node);
 634          break;
 635       }
 636       case ppir_target_register: {
 637          new_src->type = src->type;
 638          new_src->reg = src->reg;
 639          new_src->node = NULL;
 640          break;
 641       }
 642       default:
 643          /* pipeline is not expected here */
 644          assert(0);
 645       }
 646    }
 647
 648    return &new_tnode->node;
 649 }
 650
 651 static ppir_node *
 652 ppir_node_clone_load(ppir_block *block, ppir_node *node)
 653 {
 654    ppir_load_node *load_node = ppir_node_to_load(node);
 655    ppir_load_node *new_lnode = ppir_node_create(block, node->op, -1, 0);
 656
 657    if (!new_lnode)
 658       return NULL;
 659
 660    list_addtail(&new_lnode->node.list, &block->node_list);
 661
 662    new_lnode->num_components = load_node->num_components;
 663    new_lnode->index = load_node->index;
 664
 665    ppir_dest *dest = ppir_node_get_dest(node);
 666    new_lnode->dest = *dest;
 667
 668    return &new_lnode->node;
 669 }
 670
 671 ppir_node *ppir_node_clone(ppir_block *block, ppir_node *node)
 672 {
 673    switch (node->op) {
 674    case ppir_op_const:
 675       return ppir_node_clone_const(block, node);
 676    case ppir_op_load_texture:
 677       return ppir_node_clone_tex(block, node);
 678    case ppir_op_load_uniform:
 679    case ppir_op_load_varying:
 680    case ppir_op_load_temp:
 681       return ppir_node_clone_load(block, node);
 682    default:
 683       return NULL;
 684    }
 685 }