src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_sum3] = {
  64       .name = "sum3",
  65       .slots = (int []) {
  66          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  67       },
  68    },
  69    [ppir_op_sum4] = {
  70       .name = "sum4",
  71       .slots = (int []) {
  72          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  73       },
  74    },
  75    [ppir_op_rsqrt] = {
  76       .name = "rsqrt",
  77       .slots = (int []) {
  78          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  79       },
  80    },
  81    [ppir_op_log2] = {
  82       .name = "log2",
  83       .slots = (int []) {
  84          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  85       },
  86    },
  87    [ppir_op_exp2] = {
  88       .name = "exp2",
  89       .slots = (int []) {
  90          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  91       },
  92    },
  93    [ppir_op_sqrt] = {
  94       .name = "sqrt",
  95       .slots = (int []) {
  96          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  97       },
  98    },
  99    [ppir_op_sin] = {
 100       .name = "sin",
 101       .slots = (int []) {
 102          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 103       },
 104    },
 105    [ppir_op_cos] = {
 106       .name = "cos",
 107       .slots = (int []) {
 108          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 109       },
 110    },
 111    [ppir_op_max] = {
 112       .name = "max",
 113       .slots = (int []) {
 114          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 115          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 116          PPIR_INSTR_SLOT_END
 117       },
 118    },
 119    [ppir_op_min] = {
 120       .name = "min",
 121       .slots = (int []) {
 122          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 123          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 124          PPIR_INSTR_SLOT_END
 125       },
 126    },
 127    [ppir_op_floor] = {
 128       .name = "floor",
 129       .slots = (int []) {
 130          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 131          PPIR_INSTR_SLOT_END
 132       },
 133    },
 134    [ppir_op_ceil] = {
 135       .name = "ceil",
 136       .slots = (int []) {
 137          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 138          PPIR_INSTR_SLOT_END
 139       },
 140    },
 141    [ppir_op_fract] = {
 142       .name = "fract",
 143       .slots = (int []) {
 144          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 145          PPIR_INSTR_SLOT_END
 146       },
 147    },
 148    [ppir_op_ddx] = {
 149       .name = "ddx",
 150       .slots = (int []) {
 151          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 152          PPIR_INSTR_SLOT_END
 153       },
 154    },
 155    [ppir_op_ddy] = {
 156       .name = "ddy",
 157       .slots = (int []) {
 158          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 159          PPIR_INSTR_SLOT_END
 160       },
 161    },
 162    [ppir_op_and] = {
 163       .name = "and",
 164       .slots = (int []) {
 165          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 166          PPIR_INSTR_SLOT_END
 167       },
 168    },
 169    [ppir_op_or] = {
 170       .name = "or",
 171       .slots = (int []) {
 172          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 173          PPIR_INSTR_SLOT_END
 174       },
 175    },
 176    [ppir_op_xor] = {
 177       .name = "xor",
 178       .slots = (int []) {
 179          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 180          PPIR_INSTR_SLOT_END
 181       },
 182    },
 183    [ppir_op_not] = {
 184       .name = "not",
 185       .slots = (int []) {
 186          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 187          PPIR_INSTR_SLOT_END
 188       },
 189    },
 190    [ppir_op_lt] = {
 191       .name = "lt",
 192    },
 193    [ppir_op_le] = {
 194       .name = "le",
 195    },
 196    [ppir_op_gt] = {
 197       .name = "gt",
 198       .slots = (int []) {
 199          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 200          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 201          PPIR_INSTR_SLOT_END
 202       },
 203    },
 204    [ppir_op_ge] = {
 205       .name = "ge",
 206       .slots = (int []) {
 207          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 208          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 209          PPIR_INSTR_SLOT_END
 210       },
 211    },
 212    [ppir_op_eq] = {
 213       .name = "eq",
 214       .slots = (int []) {
 215          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 216          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 217          PPIR_INSTR_SLOT_END
 218       },
 219    },
 220    [ppir_op_ne] = {
 221       .name = "ne",
 222       .slots = (int []) {
 223          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 224          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 225          PPIR_INSTR_SLOT_END
 226       },
 227    },
 228    [ppir_op_sel_cond] = {
 229       /* effectively mov, but must be scheduled only to
 230        * PPIR_INSTR_SLOT_ALU_SCL_MUL */
 231       .name = "sel_cond",
 232       .slots = (int []) {
 233          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
 234       },
 235    },
 236    [ppir_op_select] = {
 237       .name = "select",
 238       .slots = (int []) {
 239          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 240          PPIR_INSTR_SLOT_END
 241       },
 242    },
 243    [ppir_op_rcp] = {
 244       .name = "rcp",
 245       .slots = (int []) {
 246          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 247       },
 248    },
 249    [ppir_op_load_varying] = {
 250       .name = "ld_var",
 251       .type = ppir_node_type_load,
 252       .slots = (int []) {
 253          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 254       },
 255    },
 256    [ppir_op_load_coords] = {
 257       .name = "ld_coords",
 258       .type = ppir_node_type_load,
 259       .slots = (int []) {
 260          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 261       },
 262    },
 263    [ppir_op_load_coords_reg] = {
 264       .name = "ld_coords_reg",
 265       .type = ppir_node_type_load,
 266       .slots = (int []) {
 267          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 268       },
 269    },
 270    [ppir_op_load_fragcoord] = {
 271       .name = "ld_fragcoord",
 272       .type = ppir_node_type_load,
 273       .slots = (int []) {
 274          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 275       },
 276    },
 277    [ppir_op_load_pointcoord] = {
 278       .name = "ld_pointcoord",
 279       .type = ppir_node_type_load,
 280       .slots = (int []) {
 281          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 282       },
 283    },
 284    [ppir_op_load_frontface] = {
 285       .name = "ld_frontface",
 286       .type = ppir_node_type_load,
 287       .slots = (int []) {
 288          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 289       },
 290    },
 291    [ppir_op_load_uniform] = {
 292       .name = "ld_uni",
 293       .type = ppir_node_type_load,
 294       .slots = (int []) {
 295          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 296       },
 297    },
 298    [ppir_op_load_texture] = {
 299       .name = "ld_tex",
 300       .type = ppir_node_type_load_texture,
 301       .slots = (int []) {
 302          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 303       },
 304    },
 305    [ppir_op_load_temp] = {
 306       .name = "ld_temp",
 307       .type = ppir_node_type_load,
 308       .slots = (int []) {
 309          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 310       },
 311    },
 312    [ppir_op_const] = {
 313       .name = "const",
 314       .type = ppir_node_type_const,
 315    },
 316    [ppir_op_store_color] = {
 317       .name = "st_col",
 318       .type = ppir_node_type_alu,
 319       .slots = (int []) {
 320          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 321          PPIR_INSTR_SLOT_END
 322       },
 323    },
 324    [ppir_op_store_temp] = {
 325       .name = "st_temp",
 326       .type = ppir_node_type_store,
 327       .slots = (int []) {
 328          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 329       },
 330    },
 331    [ppir_op_discard] = {
 332       .name = "discard",
 333       .type = ppir_node_type_discard,
 334       .slots = (int []) {
 335          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 336       },
 337    },
 338    [ppir_op_branch] = {
 339       .name = "branch",
 340       .type = ppir_node_type_branch,
 341       .slots = (int []) {
 342          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 343       },
 344    },
 345    [ppir_op_undef] = {
 346       .name = "undef",
 347       .type = ppir_node_type_alu,
 348       .slots = (int []) {
 349       },
 350    },
 351 };
 352
 353 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 354 {
 355    ppir_compiler *comp = block->comp;
 356    static const int node_size[] = {
 357       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 358       [ppir_node_type_const] = sizeof(ppir_const_node),
 359       [ppir_node_type_load] = sizeof(ppir_load_node),
 360       [ppir_node_type_store] = sizeof(ppir_store_node),
 361       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 362       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 363       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 364    };
 365
 366    ppir_node_type type = ppir_op_infos[op].type;
 367    int size = node_size[type];
 368    ppir_node *node = rzalloc_size(block, size);
 369    if (!node)
 370       return NULL;
 371
 372    list_inithead(&node->succ_list);
 373    list_inithead(&node->pred_list);
 374
 375    if (index >= 0) {
 376       if (mask) {
 377          /* reg has 4 slots for each componemt write node */
 378          while (mask)
 379             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 380          snprintf(node->name, sizeof(node->name), "reg%d", index);
 381       } else {
 382          comp->var_nodes[index] = node;
 383          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 384       }
 385    }
 386    else
 387       snprintf(node->name, sizeof(node->name), "new");
 388
 389    node->op = op;
 390    node->type = type;
 391    node->index = comp->cur_index++;
 392    node->block = block;
 393
 394    return node;
 395 }
 396
 397 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred,
 398                        ppir_dep_type type)
 399 {
 400    /* don't add dep for two nodes from different block */
 401    if (succ->block != pred->block)
 402       return;
 403
 404    /* don't add duplicated dep */
 405    ppir_node_foreach_pred(succ, dep) {
 406       if (dep->pred == pred)
 407          return;
 408    }
 409
 410    ppir_dep *dep = ralloc(succ, ppir_dep);
 411    dep->pred = pred;
 412    dep->succ = succ;
 413    dep->type = type;
 414    list_addtail(&dep->pred_link, &succ->pred_list);
 415    list_addtail(&dep->succ_link, &pred->succ_list);
 416 }
 417
 418 void ppir_node_remove_dep(ppir_dep *dep)
 419 {
 420    list_del(&dep->succ_link);
 421    list_del(&dep->pred_link);
 422    ralloc_free(dep);
 423 }
 424
 425 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 426 {
 427    ppir_dest *od = ppir_node_get_dest(old_child);
 428    if (ppir_node_target_equal(src, od)) {
 429       ppir_node_target_assign(src, new_child);
 430    }
 431 }
 432
 433 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 434 {
 435    switch (parent->type) {
 436    case ppir_node_type_alu:
 437    {
 438       ppir_alu_node *alu = ppir_node_to_alu(parent);
 439       for (int i = 0; i < alu->num_src; i++)
 440          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 441       break;
 442    }
 443    case ppir_node_type_branch:
 444    {
 445       ppir_branch_node *branch = ppir_node_to_branch(parent);
 446       for (int i = 0; i < 2; i++)
 447          _ppir_node_replace_child(branch->src + i, old_child, new_child);
 448       break;
 449    }
 450    case ppir_node_type_load:
 451    {
 452       ppir_load_node *load = ppir_node_to_load(parent);
 453       _ppir_node_replace_child(&load->src, old_child, new_child);
 454       break;
 455    }
 456    case ppir_node_type_load_texture:
 457    {
 458       ppir_load_texture_node *load_texture = ppir_node_to_load_texture(parent);
 459       _ppir_node_replace_child(&load_texture->src_coords, old_child, new_child);
 460       break;
 461    }
 462    case ppir_node_type_store:
 463    {
 464       ppir_store_node *store = ppir_node_to_store(parent);
 465       _ppir_node_replace_child(&store->src, old_child, new_child);
 466       break;
 467    }
 468    default:
 469       ppir_debug("unknown node type in %s\n", __func__);
 470       break;
 471    }
 472 }
 473
 474 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 475 {
 476    list_del(&dep->succ_link);
 477    dep->pred = new_pred;
 478    list_addtail(&dep->succ_link, &new_pred->succ_list);
 479 }
 480
 481 ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred)
 482 {
 483    if (!pred)
 484       return NULL;
 485
 486    if (node->block != pred->block)
 487       return NULL;
 488
 489    ppir_node_foreach_pred(node, dep) {
 490       if (dep->pred == pred)
 491          return dep;
 492    }
 493    return NULL;
 494 }
 495
 496 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 497 {
 498    ppir_node_foreach_succ_safe(src, dep) {
 499       ppir_node_replace_pred(dep, dst);
 500       ppir_node_replace_child(dep->succ, src, dst);
 501    }
 502 }
 503
 504 void ppir_node_delete(ppir_node *node)
 505 {
 506    ppir_node_foreach_succ_safe(node, dep)
 507       ppir_node_remove_dep(dep);
 508
 509    ppir_node_foreach_pred_safe(node, dep)
 510       ppir_node_remove_dep(dep);
 511
 512    list_del(&node->list);
 513    ralloc_free(node);
 514 }
 515
 516 static void ppir_node_print_dest(ppir_dest *dest)
 517 {
 518    switch (dest->type) {
 519    case ppir_target_ssa:
 520       printf("ssa%d", dest->ssa.index);
 521       break;
 522    case ppir_target_pipeline:
 523       printf("pipeline %d", dest->pipeline);
 524       break;
 525    case ppir_target_register:
 526       printf("reg %d", dest->reg->index);
 527       break;
 528    }
 529 }
 530
 531 static void ppir_node_print_src(ppir_src *src)
 532 {
 533    switch (src->type) {
 534    case ppir_target_ssa: {
 535       if (src->node)
 536          printf("ssa node %d", src->node->index);
 537       else
 538          printf("ssa idx %d", src->ssa ? src->ssa->index : -1);
 539       break;
 540    }
 541    case ppir_target_pipeline:
 542       if (src->node)
 543          printf("pipeline %d node %d", src->pipeline, src->node->index);
 544       else
 545          printf("pipeline %d", src->pipeline);
 546       break;
 547    case ppir_target_register:
 548       printf("reg %d", src->reg->index);
 549       break;
 550    }
 551 }
 552
 553 static void ppir_node_print_node(ppir_node *node, int space)
 554 {
 555    for (int i = 0; i < space; i++)
 556       printf(" ");
 557
 558    printf("%s%d: %s %s: ", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 559           node->index, ppir_op_infos[node->op].name, node->name);
 560
 561    ppir_dest *dest = ppir_node_get_dest(node);
 562    if (dest) {
 563       printf("dest: ");
 564       ppir_node_print_dest(dest);
 565    }
 566
 567    if (ppir_node_get_src_num(node) > 0) {
 568       printf(" src: ");
 569    }
 570    for (int i = 0; i < ppir_node_get_src_num(node); i++) {
 571       ppir_node_print_src(ppir_node_get_src(node, i));
 572       if (i != (ppir_node_get_src_num(node) - 1))
 573          printf(", ");
 574    }
 575    printf("\n");
 576
 577    if (!node->printed) {
 578       ppir_node_foreach_pred(node, dep) {
 579          ppir_node *pred = dep->pred;
 580          ppir_node_print_node(pred, space + 2);
 581       }
 582
 583       node->printed = true;
 584    }
 585 }
 586
 587 void ppir_node_print_prog(ppir_compiler *comp)
 588 {
 589    if (!(lima_debug & LIMA_DEBUG_PP))
 590       return;
 591
 592    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 593       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 594          node->printed = false;
 595       }
 596    }
 597
 598    printf("========prog========\n");
 599    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 600       printf("-------block %3d-------\n", block->index);
 601       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 602          if (ppir_node_is_root(node))
 603             ppir_node_print_node(node, 0);
 604       }
 605    }
 606    printf("====================\n");
 607 }
 608
 609 static ppir_node *ppir_node_clone_const(ppir_block *block, ppir_node *node)
 610 {
 611    ppir_const_node *cnode = ppir_node_to_const(node);
 612    ppir_const_node *new_cnode = ppir_node_create(block, ppir_op_const, -1, 0);
 613
 614    if (!new_cnode)
 615       return NULL;
 616
 617    list_addtail(&new_cnode->node.list, &block->node_list);
 618
 619    new_cnode->constant.num = cnode->constant.num;
 620    for (int i = 0; i < cnode->constant.num; i++) {
 621       new_cnode->constant.value[i] = cnode->constant.value[i];
 622    }
 623    new_cnode->dest.type = ppir_target_ssa;
 624    new_cnode->dest.ssa.num_components = cnode->dest.ssa.num_components;
 625    new_cnode->dest.ssa.live_in = INT_MAX;
 626    new_cnode->dest.ssa.live_out = 0;
 627    new_cnode->dest.write_mask = cnode->dest.write_mask;
 628
 629    return &new_cnode->node;
 630 }
 631
 632 static ppir_node *
 633 ppir_node_clone_load(ppir_block *block, ppir_node *node)
 634 {
 635    ppir_load_node *load_node = ppir_node_to_load(node);
 636    ppir_load_node *new_lnode = ppir_node_create(block, node->op, -1, 0);
 637
 638    if (!new_lnode)
 639       return NULL;
 640
 641    list_addtail(&new_lnode->node.list, &block->node_list);
 642
 643    new_lnode->num_components = load_node->num_components;
 644    new_lnode->index = load_node->index;
 645
 646    ppir_dest *dest = ppir_node_get_dest(node);
 647    new_lnode->dest = *dest;
 648
 649    ppir_src *src = ppir_node_get_src(node, 0);
 650    if (src) {
 651       new_lnode->num_src = 1;
 652       switch (src->type) {
 653       case ppir_target_ssa:
 654          ppir_node_target_assign(&new_lnode->src, src->node);
 655          ppir_node_add_dep(&new_lnode->node, src->node, ppir_dep_src);
 656          break;
 657       case ppir_target_register:
 658          new_lnode->src.type = src->type;
 659          new_lnode->src.reg = src->reg;
 660          new_lnode->src.node = NULL;
 661          break;
 662       default:
 663          /* Load nodes can't consume pipeline registers */
 664          assert(0);
 665       }
 666    }
 667
 668    return &new_lnode->node;
 669 }
 670
 671 ppir_node *ppir_node_clone(ppir_block *block, ppir_node *node)
 672 {
 673    switch (node->op) {
 674    case ppir_op_const:
 675       return ppir_node_clone_const(block, node);
 676    case ppir_op_load_uniform:
 677    case ppir_op_load_varying:
 678    case ppir_op_load_temp:
 679    case ppir_op_load_coords:
 680    case ppir_op_load_coords_reg:
 681       return ppir_node_clone_load(block, node);
 682    default:
 683       return NULL;
 684    }
 685 }
 686
 687 ppir_node *ppir_node_insert_mov(ppir_node *node)
 688 {
 689    ppir_node *move = ppir_node_create(node->block, ppir_op_mov, -1, 0);
 690    if (unlikely(!move))
 691       return NULL;
 692
 693    ppir_dest *dest = ppir_node_get_dest(node);
 694    ppir_alu_node *alu = ppir_node_to_alu(move);
 695    alu->dest = *dest;
 696    alu->num_src = 1;
 697    ppir_node_target_assign(alu->src, node);
 698
 699    for (int s = 0; s < 4; s++)
 700       alu->src->swizzle[s] = s;
 701
 702    ppir_node_replace_all_succ(move, node);
 703    ppir_node_add_dep(move, node, ppir_dep_src);
 704    list_addtail(&move->list, &node->list);
 705
 706    return move;
 707 }
 708
 709 bool ppir_node_has_single_src_succ(ppir_node *node)
 710 {
 711    if (list_is_singular(&node->succ_list) &&
 712        list_first_entry(&node->succ_list,
 713                         ppir_dep, succ_link)->type == ppir_dep_src)
 714       return true;
 715
 716    int cnt = 0;
 717    ppir_node_foreach_succ(node, dep) {
 718       if (dep->type != ppir_dep_src)
 719          continue;
 720       cnt++;
 721    }
 722
 723    return cnt == 1;
 724 }