lima/ppir: refactor texture code to simplify scheduler
[mesa.git] / src / gallium / drivers / lima / ir / pp / node_to_instr.c
1 /*
2 * Copyright (c) 2017 Lima Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "ppir.h"
26
27
28 static bool create_new_instr(ppir_block *block, ppir_node *node)
29 {
30 ppir_instr *instr = ppir_instr_create(block);
31 if (unlikely(!instr))
32 return false;
33
34 if (!ppir_instr_insert_node(instr, node))
35 return false;
36
37 return true;
38 }
39
40 static bool insert_to_load_tex(ppir_block *block, ppir_node *load_coords, ppir_node *ldtex)
41 {
42 ppir_dest *dest = ppir_node_get_dest(ldtex);
43 ppir_node *move = NULL;
44
45 /* Insert load_coords to ldtex instruction */
46 if (!ppir_instr_insert_node(ldtex->instr, load_coords))
47 return false;
48
49 /* Create move node */
50 move = ppir_node_create(block, ppir_op_mov, -1 , 0);
51 if (unlikely(!move))
52 return false;
53
54 ppir_debug("insert_load_tex: create move %d for %d\n",
55 move->index, ldtex->index);
56
57 ppir_alu_node *alu = ppir_node_to_alu(move);
58 alu->dest = *dest;
59
60 ppir_node_replace_all_succ(move, ldtex);
61
62 dest->type = ppir_target_pipeline;
63 dest->pipeline = ppir_pipeline_reg_sampler;
64
65 alu->num_src = 1;
66 ppir_node_target_assign(&alu->src[0], dest);
67 for (int i = 0; i < 4; i++)
68 alu->src->swizzle[i] = i;
69
70 ppir_node_add_dep(move, ldtex);
71 list_addtail(&move->list, &ldtex->list);
72
73 if (!ppir_instr_insert_node(ldtex->instr, move))
74 return false;
75
76 return true;
77 }
78
79 static bool insert_to_each_succ_instr(ppir_block *block, ppir_node *node)
80 {
81 ppir_dest *dest = ppir_node_get_dest(node);
82 assert(dest->type == ppir_target_ssa);
83
84 ppir_node *move = NULL;
85
86 ppir_node_foreach_succ_safe(node, dep) {
87 ppir_node *succ = dep->succ;
88 assert(succ->type == ppir_node_type_alu ||
89 succ->type == ppir_node_type_branch);
90
91 if (!ppir_instr_insert_node(succ->instr, node)) {
92 /* create a move node to insert for failed node */
93 if (!move) {
94 move = ppir_node_create(block, ppir_op_mov, -1, 0);
95 if (unlikely(!move))
96 return false;
97
98 ppir_debug("node_to_instr create move %d for %d\n",
99 move->index, node->index);
100
101 ppir_alu_node *alu = ppir_node_to_alu(move);
102 alu->dest = *dest;
103 alu->num_src = 1;
104 ppir_node_target_assign(alu->src, dest);
105 for (int i = 0; i < 4; i++)
106 alu->src->swizzle[i] = i;
107 }
108
109 ppir_node_replace_pred(dep, move);
110 ppir_node_replace_child(succ, node, move);
111 }
112 }
113
114 if (move) {
115 if (!create_new_instr(block, move))
116 return false;
117
118 ASSERTED bool insert_result =
119 ppir_instr_insert_node(move->instr, node);
120 assert(insert_result);
121
122 ppir_node_add_dep(move, node);
123 list_addtail(&move->list, &node->list);
124 }
125
126 /* dupliacte node for each successor */
127
128 bool first = true;
129 struct list_head dup_list;
130 list_inithead(&dup_list);
131
132 ppir_node_foreach_succ_safe(node, dep) {
133 ppir_node *succ = dep->succ;
134
135 if (first) {
136 first = false;
137 node->instr = succ->instr;
138 continue;
139 }
140
141 if (succ->instr == node->instr)
142 continue;
143
144 list_for_each_entry(ppir_node, dup, &dup_list, list) {
145 if (succ->instr == dup->instr) {
146 ppir_node_replace_pred(dep, dup);
147 continue;
148 }
149 }
150
151 ppir_node *dup = ppir_node_create(block, node->op, -1, 0);
152 if (unlikely(!dup))
153 return false;
154 list_addtail(&dup->list, &dup_list);
155
156 ppir_debug("node_to_instr duplicate %s %d from %d\n",
157 ppir_op_infos[dup->op].name, dup->index, node->index);
158
159 ppir_instr *instr = succ->instr;
160 dup->instr = instr;
161 dup->instr_pos = node->instr_pos;
162 ppir_node_replace_pred(dep, dup);
163
164 if ((node->op == ppir_op_load_uniform) || (node->op == ppir_op_load_temp)) {
165 ppir_load_node *load = ppir_node_to_load(node);
166 ppir_load_node *dup_load = ppir_node_to_load(dup);
167 dup_load->dest = load->dest;
168 dup_load->index = load->index;
169 dup_load->num_components = load->num_components;
170 instr->slots[node->instr_pos] = dup;
171 }
172 }
173
174 list_splicetail(&dup_list, &node->list);
175
176 return true;
177 }
178
179 static bool ppir_do_node_to_instr(ppir_block *block, ppir_node *node)
180 {
181 switch (node->type) {
182 case ppir_node_type_alu:
183 {
184 /* merge pred mul and succ add in the same instr can save a reg
185 * by using pipeline reg ^vmul/^fmul */
186 ppir_alu_node *alu = ppir_node_to_alu(node);
187 if (alu->dest.type == ppir_target_ssa &&
188 ppir_node_has_single_succ(node)) {
189 ppir_node *succ = ppir_node_first_succ(node);
190 if (succ->instr_pos == PPIR_INSTR_SLOT_ALU_VEC_ADD) {
191 node->instr_pos = PPIR_INSTR_SLOT_ALU_VEC_MUL;
192 /* select instr's condition must be inserted to fmul slot */
193 if (succ->op == ppir_op_select &&
194 ppir_node_first_pred(succ) == node) {
195 assert(alu->dest.ssa.num_components == 1);
196 node->instr_pos = PPIR_INSTR_SLOT_ALU_SCL_MUL;
197 }
198 ppir_instr_insert_mul_node(succ, node);
199 }
200 else if (succ->instr_pos == PPIR_INSTR_SLOT_ALU_SCL_ADD &&
201 alu->dest.ssa.num_components == 1) {
202 node->instr_pos = PPIR_INSTR_SLOT_ALU_SCL_MUL;
203 ppir_instr_insert_mul_node(succ, node);
204 }
205 }
206
207 /* can't inserted to any existing instr, create one */
208 if (!node->instr && !create_new_instr(block, node))
209 return false;
210
211 break;
212 }
213 case ppir_node_type_load:
214 if ((node->op == ppir_op_load_uniform) || (node->op == ppir_op_load_temp)) {
215 /* merge pred load_uniform into succ instr can save a reg
216 * by using pipeline reg */
217 if (!insert_to_each_succ_instr(block, node))
218 return false;
219
220 ppir_load_node *load = ppir_node_to_load(node);
221 load->dest.type = ppir_target_pipeline;
222 load->dest.pipeline = ppir_pipeline_reg_uniform;
223 }
224 else if (node->op == ppir_op_load_temp) {
225 /* merge pred load_temp into succ instr can save a reg
226 * by using pipeline reg */
227 if (!insert_to_each_succ_instr(block, node))
228 return false;
229
230 ppir_load_node *load = ppir_node_to_load(node);
231 load->dest.type = ppir_target_pipeline;
232 load->dest.pipeline = ppir_pipeline_reg_uniform;
233 }
234 else if (node->op == ppir_op_load_varying ||
235 node->op == ppir_op_load_fragcoord ||
236 node->op == ppir_op_load_pointcoord) {
237 /* delay the load varying dup to scheduler */
238 if (!create_new_instr(block, node))
239 return false;
240 }
241 else if (node->op == ppir_op_load_coords) {
242 ppir_node *ldtex = ppir_node_first_succ(node);
243 if (!insert_to_load_tex(block, node, ldtex))
244 return false;
245 }
246 else {
247 /* not supported yet */
248 assert(0);
249 return false;
250 }
251 break;
252 case ppir_node_type_load_texture:
253 if (!create_new_instr(block, node))
254 return false;
255 break;
256 case ppir_node_type_const:
257 if (!insert_to_each_succ_instr(block, node))
258 return false;
259 break;
260 case ppir_node_type_store:
261 {
262 if (node->op == ppir_op_store_temp) {
263 if (!create_new_instr(block, node))
264 return false;
265 break;
266 }
267
268 /* Only the store color node should appear here.
269 * Currently we always insert a move node as the end instr.
270 * But it should only be done when:
271 * 1. store a const node
272 * 2. store a load node
273 * 3. store a reg assigned in another block like loop/if
274 */
275
276 assert(node->op == ppir_op_store_color);
277
278 ppir_node *move = ppir_node_create(block, ppir_op_mov, -1, 0);
279 if (unlikely(!move))
280 return false;
281
282 ppir_debug("node_to_instr create move %d from store %d\n",
283 move->index, node->index);
284
285 ppir_node_foreach_pred_safe(node, dep) {
286 ppir_node *pred = dep->pred;
287 /* we can't do this in this function except here as this
288 * store is the root of this recursion */
289 ppir_node_remove_dep(dep);
290 ppir_node_add_dep(move, pred);
291 }
292
293 ppir_node_add_dep(node, move);
294 list_addtail(&move->list, &node->list);
295
296 ppir_alu_node *alu = ppir_node_to_alu(move);
297 ppir_store_node *store = ppir_node_to_store(node);
298 alu->src[0] = store->src;
299 alu->num_src = 1;
300
301 alu->dest.type = ppir_target_ssa;
302 alu->dest.ssa.num_components = 4;
303 alu->dest.ssa.live_in = INT_MAX;
304 alu->dest.ssa.live_out = 0;
305 alu->dest.write_mask = 0xf;
306
307 store->src.type = ppir_target_ssa;
308 store->src.ssa = &alu->dest.ssa;
309
310 if (!create_new_instr(block, move))
311 return false;
312
313 move->instr->is_end = true;
314 node->instr = move->instr;
315
316 /* use move for the following recursion */
317 node = move;
318 break;
319 }
320 case ppir_node_type_discard:
321 if (!create_new_instr(block, node))
322 return false;
323 node->instr->is_end = true;
324 break;
325 case ppir_node_type_branch:
326 if (!create_new_instr(block, node))
327 return false;
328 break;
329 default:
330 return false;
331 }
332
333 /* we have to make sure the dep not be destroyed (due to
334 * succ change) in ppir_do_node_to_instr, otherwise we can't
335 * do recursion like this */
336 ppir_node_foreach_pred(node, dep) {
337 ppir_node *pred = dep->pred;
338 bool ready = true;
339
340 /* pred may already be processed by the previous pred
341 * (this pred may be both node and previous pred's child) */
342 if (pred->instr)
343 continue;
344
345 /* insert pred only when all its successors have been inserted */
346 ppir_node_foreach_succ(pred, dep) {
347 ppir_node *succ = dep->succ;
348 if (!succ->instr) {
349 ready = false;
350 break;
351 }
352 }
353
354 if (ready) {
355 if (!ppir_do_node_to_instr(block, pred))
356 return false;
357 }
358 }
359
360 return true;
361 }
362
363 static bool ppir_create_instr_from_node(ppir_compiler *comp)
364 {
365 list_for_each_entry(ppir_block, block, &comp->block_list, list) {
366 list_for_each_entry(ppir_node, node, &block->node_list, list) {
367 if (ppir_node_is_root(node)) {
368 if (!ppir_do_node_to_instr(block, node))
369 return false;
370 }
371 }
372 }
373
374 return true;
375 }
376
377 static void ppir_build_instr_dependency(ppir_compiler *comp)
378 {
379 list_for_each_entry(ppir_block, block, &comp->block_list, list) {
380 list_for_each_entry(ppir_instr, instr, &block->instr_list, list) {
381 for (int i = 0; i < PPIR_INSTR_SLOT_NUM; i++) {
382 ppir_node *node = instr->slots[i];
383 if (node) {
384 ppir_node_foreach_pred(node, dep) {
385 ppir_node *pred = dep->pred;
386 if (pred->instr && pred->instr != instr)
387 ppir_instr_add_dep(instr, pred->instr);
388 }
389 }
390 }
391 }
392 }
393 }
394
395 bool ppir_node_to_instr(ppir_compiler *comp)
396 {
397 if (!ppir_create_instr_from_node(comp))
398 return false;
399 ppir_instr_print_list(comp);
400
401 ppir_build_instr_dependency(comp);
402 ppir_instr_print_dep(comp);
403
404 return true;
405 }