3395a13ee564c438162373c1e2083dbd9d4cab36
[mesa.git] / src / gallium / drivers / lima / ir / pp / ppir.h
1 /*
2 * Copyright (c) 2017 Lima Project
3 * Copyright (c) 2013 Connor Abbott
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 *
23 */
24
25 #ifndef LIMA_IR_PP_PPIR_H
26 #define LIMA_IR_PP_PPIR_H
27
28 #include "util/u_math.h"
29 #include "util/list.h"
30
31 #include "ir/lima_ir.h"
32
33 typedef enum {
34 ppir_op_mov,
35 ppir_op_abs,
36 ppir_op_neg,
37 ppir_op_sat,
38 ppir_op_add,
39
40 ppir_op_ddx,
41 ppir_op_ddy,
42
43 ppir_op_mul,
44 ppir_op_rcp,
45
46 ppir_op_sin_lut,
47 ppir_op_cos_lut,
48
49 ppir_op_sum3,
50 ppir_op_sum4,
51
52 ppir_op_normalize2,
53 ppir_op_normalize3,
54 ppir_op_normalize4,
55
56 ppir_op_select,
57
58 ppir_op_sin,
59 ppir_op_cos,
60 ppir_op_tan,
61 ppir_op_asin,
62 ppir_op_acos,
63
64 ppir_op_atan,
65 ppir_op_atan2,
66 ppir_op_atan_pt1,
67 ppir_op_atan2_pt1,
68 ppir_op_atan_pt2,
69
70 ppir_op_exp,
71 ppir_op_log,
72 ppir_op_exp2,
73 ppir_op_log2,
74 ppir_op_sqrt,
75 ppir_op_rsqrt,
76
77 ppir_op_sign,
78 ppir_op_floor,
79 ppir_op_ceil,
80 ppir_op_fract,
81 ppir_op_mod,
82 ppir_op_min,
83 ppir_op_max,
84 ppir_op_trunc,
85
86 ppir_op_dot2,
87 ppir_op_dot3,
88 ppir_op_dot4,
89
90 ppir_op_and,
91 ppir_op_or,
92 ppir_op_xor,
93
94 ppir_op_lt,
95 ppir_op_gt,
96 ppir_op_le,
97 ppir_op_ge,
98 ppir_op_eq,
99 ppir_op_ne,
100 ppir_op_not,
101
102 ppir_op_load_uniform,
103 ppir_op_load_varying,
104 ppir_op_load_coords,
105 ppir_op_load_fragcoord,
106 ppir_op_load_pointcoord,
107 ppir_op_load_texture,
108 ppir_op_load_temp,
109
110 ppir_op_store_temp,
111 ppir_op_store_color,
112
113 ppir_op_const,
114
115 ppir_op_discard,
116 ppir_op_branch,
117
118 ppir_op_num,
119 } ppir_op;
120
121 typedef enum {
122 ppir_node_type_alu,
123 ppir_node_type_const,
124 ppir_node_type_load,
125 ppir_node_type_store,
126 ppir_node_type_load_texture,
127 ppir_node_type_discard,
128 ppir_node_type_branch,
129 } ppir_node_type;
130
131 typedef struct {
132 char *name;
133 ppir_node_type type;
134 int *slots;
135 } ppir_op_info;
136
137 extern const ppir_op_info ppir_op_infos[];
138
139 typedef struct {
140 void *pred, *succ;
141 struct list_head pred_link;
142 struct list_head succ_link;
143 } ppir_dep;
144
145 typedef struct ppir_node {
146 struct list_head list;
147 ppir_op op;
148 ppir_node_type type;
149 int index;
150 char name[16];
151 bool printed;
152 struct ppir_instr *instr;
153 int instr_pos;
154 struct ppir_block *block;
155
156 /* for scheduler */
157 struct list_head succ_list;
158 struct list_head pred_list;
159 } ppir_node;
160
161 typedef enum {
162 ppir_pipeline_reg_const0,
163 ppir_pipeline_reg_const1,
164 ppir_pipeline_reg_sampler,
165 ppir_pipeline_reg_uniform,
166 ppir_pipeline_reg_vmul,
167 ppir_pipeline_reg_fmul,
168 ppir_pipeline_reg_discard, /* varying load */
169 } ppir_pipeline;
170
171 typedef struct ppir_reg {
172 struct list_head list;
173 int index;
174 int num_components;
175 /* whether this reg has to start from the x component
176 * of a full physical reg, this is true for reg used
177 * in load/store instr which has no swizzle field
178 */
179 bool is_head;
180 /* instr live range */
181 int live_in, live_out;
182 bool spilled;
183 } ppir_reg;
184
185 typedef enum {
186 ppir_target_ssa,
187 ppir_target_pipeline,
188 ppir_target_register,
189 } ppir_target;
190
191 typedef struct ppir_src {
192 ppir_target type;
193
194 union {
195 ppir_reg *ssa;
196 ppir_reg *reg;
197 ppir_pipeline pipeline;
198 };
199
200 uint8_t swizzle[4];
201 bool absolute, negate;
202 } ppir_src;
203
204 typedef enum {
205 ppir_outmod_none,
206 ppir_outmod_clamp_fraction,
207 ppir_outmod_clamp_positive,
208 ppir_outmod_round,
209 } ppir_outmod;
210
211 typedef struct ppir_dest {
212 ppir_target type;
213
214 union {
215 ppir_reg ssa;
216 ppir_reg *reg;
217 ppir_pipeline pipeline;
218 };
219
220 ppir_outmod modifier;
221 unsigned write_mask : 4;
222 } ppir_dest;
223
224 typedef struct {
225 ppir_node node;
226 ppir_dest dest;
227 ppir_src src[3];
228 int num_src;
229 int shift : 3; /* Only used for ppir_op_mul */
230 } ppir_alu_node;
231
232 typedef struct ppir_const {
233 union fi value[4];
234 int num;
235 } ppir_const;
236
237 typedef struct {
238 ppir_node node;
239 ppir_const constant;
240 ppir_dest dest;
241 } ppir_const_node;
242
243 typedef struct {
244 ppir_node node;
245 int index;
246 int num_components;
247 ppir_dest dest;
248 ppir_src src;
249 } ppir_load_node;
250
251 typedef struct {
252 ppir_node node;
253 int index;
254 int num_components;
255 ppir_src src;
256 } ppir_store_node;
257
258 typedef struct {
259 ppir_node node;
260 ppir_dest dest;
261 ppir_src src_coords;
262 int sampler;
263 int sampler_dim;
264 } ppir_load_texture_node;
265
266 typedef struct {
267 ppir_node node;
268 } ppir_discard_node;
269
270 enum ppir_instr_slot {
271 PPIR_INSTR_SLOT_VARYING,
272 PPIR_INSTR_SLOT_TEXLD,
273 PPIR_INSTR_SLOT_UNIFORM,
274 PPIR_INSTR_SLOT_ALU_VEC_MUL,
275 PPIR_INSTR_SLOT_ALU_SCL_MUL,
276 PPIR_INSTR_SLOT_ALU_VEC_ADD,
277 PPIR_INSTR_SLOT_ALU_SCL_ADD,
278 PPIR_INSTR_SLOT_ALU_COMBINE,
279 PPIR_INSTR_SLOT_STORE_TEMP,
280 PPIR_INSTR_SLOT_BRANCH,
281 PPIR_INSTR_SLOT_NUM,
282 PPIR_INSTR_SLOT_END,
283 PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
284 PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
285 };
286
287 typedef struct ppir_instr {
288 struct list_head list;
289 int index;
290 bool printed;
291 int seq; /* command sequence after schedule */
292
293 ppir_node *slots[PPIR_INSTR_SLOT_NUM];
294 ppir_const constant[2];
295 bool is_end;
296
297 /* for scheduler */
298 struct list_head succ_list;
299 struct list_head pred_list;
300 float reg_pressure;
301 int est; /* earliest start time */
302 int parent_index;
303 bool scheduled;
304 int offset;
305 int encode_size;
306 } ppir_instr;
307
308 typedef struct ppir_block {
309 struct list_head list;
310 struct list_head node_list;
311 struct list_head instr_list;
312 struct ppir_compiler *comp;
313
314 /* for scheduler */
315 int sched_instr_index;
316 int sched_instr_base;
317 } ppir_block;
318
319 typedef struct {
320 ppir_node node;
321 ppir_src src[2];
322 bool cond_gt;
323 bool cond_eq;
324 bool cond_lt;
325 ppir_block *target;
326 } ppir_branch_node;
327
328 struct ra_regs;
329 struct lima_fs_shader_state;
330
331 typedef struct ppir_compiler {
332 struct list_head block_list;
333 int cur_index;
334 int cur_instr_index;
335
336 struct list_head reg_list;
337
338 /* array for searching ssa/reg node */
339 ppir_node **var_nodes;
340 unsigned reg_base;
341
342 struct ra_regs *ra;
343 struct lima_fs_shader_state *prog;
344
345 /* for scheduler */
346 int sched_instr_base;
347
348 /* for regalloc spilling debug */
349 int force_spilling;
350
351 ppir_block *discard_block;
352 } ppir_compiler;
353
354 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
355 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred);
356 void ppir_node_remove_dep(ppir_dep *dep);
357 void ppir_node_delete(ppir_node *node);
358 void ppir_node_print_prog(ppir_compiler *comp);
359 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
360 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
361 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
362
363 static inline bool ppir_node_is_root(ppir_node *node)
364 {
365 return list_empty(&node->succ_list);
366 }
367
368 static inline bool ppir_node_is_leaf(ppir_node *node)
369 {
370 return list_empty(&node->pred_list);
371 }
372
373 static inline bool ppir_node_has_single_succ(ppir_node *node)
374 {
375 return list_is_singular(&node->succ_list);
376 }
377
378 static inline ppir_node *ppir_node_first_succ(ppir_node *node)
379 {
380 return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
381 }
382
383 static inline bool ppir_node_has_single_pred(ppir_node *node)
384 {
385 return list_is_singular(&node->pred_list);
386 }
387
388 static inline ppir_node *ppir_node_first_pred(ppir_node *node)
389 {
390 return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
391 }
392
393 #define ppir_node_foreach_succ(node, dep) \
394 list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
395 #define ppir_node_foreach_succ_safe(node, dep) \
396 list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
397 #define ppir_node_foreach_pred(node, dep) \
398 list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
399 #define ppir_node_foreach_pred_safe(node, dep) \
400 list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
401
402 #define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
403 #define ppir_node_to_const(node) ((ppir_const_node *)(node))
404 #define ppir_node_to_load(node) ((ppir_load_node *)(node))
405 #define ppir_node_to_store(node) ((ppir_store_node *)(node))
406 #define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
407 #define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
408 #define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
409
410 static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
411 {
412 switch (node->type) {
413 case ppir_node_type_alu:
414 return &ppir_node_to_alu(node)->dest;
415 case ppir_node_type_load:
416 return &ppir_node_to_load(node)->dest;
417 case ppir_node_type_const:
418 return &ppir_node_to_const(node)->dest;
419 case ppir_node_type_load_texture:
420 return &ppir_node_to_load_texture(node)->dest;
421 default:
422 return NULL;
423 }
424 }
425
426 static inline void ppir_node_target_assign(ppir_src *src, ppir_dest *dest)
427 {
428 src->type = dest->type;
429 switch (src->type) {
430 case ppir_target_ssa:
431 src->ssa = &dest->ssa;
432 break;
433 case ppir_target_register:
434 src->reg = dest->reg;
435 break;
436 case ppir_target_pipeline:
437 src->pipeline = dest->pipeline;
438 break;
439 }
440 }
441
442 static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
443 {
444 if (src->type != dest->type ||
445 (src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
446 (src->type == ppir_target_register && src->reg != dest->reg) ||
447 (src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
448 return false;
449
450 return true;
451 }
452
453 static inline int ppir_target_get_src_reg_index(ppir_src *src)
454 {
455 switch (src->type) {
456 case ppir_target_ssa:
457 return src->ssa->index;
458 case ppir_target_register:
459 return src->reg->index;
460 case ppir_target_pipeline:
461 if (src->pipeline == ppir_pipeline_reg_discard)
462 return 15 * 4;
463 return (src->pipeline + 12) * 4;
464 }
465
466 return -1;
467 }
468
469 static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
470 {
471 switch (dest->type) {
472 case ppir_target_ssa:
473 return dest->ssa.index;
474 case ppir_target_register:
475 return dest->reg->index;
476 case ppir_target_pipeline:
477 if (dest->pipeline == ppir_pipeline_reg_discard)
478 return 15 * 4;
479 return (dest->pipeline + 12) * 4;
480 }
481
482 return -1;
483 }
484
485 static inline bool ppir_target_is_scaler(ppir_dest *dest)
486 {
487 switch (dest->type) {
488 case ppir_target_ssa:
489 return dest->ssa.num_components == 1;
490 case ppir_target_register:
491 /* only one bit in mask is set */
492 if ((dest->write_mask & 0x3) == 0x3 ||
493 (dest->write_mask & 0x5) == 0x5 ||
494 (dest->write_mask & 0x9) == 0x9 ||
495 (dest->write_mask & 0x6) == 0x6 ||
496 (dest->write_mask & 0xa) == 0xa ||
497 (dest->write_mask & 0xc) == 0xc)
498 return false;
499 else
500 return true;
501 case ppir_target_pipeline:
502 if (dest->pipeline == ppir_pipeline_reg_fmul)
503 return true;
504 else
505 return false;
506 default:
507 return false;
508 }
509 }
510
511 ppir_instr *ppir_instr_create(ppir_block *block);
512 bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
513 void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
514 void ppir_instr_print_list(ppir_compiler *comp);
515 void ppir_instr_print_dep(ppir_compiler *comp);
516 void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
517
518 #define ppir_instr_foreach_succ(instr, dep) \
519 list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
520 #define ppir_instr_foreach_succ_safe(instr, dep) \
521 list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
522 #define ppir_instr_foreach_pred(instr, dep) \
523 list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
524 #define ppir_instr_foreach_pred_safe(instr, dep) \
525 list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
526
527 static inline bool ppir_instr_is_root(ppir_instr *instr)
528 {
529 return list_empty(&instr->succ_list);
530 }
531
532 static inline bool ppir_instr_is_leaf(ppir_instr *instr)
533 {
534 return list_empty(&instr->pred_list);
535 }
536
537 bool ppir_lower_prog(ppir_compiler *comp);
538 bool ppir_node_to_instr(ppir_compiler *comp);
539 bool ppir_schedule_prog(ppir_compiler *comp);
540 bool ppir_regalloc_prog(ppir_compiler *comp);
541 bool ppir_codegen_prog(ppir_compiler *comp);
542
543 #endif