821107302d71fd99ea76c2460cbf4e1c46d18013
[mesa.git] / src / gallium / drivers / lima / ir / pp / ppir.h
1 /*
2 * Copyright (c) 2017 Lima Project
3 * Copyright (c) 2013 Connor Abbott
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 *
23 */
24
25 #ifndef LIMA_IR_PP_PPIR_H
26 #define LIMA_IR_PP_PPIR_H
27
28 #include "util/u_math.h"
29 #include "util/list.h"
30 #include "util/set.h"
31
32 #include "ir/lima_ir.h"
33
34 typedef enum {
35 ppir_op_mov,
36 ppir_op_abs,
37 ppir_op_neg,
38 ppir_op_sat,
39 ppir_op_add,
40
41 ppir_op_ddx,
42 ppir_op_ddy,
43
44 ppir_op_mul,
45 ppir_op_rcp,
46
47 ppir_op_sin_lut,
48 ppir_op_cos_lut,
49
50 ppir_op_sum3,
51 ppir_op_sum4,
52
53 ppir_op_normalize2,
54 ppir_op_normalize3,
55 ppir_op_normalize4,
56
57 ppir_op_select,
58
59 ppir_op_sin,
60 ppir_op_cos,
61 ppir_op_tan,
62 ppir_op_asin,
63 ppir_op_acos,
64
65 ppir_op_atan,
66 ppir_op_atan2,
67 ppir_op_atan_pt1,
68 ppir_op_atan2_pt1,
69 ppir_op_atan_pt2,
70
71 ppir_op_exp,
72 ppir_op_log,
73 ppir_op_exp2,
74 ppir_op_log2,
75 ppir_op_sqrt,
76 ppir_op_rsqrt,
77
78 ppir_op_sign,
79 ppir_op_floor,
80 ppir_op_ceil,
81 ppir_op_fract,
82 ppir_op_mod,
83 ppir_op_min,
84 ppir_op_max,
85 ppir_op_trunc,
86
87 ppir_op_and,
88 ppir_op_or,
89 ppir_op_xor,
90
91 ppir_op_lt,
92 ppir_op_gt,
93 ppir_op_le,
94 ppir_op_ge,
95 ppir_op_eq,
96 ppir_op_ne,
97 ppir_op_not,
98
99 ppir_op_load_uniform,
100 ppir_op_load_varying,
101 ppir_op_load_coords,
102 ppir_op_load_coords_reg,
103 ppir_op_load_fragcoord,
104 ppir_op_load_pointcoord,
105 ppir_op_load_frontface,
106 ppir_op_load_texture,
107 ppir_op_load_temp,
108
109 ppir_op_store_temp,
110
111 ppir_op_const,
112
113 ppir_op_discard,
114 ppir_op_branch,
115
116 ppir_op_undef,
117 ppir_op_dummy,
118
119 ppir_op_num,
120 } ppir_op;
121
122 typedef enum {
123 ppir_node_type_alu,
124 ppir_node_type_const,
125 ppir_node_type_load,
126 ppir_node_type_store,
127 ppir_node_type_load_texture,
128 ppir_node_type_discard,
129 ppir_node_type_branch,
130 } ppir_node_type;
131
132 typedef struct {
133 char *name;
134 ppir_node_type type;
135 int *slots;
136 } ppir_op_info;
137
138 extern const ppir_op_info ppir_op_infos[];
139
140 typedef enum {
141 ppir_dep_src,
142 ppir_dep_write_after_read,
143 ppir_dep_sequence,
144 } ppir_dep_type;
145
146 typedef struct {
147 void *pred, *succ;
148 ppir_dep_type type;
149 struct list_head pred_link;
150 struct list_head succ_link;
151 } ppir_dep;
152
153 typedef struct ppir_node {
154 struct list_head list;
155 ppir_op op;
156 ppir_node_type type;
157 int index;
158 char name[16];
159 bool printed;
160 struct ppir_instr *instr;
161 int instr_pos;
162 struct ppir_block *block;
163 bool is_end;
164
165 /* for scheduler */
166 struct list_head succ_list;
167 struct list_head pred_list;
168 } ppir_node;
169
170 typedef enum {
171 ppir_pipeline_reg_const0,
172 ppir_pipeline_reg_const1,
173 ppir_pipeline_reg_sampler,
174 ppir_pipeline_reg_uniform,
175 ppir_pipeline_reg_vmul,
176 ppir_pipeline_reg_fmul,
177 ppir_pipeline_reg_discard, /* varying load */
178 } ppir_pipeline;
179
180 typedef struct ppir_reg {
181 struct list_head list;
182 int index;
183 int regalloc_index;
184 int num_components;
185
186 /* whether this reg has to start from the x component
187 * of a full physical reg, this is true for reg used
188 * in load/store instr which has no swizzle field */
189 bool is_head;
190 bool spilled;
191 bool undef;
192 } ppir_reg;
193
194 typedef enum {
195 ppir_target_ssa,
196 ppir_target_pipeline,
197 ppir_target_register,
198 } ppir_target;
199
200 typedef struct ppir_src {
201 ppir_target type;
202 ppir_node *node;
203
204 union {
205 ppir_reg *ssa;
206 ppir_reg *reg;
207 ppir_pipeline pipeline;
208 };
209
210 uint8_t swizzle[4];
211 bool absolute, negate;
212 } ppir_src;
213
214 typedef enum {
215 ppir_outmod_none,
216 ppir_outmod_clamp_fraction,
217 ppir_outmod_clamp_positive,
218 ppir_outmod_round,
219 } ppir_outmod;
220
221 typedef struct ppir_dest {
222 ppir_target type;
223
224 union {
225 ppir_reg ssa;
226 ppir_reg *reg;
227 ppir_pipeline pipeline;
228 };
229
230 ppir_outmod modifier;
231 unsigned write_mask : 4;
232 } ppir_dest;
233
234 typedef struct {
235 ppir_node node;
236 ppir_dest dest;
237 ppir_src src[3];
238 int num_src;
239 int shift : 3; /* Only used for ppir_op_mul */
240 } ppir_alu_node;
241
242 typedef struct ppir_const {
243 union fi value[4];
244 int num;
245 } ppir_const;
246
247 typedef struct {
248 ppir_node node;
249 ppir_const constant;
250 ppir_dest dest;
251 } ppir_const_node;
252
253 typedef struct {
254 ppir_node node;
255 int index;
256 int num_components;
257 ppir_dest dest;
258 ppir_src src;
259 int num_src;
260 } ppir_load_node;
261
262 typedef struct {
263 ppir_node node;
264 int index;
265 int num_components;
266 ppir_src src;
267 } ppir_store_node;
268
269 typedef struct {
270 ppir_node node;
271 ppir_dest dest;
272 ppir_src src[2]; /* src[0] temporarily stores src_coords,
273 not to be used after lowering */
274 int num_src;
275 int sampler;
276 int sampler_dim;
277 bool lod_bias_en;
278 bool explicit_lod;
279 } ppir_load_texture_node;
280
281 typedef struct {
282 ppir_node node;
283 } ppir_discard_node;
284
285 enum ppir_instr_slot {
286 PPIR_INSTR_SLOT_VARYING,
287 PPIR_INSTR_SLOT_TEXLD,
288 PPIR_INSTR_SLOT_UNIFORM,
289 PPIR_INSTR_SLOT_ALU_VEC_MUL,
290 PPIR_INSTR_SLOT_ALU_SCL_MUL,
291 PPIR_INSTR_SLOT_ALU_VEC_ADD,
292 PPIR_INSTR_SLOT_ALU_SCL_ADD,
293 PPIR_INSTR_SLOT_ALU_COMBINE,
294 PPIR_INSTR_SLOT_STORE_TEMP,
295 PPIR_INSTR_SLOT_BRANCH,
296 PPIR_INSTR_SLOT_NUM,
297 PPIR_INSTR_SLOT_END,
298 PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
299 PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
300 };
301
302 struct ppir_liveness {
303 ppir_reg *reg;
304 unsigned mask : 4;
305 };
306
307 typedef struct ppir_instr {
308 struct list_head list;
309 int index;
310 bool printed;
311 int seq; /* command sequence after schedule */
312
313 ppir_node *slots[PPIR_INSTR_SLOT_NUM];
314 ppir_const constant[2];
315 bool is_end;
316
317 /* for scheduler */
318 struct list_head succ_list;
319 struct list_head pred_list;
320 float reg_pressure;
321 int est; /* earliest start time */
322 int parent_index;
323 bool scheduled;
324 int offset;
325 int encode_size;
326
327 /* for liveness analysis */
328 struct ppir_liveness *live_in;
329 struct ppir_liveness *live_out;
330 /* live_internal is to mark registers only live within an
331 * instruction, without propagation */
332 struct ppir_liveness *live_internal;
333 struct set *live_in_set;
334 struct set *live_out_set;
335 struct set *live_internal_set;
336 } ppir_instr;
337
338 typedef struct ppir_block {
339 struct list_head list;
340 struct list_head node_list;
341 struct list_head instr_list;
342
343 struct ppir_block *successors[2];
344
345 struct ppir_compiler *comp;
346
347 /* for scheduler */
348 int sched_instr_index;
349 int sched_instr_base;
350 int index;
351
352 /* for liveness analysis */
353 struct ppir_liveness *live_in;
354 struct ppir_liveness *live_out;
355 struct set *live_in_set;
356 struct set *live_out_set;
357 } ppir_block;
358
359 typedef struct {
360 ppir_node node;
361 ppir_src src[2];
362 int num_src;
363 bool cond_gt;
364 bool cond_eq;
365 bool cond_lt;
366 bool negate;
367 ppir_block *target;
368 } ppir_branch_node;
369
370 struct ra_regs;
371 struct lima_fs_shader_state;
372
373 typedef struct ppir_compiler {
374 struct list_head block_list;
375 struct hash_table_u64 *blocks;
376 int cur_index;
377 int cur_instr_index;
378
379 struct list_head reg_list;
380
381 /* array for searching ssa/reg node */
382 ppir_node **var_nodes;
383 unsigned reg_base;
384
385 struct ra_regs *ra;
386 struct lima_fs_shader_state *prog;
387 bool uses_discard;
388
389 /* for scheduler */
390 int sched_instr_base;
391
392 /* for regalloc spilling debug */
393 int force_spilling;
394
395 /* shaderdb */
396 int num_loops;
397 int num_spills;
398 int num_fills;
399
400 ppir_block *discard_block;
401 ppir_block *current_block;
402 ppir_block *loop_break_block;
403 ppir_block *loop_cont_block;
404 } ppir_compiler;
405
406 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
407 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred, ppir_dep_type type);
408 void ppir_node_remove_dep(ppir_dep *dep);
409 void ppir_node_delete(ppir_node *node);
410 void ppir_node_print_prog(ppir_compiler *comp);
411 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
412 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
413 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
414 ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred);
415 /* Assumes that node successors are in the same block */
416 ppir_node *ppir_node_insert_mov(ppir_node *node);
417 ppir_node *ppir_node_insert_mov_all_blocks(ppir_node *node);
418
419 static inline bool ppir_node_is_root(ppir_node *node)
420 {
421 return list_is_empty(&node->succ_list);
422 }
423
424 static inline bool ppir_node_is_leaf(ppir_node *node)
425 {
426 return list_is_empty(&node->pred_list);
427 }
428
429 static inline bool ppir_node_has_single_succ(ppir_node *node)
430 {
431 return list_is_singular(&node->succ_list);
432 }
433
434 bool ppir_node_has_single_src_succ(ppir_node *node);
435
436 static inline ppir_node *ppir_node_first_succ(ppir_node *node)
437 {
438 return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
439 }
440
441 static inline bool ppir_node_has_single_pred(ppir_node *node)
442 {
443 return list_is_singular(&node->pred_list);
444 }
445
446 static inline ppir_node *ppir_node_first_pred(ppir_node *node)
447 {
448 return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
449 }
450
451 #define ppir_node_foreach_succ(node, dep) \
452 list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
453 #define ppir_node_foreach_succ_safe(node, dep) \
454 list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
455 #define ppir_node_foreach_pred(node, dep) \
456 list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
457 #define ppir_node_foreach_pred_safe(node, dep) \
458 list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
459
460 #define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
461 #define ppir_node_to_const(node) ((ppir_const_node *)(node))
462 #define ppir_node_to_load(node) ((ppir_load_node *)(node))
463 #define ppir_node_to_store(node) ((ppir_store_node *)(node))
464 #define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
465 #define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
466 #define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
467
468 static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
469 {
470 switch (node->type) {
471 case ppir_node_type_alu:
472 return &ppir_node_to_alu(node)->dest;
473 case ppir_node_type_load:
474 return &ppir_node_to_load(node)->dest;
475 case ppir_node_type_const:
476 return &ppir_node_to_const(node)->dest;
477 case ppir_node_type_load_texture:
478 return &ppir_node_to_load_texture(node)->dest;
479 default:
480 return NULL;
481 }
482 }
483
484 static inline int ppir_node_get_src_num(ppir_node *node)
485 {
486 switch (node->type) {
487 case ppir_node_type_alu:
488 return ppir_node_to_alu(node)->num_src;
489 case ppir_node_type_branch:
490 return ppir_node_to_branch(node)->num_src;
491 case ppir_node_type_load:
492 return ppir_node_to_load(node)->num_src;
493 case ppir_node_type_load_texture:
494 return ppir_node_to_load_texture(node)->num_src;
495 case ppir_node_type_store:
496 return 1;
497 default:
498 return 0;
499 }
500
501 return 0;
502 }
503
504 static inline ppir_src *ppir_node_get_src(ppir_node *node, int idx)
505 {
506 if (idx < 0 || idx >= ppir_node_get_src_num(node))
507 return NULL;
508
509 switch (node->type) {
510 case ppir_node_type_alu:
511 return &ppir_node_to_alu(node)->src[idx];
512 case ppir_node_type_branch:
513 return &ppir_node_to_branch(node)->src[idx];
514 case ppir_node_type_load_texture:
515 return &ppir_node_to_load_texture(node)->src[idx];
516 case ppir_node_type_load:
517 return &ppir_node_to_load(node)->src;
518 case ppir_node_type_store:
519 return &ppir_node_to_store(node)->src;
520 default:
521 break;
522 }
523
524 return NULL;
525 }
526
527 static inline ppir_reg *ppir_src_get_reg(ppir_src *src)
528 {
529 switch (src->type) {
530 case ppir_target_ssa:
531 return src->ssa;
532 case ppir_target_register:
533 return src->reg;
534 default:
535 return NULL;
536 }
537 }
538
539 static inline ppir_reg *ppir_dest_get_reg(ppir_dest *dest)
540 {
541 switch (dest->type) {
542 case ppir_target_ssa:
543 return &dest->ssa;
544 case ppir_target_register:
545 return dest->reg;
546 default:
547 return NULL;
548 }
549 }
550
551 static inline void ppir_node_target_assign(ppir_src *src, ppir_node *node)
552 {
553 ppir_dest *dest = ppir_node_get_dest(node);
554 src->type = dest->type;
555 switch (src->type) {
556 case ppir_target_ssa:
557 src->ssa = &dest->ssa;
558 src->node = node;
559 break;
560 case ppir_target_register:
561 src->reg = dest->reg;
562 /* Registers can be assigned from multiple nodes, so don't keep
563 * pointer to the node here
564 */
565 src->node = NULL;
566 break;
567 case ppir_target_pipeline:
568 src->pipeline = dest->pipeline;
569 src->node = node;
570 break;
571 }
572 }
573
574 static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
575 {
576 if (src->type != dest->type ||
577 (src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
578 (src->type == ppir_target_register && src->reg != dest->reg) ||
579 (src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
580 return false;
581
582 return true;
583 }
584
585 static inline int ppir_target_get_src_reg_index(ppir_src *src)
586 {
587 switch (src->type) {
588 case ppir_target_ssa:
589 if (src->ssa)
590 return src->ssa->index;
591 break;
592 case ppir_target_register:
593 if (src->reg)
594 return src->reg->index;
595 break;
596 case ppir_target_pipeline:
597 if (src->pipeline == ppir_pipeline_reg_discard)
598 return 15 * 4;
599 return (src->pipeline + 12) * 4;
600 }
601
602 return -1;
603 }
604
605 static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
606 {
607 switch (dest->type) {
608 case ppir_target_ssa:
609 return dest->ssa.index;
610 case ppir_target_register:
611 return dest->reg->index;
612 case ppir_target_pipeline:
613 if (dest->pipeline == ppir_pipeline_reg_discard)
614 return 15 * 4;
615 return (dest->pipeline + 12) * 4;
616 }
617
618 return -1;
619 }
620
621 static inline int ppir_src_get_mask(ppir_src *src)
622 {
623 ppir_reg *reg = ppir_src_get_reg(src);
624 int mask = 0;
625
626 for (int i = 0; i < reg->num_components; i++)
627 mask |= (1 << src->swizzle[i]);
628
629 return mask;
630 }
631
632 static inline bool ppir_target_is_scalar(ppir_dest *dest)
633 {
634 switch (dest->type) {
635 case ppir_target_ssa:
636 return dest->ssa.num_components == 1;
637 case ppir_target_register:
638 /* only one bit in mask is set */
639 if ((dest->write_mask & 0x3) == 0x3 ||
640 (dest->write_mask & 0x5) == 0x5 ||
641 (dest->write_mask & 0x9) == 0x9 ||
642 (dest->write_mask & 0x6) == 0x6 ||
643 (dest->write_mask & 0xa) == 0xa ||
644 (dest->write_mask & 0xc) == 0xc)
645 return false;
646 else
647 return true;
648 case ppir_target_pipeline:
649 if (dest->pipeline == ppir_pipeline_reg_fmul)
650 return true;
651 else
652 return false;
653 default:
654 return false;
655 }
656 }
657
658 static inline bool ppir_node_schedulable_slot(ppir_node *node,
659 enum ppir_instr_slot slot)
660 {
661 int *slots = ppir_op_infos[node->op].slots;
662 for (int i = 0; slots[i] != PPIR_INSTR_SLOT_END; i++)
663 if (slots[i] == slot)
664 return true;
665
666 return false;
667 }
668
669 ppir_instr *ppir_instr_create(ppir_block *block);
670 bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
671 void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
672 void ppir_instr_print_list(ppir_compiler *comp);
673 void ppir_instr_print_dep(ppir_compiler *comp);
674 void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
675
676 #define ppir_instr_foreach_succ(instr, dep) \
677 list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
678 #define ppir_instr_foreach_succ_safe(instr, dep) \
679 list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
680 #define ppir_instr_foreach_pred(instr, dep) \
681 list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
682 #define ppir_instr_foreach_pred_safe(instr, dep) \
683 list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
684
685 static inline bool ppir_instr_is_root(ppir_instr *instr)
686 {
687 return list_is_empty(&instr->succ_list);
688 }
689
690 static inline bool ppir_instr_is_leaf(ppir_instr *instr)
691 {
692 return list_is_empty(&instr->pred_list);
693 }
694
695 bool ppir_lower_prog(ppir_compiler *comp);
696 bool ppir_node_to_instr(ppir_compiler *comp);
697 bool ppir_schedule_prog(ppir_compiler *comp);
698 bool ppir_regalloc_prog(ppir_compiler *comp);
699 bool ppir_codegen_prog(ppir_compiler *comp);
700 void ppir_liveness_analysis(ppir_compiler *comp);
701
702 #endif