lima/ppir: add dummy op
[mesa.git] / src / gallium / drivers / lima / ir / pp / ppir.h
1 /*
2 * Copyright (c) 2017 Lima Project
3 * Copyright (c) 2013 Connor Abbott
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 *
23 */
24
25 #ifndef LIMA_IR_PP_PPIR_H
26 #define LIMA_IR_PP_PPIR_H
27
28 #include "util/u_math.h"
29 #include "util/list.h"
30
31 #include "ir/lima_ir.h"
32
33 typedef enum {
34 ppir_op_mov,
35 ppir_op_abs,
36 ppir_op_neg,
37 ppir_op_sat,
38 ppir_op_add,
39
40 ppir_op_ddx,
41 ppir_op_ddy,
42
43 ppir_op_mul,
44 ppir_op_rcp,
45
46 ppir_op_sin_lut,
47 ppir_op_cos_lut,
48
49 ppir_op_sum3,
50 ppir_op_sum4,
51
52 ppir_op_normalize2,
53 ppir_op_normalize3,
54 ppir_op_normalize4,
55
56 ppir_op_sel_cond,
57 ppir_op_select,
58
59 ppir_op_sin,
60 ppir_op_cos,
61 ppir_op_tan,
62 ppir_op_asin,
63 ppir_op_acos,
64
65 ppir_op_atan,
66 ppir_op_atan2,
67 ppir_op_atan_pt1,
68 ppir_op_atan2_pt1,
69 ppir_op_atan_pt2,
70
71 ppir_op_exp,
72 ppir_op_log,
73 ppir_op_exp2,
74 ppir_op_log2,
75 ppir_op_sqrt,
76 ppir_op_rsqrt,
77
78 ppir_op_sign,
79 ppir_op_floor,
80 ppir_op_ceil,
81 ppir_op_fract,
82 ppir_op_mod,
83 ppir_op_min,
84 ppir_op_max,
85 ppir_op_trunc,
86
87 ppir_op_and,
88 ppir_op_or,
89 ppir_op_xor,
90
91 ppir_op_lt,
92 ppir_op_gt,
93 ppir_op_le,
94 ppir_op_ge,
95 ppir_op_eq,
96 ppir_op_ne,
97 ppir_op_not,
98
99 ppir_op_load_uniform,
100 ppir_op_load_varying,
101 ppir_op_load_coords,
102 ppir_op_load_fragcoord,
103 ppir_op_load_pointcoord,
104 ppir_op_load_frontface,
105 ppir_op_load_texture,
106 ppir_op_load_temp,
107
108 ppir_op_store_temp,
109 ppir_op_store_color,
110
111 ppir_op_const,
112
113 ppir_op_discard,
114 ppir_op_branch,
115
116 ppir_op_dummy,
117
118 ppir_op_num,
119 } ppir_op;
120
121 typedef enum {
122 ppir_node_type_alu,
123 ppir_node_type_const,
124 ppir_node_type_load,
125 ppir_node_type_store,
126 ppir_node_type_load_texture,
127 ppir_node_type_discard,
128 ppir_node_type_branch,
129 } ppir_node_type;
130
131 typedef struct {
132 char *name;
133 ppir_node_type type;
134 int *slots;
135 } ppir_op_info;
136
137 extern const ppir_op_info ppir_op_infos[];
138
139 typedef struct {
140 void *pred, *succ;
141 struct list_head pred_link;
142 struct list_head succ_link;
143 } ppir_dep;
144
145 typedef struct ppir_node {
146 struct list_head list;
147 ppir_op op;
148 ppir_node_type type;
149 int index;
150 char name[16];
151 bool printed;
152 struct ppir_instr *instr;
153 int instr_pos;
154 struct ppir_block *block;
155
156 /* for scheduler */
157 struct list_head succ_list;
158 struct list_head pred_list;
159 } ppir_node;
160
161 typedef enum {
162 ppir_pipeline_reg_const0,
163 ppir_pipeline_reg_const1,
164 ppir_pipeline_reg_sampler,
165 ppir_pipeline_reg_uniform,
166 ppir_pipeline_reg_vmul,
167 ppir_pipeline_reg_fmul,
168 ppir_pipeline_reg_discard, /* varying load */
169 } ppir_pipeline;
170
171 typedef struct ppir_reg {
172 struct list_head list;
173 int index;
174 int num_components;
175 /* whether this reg has to start from the x component
176 * of a full physical reg, this is true for reg used
177 * in load/store instr which has no swizzle field
178 */
179 bool is_head;
180 /* instr live range */
181 int live_in, live_out;
182 bool spilled;
183 } ppir_reg;
184
185 typedef enum {
186 ppir_target_ssa,
187 ppir_target_pipeline,
188 ppir_target_register,
189 } ppir_target;
190
191 typedef struct ppir_src {
192 ppir_target type;
193 ppir_node *node;
194
195 union {
196 ppir_reg *ssa;
197 ppir_reg *reg;
198 ppir_pipeline pipeline;
199 };
200
201 uint8_t swizzle[4];
202 bool absolute, negate;
203 } ppir_src;
204
205 typedef enum {
206 ppir_outmod_none,
207 ppir_outmod_clamp_fraction,
208 ppir_outmod_clamp_positive,
209 ppir_outmod_round,
210 } ppir_outmod;
211
212 typedef struct ppir_dest {
213 ppir_target type;
214
215 union {
216 ppir_reg ssa;
217 ppir_reg *reg;
218 ppir_pipeline pipeline;
219 };
220
221 ppir_outmod modifier;
222 unsigned write_mask : 4;
223 } ppir_dest;
224
225 typedef struct {
226 ppir_node node;
227 ppir_dest dest;
228 ppir_src src[3];
229 int num_src;
230 int shift : 3; /* Only used for ppir_op_mul */
231 } ppir_alu_node;
232
233 typedef struct ppir_const {
234 union fi value[4];
235 int num;
236 } ppir_const;
237
238 typedef struct {
239 ppir_node node;
240 ppir_const constant;
241 ppir_dest dest;
242 } ppir_const_node;
243
244 typedef struct {
245 ppir_node node;
246 int index;
247 int num_components;
248 ppir_dest dest;
249 ppir_src src;
250 } ppir_load_node;
251
252 typedef struct {
253 ppir_node node;
254 int index;
255 int num_components;
256 ppir_src src;
257 } ppir_store_node;
258
259 typedef struct {
260 ppir_node node;
261 ppir_dest dest;
262 ppir_src src_coords; /* not to be used after lowering */
263 int sampler;
264 int sampler_dim;
265 } ppir_load_texture_node;
266
267 typedef struct {
268 ppir_node node;
269 } ppir_discard_node;
270
271 enum ppir_instr_slot {
272 PPIR_INSTR_SLOT_VARYING,
273 PPIR_INSTR_SLOT_TEXLD,
274 PPIR_INSTR_SLOT_UNIFORM,
275 PPIR_INSTR_SLOT_ALU_VEC_MUL,
276 PPIR_INSTR_SLOT_ALU_SCL_MUL,
277 PPIR_INSTR_SLOT_ALU_VEC_ADD,
278 PPIR_INSTR_SLOT_ALU_SCL_ADD,
279 PPIR_INSTR_SLOT_ALU_COMBINE,
280 PPIR_INSTR_SLOT_STORE_TEMP,
281 PPIR_INSTR_SLOT_BRANCH,
282 PPIR_INSTR_SLOT_NUM,
283 PPIR_INSTR_SLOT_END,
284 PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
285 PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
286 };
287
288 typedef struct ppir_instr {
289 struct list_head list;
290 int index;
291 bool printed;
292 int seq; /* command sequence after schedule */
293
294 ppir_node *slots[PPIR_INSTR_SLOT_NUM];
295 ppir_const constant[2];
296 bool is_end;
297
298 /* for scheduler */
299 struct list_head succ_list;
300 struct list_head pred_list;
301 float reg_pressure;
302 int est; /* earliest start time */
303 int parent_index;
304 bool scheduled;
305 int offset;
306 int encode_size;
307 } ppir_instr;
308
309 typedef struct ppir_block {
310 struct list_head list;
311 struct list_head node_list;
312 struct list_head instr_list;
313 struct ppir_compiler *comp;
314
315 /* for scheduler */
316 int sched_instr_index;
317 int sched_instr_base;
318 } ppir_block;
319
320 typedef struct {
321 ppir_node node;
322 ppir_src src[2];
323 int num_src;
324 bool cond_gt;
325 bool cond_eq;
326 bool cond_lt;
327 bool negate;
328 ppir_block *target;
329 } ppir_branch_node;
330
331 struct ra_regs;
332 struct lima_fs_shader_state;
333
334 typedef struct ppir_compiler {
335 struct list_head block_list;
336 int cur_index;
337 int cur_instr_index;
338
339 struct list_head reg_list;
340
341 /* array for searching ssa/reg node */
342 ppir_node **var_nodes;
343 unsigned reg_base;
344
345 struct ra_regs *ra;
346 struct lima_fs_shader_state *prog;
347
348 /* for scheduler */
349 int sched_instr_base;
350
351 /* for regalloc spilling debug */
352 int force_spilling;
353
354 /* shaderdb */
355 int num_loops;
356 int num_spills;
357 int num_fills;
358
359 ppir_block *discard_block;
360 } ppir_compiler;
361
362 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
363 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred);
364 void ppir_node_remove_dep(ppir_dep *dep);
365 void ppir_node_delete(ppir_node *node);
366 void ppir_node_print_prog(ppir_compiler *comp);
367 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
368 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
369 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
370 ppir_node *ppir_node_clone(ppir_block *block, ppir_node *node);
371
372 static inline bool ppir_node_is_root(ppir_node *node)
373 {
374 return list_empty(&node->succ_list);
375 }
376
377 static inline bool ppir_node_is_leaf(ppir_node *node)
378 {
379 return list_empty(&node->pred_list);
380 }
381
382 static inline bool ppir_node_has_single_succ(ppir_node *node)
383 {
384 return list_is_singular(&node->succ_list);
385 }
386
387 static inline ppir_node *ppir_node_first_succ(ppir_node *node)
388 {
389 return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
390 }
391
392 static inline bool ppir_node_has_single_pred(ppir_node *node)
393 {
394 return list_is_singular(&node->pred_list);
395 }
396
397 static inline ppir_node *ppir_node_first_pred(ppir_node *node)
398 {
399 return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
400 }
401
402 #define ppir_node_foreach_succ(node, dep) \
403 list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
404 #define ppir_node_foreach_succ_safe(node, dep) \
405 list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
406 #define ppir_node_foreach_pred(node, dep) \
407 list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
408 #define ppir_node_foreach_pred_safe(node, dep) \
409 list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
410
411 #define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
412 #define ppir_node_to_const(node) ((ppir_const_node *)(node))
413 #define ppir_node_to_load(node) ((ppir_load_node *)(node))
414 #define ppir_node_to_store(node) ((ppir_store_node *)(node))
415 #define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
416 #define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
417 #define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
418
419 static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
420 {
421 switch (node->type) {
422 case ppir_node_type_alu:
423 return &ppir_node_to_alu(node)->dest;
424 case ppir_node_type_load:
425 return &ppir_node_to_load(node)->dest;
426 case ppir_node_type_const:
427 return &ppir_node_to_const(node)->dest;
428 case ppir_node_type_load_texture:
429 return &ppir_node_to_load_texture(node)->dest;
430 default:
431 return NULL;
432 }
433 }
434
435 static inline int ppir_node_get_src_num(ppir_node *node)
436 {
437 switch (node->type) {
438 case ppir_node_type_alu:
439 return ppir_node_to_alu(node)->num_src;
440 case ppir_node_type_branch:
441 return ppir_node_to_branch(node)->num_src;
442 case ppir_node_type_load_texture:
443 case ppir_node_type_load:
444 case ppir_node_type_store:
445 return 1;
446 default:
447 return 0;
448 }
449
450 return 0;
451 }
452
453 static inline ppir_src *ppir_node_get_src(ppir_node *node, int idx)
454 {
455 if (idx < 0 || idx >= ppir_node_get_src_num(node))
456 return NULL;
457
458 switch (node->type) {
459 case ppir_node_type_alu:
460 return &ppir_node_to_alu(node)->src[idx];
461 case ppir_node_type_branch:
462 return &ppir_node_to_branch(node)->src[idx];
463 case ppir_node_type_load_texture:
464 return &ppir_node_to_load_texture(node)->src_coords;
465 case ppir_node_type_load:
466 return &ppir_node_to_load(node)->src;
467 case ppir_node_type_store:
468 return &ppir_node_to_store(node)->src;
469 default:
470 break;
471 }
472
473 return NULL;
474 }
475
476 static inline ppir_src *ppir_node_get_src_for_pred(ppir_node *node, ppir_node *pred)
477 {
478 for (int i = 0; i < ppir_node_get_src_num(node); i++) {
479 ppir_src *src = ppir_node_get_src(node, i);
480 if (src && src->node == pred)
481 return src;
482 }
483
484 return NULL;
485 }
486
487 static inline void ppir_node_target_assign(ppir_src *src, ppir_node *node)
488 {
489 ppir_dest *dest = ppir_node_get_dest(node);
490 src->type = dest->type;
491 switch (src->type) {
492 case ppir_target_ssa:
493 src->ssa = &dest->ssa;
494 src->node = node;
495 break;
496 case ppir_target_register:
497 src->reg = dest->reg;
498 /* Registers can be assigned from multiple nodes, so don't keep
499 * pointer to the node here
500 */
501 src->node = NULL;
502 break;
503 case ppir_target_pipeline:
504 src->pipeline = dest->pipeline;
505 src->node = node;
506 break;
507 }
508 }
509
510 static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
511 {
512 if (src->type != dest->type ||
513 (src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
514 (src->type == ppir_target_register && src->reg != dest->reg) ||
515 (src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
516 return false;
517
518 return true;
519 }
520
521 static inline int ppir_target_get_src_reg_index(ppir_src *src)
522 {
523 switch (src->type) {
524 case ppir_target_ssa:
525 if (src->ssa)
526 return src->ssa->index;
527 break;
528 case ppir_target_register:
529 if (src->reg)
530 return src->reg->index;
531 break;
532 case ppir_target_pipeline:
533 if (src->pipeline == ppir_pipeline_reg_discard)
534 return 15 * 4;
535 return (src->pipeline + 12) * 4;
536 }
537
538 return -1;
539 }
540
541 static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
542 {
543 switch (dest->type) {
544 case ppir_target_ssa:
545 return dest->ssa.index;
546 case ppir_target_register:
547 return dest->reg->index;
548 case ppir_target_pipeline:
549 if (dest->pipeline == ppir_pipeline_reg_discard)
550 return 15 * 4;
551 return (dest->pipeline + 12) * 4;
552 }
553
554 return -1;
555 }
556
557 static inline bool ppir_target_is_scaler(ppir_dest *dest)
558 {
559 switch (dest->type) {
560 case ppir_target_ssa:
561 return dest->ssa.num_components == 1;
562 case ppir_target_register:
563 /* only one bit in mask is set */
564 if ((dest->write_mask & 0x3) == 0x3 ||
565 (dest->write_mask & 0x5) == 0x5 ||
566 (dest->write_mask & 0x9) == 0x9 ||
567 (dest->write_mask & 0x6) == 0x6 ||
568 (dest->write_mask & 0xa) == 0xa ||
569 (dest->write_mask & 0xc) == 0xc)
570 return false;
571 else
572 return true;
573 case ppir_target_pipeline:
574 if (dest->pipeline == ppir_pipeline_reg_fmul)
575 return true;
576 else
577 return false;
578 default:
579 return false;
580 }
581 }
582
583 ppir_instr *ppir_instr_create(ppir_block *block);
584 bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
585 void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
586 void ppir_instr_print_list(ppir_compiler *comp);
587 void ppir_instr_print_dep(ppir_compiler *comp);
588 void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
589
590 #define ppir_instr_foreach_succ(instr, dep) \
591 list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
592 #define ppir_instr_foreach_succ_safe(instr, dep) \
593 list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
594 #define ppir_instr_foreach_pred(instr, dep) \
595 list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
596 #define ppir_instr_foreach_pred_safe(instr, dep) \
597 list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
598
599 static inline bool ppir_instr_is_root(ppir_instr *instr)
600 {
601 return list_empty(&instr->succ_list);
602 }
603
604 static inline bool ppir_instr_is_leaf(ppir_instr *instr)
605 {
606 return list_empty(&instr->pred_list);
607 }
608
609 bool ppir_lower_prog(ppir_compiler *comp);
610 bool ppir_node_to_instr(ppir_compiler *comp);
611 bool ppir_schedule_prog(ppir_compiler *comp);
612 bool ppir_regalloc_prog(ppir_compiler *comp);
613 bool ppir_codegen_prog(ppir_compiler *comp);
614
615 #endif