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panfrost: Rename pan_bo_cache.c into pan_bo.c
[mesa.git] / src / gallium / drivers / lima / lima_draw.c
1 /*
2 * Copyright (c) 2011-2013 Luc Verhaegen <libv@skynet.be>
3 * Copyright (c) 2017-2019 Lima Project
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "util/u_math.h"
27 #include "util/u_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_half.h"
30 #include "util/u_helpers.h"
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/hash_table.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36 #include "util/u_vbuf.h"
37
38 #include "lima_context.h"
39 #include "lima_screen.h"
40 #include "lima_resource.h"
41 #include "lima_program.h"
42 #include "lima_bo.h"
43 #include "lima_submit.h"
44 #include "lima_texture.h"
45 #include "lima_util.h"
46 #include "lima_fence.h"
47 #include "lima_format.h"
48
49 #include <drm-uapi/lima_drm.h>
50
51 struct lima_gp_frame_reg {
52 uint32_t vs_cmd_start;
53 uint32_t vs_cmd_end;
54 uint32_t plbu_cmd_start;
55 uint32_t plbu_cmd_end;
56 uint32_t tile_heap_start;
57 uint32_t tile_heap_end;
58 };
59
60 struct lima_pp_frame_reg {
61 uint32_t plbu_array_address;
62 uint32_t render_address;
63 uint32_t unused_0;
64 uint32_t flags;
65 uint32_t clear_value_depth;
66 uint32_t clear_value_stencil;
67 uint32_t clear_value_color;
68 uint32_t clear_value_color_1;
69 uint32_t clear_value_color_2;
70 uint32_t clear_value_color_3;
71 uint32_t width;
72 uint32_t height;
73 uint32_t fragment_stack_address;
74 uint32_t fragment_stack_size;
75 uint32_t unused_1;
76 uint32_t unused_2;
77 uint32_t one;
78 uint32_t supersampled_height;
79 uint32_t dubya;
80 uint32_t onscreen;
81 uint32_t blocking;
82 uint32_t scale;
83 uint32_t foureight;
84 };
85
86 struct lima_pp_wb_reg {
87 uint32_t type;
88 uint32_t address;
89 uint32_t pixel_format;
90 uint32_t downsample_factor;
91 uint32_t pixel_layout;
92 uint32_t pitch;
93 uint32_t mrt_bits;
94 uint32_t mrt_pitch;
95 uint32_t zero;
96 uint32_t unused0;
97 uint32_t unused1;
98 uint32_t unused2;
99 };
100
101 struct lima_render_state {
102 uint32_t blend_color_bg;
103 uint32_t blend_color_ra;
104 uint32_t alpha_blend;
105 uint32_t depth_test;
106 uint32_t depth_range;
107 uint32_t stencil_front;
108 uint32_t stencil_back;
109 uint32_t stencil_test;
110 uint32_t multi_sample;
111 uint32_t shader_address;
112 uint32_t varying_types;
113 uint32_t uniforms_address;
114 uint32_t textures_address;
115 uint32_t aux0;
116 uint32_t aux1;
117 uint32_t varyings_address;
118 };
119
120
121 /* plbu commands */
122 #define PLBU_CMD_BEGIN(max) { \
123 int i = 0, max_n = max; \
124 uint32_t *plbu_cmd = util_dynarray_ensure_cap(&ctx->plbu_cmd_array, ctx->plbu_cmd_array.size + max_n * 4);
125
126 #define PLBU_CMD_END() \
127 assert(i <= max_n); \
128 ctx->plbu_cmd_array.size += i * 4; \
129 }
130
131 #define PLBU_CMD(v1, v2) \
132 do { \
133 plbu_cmd[i++] = v1; \
134 plbu_cmd[i++] = v2; \
135 } while (0)
136
137 #define PLBU_CMD_BLOCK_STEP(shift_min, shift_h, shift_w) \
138 PLBU_CMD(((shift_min) << 28) | ((shift_h) << 16) | (shift_w), 0x1000010C)
139 #define PLBU_CMD_TILED_DIMENSIONS(tiled_w, tiled_h) \
140 PLBU_CMD((((tiled_w) - 1) << 24) | (((tiled_h) - 1) << 8), 0x10000109)
141 #define PLBU_CMD_BLOCK_STRIDE(block_w) PLBU_CMD((block_w) & 0xff, 0x30000000)
142 #define PLBU_CMD_ARRAY_ADDRESS(gp_stream, block_num) \
143 PLBU_CMD(gp_stream, 0x28000000 | ((block_num) - 1) | 1)
144 #define PLBU_CMD_VIEWPORT_X(v) PLBU_CMD(v, 0x10000107)
145 #define PLBU_CMD_VIEWPORT_W(v) PLBU_CMD(v, 0x10000108)
146 #define PLBU_CMD_VIEWPORT_Y(v) PLBU_CMD(v, 0x10000105)
147 #define PLBU_CMD_VIEWPORT_H(v) PLBU_CMD(v, 0x10000106)
148 #define PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN() PLBU_CMD(0x00010002, 0x60000000)
149 #define PLBU_CMD_ARRAYS_SEMAPHORE_END() PLBU_CMD(0x00010001, 0x60000000)
150 #define PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, index_size) \
151 PLBU_CMD(((low_prim) ? 0x00003200 : 0x00002200) | (cull) | ((index_size) << 9), 0x1000010B)
152 #define PLBU_CMD_RSW_VERTEX_ARRAY(rsw, gl_pos) \
153 PLBU_CMD(rsw, 0x80000000 | ((gl_pos) >> 4))
154 #define PLBU_CMD_SCISSORS(minx, maxx, miny, maxy) \
155 PLBU_CMD(((minx) << 30) | ((maxy) - 1) << 15 | (miny), \
156 0x70000000 | ((maxx) - 1) << 13 | ((minx) >> 2))
157 #define PLBU_CMD_UNKNOWN1() PLBU_CMD(0x00000000, 0x1000010A)
158 #define PLBU_CMD_UNKNOWN2() PLBU_CMD(0x00000200, 0x1000010B)
159 #define PLBU_CMD_LOW_PRIM_SIZE(v) PLBU_CMD(v, 0x1000010D)
160 #define PLBU_CMD_DEPTH_RANGE_NEAR(v) PLBU_CMD(v, 0x1000010E)
161 #define PLBU_CMD_DEPTH_RANGE_FAR(v) PLBU_CMD(v, 0x1000010F)
162 #define PLBU_CMD_INDEXED_DEST(gl_pos) PLBU_CMD(gl_pos, 0x10000100)
163 #define PLBU_CMD_INDICES(va) PLBU_CMD(va, 0x10000101)
164 #define PLBU_CMD_DRAW_ARRAYS(mode, start, count) \
165 PLBU_CMD(((count) << 24) | (start), (((mode) & 0x1F) << 16) | ((count) >> 8))
166 #define PLBU_CMD_DRAW_ELEMENTS(mode, start, count) \
167 PLBU_CMD(((count) << 24) | (start), \
168 0x00200000 | (((mode) & 0x1F) << 16) | ((count) >> 8))
169
170 /* vs commands */
171 #define VS_CMD_BEGIN(max) { \
172 int i = 0, max_n = max; \
173 uint32_t *vs_cmd = util_dynarray_ensure_cap(&ctx->vs_cmd_array, ctx->vs_cmd_array.size + max_n * 4);
174
175 #define VS_CMD_END() \
176 assert(i <= max_n); \
177 ctx->vs_cmd_array.size += i * 4; \
178 }
179
180 #define VS_CMD(v1, v2) \
181 do { \
182 vs_cmd[i++] = v1; \
183 vs_cmd[i++] = v2; \
184 } while (0)
185
186 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1() VS_CMD(0x00028000, 0x50000000)
187 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2() VS_CMD(0x00000001, 0x50000000)
188 #define VS_CMD_ARRAYS_SEMAPHORE_END(index_draw) \
189 VS_CMD((index_draw) ? 0x00018000 : 0x00000000, 0x50000000)
190 #define VS_CMD_UNIFORMS_ADDRESS(addr, size) \
191 VS_CMD(addr, 0x30000000 | ((size) << 12))
192 #define VS_CMD_SHADER_ADDRESS(addr, size) \
193 VS_CMD(addr, 0x40000000 | ((size) << 12))
194 #define VS_CMD_SHADER_INFO(prefetch, size) \
195 VS_CMD(((prefetch) << 20) | ((((size) >> 4) - 1) << 10), 0x10000040)
196 #define VS_CMD_VARYING_ATTRIBUTE_COUNT(nv, na) \
197 VS_CMD((((nv) - 1) << 8) | (((na) - 1) << 24), 0x10000042)
198 #define VS_CMD_UNKNOWN1() VS_CMD(0x00000003, 0x10000041)
199 #define VS_CMD_UNKNOWN2() VS_CMD(0x00000000, 0x60000000)
200 #define VS_CMD_ATTRIBUTES_ADDRESS(addr, na) \
201 VS_CMD(addr, 0x20000000 | ((na) << 17))
202 #define VS_CMD_VARYINGS_ADDRESS(addr, nv) \
203 VS_CMD(addr, 0x20000008 | ((nv) << 17))
204 #define VS_CMD_DRAW(num, index_draw) \
205 VS_CMD(((num) << 24) | ((index_draw) ? 1 : 0), ((num) >> 8))
206
207 static inline bool
208 lima_ctx_dirty(struct lima_context *ctx)
209 {
210 return ctx->plbu_cmd_array.size;
211 }
212
213 static bool
214 lima_fb_need_reload(struct lima_context *ctx)
215 {
216 /* Depth buffer is always discarded */
217 if (!ctx->framebuffer.base.nr_cbufs)
218 return false;
219 if (ctx->damage.region) {
220 /* for EGL_KHR_partial_update we just want to reload the
221 * region not aligned to tile boundary */
222 if (!ctx->damage.aligned)
223 return true;
224 }
225 else {
226 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
227 if (surf->reload)
228 return true;
229 }
230
231 return false;
232 }
233
234 static void
235 lima_pack_reload_plbu_cmd(struct lima_context *ctx)
236 {
237 #define lima_reload_render_state_offset 0x0000
238 #define lima_reload_gl_pos_offset 0x0040
239 #define lima_reload_varying_offset 0x0080
240 #define lima_reload_tex_desc_offset 0x00c0
241 #define lima_reload_tex_array_offset 0x0100
242 #define lima_reload_buffer_size 0x0140
243
244 void *cpu;
245 unsigned offset;
246 struct pipe_resource *pres = NULL;
247 u_upload_alloc(ctx->uploader, 0, lima_reload_buffer_size,
248 0x40, &offset, &pres, &cpu);
249
250 struct lima_resource *res = lima_resource(pres);
251 uint32_t va = res->bo->va + offset;
252
253 struct lima_screen *screen = lima_screen(ctx->base.screen);
254
255 uint32_t reload_shader_first_instr_size =
256 ((uint32_t *)(screen->pp_buffer->map + pp_reload_program_offset))[0] & 0x1f;
257 uint32_t reload_shader_va = screen->pp_buffer->va + pp_reload_program_offset;
258
259 struct lima_render_state reload_render_state = {
260 .alpha_blend = 0xf03b1ad2,
261 .depth_test = 0x0000000e,
262 .depth_range = 0xffff0000,
263 .stencil_front = 0x00000007,
264 .stencil_back = 0x00000007,
265 .multi_sample = 0x0000f007,
266 .shader_address = reload_shader_va | reload_shader_first_instr_size,
267 .varying_types = 0x00000001,
268 .textures_address = va + lima_reload_tex_array_offset,
269 .aux0 = 0x00004021,
270 .varyings_address = va + lima_reload_varying_offset,
271 };
272 memcpy(cpu + lima_reload_render_state_offset, &reload_render_state,
273 sizeof(reload_render_state));
274
275 struct lima_context_framebuffer *fb = &ctx->framebuffer;
276 lima_tex_desc *td = cpu + lima_reload_tex_desc_offset;
277 memset(td, 0, lima_min_tex_desc_size);
278 lima_texture_desc_set_res(ctx, td, fb->base.cbufs[0]->texture, 0, 0);
279 td->unknown_1_1 = 0x80;
280 td->texture_2d = 1;
281 td->min_img_filter_nearest = 1;
282 td->mag_img_filter_nearest = 1;
283 td->wrap_s_clamp_to_edge = 1;
284 td->wrap_t_clamp_to_edge = 1;
285 td->unknown_2_2 = 0x1;
286
287 uint32_t *ta = cpu + lima_reload_tex_array_offset;
288 ta[0] = va + lima_reload_tex_desc_offset;
289
290 float reload_gl_pos[] = {
291 fb->base.width, 0, 0, 1,
292 0, 0, 0, 1,
293 0, fb->base.height, 0, 1,
294 };
295 memcpy(cpu + lima_reload_gl_pos_offset, reload_gl_pos,
296 sizeof(reload_gl_pos));
297
298 float reload_varying[] = {
299 fb->base.width, 0, 0, 0,
300 0, fb->base.height, 0, 0,
301 };
302 memcpy(cpu + lima_reload_varying_offset, reload_varying,
303 sizeof(reload_varying));
304
305 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
306 pipe_resource_reference(&pres, NULL);
307
308 PLBU_CMD_BEGIN(20);
309
310 PLBU_CMD_VIEWPORT_X(0);
311 PLBU_CMD_VIEWPORT_W(fui(fb->base.width));
312 PLBU_CMD_VIEWPORT_Y(0);
313 PLBU_CMD_VIEWPORT_H(fui(fb->base.height));
314
315 PLBU_CMD_RSW_VERTEX_ARRAY(
316 va + lima_reload_render_state_offset,
317 va + lima_reload_gl_pos_offset);
318
319 PLBU_CMD_UNKNOWN2();
320 PLBU_CMD_UNKNOWN1();
321
322 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
323 PLBU_CMD_INDEXED_DEST(va + lima_reload_gl_pos_offset);
324 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
325
326 PLBU_CMD_END();
327 }
328
329 static void
330 lima_pack_clear_plbu_cmd(struct lima_context *ctx)
331 {
332 #define lima_clear_render_state_offset 0x0000
333 #define lima_clear_shader_offset 0x0040
334 #define lima_clear_buffer_size 0x0080
335
336 void *cpu;
337 unsigned offset;
338 struct pipe_resource *pres = NULL;
339 u_upload_alloc(ctx->uploader, 0, lima_clear_buffer_size,
340 0x40, &offset, &pres, &cpu);
341
342 struct lima_resource *res = lima_resource(pres);
343 uint32_t va = res->bo->va + offset;
344
345 struct lima_screen *screen = lima_screen(ctx->base.screen);
346 uint32_t gl_pos_va = screen->pp_buffer->va + pp_clear_gl_pos_offset;
347
348 /* const0 clear_color, mov.v1 $0 ^const0.xxxx, stop */
349 uint32_t clear_shader[] = {
350 0x00021025, 0x0000000c,
351 (ctx->clear.color_16pc << 12) | 0x000007cf,
352 ctx->clear.color_16pc >> 12,
353 ctx->clear.color_16pc >> 44,
354 };
355 memcpy(cpu + lima_clear_shader_offset, &clear_shader,
356 sizeof(clear_shader));
357
358 uint32_t clear_shader_va = va + lima_clear_shader_offset;
359 uint32_t clear_shader_first_instr_size = clear_shader[0] & 0x1f;
360
361 struct lima_render_state clear_render_state = {
362 .blend_color_bg = 0x00800080,
363 .blend_color_ra = 0x00ff0080,
364 .alpha_blend = 0xfc321892,
365 .depth_test = 0x0000003e,
366 .depth_range = 0xffff0000,
367 .stencil_front = 0x00000007,
368 .stencil_back = 0x00000007,
369 .multi_sample = 0x0000f007,
370 .shader_address = clear_shader_va | clear_shader_first_instr_size,
371 };
372 memcpy(cpu + lima_clear_render_state_offset, &clear_render_state,
373 sizeof(clear_render_state));
374
375 PLBU_CMD_BEGIN(22);
376
377 PLBU_CMD_VIEWPORT_X(0);
378 PLBU_CMD_VIEWPORT_W(0x45800000);
379 PLBU_CMD_VIEWPORT_Y(0);
380 PLBU_CMD_VIEWPORT_H(0x45800000);
381
382 struct pipe_scissor_state *scissor = &ctx->scissor;
383 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
384
385 PLBU_CMD_RSW_VERTEX_ARRAY(va + lima_clear_render_state_offset, gl_pos_va);
386
387 PLBU_CMD_UNKNOWN2();
388 PLBU_CMD_UNKNOWN1();
389
390 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
391 PLBU_CMD_INDEXED_DEST(gl_pos_va);
392 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
393
394 PLBU_CMD_END();
395 }
396
397 static void
398 lima_pack_head_plbu_cmd(struct lima_context *ctx)
399 {
400 /* first draw need create a PLBU command header */
401 if (lima_ctx_dirty(ctx))
402 return;
403
404 struct lima_context_framebuffer *fb = &ctx->framebuffer;
405
406 PLBU_CMD_BEGIN(10);
407
408 PLBU_CMD_UNKNOWN2();
409 PLBU_CMD_BLOCK_STEP(fb->shift_min, fb->shift_h, fb->shift_w);
410 PLBU_CMD_TILED_DIMENSIONS(fb->tiled_w, fb->tiled_h);
411 PLBU_CMD_BLOCK_STRIDE(fb->block_w);
412
413 PLBU_CMD_ARRAY_ADDRESS(
414 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size,
415 fb->block_w * fb->block_h);
416
417 PLBU_CMD_END();
418
419 if (lima_fb_need_reload(ctx))
420 lima_pack_reload_plbu_cmd(ctx);
421 }
422
423 static bool
424 lima_is_scissor_zero(struct lima_context *ctx)
425 {
426 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
427 return false;
428
429 struct pipe_scissor_state *scissor = &ctx->scissor;
430 return
431 scissor->minx == scissor->maxx
432 && scissor->miny == scissor->maxy;
433 }
434
435 static bool
436 lima_is_scissor_full_fb(struct lima_context *ctx)
437 {
438 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
439 return true;
440
441 struct pipe_scissor_state *scissor = &ctx->scissor;
442 struct lima_context_framebuffer *fb = &ctx->framebuffer;
443 return
444 scissor->minx == 0 && scissor->maxx == fb->base.width &&
445 scissor->miny == 0 && scissor->maxy == fb->base.height;
446 }
447
448 static void
449 hilbert_rotate(int n, int *x, int *y, int rx, int ry)
450 {
451 if (ry == 0) {
452 if (rx == 1) {
453 *x = n-1 - *x;
454 *y = n-1 - *y;
455 }
456
457 /* Swap x and y */
458 int t = *x;
459 *x = *y;
460 *y = t;
461 }
462 }
463
464 static void
465 hilbert_coords(int n, int d, int *x, int *y)
466 {
467 int rx, ry, i, t=d;
468
469 *x = *y = 0;
470
471 for (i = 0; (1 << i) < n; i++) {
472
473 rx = 1 & (t / 2);
474 ry = 1 & (t ^ rx);
475
476 hilbert_rotate(1 << i, x, y, rx, ry);
477
478 *x += rx << i;
479 *y += ry << i;
480
481 t /= 4;
482 }
483 }
484
485 static int
486 lima_get_pp_stream_size(int num_pp, int tiled_w, int tiled_h, uint32_t *off)
487 {
488 /* carefully calculate each stream start address:
489 * 1. overflow: each stream size may be different due to
490 * fb->tiled_w * fb->tiled_h can't be divided by num_pp,
491 * extra size should be added to the preceeding stream
492 * 2. alignment: each stream address should be 0x20 aligned
493 */
494 int delta = tiled_w * tiled_h / num_pp * 16 + 8;
495 int remain = tiled_w * tiled_h % num_pp;
496 int offset = 0;
497
498 for (int i = 0; i < num_pp; i++) {
499 off[i] = offset;
500
501 offset += delta;
502 if (remain) {
503 offset += 16;
504 remain--;
505 }
506 offset = align(offset, 0x20);
507 }
508
509 return offset;
510 }
511
512 static bool
513 inside_damage_region(int x, int y, struct lima_damage_state *ds)
514 {
515 if (!ds->region)
516 return true;
517
518 for (int i = 0; i < ds->num_region; i++) {
519 struct pipe_scissor_state *ss = ds->region + i;
520 if (x >= ss->minx && x < ss->maxx &&
521 y >= ss->miny && y < ss->maxy)
522 return true;
523 }
524
525 return false;
526 }
527
528 static void
529 lima_update_pp_stream(struct lima_context *ctx, int off_x, int off_y,
530 int tiled_w, int tiled_h)
531 {
532 struct lima_pp_stream_state *ps = &ctx->pp_stream;
533 struct lima_context_framebuffer *fb = &ctx->framebuffer;
534 struct lima_screen *screen = lima_screen(ctx->base.screen);
535 int i, num_pp = screen->num_pp;
536
537 /* use hilbert_coords to generates 1D to 2D relationship.
538 * 1D for pp stream index and 2D for plb block x/y on framebuffer.
539 * if multi pp, interleave the 1D index to make each pp's render target
540 * close enough which should result close workload
541 */
542 int max = MAX2(tiled_w, tiled_h);
543 int dim = util_logbase2_ceil(max);
544 int count = 1 << (dim + dim);
545 int index = 0;
546 uint32_t *stream[4];
547 int si[4] = {0};
548
549 for (i = 0; i < num_pp; i++)
550 stream[i] = ps->bo->map + ps->bo_offset + ps->offset[i];
551
552 for (i = 0; i < count; i++) {
553 int x, y;
554 hilbert_coords(max, i, &x, &y);
555 if (x < tiled_w && y < tiled_h) {
556 x += off_x;
557 y += off_y;
558
559 if (!inside_damage_region(x, y, &ctx->damage))
560 continue;
561
562 int pp = index % num_pp;
563 int offset = ((y >> fb->shift_h) * fb->block_w +
564 (x >> fb->shift_w)) * LIMA_CTX_PLB_BLK_SIZE;
565 int plb_va = ctx->plb[ctx->plb_index]->va + offset;
566
567 stream[pp][si[pp]++] = 0;
568 stream[pp][si[pp]++] = 0xB8000000 | x | (y << 8);
569 stream[pp][si[pp]++] = 0xE0000002 | ((plb_va >> 3) & ~0xE0000003);
570 stream[pp][si[pp]++] = 0xB0000000;
571
572 index++;
573 }
574 }
575
576 for (i = 0; i < num_pp; i++) {
577 stream[i][si[i]++] = 0;
578 stream[i][si[i]++] = 0xBC000000;
579
580 lima_dump_command_stream_print(
581 stream[i], si[i] * 4, false, "pp plb stream %d at va %x\n",
582 i, ps->bo->va + ps->bo_offset + ps->offset[i]);
583 }
584 }
585
586 static void
587 lima_update_damage_pp_stream(struct lima_context *ctx)
588 {
589 struct lima_damage_state *ds = &ctx->damage;
590 struct pipe_scissor_state max = ds->region[0];
591
592 /* find a max region to cover all the damage region */
593 for (int i = 1; i < ds->num_region; i++) {
594 struct pipe_scissor_state *ss = ds->region + i;
595 max.minx = MIN2(max.minx, ss->minx);
596 max.miny = MIN2(max.miny, ss->miny);
597 max.maxx = MAX2(max.maxx, ss->maxx);
598 max.maxy = MAX2(max.maxy, ss->maxy);
599 }
600
601 int tiled_w = max.maxx - max.minx;
602 int tiled_h = max.maxy - max.miny;
603 struct lima_screen *screen = lima_screen(ctx->base.screen);
604 int size = lima_get_pp_stream_size(
605 screen->num_pp, tiled_w, tiled_h, ctx->pp_stream.offset);
606
607 void *cpu;
608 unsigned offset;
609 struct pipe_resource *pres = NULL;
610 u_upload_alloc(ctx->uploader, 0, size, 0x40, &offset, &pres, &cpu);
611
612 struct lima_resource *res = lima_resource(pres);
613 ctx->pp_stream.bo = res->bo;
614 ctx->pp_stream.bo_offset = offset;
615
616 lima_update_pp_stream(ctx, max.minx, max.miny, tiled_w, tiled_h);
617
618 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
619 pipe_resource_reference(&pres, NULL);
620 }
621
622 static void
623 lima_update_full_pp_stream(struct lima_context *ctx)
624 {
625 struct lima_context_framebuffer *fb = &ctx->framebuffer;
626 struct lima_ctx_plb_pp_stream_key key = {
627 .plb_index = ctx->plb_index,
628 .tiled_w = fb->tiled_w,
629 .tiled_h = fb->tiled_h,
630 };
631
632 struct hash_entry *entry =
633 _mesa_hash_table_search(ctx->plb_pp_stream, &key);
634 struct lima_ctx_plb_pp_stream *s = entry->data;
635
636 if (s->bo) {
637 ctx->pp_stream.bo = s->bo;
638 ctx->pp_stream.bo_offset = 0;
639 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
640 }
641 else {
642 struct lima_screen *screen = lima_screen(ctx->base.screen);
643 int size = lima_get_pp_stream_size(
644 screen->num_pp, fb->tiled_w, fb->tiled_h, s->offset);
645 s->bo = lima_bo_create(screen, size, 0);
646 lima_bo_map(s->bo);
647
648 ctx->pp_stream.bo = s->bo;
649 ctx->pp_stream.bo_offset = 0;
650 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
651
652 lima_update_pp_stream(ctx, 0, 0, fb->tiled_w, fb->tiled_h);
653 }
654
655 lima_submit_add_bo(ctx->pp_submit, s->bo, LIMA_SUBMIT_BO_READ);
656 }
657
658 static void
659 lima_update_submit_bo(struct lima_context *ctx)
660 {
661 if (lima_ctx_dirty(ctx))
662 return;
663
664 struct lima_screen *screen = lima_screen(ctx->base.screen);
665 lima_submit_add_bo(ctx->gp_submit, ctx->plb_gp_stream, LIMA_SUBMIT_BO_READ);
666 lima_submit_add_bo(ctx->gp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
667 lima_submit_add_bo(ctx->gp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
668
669 lima_dump_command_stream_print(
670 ctx->plb_gp_stream->map + ctx->plb_index * ctx->plb_gp_size,
671 ctx->plb_gp_size, false, "gp plb stream at va %x\n",
672 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size);
673
674 if (ctx->damage.region)
675 lima_update_damage_pp_stream(ctx);
676 else if (ctx->plb_pp_stream)
677 lima_update_full_pp_stream(ctx);
678 else
679 ctx->pp_stream.bo = NULL;
680
681 if (ctx->framebuffer.base.nr_cbufs) {
682 struct lima_resource *res = lima_resource(ctx->framebuffer.base.cbufs[0]->texture);
683 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
684 }
685 if (ctx->framebuffer.base.zsbuf) {
686 struct lima_resource *res = lima_resource(ctx->framebuffer.base.zsbuf->texture);
687 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
688 }
689 lima_submit_add_bo(ctx->pp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_READ);
690 lima_submit_add_bo(ctx->pp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_READ);
691 lima_submit_add_bo(ctx->pp_submit, screen->pp_buffer, LIMA_SUBMIT_BO_READ);
692 }
693
694 static void
695 lima_clear(struct pipe_context *pctx, unsigned buffers,
696 const union pipe_color_union *color, double depth, unsigned stencil)
697 {
698 struct lima_context *ctx = lima_context(pctx);
699 bool full_fb_clear = lima_is_scissor_full_fb(ctx);
700
701 if (full_fb_clear) {
702 lima_flush(ctx);
703
704 /* no need to reload if cleared */
705 if (ctx->framebuffer.base.nr_cbufs && (buffers & PIPE_CLEAR_COLOR0)) {
706 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
707 surf->reload = false;
708 }
709 }
710
711 struct lima_context_clear *clear = &ctx->clear;
712 clear->buffers = buffers;
713
714 if (buffers & PIPE_CLEAR_COLOR0) {
715 clear->color_8pc =
716 ((uint32_t)float_to_ubyte(color->f[3]) << 24) |
717 ((uint32_t)float_to_ubyte(color->f[2]) << 16) |
718 ((uint32_t)float_to_ubyte(color->f[1]) << 8) |
719 float_to_ubyte(color->f[0]);
720
721 clear->color_16pc =
722 ((uint64_t)float_to_ushort(color->f[3]) << 48) |
723 ((uint64_t)float_to_ushort(color->f[2]) << 32) |
724 ((uint64_t)float_to_ushort(color->f[1]) << 16) |
725 float_to_ushort(color->f[0]);
726 }
727
728 if (buffers & PIPE_CLEAR_DEPTH)
729 clear->depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
730
731 if (buffers & PIPE_CLEAR_STENCIL)
732 clear->stencil = stencil;
733
734 lima_update_submit_bo(ctx);
735
736 lima_pack_head_plbu_cmd(ctx);
737
738 /* partial clear */
739 if (!full_fb_clear)
740 lima_pack_clear_plbu_cmd(ctx);
741
742 ctx->dirty |= LIMA_CONTEXT_DIRTY_CLEAR;
743 }
744
745 enum lima_attrib_type {
746 LIMA_ATTRIB_FLOAT = 0x000,
747 /* todo: find out what lives here. */
748 LIMA_ATTRIB_I16 = 0x004,
749 LIMA_ATTRIB_U16 = 0x005,
750 LIMA_ATTRIB_I8 = 0x006,
751 LIMA_ATTRIB_U8 = 0x007,
752 LIMA_ATTRIB_I8N = 0x008,
753 LIMA_ATTRIB_U8N = 0x009,
754 LIMA_ATTRIB_I16N = 0x00A,
755 LIMA_ATTRIB_U16N = 0x00B,
756 /* todo: where is the 32 int */
757 /* todo: find out what lives here. */
758 LIMA_ATTRIB_FIXED = 0x101
759 };
760
761 static enum lima_attrib_type
762 lima_pipe_format_to_attrib_type(enum pipe_format format)
763 {
764 const struct util_format_description *desc = util_format_description(format);
765 int i = util_format_get_first_non_void_channel(format);
766 const struct util_format_channel_description *c = desc->channel + i;
767
768 switch (c->type) {
769 case UTIL_FORMAT_TYPE_FLOAT:
770 return LIMA_ATTRIB_FLOAT;
771 case UTIL_FORMAT_TYPE_FIXED:
772 return LIMA_ATTRIB_FIXED;
773 case UTIL_FORMAT_TYPE_SIGNED:
774 if (c->size == 8) {
775 if (c->normalized)
776 return LIMA_ATTRIB_I8N;
777 else
778 return LIMA_ATTRIB_I8;
779 }
780 else if (c->size == 16) {
781 if (c->normalized)
782 return LIMA_ATTRIB_I16N;
783 else
784 return LIMA_ATTRIB_I16;
785 }
786 break;
787 case UTIL_FORMAT_TYPE_UNSIGNED:
788 if (c->size == 8) {
789 if (c->normalized)
790 return LIMA_ATTRIB_U8N;
791 else
792 return LIMA_ATTRIB_U8;
793 }
794 else if (c->size == 16) {
795 if (c->normalized)
796 return LIMA_ATTRIB_U16N;
797 else
798 return LIMA_ATTRIB_U16;
799 }
800 break;
801 }
802
803 return LIMA_ATTRIB_FLOAT;
804 }
805
806 static void
807 lima_pack_vs_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
808 {
809 VS_CMD_BEGIN(24);
810
811 if (!info->index_size) {
812 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1();
813 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2();
814 }
815
816 int uniform_size = ctx->vs->uniform_pending_offset + ctx->vs->constant_size + 32;
817 VS_CMD_UNIFORMS_ADDRESS(
818 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, LIMA_CTX_BUFF_SUBMIT_GP),
819 align(uniform_size, 16));
820
821 VS_CMD_SHADER_ADDRESS(ctx->vs->bo->va, ctx->vs->shader_size);
822 VS_CMD_SHADER_INFO(ctx->vs->prefetch, ctx->vs->shader_size);
823
824 int num_varryings = ctx->vs->num_varying;
825 int num_attributes = ctx->vertex_elements->num_elements;
826 VS_CMD_VARYING_ATTRIBUTE_COUNT(num_varryings, num_attributes);
827
828 VS_CMD_UNKNOWN1();
829
830 VS_CMD_ATTRIBUTES_ADDRESS(
831 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, LIMA_CTX_BUFF_SUBMIT_GP),
832 num_attributes);
833
834 VS_CMD_VARYINGS_ADDRESS(
835 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, LIMA_CTX_BUFF_SUBMIT_GP),
836 num_varryings);
837
838 unsigned num = info->index_size ? (ctx->max_index - ctx->min_index + 1) : info->count;
839 VS_CMD_DRAW(num, info->index_size);
840
841 VS_CMD_UNKNOWN2();
842
843 VS_CMD_ARRAYS_SEMAPHORE_END(info->index_size);
844
845 VS_CMD_END();
846 }
847
848 static void
849 lima_pack_plbu_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
850 {
851 lima_pack_head_plbu_cmd(ctx);
852
853 /* If it's zero scissor, we skip adding all other commands */
854 if (lima_is_scissor_zero(ctx))
855 return;
856
857 PLBU_CMD_BEGIN(30);
858
859 PLBU_CMD_VIEWPORT_X(fui(ctx->viewport.x));
860 PLBU_CMD_VIEWPORT_W(fui(ctx->viewport.width));
861 PLBU_CMD_VIEWPORT_Y(fui(ctx->viewport.y));
862 PLBU_CMD_VIEWPORT_H(fui(ctx->viewport.height));
863
864 if (!info->index_size)
865 PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN();
866
867 bool low_prim = info->mode < PIPE_PRIM_TRIANGLES;
868 int cf = ctx->rasterizer->base.cull_face;
869 int ccw = ctx->rasterizer->base.front_ccw;
870 uint32_t cull = 0;
871 if (cf != PIPE_FACE_NONE) {
872 if (cf & PIPE_FACE_FRONT)
873 cull |= ccw ? 0x00040000 : 0x00020000;
874 if (cf & PIPE_FACE_BACK)
875 cull |= ccw ? 0x00020000 : 0x00040000;
876 }
877 PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, info->index_size);
878
879 uint32_t gl_position_va =
880 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
881 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
882 PLBU_CMD_RSW_VERTEX_ARRAY(
883 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, LIMA_CTX_BUFF_SUBMIT_PP),
884 gl_position_va);
885
886 /* TODO
887 * - we should set it only for the first draw that enabled the scissor and for
888 * latter draw only if scissor is dirty
889 */
890 if (ctx->rasterizer->base.scissor) {
891 struct pipe_scissor_state *scissor = &ctx->scissor;
892 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
893 }
894
895 PLBU_CMD_UNKNOWN1();
896
897 PLBU_CMD_DEPTH_RANGE_NEAR(fui(ctx->viewport.near));
898 PLBU_CMD_DEPTH_RANGE_FAR(fui(ctx->viewport.far));
899
900 if (low_prim) {
901 uint32_t v = info->mode == PIPE_PRIM_POINTS ?
902 fui(ctx->rasterizer->base.point_size) : fui(ctx->rasterizer->base.line_width);
903 PLBU_CMD_LOW_PRIM_SIZE(v);
904 }
905
906 if (info->index_size) {
907 PLBU_CMD_INDEXED_DEST(gl_position_va);
908
909 struct pipe_resource *indexbuf = NULL;
910 unsigned index_offset = 0;
911 struct lima_resource *res;
912 if (info->has_user_indices) {
913 util_upload_index_buffer(&ctx->base, info, &indexbuf, &index_offset);
914 res = lima_resource(indexbuf);
915 }
916 else
917 res = lima_resource(info->index.resource);
918
919 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
920 PLBU_CMD_INDICES(res->bo->va + info->start * info->index_size + index_offset);
921
922 if (indexbuf)
923 pipe_resource_reference(&indexbuf, NULL);
924 }
925 else {
926 /* can this make the attribute info static? */
927 PLBU_CMD_DRAW_ARRAYS(info->mode, info->start, info->count);
928 }
929
930 PLBU_CMD_ARRAYS_SEMAPHORE_END();
931
932 if (info->index_size)
933 PLBU_CMD_DRAW_ELEMENTS(info->mode, ctx->min_index, info->count);
934
935 PLBU_CMD_END();
936 }
937
938 static int
939 lima_blend_func(enum pipe_blend_func pipe)
940 {
941 switch (pipe) {
942 case PIPE_BLEND_ADD:
943 return 2;
944 case PIPE_BLEND_SUBTRACT:
945 return 0;
946 case PIPE_BLEND_REVERSE_SUBTRACT:
947 return 1;
948 case PIPE_BLEND_MIN:
949 return 4;
950 case PIPE_BLEND_MAX:
951 return 5;
952 }
953 return -1;
954 }
955
956 static int
957 lima_blend_factor(enum pipe_blendfactor pipe)
958 {
959 switch (pipe) {
960 case PIPE_BLENDFACTOR_ONE:
961 return 11;
962 case PIPE_BLENDFACTOR_SRC_COLOR:
963 return 0;
964 case PIPE_BLENDFACTOR_SRC_ALPHA:
965 return 16;
966 case PIPE_BLENDFACTOR_DST_ALPHA:
967 return 17;
968 case PIPE_BLENDFACTOR_DST_COLOR:
969 return 1;
970 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
971 return 7;
972 case PIPE_BLENDFACTOR_CONST_COLOR:
973 return 2;
974 case PIPE_BLENDFACTOR_CONST_ALPHA:
975 return 18;
976 case PIPE_BLENDFACTOR_ZERO:
977 return 3;
978 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
979 return 8;
980 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
981 return 24;
982 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
983 return 25;
984 case PIPE_BLENDFACTOR_INV_DST_COLOR:
985 return 9;
986 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
987 return 10;
988 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
989 return 26;
990 case PIPE_BLENDFACTOR_SRC1_COLOR:
991 case PIPE_BLENDFACTOR_SRC1_ALPHA:
992 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
993 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
994 return -1; /* not support */
995 }
996 return -1;
997 }
998
999 static int
1000 lima_calculate_alpha_blend(enum pipe_blend_func rgb_func, enum pipe_blend_func alpha_func,
1001 enum pipe_blendfactor rgb_src_factor, enum pipe_blendfactor rgb_dst_factor,
1002 enum pipe_blendfactor alpha_src_factor, enum pipe_blendfactor alpha_dst_factor)
1003 {
1004 return lima_blend_func(rgb_func) |
1005 (lima_blend_func(alpha_func) << 3) |
1006 (lima_blend_factor(rgb_src_factor) << 6) |
1007 (lima_blend_factor(rgb_dst_factor) << 11) |
1008 ((lima_blend_factor(alpha_src_factor) & 0xF) << 16) |
1009 ((lima_blend_factor(alpha_dst_factor) & 0xF) << 20) |
1010 0x0C000000; /* need check if this GLESv1 glAlphaFunc */
1011 }
1012
1013 #if 0
1014 static int
1015 lima_stencil_op(enum pipe_stencil_op pipe)
1016 {
1017 switch (pipe) {
1018 case PIPE_STENCIL_OP_KEEP:
1019 return 0;
1020 case PIPE_STENCIL_OP_ZERO:
1021 return 2;
1022 case PIPE_STENCIL_OP_REPLACE:
1023 return 1;
1024 case PIPE_STENCIL_OP_INCR:
1025 return 6;
1026 case PIPE_STENCIL_OP_DECR:
1027 return 7;
1028 case PIPE_STENCIL_OP_INCR_WRAP:
1029 return 4;
1030 case PIPE_STENCIL_OP_DECR_WRAP:
1031 return 5;
1032 case PIPE_STENCIL_OP_INVERT:
1033 return 3;
1034 }
1035 return -1;
1036 }
1037 #endif
1038
1039 static int
1040 lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer_state *rst)
1041 {
1042 enum pipe_compare_func func = (depth->enabled ? depth->func : PIPE_FUNC_ALWAYS);
1043
1044 int offset_scale = 0;
1045
1046 //TODO: implement polygon offset
1047 #if 0
1048 if (rst->offset_scale < -32)
1049 offset_scale = -32;
1050 else if (rst->offset_scale > 31)
1051 offset_scale = 31;
1052 else
1053 offset_scale = rst->offset_scale * 4;
1054
1055 if (offset_scale < 0)
1056 offset_scale = 0x100 + offset_scale;
1057 #endif
1058
1059 return (depth->enabled && depth->writemask) |
1060 ((int)func << 1) |
1061 (offset_scale << 16) |
1062 0x30; /* find out what is this */
1063 }
1064
1065 static void
1066 lima_pack_render_state(struct lima_context *ctx, const struct pipe_draw_info *info)
1067 {
1068 struct lima_render_state *render =
1069 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_plb_rsw,
1070 sizeof(*render), true);
1071
1072 /* do hw support RGBA independ blend?
1073 * PIPE_CAP_INDEP_BLEND_ENABLE
1074 *
1075 * how to handle the no cbuf only zbuf case?
1076 */
1077 struct pipe_rt_blend_state *rt = ctx->blend->base.rt;
1078 render->blend_color_bg = float_to_ubyte(ctx->blend_color.color[2]) |
1079 (float_to_ubyte(ctx->blend_color.color[1]) << 16);
1080 render->blend_color_ra = float_to_ubyte(ctx->blend_color.color[0]) |
1081 (float_to_ubyte(ctx->blend_color.color[3]) << 16);
1082
1083 if (rt->blend_enable) {
1084 render->alpha_blend = lima_calculate_alpha_blend(rt->rgb_func, rt->alpha_func,
1085 rt->rgb_src_factor, rt->rgb_dst_factor,
1086 rt->alpha_src_factor, rt->alpha_dst_factor);
1087 }
1088 else {
1089 /*
1090 * Special handling for blending disabled.
1091 * Binary driver is generating the same alpha_value,
1092 * as when we would just enable blending, without changing/setting any blend equation/params.
1093 * Normaly in this case mesa would set all rt fields (func/factor) to zero.
1094 */
1095 render->alpha_blend = lima_calculate_alpha_blend(PIPE_BLEND_ADD, PIPE_BLEND_ADD,
1096 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO,
1097 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO);
1098 }
1099
1100 render->alpha_blend |= (rt->colormask & PIPE_MASK_RGBA) << 28;
1101
1102 struct pipe_rasterizer_state *rst = &ctx->rasterizer->base;
1103 struct pipe_depth_state *depth = &ctx->zsa->base.depth;
1104 render->depth_test = lima_calculate_depth_test(depth, rst);
1105
1106 /* overlap with plbu? any place can remove one? */
1107 render->depth_range = float_to_ushort(ctx->viewport.near) |
1108 (float_to_ushort(ctx->viewport.far) << 16);
1109
1110 #if 0
1111 struct pipe_stencil_state *stencil = ctx->zsa->base.stencil;
1112 struct pipe_stencil_ref *ref = &ctx->stencil_ref;
1113 render->stencil_front = stencil[0].func |
1114 (lima_stencil_op(stencil[0].fail_op) << 3) |
1115 (lima_stencil_op(stencil[0].zfail_op) << 6) |
1116 (lima_stencil_op(stencil[0].zpass_op) << 9) |
1117 (ref->ref_value[0] << 16) |
1118 (stencil[0].valuemask << 24);
1119 render->stencil_back = stencil[1].func |
1120 (lima_stencil_op(stencil[1].fail_op) << 3) |
1121 (lima_stencil_op(stencil[1].zfail_op) << 6) |
1122 (lima_stencil_op(stencil[1].zpass_op) << 9) |
1123 (ref->ref_value[1] << 16) |
1124 (stencil[1].valuemask << 24);
1125 #else
1126 render->stencil_front = 0xff000007;
1127 render->stencil_back = 0xff000007;
1128 #endif
1129
1130 /* seems not correct? */
1131 //struct pipe_alpha_state *alpha = &ctx->zsa->base.alpha;
1132 render->stencil_test = 0;
1133 //(stencil->enabled ? 0xFF : 0x00) | (float_to_ubyte(alpha->ref_value) << 16)
1134
1135 /* need more investigation */
1136 if (info->mode == PIPE_PRIM_POINTS)
1137 render->multi_sample = 0x0000F007;
1138 else if (info->mode < PIPE_PRIM_TRIANGLES)
1139 render->multi_sample = 0x0000F407;
1140 else
1141 render->multi_sample = 0x0000F807;
1142 if (ctx->framebuffer.base.samples)
1143 render->multi_sample |= 0x68;
1144
1145 render->shader_address =
1146 ctx->fs->bo->va | (((uint32_t *)ctx->fs->bo->map)[0] & 0x1F);
1147
1148 /* seems not needed */
1149 render->uniforms_address = 0x00000000;
1150
1151 render->textures_address = 0x00000000;
1152
1153 /* more investigation */
1154 render->aux0 = 0x00000300 | (ctx->vs->varying_stride >> 3);
1155 render->aux1 = 0x00003000;
1156
1157 if (ctx->tex_stateobj.num_samplers) {
1158 render->textures_address =
1159 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_tex_desc, LIMA_CTX_BUFF_SUBMIT_PP);
1160 render->aux0 |= ctx->tex_stateobj.num_samplers << 14;
1161 render->aux0 |= 0x20;
1162 }
1163
1164 if (ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer) {
1165 render->uniforms_address =
1166 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, LIMA_CTX_BUFF_SUBMIT_PP);
1167 render->uniforms_address |= ((ctx->buffer_state[lima_ctx_buff_pp_uniform].size) / 4 - 1);
1168 render->aux0 |= 0x80;
1169 render->aux1 |= 0x10000;
1170 }
1171
1172 if (ctx->vs->num_varying > 1) {
1173 render->varying_types = 0x00000000;
1174 render->varyings_address =
1175 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_PP);
1176 for (int i = 1; i < ctx->vs->num_varying; i++) {
1177 int val;
1178
1179 struct lima_varying_info *v = ctx->vs->varying + i;
1180 if (v->component_size == 4)
1181 val = v->components > 2 ? 0 : 1;
1182 else
1183 val = v->components > 2 ? 2 : 3;
1184
1185 int index = i - 1;
1186 if (index < 10)
1187 render->varying_types |= val << (3 * index);
1188 else if (index == 10) {
1189 render->varying_types |= val << 30;
1190 render->varyings_address |= val >> 2;
1191 }
1192 else if (index == 11)
1193 render->varyings_address |= val << 1;
1194 }
1195 }
1196 else {
1197 render->varying_types = 0x00000000;
1198 render->varyings_address = 0x00000000;
1199 }
1200
1201 lima_dump_command_stream_print(
1202 render, sizeof(*render), false, "add render state at va %x\n",
1203 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, 0));
1204 }
1205
1206 static void
1207 lima_update_gp_attribute_info(struct lima_context *ctx, const struct pipe_draw_info *info)
1208 {
1209 struct lima_vertex_element_state *ve = ctx->vertex_elements;
1210 struct lima_context_vertex_buffer *vb = &ctx->vertex_buffers;
1211
1212 uint32_t *attribute =
1213 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_attribute_info,
1214 ve->num_elements * 8, true);
1215
1216 int n = 0;
1217 for (int i = 0; i < ve->num_elements; i++) {
1218 struct pipe_vertex_element *pve = ve->pipe + i;
1219
1220 assert(pve->vertex_buffer_index < vb->count);
1221 assert(vb->enabled_mask & (1 << pve->vertex_buffer_index));
1222
1223 struct pipe_vertex_buffer *pvb = vb->vb + pve->vertex_buffer_index;
1224 struct lima_resource *res = lima_resource(pvb->buffer.resource);
1225
1226 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
1227
1228 unsigned start = info->index_size ? ctx->min_index : info->start;
1229 attribute[n++] = res->bo->va + pvb->buffer_offset + pve->src_offset
1230 + start * pvb->stride;
1231 attribute[n++] = (pvb->stride << 11) |
1232 (lima_pipe_format_to_attrib_type(pve->src_format) << 2) |
1233 (util_format_get_nr_components(pve->src_format) - 1);
1234 }
1235
1236 lima_dump_command_stream_print(
1237 attribute, n * 4, false, "update attribute info at va %x\n",
1238 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, 0));
1239 }
1240
1241 static void
1242 lima_update_gp_uniform(struct lima_context *ctx)
1243 {
1244 struct lima_context_constant_buffer *ccb =
1245 ctx->const_buffer + PIPE_SHADER_VERTEX;
1246 struct lima_vs_shader_state *vs = ctx->vs;
1247
1248 int size = vs->uniform_pending_offset + vs->constant_size + 32;
1249 void *vs_const_buff =
1250 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_uniform, size, true);
1251
1252 if (ccb->buffer)
1253 memcpy(vs_const_buff, ccb->buffer, ccb->size);
1254
1255 memcpy(vs_const_buff + vs->uniform_pending_offset,
1256 ctx->viewport.transform.scale,
1257 sizeof(ctx->viewport.transform.scale));
1258 memcpy(vs_const_buff + vs->uniform_pending_offset + 16,
1259 ctx->viewport.transform.translate,
1260 sizeof(ctx->viewport.transform.translate));
1261
1262 if (vs->constant)
1263 memcpy(vs_const_buff + vs->uniform_pending_offset + 32,
1264 vs->constant, vs->constant_size);
1265
1266 lima_dump_command_stream_print(
1267 vs_const_buff, size, true,
1268 "update gp uniform at va %x\n",
1269 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, 0));
1270 }
1271
1272 static void
1273 lima_update_pp_uniform(struct lima_context *ctx)
1274 {
1275 const float *const_buff = ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer;
1276 size_t const_buff_size = ctx->const_buffer[PIPE_SHADER_FRAGMENT].size / sizeof(float);
1277
1278 if (!const_buff)
1279 return;
1280
1281 uint16_t *fp16_const_buff =
1282 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform,
1283 const_buff_size * sizeof(uint16_t), true);
1284
1285 uint32_t *array =
1286 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform_array, 4, true);
1287
1288 for (int i = 0; i < const_buff_size; i++)
1289 fp16_const_buff[i] = util_float_to_half(const_buff[i]);
1290
1291 *array = lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, LIMA_CTX_BUFF_SUBMIT_PP);
1292
1293 lima_dump_command_stream_print(
1294 fp16_const_buff, const_buff_size * 2, false, "add pp uniform data at va %x\n",
1295 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, 0));
1296 lima_dump_command_stream_print(
1297 array, 4, false, "add pp uniform info at va %x\n",
1298 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, 0));
1299 }
1300
1301 static void
1302 lima_update_varying(struct lima_context *ctx, const struct pipe_draw_info *info)
1303 {
1304 struct lima_vs_shader_state *vs = ctx->vs;
1305
1306 uint32_t *varying =
1307 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_varying_info,
1308 vs->num_varying * 8, true);
1309 int n = 0;
1310
1311 /* should be LIMA_SUBMIT_BO_WRITE for GP, but each draw will use
1312 * different part of this bo, so no need to set exclusive constraint */
1313 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_gl_pos,
1314 4 * 4 * info->count, false);
1315
1316 /* for gl_Position */
1317 varying[n++] =
1318 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
1319 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
1320 varying[n++] = 0x8020;
1321
1322 int offset = 0;
1323 for (int i = 1; i < vs->num_varying; i++) {
1324 struct lima_varying_info *v = vs->varying + i;
1325 int size = v->component_size * 4;
1326
1327 /* does component_size == 2 need to be 16 aligned? */
1328 if (v->component_size == 4)
1329 offset = align(offset, 16);
1330
1331 v->offset = offset;
1332 offset += size;
1333 }
1334 vs->varying_stride = align(offset, 16);
1335
1336 if (vs->num_varying > 1)
1337 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_varying,
1338 vs->varying_stride * info->count, false);
1339
1340 for (int i = 1; i < vs->num_varying; i++) {
1341 struct lima_varying_info *v = vs->varying + i;
1342 varying[n++] =
1343 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_GP) +
1344 v->offset;
1345 varying[n++] = (vs->varying_stride << 11) | (v->components - 1) |
1346 (v->component_size == 2 ? 0x0C : 0);
1347 }
1348
1349 lima_dump_command_stream_print(
1350 varying, n * 4, false, "update varying info at va %x\n",
1351 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, 0));
1352 }
1353
1354 static void
1355 lima_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
1356 {
1357 /* check if draw mode and vertex/index count match,
1358 * otherwise gp will hang */
1359 if (!u_trim_pipe_prim(info->mode, (unsigned*)&info->count)) {
1360 debug_printf("draw mode and vertex/index count mismatch\n");
1361 return;
1362 }
1363
1364 struct lima_context *ctx = lima_context(pctx);
1365
1366 if (!ctx->vs || !ctx->fs) {
1367 debug_warn_once("no shader, skip draw\n");
1368 return;
1369 }
1370
1371 if (!lima_update_vs_state(ctx) || !lima_update_fs_state(ctx))
1372 return;
1373
1374 lima_dump_command_stream_print(
1375 ctx->vs->bo->map, ctx->vs->shader_size, false,
1376 "add vs at va %x\n", ctx->vs->bo->va);
1377
1378 lima_dump_command_stream_print(
1379 ctx->fs->bo->map, ctx->fs->shader_size, false,
1380 "add fs at va %x\n", ctx->fs->bo->va);
1381
1382 lima_submit_add_bo(ctx->gp_submit, ctx->vs->bo, LIMA_SUBMIT_BO_READ);
1383 lima_submit_add_bo(ctx->pp_submit, ctx->fs->bo, LIMA_SUBMIT_BO_READ);
1384
1385 lima_update_submit_bo(ctx);
1386
1387 /* Mali Utgard GPU always need min/max index info for index draw,
1388 * compute it if upper layer does not do for us */
1389 if (info->index_size && info->max_index == ~0u)
1390 u_vbuf_get_minmax_index(pctx, info, &ctx->min_index, &ctx->max_index);
1391 else {
1392 ctx->min_index = info->min_index;
1393 ctx->max_index = info->max_index;
1394 }
1395
1396 lima_update_gp_attribute_info(ctx, info);
1397
1398 if ((ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1399 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty) ||
1400 ctx->dirty & LIMA_CONTEXT_DIRTY_VIEWPORT ||
1401 ctx->dirty & LIMA_CONTEXT_DIRTY_SHADER_VERT) {
1402 lima_update_gp_uniform(ctx);
1403 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty = false;
1404 }
1405
1406 lima_update_varying(ctx, info);
1407
1408 /* If it's zero scissor, don't build vs cmd list */
1409 if (!lima_is_scissor_zero(ctx))
1410 lima_pack_vs_cmd(ctx, info);
1411
1412 if (ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1413 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty) {
1414 lima_update_pp_uniform(ctx);
1415 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty = false;
1416 }
1417
1418 if (ctx->dirty & LIMA_CONTEXT_DIRTY_TEXTURES)
1419 lima_update_textures(ctx);
1420
1421 lima_pack_render_state(ctx, info);
1422 lima_pack_plbu_cmd(ctx, info);
1423
1424 ctx->dirty = 0;
1425 }
1426
1427 static void
1428 lima_finish_plbu_cmd(struct lima_context *ctx)
1429 {
1430 int i = 0;
1431 uint32_t *plbu_cmd = util_dynarray_ensure_cap(&ctx->plbu_cmd_array, ctx->plbu_cmd_array.size + 2 * 4);
1432
1433 plbu_cmd[i++] = 0x00000000;
1434 plbu_cmd[i++] = 0x50000000; /* END */
1435
1436 ctx->plbu_cmd_array.size += i * 4;
1437 }
1438
1439 static void
1440 lima_pack_wb_zsbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1441 {
1442 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1443 struct lima_resource *res = lima_resource(fb->base.zsbuf->texture);
1444 int level = fb->base.zsbuf->u.tex.level;
1445 uint32_t format = lima_format_get_pixel(fb->base.zsbuf->format);
1446
1447 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1448 wb[wb_idx].type = 0x01; /* 1 for depth, stencil */
1449 wb[wb_idx].address = res->bo->va + res->levels[level].offset;
1450 wb[wb_idx].pixel_format = format;
1451 if (res->tiled) {
1452 wb[wb_idx].pixel_layout = 0x2;
1453 wb[wb_idx].pitch = fb->tiled_w;
1454 } else {
1455 wb[wb_idx].pixel_layout = 0x0;
1456 wb[wb_idx].pitch = res->levels[level].stride / 8;
1457 }
1458 wb[wb_idx].mrt_bits = 0;
1459 }
1460
1461 static void
1462 lima_pack_wb_cbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1463 {
1464 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1465 struct lima_resource *res = lima_resource(fb->base.cbufs[0]->texture);
1466 int level = fb->base.cbufs[0]->u.tex.level;
1467 uint32_t format = lima_format_get_pixel(fb->base.cbufs[0]->format);
1468 bool swap_channels = lima_format_get_swap_rb(fb->base.cbufs[0]->format);
1469
1470 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1471 wb[wb_idx].type = 0x02; /* 2 for color buffer */
1472 wb[wb_idx].address = res->bo->va + res->levels[level].offset;
1473 wb[wb_idx].pixel_format = format;
1474 if (res->tiled) {
1475 wb[wb_idx].pixel_layout = 0x2;
1476 wb[wb_idx].pitch = fb->tiled_w;
1477 } else {
1478 wb[wb_idx].pixel_layout = 0x0;
1479 wb[wb_idx].pitch = res->levels[level].stride / 8;
1480 }
1481 wb[wb_idx].mrt_bits = swap_channels ? 0x4 : 0x0;
1482 }
1483
1484
1485 static void
1486 lima_pack_pp_frame_reg(struct lima_context *ctx, uint32_t *frame_reg,
1487 uint32_t *wb_reg)
1488 {
1489 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1490 struct lima_pp_frame_reg *frame = (void *)frame_reg;
1491 struct lima_screen *screen = lima_screen(ctx->base.screen);
1492 int wb_idx = 0;
1493
1494 frame->render_address = screen->pp_buffer->va + pp_frame_rsw_offset;
1495 frame->flags = 0x02;
1496 frame->clear_value_depth = ctx->clear.depth;
1497 frame->clear_value_stencil = ctx->clear.stencil;
1498 frame->clear_value_color = ctx->clear.color_8pc;
1499 frame->clear_value_color_1 = ctx->clear.color_8pc;
1500 frame->clear_value_color_2 = ctx->clear.color_8pc;
1501 frame->clear_value_color_3 = ctx->clear.color_8pc;
1502 frame->one = 1;
1503
1504 frame->width = fb->base.width - 1;
1505 frame->height = fb->base.height - 1;
1506
1507 /* frame->fragment_stack_address is overwritten per-pp in the kernel
1508 * by the values of pp_frame.fragment_stack_address[i] */
1509
1510 /* These are "stack size" and "stack offset" shifted,
1511 * here they are assumed to be always the same. */
1512 uint32_t fs_stack_size = ctx->fs ? ctx->fs->stack_size : 0;
1513 frame->fragment_stack_size = fs_stack_size << 16 | fs_stack_size;
1514
1515 /* related with MSAA and different value when r4p0/r7p0 */
1516 frame->supersampled_height = fb->base.height * 2 - 1;
1517 frame->scale = 0xE0C;
1518
1519 frame->dubya = 0x77;
1520 frame->onscreen = 1;
1521 frame->blocking = (fb->shift_min << 28) | (fb->shift_h << 16) | fb->shift_w;
1522 frame->foureight = 0x8888;
1523
1524 if (fb->base.nr_cbufs)
1525 lima_pack_wb_cbuf_reg(ctx, wb_reg, wb_idx++);
1526
1527 /* Mali4x0 can use on-tile buffer for depth/stencil, so to save some
1528 * memory bandwidth don't write depth/stencil back to memory if we're
1529 * rendering to scanout
1530 */
1531 if (!lima_is_scanout(ctx) && fb->base.zsbuf)
1532 lima_pack_wb_zsbuf_reg(ctx, wb_reg, wb_idx++);
1533 }
1534
1535 static void
1536 _lima_flush(struct lima_context *ctx, bool end_of_frame)
1537 {
1538 #define pp_stack_pp_size 0x400
1539
1540 lima_finish_plbu_cmd(ctx);
1541
1542 int vs_cmd_size = ctx->vs_cmd_array.size;
1543 int plbu_cmd_size = ctx->plbu_cmd_array.size;
1544 uint32_t vs_cmd_va = 0;
1545 uint32_t plbu_cmd_va;
1546
1547 if (vs_cmd_size) {
1548 void *vs_cmd =
1549 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_vs_cmd, vs_cmd_size, true);
1550 memcpy(vs_cmd, util_dynarray_begin(&ctx->vs_cmd_array), vs_cmd_size);
1551 util_dynarray_clear(&ctx->vs_cmd_array);
1552 vs_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_vs_cmd,
1553 LIMA_CTX_BUFF_SUBMIT_GP);
1554
1555 lima_dump_command_stream_print(
1556 vs_cmd, vs_cmd_size, false, "flush vs cmd at va %x\n", vs_cmd_va);
1557 }
1558
1559 void *plbu_cmd =
1560 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_plbu_cmd, plbu_cmd_size, true);
1561 memcpy(plbu_cmd, util_dynarray_begin(&ctx->plbu_cmd_array), plbu_cmd_size);
1562 util_dynarray_clear(&ctx->plbu_cmd_array);
1563 plbu_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_plbu_cmd,
1564 LIMA_CTX_BUFF_SUBMIT_GP);
1565
1566 lima_dump_command_stream_print(
1567 plbu_cmd, plbu_cmd_size, false, "flush plbu cmd at va %x\n", plbu_cmd_va);
1568
1569 struct lima_screen *screen = lima_screen(ctx->base.screen);
1570 struct drm_lima_gp_frame gp_frame;
1571 struct lima_gp_frame_reg *gp_frame_reg = (void *)gp_frame.frame;
1572 gp_frame_reg->vs_cmd_start = vs_cmd_va;
1573 gp_frame_reg->vs_cmd_end = vs_cmd_va + vs_cmd_size;
1574 gp_frame_reg->plbu_cmd_start = plbu_cmd_va;
1575 gp_frame_reg->plbu_cmd_end = plbu_cmd_va + plbu_cmd_size;
1576 gp_frame_reg->tile_heap_start = ctx->gp_tile_heap[ctx->plb_index]->va;
1577 gp_frame_reg->tile_heap_end = ctx->gp_tile_heap[ctx->plb_index]->va + gp_tile_heap_size;
1578
1579 lima_dump_command_stream_print(
1580 &gp_frame, sizeof(gp_frame), false, "add gp frame\n");
1581
1582 if (!lima_submit_start(ctx->gp_submit, &gp_frame, sizeof(gp_frame)))
1583 fprintf(stderr, "gp submit error\n");
1584
1585 if (lima_dump_command_stream) {
1586 if (lima_submit_wait(ctx->gp_submit, PIPE_TIMEOUT_INFINITE)) {
1587 if (ctx->buffer_state[lima_ctx_buff_sh_gl_pos].res) {
1588 float *pos = lima_ctx_buff_map(ctx, lima_ctx_buff_sh_gl_pos);
1589 lima_dump_command_stream_print(
1590 pos, 4 * 4 * 16, true, "gl_pos dump at va %x\n",
1591 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos, 0));
1592 }
1593
1594 uint32_t *plb = lima_bo_map(ctx->plb[ctx->plb_index]);
1595 lima_dump_command_stream_print(
1596 plb, LIMA_CTX_PLB_BLK_SIZE, false, "plb dump at va %x\n",
1597 ctx->plb[ctx->plb_index]->va);
1598 }
1599 else {
1600 fprintf(stderr, "gp submit wait error\n");
1601 exit(1);
1602 }
1603 }
1604
1605 uint32_t pp_stack_va = 0;
1606 if (ctx->pp_max_stack_size) {
1607 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_stack, screen->num_pp *
1608 ctx->pp_max_stack_size * pp_stack_pp_size, true);
1609 pp_stack_va = lima_ctx_buff_va(ctx, lima_ctx_buff_pp_stack,
1610 LIMA_CTX_BUFF_SUBMIT_PP);
1611 }
1612
1613 struct lima_pp_stream_state *ps = &ctx->pp_stream;
1614 if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI400) {
1615 struct drm_lima_m400_pp_frame pp_frame = {0};
1616 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1617 pp_frame.num_pp = screen->num_pp;
1618
1619 for (int i = 0; i < screen->num_pp; i++) {
1620 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1621 if (ctx->pp_max_stack_size)
1622 pp_frame.fragment_stack_address[i] = pp_stack_va +
1623 ctx->pp_max_stack_size * pp_stack_pp_size * i;
1624 }
1625
1626 lima_dump_command_stream_print(
1627 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1628
1629 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1630 fprintf(stderr, "pp submit error\n");
1631 }
1632 else {
1633 struct drm_lima_m450_pp_frame pp_frame = {0};
1634 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1635 pp_frame.num_pp = screen->num_pp;
1636
1637 if (ctx->pp_max_stack_size)
1638 for (int i = 0; i < screen->num_pp; i++)
1639 pp_frame.fragment_stack_address[i] = pp_stack_va +
1640 ctx->pp_max_stack_size * pp_stack_pp_size * i;
1641
1642 if (ps->bo) {
1643 for (int i = 0; i < screen->num_pp; i++)
1644 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1645 }
1646 else {
1647 pp_frame.use_dlbu = true;
1648
1649 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1650 pp_frame.dlbu_regs[0] = ctx->plb[ctx->plb_index]->va;
1651 pp_frame.dlbu_regs[1] = ((fb->tiled_h - 1) << 16) | (fb->tiled_w - 1);
1652 unsigned s = util_logbase2(LIMA_CTX_PLB_BLK_SIZE) - 7;
1653 pp_frame.dlbu_regs[2] = (s << 28) | (fb->shift_h << 16) | fb->shift_w;
1654 pp_frame.dlbu_regs[3] = ((fb->tiled_h - 1) << 24) | ((fb->tiled_w - 1) << 16);
1655 }
1656
1657 lima_dump_command_stream_print(
1658 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1659
1660 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1661 fprintf(stderr, "pp submit error\n");
1662 }
1663
1664 if (lima_dump_command_stream) {
1665 if (!lima_submit_wait(ctx->pp_submit, PIPE_TIMEOUT_INFINITE)) {
1666 fprintf(stderr, "pp wait error\n");
1667 exit(1);
1668 }
1669 }
1670
1671 ctx->plb_index = (ctx->plb_index + 1) % lima_ctx_num_plb;
1672
1673 if (ctx->framebuffer.base.nr_cbufs) {
1674 /* Set reload flag for next draw. It'll be unset if buffer is cleared */
1675 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
1676 surf->reload = true;
1677 }
1678
1679 ctx->pp_max_stack_size = 0;
1680 }
1681
1682 void
1683 lima_flush(struct lima_context *ctx)
1684 {
1685 if (!lima_ctx_dirty(ctx))
1686 return;
1687
1688 _lima_flush(ctx, false);
1689 }
1690
1691 static void
1692 lima_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
1693 unsigned flags)
1694 {
1695 struct lima_context *ctx = lima_context(pctx);
1696 if (lima_ctx_dirty(ctx))
1697 _lima_flush(ctx, flags & PIPE_FLUSH_END_OF_FRAME);
1698
1699 if (fence) {
1700 int fd;
1701 if (lima_submit_get_out_sync(ctx->pp_submit, &fd))
1702 *fence = lima_fence_create(fd);
1703 }
1704 }
1705
1706 void
1707 lima_draw_init(struct lima_context *ctx)
1708 {
1709 ctx->base.clear = lima_clear;
1710 ctx->base.draw_vbo = lima_draw_vbo;
1711 ctx->base.flush = lima_pipe_flush;
1712 }