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lima/ppir: Add fddx and fddy
[mesa.git] / src / gallium / drivers / lima / lima_draw.c
1 /*
2 * Copyright (c) 2011-2013 Luc Verhaegen <libv@skynet.be>
3 * Copyright (c) 2017-2019 Lima Project
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "util/u_math.h"
27 #include "util/u_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_half.h"
30 #include "util/u_helpers.h"
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/hash_table.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36 #include "util/u_vbuf.h"
37
38 #include "lima_context.h"
39 #include "lima_screen.h"
40 #include "lima_resource.h"
41 #include "lima_program.h"
42 #include "lima_bo.h"
43 #include "lima_submit.h"
44 #include "lima_texture.h"
45 #include "lima_util.h"
46 #include "lima_fence.h"
47
48 #include <drm-uapi/lima_drm.h>
49
50 struct lima_gp_frame_reg {
51 uint32_t vs_cmd_start;
52 uint32_t vs_cmd_end;
53 uint32_t plbu_cmd_start;
54 uint32_t plbu_cmd_end;
55 uint32_t tile_heap_start;
56 uint32_t tile_heap_end;
57 };
58
59 struct lima_pp_frame_reg {
60 uint32_t plbu_array_address;
61 uint32_t render_address;
62 uint32_t unused_0;
63 uint32_t flags;
64 uint32_t clear_value_depth;
65 uint32_t clear_value_stencil;
66 uint32_t clear_value_color;
67 uint32_t clear_value_color_1;
68 uint32_t clear_value_color_2;
69 uint32_t clear_value_color_3;
70 uint32_t width;
71 uint32_t height;
72 uint32_t fragment_stack_address;
73 uint32_t fragment_stack_size;
74 uint32_t unused_1;
75 uint32_t unused_2;
76 uint32_t one;
77 uint32_t supersampled_height;
78 uint32_t dubya;
79 uint32_t onscreen;
80 uint32_t blocking;
81 uint32_t scale;
82 uint32_t foureight;
83 };
84
85 struct lima_pp_wb_reg {
86 uint32_t type;
87 uint32_t address;
88 uint32_t pixel_format;
89 uint32_t downsample_factor;
90 uint32_t pixel_layout;
91 uint32_t pitch;
92 uint32_t mrt_bits;
93 uint32_t mrt_pitch;
94 uint32_t zero;
95 uint32_t unused0;
96 uint32_t unused1;
97 uint32_t unused2;
98 };
99
100 struct lima_render_state {
101 uint32_t blend_color_bg;
102 uint32_t blend_color_ra;
103 uint32_t alpha_blend;
104 uint32_t depth_test;
105 uint32_t depth_range;
106 uint32_t stencil_front;
107 uint32_t stencil_back;
108 uint32_t stencil_test;
109 uint32_t multi_sample;
110 uint32_t shader_address;
111 uint32_t varying_types;
112 uint32_t uniforms_address;
113 uint32_t textures_address;
114 uint32_t aux0;
115 uint32_t aux1;
116 uint32_t varyings_address;
117 };
118
119 #define LIMA_PIXEL_FORMAT_B8G8R8A8 0x03
120 #define LIMA_PIXEL_FORMAT_Z16 0x0e
121 #define LIMA_PIXEL_FORMAT_Z24S8 0x0f
122
123 /* plbu commands */
124 #define PLBU_CMD_BEGIN(max) { \
125 int i = 0, max_n = max; \
126 uint32_t *plbu_cmd = util_dynarray_ensure_cap(&ctx->plbu_cmd_array, ctx->plbu_cmd_array.size + max_n * 4);
127
128 #define PLBU_CMD_END() \
129 assert(i <= max_n); \
130 ctx->plbu_cmd_array.size += i * 4; \
131 }
132
133 #define PLBU_CMD(v1, v2) \
134 do { \
135 plbu_cmd[i++] = v1; \
136 plbu_cmd[i++] = v2; \
137 } while (0)
138
139 #define PLBU_CMD_BLOCK_STEP(shift_min, shift_h, shift_w) \
140 PLBU_CMD(((shift_min) << 28) | ((shift_h) << 16) | (shift_w), 0x1000010C)
141 #define PLBU_CMD_TILED_DIMENSIONS(tiled_w, tiled_h) \
142 PLBU_CMD((((tiled_w) - 1) << 24) | (((tiled_h) - 1) << 8), 0x10000109)
143 #define PLBU_CMD_BLOCK_STRIDE(block_w) PLBU_CMD((block_w) & 0xff, 0x30000000)
144 #define PLBU_CMD_ARRAY_ADDRESS(gp_stream, block_num) \
145 PLBU_CMD(gp_stream, 0x28000000 | ((block_num) - 1) | 1)
146 #define PLBU_CMD_VIEWPORT_X(v) PLBU_CMD(v, 0x10000107)
147 #define PLBU_CMD_VIEWPORT_W(v) PLBU_CMD(v, 0x10000108)
148 #define PLBU_CMD_VIEWPORT_Y(v) PLBU_CMD(v, 0x10000105)
149 #define PLBU_CMD_VIEWPORT_H(v) PLBU_CMD(v, 0x10000106)
150 #define PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN() PLBU_CMD(0x00010002, 0x60000000)
151 #define PLBU_CMD_ARRAYS_SEMAPHORE_END() PLBU_CMD(0x00010001, 0x60000000)
152 #define PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, index_size) \
153 PLBU_CMD(((low_prim) ? 0x00003200 : 0x00002200) | (cull) | ((index_size) << 9), 0x1000010B)
154 #define PLBU_CMD_RSW_VERTEX_ARRAY(rsw, gl_pos) \
155 PLBU_CMD(rsw, 0x80000000 | ((gl_pos) >> 4))
156 #define PLBU_CMD_SCISSORS(minx, maxx, miny, maxy) \
157 PLBU_CMD(((minx) << 30) | ((maxy) - 1) << 15 | (miny), \
158 0x70000000 | ((maxx) - 1) << 13 | ((minx) >> 2))
159 #define PLBU_CMD_UNKNOWN1() PLBU_CMD(0x00000000, 0x1000010A)
160 #define PLBU_CMD_UNKNOWN2() PLBU_CMD(0x00000200, 0x1000010B)
161 #define PLBU_CMD_LOW_PRIM_SIZE(v) PLBU_CMD(v, 0x1000010D)
162 #define PLBU_CMD_DEPTH_RANGE_NEAR(v) PLBU_CMD(v, 0x1000010E)
163 #define PLBU_CMD_DEPTH_RANGE_FAR(v) PLBU_CMD(v, 0x1000010F)
164 #define PLBU_CMD_INDEXED_DEST(gl_pos) PLBU_CMD(gl_pos, 0x10000100)
165 #define PLBU_CMD_INDICES(va) PLBU_CMD(va, 0x10000101)
166 #define PLBU_CMD_DRAW_ARRAYS(mode, start, count) \
167 PLBU_CMD(((count) << 24) | (start), (((mode) & 0x1F) << 16) | ((count) >> 8))
168 #define PLBU_CMD_DRAW_ELEMENTS(mode, start, count) \
169 PLBU_CMD(((count) << 24) | (start), \
170 0x00200000 | (((mode) & 0x1F) << 16) | ((count) >> 8))
171
172 /* vs commands */
173 #define VS_CMD_BEGIN(max) { \
174 int i = 0, max_n = max; \
175 uint32_t *vs_cmd = util_dynarray_ensure_cap(&ctx->vs_cmd_array, ctx->vs_cmd_array.size + max_n * 4);
176
177 #define VS_CMD_END() \
178 assert(i <= max_n); \
179 ctx->vs_cmd_array.size += i * 4; \
180 }
181
182 #define VS_CMD(v1, v2) \
183 do { \
184 vs_cmd[i++] = v1; \
185 vs_cmd[i++] = v2; \
186 } while (0)
187
188 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1() VS_CMD(0x00028000, 0x50000000)
189 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2() VS_CMD(0x00000001, 0x50000000)
190 #define VS_CMD_ARRAYS_SEMAPHORE_END(index_draw) \
191 VS_CMD((index_draw) ? 0x00018000 : 0x00000000, 0x50000000)
192 #define VS_CMD_UNIFORMS_ADDRESS(addr, size) \
193 VS_CMD(addr, 0x30000000 | ((size) << 12))
194 #define VS_CMD_SHADER_ADDRESS(addr, size) \
195 VS_CMD(addr, 0x40000000 | ((size) << 12))
196 #define VS_CMD_SHADER_INFO(prefetch, size) \
197 VS_CMD(((prefetch) << 20) | ((((size) >> 4) - 1) << 10), 0x10000040)
198 #define VS_CMD_VARYING_ATTRIBUTE_COUNT(nv, na) \
199 VS_CMD((((nv) - 1) << 8) | (((na) - 1) << 24), 0x10000042)
200 #define VS_CMD_UNKNOWN1() VS_CMD(0x00000003, 0x10000041)
201 #define VS_CMD_UNKNOWN2() VS_CMD(0x00000000, 0x60000000)
202 #define VS_CMD_ATTRIBUTES_ADDRESS(addr, na) \
203 VS_CMD(addr, 0x20000000 | ((na) << 17))
204 #define VS_CMD_VARYINGS_ADDRESS(addr, nv) \
205 VS_CMD(addr, 0x20000008 | ((nv) << 17))
206 #define VS_CMD_DRAW(num, index_draw) \
207 VS_CMD(((num) << 24) | ((index_draw) ? 1 : 0), ((num) >> 8))
208
209 static inline bool
210 lima_ctx_dirty(struct lima_context *ctx)
211 {
212 return ctx->plbu_cmd_array.size;
213 }
214
215 static bool
216 lima_fb_need_reload(struct lima_context *ctx)
217 {
218 /* Depth buffer is always discarded */
219 if (!ctx->framebuffer.base.nr_cbufs)
220 return false;
221 if (ctx->damage.region) {
222 /* for EGL_KHR_partial_update we just want to reload the
223 * region not aligned to tile boundary */
224 if (!ctx->damage.aligned)
225 return true;
226 }
227 else {
228 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
229 if (surf->reload)
230 return true;
231 }
232
233 return false;
234 }
235
236 static void
237 lima_pack_reload_plbu_cmd(struct lima_context *ctx)
238 {
239 #define lima_reload_render_state_offset 0x0000
240 #define lima_reload_gl_pos_offset 0x0040
241 #define lima_reload_varying_offset 0x0080
242 #define lima_reload_tex_desc_offset 0x00c0
243 #define lima_reload_tex_array_offset 0x0100
244 #define lima_reload_buffer_size 0x0140
245
246 void *cpu;
247 unsigned offset;
248 struct pipe_resource *pres = NULL;
249 u_upload_alloc(ctx->uploader, 0, lima_reload_buffer_size,
250 0x40, &offset, &pres, &cpu);
251
252 struct lima_resource *res = lima_resource(pres);
253 uint32_t va = res->bo->va + offset;
254
255 struct lima_screen *screen = lima_screen(ctx->base.screen);
256
257 uint32_t reload_shader_first_instr_size =
258 ((uint32_t *)(screen->pp_buffer->map + pp_reload_program_offset))[0] & 0x1f;
259 uint32_t reload_shader_va = screen->pp_buffer->va + pp_reload_program_offset;
260
261 struct lima_render_state reload_render_state = {
262 .alpha_blend = 0xf03b1ad2,
263 .depth_test = 0x0000000e,
264 .depth_range = 0xffff0000,
265 .stencil_front = 0x00000007,
266 .stencil_back = 0x00000007,
267 .multi_sample = 0x0000f007,
268 .shader_address = reload_shader_va | reload_shader_first_instr_size,
269 .varying_types = 0x00000001,
270 .textures_address = va + lima_reload_tex_array_offset,
271 .aux0 = 0x00004021,
272 .varyings_address = va + lima_reload_varying_offset,
273 };
274 memcpy(cpu + lima_reload_render_state_offset, &reload_render_state,
275 sizeof(reload_render_state));
276
277 struct lima_context_framebuffer *fb = &ctx->framebuffer;
278 lima_tex_desc *td = cpu + lima_reload_tex_desc_offset;
279 memset(td, 0, lima_min_tex_desc_size);
280 lima_texture_desc_set_res(ctx, td, fb->base.cbufs[0]->texture, 0, 0);
281 td->unknown_1_1 = 0x80;
282 td->texture_2d = 1;
283 td->min_img_filter_nearest = 1;
284 td->mag_img_filter_nearest = 1;
285 td->wrap_s_clamp_to_edge = 1;
286 td->wrap_t_clamp_to_edge = 1;
287 td->unknown_2_2 = 0x1;
288
289 uint32_t *ta = cpu + lima_reload_tex_array_offset;
290 ta[0] = va + lima_reload_tex_desc_offset;
291
292 float reload_gl_pos[] = {
293 fb->base.width, 0, 0, 1,
294 0, 0, 0, 1,
295 0, fb->base.height, 0, 1,
296 };
297 memcpy(cpu + lima_reload_gl_pos_offset, reload_gl_pos,
298 sizeof(reload_gl_pos));
299
300 float reload_varying[] = {
301 fb->base.width, 0, 0, 0,
302 0, fb->base.height, 0, 0,
303 };
304 memcpy(cpu + lima_reload_varying_offset, reload_varying,
305 sizeof(reload_varying));
306
307 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
308 pipe_resource_reference(&pres, NULL);
309
310 PLBU_CMD_BEGIN(20);
311
312 PLBU_CMD_VIEWPORT_X(0);
313 PLBU_CMD_VIEWPORT_W(fui(fb->base.width));
314 PLBU_CMD_VIEWPORT_Y(0);
315 PLBU_CMD_VIEWPORT_H(fui(fb->base.height));
316
317 PLBU_CMD_RSW_VERTEX_ARRAY(
318 va + lima_reload_render_state_offset,
319 va + lima_reload_gl_pos_offset);
320
321 PLBU_CMD_UNKNOWN2();
322 PLBU_CMD_UNKNOWN1();
323
324 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
325 PLBU_CMD_INDEXED_DEST(va + lima_reload_gl_pos_offset);
326 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
327
328 PLBU_CMD_END();
329 }
330
331 static void
332 lima_pack_clear_plbu_cmd(struct lima_context *ctx)
333 {
334 #define lima_clear_render_state_offset 0x0000
335 #define lima_clear_shader_offset 0x0040
336 #define lima_clear_buffer_size 0x0080
337
338 void *cpu;
339 unsigned offset;
340 struct pipe_resource *pres = NULL;
341 u_upload_alloc(ctx->uploader, 0, lima_clear_buffer_size,
342 0x40, &offset, &pres, &cpu);
343
344 struct lima_resource *res = lima_resource(pres);
345 uint32_t va = res->bo->va + offset;
346
347 struct lima_screen *screen = lima_screen(ctx->base.screen);
348 uint32_t gl_pos_va = screen->pp_buffer->va + pp_clear_gl_pos_offset;
349
350 /* const0 clear_color, mov.v1 $0 ^const0.xxxx, stop */
351 uint32_t clear_shader[] = {
352 0x00021025, 0x0000000c,
353 (ctx->clear.color_16pc << 12) | 0x000007cf,
354 ctx->clear.color_16pc >> 12,
355 ctx->clear.color_16pc >> 44,
356 };
357 memcpy(cpu + lima_clear_shader_offset, &clear_shader,
358 sizeof(clear_shader));
359
360 uint32_t clear_shader_va = va + lima_clear_shader_offset;
361 uint32_t clear_shader_first_instr_size = clear_shader[0] & 0x1f;
362
363 struct lima_render_state clear_render_state = {
364 .blend_color_bg = 0x00800080,
365 .blend_color_ra = 0x00ff0080,
366 .alpha_blend = 0xfc321892,
367 .depth_test = 0x0000003e,
368 .depth_range = 0xffff0000,
369 .stencil_front = 0x00000007,
370 .stencil_back = 0x00000007,
371 .multi_sample = 0x0000f007,
372 .shader_address = clear_shader_va | clear_shader_first_instr_size,
373 };
374 memcpy(cpu + lima_clear_render_state_offset, &clear_render_state,
375 sizeof(clear_render_state));
376
377 PLBU_CMD_BEGIN(22);
378
379 PLBU_CMD_VIEWPORT_X(0);
380 PLBU_CMD_VIEWPORT_W(0x45800000);
381 PLBU_CMD_VIEWPORT_Y(0);
382 PLBU_CMD_VIEWPORT_H(0x45800000);
383
384 struct pipe_scissor_state *scissor = &ctx->scissor;
385 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
386
387 PLBU_CMD_RSW_VERTEX_ARRAY(va + lima_clear_render_state_offset, gl_pos_va);
388
389 PLBU_CMD_UNKNOWN2();
390 PLBU_CMD_UNKNOWN1();
391
392 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
393 PLBU_CMD_INDEXED_DEST(gl_pos_va);
394 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
395
396 PLBU_CMD_END();
397 }
398
399 static void
400 lima_pack_head_plbu_cmd(struct lima_context *ctx)
401 {
402 /* first draw need create a PLBU command header */
403 if (lima_ctx_dirty(ctx))
404 return;
405
406 struct lima_context_framebuffer *fb = &ctx->framebuffer;
407
408 PLBU_CMD_BEGIN(10);
409
410 PLBU_CMD_UNKNOWN2();
411 PLBU_CMD_BLOCK_STEP(fb->shift_min, fb->shift_h, fb->shift_w);
412 PLBU_CMD_TILED_DIMENSIONS(fb->tiled_w, fb->tiled_h);
413 PLBU_CMD_BLOCK_STRIDE(fb->block_w);
414
415 PLBU_CMD_ARRAY_ADDRESS(
416 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size,
417 fb->block_w * fb->block_h);
418
419 PLBU_CMD_END();
420
421 if (lima_fb_need_reload(ctx))
422 lima_pack_reload_plbu_cmd(ctx);
423 }
424
425 static bool
426 lima_is_scissor_zero(struct lima_context *ctx)
427 {
428 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
429 return false;
430
431 struct pipe_scissor_state *scissor = &ctx->scissor;
432 return
433 scissor->minx == scissor->maxx
434 && scissor->miny == scissor->maxy;
435 }
436
437 static bool
438 lima_is_scissor_full_fb(struct lima_context *ctx)
439 {
440 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
441 return true;
442
443 struct pipe_scissor_state *scissor = &ctx->scissor;
444 struct lima_context_framebuffer *fb = &ctx->framebuffer;
445 return
446 scissor->minx == 0 && scissor->maxx == fb->base.width &&
447 scissor->miny == 0 && scissor->maxy == fb->base.height;
448 }
449
450 static void
451 hilbert_rotate(int n, int *x, int *y, int rx, int ry)
452 {
453 if (ry == 0) {
454 if (rx == 1) {
455 *x = n-1 - *x;
456 *y = n-1 - *y;
457 }
458
459 /* Swap x and y */
460 int t = *x;
461 *x = *y;
462 *y = t;
463 }
464 }
465
466 static void
467 hilbert_coords(int n, int d, int *x, int *y)
468 {
469 int rx, ry, i, t=d;
470
471 *x = *y = 0;
472
473 for (i = 0; (1 << i) < n; i++) {
474
475 rx = 1 & (t / 2);
476 ry = 1 & (t ^ rx);
477
478 hilbert_rotate(1 << i, x, y, rx, ry);
479
480 *x += rx << i;
481 *y += ry << i;
482
483 t /= 4;
484 }
485 }
486
487 static int
488 lima_get_pp_stream_size(int num_pp, int tiled_w, int tiled_h, uint32_t *off)
489 {
490 /* carefully calculate each stream start address:
491 * 1. overflow: each stream size may be different due to
492 * fb->tiled_w * fb->tiled_h can't be divided by num_pp,
493 * extra size should be added to the preceeding stream
494 * 2. alignment: each stream address should be 0x20 aligned
495 */
496 int delta = tiled_w * tiled_h / num_pp * 16 + 8;
497 int remain = tiled_w * tiled_h % num_pp;
498 int offset = 0;
499
500 for (int i = 0; i < num_pp; i++) {
501 off[i] = offset;
502
503 offset += delta;
504 if (remain) {
505 offset += 16;
506 remain--;
507 }
508 offset = align(offset, 0x20);
509 }
510
511 return offset;
512 }
513
514 static bool
515 inside_damage_region(int x, int y, struct lima_damage_state *ds)
516 {
517 if (!ds->region)
518 return true;
519
520 for (int i = 0; i < ds->num_region; i++) {
521 struct pipe_scissor_state *ss = ds->region + i;
522 if (x >= ss->minx && x < ss->maxx &&
523 y >= ss->miny && y < ss->maxy)
524 return true;
525 }
526
527 return false;
528 }
529
530 static void
531 lima_update_pp_stream(struct lima_context *ctx, int off_x, int off_y,
532 int tiled_w, int tiled_h)
533 {
534 struct lima_pp_stream_state *ps = &ctx->pp_stream;
535 struct lima_context_framebuffer *fb = &ctx->framebuffer;
536 struct lima_screen *screen = lima_screen(ctx->base.screen);
537 int i, num_pp = screen->num_pp;
538
539 /* use hilbert_coords to generates 1D to 2D relationship.
540 * 1D for pp stream index and 2D for plb block x/y on framebuffer.
541 * if multi pp, interleave the 1D index to make each pp's render target
542 * close enough which should result close workload
543 */
544 int max = MAX2(tiled_w, tiled_h);
545 int dim = util_logbase2_ceil(max);
546 int count = 1 << (dim + dim);
547 int index = 0;
548 uint32_t *stream[4];
549 int si[4] = {0};
550
551 for (i = 0; i < num_pp; i++)
552 stream[i] = ps->bo->map + ps->bo_offset + ps->offset[i];
553
554 for (i = 0; i < count; i++) {
555 int x, y;
556 hilbert_coords(max, i, &x, &y);
557 if (x < tiled_w && y < tiled_h) {
558 x += off_x;
559 y += off_y;
560
561 if (!inside_damage_region(x, y, &ctx->damage))
562 continue;
563
564 int pp = index % num_pp;
565 int offset = ((y >> fb->shift_h) * fb->block_w +
566 (x >> fb->shift_w)) * LIMA_CTX_PLB_BLK_SIZE;
567 int plb_va = ctx->plb[ctx->plb_index]->va + offset;
568
569 stream[pp][si[pp]++] = 0;
570 stream[pp][si[pp]++] = 0xB8000000 | x | (y << 8);
571 stream[pp][si[pp]++] = 0xE0000002 | ((plb_va >> 3) & ~0xE0000003);
572 stream[pp][si[pp]++] = 0xB0000000;
573
574 index++;
575 }
576 }
577
578 for (i = 0; i < num_pp; i++) {
579 stream[i][si[i]++] = 0;
580 stream[i][si[i]++] = 0xBC000000;
581
582 lima_dump_command_stream_print(
583 stream[i], si[i] * 4, false, "pp plb stream %d at va %x\n",
584 i, ps->bo->va + ps->bo_offset + ps->offset[i]);
585 }
586 }
587
588 static void
589 lima_update_damage_pp_stream(struct lima_context *ctx)
590 {
591 struct lima_damage_state *ds = &ctx->damage;
592 struct pipe_scissor_state max = ds->region[0];
593
594 /* find a max region to cover all the damage region */
595 for (int i = 1; i < ds->num_region; i++) {
596 struct pipe_scissor_state *ss = ds->region + i;
597 max.minx = MIN2(max.minx, ss->minx);
598 max.miny = MIN2(max.miny, ss->miny);
599 max.maxx = MAX2(max.maxx, ss->maxx);
600 max.maxy = MAX2(max.maxy, ss->maxy);
601 }
602
603 int tiled_w = max.maxx - max.minx;
604 int tiled_h = max.maxy - max.miny;
605 struct lima_screen *screen = lima_screen(ctx->base.screen);
606 int size = lima_get_pp_stream_size(
607 screen->num_pp, tiled_w, tiled_h, ctx->pp_stream.offset);
608
609 void *cpu;
610 unsigned offset;
611 struct pipe_resource *pres = NULL;
612 u_upload_alloc(ctx->uploader, 0, size, 0x40, &offset, &pres, &cpu);
613
614 struct lima_resource *res = lima_resource(pres);
615 ctx->pp_stream.bo = res->bo;
616 ctx->pp_stream.bo_offset = offset;
617
618 lima_update_pp_stream(ctx, max.minx, max.miny, tiled_w, tiled_h);
619
620 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
621 pipe_resource_reference(&pres, NULL);
622 }
623
624 static void
625 lima_update_full_pp_stream(struct lima_context *ctx)
626 {
627 struct lima_context_framebuffer *fb = &ctx->framebuffer;
628 struct lima_ctx_plb_pp_stream_key key = {
629 .plb_index = ctx->plb_index,
630 .tiled_w = fb->tiled_w,
631 .tiled_h = fb->tiled_h,
632 };
633
634 struct hash_entry *entry =
635 _mesa_hash_table_search(ctx->plb_pp_stream, &key);
636 struct lima_ctx_plb_pp_stream *s = entry->data;
637
638 if (s->bo) {
639 ctx->pp_stream.bo = s->bo;
640 ctx->pp_stream.bo_offset = 0;
641 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
642 }
643 else {
644 struct lima_screen *screen = lima_screen(ctx->base.screen);
645 int size = lima_get_pp_stream_size(
646 screen->num_pp, fb->tiled_w, fb->tiled_h, s->offset);
647 s->bo = lima_bo_create(screen, size, 0);
648 lima_bo_map(s->bo);
649
650 ctx->pp_stream.bo = s->bo;
651 ctx->pp_stream.bo_offset = 0;
652 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
653
654 lima_update_pp_stream(ctx, 0, 0, fb->tiled_w, fb->tiled_h);
655 }
656
657 lima_submit_add_bo(ctx->pp_submit, s->bo, LIMA_SUBMIT_BO_READ);
658 }
659
660 static void
661 lima_update_submit_bo(struct lima_context *ctx)
662 {
663 if (lima_ctx_dirty(ctx))
664 return;
665
666 struct lima_screen *screen = lima_screen(ctx->base.screen);
667 lima_submit_add_bo(ctx->gp_submit, ctx->plb_gp_stream, LIMA_SUBMIT_BO_READ);
668 lima_submit_add_bo(ctx->gp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
669 lima_submit_add_bo(ctx->gp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
670
671 lima_dump_command_stream_print(
672 ctx->plb_gp_stream->map + ctx->plb_index * ctx->plb_gp_size,
673 ctx->plb_gp_size, false, "gp plb stream at va %x\n",
674 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size);
675
676 if (ctx->damage.region)
677 lima_update_damage_pp_stream(ctx);
678 else if (ctx->plb_pp_stream)
679 lima_update_full_pp_stream(ctx);
680 else
681 ctx->pp_stream.bo = NULL;
682
683 if (ctx->framebuffer.base.nr_cbufs) {
684 struct lima_resource *res = lima_resource(ctx->framebuffer.base.cbufs[0]->texture);
685 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
686 }
687 if (ctx->framebuffer.base.zsbuf) {
688 struct lima_resource *res = lima_resource(ctx->framebuffer.base.zsbuf->texture);
689 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
690 }
691 lima_submit_add_bo(ctx->pp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_READ);
692 lima_submit_add_bo(ctx->pp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_READ);
693 lima_submit_add_bo(ctx->pp_submit, screen->pp_buffer, LIMA_SUBMIT_BO_READ);
694 }
695
696 static void
697 lima_clear(struct pipe_context *pctx, unsigned buffers,
698 const union pipe_color_union *color, double depth, unsigned stencil)
699 {
700 struct lima_context *ctx = lima_context(pctx);
701 bool full_fb_clear = lima_is_scissor_full_fb(ctx);
702
703 if (full_fb_clear) {
704 lima_flush(ctx);
705
706 /* no need to reload if cleared */
707 if (ctx->framebuffer.base.nr_cbufs && (buffers & PIPE_CLEAR_COLOR0)) {
708 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
709 surf->reload = false;
710 }
711 }
712
713 struct lima_context_clear *clear = &ctx->clear;
714 clear->buffers = buffers;
715
716 if (buffers & PIPE_CLEAR_COLOR0) {
717 clear->color_8pc =
718 ((uint32_t)float_to_ubyte(color->f[3]) << 24) |
719 ((uint32_t)float_to_ubyte(color->f[2]) << 16) |
720 ((uint32_t)float_to_ubyte(color->f[1]) << 8) |
721 float_to_ubyte(color->f[0]);
722
723 clear->color_16pc =
724 ((uint64_t)float_to_ushort(color->f[3]) << 48) |
725 ((uint64_t)float_to_ushort(color->f[2]) << 32) |
726 ((uint64_t)float_to_ushort(color->f[1]) << 16) |
727 float_to_ushort(color->f[0]);
728 }
729
730 if (buffers & PIPE_CLEAR_DEPTH)
731 clear->depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
732
733 if (buffers & PIPE_CLEAR_STENCIL)
734 clear->stencil = stencil;
735
736 lima_update_submit_bo(ctx);
737
738 lima_pack_head_plbu_cmd(ctx);
739
740 /* partial clear */
741 if (!full_fb_clear)
742 lima_pack_clear_plbu_cmd(ctx);
743
744 ctx->dirty |= LIMA_CONTEXT_DIRTY_CLEAR;
745 }
746
747 enum lima_attrib_type {
748 LIMA_ATTRIB_FLOAT = 0x000,
749 /* todo: find out what lives here. */
750 LIMA_ATTRIB_I16 = 0x004,
751 LIMA_ATTRIB_U16 = 0x005,
752 LIMA_ATTRIB_I8 = 0x006,
753 LIMA_ATTRIB_U8 = 0x007,
754 LIMA_ATTRIB_I8N = 0x008,
755 LIMA_ATTRIB_U8N = 0x009,
756 LIMA_ATTRIB_I16N = 0x00A,
757 LIMA_ATTRIB_U16N = 0x00B,
758 /* todo: where is the 32 int */
759 /* todo: find out what lives here. */
760 LIMA_ATTRIB_FIXED = 0x101
761 };
762
763 static enum lima_attrib_type
764 lima_pipe_format_to_attrib_type(enum pipe_format format)
765 {
766 const struct util_format_description *desc = util_format_description(format);
767 int i = util_format_get_first_non_void_channel(format);
768 const struct util_format_channel_description *c = desc->channel + i;
769
770 switch (c->type) {
771 case UTIL_FORMAT_TYPE_FLOAT:
772 return LIMA_ATTRIB_FLOAT;
773 case UTIL_FORMAT_TYPE_FIXED:
774 return LIMA_ATTRIB_FIXED;
775 case UTIL_FORMAT_TYPE_SIGNED:
776 if (c->size == 8) {
777 if (c->normalized)
778 return LIMA_ATTRIB_I8N;
779 else
780 return LIMA_ATTRIB_I8;
781 }
782 else if (c->size == 16) {
783 if (c->normalized)
784 return LIMA_ATTRIB_I16N;
785 else
786 return LIMA_ATTRIB_I16;
787 }
788 break;
789 case UTIL_FORMAT_TYPE_UNSIGNED:
790 if (c->size == 8) {
791 if (c->normalized)
792 return LIMA_ATTRIB_U8N;
793 else
794 return LIMA_ATTRIB_U8;
795 }
796 else if (c->size == 16) {
797 if (c->normalized)
798 return LIMA_ATTRIB_U16N;
799 else
800 return LIMA_ATTRIB_U16;
801 }
802 break;
803 }
804
805 return LIMA_ATTRIB_FLOAT;
806 }
807
808 static void
809 lima_pack_vs_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
810 {
811 VS_CMD_BEGIN(24);
812
813 if (!info->index_size) {
814 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1();
815 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2();
816 }
817
818 int uniform_size = ctx->vs->uniform_pending_offset + ctx->vs->constant_size + 32;
819 VS_CMD_UNIFORMS_ADDRESS(
820 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, LIMA_CTX_BUFF_SUBMIT_GP),
821 align(uniform_size, 16));
822
823 VS_CMD_SHADER_ADDRESS(ctx->vs->bo->va, ctx->vs->shader_size);
824 VS_CMD_SHADER_INFO(ctx->vs->prefetch, ctx->vs->shader_size);
825
826 int num_varryings = ctx->vs->num_varying;
827 int num_attributes = ctx->vertex_elements->num_elements;
828 VS_CMD_VARYING_ATTRIBUTE_COUNT(num_varryings, num_attributes);
829
830 VS_CMD_UNKNOWN1();
831
832 VS_CMD_ATTRIBUTES_ADDRESS(
833 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, LIMA_CTX_BUFF_SUBMIT_GP),
834 num_attributes);
835
836 VS_CMD_VARYINGS_ADDRESS(
837 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, LIMA_CTX_BUFF_SUBMIT_GP),
838 num_varryings);
839
840 unsigned num = info->index_size ? (ctx->max_index - ctx->min_index + 1) : info->count;
841 VS_CMD_DRAW(num, info->index_size);
842
843 VS_CMD_UNKNOWN2();
844
845 VS_CMD_ARRAYS_SEMAPHORE_END(info->index_size);
846
847 VS_CMD_END();
848 }
849
850 static void
851 lima_pack_plbu_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
852 {
853 lima_pack_head_plbu_cmd(ctx);
854
855 /* If it's zero scissor, we skip adding all other commands */
856 if (lima_is_scissor_zero(ctx))
857 return;
858
859 PLBU_CMD_BEGIN(30);
860
861 PLBU_CMD_VIEWPORT_X(fui(ctx->viewport.x));
862 PLBU_CMD_VIEWPORT_W(fui(ctx->viewport.width));
863 PLBU_CMD_VIEWPORT_Y(fui(ctx->viewport.y));
864 PLBU_CMD_VIEWPORT_H(fui(ctx->viewport.height));
865
866 if (!info->index_size)
867 PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN();
868
869 bool low_prim = info->mode < PIPE_PRIM_TRIANGLES;
870 int cf = ctx->rasterizer->base.cull_face;
871 int ccw = ctx->rasterizer->base.front_ccw;
872 uint32_t cull = 0;
873 if (cf != PIPE_FACE_NONE) {
874 if (cf & PIPE_FACE_FRONT)
875 cull |= ccw ? 0x00040000 : 0x00020000;
876 if (cf & PIPE_FACE_BACK)
877 cull |= ccw ? 0x00020000 : 0x00040000;
878 }
879 PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, info->index_size);
880
881 uint32_t gl_position_va =
882 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
883 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
884 PLBU_CMD_RSW_VERTEX_ARRAY(
885 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, LIMA_CTX_BUFF_SUBMIT_PP),
886 gl_position_va);
887
888 /* TODO
889 * - we should set it only for the first draw that enabled the scissor and for
890 * latter draw only if scissor is dirty
891 */
892 if (ctx->rasterizer->base.scissor) {
893 struct pipe_scissor_state *scissor = &ctx->scissor;
894 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
895 }
896
897 PLBU_CMD_UNKNOWN1();
898
899 PLBU_CMD_DEPTH_RANGE_NEAR(fui(ctx->viewport.near));
900 PLBU_CMD_DEPTH_RANGE_FAR(fui(ctx->viewport.far));
901
902 if (low_prim) {
903 uint32_t v = info->mode == PIPE_PRIM_POINTS ?
904 fui(ctx->rasterizer->base.point_size) : fui(ctx->rasterizer->base.line_width);
905 PLBU_CMD_LOW_PRIM_SIZE(v);
906 }
907
908 if (info->index_size) {
909 PLBU_CMD_INDEXED_DEST(gl_position_va);
910
911 struct pipe_resource *indexbuf = NULL;
912 unsigned index_offset = 0;
913 struct lima_resource *res;
914 if (info->has_user_indices) {
915 util_upload_index_buffer(&ctx->base, info, &indexbuf, &index_offset);
916 res = lima_resource(indexbuf);
917 }
918 else
919 res = lima_resource(info->index.resource);
920
921 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
922 PLBU_CMD_INDICES(res->bo->va + info->start * info->index_size + index_offset);
923
924 if (indexbuf)
925 pipe_resource_reference(&indexbuf, NULL);
926 }
927 else {
928 /* can this make the attribute info static? */
929 PLBU_CMD_DRAW_ARRAYS(info->mode, info->start, info->count);
930 }
931
932 PLBU_CMD_ARRAYS_SEMAPHORE_END();
933
934 if (info->index_size)
935 PLBU_CMD_DRAW_ELEMENTS(info->mode, ctx->min_index, info->count);
936
937 PLBU_CMD_END();
938 }
939
940 static int
941 lima_blend_func(enum pipe_blend_func pipe)
942 {
943 switch (pipe) {
944 case PIPE_BLEND_ADD:
945 return 2;
946 case PIPE_BLEND_SUBTRACT:
947 return 0;
948 case PIPE_BLEND_REVERSE_SUBTRACT:
949 return 1;
950 case PIPE_BLEND_MIN:
951 return 4;
952 case PIPE_BLEND_MAX:
953 return 5;
954 }
955 return -1;
956 }
957
958 static int
959 lima_blend_factor(enum pipe_blendfactor pipe)
960 {
961 switch (pipe) {
962 case PIPE_BLENDFACTOR_ONE:
963 return 11;
964 case PIPE_BLENDFACTOR_SRC_COLOR:
965 return 0;
966 case PIPE_BLENDFACTOR_SRC_ALPHA:
967 return 16;
968 case PIPE_BLENDFACTOR_DST_ALPHA:
969 return 17;
970 case PIPE_BLENDFACTOR_DST_COLOR:
971 return 1;
972 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
973 return 7;
974 case PIPE_BLENDFACTOR_CONST_COLOR:
975 return 2;
976 case PIPE_BLENDFACTOR_CONST_ALPHA:
977 return 18;
978 case PIPE_BLENDFACTOR_ZERO:
979 return 3;
980 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
981 return 8;
982 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
983 return 24;
984 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
985 return 25;
986 case PIPE_BLENDFACTOR_INV_DST_COLOR:
987 return 9;
988 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
989 return 10;
990 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
991 return 26;
992 case PIPE_BLENDFACTOR_SRC1_COLOR:
993 case PIPE_BLENDFACTOR_SRC1_ALPHA:
994 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
995 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
996 return -1; /* not support */
997 }
998 return -1;
999 }
1000
1001 static int
1002 lima_calculate_alpha_blend(enum pipe_blend_func rgb_func, enum pipe_blend_func alpha_func,
1003 enum pipe_blendfactor rgb_src_factor, enum pipe_blendfactor rgb_dst_factor,
1004 enum pipe_blendfactor alpha_src_factor, enum pipe_blendfactor alpha_dst_factor)
1005 {
1006 return lima_blend_func(rgb_func) |
1007 (lima_blend_func(alpha_func) << 3) |
1008 (lima_blend_factor(rgb_src_factor) << 6) |
1009 (lima_blend_factor(rgb_dst_factor) << 11) |
1010 ((lima_blend_factor(alpha_src_factor) & 0xF) << 16) |
1011 ((lima_blend_factor(alpha_dst_factor) & 0xF) << 20) |
1012 0x0C000000; /* need check if this GLESv1 glAlphaFunc */
1013 }
1014
1015 #if 0
1016 static int
1017 lima_stencil_op(enum pipe_stencil_op pipe)
1018 {
1019 switch (pipe) {
1020 case PIPE_STENCIL_OP_KEEP:
1021 return 0;
1022 case PIPE_STENCIL_OP_ZERO:
1023 return 2;
1024 case PIPE_STENCIL_OP_REPLACE:
1025 return 1;
1026 case PIPE_STENCIL_OP_INCR:
1027 return 6;
1028 case PIPE_STENCIL_OP_DECR:
1029 return 7;
1030 case PIPE_STENCIL_OP_INCR_WRAP:
1031 return 4;
1032 case PIPE_STENCIL_OP_DECR_WRAP:
1033 return 5;
1034 case PIPE_STENCIL_OP_INVERT:
1035 return 3;
1036 }
1037 return -1;
1038 }
1039 #endif
1040
1041 static int
1042 lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer_state *rst)
1043 {
1044 enum pipe_compare_func func = (depth->enabled ? depth->func : PIPE_FUNC_ALWAYS);
1045
1046 int offset_scale = 0;
1047
1048 //TODO: implement polygon offset
1049 #if 0
1050 if (rst->offset_scale < -32)
1051 offset_scale = -32;
1052 else if (rst->offset_scale > 31)
1053 offset_scale = 31;
1054 else
1055 offset_scale = rst->offset_scale * 4;
1056
1057 if (offset_scale < 0)
1058 offset_scale = 0x100 + offset_scale;
1059 #endif
1060
1061 return (depth->enabled && depth->writemask) |
1062 ((int)func << 1) |
1063 (offset_scale << 16) |
1064 0x30; /* find out what is this */
1065 }
1066
1067 static void
1068 lima_pack_render_state(struct lima_context *ctx, const struct pipe_draw_info *info)
1069 {
1070 struct lima_render_state *render =
1071 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_plb_rsw,
1072 sizeof(*render), true);
1073
1074 /* do hw support RGBA independ blend?
1075 * PIPE_CAP_INDEP_BLEND_ENABLE
1076 *
1077 * how to handle the no cbuf only zbuf case?
1078 */
1079 struct pipe_rt_blend_state *rt = ctx->blend->base.rt;
1080 render->blend_color_bg = float_to_ubyte(ctx->blend_color.color[2]) |
1081 (float_to_ubyte(ctx->blend_color.color[1]) << 16);
1082 render->blend_color_ra = float_to_ubyte(ctx->blend_color.color[0]) |
1083 (float_to_ubyte(ctx->blend_color.color[3]) << 16);
1084
1085 if (rt->blend_enable) {
1086 render->alpha_blend = lima_calculate_alpha_blend(rt->rgb_func, rt->alpha_func,
1087 rt->rgb_src_factor, rt->rgb_dst_factor,
1088 rt->alpha_src_factor, rt->alpha_dst_factor);
1089 }
1090 else {
1091 /*
1092 * Special handling for blending disabled.
1093 * Binary driver is generating the same alpha_value,
1094 * as when we would just enable blending, without changing/setting any blend equation/params.
1095 * Normaly in this case mesa would set all rt fields (func/factor) to zero.
1096 */
1097 render->alpha_blend = lima_calculate_alpha_blend(PIPE_BLEND_ADD, PIPE_BLEND_ADD,
1098 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO,
1099 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO);
1100 }
1101
1102 render->alpha_blend |= (rt->colormask & PIPE_MASK_RGBA) << 28;
1103
1104 struct pipe_rasterizer_state *rst = &ctx->rasterizer->base;
1105 struct pipe_depth_state *depth = &ctx->zsa->base.depth;
1106 render->depth_test = lima_calculate_depth_test(depth, rst);
1107
1108 /* overlap with plbu? any place can remove one? */
1109 render->depth_range = float_to_ushort(ctx->viewport.near) |
1110 (float_to_ushort(ctx->viewport.far) << 16);
1111
1112 #if 0
1113 struct pipe_stencil_state *stencil = ctx->zsa->base.stencil;
1114 struct pipe_stencil_ref *ref = &ctx->stencil_ref;
1115 render->stencil_front = stencil[0].func |
1116 (lima_stencil_op(stencil[0].fail_op) << 3) |
1117 (lima_stencil_op(stencil[0].zfail_op) << 6) |
1118 (lima_stencil_op(stencil[0].zpass_op) << 9) |
1119 (ref->ref_value[0] << 16) |
1120 (stencil[0].valuemask << 24);
1121 render->stencil_back = stencil[1].func |
1122 (lima_stencil_op(stencil[1].fail_op) << 3) |
1123 (lima_stencil_op(stencil[1].zfail_op) << 6) |
1124 (lima_stencil_op(stencil[1].zpass_op) << 9) |
1125 (ref->ref_value[1] << 16) |
1126 (stencil[1].valuemask << 24);
1127 #else
1128 render->stencil_front = 0xff000007;
1129 render->stencil_back = 0xff000007;
1130 #endif
1131
1132 /* seems not correct? */
1133 //struct pipe_alpha_state *alpha = &ctx->zsa->base.alpha;
1134 render->stencil_test = 0;
1135 //(stencil->enabled ? 0xFF : 0x00) | (float_to_ubyte(alpha->ref_value) << 16)
1136
1137 /* need more investigation */
1138 if (info->mode == PIPE_PRIM_POINTS)
1139 render->multi_sample = 0x0000F007;
1140 else if (info->mode < PIPE_PRIM_TRIANGLES)
1141 render->multi_sample = 0x0000F407;
1142 else
1143 render->multi_sample = 0x0000F807;
1144 if (ctx->framebuffer.base.samples)
1145 render->multi_sample |= 0x68;
1146
1147 render->shader_address =
1148 ctx->fs->bo->va | (((uint32_t *)ctx->fs->bo->map)[0] & 0x1F);
1149
1150 /* seems not needed */
1151 render->uniforms_address = 0x00000000;
1152
1153 render->textures_address = 0x00000000;
1154
1155 /* more investigation */
1156 render->aux0 = 0x00000300 | (ctx->vs->varying_stride >> 3);
1157 render->aux1 = 0x00003000;
1158
1159 if (ctx->tex_stateobj.num_samplers) {
1160 render->textures_address =
1161 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_tex_desc, LIMA_CTX_BUFF_SUBMIT_PP);
1162 render->aux0 |= ctx->tex_stateobj.num_samplers << 14;
1163 render->aux0 |= 0x20;
1164 }
1165
1166 if (ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer) {
1167 render->uniforms_address =
1168 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, LIMA_CTX_BUFF_SUBMIT_PP);
1169 render->uniforms_address |= ((ctx->buffer_state[lima_ctx_buff_pp_uniform].size) / 4 - 1);
1170 render->aux0 |= 0x80;
1171 render->aux1 |= 0x10000;
1172 }
1173
1174 if (ctx->vs->num_varying > 1) {
1175 render->varying_types = 0x00000000;
1176 render->varyings_address =
1177 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_PP);
1178 for (int i = 1; i < ctx->vs->num_varying; i++) {
1179 int val;
1180
1181 struct lima_varying_info *v = ctx->vs->varying + i;
1182 if (v->component_size == 4)
1183 val = v->components > 2 ? 0 : 1;
1184 else
1185 val = v->components > 2 ? 2 : 3;
1186
1187 int index = i - 1;
1188 if (index < 10)
1189 render->varying_types |= val << (3 * index);
1190 else if (index == 10) {
1191 render->varying_types |= val << 30;
1192 render->varyings_address |= val >> 2;
1193 }
1194 else if (index == 11)
1195 render->varyings_address |= val << 1;
1196 }
1197 }
1198 else {
1199 render->varying_types = 0x00000000;
1200 render->varyings_address = 0x00000000;
1201 }
1202
1203 lima_dump_command_stream_print(
1204 render, sizeof(*render), false, "add render state at va %x\n",
1205 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, 0));
1206 }
1207
1208 static void
1209 lima_update_gp_attribute_info(struct lima_context *ctx, const struct pipe_draw_info *info)
1210 {
1211 struct lima_vertex_element_state *ve = ctx->vertex_elements;
1212 struct lima_context_vertex_buffer *vb = &ctx->vertex_buffers;
1213
1214 uint32_t *attribute =
1215 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_attribute_info,
1216 ve->num_elements * 8, true);
1217
1218 int n = 0;
1219 for (int i = 0; i < ve->num_elements; i++) {
1220 struct pipe_vertex_element *pve = ve->pipe + i;
1221
1222 assert(pve->vertex_buffer_index < vb->count);
1223 assert(vb->enabled_mask & (1 << pve->vertex_buffer_index));
1224
1225 struct pipe_vertex_buffer *pvb = vb->vb + pve->vertex_buffer_index;
1226 struct lima_resource *res = lima_resource(pvb->buffer.resource);
1227
1228 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
1229
1230 unsigned start = info->index_size ? ctx->min_index : info->start;
1231 attribute[n++] = res->bo->va + pvb->buffer_offset + pve->src_offset
1232 + start * pvb->stride;
1233 attribute[n++] = (pvb->stride << 11) |
1234 (lima_pipe_format_to_attrib_type(pve->src_format) << 2) |
1235 (util_format_get_nr_components(pve->src_format) - 1);
1236 }
1237
1238 lima_dump_command_stream_print(
1239 attribute, n * 4, false, "update attribute info at va %x\n",
1240 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, 0));
1241 }
1242
1243 static void
1244 lima_update_gp_uniform(struct lima_context *ctx)
1245 {
1246 struct lima_context_constant_buffer *ccb =
1247 ctx->const_buffer + PIPE_SHADER_VERTEX;
1248 struct lima_vs_shader_state *vs = ctx->vs;
1249
1250 int size = vs->uniform_pending_offset + vs->constant_size + 32;
1251 void *vs_const_buff =
1252 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_uniform, size, true);
1253
1254 if (ccb->buffer)
1255 memcpy(vs_const_buff, ccb->buffer, ccb->size);
1256
1257 memcpy(vs_const_buff + vs->uniform_pending_offset,
1258 ctx->viewport.transform.scale,
1259 sizeof(ctx->viewport.transform.scale));
1260 memcpy(vs_const_buff + vs->uniform_pending_offset + 16,
1261 ctx->viewport.transform.translate,
1262 sizeof(ctx->viewport.transform.translate));
1263
1264 if (vs->constant)
1265 memcpy(vs_const_buff + vs->uniform_pending_offset + 32,
1266 vs->constant, vs->constant_size);
1267
1268 lima_dump_command_stream_print(
1269 vs_const_buff, size, true,
1270 "update gp uniform at va %x\n",
1271 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, 0));
1272 }
1273
1274 static void
1275 lima_update_pp_uniform(struct lima_context *ctx)
1276 {
1277 const float *const_buff = ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer;
1278 size_t const_buff_size = ctx->const_buffer[PIPE_SHADER_FRAGMENT].size / sizeof(float);
1279
1280 if (!const_buff)
1281 return;
1282
1283 uint16_t *fp16_const_buff =
1284 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform,
1285 const_buff_size * sizeof(uint16_t), true);
1286
1287 uint32_t *array =
1288 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform_array, 4, true);
1289
1290 for (int i = 0; i < const_buff_size; i++)
1291 fp16_const_buff[i] = util_float_to_half(const_buff[i]);
1292
1293 *array = lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, LIMA_CTX_BUFF_SUBMIT_PP);
1294
1295 lima_dump_command_stream_print(
1296 fp16_const_buff, const_buff_size * 2, false, "add pp uniform data at va %x\n",
1297 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, 0));
1298 lima_dump_command_stream_print(
1299 array, 4, false, "add pp uniform info at va %x\n",
1300 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, 0));
1301 }
1302
1303 static void
1304 lima_update_varying(struct lima_context *ctx, const struct pipe_draw_info *info)
1305 {
1306 struct lima_vs_shader_state *vs = ctx->vs;
1307
1308 uint32_t *varying =
1309 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_varying_info,
1310 vs->num_varying * 8, true);
1311 int n = 0;
1312
1313 /* should be LIMA_SUBMIT_BO_WRITE for GP, but each draw will use
1314 * different part of this bo, so no need to set exclusive constraint */
1315 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_gl_pos,
1316 4 * 4 * info->count, false);
1317
1318 /* for gl_Position */
1319 varying[n++] =
1320 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
1321 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
1322 varying[n++] = 0x8020;
1323
1324 int offset = 0;
1325 for (int i = 1; i < vs->num_varying; i++) {
1326 struct lima_varying_info *v = vs->varying + i;
1327 int size = v->component_size * 4;
1328
1329 /* does component_size == 2 need to be 16 aligned? */
1330 if (v->component_size == 4)
1331 offset = align(offset, 16);
1332
1333 v->offset = offset;
1334 offset += size;
1335 }
1336 vs->varying_stride = align(offset, 16);
1337
1338 if (vs->num_varying > 1)
1339 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_varying,
1340 vs->varying_stride * info->count, false);
1341
1342 for (int i = 1; i < vs->num_varying; i++) {
1343 struct lima_varying_info *v = vs->varying + i;
1344 varying[n++] =
1345 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_GP) +
1346 v->offset;
1347 varying[n++] = (vs->varying_stride << 11) | (v->components - 1) |
1348 (v->component_size == 2 ? 0x0C : 0);
1349 }
1350
1351 lima_dump_command_stream_print(
1352 varying, n * 4, false, "update varying info at va %x\n",
1353 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, 0));
1354 }
1355
1356 static void
1357 lima_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
1358 {
1359 /* check if draw mode and vertex/index count match,
1360 * otherwise gp will hang */
1361 if (!u_trim_pipe_prim(info->mode, (unsigned*)&info->count)) {
1362 debug_printf("draw mode and vertex/index count mismatch\n");
1363 return;
1364 }
1365
1366 struct lima_context *ctx = lima_context(pctx);
1367
1368 if (!ctx->vs || !ctx->fs) {
1369 debug_warn_once("no shader, skip draw\n");
1370 return;
1371 }
1372
1373 if (!lima_update_vs_state(ctx) || !lima_update_fs_state(ctx))
1374 return;
1375
1376 lima_dump_command_stream_print(
1377 ctx->vs->bo->map, ctx->vs->shader_size, false,
1378 "add vs at va %x\n", ctx->vs->bo->va);
1379
1380 lima_dump_command_stream_print(
1381 ctx->fs->bo->map, ctx->fs->shader_size, false,
1382 "add fs at va %x\n", ctx->fs->bo->va);
1383
1384 lima_submit_add_bo(ctx->gp_submit, ctx->vs->bo, LIMA_SUBMIT_BO_READ);
1385 lima_submit_add_bo(ctx->pp_submit, ctx->fs->bo, LIMA_SUBMIT_BO_READ);
1386
1387 lima_update_submit_bo(ctx);
1388
1389 /* Mali Utgard GPU always need min/max index info for index draw,
1390 * compute it if upper layer does not do for us */
1391 if (info->index_size && info->max_index == ~0u)
1392 u_vbuf_get_minmax_index(pctx, info, &ctx->min_index, &ctx->max_index);
1393 else {
1394 ctx->min_index = info->min_index;
1395 ctx->max_index = info->max_index;
1396 }
1397
1398 lima_update_gp_attribute_info(ctx, info);
1399
1400 if ((ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1401 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty) ||
1402 ctx->dirty & LIMA_CONTEXT_DIRTY_VIEWPORT ||
1403 ctx->dirty & LIMA_CONTEXT_DIRTY_SHADER_VERT) {
1404 lima_update_gp_uniform(ctx);
1405 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty = false;
1406 }
1407
1408 lima_update_varying(ctx, info);
1409
1410 /* If it's zero scissor, don't build vs cmd list */
1411 if (!lima_is_scissor_zero(ctx))
1412 lima_pack_vs_cmd(ctx, info);
1413
1414 if (ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1415 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty) {
1416 lima_update_pp_uniform(ctx);
1417 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty = false;
1418 }
1419
1420 if (ctx->dirty & LIMA_CONTEXT_DIRTY_TEXTURES)
1421 lima_update_textures(ctx);
1422
1423 lima_pack_render_state(ctx, info);
1424 lima_pack_plbu_cmd(ctx, info);
1425
1426 ctx->dirty = 0;
1427 }
1428
1429 static void
1430 lima_finish_plbu_cmd(struct lima_context *ctx)
1431 {
1432 int i = 0;
1433 uint32_t *plbu_cmd = util_dynarray_ensure_cap(&ctx->plbu_cmd_array, ctx->plbu_cmd_array.size + 2 * 4);
1434
1435 plbu_cmd[i++] = 0x00000000;
1436 plbu_cmd[i++] = 0x50000000; /* END */
1437
1438 ctx->plbu_cmd_array.size += i * 4;
1439 }
1440
1441 static void
1442 lima_pack_wb_zsbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1443 {
1444 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1445 struct lima_resource *res = lima_resource(fb->base.zsbuf->texture);
1446 int level = fb->base.zsbuf->u.tex.level;
1447
1448 uint32_t format;
1449
1450 switch (fb->base.zsbuf->format) {
1451 case PIPE_FORMAT_Z16_UNORM:
1452 format = LIMA_PIXEL_FORMAT_Z16;
1453 break;
1454 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1455 case PIPE_FORMAT_Z24X8_UNORM:
1456 default:
1457 /* Assume Z24S8 */
1458 format = LIMA_PIXEL_FORMAT_Z24S8;
1459 break;
1460 }
1461
1462 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1463 wb[wb_idx].type = 0x01; /* 1 for depth, stencil */
1464 wb[wb_idx].address = res->bo->va + res->levels[level].offset;
1465 wb[wb_idx].pixel_format = format;
1466 if (res->tiled) {
1467 wb[wb_idx].pixel_layout = 0x2;
1468 wb[wb_idx].pitch = fb->tiled_w;
1469 } else {
1470 wb[wb_idx].pixel_layout = 0x0;
1471 wb[wb_idx].pitch = res->levels[level].stride / 8;
1472 }
1473 wb[wb_idx].mrt_bits = 0;
1474 }
1475
1476 static void
1477 lima_pack_wb_cbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1478 {
1479 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1480 struct lima_resource *res = lima_resource(fb->base.cbufs[0]->texture);
1481 int level = fb->base.cbufs[0]->u.tex.level;
1482
1483 bool swap_channels = false;
1484 switch (fb->base.cbufs[0]->format) {
1485 case PIPE_FORMAT_R8G8B8A8_UNORM:
1486 case PIPE_FORMAT_R8G8B8X8_UNORM:
1487 swap_channels = true;
1488 break;
1489 default:
1490 break;
1491 }
1492
1493 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1494 wb[wb_idx].type = 0x02; /* 2 for color buffer */
1495 wb[wb_idx].address = res->bo->va + res->levels[level].offset;
1496 wb[wb_idx].pixel_format = LIMA_PIXEL_FORMAT_B8G8R8A8;
1497 if (res->tiled) {
1498 wb[wb_idx].pixel_layout = 0x2;
1499 wb[wb_idx].pitch = fb->tiled_w;
1500 } else {
1501 wb[wb_idx].pixel_layout = 0x0;
1502 wb[wb_idx].pitch = res->levels[level].stride / 8;
1503 }
1504 wb[wb_idx].mrt_bits = swap_channels ? 0x4 : 0x0;
1505 }
1506
1507
1508 static void
1509 lima_pack_pp_frame_reg(struct lima_context *ctx, uint32_t *frame_reg,
1510 uint32_t *wb_reg)
1511 {
1512 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1513 struct lima_pp_frame_reg *frame = (void *)frame_reg;
1514 struct lima_screen *screen = lima_screen(ctx->base.screen);
1515 int wb_idx = 0;
1516
1517 frame->render_address = screen->pp_buffer->va + pp_frame_rsw_offset;
1518 frame->flags = 0x02;
1519 frame->clear_value_depth = ctx->clear.depth;
1520 frame->clear_value_stencil = ctx->clear.stencil;
1521 frame->clear_value_color = ctx->clear.color_8pc;
1522 frame->clear_value_color_1 = ctx->clear.color_8pc;
1523 frame->clear_value_color_2 = ctx->clear.color_8pc;
1524 frame->clear_value_color_3 = ctx->clear.color_8pc;
1525 frame->one = 1;
1526
1527 frame->width = fb->base.width - 1;
1528 frame->height = fb->base.height - 1;
1529
1530 /* frame->fragment_stack_address is overwritten per-pp in the kernel
1531 * by the values of pp_frame.fragment_stack_address[i] */
1532
1533 /* These are "stack size" and "stack offset" shifted,
1534 * here they are assumed to be always the same. */
1535 uint32_t fs_stack_size = ctx->fs ? ctx->fs->stack_size : 0;
1536 frame->fragment_stack_size = fs_stack_size << 16 | fs_stack_size;
1537
1538 /* related with MSAA and different value when r4p0/r7p0 */
1539 frame->supersampled_height = fb->base.height * 2 - 1;
1540 frame->scale = 0xE0C;
1541
1542 frame->dubya = 0x77;
1543 frame->onscreen = 1;
1544 frame->blocking = (fb->shift_min << 28) | (fb->shift_h << 16) | fb->shift_w;
1545 frame->foureight = 0x8888;
1546
1547 if (fb->base.nr_cbufs)
1548 lima_pack_wb_cbuf_reg(ctx, wb_reg, wb_idx++);
1549
1550 /* Mali4x0 can use on-tile buffer for depth/stencil, so to save some
1551 * memory bandwidth don't write depth/stencil back to memory if we're
1552 * rendering to scanout
1553 */
1554 if (!lima_is_scanout(ctx) && fb->base.zsbuf)
1555 lima_pack_wb_zsbuf_reg(ctx, wb_reg, wb_idx++);
1556 }
1557
1558 static void
1559 _lima_flush(struct lima_context *ctx, bool end_of_frame)
1560 {
1561 lima_finish_plbu_cmd(ctx);
1562
1563 int vs_cmd_size = ctx->vs_cmd_array.size;
1564 int plbu_cmd_size = ctx->plbu_cmd_array.size;
1565 uint32_t vs_cmd_va = 0;
1566 uint32_t plbu_cmd_va;
1567
1568 if (vs_cmd_size) {
1569 void *vs_cmd =
1570 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_vs_cmd, vs_cmd_size, true);
1571 memcpy(vs_cmd, util_dynarray_begin(&ctx->vs_cmd_array), vs_cmd_size);
1572 util_dynarray_clear(&ctx->vs_cmd_array);
1573 vs_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_vs_cmd,
1574 LIMA_CTX_BUFF_SUBMIT_GP);
1575
1576 lima_dump_command_stream_print(
1577 vs_cmd, vs_cmd_size, false, "flush vs cmd at va %x\n", vs_cmd_va);
1578 }
1579
1580 void *plbu_cmd =
1581 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_plbu_cmd, plbu_cmd_size, true);
1582 memcpy(plbu_cmd, util_dynarray_begin(&ctx->plbu_cmd_array), plbu_cmd_size);
1583 util_dynarray_clear(&ctx->plbu_cmd_array);
1584 plbu_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_plbu_cmd,
1585 LIMA_CTX_BUFF_SUBMIT_GP);
1586
1587 lima_dump_command_stream_print(
1588 plbu_cmd, plbu_cmd_size, false, "flush plbu cmd at va %x\n", plbu_cmd_va);
1589
1590 struct lima_screen *screen = lima_screen(ctx->base.screen);
1591 struct drm_lima_gp_frame gp_frame;
1592 struct lima_gp_frame_reg *gp_frame_reg = (void *)gp_frame.frame;
1593 gp_frame_reg->vs_cmd_start = vs_cmd_va;
1594 gp_frame_reg->vs_cmd_end = vs_cmd_va + vs_cmd_size;
1595 gp_frame_reg->plbu_cmd_start = plbu_cmd_va;
1596 gp_frame_reg->plbu_cmd_end = plbu_cmd_va + plbu_cmd_size;
1597 gp_frame_reg->tile_heap_start = ctx->gp_tile_heap[ctx->plb_index]->va;
1598 gp_frame_reg->tile_heap_end = ctx->gp_tile_heap[ctx->plb_index]->va + gp_tile_heap_size;
1599
1600 lima_dump_command_stream_print(
1601 &gp_frame, sizeof(gp_frame), false, "add gp frame\n");
1602
1603 if (!lima_submit_start(ctx->gp_submit, &gp_frame, sizeof(gp_frame)))
1604 fprintf(stderr, "gp submit error\n");
1605
1606 if (lima_dump_command_stream) {
1607 if (lima_submit_wait(ctx->gp_submit, PIPE_TIMEOUT_INFINITE)) {
1608 if (ctx->buffer_state[lima_ctx_buff_sh_gl_pos].res) {
1609 float *pos = lima_ctx_buff_map(ctx, lima_ctx_buff_sh_gl_pos);
1610 lima_dump_command_stream_print(
1611 pos, 4 * 4 * 16, true, "gl_pos dump at va %x\n",
1612 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos, 0));
1613 }
1614
1615 uint32_t *plb = lima_bo_map(ctx->plb[ctx->plb_index]);
1616 lima_dump_command_stream_print(
1617 plb, LIMA_CTX_PLB_BLK_SIZE, false, "plb dump at va %x\n",
1618 ctx->plb[ctx->plb_index]->va);
1619 }
1620 else {
1621 fprintf(stderr, "gp submit wait error\n");
1622 exit(1);
1623 }
1624 }
1625
1626 struct lima_pp_stream_state *ps = &ctx->pp_stream;
1627 if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI400) {
1628 struct drm_lima_m400_pp_frame pp_frame = {0};
1629 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1630 pp_frame.num_pp = screen->num_pp;
1631
1632 for (int i = 0; i < screen->num_pp; i++) {
1633 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1634 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1635 pp_stack_offset + pp_stack_pp_size * i;
1636 }
1637
1638 lima_dump_command_stream_print(
1639 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1640
1641 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1642 fprintf(stderr, "pp submit error\n");
1643 }
1644 else {
1645 struct drm_lima_m450_pp_frame pp_frame = {0};
1646 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1647 pp_frame.num_pp = screen->num_pp;
1648
1649 for (int i = 0; i < screen->num_pp; i++)
1650 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1651 pp_stack_offset + pp_stack_pp_size * i;
1652
1653 if (ps->bo) {
1654 for (int i = 0; i < screen->num_pp; i++)
1655 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1656 }
1657 else {
1658 pp_frame.use_dlbu = true;
1659
1660 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1661 pp_frame.dlbu_regs[0] = ctx->plb[ctx->plb_index]->va;
1662 pp_frame.dlbu_regs[1] = ((fb->tiled_h - 1) << 16) | (fb->tiled_w - 1);
1663 unsigned s = util_logbase2(LIMA_CTX_PLB_BLK_SIZE) - 7;
1664 pp_frame.dlbu_regs[2] = (s << 28) | (fb->shift_h << 16) | fb->shift_w;
1665 pp_frame.dlbu_regs[3] = ((fb->tiled_h - 1) << 24) | ((fb->tiled_w - 1) << 16);
1666 }
1667
1668 lima_dump_command_stream_print(
1669 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1670
1671 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1672 fprintf(stderr, "pp submit error\n");
1673 }
1674
1675 if (lima_dump_command_stream) {
1676 if (!lima_submit_wait(ctx->pp_submit, PIPE_TIMEOUT_INFINITE)) {
1677 fprintf(stderr, "pp wait error\n");
1678 exit(1);
1679 }
1680 }
1681
1682 ctx->plb_index = (ctx->plb_index + 1) % lima_ctx_num_plb;
1683
1684 if (ctx->framebuffer.base.nr_cbufs) {
1685 /* Set reload flag for next draw. It'll be unset if buffer is cleared */
1686 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
1687 surf->reload = true;
1688 }
1689 }
1690
1691 void
1692 lima_flush(struct lima_context *ctx)
1693 {
1694 if (!lima_ctx_dirty(ctx))
1695 return;
1696
1697 _lima_flush(ctx, false);
1698 }
1699
1700 static void
1701 lima_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
1702 unsigned flags)
1703 {
1704 struct lima_context *ctx = lima_context(pctx);
1705 if (!lima_ctx_dirty(ctx))
1706 return;
1707
1708 _lima_flush(ctx, flags & PIPE_FLUSH_END_OF_FRAME);
1709
1710 if (fence) {
1711 int fd;
1712 if (lima_submit_get_out_sync(ctx->pp_submit, &fd))
1713 *fence = lima_fence_create(fd);
1714 }
1715 }
1716
1717 void
1718 lima_draw_init(struct lima_context *ctx)
1719 {
1720 ctx->base.clear = lima_clear;
1721 ctx->base.draw_vbo = lima_draw_vbo;
1722 ctx->base.flush = lima_pipe_flush;
1723 }