2 * Copyright (c) 2011-2013 Luc Verhaegen <libv@skynet.be>
3 * Copyright (c) 2017-2019 Lima Project
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 #include "util/u_math.h"
27 #include "util/u_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_half.h"
30 #include "util/u_helpers.h"
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/hash_table.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36 #include "util/u_vbuf.h"
38 #include "lima_context.h"
39 #include "lima_screen.h"
40 #include "lima_resource.h"
41 #include "lima_program.h"
43 #include "lima_submit.h"
44 #include "lima_texture.h"
45 #include "lima_util.h"
46 #include "lima_fence.h"
47 #include "lima_format.h"
49 #include <drm-uapi/lima_drm.h>
51 struct lima_gp_frame_reg
{
52 uint32_t vs_cmd_start
;
54 uint32_t plbu_cmd_start
;
55 uint32_t plbu_cmd_end
;
56 uint32_t tile_heap_start
;
57 uint32_t tile_heap_end
;
60 struct lima_pp_frame_reg
{
61 uint32_t plbu_array_address
;
62 uint32_t render_address
;
65 uint32_t clear_value_depth
;
66 uint32_t clear_value_stencil
;
67 uint32_t clear_value_color
;
68 uint32_t clear_value_color_1
;
69 uint32_t clear_value_color_2
;
70 uint32_t clear_value_color_3
;
73 uint32_t fragment_stack_address
;
74 uint32_t fragment_stack_size
;
78 uint32_t supersampled_height
;
86 struct lima_pp_wb_reg
{
89 uint32_t pixel_format
;
90 uint32_t downsample_factor
;
91 uint32_t pixel_layout
;
101 struct lima_render_state
{
102 uint32_t blend_color_bg
;
103 uint32_t blend_color_ra
;
104 uint32_t alpha_blend
;
106 uint32_t depth_range
;
107 uint32_t stencil_front
;
108 uint32_t stencil_back
;
109 uint32_t stencil_test
;
110 uint32_t multi_sample
;
111 uint32_t shader_address
;
112 uint32_t varying_types
;
113 uint32_t uniforms_address
;
114 uint32_t textures_address
;
117 uint32_t varyings_address
;
122 #define PLBU_CMD_BEGIN(max) { \
123 int i = 0, max_n = max; \
124 uint32_t *plbu_cmd = util_dynarray_ensure_cap(&ctx->plbu_cmd_array, ctx->plbu_cmd_array.size + max_n * 4);
126 #define PLBU_CMD_END() \
127 assert(i <= max_n); \
128 ctx->plbu_cmd_array.size += i * 4; \
131 #define PLBU_CMD(v1, v2) \
133 plbu_cmd[i++] = v1; \
134 plbu_cmd[i++] = v2; \
137 #define PLBU_CMD_BLOCK_STEP(shift_min, shift_h, shift_w) \
138 PLBU_CMD(((shift_min) << 28) | ((shift_h) << 16) | (shift_w), 0x1000010C)
139 #define PLBU_CMD_TILED_DIMENSIONS(tiled_w, tiled_h) \
140 PLBU_CMD((((tiled_w) - 1) << 24) | (((tiled_h) - 1) << 8), 0x10000109)
141 #define PLBU_CMD_BLOCK_STRIDE(block_w) PLBU_CMD((block_w) & 0xff, 0x30000000)
142 #define PLBU_CMD_ARRAY_ADDRESS(gp_stream, block_num) \
143 PLBU_CMD(gp_stream, 0x28000000 | ((block_num) - 1) | 1)
144 #define PLBU_CMD_VIEWPORT_LEFT(v) PLBU_CMD(v, 0x10000107)
145 #define PLBU_CMD_VIEWPORT_RIGHT(v) PLBU_CMD(v, 0x10000108)
146 #define PLBU_CMD_VIEWPORT_BOTTOM(v) PLBU_CMD(v, 0x10000105)
147 #define PLBU_CMD_VIEWPORT_TOP(v) PLBU_CMD(v, 0x10000106)
148 #define PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN() PLBU_CMD(0x00010002, 0x60000000)
149 #define PLBU_CMD_ARRAYS_SEMAPHORE_END() PLBU_CMD(0x00010001, 0x60000000)
150 #define PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, index_size) \
151 PLBU_CMD(((low_prim) ? 0x00003200 : 0x00002200) | (cull) | ((index_size) << 9), 0x1000010B)
152 #define PLBU_CMD_RSW_VERTEX_ARRAY(rsw, gl_pos) \
153 PLBU_CMD(rsw, 0x80000000 | ((gl_pos) >> 4))
154 #define PLBU_CMD_SCISSORS(minx, maxx, miny, maxy) \
155 PLBU_CMD(((minx) << 30) | ((maxy) - 1) << 15 | (miny), \
156 0x70000000 | ((maxx) - 1) << 13 | ((minx) >> 2))
157 #define PLBU_CMD_UNKNOWN1() PLBU_CMD(0x00000000, 0x1000010A)
158 #define PLBU_CMD_UNKNOWN2() PLBU_CMD(0x00000200, 0x1000010B)
159 #define PLBU_CMD_LOW_PRIM_SIZE(v) PLBU_CMD(v, 0x1000010D)
160 #define PLBU_CMD_DEPTH_RANGE_NEAR(v) PLBU_CMD(v, 0x1000010E)
161 #define PLBU_CMD_DEPTH_RANGE_FAR(v) PLBU_CMD(v, 0x1000010F)
162 #define PLBU_CMD_INDEXED_DEST(gl_pos) PLBU_CMD(gl_pos, 0x10000100)
163 #define PLBU_CMD_INDICES(va) PLBU_CMD(va, 0x10000101)
164 #define PLBU_CMD_DRAW_ARRAYS(mode, start, count) \
165 PLBU_CMD(((count) << 24) | (start), (((mode) & 0x1F) << 16) | ((count) >> 8))
166 #define PLBU_CMD_DRAW_ELEMENTS(mode, start, count) \
167 PLBU_CMD(((count) << 24) | (start), \
168 0x00200000 | (((mode) & 0x1F) << 16) | ((count) >> 8))
171 #define VS_CMD_BEGIN(max) { \
172 int i = 0, max_n = max; \
173 uint32_t *vs_cmd = util_dynarray_ensure_cap(&ctx->vs_cmd_array, ctx->vs_cmd_array.size + max_n * 4);
175 #define VS_CMD_END() \
176 assert(i <= max_n); \
177 ctx->vs_cmd_array.size += i * 4; \
180 #define VS_CMD(v1, v2) \
186 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1() VS_CMD(0x00028000, 0x50000000)
187 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2() VS_CMD(0x00000001, 0x50000000)
188 #define VS_CMD_ARRAYS_SEMAPHORE_END(index_draw) \
189 VS_CMD((index_draw) ? 0x00018000 : 0x00000000, 0x50000000)
190 #define VS_CMD_UNIFORMS_ADDRESS(addr, size) \
191 VS_CMD(addr, 0x30000000 | ((size) << 12))
192 #define VS_CMD_SHADER_ADDRESS(addr, size) \
193 VS_CMD(addr, 0x40000000 | ((size) << 12))
194 #define VS_CMD_SHADER_INFO(prefetch, size) \
195 VS_CMD(((prefetch) << 20) | ((((size) >> 4) - 1) << 10), 0x10000040)
196 #define VS_CMD_VARYING_ATTRIBUTE_COUNT(nv, na) \
197 VS_CMD((((nv) - 1) << 8) | (((na) - 1) << 24), 0x10000042)
198 #define VS_CMD_UNKNOWN1() VS_CMD(0x00000003, 0x10000041)
199 #define VS_CMD_UNKNOWN2() VS_CMD(0x00000000, 0x60000000)
200 #define VS_CMD_ATTRIBUTES_ADDRESS(addr, na) \
201 VS_CMD(addr, 0x20000000 | ((na) << 17))
202 #define VS_CMD_VARYINGS_ADDRESS(addr, nv) \
203 VS_CMD(addr, 0x20000008 | ((nv) << 17))
204 #define VS_CMD_DRAW(num, index_draw) \
205 VS_CMD(((num) << 24) | ((index_draw) ? 1 : 0), ((num) >> 8))
208 lima_ctx_dirty(struct lima_context
*ctx
)
210 return ctx
->plbu_cmd_array
.size
;
214 lima_fb_need_reload(struct lima_context
*ctx
)
216 /* Depth buffer is always discarded */
217 if (!ctx
->framebuffer
.base
.nr_cbufs
)
219 if (ctx
->damage
.region
) {
220 /* for EGL_KHR_partial_update we just want to reload the
221 * region not aligned to tile boundary */
222 if (!ctx
->damage
.aligned
)
226 struct lima_surface
*surf
= lima_surface(ctx
->framebuffer
.base
.cbufs
[0]);
235 lima_pack_reload_plbu_cmd(struct lima_context
*ctx
)
237 #define lima_reload_render_state_offset 0x0000
238 #define lima_reload_gl_pos_offset 0x0040
239 #define lima_reload_varying_offset 0x0080
240 #define lima_reload_tex_desc_offset 0x00c0
241 #define lima_reload_tex_array_offset 0x0100
242 #define lima_reload_buffer_size 0x0140
246 struct pipe_resource
*pres
= NULL
;
247 u_upload_alloc(ctx
->uploader
, 0, lima_reload_buffer_size
,
248 0x40, &offset
, &pres
, &cpu
);
250 struct lima_resource
*res
= lima_resource(pres
);
251 uint32_t va
= res
->bo
->va
+ offset
;
253 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
255 uint32_t reload_shader_first_instr_size
=
256 ((uint32_t *)(screen
->pp_buffer
->map
+ pp_reload_program_offset
))[0] & 0x1f;
257 uint32_t reload_shader_va
= screen
->pp_buffer
->va
+ pp_reload_program_offset
;
259 struct lima_render_state reload_render_state
= {
260 .alpha_blend
= 0xf03b1ad2,
261 .depth_test
= 0x0000000e,
262 .depth_range
= 0xffff0000,
263 .stencil_front
= 0x00000007,
264 .stencil_back
= 0x00000007,
265 .multi_sample
= 0x0000f007,
266 .shader_address
= reload_shader_va
| reload_shader_first_instr_size
,
267 .varying_types
= 0x00000001,
268 .textures_address
= va
+ lima_reload_tex_array_offset
,
270 .varyings_address
= va
+ lima_reload_varying_offset
,
272 memcpy(cpu
+ lima_reload_render_state_offset
, &reload_render_state
,
273 sizeof(reload_render_state
));
275 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
276 lima_tex_desc
*td
= cpu
+ lima_reload_tex_desc_offset
;
277 memset(td
, 0, lima_min_tex_desc_size
);
278 lima_texture_desc_set_res(ctx
, td
, fb
->base
.cbufs
[0]->texture
, 0, 0);
279 td
->unknown_1_1
= 0x80;
281 td
->min_img_filter_nearest
= 1;
282 td
->mag_img_filter_nearest
= 1;
283 td
->wrap_s_clamp_to_edge
= 1;
284 td
->wrap_t_clamp_to_edge
= 1;
285 td
->unknown_2_2
= 0x1;
287 uint32_t *ta
= cpu
+ lima_reload_tex_array_offset
;
288 ta
[0] = va
+ lima_reload_tex_desc_offset
;
290 float reload_gl_pos
[] = {
291 fb
->base
.width
, 0, 0, 1,
293 0, fb
->base
.height
, 0, 1,
295 memcpy(cpu
+ lima_reload_gl_pos_offset
, reload_gl_pos
,
296 sizeof(reload_gl_pos
));
298 float reload_varying
[] = {
299 fb
->base
.width
, 0, 0, 0,
300 0, fb
->base
.height
, 0, 0,
302 memcpy(cpu
+ lima_reload_varying_offset
, reload_varying
,
303 sizeof(reload_varying
));
305 lima_submit_add_bo(ctx
->pp_submit
, res
->bo
, LIMA_SUBMIT_BO_READ
);
306 pipe_resource_reference(&pres
, NULL
);
310 PLBU_CMD_VIEWPORT_LEFT(0);
311 PLBU_CMD_VIEWPORT_RIGHT(fui(fb
->base
.width
));
312 PLBU_CMD_VIEWPORT_BOTTOM(0);
313 PLBU_CMD_VIEWPORT_TOP(fui(fb
->base
.height
));
315 PLBU_CMD_RSW_VERTEX_ARRAY(
316 va
+ lima_reload_render_state_offset
,
317 va
+ lima_reload_gl_pos_offset
);
322 PLBU_CMD_INDICES(screen
->pp_buffer
->va
+ pp_shared_index_offset
);
323 PLBU_CMD_INDEXED_DEST(va
+ lima_reload_gl_pos_offset
);
324 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
330 lima_pack_clear_plbu_cmd(struct lima_context
*ctx
)
332 #define lima_clear_render_state_offset 0x0000
333 #define lima_clear_shader_offset 0x0040
334 #define lima_clear_buffer_size 0x0080
338 struct pipe_resource
*pres
= NULL
;
339 u_upload_alloc(ctx
->uploader
, 0, lima_clear_buffer_size
,
340 0x40, &offset
, &pres
, &cpu
);
342 struct lima_resource
*res
= lima_resource(pres
);
343 uint32_t va
= res
->bo
->va
+ offset
;
345 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
346 uint32_t gl_pos_va
= screen
->pp_buffer
->va
+ pp_clear_gl_pos_offset
;
348 /* const0 clear_color, mov.v1 $0 ^const0.xxxx, stop */
349 uint32_t clear_shader
[] = {
350 0x00021025, 0x0000000c,
351 (ctx
->clear
.color_16pc
<< 12) | 0x000007cf,
352 ctx
->clear
.color_16pc
>> 12,
353 ctx
->clear
.color_16pc
>> 44,
355 memcpy(cpu
+ lima_clear_shader_offset
, &clear_shader
,
356 sizeof(clear_shader
));
358 uint32_t clear_shader_va
= va
+ lima_clear_shader_offset
;
359 uint32_t clear_shader_first_instr_size
= clear_shader
[0] & 0x1f;
361 struct lima_render_state clear_render_state
= {
362 .blend_color_bg
= 0x00800080,
363 .blend_color_ra
= 0x00ff0080,
364 .alpha_blend
= 0xfc321892,
365 .depth_test
= 0x0000003e,
366 .depth_range
= 0xffff0000,
367 .stencil_front
= 0x00000007,
368 .stencil_back
= 0x00000007,
369 .multi_sample
= 0x0000f007,
370 .shader_address
= clear_shader_va
| clear_shader_first_instr_size
,
372 memcpy(cpu
+ lima_clear_render_state_offset
, &clear_render_state
,
373 sizeof(clear_render_state
));
377 PLBU_CMD_VIEWPORT_LEFT(0);
378 PLBU_CMD_VIEWPORT_RIGHT(0x45800000);
379 PLBU_CMD_VIEWPORT_TOP(0);
380 PLBU_CMD_VIEWPORT_BOTTOM(0x45800000);
382 struct pipe_scissor_state
*scissor
= &ctx
->scissor
;
383 PLBU_CMD_SCISSORS(scissor
->minx
, scissor
->maxx
, scissor
->miny
, scissor
->maxy
);
385 PLBU_CMD_RSW_VERTEX_ARRAY(va
+ lima_clear_render_state_offset
, gl_pos_va
);
390 PLBU_CMD_INDICES(screen
->pp_buffer
->va
+ pp_shared_index_offset
);
391 PLBU_CMD_INDEXED_DEST(gl_pos_va
);
392 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
398 lima_pack_head_plbu_cmd(struct lima_context
*ctx
)
400 /* first draw need create a PLBU command header */
401 if (lima_ctx_dirty(ctx
))
404 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
409 PLBU_CMD_BLOCK_STEP(fb
->shift_min
, fb
->shift_h
, fb
->shift_w
);
410 PLBU_CMD_TILED_DIMENSIONS(fb
->tiled_w
, fb
->tiled_h
);
411 PLBU_CMD_BLOCK_STRIDE(fb
->block_w
);
413 PLBU_CMD_ARRAY_ADDRESS(
414 ctx
->plb_gp_stream
->va
+ ctx
->plb_index
* ctx
->plb_gp_size
,
415 fb
->block_w
* fb
->block_h
);
419 if (lima_fb_need_reload(ctx
))
420 lima_pack_reload_plbu_cmd(ctx
);
424 lima_is_scissor_zero(struct lima_context
*ctx
)
426 if (!ctx
->rasterizer
|| !ctx
->rasterizer
->base
.scissor
)
429 struct pipe_scissor_state
*scissor
= &ctx
->scissor
;
431 scissor
->minx
== scissor
->maxx
432 && scissor
->miny
== scissor
->maxy
;
436 lima_is_scissor_full_fb(struct lima_context
*ctx
)
438 if (!ctx
->rasterizer
|| !ctx
->rasterizer
->base
.scissor
)
441 struct pipe_scissor_state
*scissor
= &ctx
->scissor
;
442 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
444 scissor
->minx
== 0 && scissor
->maxx
== fb
->base
.width
&&
445 scissor
->miny
== 0 && scissor
->maxy
== fb
->base
.height
;
449 hilbert_rotate(int n
, int *x
, int *y
, int rx
, int ry
)
465 hilbert_coords(int n
, int d
, int *x
, int *y
)
471 for (i
= 0; (1 << i
) < n
; i
++) {
476 hilbert_rotate(1 << i
, x
, y
, rx
, ry
);
486 lima_get_pp_stream_size(int num_pp
, int tiled_w
, int tiled_h
, uint32_t *off
)
488 /* carefully calculate each stream start address:
489 * 1. overflow: each stream size may be different due to
490 * fb->tiled_w * fb->tiled_h can't be divided by num_pp,
491 * extra size should be added to the preceeding stream
492 * 2. alignment: each stream address should be 0x20 aligned
494 int delta
= tiled_w
* tiled_h
/ num_pp
* 16 + 8;
495 int remain
= tiled_w
* tiled_h
% num_pp
;
498 for (int i
= 0; i
< num_pp
; i
++) {
506 offset
= align(offset
, 0x20);
513 inside_damage_region(int x
, int y
, struct lima_damage_state
*ds
)
518 for (int i
= 0; i
< ds
->num_region
; i
++) {
519 struct pipe_scissor_state
*ss
= ds
->region
+ i
;
520 if (x
>= ss
->minx
&& x
< ss
->maxx
&&
521 y
>= ss
->miny
&& y
< ss
->maxy
)
529 lima_update_pp_stream(struct lima_context
*ctx
, int off_x
, int off_y
,
530 int tiled_w
, int tiled_h
)
532 struct lima_pp_stream_state
*ps
= &ctx
->pp_stream
;
533 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
534 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
535 int i
, num_pp
= screen
->num_pp
;
537 /* use hilbert_coords to generates 1D to 2D relationship.
538 * 1D for pp stream index and 2D for plb block x/y on framebuffer.
539 * if multi pp, interleave the 1D index to make each pp's render target
540 * close enough which should result close workload
542 int max
= MAX2(tiled_w
, tiled_h
);
543 int dim
= util_logbase2_ceil(max
);
544 int count
= 1 << (dim
+ dim
);
549 for (i
= 0; i
< num_pp
; i
++)
550 stream
[i
] = ps
->bo
->map
+ ps
->bo_offset
+ ps
->offset
[i
];
552 for (i
= 0; i
< count
; i
++) {
554 hilbert_coords(max
, i
, &x
, &y
);
555 if (x
< tiled_w
&& y
< tiled_h
) {
559 if (!inside_damage_region(x
, y
, &ctx
->damage
))
562 int pp
= index
% num_pp
;
563 int offset
= ((y
>> fb
->shift_h
) * fb
->block_w
+
564 (x
>> fb
->shift_w
)) * LIMA_CTX_PLB_BLK_SIZE
;
565 int plb_va
= ctx
->plb
[ctx
->plb_index
]->va
+ offset
;
567 stream
[pp
][si
[pp
]++] = 0;
568 stream
[pp
][si
[pp
]++] = 0xB8000000 | x
| (y
<< 8);
569 stream
[pp
][si
[pp
]++] = 0xE0000002 | ((plb_va
>> 3) & ~0xE0000003);
570 stream
[pp
][si
[pp
]++] = 0xB0000000;
576 for (i
= 0; i
< num_pp
; i
++) {
577 stream
[i
][si
[i
]++] = 0;
578 stream
[i
][si
[i
]++] = 0xBC000000;
580 lima_dump_command_stream_print(
581 stream
[i
], si
[i
] * 4, false, "pp plb stream %d at va %x\n",
582 i
, ps
->bo
->va
+ ps
->bo_offset
+ ps
->offset
[i
]);
587 lima_update_damage_pp_stream(struct lima_context
*ctx
)
589 struct lima_damage_state
*ds
= &ctx
->damage
;
590 struct pipe_scissor_state max
= ds
->region
[0];
592 /* find a max region to cover all the damage region */
593 for (int i
= 1; i
< ds
->num_region
; i
++) {
594 struct pipe_scissor_state
*ss
= ds
->region
+ i
;
595 max
.minx
= MIN2(max
.minx
, ss
->minx
);
596 max
.miny
= MIN2(max
.miny
, ss
->miny
);
597 max
.maxx
= MAX2(max
.maxx
, ss
->maxx
);
598 max
.maxy
= MAX2(max
.maxy
, ss
->maxy
);
601 int tiled_w
= max
.maxx
- max
.minx
;
602 int tiled_h
= max
.maxy
- max
.miny
;
603 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
604 int size
= lima_get_pp_stream_size(
605 screen
->num_pp
, tiled_w
, tiled_h
, ctx
->pp_stream
.offset
);
609 struct pipe_resource
*pres
= NULL
;
610 u_upload_alloc(ctx
->uploader
, 0, size
, 0x40, &offset
, &pres
, &cpu
);
612 struct lima_resource
*res
= lima_resource(pres
);
613 ctx
->pp_stream
.bo
= res
->bo
;
614 ctx
->pp_stream
.bo_offset
= offset
;
616 lima_update_pp_stream(ctx
, max
.minx
, max
.miny
, tiled_w
, tiled_h
);
618 lima_submit_add_bo(ctx
->pp_submit
, res
->bo
, LIMA_SUBMIT_BO_READ
);
619 pipe_resource_reference(&pres
, NULL
);
623 lima_update_full_pp_stream(struct lima_context
*ctx
)
625 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
626 struct lima_ctx_plb_pp_stream_key key
= {
627 .plb_index
= ctx
->plb_index
,
628 .tiled_w
= fb
->tiled_w
,
629 .tiled_h
= fb
->tiled_h
,
632 struct hash_entry
*entry
=
633 _mesa_hash_table_search(ctx
->plb_pp_stream
, &key
);
634 struct lima_ctx_plb_pp_stream
*s
= entry
->data
;
637 ctx
->pp_stream
.bo
= s
->bo
;
638 ctx
->pp_stream
.bo_offset
= 0;
639 memcpy(ctx
->pp_stream
.offset
, s
->offset
, sizeof(s
->offset
));
642 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
643 int size
= lima_get_pp_stream_size(
644 screen
->num_pp
, fb
->tiled_w
, fb
->tiled_h
, s
->offset
);
645 s
->bo
= lima_bo_create(screen
, size
, 0);
648 ctx
->pp_stream
.bo
= s
->bo
;
649 ctx
->pp_stream
.bo_offset
= 0;
650 memcpy(ctx
->pp_stream
.offset
, s
->offset
, sizeof(s
->offset
));
652 lima_update_pp_stream(ctx
, 0, 0, fb
->tiled_w
, fb
->tiled_h
);
655 lima_submit_add_bo(ctx
->pp_submit
, s
->bo
, LIMA_SUBMIT_BO_READ
);
659 lima_update_submit_bo(struct lima_context
*ctx
)
661 if (lima_ctx_dirty(ctx
))
664 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
665 lima_submit_add_bo(ctx
->gp_submit
, ctx
->plb_gp_stream
, LIMA_SUBMIT_BO_READ
);
666 lima_submit_add_bo(ctx
->gp_submit
, ctx
->plb
[ctx
->plb_index
], LIMA_SUBMIT_BO_WRITE
);
667 lima_submit_add_bo(ctx
->gp_submit
, ctx
->gp_tile_heap
[ctx
->plb_index
], LIMA_SUBMIT_BO_WRITE
);
669 lima_dump_command_stream_print(
670 ctx
->plb_gp_stream
->map
+ ctx
->plb_index
* ctx
->plb_gp_size
,
671 ctx
->plb_gp_size
, false, "gp plb stream at va %x\n",
672 ctx
->plb_gp_stream
->va
+ ctx
->plb_index
* ctx
->plb_gp_size
);
674 if (ctx
->damage
.region
)
675 lima_update_damage_pp_stream(ctx
);
676 else if (ctx
->plb_pp_stream
)
677 lima_update_full_pp_stream(ctx
);
679 ctx
->pp_stream
.bo
= NULL
;
681 if (ctx
->framebuffer
.base
.nr_cbufs
) {
682 struct lima_resource
*res
= lima_resource(ctx
->framebuffer
.base
.cbufs
[0]->texture
);
683 lima_submit_add_bo(ctx
->pp_submit
, res
->bo
, LIMA_SUBMIT_BO_WRITE
);
685 if (ctx
->framebuffer
.base
.zsbuf
) {
686 struct lima_resource
*res
= lima_resource(ctx
->framebuffer
.base
.zsbuf
->texture
);
687 lima_submit_add_bo(ctx
->pp_submit
, res
->bo
, LIMA_SUBMIT_BO_WRITE
);
689 lima_submit_add_bo(ctx
->pp_submit
, ctx
->plb
[ctx
->plb_index
], LIMA_SUBMIT_BO_READ
);
690 lima_submit_add_bo(ctx
->pp_submit
, ctx
->gp_tile_heap
[ctx
->plb_index
], LIMA_SUBMIT_BO_READ
);
691 lima_submit_add_bo(ctx
->pp_submit
, screen
->pp_buffer
, LIMA_SUBMIT_BO_READ
);
695 lima_clear(struct pipe_context
*pctx
, unsigned buffers
,
696 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
698 struct lima_context
*ctx
= lima_context(pctx
);
699 bool full_fb_clear
= lima_is_scissor_full_fb(ctx
);
704 /* no need to reload if cleared */
705 if (ctx
->framebuffer
.base
.nr_cbufs
&& (buffers
& PIPE_CLEAR_COLOR0
)) {
706 struct lima_surface
*surf
= lima_surface(ctx
->framebuffer
.base
.cbufs
[0]);
707 surf
->reload
= false;
711 struct lima_context_clear
*clear
= &ctx
->clear
;
712 clear
->buffers
= buffers
;
714 if (buffers
& PIPE_CLEAR_COLOR0
) {
716 ((uint32_t)float_to_ubyte(color
->f
[3]) << 24) |
717 ((uint32_t)float_to_ubyte(color
->f
[2]) << 16) |
718 ((uint32_t)float_to_ubyte(color
->f
[1]) << 8) |
719 float_to_ubyte(color
->f
[0]);
722 ((uint64_t)float_to_ushort(color
->f
[3]) << 48) |
723 ((uint64_t)float_to_ushort(color
->f
[2]) << 32) |
724 ((uint64_t)float_to_ushort(color
->f
[1]) << 16) |
725 float_to_ushort(color
->f
[0]);
728 if (buffers
& PIPE_CLEAR_DEPTH
)
729 clear
->depth
= util_pack_z(PIPE_FORMAT_Z24X8_UNORM
, depth
);
731 if (buffers
& PIPE_CLEAR_STENCIL
)
732 clear
->stencil
= stencil
;
734 lima_update_submit_bo(ctx
);
736 lima_pack_head_plbu_cmd(ctx
);
740 lima_pack_clear_plbu_cmd(ctx
);
742 ctx
->dirty
|= LIMA_CONTEXT_DIRTY_CLEAR
;
745 enum lima_attrib_type
{
746 LIMA_ATTRIB_FLOAT
= 0x000,
747 /* todo: find out what lives here. */
748 LIMA_ATTRIB_I16
= 0x004,
749 LIMA_ATTRIB_U16
= 0x005,
750 LIMA_ATTRIB_I8
= 0x006,
751 LIMA_ATTRIB_U8
= 0x007,
752 LIMA_ATTRIB_I8N
= 0x008,
753 LIMA_ATTRIB_U8N
= 0x009,
754 LIMA_ATTRIB_I16N
= 0x00A,
755 LIMA_ATTRIB_U16N
= 0x00B,
756 /* todo: where is the 32 int */
757 /* todo: find out what lives here. */
758 LIMA_ATTRIB_FIXED
= 0x101
761 static enum lima_attrib_type
762 lima_pipe_format_to_attrib_type(enum pipe_format format
)
764 const struct util_format_description
*desc
= util_format_description(format
);
765 int i
= util_format_get_first_non_void_channel(format
);
766 const struct util_format_channel_description
*c
= desc
->channel
+ i
;
769 case UTIL_FORMAT_TYPE_FLOAT
:
770 return LIMA_ATTRIB_FLOAT
;
771 case UTIL_FORMAT_TYPE_FIXED
:
772 return LIMA_ATTRIB_FIXED
;
773 case UTIL_FORMAT_TYPE_SIGNED
:
776 return LIMA_ATTRIB_I8N
;
778 return LIMA_ATTRIB_I8
;
780 else if (c
->size
== 16) {
782 return LIMA_ATTRIB_I16N
;
784 return LIMA_ATTRIB_I16
;
787 case UTIL_FORMAT_TYPE_UNSIGNED
:
790 return LIMA_ATTRIB_U8N
;
792 return LIMA_ATTRIB_U8
;
794 else if (c
->size
== 16) {
796 return LIMA_ATTRIB_U16N
;
798 return LIMA_ATTRIB_U16
;
803 return LIMA_ATTRIB_FLOAT
;
807 lima_pack_vs_cmd(struct lima_context
*ctx
, const struct pipe_draw_info
*info
)
811 if (!info
->index_size
) {
812 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1();
813 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2();
816 int uniform_size
= ctx
->vs
->uniform_pending_offset
+ ctx
->vs
->constant_size
+ 32;
817 VS_CMD_UNIFORMS_ADDRESS(
818 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_uniform
, LIMA_CTX_BUFF_SUBMIT_GP
),
819 align(uniform_size
, 16));
821 VS_CMD_SHADER_ADDRESS(ctx
->vs
->bo
->va
, ctx
->vs
->shader_size
);
822 VS_CMD_SHADER_INFO(ctx
->vs
->prefetch
, ctx
->vs
->shader_size
);
824 int num_varryings
= ctx
->vs
->num_varying
;
825 int num_attributes
= ctx
->vertex_elements
->num_elements
;
826 VS_CMD_VARYING_ATTRIBUTE_COUNT(num_varryings
, num_attributes
);
830 VS_CMD_ATTRIBUTES_ADDRESS(
831 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_attribute_info
, LIMA_CTX_BUFF_SUBMIT_GP
),
834 VS_CMD_VARYINGS_ADDRESS(
835 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_varying_info
, LIMA_CTX_BUFF_SUBMIT_GP
),
838 unsigned num
= info
->index_size
? (ctx
->max_index
- ctx
->min_index
+ 1) : info
->count
;
839 VS_CMD_DRAW(num
, info
->index_size
);
843 VS_CMD_ARRAYS_SEMAPHORE_END(info
->index_size
);
849 lima_pack_plbu_cmd(struct lima_context
*ctx
, const struct pipe_draw_info
*info
)
851 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
853 lima_pack_head_plbu_cmd(ctx
);
855 /* If it's zero scissor, we skip adding all other commands */
856 if (lima_is_scissor_zero(ctx
))
861 PLBU_CMD_VIEWPORT_LEFT(fui(ctx
->viewport
.left
));
862 PLBU_CMD_VIEWPORT_RIGHT(fui(ctx
->viewport
.right
));
863 PLBU_CMD_VIEWPORT_BOTTOM(fui(ctx
->viewport
.bottom
));
864 PLBU_CMD_VIEWPORT_TOP(fui(ctx
->viewport
.top
));
866 if (!info
->index_size
)
867 PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN();
869 bool low_prim
= info
->mode
< PIPE_PRIM_TRIANGLES
;
870 int cf
= ctx
->rasterizer
->base
.cull_face
;
871 int ccw
= ctx
->rasterizer
->base
.front_ccw
;
873 if (cf
!= PIPE_FACE_NONE
) {
874 if (cf
& PIPE_FACE_FRONT
)
875 cull
|= ccw
? 0x00040000 : 0x00020000;
876 if (cf
& PIPE_FACE_BACK
)
877 cull
|= ccw
? 0x00020000 : 0x00040000;
879 PLBU_CMD_PRIMITIVE_SETUP(low_prim
, cull
, info
->index_size
);
881 uint32_t gl_position_va
=
882 lima_ctx_buff_va(ctx
, lima_ctx_buff_sh_gl_pos
,
883 LIMA_CTX_BUFF_SUBMIT_GP
| LIMA_CTX_BUFF_SUBMIT_PP
);
884 PLBU_CMD_RSW_VERTEX_ARRAY(
885 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_plb_rsw
, LIMA_CTX_BUFF_SUBMIT_PP
),
889 * - we should set it only for the first draw that enabled the scissor and for
890 * latter draw only if scissor is dirty
892 if (ctx
->rasterizer
->base
.scissor
) {
893 struct pipe_scissor_state
*scissor
= &ctx
->scissor
;
894 PLBU_CMD_SCISSORS(scissor
->minx
, scissor
->maxx
, scissor
->miny
, scissor
->maxy
);
896 PLBU_CMD_SCISSORS(0, fb
->base
.width
, 0, fb
->base
.height
);
901 PLBU_CMD_DEPTH_RANGE_NEAR(fui(ctx
->viewport
.near
));
902 PLBU_CMD_DEPTH_RANGE_FAR(fui(ctx
->viewport
.far
));
905 uint32_t v
= info
->mode
== PIPE_PRIM_POINTS
?
906 fui(ctx
->rasterizer
->base
.point_size
) : fui(ctx
->rasterizer
->base
.line_width
);
907 PLBU_CMD_LOW_PRIM_SIZE(v
);
910 if (info
->index_size
) {
911 PLBU_CMD_INDEXED_DEST(gl_position_va
);
913 struct pipe_resource
*indexbuf
= NULL
;
914 unsigned index_offset
= 0;
915 struct lima_resource
*res
;
916 if (info
->has_user_indices
) {
917 util_upload_index_buffer(&ctx
->base
, info
, &indexbuf
, &index_offset
);
918 res
= lima_resource(indexbuf
);
921 res
= lima_resource(info
->index
.resource
);
923 lima_submit_add_bo(ctx
->gp_submit
, res
->bo
, LIMA_SUBMIT_BO_READ
);
924 PLBU_CMD_INDICES(res
->bo
->va
+ info
->start
* info
->index_size
+ index_offset
);
927 pipe_resource_reference(&indexbuf
, NULL
);
930 /* can this make the attribute info static? */
931 PLBU_CMD_DRAW_ARRAYS(info
->mode
, info
->start
, info
->count
);
934 PLBU_CMD_ARRAYS_SEMAPHORE_END();
936 if (info
->index_size
)
937 PLBU_CMD_DRAW_ELEMENTS(info
->mode
, ctx
->min_index
, info
->count
);
943 lima_blend_func(enum pipe_blend_func pipe
)
948 case PIPE_BLEND_SUBTRACT
:
950 case PIPE_BLEND_REVERSE_SUBTRACT
:
961 lima_blend_factor(enum pipe_blendfactor pipe
)
964 case PIPE_BLENDFACTOR_ONE
:
966 case PIPE_BLENDFACTOR_SRC_COLOR
:
968 case PIPE_BLENDFACTOR_SRC_ALPHA
:
970 case PIPE_BLENDFACTOR_DST_ALPHA
:
972 case PIPE_BLENDFACTOR_DST_COLOR
:
974 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
976 case PIPE_BLENDFACTOR_CONST_COLOR
:
978 case PIPE_BLENDFACTOR_CONST_ALPHA
:
980 case PIPE_BLENDFACTOR_ZERO
:
982 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
984 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
986 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
988 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
990 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
992 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
994 case PIPE_BLENDFACTOR_SRC1_COLOR
:
995 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
996 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
997 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
998 return -1; /* not support */
1004 lima_calculate_alpha_blend(enum pipe_blend_func rgb_func
, enum pipe_blend_func alpha_func
,
1005 enum pipe_blendfactor rgb_src_factor
, enum pipe_blendfactor rgb_dst_factor
,
1006 enum pipe_blendfactor alpha_src_factor
, enum pipe_blendfactor alpha_dst_factor
)
1008 return lima_blend_func(rgb_func
) |
1009 (lima_blend_func(alpha_func
) << 3) |
1010 (lima_blend_factor(rgb_src_factor
) << 6) |
1011 (lima_blend_factor(rgb_dst_factor
) << 11) |
1012 ((lima_blend_factor(alpha_src_factor
) & 0xF) << 16) |
1013 ((lima_blend_factor(alpha_dst_factor
) & 0xF) << 20) |
1014 0x0C000000; /* need check if this GLESv1 glAlphaFunc */
1019 lima_stencil_op(enum pipe_stencil_op pipe
)
1022 case PIPE_STENCIL_OP_KEEP
:
1024 case PIPE_STENCIL_OP_ZERO
:
1026 case PIPE_STENCIL_OP_REPLACE
:
1028 case PIPE_STENCIL_OP_INCR
:
1030 case PIPE_STENCIL_OP_DECR
:
1032 case PIPE_STENCIL_OP_INCR_WRAP
:
1034 case PIPE_STENCIL_OP_DECR_WRAP
:
1036 case PIPE_STENCIL_OP_INVERT
:
1044 lima_calculate_depth_test(struct pipe_depth_state
*depth
, struct pipe_rasterizer_state
*rst
)
1046 enum pipe_compare_func func
= (depth
->enabled
? depth
->func
: PIPE_FUNC_ALWAYS
);
1048 int offset_scale
= 0;
1050 //TODO: implement polygon offset
1052 if (rst
->offset_scale
< -32)
1054 else if (rst
->offset_scale
> 31)
1057 offset_scale
= rst
->offset_scale
* 4;
1059 if (offset_scale
< 0)
1060 offset_scale
= 0x100 + offset_scale
;
1063 return (depth
->enabled
&& depth
->writemask
) |
1065 (offset_scale
<< 16) |
1066 0x30; /* find out what is this */
1070 lima_pack_render_state(struct lima_context
*ctx
, const struct pipe_draw_info
*info
)
1072 struct lima_render_state
*render
=
1073 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_pp_plb_rsw
,
1074 sizeof(*render
), true);
1076 /* do hw support RGBA independ blend?
1077 * PIPE_CAP_INDEP_BLEND_ENABLE
1079 * how to handle the no cbuf only zbuf case?
1081 struct pipe_rt_blend_state
*rt
= ctx
->blend
->base
.rt
;
1082 render
->blend_color_bg
= float_to_ubyte(ctx
->blend_color
.color
[2]) |
1083 (float_to_ubyte(ctx
->blend_color
.color
[1]) << 16);
1084 render
->blend_color_ra
= float_to_ubyte(ctx
->blend_color
.color
[0]) |
1085 (float_to_ubyte(ctx
->blend_color
.color
[3]) << 16);
1087 if (rt
->blend_enable
) {
1088 render
->alpha_blend
= lima_calculate_alpha_blend(rt
->rgb_func
, rt
->alpha_func
,
1089 rt
->rgb_src_factor
, rt
->rgb_dst_factor
,
1090 rt
->alpha_src_factor
, rt
->alpha_dst_factor
);
1094 * Special handling for blending disabled.
1095 * Binary driver is generating the same alpha_value,
1096 * as when we would just enable blending, without changing/setting any blend equation/params.
1097 * Normaly in this case mesa would set all rt fields (func/factor) to zero.
1099 render
->alpha_blend
= lima_calculate_alpha_blend(PIPE_BLEND_ADD
, PIPE_BLEND_ADD
,
1100 PIPE_BLENDFACTOR_ONE
, PIPE_BLENDFACTOR_ZERO
,
1101 PIPE_BLENDFACTOR_ONE
, PIPE_BLENDFACTOR_ZERO
);
1104 render
->alpha_blend
|= (rt
->colormask
& PIPE_MASK_RGBA
) << 28;
1106 struct pipe_rasterizer_state
*rst
= &ctx
->rasterizer
->base
;
1107 struct pipe_depth_state
*depth
= &ctx
->zsa
->base
.depth
;
1108 render
->depth_test
= lima_calculate_depth_test(depth
, rst
);
1110 /* overlap with plbu? any place can remove one? */
1111 render
->depth_range
= float_to_ushort(ctx
->viewport
.near
) |
1112 (float_to_ushort(ctx
->viewport
.far
) << 16);
1115 struct pipe_stencil_state
*stencil
= ctx
->zsa
->base
.stencil
;
1116 struct pipe_stencil_ref
*ref
= &ctx
->stencil_ref
;
1117 render
->stencil_front
= stencil
[0].func
|
1118 (lima_stencil_op(stencil
[0].fail_op
) << 3) |
1119 (lima_stencil_op(stencil
[0].zfail_op
) << 6) |
1120 (lima_stencil_op(stencil
[0].zpass_op
) << 9) |
1121 (ref
->ref_value
[0] << 16) |
1122 (stencil
[0].valuemask
<< 24);
1123 render
->stencil_back
= stencil
[1].func
|
1124 (lima_stencil_op(stencil
[1].fail_op
) << 3) |
1125 (lima_stencil_op(stencil
[1].zfail_op
) << 6) |
1126 (lima_stencil_op(stencil
[1].zpass_op
) << 9) |
1127 (ref
->ref_value
[1] << 16) |
1128 (stencil
[1].valuemask
<< 24);
1130 render
->stencil_front
= 0xff000007;
1131 render
->stencil_back
= 0xff000007;
1134 /* seems not correct? */
1135 //struct pipe_alpha_state *alpha = &ctx->zsa->base.alpha;
1136 render
->stencil_test
= 0;
1137 //(stencil->enabled ? 0xFF : 0x00) | (float_to_ubyte(alpha->ref_value) << 16)
1139 /* need more investigation */
1140 if (info
->mode
== PIPE_PRIM_POINTS
)
1141 render
->multi_sample
= 0x0000F007;
1142 else if (info
->mode
< PIPE_PRIM_TRIANGLES
)
1143 render
->multi_sample
= 0x0000F407;
1145 render
->multi_sample
= 0x0000F807;
1146 if (ctx
->framebuffer
.base
.samples
)
1147 render
->multi_sample
|= 0x68;
1149 render
->shader_address
=
1150 ctx
->fs
->bo
->va
| (((uint32_t *)ctx
->fs
->bo
->map
)[0] & 0x1F);
1152 /* seems not needed */
1153 render
->uniforms_address
= 0x00000000;
1155 render
->textures_address
= 0x00000000;
1157 /* more investigation */
1158 render
->aux0
= 0x00000300 | (ctx
->vs
->varying_stride
>> 3);
1159 render
->aux1
= 0x00003000;
1161 if (ctx
->tex_stateobj
.num_samplers
) {
1162 render
->textures_address
=
1163 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_tex_desc
, LIMA_CTX_BUFF_SUBMIT_PP
);
1164 render
->aux0
|= ctx
->tex_stateobj
.num_samplers
<< 14;
1165 render
->aux0
|= 0x20;
1168 if (ctx
->const_buffer
[PIPE_SHADER_FRAGMENT
].buffer
) {
1169 render
->uniforms_address
=
1170 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_uniform_array
, LIMA_CTX_BUFF_SUBMIT_PP
);
1171 render
->uniforms_address
|= ((ctx
->buffer_state
[lima_ctx_buff_pp_uniform
].size
) / 4 - 1);
1172 render
->aux0
|= 0x80;
1173 render
->aux1
|= 0x10000;
1176 if (ctx
->vs
->num_varying
> 1) {
1177 render
->varying_types
= 0x00000000;
1178 render
->varyings_address
=
1179 lima_ctx_buff_va(ctx
, lima_ctx_buff_sh_varying
, LIMA_CTX_BUFF_SUBMIT_PP
);
1180 for (int i
= 1; i
< ctx
->vs
->num_varying
; i
++) {
1183 struct lima_varying_info
*v
= ctx
->vs
->varying
+ i
;
1184 if (v
->component_size
== 4)
1185 val
= v
->components
> 2 ? 0 : 1;
1187 val
= v
->components
> 2 ? 2 : 3;
1191 render
->varying_types
|= val
<< (3 * index
);
1192 else if (index
== 10) {
1193 render
->varying_types
|= val
<< 30;
1194 render
->varyings_address
|= val
>> 2;
1196 else if (index
== 11)
1197 render
->varyings_address
|= val
<< 1;
1201 render
->varying_types
= 0x00000000;
1202 render
->varyings_address
= 0x00000000;
1205 lima_dump_command_stream_print(
1206 render
, sizeof(*render
), false, "add render state at va %x\n",
1207 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_plb_rsw
, 0));
1211 lima_update_gp_attribute_info(struct lima_context
*ctx
, const struct pipe_draw_info
*info
)
1213 struct lima_vertex_element_state
*ve
= ctx
->vertex_elements
;
1214 struct lima_context_vertex_buffer
*vb
= &ctx
->vertex_buffers
;
1216 uint32_t *attribute
=
1217 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_gp_attribute_info
,
1218 ve
->num_elements
* 8, true);
1221 for (int i
= 0; i
< ve
->num_elements
; i
++) {
1222 struct pipe_vertex_element
*pve
= ve
->pipe
+ i
;
1224 assert(pve
->vertex_buffer_index
< vb
->count
);
1225 assert(vb
->enabled_mask
& (1 << pve
->vertex_buffer_index
));
1227 struct pipe_vertex_buffer
*pvb
= vb
->vb
+ pve
->vertex_buffer_index
;
1228 struct lima_resource
*res
= lima_resource(pvb
->buffer
.resource
);
1230 lima_submit_add_bo(ctx
->gp_submit
, res
->bo
, LIMA_SUBMIT_BO_READ
);
1232 unsigned start
= info
->index_size
? ctx
->min_index
: info
->start
;
1233 attribute
[n
++] = res
->bo
->va
+ pvb
->buffer_offset
+ pve
->src_offset
1234 + start
* pvb
->stride
;
1235 attribute
[n
++] = (pvb
->stride
<< 11) |
1236 (lima_pipe_format_to_attrib_type(pve
->src_format
) << 2) |
1237 (util_format_get_nr_components(pve
->src_format
) - 1);
1240 lima_dump_command_stream_print(
1241 attribute
, n
* 4, false, "update attribute info at va %x\n",
1242 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_attribute_info
, 0));
1246 lima_update_gp_uniform(struct lima_context
*ctx
)
1248 struct lima_context_constant_buffer
*ccb
=
1249 ctx
->const_buffer
+ PIPE_SHADER_VERTEX
;
1250 struct lima_vs_shader_state
*vs
= ctx
->vs
;
1252 int size
= vs
->uniform_pending_offset
+ vs
->constant_size
+ 32;
1253 void *vs_const_buff
=
1254 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_gp_uniform
, size
, true);
1257 memcpy(vs_const_buff
, ccb
->buffer
, ccb
->size
);
1259 memcpy(vs_const_buff
+ vs
->uniform_pending_offset
,
1260 ctx
->viewport
.transform
.scale
,
1261 sizeof(ctx
->viewport
.transform
.scale
));
1262 memcpy(vs_const_buff
+ vs
->uniform_pending_offset
+ 16,
1263 ctx
->viewport
.transform
.translate
,
1264 sizeof(ctx
->viewport
.transform
.translate
));
1267 memcpy(vs_const_buff
+ vs
->uniform_pending_offset
+ 32,
1268 vs
->constant
, vs
->constant_size
);
1270 lima_dump_command_stream_print(
1271 vs_const_buff
, size
, true,
1272 "update gp uniform at va %x\n",
1273 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_uniform
, 0));
1277 lima_update_pp_uniform(struct lima_context
*ctx
)
1279 const float *const_buff
= ctx
->const_buffer
[PIPE_SHADER_FRAGMENT
].buffer
;
1280 size_t const_buff_size
= ctx
->const_buffer
[PIPE_SHADER_FRAGMENT
].size
/ sizeof(float);
1285 uint16_t *fp16_const_buff
=
1286 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_pp_uniform
,
1287 const_buff_size
* sizeof(uint16_t), true);
1290 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_pp_uniform_array
, 4, true);
1292 for (int i
= 0; i
< const_buff_size
; i
++)
1293 fp16_const_buff
[i
] = util_float_to_half(const_buff
[i
]);
1295 *array
= lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_uniform
, LIMA_CTX_BUFF_SUBMIT_PP
);
1297 lima_dump_command_stream_print(
1298 fp16_const_buff
, const_buff_size
* 2, false, "add pp uniform data at va %x\n",
1299 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_uniform
, 0));
1300 lima_dump_command_stream_print(
1301 array
, 4, false, "add pp uniform info at va %x\n",
1302 lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_uniform_array
, 0));
1306 lima_update_varying(struct lima_context
*ctx
, const struct pipe_draw_info
*info
)
1308 struct lima_vs_shader_state
*vs
= ctx
->vs
;
1311 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_gp_varying_info
,
1312 vs
->num_varying
* 8, true);
1315 /* should be LIMA_SUBMIT_BO_WRITE for GP, but each draw will use
1316 * different part of this bo, so no need to set exclusive constraint */
1317 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_sh_gl_pos
,
1318 4 * 4 * info
->count
, false);
1320 /* for gl_Position */
1322 lima_ctx_buff_va(ctx
, lima_ctx_buff_sh_gl_pos
,
1323 LIMA_CTX_BUFF_SUBMIT_GP
| LIMA_CTX_BUFF_SUBMIT_PP
);
1324 varying
[n
++] = 0x8020;
1327 for (int i
= 1; i
< vs
->num_varying
; i
++) {
1328 struct lima_varying_info
*v
= vs
->varying
+ i
;
1329 int size
= v
->component_size
* 4;
1331 /* does component_size == 2 need to be 16 aligned? */
1332 if (v
->component_size
== 4)
1333 offset
= align(offset
, 16);
1338 vs
->varying_stride
= align(offset
, 16);
1340 if (vs
->num_varying
> 1)
1341 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_sh_varying
,
1342 vs
->varying_stride
* info
->count
, false);
1344 for (int i
= 1; i
< vs
->num_varying
; i
++) {
1345 struct lima_varying_info
*v
= vs
->varying
+ i
;
1347 lima_ctx_buff_va(ctx
, lima_ctx_buff_sh_varying
, LIMA_CTX_BUFF_SUBMIT_GP
) +
1349 varying
[n
++] = (vs
->varying_stride
<< 11) | (v
->components
- 1) |
1350 (v
->component_size
== 2 ? 0x0C : 0);
1353 lima_dump_command_stream_print(
1354 varying
, n
* 4, false, "update varying info at va %x\n",
1355 lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_varying_info
, 0));
1359 lima_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
1361 /* check if draw mode and vertex/index count match,
1362 * otherwise gp will hang */
1363 if (!u_trim_pipe_prim(info
->mode
, (unsigned*)&info
->count
)) {
1364 debug_printf("draw mode and vertex/index count mismatch\n");
1368 struct lima_context
*ctx
= lima_context(pctx
);
1370 if (!ctx
->vs
|| !ctx
->fs
) {
1371 debug_warn_once("no shader, skip draw\n");
1375 if (!lima_update_vs_state(ctx
) || !lima_update_fs_state(ctx
))
1378 lima_dump_command_stream_print(
1379 ctx
->vs
->bo
->map
, ctx
->vs
->shader_size
, false,
1380 "add vs at va %x\n", ctx
->vs
->bo
->va
);
1382 lima_dump_command_stream_print(
1383 ctx
->fs
->bo
->map
, ctx
->fs
->shader_size
, false,
1384 "add fs at va %x\n", ctx
->fs
->bo
->va
);
1386 lima_submit_add_bo(ctx
->gp_submit
, ctx
->vs
->bo
, LIMA_SUBMIT_BO_READ
);
1387 lima_submit_add_bo(ctx
->pp_submit
, ctx
->fs
->bo
, LIMA_SUBMIT_BO_READ
);
1389 lima_update_submit_bo(ctx
);
1391 /* Mali Utgard GPU always need min/max index info for index draw,
1392 * compute it if upper layer does not do for us */
1393 if (info
->index_size
&& info
->max_index
== ~0u)
1394 u_vbuf_get_minmax_index(pctx
, info
, &ctx
->min_index
, &ctx
->max_index
);
1396 ctx
->min_index
= info
->min_index
;
1397 ctx
->max_index
= info
->max_index
;
1400 lima_update_gp_attribute_info(ctx
, info
);
1402 if ((ctx
->dirty
& LIMA_CONTEXT_DIRTY_CONST_BUFF
&&
1403 ctx
->const_buffer
[PIPE_SHADER_VERTEX
].dirty
) ||
1404 ctx
->dirty
& LIMA_CONTEXT_DIRTY_VIEWPORT
||
1405 ctx
->dirty
& LIMA_CONTEXT_DIRTY_SHADER_VERT
) {
1406 lima_update_gp_uniform(ctx
);
1407 ctx
->const_buffer
[PIPE_SHADER_VERTEX
].dirty
= false;
1410 lima_update_varying(ctx
, info
);
1412 /* If it's zero scissor, don't build vs cmd list */
1413 if (!lima_is_scissor_zero(ctx
))
1414 lima_pack_vs_cmd(ctx
, info
);
1416 if (ctx
->dirty
& LIMA_CONTEXT_DIRTY_CONST_BUFF
&&
1417 ctx
->const_buffer
[PIPE_SHADER_FRAGMENT
].dirty
) {
1418 lima_update_pp_uniform(ctx
);
1419 ctx
->const_buffer
[PIPE_SHADER_FRAGMENT
].dirty
= false;
1422 if (ctx
->dirty
& LIMA_CONTEXT_DIRTY_TEXTURES
)
1423 lima_update_textures(ctx
);
1425 lima_pack_render_state(ctx
, info
);
1426 lima_pack_plbu_cmd(ctx
, info
);
1432 lima_finish_plbu_cmd(struct lima_context
*ctx
)
1435 uint32_t *plbu_cmd
= util_dynarray_ensure_cap(&ctx
->plbu_cmd_array
, ctx
->plbu_cmd_array
.size
+ 2 * 4);
1437 plbu_cmd
[i
++] = 0x00000000;
1438 plbu_cmd
[i
++] = 0x50000000; /* END */
1440 ctx
->plbu_cmd_array
.size
+= i
* 4;
1444 lima_pack_wb_zsbuf_reg(struct lima_context
*ctx
, uint32_t *wb_reg
, int wb_idx
)
1446 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
1447 struct lima_resource
*res
= lima_resource(fb
->base
.zsbuf
->texture
);
1448 int level
= fb
->base
.zsbuf
->u
.tex
.level
;
1449 uint32_t format
= lima_format_get_pixel(fb
->base
.zsbuf
->format
);
1451 struct lima_pp_wb_reg
*wb
= (void *)wb_reg
;
1452 wb
[wb_idx
].type
= 0x01; /* 1 for depth, stencil */
1453 wb
[wb_idx
].address
= res
->bo
->va
+ res
->levels
[level
].offset
;
1454 wb
[wb_idx
].pixel_format
= format
;
1456 wb
[wb_idx
].pixel_layout
= 0x2;
1457 wb
[wb_idx
].pitch
= fb
->tiled_w
;
1459 wb
[wb_idx
].pixel_layout
= 0x0;
1460 wb
[wb_idx
].pitch
= res
->levels
[level
].stride
/ 8;
1462 wb
[wb_idx
].mrt_bits
= 0;
1466 lima_pack_wb_cbuf_reg(struct lima_context
*ctx
, uint32_t *wb_reg
, int wb_idx
)
1468 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
1469 struct lima_resource
*res
= lima_resource(fb
->base
.cbufs
[0]->texture
);
1470 int level
= fb
->base
.cbufs
[0]->u
.tex
.level
;
1471 uint32_t format
= lima_format_get_pixel(fb
->base
.cbufs
[0]->format
);
1472 bool swap_channels
= lima_format_get_swap_rb(fb
->base
.cbufs
[0]->format
);
1474 struct lima_pp_wb_reg
*wb
= (void *)wb_reg
;
1475 wb
[wb_idx
].type
= 0x02; /* 2 for color buffer */
1476 wb
[wb_idx
].address
= res
->bo
->va
+ res
->levels
[level
].offset
;
1477 wb
[wb_idx
].pixel_format
= format
;
1479 wb
[wb_idx
].pixel_layout
= 0x2;
1480 wb
[wb_idx
].pitch
= fb
->tiled_w
;
1482 wb
[wb_idx
].pixel_layout
= 0x0;
1483 wb
[wb_idx
].pitch
= res
->levels
[level
].stride
/ 8;
1485 wb
[wb_idx
].mrt_bits
= swap_channels
? 0x4 : 0x0;
1490 lima_pack_pp_frame_reg(struct lima_context
*ctx
, uint32_t *frame_reg
,
1493 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
1494 struct lima_pp_frame_reg
*frame
= (void *)frame_reg
;
1495 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
1498 frame
->render_address
= screen
->pp_buffer
->va
+ pp_frame_rsw_offset
;
1499 frame
->flags
= 0x02;
1500 frame
->clear_value_depth
= ctx
->clear
.depth
;
1501 frame
->clear_value_stencil
= ctx
->clear
.stencil
;
1502 frame
->clear_value_color
= ctx
->clear
.color_8pc
;
1503 frame
->clear_value_color_1
= ctx
->clear
.color_8pc
;
1504 frame
->clear_value_color_2
= ctx
->clear
.color_8pc
;
1505 frame
->clear_value_color_3
= ctx
->clear
.color_8pc
;
1508 frame
->width
= fb
->base
.width
- 1;
1509 frame
->height
= fb
->base
.height
- 1;
1511 /* frame->fragment_stack_address is overwritten per-pp in the kernel
1512 * by the values of pp_frame.fragment_stack_address[i] */
1514 /* These are "stack size" and "stack offset" shifted,
1515 * here they are assumed to be always the same. */
1516 uint32_t fs_stack_size
= ctx
->fs
? ctx
->fs
->stack_size
: 0;
1517 frame
->fragment_stack_size
= fs_stack_size
<< 16 | fs_stack_size
;
1519 /* related with MSAA and different value when r4p0/r7p0 */
1520 frame
->supersampled_height
= fb
->base
.height
* 2 - 1;
1521 frame
->scale
= 0xE0C;
1523 frame
->dubya
= 0x77;
1524 frame
->onscreen
= 1;
1525 frame
->blocking
= (fb
->shift_min
<< 28) | (fb
->shift_h
<< 16) | fb
->shift_w
;
1526 frame
->foureight
= 0x8888;
1528 if (fb
->base
.nr_cbufs
)
1529 lima_pack_wb_cbuf_reg(ctx
, wb_reg
, wb_idx
++);
1531 /* Mali4x0 can use on-tile buffer for depth/stencil, so to save some
1532 * memory bandwidth don't write depth/stencil back to memory if we're
1533 * rendering to scanout
1535 if (!lima_is_scanout(ctx
) && fb
->base
.zsbuf
)
1536 lima_pack_wb_zsbuf_reg(ctx
, wb_reg
, wb_idx
++);
1540 _lima_flush(struct lima_context
*ctx
, bool end_of_frame
)
1542 #define pp_stack_pp_size 0x400
1544 lima_finish_plbu_cmd(ctx
);
1546 int vs_cmd_size
= ctx
->vs_cmd_array
.size
;
1547 int plbu_cmd_size
= ctx
->plbu_cmd_array
.size
;
1548 uint32_t vs_cmd_va
= 0;
1549 uint32_t plbu_cmd_va
;
1553 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_gp_vs_cmd
, vs_cmd_size
, true);
1554 memcpy(vs_cmd
, util_dynarray_begin(&ctx
->vs_cmd_array
), vs_cmd_size
);
1555 util_dynarray_clear(&ctx
->vs_cmd_array
);
1556 vs_cmd_va
= lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_vs_cmd
,
1557 LIMA_CTX_BUFF_SUBMIT_GP
);
1559 lima_dump_command_stream_print(
1560 vs_cmd
, vs_cmd_size
, false, "flush vs cmd at va %x\n", vs_cmd_va
);
1564 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_gp_plbu_cmd
, plbu_cmd_size
, true);
1565 memcpy(plbu_cmd
, util_dynarray_begin(&ctx
->plbu_cmd_array
), plbu_cmd_size
);
1566 util_dynarray_clear(&ctx
->plbu_cmd_array
);
1567 plbu_cmd_va
= lima_ctx_buff_va(ctx
, lima_ctx_buff_gp_plbu_cmd
,
1568 LIMA_CTX_BUFF_SUBMIT_GP
);
1570 lima_dump_command_stream_print(
1571 plbu_cmd
, plbu_cmd_size
, false, "flush plbu cmd at va %x\n", plbu_cmd_va
);
1573 struct lima_screen
*screen
= lima_screen(ctx
->base
.screen
);
1574 struct drm_lima_gp_frame gp_frame
;
1575 struct lima_gp_frame_reg
*gp_frame_reg
= (void *)gp_frame
.frame
;
1576 gp_frame_reg
->vs_cmd_start
= vs_cmd_va
;
1577 gp_frame_reg
->vs_cmd_end
= vs_cmd_va
+ vs_cmd_size
;
1578 gp_frame_reg
->plbu_cmd_start
= plbu_cmd_va
;
1579 gp_frame_reg
->plbu_cmd_end
= plbu_cmd_va
+ plbu_cmd_size
;
1580 gp_frame_reg
->tile_heap_start
= ctx
->gp_tile_heap
[ctx
->plb_index
]->va
;
1581 gp_frame_reg
->tile_heap_end
= ctx
->gp_tile_heap
[ctx
->plb_index
]->va
+ gp_tile_heap_size
;
1583 lima_dump_command_stream_print(
1584 &gp_frame
, sizeof(gp_frame
), false, "add gp frame\n");
1586 if (!lima_submit_start(ctx
->gp_submit
, &gp_frame
, sizeof(gp_frame
)))
1587 fprintf(stderr
, "gp submit error\n");
1589 if (lima_dump_command_stream
) {
1590 if (lima_submit_wait(ctx
->gp_submit
, PIPE_TIMEOUT_INFINITE
)) {
1591 if (ctx
->buffer_state
[lima_ctx_buff_sh_gl_pos
].res
) {
1592 float *pos
= lima_ctx_buff_map(ctx
, lima_ctx_buff_sh_gl_pos
);
1593 lima_dump_command_stream_print(
1594 pos
, 4 * 4 * 16, true, "gl_pos dump at va %x\n",
1595 lima_ctx_buff_va(ctx
, lima_ctx_buff_sh_gl_pos
, 0));
1598 uint32_t *plb
= lima_bo_map(ctx
->plb
[ctx
->plb_index
]);
1599 lima_dump_command_stream_print(
1600 plb
, LIMA_CTX_PLB_BLK_SIZE
, false, "plb dump at va %x\n",
1601 ctx
->plb
[ctx
->plb_index
]->va
);
1604 fprintf(stderr
, "gp submit wait error\n");
1609 uint32_t pp_stack_va
= 0;
1610 if (ctx
->pp_max_stack_size
) {
1611 lima_ctx_buff_alloc(ctx
, lima_ctx_buff_pp_stack
, screen
->num_pp
*
1612 ctx
->pp_max_stack_size
* pp_stack_pp_size
, true);
1613 pp_stack_va
= lima_ctx_buff_va(ctx
, lima_ctx_buff_pp_stack
,
1614 LIMA_CTX_BUFF_SUBMIT_PP
);
1617 struct lima_pp_stream_state
*ps
= &ctx
->pp_stream
;
1618 if (screen
->gpu_type
== DRM_LIMA_PARAM_GPU_ID_MALI400
) {
1619 struct drm_lima_m400_pp_frame pp_frame
= {0};
1620 lima_pack_pp_frame_reg(ctx
, pp_frame
.frame
, pp_frame
.wb
);
1621 pp_frame
.num_pp
= screen
->num_pp
;
1623 for (int i
= 0; i
< screen
->num_pp
; i
++) {
1624 pp_frame
.plbu_array_address
[i
] = ps
->bo
->va
+ ps
->bo_offset
+ ps
->offset
[i
];
1625 if (ctx
->pp_max_stack_size
)
1626 pp_frame
.fragment_stack_address
[i
] = pp_stack_va
+
1627 ctx
->pp_max_stack_size
* pp_stack_pp_size
* i
;
1630 lima_dump_command_stream_print(
1631 &pp_frame
, sizeof(pp_frame
), false, "add pp frame\n");
1633 if (!lima_submit_start(ctx
->pp_submit
, &pp_frame
, sizeof(pp_frame
)))
1634 fprintf(stderr
, "pp submit error\n");
1637 struct drm_lima_m450_pp_frame pp_frame
= {0};
1638 lima_pack_pp_frame_reg(ctx
, pp_frame
.frame
, pp_frame
.wb
);
1639 pp_frame
.num_pp
= screen
->num_pp
;
1641 if (ctx
->pp_max_stack_size
)
1642 for (int i
= 0; i
< screen
->num_pp
; i
++)
1643 pp_frame
.fragment_stack_address
[i
] = pp_stack_va
+
1644 ctx
->pp_max_stack_size
* pp_stack_pp_size
* i
;
1647 for (int i
= 0; i
< screen
->num_pp
; i
++)
1648 pp_frame
.plbu_array_address
[i
] = ps
->bo
->va
+ ps
->bo_offset
+ ps
->offset
[i
];
1651 pp_frame
.use_dlbu
= true;
1653 struct lima_context_framebuffer
*fb
= &ctx
->framebuffer
;
1654 pp_frame
.dlbu_regs
[0] = ctx
->plb
[ctx
->plb_index
]->va
;
1655 pp_frame
.dlbu_regs
[1] = ((fb
->tiled_h
- 1) << 16) | (fb
->tiled_w
- 1);
1656 unsigned s
= util_logbase2(LIMA_CTX_PLB_BLK_SIZE
) - 7;
1657 pp_frame
.dlbu_regs
[2] = (s
<< 28) | (fb
->shift_h
<< 16) | fb
->shift_w
;
1658 pp_frame
.dlbu_regs
[3] = ((fb
->tiled_h
- 1) << 24) | ((fb
->tiled_w
- 1) << 16);
1661 lima_dump_command_stream_print(
1662 &pp_frame
, sizeof(pp_frame
), false, "add pp frame\n");
1664 if (!lima_submit_start(ctx
->pp_submit
, &pp_frame
, sizeof(pp_frame
)))
1665 fprintf(stderr
, "pp submit error\n");
1668 if (lima_dump_command_stream
) {
1669 if (!lima_submit_wait(ctx
->pp_submit
, PIPE_TIMEOUT_INFINITE
)) {
1670 fprintf(stderr
, "pp wait error\n");
1675 ctx
->plb_index
= (ctx
->plb_index
+ 1) % lima_ctx_num_plb
;
1677 if (ctx
->framebuffer
.base
.nr_cbufs
) {
1678 /* Set reload flag for next draw. It'll be unset if buffer is cleared */
1679 struct lima_surface
*surf
= lima_surface(ctx
->framebuffer
.base
.cbufs
[0]);
1680 surf
->reload
= true;
1683 ctx
->pp_max_stack_size
= 0;
1687 lima_flush(struct lima_context
*ctx
)
1689 if (!lima_ctx_dirty(ctx
))
1692 _lima_flush(ctx
, false);
1696 lima_pipe_flush(struct pipe_context
*pctx
, struct pipe_fence_handle
**fence
,
1699 struct lima_context
*ctx
= lima_context(pctx
);
1700 if (lima_ctx_dirty(ctx
))
1701 _lima_flush(ctx
, flags
& PIPE_FLUSH_END_OF_FRAME
);
1705 if (lima_submit_get_out_sync(ctx
->pp_submit
, &fd
))
1706 *fence
= lima_fence_create(fd
);
1711 lima_draw_init(struct lima_context
*ctx
)
1713 ctx
->base
.clear
= lima_clear
;
1714 ctx
->base
.draw_vbo
= lima_draw_vbo
;
1715 ctx
->base
.flush
= lima_pipe_flush
;