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gallium: add lima driver
[mesa.git] / src / gallium / drivers / lima / lima_draw.c
1 /*
2 * Copyright (c) 2011-2013 Luc Verhaegen <libv@skynet.be>
3 * Copyright (c) 2017-2019 Lima Project
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "util/u_math.h"
27 #include "util/u_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_half.h"
30 #include "util/u_helpers.h"
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/hash_table.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36 #include "util/u_vbuf.h"
37
38 #include "lima_context.h"
39 #include "lima_screen.h"
40 #include "lima_resource.h"
41 #include "lima_program.h"
42 #include "lima_bo.h"
43 #include "lima_submit.h"
44 #include "lima_texture.h"
45 #include "lima_util.h"
46 #include "lima_fence.h"
47
48 #include <drm-uapi/lima_drm.h>
49
50 struct lima_gp_frame_reg {
51 uint32_t vs_cmd_start;
52 uint32_t vs_cmd_end;
53 uint32_t plbu_cmd_start;
54 uint32_t plbu_cmd_end;
55 uint32_t tile_heap_start;
56 uint32_t tile_heap_end;
57 };
58
59 struct lima_pp_frame_reg {
60 uint32_t plbu_array_address;
61 uint32_t render_address;
62 uint32_t unused_0;
63 uint32_t flags;
64 uint32_t clear_value_depth;
65 uint32_t clear_value_stencil;
66 uint32_t clear_value_color;
67 uint32_t clear_value_color_1;
68 uint32_t clear_value_color_2;
69 uint32_t clear_value_color_3;
70 uint32_t width;
71 uint32_t height;
72 uint32_t fragment_stack_address;
73 uint32_t fragment_stack_size;
74 uint32_t unused_1;
75 uint32_t unused_2;
76 uint32_t one;
77 uint32_t supersampled_height;
78 uint32_t dubya;
79 uint32_t onscreen;
80 uint32_t blocking;
81 uint32_t scale;
82 uint32_t foureight;
83 };
84
85 struct lima_pp_wb_reg {
86 uint32_t type;
87 uint32_t address;
88 uint32_t pixel_format;
89 uint32_t downsample_factor;
90 uint32_t pixel_layout;
91 uint32_t pitch;
92 uint32_t mrt_bits;
93 uint32_t mrt_pitch;
94 uint32_t zero;
95 uint32_t unused0;
96 uint32_t unused1;
97 uint32_t unused2;
98 };
99
100 struct lima_render_state {
101 uint32_t blend_color_bg;
102 uint32_t blend_color_ra;
103 uint32_t alpha_blend;
104 uint32_t depth_test;
105 uint32_t depth_range;
106 uint32_t stencil_front;
107 uint32_t stencil_back;
108 uint32_t stencil_test;
109 uint32_t multi_sample;
110 uint32_t shader_address;
111 uint32_t varying_types;
112 uint32_t uniforms_address;
113 uint32_t textures_address;
114 uint32_t aux0;
115 uint32_t aux1;
116 uint32_t varyings_address;
117 };
118
119 /* plbu commands */
120 #define PLBU_CMD_BEGIN(max) { \
121 int i = 0, max_n = max; \
122 uint32_t *plbu_cmd = util_dynarray_grow_cap(&ctx->plbu_cmd_array, max_n * 4);
123
124 #define PLBU_CMD_END() \
125 assert(i <= max_n); \
126 ctx->plbu_cmd_array.size += i * 4; \
127 }
128
129 #define PLBU_CMD(v1, v2) \
130 do { \
131 plbu_cmd[i++] = v1; \
132 plbu_cmd[i++] = v2; \
133 } while (0)
134
135 #define PLBU_CMD_BLOCK_STEP(shift_min, shift_h, shift_w) \
136 PLBU_CMD(((shift_min) << 28) | ((shift_h) << 16) | (shift_w), 0x1000010C)
137 #define PLBU_CMD_TILED_DIMENSIONS(tiled_w, tiled_h) \
138 PLBU_CMD((((tiled_w) - 1) << 24) | (((tiled_h) - 1) << 8), 0x10000109)
139 #define PLBU_CMD_BLOCK_STRIDE(block_w) PLBU_CMD(block_w, 0x30000000)
140 #define PLBU_CMD_ARRAY_ADDRESS(gp_stream, block_num) \
141 PLBU_CMD(gp_stream, 0x28000000 | ((block_num) - 1) | 1)
142 #define PLBU_CMD_VIEWPORT_X(v) PLBU_CMD(v, 0x10000107)
143 #define PLBU_CMD_VIEWPORT_W(v) PLBU_CMD(v, 0x10000108)
144 #define PLBU_CMD_VIEWPORT_Y(v) PLBU_CMD(v, 0x10000105)
145 #define PLBU_CMD_VIEWPORT_H(v) PLBU_CMD(v, 0x10000106)
146 #define PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN() PLBU_CMD(0x00010002, 0x60000000)
147 #define PLBU_CMD_ARRAYS_SEMAPHORE_END() PLBU_CMD(0x00010001, 0x60000000)
148 #define PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, index_size) \
149 PLBU_CMD(((low_prim) ? 0x00003200 : 0x00002200) | (cull) | ((index_size) << 9), 0x1000010B)
150 #define PLBU_CMD_RSW_VERTEX_ARRAY(rsw, gl_pos) \
151 PLBU_CMD(rsw, 0x80000000 | ((gl_pos) >> 4))
152 #define PLBU_CMD_SCISSORS(minx, maxx, miny, maxy) \
153 PLBU_CMD(((minx) << 30) | ((maxy) - 1) << 15 | (miny), \
154 0x70000000 | ((maxx) - 1) << 13 | ((minx) >> 2))
155 #define PLBU_CMD_UNKNOWN1() PLBU_CMD(0x00000000, 0x1000010A)
156 #define PLBU_CMD_UNKNOWN2() PLBU_CMD(0x00000200, 0x1000010B)
157 #define PLBU_CMD_LOW_PRIM_SIZE(v) PLBU_CMD(v, 0x1000010D)
158 #define PLBU_CMD_DEPTH_RANGE_NEAR(v) PLBU_CMD(v, 0x1000010E)
159 #define PLBU_CMD_DEPTH_RANGE_FAR(v) PLBU_CMD(v, 0x1000010F)
160 #define PLBU_CMD_INDEXED_DEST(gl_pos) PLBU_CMD(gl_pos, 0x10000100)
161 #define PLBU_CMD_INDICES(va) PLBU_CMD(va, 0x10000101)
162 #define PLBU_CMD_DRAW_ARRAYS(mode, start, count) \
163 PLBU_CMD(((count) << 24) | (start), (((mode) & 0x1F) << 16) | ((count) >> 8))
164 #define PLBU_CMD_DRAW_ELEMENTS(mode, start, count) \
165 PLBU_CMD(((count) << 24) | (start), \
166 0x00200000 | (((mode) & 0x1F) << 16) | ((count) >> 8))
167
168 /* vs commands */
169 #define VS_CMD_BEGIN(max) { \
170 int i = 0, max_n = max; \
171 uint32_t *vs_cmd = util_dynarray_grow_cap(&ctx->vs_cmd_array, max_n * 4);
172
173 #define VS_CMD_END() \
174 assert(i <= max_n); \
175 ctx->vs_cmd_array.size += i * 4; \
176 }
177
178 #define VS_CMD(v1, v2) \
179 do { \
180 vs_cmd[i++] = v1; \
181 vs_cmd[i++] = v2; \
182 } while (0)
183
184 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1() VS_CMD(0x00028000, 0x50000000)
185 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2() VS_CMD(0x00000001, 0x50000000)
186 #define VS_CMD_ARRAYS_SEMAPHORE_END(index_draw) \
187 VS_CMD((index_draw) ? 0x00018000 : 0x00000000, 0x50000000)
188 #define VS_CMD_UNIFORMS_ADDRESS(addr, size) \
189 VS_CMD(addr, 0x30000000 | ((size) << 12))
190 #define VS_CMD_SHADER_ADDRESS(addr, size) \
191 VS_CMD(addr, 0x40000000 | ((size) << 12))
192 #define VS_CMD_SHADER_INFO(prefetch, size) \
193 VS_CMD(((prefetch) << 20) | ((((size) >> 4) - 1) << 10), 0x10000040)
194 #define VS_CMD_VARYING_ATTRIBUTE_COUNT(nv, na) \
195 VS_CMD((((nv) - 1) << 8) | (((na) - 1) << 24), 0x10000042)
196 #define VS_CMD_UNKNOWN1() VS_CMD(0x00000003, 0x10000041)
197 #define VS_CMD_UNKNOWN2() VS_CMD(0x00000000, 0x60000000)
198 #define VS_CMD_ATTRIBUTES_ADDRESS(addr, na) \
199 VS_CMD(addr, 0x20000000 | ((na) << 17))
200 #define VS_CMD_VARYINGS_ADDRESS(addr, nv) \
201 VS_CMD(addr, 0x20000008 | ((nv) << 17))
202 #define VS_CMD_DRAW(num, index_draw) \
203 VS_CMD(((num) << 24) | ((index_draw) ? 1 : 0), ((num) >> 8))
204
205 static inline bool
206 lima_ctx_dirty(struct lima_context *ctx)
207 {
208 return ctx->plbu_cmd_array.size;
209 }
210
211 static bool
212 lima_fb_need_reload(struct lima_context *ctx)
213 {
214 if (ctx->damage.region) {
215 /* for EGL_KHR_partial_update we just want to reload the
216 * region not aligned to tile boundary */
217 if (!ctx->damage.aligned)
218 return true;
219 }
220 else {
221 struct lima_surface *surf = lima_surface(ctx->framebuffer.cbuf);
222 if (surf->reload)
223 return true;
224 }
225
226 return false;
227 }
228
229 static void
230 lima_pack_reload_plbu_cmd(struct lima_context *ctx)
231 {
232 #define lima_reload_render_state_offset 0x0000
233 #define lima_reload_gl_pos_offset 0x0040
234 #define lima_reload_varying_offset 0x0080
235 #define lima_reload_tex_desc_offset 0x00c0
236 #define lima_reload_tex_array_offset 0x0100
237 #define lima_reload_buffer_size 0x0140
238
239 void *cpu;
240 unsigned offset;
241 struct pipe_resource *pres = NULL;
242 u_upload_alloc(ctx->uploader, 0, lima_reload_buffer_size,
243 0x40, &offset, &pres, &cpu);
244
245 struct lima_resource *res = lima_resource(pres);
246 uint32_t va = res->bo->va + offset;
247
248 struct lima_screen *screen = lima_screen(ctx->base.screen);
249
250 uint32_t reload_shader_first_instr_size =
251 ((uint32_t *)(screen->pp_buffer->map + pp_reload_program_offset))[0] & 0x1f;
252 uint32_t reload_shader_va = screen->pp_buffer->va + pp_reload_program_offset;
253
254 struct lima_render_state reload_render_state = {
255 .alpha_blend = 0xf03b1ad2,
256 .depth_test = 0x0000000e,
257 .depth_range = 0xffff0000,
258 .stencil_front = 0x00000007,
259 .stencil_back = 0x00000007,
260 .multi_sample = 0x0000f007,
261 .shader_address = reload_shader_va | reload_shader_first_instr_size,
262 .varying_types = 0x00000001,
263 .textures_address = va + lima_reload_tex_array_offset,
264 .aux0 = 0x00004021,
265 .varyings_address = va + lima_reload_varying_offset,
266 };
267 memcpy(cpu + lima_reload_render_state_offset, &reload_render_state,
268 sizeof(reload_render_state));
269
270 struct lima_context_framebuffer *fb = &ctx->framebuffer;
271 uint32_t *td = cpu + lima_reload_tex_desc_offset;
272 memset(td, 0, lima_tex_desc_size);
273 lima_texture_desc_set_res(ctx, td, fb->cbuf->texture, 0, 0);
274 td[1] = 0x00000480;
275 td[2] |= 0x00093800;
276 td[4] = 0x00000000;
277 td[5] = 0x00000000;
278
279 uint32_t *ta = cpu + lima_reload_tex_array_offset;
280 ta[0] = va + lima_reload_tex_desc_offset;
281
282 float reload_gl_pos[] = {
283 fb->width, 0, 0, 1,
284 0, 0, 0, 1,
285 0, fb->height, 0, 1,
286 };
287 memcpy(cpu + lima_reload_gl_pos_offset, reload_gl_pos,
288 sizeof(reload_gl_pos));
289
290 float reload_varying[] = {
291 fb->width, 0, 0, 0,
292 0, fb->height, 0, 0,
293 };
294 memcpy(cpu + lima_reload_varying_offset, reload_varying,
295 sizeof(reload_varying));
296
297 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
298 pipe_resource_reference(&pres, NULL);
299
300 PLBU_CMD_BEGIN(20);
301
302 PLBU_CMD_VIEWPORT_X(0);
303 PLBU_CMD_VIEWPORT_W(fui(fb->width));
304 PLBU_CMD_VIEWPORT_Y(0);
305 PLBU_CMD_VIEWPORT_H(fui(fb->height));
306
307 PLBU_CMD_RSW_VERTEX_ARRAY(
308 va + lima_reload_render_state_offset,
309 va + lima_reload_gl_pos_offset);
310
311 PLBU_CMD_UNKNOWN2();
312 PLBU_CMD_UNKNOWN1();
313
314 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
315 PLBU_CMD_INDEXED_DEST(va + lima_reload_gl_pos_offset);
316 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
317
318 PLBU_CMD_END();
319 }
320
321 static void
322 lima_pack_clear_plbu_cmd(struct lima_context *ctx)
323 {
324 #define lima_clear_render_state_offset 0x0000
325 #define lima_clear_shader_offset 0x0040
326 #define lima_clear_buffer_size 0x0080
327
328 void *cpu;
329 unsigned offset;
330 struct pipe_resource *pres = NULL;
331 u_upload_alloc(ctx->uploader, 0, lima_clear_buffer_size,
332 0x40, &offset, &pres, &cpu);
333
334 struct lima_resource *res = lima_resource(pres);
335 uint32_t va = res->bo->va + offset;
336
337 struct lima_screen *screen = lima_screen(ctx->base.screen);
338 uint32_t gl_pos_va = screen->pp_buffer->va + pp_clear_gl_pos_offset;
339
340 /* const0 clear_color, mov.v1 $0 ^const0.xxxx, stop */
341 uint32_t clear_shader[] = {
342 0x00021025, 0x0000000c,
343 (ctx->clear.color_16pc << 12) | 0x000007cf,
344 ctx->clear.color_16pc >> 12,
345 ctx->clear.color_16pc >> 44,
346 };
347 memcpy(cpu + lima_clear_shader_offset, &clear_shader,
348 sizeof(clear_shader));
349
350 uint32_t clear_shader_va = va + lima_clear_shader_offset;
351 uint32_t clear_shader_first_instr_size = clear_shader[0] & 0x1f;
352
353 struct lima_render_state clear_render_state = {
354 .blend_color_bg = 0x00800080,
355 .blend_color_ra = 0x00ff0080,
356 .alpha_blend = 0xfc321892,
357 .depth_test = 0x0000003e,
358 .depth_range = 0xffff0000,
359 .stencil_front = 0x00000007,
360 .stencil_back = 0x00000007,
361 .multi_sample = 0x0000f007,
362 .shader_address = clear_shader_va | clear_shader_first_instr_size,
363 };
364 memcpy(cpu + lima_clear_render_state_offset, &clear_render_state,
365 sizeof(clear_render_state));
366
367 PLBU_CMD_BEGIN(22);
368
369 PLBU_CMD_VIEWPORT_X(0);
370 PLBU_CMD_VIEWPORT_W(0x45800000);
371 PLBU_CMD_VIEWPORT_Y(0);
372 PLBU_CMD_VIEWPORT_H(0x45800000);
373
374 struct pipe_scissor_state *scissor = &ctx->scissor;
375 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
376
377 PLBU_CMD_RSW_VERTEX_ARRAY(va + lima_clear_render_state_offset, gl_pos_va);
378
379 PLBU_CMD_UNKNOWN2();
380 PLBU_CMD_UNKNOWN1();
381
382 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
383 PLBU_CMD_INDEXED_DEST(gl_pos_va);
384 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
385
386 PLBU_CMD_END();
387 }
388
389 static void
390 lima_pack_head_plbu_cmd(struct lima_context *ctx)
391 {
392 /* first draw need create a PLBU command header */
393 if (lima_ctx_dirty(ctx))
394 return;
395
396 struct lima_context_framebuffer *fb = &ctx->framebuffer;
397
398 PLBU_CMD_BEGIN(10);
399
400 PLBU_CMD_UNKNOWN2();
401 PLBU_CMD_BLOCK_STEP(fb->shift_min, fb->shift_h, fb->shift_w);
402 PLBU_CMD_TILED_DIMENSIONS(fb->tiled_w, fb->tiled_h);
403 PLBU_CMD_BLOCK_STRIDE(fb->block_w);
404
405 PLBU_CMD_ARRAY_ADDRESS(
406 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size,
407 fb->block_w * fb->block_h);
408
409 PLBU_CMD_END();
410
411 if (lima_fb_need_reload(ctx))
412 lima_pack_reload_plbu_cmd(ctx);
413 }
414
415 static bool
416 lima_is_scissor_zero(struct lima_context *ctx)
417 {
418 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
419 return false;
420
421 struct pipe_scissor_state *scissor = &ctx->scissor;
422 return
423 scissor->minx == scissor->maxx
424 && scissor->miny == scissor->maxy;
425 }
426
427 static bool
428 lima_is_scissor_full_fb(struct lima_context *ctx)
429 {
430 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
431 return true;
432
433 struct pipe_scissor_state *scissor = &ctx->scissor;
434 struct lima_context_framebuffer *fb = &ctx->framebuffer;
435 return
436 scissor->minx == 0 && scissor->maxx == fb->width &&
437 scissor->miny == 0 && scissor->maxy == fb->height;
438 }
439
440 static void
441 hilbert_rotate(int n, int *x, int *y, int rx, int ry)
442 {
443 if (ry == 0) {
444 if (rx == 1) {
445 *x = n-1 - *x;
446 *y = n-1 - *y;
447 }
448
449 /* Swap x and y */
450 int t = *x;
451 *x = *y;
452 *y = t;
453 }
454 }
455
456 static void
457 hilbert_coords(int n, int d, int *x, int *y)
458 {
459 int rx, ry, i, t=d;
460
461 *x = *y = 0;
462
463 for (i = 0; (1 << i) < n; i++) {
464
465 rx = 1 & (t / 2);
466 ry = 1 & (t ^ rx);
467
468 hilbert_rotate(1 << i, x, y, rx, ry);
469
470 *x += rx << i;
471 *y += ry << i;
472
473 t /= 4;
474 }
475 }
476
477 static int
478 lima_get_pp_stream_size(int num_pp, int tiled_w, int tiled_h, uint32_t *off)
479 {
480 /* carefully calculate each stream start address:
481 * 1. overflow: each stream size may be different due to
482 * fb->tiled_w * fb->tiled_h can't be divided by num_pp,
483 * extra size should be added to the preceeding stream
484 * 2. alignment: each stream address should be 0x20 aligned
485 */
486 int delta = tiled_w * tiled_h / num_pp * 16 + 8;
487 int remain = tiled_w * tiled_h % num_pp;
488 int offset = 0;
489
490 for (int i = 0; i < num_pp; i++) {
491 off[i] = offset;
492
493 offset += delta;
494 if (remain) {
495 offset += 16;
496 remain--;
497 }
498 offset = align(offset, 0x20);
499 }
500
501 return offset;
502 }
503
504 static bool
505 inside_damage_region(int x, int y, struct lima_damage_state *ds)
506 {
507 if (!ds->region)
508 return true;
509
510 for (int i = 0; i < ds->num_region; i++) {
511 struct pipe_scissor_state *ss = ds->region + i;
512 if (x >= ss->minx && x < ss->maxx &&
513 y >= ss->miny && y < ss->maxy)
514 return true;
515 }
516
517 return false;
518 }
519
520 static void
521 lima_update_pp_stream(struct lima_context *ctx, int off_x, int off_y,
522 int tiled_w, int tiled_h)
523 {
524 struct lima_pp_stream_state *ps = &ctx->pp_stream;
525 struct lima_context_framebuffer *fb = &ctx->framebuffer;
526 struct lima_screen *screen = lima_screen(ctx->base.screen);
527 int i, num_pp = screen->num_pp;
528
529 /* use hilbert_coords to generates 1D to 2D relationship.
530 * 1D for pp stream index and 2D for plb block x/y on framebuffer.
531 * if multi pp, interleave the 1D index to make each pp's render target
532 * close enough which should result close workload
533 */
534 int max = MAX2(tiled_w, tiled_h);
535 int dim = util_logbase2_ceil(max);
536 int count = 1 << (dim + dim);
537 int index = 0;
538 uint32_t *stream[4];
539 int si[4] = {0};
540
541 for (i = 0; i < num_pp; i++)
542 stream[i] = ps->bo->map + ps->bo_offset + ps->offset[i];
543
544 for (i = 0; i < count; i++) {
545 int x, y;
546 hilbert_coords(max, i, &x, &y);
547 if (x < tiled_w && y < tiled_h) {
548 x += off_x;
549 y += off_y;
550
551 if (!inside_damage_region(x, y, &ctx->damage))
552 continue;
553
554 int pp = index % num_pp;
555 int offset = ((y >> fb->shift_h) * fb->block_w +
556 (x >> fb->shift_w)) * LIMA_CTX_PLB_BLK_SIZE;
557 int plb_va = ctx->plb[ctx->plb_index]->va + offset;
558
559 stream[pp][si[pp]++] = 0;
560 stream[pp][si[pp]++] = 0xB8000000 | x | (y << 8);
561 stream[pp][si[pp]++] = 0xE0000002 | ((plb_va >> 3) & ~0xE0000003);
562 stream[pp][si[pp]++] = 0xB0000000;
563
564 index++;
565 }
566 }
567
568 for (i = 0; i < num_pp; i++) {
569 stream[i][si[i]++] = 0;
570 stream[i][si[i]++] = 0xBC000000;
571
572 lima_dump_command_stream_print(
573 stream[i], si[i] * 4, false, "pp plb stream %d at va %x\n",
574 i, ps->bo->va + ps->bo_offset + ps->offset[i]);
575 }
576 }
577
578 static void
579 lima_update_damage_pp_stream(struct lima_context *ctx)
580 {
581 struct lima_damage_state *ds = &ctx->damage;
582 struct pipe_scissor_state max = ds->region[0];
583
584 /* find a max region to cover all the damage region */
585 for (int i = 1; i < ds->num_region; i++) {
586 struct pipe_scissor_state *ss = ds->region + i;
587 max.minx = MIN2(max.minx, ss->minx);
588 max.miny = MIN2(max.miny, ss->miny);
589 max.maxx = MAX2(max.maxx, ss->maxx);
590 max.maxy = MAX2(max.maxy, ss->maxy);
591 }
592
593 int tiled_w = max.maxx - max.minx;
594 int tiled_h = max.maxy - max.miny;
595 struct lima_screen *screen = lima_screen(ctx->base.screen);
596 int size = lima_get_pp_stream_size(
597 screen->num_pp, tiled_w, tiled_h, ctx->pp_stream.offset);
598
599 void *cpu;
600 unsigned offset;
601 struct pipe_resource *pres = NULL;
602 u_upload_alloc(ctx->uploader, 0, size, 0x40, &offset, &pres, &cpu);
603
604 struct lima_resource *res = lima_resource(pres);
605 ctx->pp_stream.bo = res->bo;
606 ctx->pp_stream.bo_offset = offset;
607
608 lima_update_pp_stream(ctx, max.minx, max.miny, tiled_w, tiled_h);
609
610 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
611 pipe_resource_reference(&pres, NULL);
612 }
613
614 static void
615 lima_update_full_pp_stream(struct lima_context *ctx)
616 {
617 struct lima_context_framebuffer *fb = &ctx->framebuffer;
618 struct lima_ctx_plb_pp_stream_key key = {
619 .plb_index = ctx->plb_index,
620 .tiled_w = fb->tiled_w,
621 .tiled_h = fb->tiled_h,
622 };
623
624 struct hash_entry *entry =
625 _mesa_hash_table_search(ctx->plb_pp_stream, &key);
626 struct lima_ctx_plb_pp_stream *s = entry->data;
627
628 if (s->bo) {
629 ctx->pp_stream.bo = s->bo;
630 ctx->pp_stream.bo_offset = 0;
631 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
632 }
633 else {
634 struct lima_screen *screen = lima_screen(ctx->base.screen);
635 int size = lima_get_pp_stream_size(
636 screen->num_pp, fb->tiled_w, fb->tiled_h, s->offset);
637 s->bo = lima_bo_create(screen, size, 0);
638 lima_bo_map(s->bo);
639
640 ctx->pp_stream.bo = s->bo;
641 ctx->pp_stream.bo_offset = 0;
642 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
643
644 lima_update_pp_stream(ctx, 0, 0, fb->tiled_w, fb->tiled_h);
645 }
646
647 lima_submit_add_bo(ctx->pp_submit, s->bo, LIMA_SUBMIT_BO_READ);
648 }
649
650 static void
651 lima_update_submit_bo(struct lima_context *ctx)
652 {
653 if (lima_ctx_dirty(ctx))
654 return;
655
656 struct lima_screen *screen = lima_screen(ctx->base.screen);
657 lima_submit_add_bo(ctx->gp_submit, ctx->plb_gp_stream, LIMA_SUBMIT_BO_READ);
658 lima_submit_add_bo(ctx->gp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
659 lima_submit_add_bo(ctx->gp_submit, screen->gp_buffer, LIMA_SUBMIT_BO_READ);
660
661 lima_dump_command_stream_print(
662 ctx->plb_gp_stream->map + ctx->plb_index * ctx->plb_gp_size,
663 ctx->plb_gp_size, false, "gp plb stream at va %x\n",
664 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size);
665
666 if (ctx->damage.region)
667 lima_update_damage_pp_stream(ctx);
668 else if (ctx->plb_pp_stream)
669 lima_update_full_pp_stream(ctx);
670 else
671 ctx->pp_stream.bo = NULL;
672
673 struct lima_resource *res = lima_resource(ctx->framebuffer.cbuf->texture);
674 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
675 lima_submit_add_bo(ctx->pp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_READ);
676 lima_submit_add_bo(ctx->pp_submit, screen->pp_buffer, LIMA_SUBMIT_BO_READ);
677 }
678
679 static void
680 lima_clear(struct pipe_context *pctx, unsigned buffers,
681 const union pipe_color_union *color, double depth, unsigned stencil)
682 {
683 struct lima_context *ctx = lima_context(pctx);
684 bool full_fb_clear = lima_is_scissor_full_fb(ctx);
685
686 if (full_fb_clear) {
687 lima_flush(ctx);
688
689 /* no need to reload if cleared */
690 if (buffers & PIPE_CLEAR_COLOR0) {
691 struct lima_surface *surf = lima_surface(ctx->framebuffer.cbuf);
692 surf->reload = false;
693 }
694 }
695
696 struct lima_context_clear *clear = &ctx->clear;
697 clear->buffers = buffers;
698
699 if (buffers & PIPE_CLEAR_COLOR0) {
700 clear->color_8pc =
701 ((uint32_t)float_to_ubyte(color->f[3]) << 24) |
702 ((uint32_t)float_to_ubyte(color->f[2]) << 16) |
703 ((uint32_t)float_to_ubyte(color->f[1]) << 8) |
704 float_to_ubyte(color->f[0]);
705
706 clear->color_16pc =
707 ((uint64_t)float_to_ushort(color->f[3]) << 48) |
708 ((uint64_t)float_to_ushort(color->f[2]) << 32) |
709 ((uint64_t)float_to_ushort(color->f[1]) << 16) |
710 float_to_ushort(color->f[0]);
711 }
712
713 if (buffers & PIPE_CLEAR_DEPTH)
714 clear->depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
715
716 if (buffers & PIPE_CLEAR_STENCIL)
717 clear->stencil = stencil;
718
719 lima_update_submit_bo(ctx);
720
721 lima_pack_head_plbu_cmd(ctx);
722
723 /* partial clear */
724 if (!full_fb_clear)
725 lima_pack_clear_plbu_cmd(ctx);
726
727 ctx->dirty |= LIMA_CONTEXT_DIRTY_CLEAR;
728 }
729
730 enum lima_attrib_type {
731 LIMA_ATTRIB_FLOAT = 0x000,
732 /* todo: find out what lives here. */
733 LIMA_ATTRIB_I16 = 0x004,
734 LIMA_ATTRIB_U16 = 0x005,
735 LIMA_ATTRIB_I8 = 0x006,
736 LIMA_ATTRIB_U8 = 0x007,
737 LIMA_ATTRIB_I8N = 0x008,
738 LIMA_ATTRIB_U8N = 0x009,
739 LIMA_ATTRIB_I16N = 0x00A,
740 LIMA_ATTRIB_U16N = 0x00B,
741 /* todo: where is the 32 int */
742 /* todo: find out what lives here. */
743 LIMA_ATTRIB_FIXED = 0x101
744 };
745
746 static enum lima_attrib_type
747 lima_pipe_format_to_attrib_type(enum pipe_format format)
748 {
749 const struct util_format_description *desc = util_format_description(format);
750 int i = util_format_get_first_non_void_channel(format);
751 const struct util_format_channel_description *c = desc->channel + i;
752
753 switch (c->type) {
754 case UTIL_FORMAT_TYPE_FLOAT:
755 return LIMA_ATTRIB_FLOAT;
756 case UTIL_FORMAT_TYPE_FIXED:
757 return LIMA_ATTRIB_FIXED;
758 case UTIL_FORMAT_TYPE_SIGNED:
759 if (c->size == 8) {
760 if (c->normalized)
761 return LIMA_ATTRIB_I8N;
762 else
763 return LIMA_ATTRIB_I8;
764 }
765 else if (c->size == 16) {
766 if (c->normalized)
767 return LIMA_ATTRIB_I16N;
768 else
769 return LIMA_ATTRIB_I16;
770 }
771 break;
772 case UTIL_FORMAT_TYPE_UNSIGNED:
773 if (c->size == 8) {
774 if (c->normalized)
775 return LIMA_ATTRIB_U8N;
776 else
777 return LIMA_ATTRIB_U8;
778 }
779 else if (c->size == 16) {
780 if (c->normalized)
781 return LIMA_ATTRIB_U16N;
782 else
783 return LIMA_ATTRIB_U16;
784 }
785 break;
786 }
787
788 return LIMA_ATTRIB_FLOAT;
789 }
790
791 static void
792 lima_pack_vs_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
793 {
794 VS_CMD_BEGIN(24);
795
796 if (!info->index_size) {
797 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1();
798 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2();
799 }
800
801 int uniform_size = ctx->vs->uniform_pending_offset + ctx->vs->constant_size + 32;
802 VS_CMD_UNIFORMS_ADDRESS(
803 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, LIMA_CTX_BUFF_SUBMIT_GP),
804 align(uniform_size, 16));
805
806 VS_CMD_SHADER_ADDRESS(ctx->vs->bo->va, ctx->vs->shader_size);
807 VS_CMD_SHADER_INFO(ctx->vs->prefetch, ctx->vs->shader_size);
808
809 int num_varryings = ctx->vs->num_varying;
810 int num_attributes = ctx->vertex_elements->num_elements;
811 VS_CMD_VARYING_ATTRIBUTE_COUNT(num_varryings, num_attributes);
812
813 VS_CMD_UNKNOWN1();
814
815 VS_CMD_ATTRIBUTES_ADDRESS(
816 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, LIMA_CTX_BUFF_SUBMIT_GP),
817 num_attributes);
818
819 VS_CMD_VARYINGS_ADDRESS(
820 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, LIMA_CTX_BUFF_SUBMIT_GP),
821 num_varryings);
822
823 unsigned num = info->index_size ? (ctx->max_index - ctx->min_index + 1) : info->count;
824 VS_CMD_DRAW(num, info->index_size);
825
826 VS_CMD_UNKNOWN2();
827
828 VS_CMD_ARRAYS_SEMAPHORE_END(info->index_size);
829
830 VS_CMD_END();
831 }
832
833 static void
834 lima_pack_plbu_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
835 {
836 lima_pack_head_plbu_cmd(ctx);
837
838 /* If it's zero scissor, we skip adding all other commands */
839 if (lima_is_scissor_zero(ctx))
840 return;
841
842 PLBU_CMD_BEGIN(30);
843
844 PLBU_CMD_VIEWPORT_X(fui(ctx->viewport.x));
845 PLBU_CMD_VIEWPORT_W(fui(ctx->viewport.width));
846 PLBU_CMD_VIEWPORT_Y(fui(ctx->viewport.y));
847 PLBU_CMD_VIEWPORT_H(fui(ctx->viewport.height));
848
849 if (!info->index_size)
850 PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN();
851
852 bool low_prim = info->mode < PIPE_PRIM_TRIANGLES;
853 int cf = ctx->rasterizer->base.cull_face;
854 int ccw = ctx->rasterizer->base.front_ccw;
855 uint32_t cull = 0;
856 if (cf != PIPE_FACE_NONE) {
857 if (cf & PIPE_FACE_FRONT)
858 cull |= ccw ? 0x00040000 : 0x00020000;
859 if (cf & PIPE_FACE_BACK)
860 cull |= ccw ? 0x00020000 : 0x00040000;
861 }
862 PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, info->index_size);
863
864 uint32_t gl_position_va =
865 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
866 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
867 PLBU_CMD_RSW_VERTEX_ARRAY(
868 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, LIMA_CTX_BUFF_SUBMIT_PP),
869 gl_position_va);
870
871 /* TODO
872 * - we should set it only for the first draw that enabled the scissor and for
873 * latter draw only if scissor is dirty
874 */
875 if (ctx->rasterizer->base.scissor) {
876 struct pipe_scissor_state *scissor = &ctx->scissor;
877 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
878 }
879
880 PLBU_CMD_UNKNOWN1();
881
882 PLBU_CMD_DEPTH_RANGE_NEAR(fui(ctx->viewport.near));
883 PLBU_CMD_DEPTH_RANGE_FAR(fui(ctx->viewport.far));
884
885 if (low_prim) {
886 uint32_t v = info->mode == PIPE_PRIM_POINTS ?
887 fui(ctx->rasterizer->base.point_size) : fui(ctx->rasterizer->base.line_width);
888 PLBU_CMD_LOW_PRIM_SIZE(v);
889 }
890
891 if (info->index_size) {
892 PLBU_CMD_INDEXED_DEST(gl_position_va);
893
894 struct pipe_resource *indexbuf = NULL;
895 unsigned index_offset = 0;
896 struct lima_resource *res;
897 if (info->has_user_indices) {
898 util_upload_index_buffer(&ctx->base, info, &indexbuf, &index_offset);
899 res = lima_resource(indexbuf);
900 }
901 else
902 res = lima_resource(info->index.resource);
903
904 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
905 PLBU_CMD_INDICES(res->bo->va + info->start * info->index_size + index_offset);
906
907 if (indexbuf)
908 pipe_resource_reference(&indexbuf, NULL);
909 }
910 else {
911 /* can this make the attribute info static? */
912 PLBU_CMD_DRAW_ARRAYS(info->mode, info->start, info->count);
913 }
914
915 PLBU_CMD_ARRAYS_SEMAPHORE_END();
916
917 if (info->index_size)
918 PLBU_CMD_DRAW_ELEMENTS(info->mode, ctx->min_index, info->count);
919
920 PLBU_CMD_END();
921 }
922
923 static int
924 lima_blend_func(enum pipe_blend_func pipe)
925 {
926 switch (pipe) {
927 case PIPE_BLEND_ADD:
928 return 2;
929 case PIPE_BLEND_SUBTRACT:
930 return 0;
931 case PIPE_BLEND_REVERSE_SUBTRACT:
932 return 1;
933 case PIPE_BLEND_MIN:
934 return 4;
935 case PIPE_BLEND_MAX:
936 return 5;
937 }
938 return -1;
939 }
940
941 static int
942 lima_blend_factor(enum pipe_blendfactor pipe)
943 {
944 switch (pipe) {
945 case PIPE_BLENDFACTOR_ONE:
946 return 11;
947 case PIPE_BLENDFACTOR_SRC_COLOR:
948 return 0;
949 case PIPE_BLENDFACTOR_SRC_ALPHA:
950 return 16;
951 case PIPE_BLENDFACTOR_DST_ALPHA:
952 return 17;
953 case PIPE_BLENDFACTOR_DST_COLOR:
954 return 1;
955 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
956 return 7;
957 case PIPE_BLENDFACTOR_CONST_COLOR:
958 return 2;
959 case PIPE_BLENDFACTOR_CONST_ALPHA:
960 return 18;
961 case PIPE_BLENDFACTOR_ZERO:
962 return 3;
963 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
964 return 8;
965 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
966 return 24;
967 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
968 return 25;
969 case PIPE_BLENDFACTOR_INV_DST_COLOR:
970 return 9;
971 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
972 return 10;
973 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
974 return 26;
975 case PIPE_BLENDFACTOR_SRC1_COLOR:
976 case PIPE_BLENDFACTOR_SRC1_ALPHA:
977 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
978 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
979 return -1; /* not support */
980 }
981 return -1;
982 }
983
984 static int
985 lima_calculate_alpha_blend(enum pipe_blend_func rgb_func, enum pipe_blend_func alpha_func,
986 enum pipe_blendfactor rgb_src_factor, enum pipe_blendfactor rgb_dst_factor,
987 enum pipe_blendfactor alpha_src_factor, enum pipe_blendfactor alpha_dst_factor)
988 {
989 return lima_blend_func(rgb_func) |
990 (lima_blend_func(alpha_func) << 3) |
991 (lima_blend_factor(rgb_src_factor) << 6) |
992 (lima_blend_factor(rgb_dst_factor) << 11) |
993 ((lima_blend_factor(alpha_src_factor) & 0xF) << 16) |
994 ((lima_blend_factor(alpha_dst_factor) & 0xF) << 20) |
995 0x0C000000; /* need check if this GLESv1 glAlphaFunc */
996 }
997
998 static int
999 lima_stencil_op(enum pipe_stencil_op pipe)
1000 {
1001 switch (pipe) {
1002 case PIPE_STENCIL_OP_KEEP:
1003 return 0;
1004 case PIPE_STENCIL_OP_ZERO:
1005 return 2;
1006 case PIPE_STENCIL_OP_REPLACE:
1007 return 1;
1008 case PIPE_STENCIL_OP_INCR:
1009 return 6;
1010 case PIPE_STENCIL_OP_DECR:
1011 return 7;
1012 case PIPE_STENCIL_OP_INCR_WRAP:
1013 return 4;
1014 case PIPE_STENCIL_OP_DECR_WRAP:
1015 return 5;
1016 case PIPE_STENCIL_OP_INVERT:
1017 return 3;
1018 }
1019 return -1;
1020 }
1021
1022 static int
1023 lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer_state *rst)
1024 {
1025 enum pipe_compare_func func = (depth->enabled ? depth->func : PIPE_FUNC_ALWAYS);
1026
1027 int offset_scale = 0;
1028
1029 //TODO: implement polygon offset
1030 #if 0
1031 if (rst->offset_scale < -32)
1032 offset_scale = -32;
1033 else if (rst->offset_scale > 31)
1034 offset_scale = 31;
1035 else
1036 offset_scale = rst->offset_scale * 4;
1037
1038 if (offset_scale < 0)
1039 offset_scale = 0x100 + offset_scale;
1040 #endif
1041
1042 return (depth->enabled && depth->writemask) |
1043 ((int)func << 1) |
1044 (offset_scale << 16) |
1045 0x30; /* find out what is this */
1046 }
1047
1048 static void
1049 lima_pack_render_state(struct lima_context *ctx, const struct pipe_draw_info *info)
1050 {
1051 struct lima_render_state *render =
1052 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_plb_rsw,
1053 sizeof(*render), true);
1054
1055 /* do hw support RGBA independ blend?
1056 * PIPE_CAP_INDEP_BLEND_ENABLE
1057 *
1058 * how to handle the no cbuf only zbuf case?
1059 */
1060 struct pipe_rt_blend_state *rt = ctx->blend->base.rt;
1061 render->blend_color_bg = float_to_ubyte(ctx->blend_color.color[2]) |
1062 (float_to_ubyte(ctx->blend_color.color[1]) << 16);
1063 render->blend_color_ra = float_to_ubyte(ctx->blend_color.color[0]) |
1064 (float_to_ubyte(ctx->blend_color.color[3]) << 16);
1065
1066 if (rt->blend_enable) {
1067 render->alpha_blend = lima_calculate_alpha_blend(rt->rgb_func, rt->alpha_func,
1068 rt->rgb_src_factor, rt->rgb_dst_factor,
1069 rt->alpha_src_factor, rt->alpha_dst_factor);
1070 }
1071 else {
1072 /*
1073 * Special handling for blending disabled.
1074 * Binary driver is generating the same alpha_value,
1075 * as when we would just enable blending, without changing/setting any blend equation/params.
1076 * Normaly in this case mesa would set all rt fields (func/factor) to zero.
1077 */
1078 render->alpha_blend = lima_calculate_alpha_blend(PIPE_BLEND_ADD, PIPE_BLEND_ADD,
1079 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO,
1080 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO);
1081 }
1082
1083 render->alpha_blend |= (rt->colormask & PIPE_MASK_RGBA) << 28;
1084
1085 struct pipe_rasterizer_state *rst = &ctx->rasterizer->base;
1086 struct pipe_depth_state *depth = &ctx->zsa->base.depth;
1087 render->depth_test = lima_calculate_depth_test(depth, rst);
1088
1089 /* overlap with plbu? any place can remove one? */
1090 render->depth_range = float_to_ushort(ctx->viewport.near) |
1091 (float_to_ushort(ctx->viewport.far) << 16);
1092
1093 #if 0
1094 struct pipe_stencil_state *stencil = ctx->zsa->base.stencil;
1095 struct pipe_stencil_ref *ref = &ctx->stencil_ref;
1096 render->stencil_front = stencil[0].func |
1097 (lima_stencil_op(stencil[0].fail_op) << 3) |
1098 (lima_stencil_op(stencil[0].zfail_op) << 6) |
1099 (lima_stencil_op(stencil[0].zpass_op) << 9) |
1100 (ref->ref_value[0] << 16) |
1101 (stencil[0].valuemask << 24);
1102 render->stencil_back = stencil[1].func |
1103 (lima_stencil_op(stencil[1].fail_op) << 3) |
1104 (lima_stencil_op(stencil[1].zfail_op) << 6) |
1105 (lima_stencil_op(stencil[1].zpass_op) << 9) |
1106 (ref->ref_value[1] << 16) |
1107 (stencil[1].valuemask << 24);
1108 #else
1109 render->stencil_front = 0xff000007;
1110 render->stencil_back = 0xff000007;
1111 #endif
1112
1113 /* seems not correct? */
1114 //struct pipe_alpha_state *alpha = &ctx->zsa->base.alpha;
1115 render->stencil_test = 0;
1116 //(stencil->enabled ? 0xFF : 0x00) | (float_to_ubyte(alpha->ref_value) << 16)
1117
1118 /* need more investigation */
1119 if (info->mode == PIPE_PRIM_POINTS)
1120 render->multi_sample = 0x0000F007;
1121 else if (info->mode < PIPE_PRIM_TRIANGLES)
1122 render->multi_sample = 0x0000F407;
1123 else
1124 render->multi_sample = 0x0000F807;
1125 if (ctx->framebuffer.samples)
1126 render->multi_sample |= 0x68;
1127
1128 render->shader_address =
1129 ctx->fs->bo->va | (((uint32_t *)ctx->fs->bo->map)[0] & 0x1F);
1130
1131 /* seems not needed */
1132 render->uniforms_address = 0x00000000;
1133
1134 render->textures_address = 0x00000000;
1135
1136 /* more investigation */
1137 render->aux0 = 0x00000300 | (ctx->vs->varying_stride >> 3);
1138 render->aux1 = 0x00003000;
1139
1140 if (ctx->tex_stateobj.num_samplers) {
1141 render->textures_address =
1142 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_tex_desc, LIMA_CTX_BUFF_SUBMIT_PP);
1143 render->aux0 |= ctx->tex_stateobj.num_samplers << 14;
1144 render->aux0 |= 0x20;
1145 }
1146
1147 if (ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer) {
1148 render->uniforms_address =
1149 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, LIMA_CTX_BUFF_SUBMIT_PP);
1150 render->uniforms_address |= ((ctx->buffer_state[lima_ctx_buff_pp_uniform].size) / 4 - 1);
1151 render->aux0 |= 0x80;
1152 render->aux1 |= 0x10000;
1153 }
1154
1155 if (ctx->vs->num_varying > 1) {
1156 render->varying_types = 0x00000000;
1157 render->varyings_address =
1158 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_PP);
1159 for (int i = 1; i < ctx->vs->num_varying; i++) {
1160 int val;
1161
1162 struct lima_varying_info *v = ctx->vs->varying + i;
1163 if (v->component_size == 4)
1164 val = v->components > 2 ? 0 : 1;
1165 else
1166 val = v->components > 2 ? 2 : 3;
1167
1168 int index = i - 1;
1169 if (index < 10)
1170 render->varying_types |= val << (3 * index);
1171 else if (index == 10) {
1172 render->varying_types |= val << 30;
1173 render->varyings_address |= val >> 2;
1174 }
1175 else if (index == 11)
1176 render->varyings_address |= val << 1;
1177 }
1178 }
1179 else {
1180 render->varying_types = 0x00000000;
1181 render->varyings_address = 0x00000000;
1182 }
1183
1184 lima_dump_command_stream_print(
1185 render, sizeof(*render), false, "add render state at va %x\n",
1186 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, 0));
1187 }
1188
1189 static void
1190 lima_update_gp_attribute_info(struct lima_context *ctx, const struct pipe_draw_info *info)
1191 {
1192 struct lima_vertex_element_state *ve = ctx->vertex_elements;
1193 struct lima_context_vertex_buffer *vb = &ctx->vertex_buffers;
1194
1195 uint32_t *attribute =
1196 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_attribute_info,
1197 ve->num_elements * 8, true);
1198
1199 int n = 0;
1200 for (int i = 0; i < ve->num_elements; i++) {
1201 struct pipe_vertex_element *pve = ve->pipe + i;
1202
1203 assert(pve->vertex_buffer_index < vb->count);
1204 assert(vb->enabled_mask & (1 << pve->vertex_buffer_index));
1205
1206 struct pipe_vertex_buffer *pvb = vb->vb + pve->vertex_buffer_index;
1207 struct lima_resource *res = lima_resource(pvb->buffer.resource);
1208
1209 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
1210
1211 unsigned start = info->index_size ? ctx->min_index : info->start;
1212 attribute[n++] = res->bo->va + pvb->buffer_offset + pve->src_offset
1213 + start * pvb->stride;
1214 attribute[n++] = (pvb->stride << 11) |
1215 (lima_pipe_format_to_attrib_type(pve->src_format) << 2) |
1216 (util_format_get_nr_components(pve->src_format) - 1);
1217 }
1218
1219 lima_dump_command_stream_print(
1220 attribute, n * 4, false, "update attribute info at va %x\n",
1221 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, 0));
1222 }
1223
1224 static void
1225 lima_update_gp_uniform(struct lima_context *ctx)
1226 {
1227 struct lima_context_constant_buffer *ccb =
1228 ctx->const_buffer + PIPE_SHADER_VERTEX;
1229 struct lima_vs_shader_state *vs = ctx->vs;
1230
1231 int size = vs->uniform_pending_offset + vs->constant_size + 32;
1232 void *vs_const_buff =
1233 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_uniform, size, true);
1234
1235 if (ccb->buffer)
1236 memcpy(vs_const_buff, ccb->buffer, ccb->size);
1237
1238 memcpy(vs_const_buff + vs->uniform_pending_offset,
1239 ctx->viewport.transform.scale,
1240 sizeof(ctx->viewport.transform.scale));
1241 memcpy(vs_const_buff + vs->uniform_pending_offset + 16,
1242 ctx->viewport.transform.translate,
1243 sizeof(ctx->viewport.transform.translate));
1244
1245 if (vs->constant)
1246 memcpy(vs_const_buff + vs->uniform_pending_offset + 32,
1247 vs->constant, vs->constant_size);
1248
1249 lima_dump_command_stream_print(
1250 vs_const_buff, size, true,
1251 "update gp uniform at va %x\n",
1252 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, 0));
1253 }
1254
1255 static void
1256 lima_update_pp_uniform(struct lima_context *ctx)
1257 {
1258 const float *const_buff = ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer;
1259 size_t const_buff_size = ctx->const_buffer[PIPE_SHADER_FRAGMENT].size / sizeof(float);
1260
1261 if (!const_buff)
1262 return;
1263
1264 uint16_t *fp16_const_buff =
1265 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform,
1266 const_buff_size * sizeof(uint16_t), true);
1267
1268 uint32_t *array =
1269 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform_array, 4, true);
1270
1271 for (int i = 0; i < const_buff_size; i++)
1272 fp16_const_buff[i] = util_float_to_half(const_buff[i]);
1273
1274 *array = lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, LIMA_CTX_BUFF_SUBMIT_PP);
1275
1276 lima_dump_command_stream_print(
1277 fp16_const_buff, const_buff_size * 2, false, "add pp uniform data at va %x\n",
1278 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, 0));
1279 lima_dump_command_stream_print(
1280 array, 4, false, "add pp uniform info at va %x\n",
1281 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, 0));
1282 }
1283
1284 static void
1285 lima_update_varying(struct lima_context *ctx, const struct pipe_draw_info *info)
1286 {
1287 struct lima_vs_shader_state *vs = ctx->vs;
1288
1289 uint32_t *varying =
1290 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_varying_info,
1291 vs->num_varying * 8, true);
1292 int n = 0;
1293
1294 /* should be LIMA_SUBMIT_BO_WRITE for GP, but each draw will use
1295 * different part of this bo, so no need to set exclusive constraint */
1296 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_gl_pos,
1297 4 * 4 * info->count, false);
1298
1299 /* for gl_Position */
1300 varying[n++] =
1301 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
1302 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
1303 varying[n++] = 0x8020;
1304
1305 int offset = 0;
1306 for (int i = 1; i < vs->num_varying; i++) {
1307 struct lima_varying_info *v = vs->varying + i;
1308 int size = v->component_size * 4;
1309
1310 /* does component_size == 2 need to be 16 aligned? */
1311 if (v->component_size == 4)
1312 offset = align(offset, 16);
1313
1314 v->offset = offset;
1315 offset += size;
1316 }
1317 vs->varying_stride = align(offset, 16);
1318
1319 if (vs->num_varying > 1)
1320 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_varying,
1321 vs->varying_stride * info->count, false);
1322
1323 for (int i = 1; i < vs->num_varying; i++) {
1324 struct lima_varying_info *v = vs->varying + i;
1325 varying[n++] =
1326 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_GP) +
1327 v->offset;
1328 varying[n++] = (vs->varying_stride << 11) | (v->components - 1) |
1329 (v->component_size == 2 ? 0x0C : 0);
1330 }
1331
1332 lima_dump_command_stream_print(
1333 varying, n * 4, false, "update varying info at va %x\n",
1334 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, 0));
1335 }
1336
1337 static void
1338 lima_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
1339 {
1340 /* check if draw mode and vertex/index count match,
1341 * otherwise gp will hang */
1342 if (!u_trim_pipe_prim(info->mode, (unsigned*)&info->count)) {
1343 debug_printf("draw mode and vertex/index count mismatch\n");
1344 return;
1345 }
1346
1347 struct lima_context *ctx = lima_context(pctx);
1348
1349 if (!ctx->vs || !ctx->fs) {
1350 debug_warn_once("no shader, skip draw\n");
1351 return;
1352 }
1353
1354 if (!lima_update_vs_state(ctx) || !lima_update_fs_state(ctx))
1355 return;
1356
1357 lima_dump_command_stream_print(
1358 ctx->vs->bo->map, ctx->vs->shader_size, false,
1359 "add vs at va %x\n", ctx->vs->bo->va);
1360
1361 lima_dump_command_stream_print(
1362 ctx->fs->bo->map, ctx->fs->shader_size, false,
1363 "add fs at va %x\n", ctx->fs->bo->va);
1364
1365 lima_submit_add_bo(ctx->gp_submit, ctx->vs->bo, LIMA_SUBMIT_BO_READ);
1366 lima_submit_add_bo(ctx->pp_submit, ctx->fs->bo, LIMA_SUBMIT_BO_READ);
1367
1368 lima_update_submit_bo(ctx);
1369
1370 /* Mali Utgard GPU always need min/max index info for index draw,
1371 * compute it if upper layer does not do for us */
1372 if (info->index_size && info->max_index == ~0u)
1373 u_vbuf_get_minmax_index(pctx, info, &ctx->min_index, &ctx->max_index);
1374 else {
1375 ctx->min_index = info->min_index;
1376 ctx->max_index = info->max_index;
1377 }
1378
1379 lima_update_gp_attribute_info(ctx, info);
1380
1381 if ((ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1382 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty) ||
1383 ctx->dirty & LIMA_CONTEXT_DIRTY_VIEWPORT ||
1384 ctx->dirty & LIMA_CONTEXT_DIRTY_SHADER_VERT) {
1385 lima_update_gp_uniform(ctx);
1386 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty = false;
1387 }
1388
1389 lima_update_varying(ctx, info);
1390
1391 /* If it's zero scissor, don't build vs cmd list */
1392 if (!lima_is_scissor_zero(ctx))
1393 lima_pack_vs_cmd(ctx, info);
1394
1395 if (ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1396 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty) {
1397 lima_update_pp_uniform(ctx);
1398 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty = false;
1399 }
1400
1401 if (ctx->dirty & LIMA_CONTEXT_DIRTY_TEXTURES)
1402 lima_update_textures(ctx);
1403
1404 lima_pack_render_state(ctx, info);
1405 lima_pack_plbu_cmd(ctx, info);
1406
1407 ctx->dirty = 0;
1408 }
1409
1410 static void
1411 lima_finish_plbu_cmd(struct lima_context *ctx)
1412 {
1413 int i = 0;
1414 uint32_t *plbu_cmd = util_dynarray_grow_cap(&ctx->plbu_cmd_array, 2 * 4);
1415
1416 plbu_cmd[i++] = 0x00000000;
1417 plbu_cmd[i++] = 0x50000000; /* END */
1418
1419 ctx->plbu_cmd_array.size += i * 4;
1420 }
1421
1422 static void
1423 lima_pack_pp_frame_reg(struct lima_context *ctx, uint32_t *frame_reg,
1424 uint32_t *wb_reg)
1425 {
1426 struct lima_resource *res = lima_resource(ctx->framebuffer.cbuf->texture);
1427
1428 bool swap_channels = false;
1429 switch (ctx->framebuffer.cbuf->format) {
1430 case PIPE_FORMAT_R8G8B8A8_UNORM:
1431 case PIPE_FORMAT_R8G8B8X8_UNORM:
1432 swap_channels = true;
1433 break;
1434 default:
1435 break;
1436 }
1437
1438 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1439 struct lima_pp_frame_reg *frame = (void *)frame_reg;
1440 struct lima_screen *screen = lima_screen(ctx->base.screen);
1441 frame->render_address = screen->pp_buffer->va + pp_frame_rsw_offset;
1442 frame->flags = 0x02;
1443 frame->clear_value_depth = ctx->clear.depth;
1444 frame->clear_value_stencil = ctx->clear.stencil;
1445 frame->clear_value_color = ctx->clear.color_8pc;
1446 frame->clear_value_color_1 = ctx->clear.color_8pc;
1447 frame->clear_value_color_2 = ctx->clear.color_8pc;
1448 frame->clear_value_color_3 = ctx->clear.color_8pc;
1449 frame->one = 1;
1450
1451 frame->width = fb->width - 1;
1452 frame->height = fb->height - 1;
1453
1454 /* frame->fragment_stack_address is overwritten per-pp in the kernel
1455 * by the values of pp_frame.fragment_stack_address[i] */
1456
1457 /* These are "stack size" and "stack offset" shifted,
1458 * here they are assumed to be always the same. */
1459 uint32_t fs_stack_size = ctx->fs ? ctx->fs->stack_size : 0;
1460 frame->fragment_stack_size = fs_stack_size << 16 | fs_stack_size;
1461
1462 /* related with MSAA and different value when r4p0/r7p0 */
1463 frame->supersampled_height = fb->height * 2 - 1;
1464 frame->scale = 0xE0C;
1465
1466 frame->dubya = 0x77;
1467 frame->onscreen = 1;
1468 frame->blocking = (fb->shift_min << 28) | (fb->shift_h << 16) | fb->shift_w;
1469 frame->foureight = 0x8888;
1470
1471 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1472 wb[0].type = 0x02; /* 1 for depth, stencil */
1473 wb[0].address = res->bo->va;
1474 wb[0].pixel_format = 0x03; /* BGRA8888 */
1475 if (res->tiled) {
1476 wb[0].pixel_layout = 0x2;
1477 wb[0].pitch = fb->tiled_w;
1478 } else {
1479 wb[0].pixel_layout = 0x0;
1480 wb[0].pitch = res->levels[0].stride / 8;
1481 }
1482 wb[0].mrt_bits = swap_channels ? 0x4 : 0x0;
1483 }
1484
1485 static void
1486 _lima_flush(struct lima_context *ctx, bool end_of_frame)
1487 {
1488 lima_finish_plbu_cmd(ctx);
1489
1490 int vs_cmd_size = ctx->vs_cmd_array.size;
1491 int plbu_cmd_size = ctx->plbu_cmd_array.size;
1492 uint32_t vs_cmd_va = 0;
1493 uint32_t plbu_cmd_va;
1494
1495 if (vs_cmd_size) {
1496 void *vs_cmd =
1497 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_vs_cmd, vs_cmd_size, true);
1498 memcpy(vs_cmd, util_dynarray_begin(&ctx->vs_cmd_array), vs_cmd_size);
1499 util_dynarray_clear(&ctx->vs_cmd_array);
1500 vs_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_vs_cmd,
1501 LIMA_CTX_BUFF_SUBMIT_GP);
1502
1503 lima_dump_command_stream_print(
1504 vs_cmd, vs_cmd_size, false, "flush vs cmd at va %x\n", vs_cmd_va);
1505 }
1506
1507 void *plbu_cmd =
1508 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_plbu_cmd, plbu_cmd_size, true);
1509 memcpy(plbu_cmd, util_dynarray_begin(&ctx->plbu_cmd_array), plbu_cmd_size);
1510 util_dynarray_clear(&ctx->plbu_cmd_array);
1511 plbu_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_plbu_cmd,
1512 LIMA_CTX_BUFF_SUBMIT_GP);
1513
1514 lima_dump_command_stream_print(
1515 plbu_cmd, plbu_cmd_size, false, "flush plbu cmd at va %x\n", plbu_cmd_va);
1516
1517 struct lima_screen *screen = lima_screen(ctx->base.screen);
1518 struct drm_lima_gp_frame gp_frame;
1519 struct lima_gp_frame_reg *gp_frame_reg = (void *)gp_frame.frame;
1520 gp_frame_reg->vs_cmd_start = vs_cmd_va;
1521 gp_frame_reg->vs_cmd_end = vs_cmd_va + vs_cmd_size;
1522 gp_frame_reg->plbu_cmd_start = plbu_cmd_va;
1523 gp_frame_reg->plbu_cmd_end = plbu_cmd_va + plbu_cmd_size;
1524 gp_frame_reg->tile_heap_start = screen->gp_buffer->va + gp_tile_heap_offset;
1525 gp_frame_reg->tile_heap_end = screen->gp_buffer->va + gp_buffer_size;
1526
1527 lima_dump_command_stream_print(
1528 &gp_frame, sizeof(gp_frame), false, "add gp frame\n");
1529
1530 if (!lima_submit_start(ctx->gp_submit, &gp_frame, sizeof(gp_frame)))
1531 fprintf(stderr, "gp submit error\n");
1532
1533 if (lima_dump_command_stream) {
1534 if (lima_submit_wait(ctx->gp_submit, PIPE_TIMEOUT_INFINITE)) {
1535 if (ctx->buffer_state[lima_ctx_buff_sh_gl_pos].res) {
1536 float *pos = lima_ctx_buff_map(ctx, lima_ctx_buff_sh_gl_pos);
1537 lima_dump_command_stream_print(
1538 pos, 4 * 4 * 16, true, "gl_pos dump at va %x\n",
1539 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos, 0));
1540 }
1541
1542 uint32_t *plb = lima_bo_map(ctx->plb[ctx->plb_index]);
1543 lima_dump_command_stream_print(
1544 plb, LIMA_CTX_PLB_BLK_SIZE, false, "plb dump at va %x\n",
1545 ctx->plb[ctx->plb_index]->va);
1546 }
1547 else {
1548 fprintf(stderr, "gp submit wait error\n");
1549 exit(1);
1550 }
1551 }
1552
1553 struct lima_pp_stream_state *ps = &ctx->pp_stream;
1554 if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI400) {
1555 struct drm_lima_m400_pp_frame pp_frame = {0};
1556 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1557 pp_frame.num_pp = screen->num_pp;
1558
1559 for (int i = 0; i < screen->num_pp; i++) {
1560 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1561 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1562 pp_stack_offset + pp_stack_pp_size * i;
1563 }
1564
1565 lima_dump_command_stream_print(
1566 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1567
1568 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1569 fprintf(stderr, "pp submit error\n");
1570 }
1571 else {
1572 struct drm_lima_m450_pp_frame pp_frame = {0};
1573 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1574 pp_frame.num_pp = screen->num_pp;
1575
1576 for (int i = 0; i < screen->num_pp; i++)
1577 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1578 pp_stack_offset + pp_stack_pp_size * i;
1579
1580 if (ps->bo) {
1581 for (int i = 0; i < screen->num_pp; i++)
1582 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1583 }
1584 else {
1585 pp_frame.use_dlbu = true;
1586
1587 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1588 pp_frame.dlbu_regs[0] = ctx->plb[ctx->plb_index]->va;
1589 pp_frame.dlbu_regs[1] = ((fb->tiled_h - 1) << 16) | (fb->tiled_w - 1);
1590 unsigned s = util_logbase2(LIMA_CTX_PLB_BLK_SIZE) - 7;
1591 pp_frame.dlbu_regs[2] = (s << 28) | (fb->shift_h << 16) | fb->shift_w;
1592 pp_frame.dlbu_regs[3] = ((fb->tiled_h - 1) << 24) | ((fb->tiled_w - 1) << 16);
1593 }
1594
1595 lima_dump_command_stream_print(
1596 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1597
1598 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1599 fprintf(stderr, "pp submit error\n");
1600 }
1601
1602 if (lima_dump_command_stream) {
1603 if (!lima_submit_wait(ctx->pp_submit, PIPE_TIMEOUT_INFINITE)) {
1604 fprintf(stderr, "pp wait error\n");
1605 exit(1);
1606 }
1607 }
1608
1609 ctx->plb_index = (ctx->plb_index + 1) % lima_ctx_num_plb;
1610
1611 /* this surface may need reload when next draw if not end of frame */
1612 struct lima_surface *surf = lima_surface(ctx->framebuffer.cbuf);
1613 surf->reload = !end_of_frame;
1614 }
1615
1616 void
1617 lima_flush(struct lima_context *ctx)
1618 {
1619 if (!lima_ctx_dirty(ctx))
1620 return;
1621
1622 _lima_flush(ctx, false);
1623 }
1624
1625 static void
1626 lima_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
1627 unsigned flags)
1628 {
1629 struct lima_context *ctx = lima_context(pctx);
1630 if (!lima_ctx_dirty(ctx))
1631 return;
1632
1633 _lima_flush(ctx, flags & PIPE_FLUSH_END_OF_FRAME);
1634
1635 if (fence) {
1636 int fd;
1637 if (lima_submit_get_out_sync(ctx->pp_submit, &fd))
1638 *fence = lima_fence_create(fd);
1639 }
1640 }
1641
1642 void
1643 lima_draw_init(struct lima_context *ctx)
1644 {
1645 ctx->base.clear = lima_clear;
1646 ctx->base.draw_vbo = lima_draw_vbo;
1647 ctx->base.flush = lima_pipe_flush;
1648 }