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lima: fix width 4096 resolution GP fail
[mesa.git] / src / gallium / drivers / lima / lima_draw.c
1 /*
2 * Copyright (c) 2011-2013 Luc Verhaegen <libv@skynet.be>
3 * Copyright (c) 2017-2019 Lima Project
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "util/u_math.h"
27 #include "util/u_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_half.h"
30 #include "util/u_helpers.h"
31 #include "util/u_inlines.h"
32 #include "util/u_pack_color.h"
33 #include "util/hash_table.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36 #include "util/u_vbuf.h"
37
38 #include "lima_context.h"
39 #include "lima_screen.h"
40 #include "lima_resource.h"
41 #include "lima_program.h"
42 #include "lima_bo.h"
43 #include "lima_submit.h"
44 #include "lima_texture.h"
45 #include "lima_util.h"
46 #include "lima_fence.h"
47
48 #include <drm-uapi/lima_drm.h>
49
50 struct lima_gp_frame_reg {
51 uint32_t vs_cmd_start;
52 uint32_t vs_cmd_end;
53 uint32_t plbu_cmd_start;
54 uint32_t plbu_cmd_end;
55 uint32_t tile_heap_start;
56 uint32_t tile_heap_end;
57 };
58
59 struct lima_pp_frame_reg {
60 uint32_t plbu_array_address;
61 uint32_t render_address;
62 uint32_t unused_0;
63 uint32_t flags;
64 uint32_t clear_value_depth;
65 uint32_t clear_value_stencil;
66 uint32_t clear_value_color;
67 uint32_t clear_value_color_1;
68 uint32_t clear_value_color_2;
69 uint32_t clear_value_color_3;
70 uint32_t width;
71 uint32_t height;
72 uint32_t fragment_stack_address;
73 uint32_t fragment_stack_size;
74 uint32_t unused_1;
75 uint32_t unused_2;
76 uint32_t one;
77 uint32_t supersampled_height;
78 uint32_t dubya;
79 uint32_t onscreen;
80 uint32_t blocking;
81 uint32_t scale;
82 uint32_t foureight;
83 };
84
85 struct lima_pp_wb_reg {
86 uint32_t type;
87 uint32_t address;
88 uint32_t pixel_format;
89 uint32_t downsample_factor;
90 uint32_t pixel_layout;
91 uint32_t pitch;
92 uint32_t mrt_bits;
93 uint32_t mrt_pitch;
94 uint32_t zero;
95 uint32_t unused0;
96 uint32_t unused1;
97 uint32_t unused2;
98 };
99
100 struct lima_render_state {
101 uint32_t blend_color_bg;
102 uint32_t blend_color_ra;
103 uint32_t alpha_blend;
104 uint32_t depth_test;
105 uint32_t depth_range;
106 uint32_t stencil_front;
107 uint32_t stencil_back;
108 uint32_t stencil_test;
109 uint32_t multi_sample;
110 uint32_t shader_address;
111 uint32_t varying_types;
112 uint32_t uniforms_address;
113 uint32_t textures_address;
114 uint32_t aux0;
115 uint32_t aux1;
116 uint32_t varyings_address;
117 };
118
119 #define LIMA_PIXEL_FORMAT_B8G8R8A8 0x03
120 #define LIMA_PIXEL_FORMAT_Z16 0x0e
121 #define LIMA_PIXEL_FORMAT_Z24S8 0x0f
122
123 /* plbu commands */
124 #define PLBU_CMD_BEGIN(max) { \
125 int i = 0, max_n = max; \
126 uint32_t *plbu_cmd = util_dynarray_grow_cap(&ctx->plbu_cmd_array, max_n * 4);
127
128 #define PLBU_CMD_END() \
129 assert(i <= max_n); \
130 ctx->plbu_cmd_array.size += i * 4; \
131 }
132
133 #define PLBU_CMD(v1, v2) \
134 do { \
135 plbu_cmd[i++] = v1; \
136 plbu_cmd[i++] = v2; \
137 } while (0)
138
139 #define PLBU_CMD_BLOCK_STEP(shift_min, shift_h, shift_w) \
140 PLBU_CMD(((shift_min) << 28) | ((shift_h) << 16) | (shift_w), 0x1000010C)
141 #define PLBU_CMD_TILED_DIMENSIONS(tiled_w, tiled_h) \
142 PLBU_CMD((((tiled_w) - 1) << 24) | (((tiled_h) - 1) << 8), 0x10000109)
143 #define PLBU_CMD_BLOCK_STRIDE(block_w) PLBU_CMD((block_w) & 0xff, 0x30000000)
144 #define PLBU_CMD_ARRAY_ADDRESS(gp_stream, block_num) \
145 PLBU_CMD(gp_stream, 0x28000000 | ((block_num) - 1) | 1)
146 #define PLBU_CMD_VIEWPORT_X(v) PLBU_CMD(v, 0x10000107)
147 #define PLBU_CMD_VIEWPORT_W(v) PLBU_CMD(v, 0x10000108)
148 #define PLBU_CMD_VIEWPORT_Y(v) PLBU_CMD(v, 0x10000105)
149 #define PLBU_CMD_VIEWPORT_H(v) PLBU_CMD(v, 0x10000106)
150 #define PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN() PLBU_CMD(0x00010002, 0x60000000)
151 #define PLBU_CMD_ARRAYS_SEMAPHORE_END() PLBU_CMD(0x00010001, 0x60000000)
152 #define PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, index_size) \
153 PLBU_CMD(((low_prim) ? 0x00003200 : 0x00002200) | (cull) | ((index_size) << 9), 0x1000010B)
154 #define PLBU_CMD_RSW_VERTEX_ARRAY(rsw, gl_pos) \
155 PLBU_CMD(rsw, 0x80000000 | ((gl_pos) >> 4))
156 #define PLBU_CMD_SCISSORS(minx, maxx, miny, maxy) \
157 PLBU_CMD(((minx) << 30) | ((maxy) - 1) << 15 | (miny), \
158 0x70000000 | ((maxx) - 1) << 13 | ((minx) >> 2))
159 #define PLBU_CMD_UNKNOWN1() PLBU_CMD(0x00000000, 0x1000010A)
160 #define PLBU_CMD_UNKNOWN2() PLBU_CMD(0x00000200, 0x1000010B)
161 #define PLBU_CMD_LOW_PRIM_SIZE(v) PLBU_CMD(v, 0x1000010D)
162 #define PLBU_CMD_DEPTH_RANGE_NEAR(v) PLBU_CMD(v, 0x1000010E)
163 #define PLBU_CMD_DEPTH_RANGE_FAR(v) PLBU_CMD(v, 0x1000010F)
164 #define PLBU_CMD_INDEXED_DEST(gl_pos) PLBU_CMD(gl_pos, 0x10000100)
165 #define PLBU_CMD_INDICES(va) PLBU_CMD(va, 0x10000101)
166 #define PLBU_CMD_DRAW_ARRAYS(mode, start, count) \
167 PLBU_CMD(((count) << 24) | (start), (((mode) & 0x1F) << 16) | ((count) >> 8))
168 #define PLBU_CMD_DRAW_ELEMENTS(mode, start, count) \
169 PLBU_CMD(((count) << 24) | (start), \
170 0x00200000 | (((mode) & 0x1F) << 16) | ((count) >> 8))
171
172 /* vs commands */
173 #define VS_CMD_BEGIN(max) { \
174 int i = 0, max_n = max; \
175 uint32_t *vs_cmd = util_dynarray_grow_cap(&ctx->vs_cmd_array, max_n * 4);
176
177 #define VS_CMD_END() \
178 assert(i <= max_n); \
179 ctx->vs_cmd_array.size += i * 4; \
180 }
181
182 #define VS_CMD(v1, v2) \
183 do { \
184 vs_cmd[i++] = v1; \
185 vs_cmd[i++] = v2; \
186 } while (0)
187
188 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1() VS_CMD(0x00028000, 0x50000000)
189 #define VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2() VS_CMD(0x00000001, 0x50000000)
190 #define VS_CMD_ARRAYS_SEMAPHORE_END(index_draw) \
191 VS_CMD((index_draw) ? 0x00018000 : 0x00000000, 0x50000000)
192 #define VS_CMD_UNIFORMS_ADDRESS(addr, size) \
193 VS_CMD(addr, 0x30000000 | ((size) << 12))
194 #define VS_CMD_SHADER_ADDRESS(addr, size) \
195 VS_CMD(addr, 0x40000000 | ((size) << 12))
196 #define VS_CMD_SHADER_INFO(prefetch, size) \
197 VS_CMD(((prefetch) << 20) | ((((size) >> 4) - 1) << 10), 0x10000040)
198 #define VS_CMD_VARYING_ATTRIBUTE_COUNT(nv, na) \
199 VS_CMD((((nv) - 1) << 8) | (((na) - 1) << 24), 0x10000042)
200 #define VS_CMD_UNKNOWN1() VS_CMD(0x00000003, 0x10000041)
201 #define VS_CMD_UNKNOWN2() VS_CMD(0x00000000, 0x60000000)
202 #define VS_CMD_ATTRIBUTES_ADDRESS(addr, na) \
203 VS_CMD(addr, 0x20000000 | ((na) << 17))
204 #define VS_CMD_VARYINGS_ADDRESS(addr, nv) \
205 VS_CMD(addr, 0x20000008 | ((nv) << 17))
206 #define VS_CMD_DRAW(num, index_draw) \
207 VS_CMD(((num) << 24) | ((index_draw) ? 1 : 0), ((num) >> 8))
208
209 static inline bool
210 lima_ctx_dirty(struct lima_context *ctx)
211 {
212 return ctx->plbu_cmd_array.size;
213 }
214
215 static bool
216 lima_fb_need_reload(struct lima_context *ctx)
217 {
218 /* Depth buffer is always discarded */
219 if (!ctx->framebuffer.base.nr_cbufs)
220 return false;
221 if (ctx->damage.region) {
222 /* for EGL_KHR_partial_update we just want to reload the
223 * region not aligned to tile boundary */
224 if (!ctx->damage.aligned)
225 return true;
226 }
227 else {
228 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
229 if (surf->reload)
230 return true;
231 }
232
233 return false;
234 }
235
236 static void
237 lima_pack_reload_plbu_cmd(struct lima_context *ctx)
238 {
239 #define lima_reload_render_state_offset 0x0000
240 #define lima_reload_gl_pos_offset 0x0040
241 #define lima_reload_varying_offset 0x0080
242 #define lima_reload_tex_desc_offset 0x00c0
243 #define lima_reload_tex_array_offset 0x0100
244 #define lima_reload_buffer_size 0x0140
245
246 void *cpu;
247 unsigned offset;
248 struct pipe_resource *pres = NULL;
249 u_upload_alloc(ctx->uploader, 0, lima_reload_buffer_size,
250 0x40, &offset, &pres, &cpu);
251
252 struct lima_resource *res = lima_resource(pres);
253 uint32_t va = res->bo->va + offset;
254
255 struct lima_screen *screen = lima_screen(ctx->base.screen);
256
257 uint32_t reload_shader_first_instr_size =
258 ((uint32_t *)(screen->pp_buffer->map + pp_reload_program_offset))[0] & 0x1f;
259 uint32_t reload_shader_va = screen->pp_buffer->va + pp_reload_program_offset;
260
261 struct lima_render_state reload_render_state = {
262 .alpha_blend = 0xf03b1ad2,
263 .depth_test = 0x0000000e,
264 .depth_range = 0xffff0000,
265 .stencil_front = 0x00000007,
266 .stencil_back = 0x00000007,
267 .multi_sample = 0x0000f007,
268 .shader_address = reload_shader_va | reload_shader_first_instr_size,
269 .varying_types = 0x00000001,
270 .textures_address = va + lima_reload_tex_array_offset,
271 .aux0 = 0x00004021,
272 .varyings_address = va + lima_reload_varying_offset,
273 };
274 memcpy(cpu + lima_reload_render_state_offset, &reload_render_state,
275 sizeof(reload_render_state));
276
277 struct lima_context_framebuffer *fb = &ctx->framebuffer;
278 uint32_t *td = cpu + lima_reload_tex_desc_offset;
279 memset(td, 0, lima_tex_desc_size);
280 lima_texture_desc_set_res(ctx, td, fb->base.cbufs[0]->texture, 0, 0);
281 td[1] = 0x00000480;
282 td[2] |= 0x00093800;
283 td[4] = 0x00000000;
284 td[5] = 0x00000000;
285
286 uint32_t *ta = cpu + lima_reload_tex_array_offset;
287 ta[0] = va + lima_reload_tex_desc_offset;
288
289 float reload_gl_pos[] = {
290 fb->base.width, 0, 0, 1,
291 0, 0, 0, 1,
292 0, fb->base.height, 0, 1,
293 };
294 memcpy(cpu + lima_reload_gl_pos_offset, reload_gl_pos,
295 sizeof(reload_gl_pos));
296
297 float reload_varying[] = {
298 fb->base.width, 0, 0, 0,
299 0, fb->base.height, 0, 0,
300 };
301 memcpy(cpu + lima_reload_varying_offset, reload_varying,
302 sizeof(reload_varying));
303
304 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
305 pipe_resource_reference(&pres, NULL);
306
307 PLBU_CMD_BEGIN(20);
308
309 PLBU_CMD_VIEWPORT_X(0);
310 PLBU_CMD_VIEWPORT_W(fui(fb->base.width));
311 PLBU_CMD_VIEWPORT_Y(0);
312 PLBU_CMD_VIEWPORT_H(fui(fb->base.height));
313
314 PLBU_CMD_RSW_VERTEX_ARRAY(
315 va + lima_reload_render_state_offset,
316 va + lima_reload_gl_pos_offset);
317
318 PLBU_CMD_UNKNOWN2();
319 PLBU_CMD_UNKNOWN1();
320
321 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
322 PLBU_CMD_INDEXED_DEST(va + lima_reload_gl_pos_offset);
323 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
324
325 PLBU_CMD_END();
326 }
327
328 static void
329 lima_pack_clear_plbu_cmd(struct lima_context *ctx)
330 {
331 #define lima_clear_render_state_offset 0x0000
332 #define lima_clear_shader_offset 0x0040
333 #define lima_clear_buffer_size 0x0080
334
335 void *cpu;
336 unsigned offset;
337 struct pipe_resource *pres = NULL;
338 u_upload_alloc(ctx->uploader, 0, lima_clear_buffer_size,
339 0x40, &offset, &pres, &cpu);
340
341 struct lima_resource *res = lima_resource(pres);
342 uint32_t va = res->bo->va + offset;
343
344 struct lima_screen *screen = lima_screen(ctx->base.screen);
345 uint32_t gl_pos_va = screen->pp_buffer->va + pp_clear_gl_pos_offset;
346
347 /* const0 clear_color, mov.v1 $0 ^const0.xxxx, stop */
348 uint32_t clear_shader[] = {
349 0x00021025, 0x0000000c,
350 (ctx->clear.color_16pc << 12) | 0x000007cf,
351 ctx->clear.color_16pc >> 12,
352 ctx->clear.color_16pc >> 44,
353 };
354 memcpy(cpu + lima_clear_shader_offset, &clear_shader,
355 sizeof(clear_shader));
356
357 uint32_t clear_shader_va = va + lima_clear_shader_offset;
358 uint32_t clear_shader_first_instr_size = clear_shader[0] & 0x1f;
359
360 struct lima_render_state clear_render_state = {
361 .blend_color_bg = 0x00800080,
362 .blend_color_ra = 0x00ff0080,
363 .alpha_blend = 0xfc321892,
364 .depth_test = 0x0000003e,
365 .depth_range = 0xffff0000,
366 .stencil_front = 0x00000007,
367 .stencil_back = 0x00000007,
368 .multi_sample = 0x0000f007,
369 .shader_address = clear_shader_va | clear_shader_first_instr_size,
370 };
371 memcpy(cpu + lima_clear_render_state_offset, &clear_render_state,
372 sizeof(clear_render_state));
373
374 PLBU_CMD_BEGIN(22);
375
376 PLBU_CMD_VIEWPORT_X(0);
377 PLBU_CMD_VIEWPORT_W(0x45800000);
378 PLBU_CMD_VIEWPORT_Y(0);
379 PLBU_CMD_VIEWPORT_H(0x45800000);
380
381 struct pipe_scissor_state *scissor = &ctx->scissor;
382 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
383
384 PLBU_CMD_RSW_VERTEX_ARRAY(va + lima_clear_render_state_offset, gl_pos_va);
385
386 PLBU_CMD_UNKNOWN2();
387 PLBU_CMD_UNKNOWN1();
388
389 PLBU_CMD_INDICES(screen->pp_buffer->va + pp_shared_index_offset);
390 PLBU_CMD_INDEXED_DEST(gl_pos_va);
391 PLBU_CMD_DRAW_ELEMENTS(0xf, 0, 3);
392
393 PLBU_CMD_END();
394 }
395
396 static void
397 lima_pack_head_plbu_cmd(struct lima_context *ctx)
398 {
399 /* first draw need create a PLBU command header */
400 if (lima_ctx_dirty(ctx))
401 return;
402
403 struct lima_context_framebuffer *fb = &ctx->framebuffer;
404
405 PLBU_CMD_BEGIN(10);
406
407 PLBU_CMD_UNKNOWN2();
408 PLBU_CMD_BLOCK_STEP(fb->shift_min, fb->shift_h, fb->shift_w);
409 PLBU_CMD_TILED_DIMENSIONS(fb->tiled_w, fb->tiled_h);
410 PLBU_CMD_BLOCK_STRIDE(fb->block_w);
411
412 PLBU_CMD_ARRAY_ADDRESS(
413 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size,
414 fb->block_w * fb->block_h);
415
416 PLBU_CMD_END();
417
418 if (lima_fb_need_reload(ctx))
419 lima_pack_reload_plbu_cmd(ctx);
420 }
421
422 static bool
423 lima_is_scissor_zero(struct lima_context *ctx)
424 {
425 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
426 return false;
427
428 struct pipe_scissor_state *scissor = &ctx->scissor;
429 return
430 scissor->minx == scissor->maxx
431 && scissor->miny == scissor->maxy;
432 }
433
434 static bool
435 lima_is_scissor_full_fb(struct lima_context *ctx)
436 {
437 if (!ctx->rasterizer || !ctx->rasterizer->base.scissor)
438 return true;
439
440 struct pipe_scissor_state *scissor = &ctx->scissor;
441 struct lima_context_framebuffer *fb = &ctx->framebuffer;
442 return
443 scissor->minx == 0 && scissor->maxx == fb->base.width &&
444 scissor->miny == 0 && scissor->maxy == fb->base.height;
445 }
446
447 static void
448 hilbert_rotate(int n, int *x, int *y, int rx, int ry)
449 {
450 if (ry == 0) {
451 if (rx == 1) {
452 *x = n-1 - *x;
453 *y = n-1 - *y;
454 }
455
456 /* Swap x and y */
457 int t = *x;
458 *x = *y;
459 *y = t;
460 }
461 }
462
463 static void
464 hilbert_coords(int n, int d, int *x, int *y)
465 {
466 int rx, ry, i, t=d;
467
468 *x = *y = 0;
469
470 for (i = 0; (1 << i) < n; i++) {
471
472 rx = 1 & (t / 2);
473 ry = 1 & (t ^ rx);
474
475 hilbert_rotate(1 << i, x, y, rx, ry);
476
477 *x += rx << i;
478 *y += ry << i;
479
480 t /= 4;
481 }
482 }
483
484 static int
485 lima_get_pp_stream_size(int num_pp, int tiled_w, int tiled_h, uint32_t *off)
486 {
487 /* carefully calculate each stream start address:
488 * 1. overflow: each stream size may be different due to
489 * fb->tiled_w * fb->tiled_h can't be divided by num_pp,
490 * extra size should be added to the preceeding stream
491 * 2. alignment: each stream address should be 0x20 aligned
492 */
493 int delta = tiled_w * tiled_h / num_pp * 16 + 8;
494 int remain = tiled_w * tiled_h % num_pp;
495 int offset = 0;
496
497 for (int i = 0; i < num_pp; i++) {
498 off[i] = offset;
499
500 offset += delta;
501 if (remain) {
502 offset += 16;
503 remain--;
504 }
505 offset = align(offset, 0x20);
506 }
507
508 return offset;
509 }
510
511 static bool
512 inside_damage_region(int x, int y, struct lima_damage_state *ds)
513 {
514 if (!ds->region)
515 return true;
516
517 for (int i = 0; i < ds->num_region; i++) {
518 struct pipe_scissor_state *ss = ds->region + i;
519 if (x >= ss->minx && x < ss->maxx &&
520 y >= ss->miny && y < ss->maxy)
521 return true;
522 }
523
524 return false;
525 }
526
527 static void
528 lima_update_pp_stream(struct lima_context *ctx, int off_x, int off_y,
529 int tiled_w, int tiled_h)
530 {
531 struct lima_pp_stream_state *ps = &ctx->pp_stream;
532 struct lima_context_framebuffer *fb = &ctx->framebuffer;
533 struct lima_screen *screen = lima_screen(ctx->base.screen);
534 int i, num_pp = screen->num_pp;
535
536 /* use hilbert_coords to generates 1D to 2D relationship.
537 * 1D for pp stream index and 2D for plb block x/y on framebuffer.
538 * if multi pp, interleave the 1D index to make each pp's render target
539 * close enough which should result close workload
540 */
541 int max = MAX2(tiled_w, tiled_h);
542 int dim = util_logbase2_ceil(max);
543 int count = 1 << (dim + dim);
544 int index = 0;
545 uint32_t *stream[4];
546 int si[4] = {0};
547
548 for (i = 0; i < num_pp; i++)
549 stream[i] = ps->bo->map + ps->bo_offset + ps->offset[i];
550
551 for (i = 0; i < count; i++) {
552 int x, y;
553 hilbert_coords(max, i, &x, &y);
554 if (x < tiled_w && y < tiled_h) {
555 x += off_x;
556 y += off_y;
557
558 if (!inside_damage_region(x, y, &ctx->damage))
559 continue;
560
561 int pp = index % num_pp;
562 int offset = ((y >> fb->shift_h) * fb->block_w +
563 (x >> fb->shift_w)) * LIMA_CTX_PLB_BLK_SIZE;
564 int plb_va = ctx->plb[ctx->plb_index]->va + offset;
565
566 stream[pp][si[pp]++] = 0;
567 stream[pp][si[pp]++] = 0xB8000000 | x | (y << 8);
568 stream[pp][si[pp]++] = 0xE0000002 | ((plb_va >> 3) & ~0xE0000003);
569 stream[pp][si[pp]++] = 0xB0000000;
570
571 index++;
572 }
573 }
574
575 for (i = 0; i < num_pp; i++) {
576 stream[i][si[i]++] = 0;
577 stream[i][si[i]++] = 0xBC000000;
578
579 lima_dump_command_stream_print(
580 stream[i], si[i] * 4, false, "pp plb stream %d at va %x\n",
581 i, ps->bo->va + ps->bo_offset + ps->offset[i]);
582 }
583 }
584
585 static void
586 lima_update_damage_pp_stream(struct lima_context *ctx)
587 {
588 struct lima_damage_state *ds = &ctx->damage;
589 struct pipe_scissor_state max = ds->region[0];
590
591 /* find a max region to cover all the damage region */
592 for (int i = 1; i < ds->num_region; i++) {
593 struct pipe_scissor_state *ss = ds->region + i;
594 max.minx = MIN2(max.minx, ss->minx);
595 max.miny = MIN2(max.miny, ss->miny);
596 max.maxx = MAX2(max.maxx, ss->maxx);
597 max.maxy = MAX2(max.maxy, ss->maxy);
598 }
599
600 int tiled_w = max.maxx - max.minx;
601 int tiled_h = max.maxy - max.miny;
602 struct lima_screen *screen = lima_screen(ctx->base.screen);
603 int size = lima_get_pp_stream_size(
604 screen->num_pp, tiled_w, tiled_h, ctx->pp_stream.offset);
605
606 void *cpu;
607 unsigned offset;
608 struct pipe_resource *pres = NULL;
609 u_upload_alloc(ctx->uploader, 0, size, 0x40, &offset, &pres, &cpu);
610
611 struct lima_resource *res = lima_resource(pres);
612 ctx->pp_stream.bo = res->bo;
613 ctx->pp_stream.bo_offset = offset;
614
615 lima_update_pp_stream(ctx, max.minx, max.miny, tiled_w, tiled_h);
616
617 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_READ);
618 pipe_resource_reference(&pres, NULL);
619 }
620
621 static void
622 lima_update_full_pp_stream(struct lima_context *ctx)
623 {
624 struct lima_context_framebuffer *fb = &ctx->framebuffer;
625 struct lima_ctx_plb_pp_stream_key key = {
626 .plb_index = ctx->plb_index,
627 .tiled_w = fb->tiled_w,
628 .tiled_h = fb->tiled_h,
629 };
630
631 struct hash_entry *entry =
632 _mesa_hash_table_search(ctx->plb_pp_stream, &key);
633 struct lima_ctx_plb_pp_stream *s = entry->data;
634
635 if (s->bo) {
636 ctx->pp_stream.bo = s->bo;
637 ctx->pp_stream.bo_offset = 0;
638 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
639 }
640 else {
641 struct lima_screen *screen = lima_screen(ctx->base.screen);
642 int size = lima_get_pp_stream_size(
643 screen->num_pp, fb->tiled_w, fb->tiled_h, s->offset);
644 s->bo = lima_bo_create(screen, size, 0);
645 lima_bo_map(s->bo);
646
647 ctx->pp_stream.bo = s->bo;
648 ctx->pp_stream.bo_offset = 0;
649 memcpy(ctx->pp_stream.offset, s->offset, sizeof(s->offset));
650
651 lima_update_pp_stream(ctx, 0, 0, fb->tiled_w, fb->tiled_h);
652 }
653
654 lima_submit_add_bo(ctx->pp_submit, s->bo, LIMA_SUBMIT_BO_READ);
655 }
656
657 static void
658 lima_update_submit_bo(struct lima_context *ctx)
659 {
660 if (lima_ctx_dirty(ctx))
661 return;
662
663 struct lima_screen *screen = lima_screen(ctx->base.screen);
664 lima_submit_add_bo(ctx->gp_submit, ctx->plb_gp_stream, LIMA_SUBMIT_BO_READ);
665 lima_submit_add_bo(ctx->gp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
666 lima_submit_add_bo(ctx->gp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_WRITE);
667
668 lima_dump_command_stream_print(
669 ctx->plb_gp_stream->map + ctx->plb_index * ctx->plb_gp_size,
670 ctx->plb_gp_size, false, "gp plb stream at va %x\n",
671 ctx->plb_gp_stream->va + ctx->plb_index * ctx->plb_gp_size);
672
673 if (ctx->damage.region)
674 lima_update_damage_pp_stream(ctx);
675 else if (ctx->plb_pp_stream)
676 lima_update_full_pp_stream(ctx);
677 else
678 ctx->pp_stream.bo = NULL;
679
680 if (ctx->framebuffer.base.nr_cbufs) {
681 struct lima_resource *res = lima_resource(ctx->framebuffer.base.cbufs[0]->texture);
682 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
683 }
684 if (ctx->framebuffer.base.zsbuf) {
685 struct lima_resource *res = lima_resource(ctx->framebuffer.base.zsbuf->texture);
686 lima_submit_add_bo(ctx->pp_submit, res->bo, LIMA_SUBMIT_BO_WRITE);
687 }
688 lima_submit_add_bo(ctx->pp_submit, ctx->plb[ctx->plb_index], LIMA_SUBMIT_BO_READ);
689 lima_submit_add_bo(ctx->pp_submit, ctx->gp_tile_heap[ctx->plb_index], LIMA_SUBMIT_BO_READ);
690 lima_submit_add_bo(ctx->pp_submit, screen->pp_buffer, LIMA_SUBMIT_BO_READ);
691 }
692
693 static void
694 lima_clear(struct pipe_context *pctx, unsigned buffers,
695 const union pipe_color_union *color, double depth, unsigned stencil)
696 {
697 struct lima_context *ctx = lima_context(pctx);
698 bool full_fb_clear = lima_is_scissor_full_fb(ctx);
699
700 if (full_fb_clear) {
701 lima_flush(ctx);
702
703 /* no need to reload if cleared */
704 if (ctx->framebuffer.base.nr_cbufs && (buffers & PIPE_CLEAR_COLOR0)) {
705 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
706 surf->reload = false;
707 }
708 }
709
710 struct lima_context_clear *clear = &ctx->clear;
711 clear->buffers = buffers;
712
713 if (buffers & PIPE_CLEAR_COLOR0) {
714 clear->color_8pc =
715 ((uint32_t)float_to_ubyte(color->f[3]) << 24) |
716 ((uint32_t)float_to_ubyte(color->f[2]) << 16) |
717 ((uint32_t)float_to_ubyte(color->f[1]) << 8) |
718 float_to_ubyte(color->f[0]);
719
720 clear->color_16pc =
721 ((uint64_t)float_to_ushort(color->f[3]) << 48) |
722 ((uint64_t)float_to_ushort(color->f[2]) << 32) |
723 ((uint64_t)float_to_ushort(color->f[1]) << 16) |
724 float_to_ushort(color->f[0]);
725 }
726
727 if (buffers & PIPE_CLEAR_DEPTH)
728 clear->depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth);
729
730 if (buffers & PIPE_CLEAR_STENCIL)
731 clear->stencil = stencil;
732
733 lima_update_submit_bo(ctx);
734
735 lima_pack_head_plbu_cmd(ctx);
736
737 /* partial clear */
738 if (!full_fb_clear)
739 lima_pack_clear_plbu_cmd(ctx);
740
741 ctx->dirty |= LIMA_CONTEXT_DIRTY_CLEAR;
742 }
743
744 enum lima_attrib_type {
745 LIMA_ATTRIB_FLOAT = 0x000,
746 /* todo: find out what lives here. */
747 LIMA_ATTRIB_I16 = 0x004,
748 LIMA_ATTRIB_U16 = 0x005,
749 LIMA_ATTRIB_I8 = 0x006,
750 LIMA_ATTRIB_U8 = 0x007,
751 LIMA_ATTRIB_I8N = 0x008,
752 LIMA_ATTRIB_U8N = 0x009,
753 LIMA_ATTRIB_I16N = 0x00A,
754 LIMA_ATTRIB_U16N = 0x00B,
755 /* todo: where is the 32 int */
756 /* todo: find out what lives here. */
757 LIMA_ATTRIB_FIXED = 0x101
758 };
759
760 static enum lima_attrib_type
761 lima_pipe_format_to_attrib_type(enum pipe_format format)
762 {
763 const struct util_format_description *desc = util_format_description(format);
764 int i = util_format_get_first_non_void_channel(format);
765 const struct util_format_channel_description *c = desc->channel + i;
766
767 switch (c->type) {
768 case UTIL_FORMAT_TYPE_FLOAT:
769 return LIMA_ATTRIB_FLOAT;
770 case UTIL_FORMAT_TYPE_FIXED:
771 return LIMA_ATTRIB_FIXED;
772 case UTIL_FORMAT_TYPE_SIGNED:
773 if (c->size == 8) {
774 if (c->normalized)
775 return LIMA_ATTRIB_I8N;
776 else
777 return LIMA_ATTRIB_I8;
778 }
779 else if (c->size == 16) {
780 if (c->normalized)
781 return LIMA_ATTRIB_I16N;
782 else
783 return LIMA_ATTRIB_I16;
784 }
785 break;
786 case UTIL_FORMAT_TYPE_UNSIGNED:
787 if (c->size == 8) {
788 if (c->normalized)
789 return LIMA_ATTRIB_U8N;
790 else
791 return LIMA_ATTRIB_U8;
792 }
793 else if (c->size == 16) {
794 if (c->normalized)
795 return LIMA_ATTRIB_U16N;
796 else
797 return LIMA_ATTRIB_U16;
798 }
799 break;
800 }
801
802 return LIMA_ATTRIB_FLOAT;
803 }
804
805 static void
806 lima_pack_vs_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
807 {
808 VS_CMD_BEGIN(24);
809
810 if (!info->index_size) {
811 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_1();
812 VS_CMD_ARRAYS_SEMAPHORE_BEGIN_2();
813 }
814
815 int uniform_size = ctx->vs->uniform_pending_offset + ctx->vs->constant_size + 32;
816 VS_CMD_UNIFORMS_ADDRESS(
817 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, LIMA_CTX_BUFF_SUBMIT_GP),
818 align(uniform_size, 16));
819
820 VS_CMD_SHADER_ADDRESS(ctx->vs->bo->va, ctx->vs->shader_size);
821 VS_CMD_SHADER_INFO(ctx->vs->prefetch, ctx->vs->shader_size);
822
823 int num_varryings = ctx->vs->num_varying;
824 int num_attributes = ctx->vertex_elements->num_elements;
825 VS_CMD_VARYING_ATTRIBUTE_COUNT(num_varryings, num_attributes);
826
827 VS_CMD_UNKNOWN1();
828
829 VS_CMD_ATTRIBUTES_ADDRESS(
830 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, LIMA_CTX_BUFF_SUBMIT_GP),
831 num_attributes);
832
833 VS_CMD_VARYINGS_ADDRESS(
834 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, LIMA_CTX_BUFF_SUBMIT_GP),
835 num_varryings);
836
837 unsigned num = info->index_size ? (ctx->max_index - ctx->min_index + 1) : info->count;
838 VS_CMD_DRAW(num, info->index_size);
839
840 VS_CMD_UNKNOWN2();
841
842 VS_CMD_ARRAYS_SEMAPHORE_END(info->index_size);
843
844 VS_CMD_END();
845 }
846
847 static void
848 lima_pack_plbu_cmd(struct lima_context *ctx, const struct pipe_draw_info *info)
849 {
850 lima_pack_head_plbu_cmd(ctx);
851
852 /* If it's zero scissor, we skip adding all other commands */
853 if (lima_is_scissor_zero(ctx))
854 return;
855
856 PLBU_CMD_BEGIN(30);
857
858 PLBU_CMD_VIEWPORT_X(fui(ctx->viewport.x));
859 PLBU_CMD_VIEWPORT_W(fui(ctx->viewport.width));
860 PLBU_CMD_VIEWPORT_Y(fui(ctx->viewport.y));
861 PLBU_CMD_VIEWPORT_H(fui(ctx->viewport.height));
862
863 if (!info->index_size)
864 PLBU_CMD_ARRAYS_SEMAPHORE_BEGIN();
865
866 bool low_prim = info->mode < PIPE_PRIM_TRIANGLES;
867 int cf = ctx->rasterizer->base.cull_face;
868 int ccw = ctx->rasterizer->base.front_ccw;
869 uint32_t cull = 0;
870 if (cf != PIPE_FACE_NONE) {
871 if (cf & PIPE_FACE_FRONT)
872 cull |= ccw ? 0x00040000 : 0x00020000;
873 if (cf & PIPE_FACE_BACK)
874 cull |= ccw ? 0x00020000 : 0x00040000;
875 }
876 PLBU_CMD_PRIMITIVE_SETUP(low_prim, cull, info->index_size);
877
878 uint32_t gl_position_va =
879 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
880 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
881 PLBU_CMD_RSW_VERTEX_ARRAY(
882 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, LIMA_CTX_BUFF_SUBMIT_PP),
883 gl_position_va);
884
885 /* TODO
886 * - we should set it only for the first draw that enabled the scissor and for
887 * latter draw only if scissor is dirty
888 */
889 if (ctx->rasterizer->base.scissor) {
890 struct pipe_scissor_state *scissor = &ctx->scissor;
891 PLBU_CMD_SCISSORS(scissor->minx, scissor->maxx, scissor->miny, scissor->maxy);
892 }
893
894 PLBU_CMD_UNKNOWN1();
895
896 PLBU_CMD_DEPTH_RANGE_NEAR(fui(ctx->viewport.near));
897 PLBU_CMD_DEPTH_RANGE_FAR(fui(ctx->viewport.far));
898
899 if (low_prim) {
900 uint32_t v = info->mode == PIPE_PRIM_POINTS ?
901 fui(ctx->rasterizer->base.point_size) : fui(ctx->rasterizer->base.line_width);
902 PLBU_CMD_LOW_PRIM_SIZE(v);
903 }
904
905 if (info->index_size) {
906 PLBU_CMD_INDEXED_DEST(gl_position_va);
907
908 struct pipe_resource *indexbuf = NULL;
909 unsigned index_offset = 0;
910 struct lima_resource *res;
911 if (info->has_user_indices) {
912 util_upload_index_buffer(&ctx->base, info, &indexbuf, &index_offset);
913 res = lima_resource(indexbuf);
914 }
915 else
916 res = lima_resource(info->index.resource);
917
918 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
919 PLBU_CMD_INDICES(res->bo->va + info->start * info->index_size + index_offset);
920
921 if (indexbuf)
922 pipe_resource_reference(&indexbuf, NULL);
923 }
924 else {
925 /* can this make the attribute info static? */
926 PLBU_CMD_DRAW_ARRAYS(info->mode, info->start, info->count);
927 }
928
929 PLBU_CMD_ARRAYS_SEMAPHORE_END();
930
931 if (info->index_size)
932 PLBU_CMD_DRAW_ELEMENTS(info->mode, ctx->min_index, info->count);
933
934 PLBU_CMD_END();
935 }
936
937 static int
938 lima_blend_func(enum pipe_blend_func pipe)
939 {
940 switch (pipe) {
941 case PIPE_BLEND_ADD:
942 return 2;
943 case PIPE_BLEND_SUBTRACT:
944 return 0;
945 case PIPE_BLEND_REVERSE_SUBTRACT:
946 return 1;
947 case PIPE_BLEND_MIN:
948 return 4;
949 case PIPE_BLEND_MAX:
950 return 5;
951 }
952 return -1;
953 }
954
955 static int
956 lima_blend_factor(enum pipe_blendfactor pipe)
957 {
958 switch (pipe) {
959 case PIPE_BLENDFACTOR_ONE:
960 return 11;
961 case PIPE_BLENDFACTOR_SRC_COLOR:
962 return 0;
963 case PIPE_BLENDFACTOR_SRC_ALPHA:
964 return 16;
965 case PIPE_BLENDFACTOR_DST_ALPHA:
966 return 17;
967 case PIPE_BLENDFACTOR_DST_COLOR:
968 return 1;
969 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
970 return 7;
971 case PIPE_BLENDFACTOR_CONST_COLOR:
972 return 2;
973 case PIPE_BLENDFACTOR_CONST_ALPHA:
974 return 18;
975 case PIPE_BLENDFACTOR_ZERO:
976 return 3;
977 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
978 return 8;
979 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
980 return 24;
981 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
982 return 25;
983 case PIPE_BLENDFACTOR_INV_DST_COLOR:
984 return 9;
985 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
986 return 10;
987 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
988 return 26;
989 case PIPE_BLENDFACTOR_SRC1_COLOR:
990 case PIPE_BLENDFACTOR_SRC1_ALPHA:
991 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
992 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
993 return -1; /* not support */
994 }
995 return -1;
996 }
997
998 static int
999 lima_calculate_alpha_blend(enum pipe_blend_func rgb_func, enum pipe_blend_func alpha_func,
1000 enum pipe_blendfactor rgb_src_factor, enum pipe_blendfactor rgb_dst_factor,
1001 enum pipe_blendfactor alpha_src_factor, enum pipe_blendfactor alpha_dst_factor)
1002 {
1003 return lima_blend_func(rgb_func) |
1004 (lima_blend_func(alpha_func) << 3) |
1005 (lima_blend_factor(rgb_src_factor) << 6) |
1006 (lima_blend_factor(rgb_dst_factor) << 11) |
1007 ((lima_blend_factor(alpha_src_factor) & 0xF) << 16) |
1008 ((lima_blend_factor(alpha_dst_factor) & 0xF) << 20) |
1009 0x0C000000; /* need check if this GLESv1 glAlphaFunc */
1010 }
1011
1012 static int
1013 lima_stencil_op(enum pipe_stencil_op pipe)
1014 {
1015 switch (pipe) {
1016 case PIPE_STENCIL_OP_KEEP:
1017 return 0;
1018 case PIPE_STENCIL_OP_ZERO:
1019 return 2;
1020 case PIPE_STENCIL_OP_REPLACE:
1021 return 1;
1022 case PIPE_STENCIL_OP_INCR:
1023 return 6;
1024 case PIPE_STENCIL_OP_DECR:
1025 return 7;
1026 case PIPE_STENCIL_OP_INCR_WRAP:
1027 return 4;
1028 case PIPE_STENCIL_OP_DECR_WRAP:
1029 return 5;
1030 case PIPE_STENCIL_OP_INVERT:
1031 return 3;
1032 }
1033 return -1;
1034 }
1035
1036 static int
1037 lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer_state *rst)
1038 {
1039 enum pipe_compare_func func = (depth->enabled ? depth->func : PIPE_FUNC_ALWAYS);
1040
1041 int offset_scale = 0;
1042
1043 //TODO: implement polygon offset
1044 #if 0
1045 if (rst->offset_scale < -32)
1046 offset_scale = -32;
1047 else if (rst->offset_scale > 31)
1048 offset_scale = 31;
1049 else
1050 offset_scale = rst->offset_scale * 4;
1051
1052 if (offset_scale < 0)
1053 offset_scale = 0x100 + offset_scale;
1054 #endif
1055
1056 return (depth->enabled && depth->writemask) |
1057 ((int)func << 1) |
1058 (offset_scale << 16) |
1059 0x30; /* find out what is this */
1060 }
1061
1062 static void
1063 lima_pack_render_state(struct lima_context *ctx, const struct pipe_draw_info *info)
1064 {
1065 struct lima_render_state *render =
1066 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_plb_rsw,
1067 sizeof(*render), true);
1068
1069 /* do hw support RGBA independ blend?
1070 * PIPE_CAP_INDEP_BLEND_ENABLE
1071 *
1072 * how to handle the no cbuf only zbuf case?
1073 */
1074 struct pipe_rt_blend_state *rt = ctx->blend->base.rt;
1075 render->blend_color_bg = float_to_ubyte(ctx->blend_color.color[2]) |
1076 (float_to_ubyte(ctx->blend_color.color[1]) << 16);
1077 render->blend_color_ra = float_to_ubyte(ctx->blend_color.color[0]) |
1078 (float_to_ubyte(ctx->blend_color.color[3]) << 16);
1079
1080 if (rt->blend_enable) {
1081 render->alpha_blend = lima_calculate_alpha_blend(rt->rgb_func, rt->alpha_func,
1082 rt->rgb_src_factor, rt->rgb_dst_factor,
1083 rt->alpha_src_factor, rt->alpha_dst_factor);
1084 }
1085 else {
1086 /*
1087 * Special handling for blending disabled.
1088 * Binary driver is generating the same alpha_value,
1089 * as when we would just enable blending, without changing/setting any blend equation/params.
1090 * Normaly in this case mesa would set all rt fields (func/factor) to zero.
1091 */
1092 render->alpha_blend = lima_calculate_alpha_blend(PIPE_BLEND_ADD, PIPE_BLEND_ADD,
1093 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO,
1094 PIPE_BLENDFACTOR_ONE, PIPE_BLENDFACTOR_ZERO);
1095 }
1096
1097 render->alpha_blend |= (rt->colormask & PIPE_MASK_RGBA) << 28;
1098
1099 struct pipe_rasterizer_state *rst = &ctx->rasterizer->base;
1100 struct pipe_depth_state *depth = &ctx->zsa->base.depth;
1101 render->depth_test = lima_calculate_depth_test(depth, rst);
1102
1103 /* overlap with plbu? any place can remove one? */
1104 render->depth_range = float_to_ushort(ctx->viewport.near) |
1105 (float_to_ushort(ctx->viewport.far) << 16);
1106
1107 #if 0
1108 struct pipe_stencil_state *stencil = ctx->zsa->base.stencil;
1109 struct pipe_stencil_ref *ref = &ctx->stencil_ref;
1110 render->stencil_front = stencil[0].func |
1111 (lima_stencil_op(stencil[0].fail_op) << 3) |
1112 (lima_stencil_op(stencil[0].zfail_op) << 6) |
1113 (lima_stencil_op(stencil[0].zpass_op) << 9) |
1114 (ref->ref_value[0] << 16) |
1115 (stencil[0].valuemask << 24);
1116 render->stencil_back = stencil[1].func |
1117 (lima_stencil_op(stencil[1].fail_op) << 3) |
1118 (lima_stencil_op(stencil[1].zfail_op) << 6) |
1119 (lima_stencil_op(stencil[1].zpass_op) << 9) |
1120 (ref->ref_value[1] << 16) |
1121 (stencil[1].valuemask << 24);
1122 #else
1123 render->stencil_front = 0xff000007;
1124 render->stencil_back = 0xff000007;
1125 #endif
1126
1127 /* seems not correct? */
1128 //struct pipe_alpha_state *alpha = &ctx->zsa->base.alpha;
1129 render->stencil_test = 0;
1130 //(stencil->enabled ? 0xFF : 0x00) | (float_to_ubyte(alpha->ref_value) << 16)
1131
1132 /* need more investigation */
1133 if (info->mode == PIPE_PRIM_POINTS)
1134 render->multi_sample = 0x0000F007;
1135 else if (info->mode < PIPE_PRIM_TRIANGLES)
1136 render->multi_sample = 0x0000F407;
1137 else
1138 render->multi_sample = 0x0000F807;
1139 if (ctx->framebuffer.base.samples)
1140 render->multi_sample |= 0x68;
1141
1142 render->shader_address =
1143 ctx->fs->bo->va | (((uint32_t *)ctx->fs->bo->map)[0] & 0x1F);
1144
1145 /* seems not needed */
1146 render->uniforms_address = 0x00000000;
1147
1148 render->textures_address = 0x00000000;
1149
1150 /* more investigation */
1151 render->aux0 = 0x00000300 | (ctx->vs->varying_stride >> 3);
1152 render->aux1 = 0x00003000;
1153
1154 if (ctx->tex_stateobj.num_samplers) {
1155 render->textures_address =
1156 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_tex_desc, LIMA_CTX_BUFF_SUBMIT_PP);
1157 render->aux0 |= ctx->tex_stateobj.num_samplers << 14;
1158 render->aux0 |= 0x20;
1159 }
1160
1161 if (ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer) {
1162 render->uniforms_address =
1163 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, LIMA_CTX_BUFF_SUBMIT_PP);
1164 render->uniforms_address |= ((ctx->buffer_state[lima_ctx_buff_pp_uniform].size) / 4 - 1);
1165 render->aux0 |= 0x80;
1166 render->aux1 |= 0x10000;
1167 }
1168
1169 if (ctx->vs->num_varying > 1) {
1170 render->varying_types = 0x00000000;
1171 render->varyings_address =
1172 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_PP);
1173 for (int i = 1; i < ctx->vs->num_varying; i++) {
1174 int val;
1175
1176 struct lima_varying_info *v = ctx->vs->varying + i;
1177 if (v->component_size == 4)
1178 val = v->components > 2 ? 0 : 1;
1179 else
1180 val = v->components > 2 ? 2 : 3;
1181
1182 int index = i - 1;
1183 if (index < 10)
1184 render->varying_types |= val << (3 * index);
1185 else if (index == 10) {
1186 render->varying_types |= val << 30;
1187 render->varyings_address |= val >> 2;
1188 }
1189 else if (index == 11)
1190 render->varyings_address |= val << 1;
1191 }
1192 }
1193 else {
1194 render->varying_types = 0x00000000;
1195 render->varyings_address = 0x00000000;
1196 }
1197
1198 lima_dump_command_stream_print(
1199 render, sizeof(*render), false, "add render state at va %x\n",
1200 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_plb_rsw, 0));
1201 }
1202
1203 static void
1204 lima_update_gp_attribute_info(struct lima_context *ctx, const struct pipe_draw_info *info)
1205 {
1206 struct lima_vertex_element_state *ve = ctx->vertex_elements;
1207 struct lima_context_vertex_buffer *vb = &ctx->vertex_buffers;
1208
1209 uint32_t *attribute =
1210 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_attribute_info,
1211 ve->num_elements * 8, true);
1212
1213 int n = 0;
1214 for (int i = 0; i < ve->num_elements; i++) {
1215 struct pipe_vertex_element *pve = ve->pipe + i;
1216
1217 assert(pve->vertex_buffer_index < vb->count);
1218 assert(vb->enabled_mask & (1 << pve->vertex_buffer_index));
1219
1220 struct pipe_vertex_buffer *pvb = vb->vb + pve->vertex_buffer_index;
1221 struct lima_resource *res = lima_resource(pvb->buffer.resource);
1222
1223 lima_submit_add_bo(ctx->gp_submit, res->bo, LIMA_SUBMIT_BO_READ);
1224
1225 unsigned start = info->index_size ? ctx->min_index : info->start;
1226 attribute[n++] = res->bo->va + pvb->buffer_offset + pve->src_offset
1227 + start * pvb->stride;
1228 attribute[n++] = (pvb->stride << 11) |
1229 (lima_pipe_format_to_attrib_type(pve->src_format) << 2) |
1230 (util_format_get_nr_components(pve->src_format) - 1);
1231 }
1232
1233 lima_dump_command_stream_print(
1234 attribute, n * 4, false, "update attribute info at va %x\n",
1235 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_attribute_info, 0));
1236 }
1237
1238 static void
1239 lima_update_gp_uniform(struct lima_context *ctx)
1240 {
1241 struct lima_context_constant_buffer *ccb =
1242 ctx->const_buffer + PIPE_SHADER_VERTEX;
1243 struct lima_vs_shader_state *vs = ctx->vs;
1244
1245 int size = vs->uniform_pending_offset + vs->constant_size + 32;
1246 void *vs_const_buff =
1247 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_uniform, size, true);
1248
1249 if (ccb->buffer)
1250 memcpy(vs_const_buff, ccb->buffer, ccb->size);
1251
1252 memcpy(vs_const_buff + vs->uniform_pending_offset,
1253 ctx->viewport.transform.scale,
1254 sizeof(ctx->viewport.transform.scale));
1255 memcpy(vs_const_buff + vs->uniform_pending_offset + 16,
1256 ctx->viewport.transform.translate,
1257 sizeof(ctx->viewport.transform.translate));
1258
1259 if (vs->constant)
1260 memcpy(vs_const_buff + vs->uniform_pending_offset + 32,
1261 vs->constant, vs->constant_size);
1262
1263 lima_dump_command_stream_print(
1264 vs_const_buff, size, true,
1265 "update gp uniform at va %x\n",
1266 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_uniform, 0));
1267 }
1268
1269 static void
1270 lima_update_pp_uniform(struct lima_context *ctx)
1271 {
1272 const float *const_buff = ctx->const_buffer[PIPE_SHADER_FRAGMENT].buffer;
1273 size_t const_buff_size = ctx->const_buffer[PIPE_SHADER_FRAGMENT].size / sizeof(float);
1274
1275 if (!const_buff)
1276 return;
1277
1278 uint16_t *fp16_const_buff =
1279 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform,
1280 const_buff_size * sizeof(uint16_t), true);
1281
1282 uint32_t *array =
1283 lima_ctx_buff_alloc(ctx, lima_ctx_buff_pp_uniform_array, 4, true);
1284
1285 for (int i = 0; i < const_buff_size; i++)
1286 fp16_const_buff[i] = util_float_to_half(const_buff[i]);
1287
1288 *array = lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, LIMA_CTX_BUFF_SUBMIT_PP);
1289
1290 lima_dump_command_stream_print(
1291 fp16_const_buff, const_buff_size * 2, false, "add pp uniform data at va %x\n",
1292 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform, 0));
1293 lima_dump_command_stream_print(
1294 array, 4, false, "add pp uniform info at va %x\n",
1295 lima_ctx_buff_va(ctx, lima_ctx_buff_pp_uniform_array, 0));
1296 }
1297
1298 static void
1299 lima_update_varying(struct lima_context *ctx, const struct pipe_draw_info *info)
1300 {
1301 struct lima_vs_shader_state *vs = ctx->vs;
1302
1303 uint32_t *varying =
1304 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_varying_info,
1305 vs->num_varying * 8, true);
1306 int n = 0;
1307
1308 /* should be LIMA_SUBMIT_BO_WRITE for GP, but each draw will use
1309 * different part of this bo, so no need to set exclusive constraint */
1310 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_gl_pos,
1311 4 * 4 * info->count, false);
1312
1313 /* for gl_Position */
1314 varying[n++] =
1315 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos,
1316 LIMA_CTX_BUFF_SUBMIT_GP | LIMA_CTX_BUFF_SUBMIT_PP);
1317 varying[n++] = 0x8020;
1318
1319 int offset = 0;
1320 for (int i = 1; i < vs->num_varying; i++) {
1321 struct lima_varying_info *v = vs->varying + i;
1322 int size = v->component_size * 4;
1323
1324 /* does component_size == 2 need to be 16 aligned? */
1325 if (v->component_size == 4)
1326 offset = align(offset, 16);
1327
1328 v->offset = offset;
1329 offset += size;
1330 }
1331 vs->varying_stride = align(offset, 16);
1332
1333 if (vs->num_varying > 1)
1334 lima_ctx_buff_alloc(ctx, lima_ctx_buff_sh_varying,
1335 vs->varying_stride * info->count, false);
1336
1337 for (int i = 1; i < vs->num_varying; i++) {
1338 struct lima_varying_info *v = vs->varying + i;
1339 varying[n++] =
1340 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_varying, LIMA_CTX_BUFF_SUBMIT_GP) +
1341 v->offset;
1342 varying[n++] = (vs->varying_stride << 11) | (v->components - 1) |
1343 (v->component_size == 2 ? 0x0C : 0);
1344 }
1345
1346 lima_dump_command_stream_print(
1347 varying, n * 4, false, "update varying info at va %x\n",
1348 lima_ctx_buff_va(ctx, lima_ctx_buff_gp_varying_info, 0));
1349 }
1350
1351 static void
1352 lima_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
1353 {
1354 /* check if draw mode and vertex/index count match,
1355 * otherwise gp will hang */
1356 if (!u_trim_pipe_prim(info->mode, (unsigned*)&info->count)) {
1357 debug_printf("draw mode and vertex/index count mismatch\n");
1358 return;
1359 }
1360
1361 struct lima_context *ctx = lima_context(pctx);
1362
1363 if (!ctx->vs || !ctx->fs) {
1364 debug_warn_once("no shader, skip draw\n");
1365 return;
1366 }
1367
1368 if (!lima_update_vs_state(ctx) || !lima_update_fs_state(ctx))
1369 return;
1370
1371 lima_dump_command_stream_print(
1372 ctx->vs->bo->map, ctx->vs->shader_size, false,
1373 "add vs at va %x\n", ctx->vs->bo->va);
1374
1375 lima_dump_command_stream_print(
1376 ctx->fs->bo->map, ctx->fs->shader_size, false,
1377 "add fs at va %x\n", ctx->fs->bo->va);
1378
1379 lima_submit_add_bo(ctx->gp_submit, ctx->vs->bo, LIMA_SUBMIT_BO_READ);
1380 lima_submit_add_bo(ctx->pp_submit, ctx->fs->bo, LIMA_SUBMIT_BO_READ);
1381
1382 lima_update_submit_bo(ctx);
1383
1384 /* Mali Utgard GPU always need min/max index info for index draw,
1385 * compute it if upper layer does not do for us */
1386 if (info->index_size && info->max_index == ~0u)
1387 u_vbuf_get_minmax_index(pctx, info, &ctx->min_index, &ctx->max_index);
1388 else {
1389 ctx->min_index = info->min_index;
1390 ctx->max_index = info->max_index;
1391 }
1392
1393 lima_update_gp_attribute_info(ctx, info);
1394
1395 if ((ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1396 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty) ||
1397 ctx->dirty & LIMA_CONTEXT_DIRTY_VIEWPORT ||
1398 ctx->dirty & LIMA_CONTEXT_DIRTY_SHADER_VERT) {
1399 lima_update_gp_uniform(ctx);
1400 ctx->const_buffer[PIPE_SHADER_VERTEX].dirty = false;
1401 }
1402
1403 lima_update_varying(ctx, info);
1404
1405 /* If it's zero scissor, don't build vs cmd list */
1406 if (!lima_is_scissor_zero(ctx))
1407 lima_pack_vs_cmd(ctx, info);
1408
1409 if (ctx->dirty & LIMA_CONTEXT_DIRTY_CONST_BUFF &&
1410 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty) {
1411 lima_update_pp_uniform(ctx);
1412 ctx->const_buffer[PIPE_SHADER_FRAGMENT].dirty = false;
1413 }
1414
1415 if (ctx->dirty & LIMA_CONTEXT_DIRTY_TEXTURES)
1416 lima_update_textures(ctx);
1417
1418 lima_pack_render_state(ctx, info);
1419 lima_pack_plbu_cmd(ctx, info);
1420
1421 ctx->dirty = 0;
1422 }
1423
1424 static void
1425 lima_finish_plbu_cmd(struct lima_context *ctx)
1426 {
1427 int i = 0;
1428 uint32_t *plbu_cmd = util_dynarray_grow_cap(&ctx->plbu_cmd_array, 2 * 4);
1429
1430 plbu_cmd[i++] = 0x00000000;
1431 plbu_cmd[i++] = 0x50000000; /* END */
1432
1433 ctx->plbu_cmd_array.size += i * 4;
1434 }
1435
1436 static void
1437 lima_pack_wb_zsbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1438 {
1439 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1440 struct lima_resource *res = lima_resource(fb->base.zsbuf->texture);
1441
1442 uint32_t format;
1443
1444 switch (fb->base.zsbuf->format) {
1445 case PIPE_FORMAT_Z16_UNORM:
1446 format = LIMA_PIXEL_FORMAT_Z16;
1447 break;
1448 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1449 case PIPE_FORMAT_Z24X8_UNORM:
1450 default:
1451 /* Assume Z24S8 */
1452 format = LIMA_PIXEL_FORMAT_Z24S8;
1453 break;
1454 }
1455
1456 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1457 wb[wb_idx].type = 0x01; /* 1 for depth, stencil */
1458 wb[wb_idx].address = res->bo->va;
1459 wb[wb_idx].pixel_format = format;
1460 if (res->tiled) {
1461 wb[wb_idx].pixel_layout = 0x2;
1462 wb[wb_idx].pitch = fb->tiled_w;
1463 } else {
1464 wb[wb_idx].pixel_layout = 0x0;
1465 wb[wb_idx].pitch = res->levels[0].stride / 8;
1466 }
1467 wb[wb_idx].mrt_bits = 0;
1468 }
1469
1470 static void
1471 lima_pack_wb_cbuf_reg(struct lima_context *ctx, uint32_t *wb_reg, int wb_idx)
1472 {
1473 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1474 struct lima_resource *res = lima_resource(fb->base.cbufs[0]->texture);
1475
1476 bool swap_channels = false;
1477 switch (fb->base.cbufs[0]->format) {
1478 case PIPE_FORMAT_R8G8B8A8_UNORM:
1479 case PIPE_FORMAT_R8G8B8X8_UNORM:
1480 swap_channels = true;
1481 break;
1482 default:
1483 break;
1484 }
1485
1486 struct lima_pp_wb_reg *wb = (void *)wb_reg;
1487 wb[wb_idx].type = 0x02; /* 2 for color buffer */
1488 wb[wb_idx].address = res->bo->va;
1489 wb[wb_idx].pixel_format = LIMA_PIXEL_FORMAT_B8G8R8A8;
1490 if (res->tiled) {
1491 wb[wb_idx].pixel_layout = 0x2;
1492 wb[wb_idx].pitch = fb->tiled_w;
1493 } else {
1494 wb[wb_idx].pixel_layout = 0x0;
1495 wb[wb_idx].pitch = res->levels[0].stride / 8;
1496 }
1497 wb[wb_idx].mrt_bits = swap_channels ? 0x4 : 0x0;
1498 }
1499
1500
1501 static void
1502 lima_pack_pp_frame_reg(struct lima_context *ctx, uint32_t *frame_reg,
1503 uint32_t *wb_reg)
1504 {
1505 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1506 struct lima_pp_frame_reg *frame = (void *)frame_reg;
1507 struct lima_screen *screen = lima_screen(ctx->base.screen);
1508 int wb_idx = 0;
1509
1510 frame->render_address = screen->pp_buffer->va + pp_frame_rsw_offset;
1511 frame->flags = 0x02;
1512 frame->clear_value_depth = ctx->clear.depth;
1513 frame->clear_value_stencil = ctx->clear.stencil;
1514 frame->clear_value_color = ctx->clear.color_8pc;
1515 frame->clear_value_color_1 = ctx->clear.color_8pc;
1516 frame->clear_value_color_2 = ctx->clear.color_8pc;
1517 frame->clear_value_color_3 = ctx->clear.color_8pc;
1518 frame->one = 1;
1519
1520 frame->width = fb->base.width - 1;
1521 frame->height = fb->base.height - 1;
1522
1523 /* frame->fragment_stack_address is overwritten per-pp in the kernel
1524 * by the values of pp_frame.fragment_stack_address[i] */
1525
1526 /* These are "stack size" and "stack offset" shifted,
1527 * here they are assumed to be always the same. */
1528 uint32_t fs_stack_size = ctx->fs ? ctx->fs->stack_size : 0;
1529 frame->fragment_stack_size = fs_stack_size << 16 | fs_stack_size;
1530
1531 /* related with MSAA and different value when r4p0/r7p0 */
1532 frame->supersampled_height = fb->base.height * 2 - 1;
1533 frame->scale = 0xE0C;
1534
1535 frame->dubya = 0x77;
1536 frame->onscreen = 1;
1537 frame->blocking = (fb->shift_min << 28) | (fb->shift_h << 16) | fb->shift_w;
1538 frame->foureight = 0x8888;
1539
1540 if (fb->base.nr_cbufs)
1541 lima_pack_wb_cbuf_reg(ctx, wb_reg, wb_idx++);
1542
1543 /* Mali4x0 can use on-tile buffer for depth/stencil, so to save some
1544 * memory bandwidth don't write depth/stencil back to memory if we're
1545 * rendering to scanout
1546 */
1547 if (!lima_is_scanout(ctx) && fb->base.zsbuf)
1548 lima_pack_wb_zsbuf_reg(ctx, wb_reg, wb_idx++);
1549 }
1550
1551 static void
1552 _lima_flush(struct lima_context *ctx, bool end_of_frame)
1553 {
1554 lima_finish_plbu_cmd(ctx);
1555
1556 int vs_cmd_size = ctx->vs_cmd_array.size;
1557 int plbu_cmd_size = ctx->plbu_cmd_array.size;
1558 uint32_t vs_cmd_va = 0;
1559 uint32_t plbu_cmd_va;
1560
1561 if (vs_cmd_size) {
1562 void *vs_cmd =
1563 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_vs_cmd, vs_cmd_size, true);
1564 memcpy(vs_cmd, util_dynarray_begin(&ctx->vs_cmd_array), vs_cmd_size);
1565 util_dynarray_clear(&ctx->vs_cmd_array);
1566 vs_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_vs_cmd,
1567 LIMA_CTX_BUFF_SUBMIT_GP);
1568
1569 lima_dump_command_stream_print(
1570 vs_cmd, vs_cmd_size, false, "flush vs cmd at va %x\n", vs_cmd_va);
1571 }
1572
1573 void *plbu_cmd =
1574 lima_ctx_buff_alloc(ctx, lima_ctx_buff_gp_plbu_cmd, plbu_cmd_size, true);
1575 memcpy(plbu_cmd, util_dynarray_begin(&ctx->plbu_cmd_array), plbu_cmd_size);
1576 util_dynarray_clear(&ctx->plbu_cmd_array);
1577 plbu_cmd_va = lima_ctx_buff_va(ctx, lima_ctx_buff_gp_plbu_cmd,
1578 LIMA_CTX_BUFF_SUBMIT_GP);
1579
1580 lima_dump_command_stream_print(
1581 plbu_cmd, plbu_cmd_size, false, "flush plbu cmd at va %x\n", plbu_cmd_va);
1582
1583 struct lima_screen *screen = lima_screen(ctx->base.screen);
1584 struct drm_lima_gp_frame gp_frame;
1585 struct lima_gp_frame_reg *gp_frame_reg = (void *)gp_frame.frame;
1586 gp_frame_reg->vs_cmd_start = vs_cmd_va;
1587 gp_frame_reg->vs_cmd_end = vs_cmd_va + vs_cmd_size;
1588 gp_frame_reg->plbu_cmd_start = plbu_cmd_va;
1589 gp_frame_reg->plbu_cmd_end = plbu_cmd_va + plbu_cmd_size;
1590 gp_frame_reg->tile_heap_start = ctx->gp_tile_heap[ctx->plb_index]->va;
1591 gp_frame_reg->tile_heap_end = ctx->gp_tile_heap[ctx->plb_index]->va + gp_tile_heap_size;
1592
1593 lima_dump_command_stream_print(
1594 &gp_frame, sizeof(gp_frame), false, "add gp frame\n");
1595
1596 if (!lima_submit_start(ctx->gp_submit, &gp_frame, sizeof(gp_frame)))
1597 fprintf(stderr, "gp submit error\n");
1598
1599 if (lima_dump_command_stream) {
1600 if (lima_submit_wait(ctx->gp_submit, PIPE_TIMEOUT_INFINITE)) {
1601 if (ctx->buffer_state[lima_ctx_buff_sh_gl_pos].res) {
1602 float *pos = lima_ctx_buff_map(ctx, lima_ctx_buff_sh_gl_pos);
1603 lima_dump_command_stream_print(
1604 pos, 4 * 4 * 16, true, "gl_pos dump at va %x\n",
1605 lima_ctx_buff_va(ctx, lima_ctx_buff_sh_gl_pos, 0));
1606 }
1607
1608 uint32_t *plb = lima_bo_map(ctx->plb[ctx->plb_index]);
1609 lima_dump_command_stream_print(
1610 plb, LIMA_CTX_PLB_BLK_SIZE, false, "plb dump at va %x\n",
1611 ctx->plb[ctx->plb_index]->va);
1612 }
1613 else {
1614 fprintf(stderr, "gp submit wait error\n");
1615 exit(1);
1616 }
1617 }
1618
1619 struct lima_pp_stream_state *ps = &ctx->pp_stream;
1620 if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI400) {
1621 struct drm_lima_m400_pp_frame pp_frame = {0};
1622 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1623 pp_frame.num_pp = screen->num_pp;
1624
1625 for (int i = 0; i < screen->num_pp; i++) {
1626 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1627 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1628 pp_stack_offset + pp_stack_pp_size * i;
1629 }
1630
1631 lima_dump_command_stream_print(
1632 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1633
1634 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1635 fprintf(stderr, "pp submit error\n");
1636 }
1637 else {
1638 struct drm_lima_m450_pp_frame pp_frame = {0};
1639 lima_pack_pp_frame_reg(ctx, pp_frame.frame, pp_frame.wb);
1640 pp_frame.num_pp = screen->num_pp;
1641
1642 for (int i = 0; i < screen->num_pp; i++)
1643 pp_frame.fragment_stack_address[i] = screen->pp_buffer->va +
1644 pp_stack_offset + pp_stack_pp_size * i;
1645
1646 if (ps->bo) {
1647 for (int i = 0; i < screen->num_pp; i++)
1648 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1649 }
1650 else {
1651 pp_frame.use_dlbu = true;
1652
1653 struct lima_context_framebuffer *fb = &ctx->framebuffer;
1654 pp_frame.dlbu_regs[0] = ctx->plb[ctx->plb_index]->va;
1655 pp_frame.dlbu_regs[1] = ((fb->tiled_h - 1) << 16) | (fb->tiled_w - 1);
1656 unsigned s = util_logbase2(LIMA_CTX_PLB_BLK_SIZE) - 7;
1657 pp_frame.dlbu_regs[2] = (s << 28) | (fb->shift_h << 16) | fb->shift_w;
1658 pp_frame.dlbu_regs[3] = ((fb->tiled_h - 1) << 24) | ((fb->tiled_w - 1) << 16);
1659 }
1660
1661 lima_dump_command_stream_print(
1662 &pp_frame, sizeof(pp_frame), false, "add pp frame\n");
1663
1664 if (!lima_submit_start(ctx->pp_submit, &pp_frame, sizeof(pp_frame)))
1665 fprintf(stderr, "pp submit error\n");
1666 }
1667
1668 if (lima_dump_command_stream) {
1669 if (!lima_submit_wait(ctx->pp_submit, PIPE_TIMEOUT_INFINITE)) {
1670 fprintf(stderr, "pp wait error\n");
1671 exit(1);
1672 }
1673 }
1674
1675 ctx->plb_index = (ctx->plb_index + 1) % lima_ctx_num_plb;
1676
1677 if (ctx->framebuffer.base.nr_cbufs) {
1678 /* Set reload flag for next draw. It'll be unset if buffer is cleared */
1679 struct lima_surface *surf = lima_surface(ctx->framebuffer.base.cbufs[0]);
1680 surf->reload = true;
1681 }
1682 }
1683
1684 void
1685 lima_flush(struct lima_context *ctx)
1686 {
1687 if (!lima_ctx_dirty(ctx))
1688 return;
1689
1690 _lima_flush(ctx, false);
1691 }
1692
1693 static void
1694 lima_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
1695 unsigned flags)
1696 {
1697 struct lima_context *ctx = lima_context(pctx);
1698 if (!lima_ctx_dirty(ctx))
1699 return;
1700
1701 _lima_flush(ctx, flags & PIPE_FLUSH_END_OF_FRAME);
1702
1703 if (fence) {
1704 int fd;
1705 if (lima_submit_get_out_sync(ctx->pp_submit, &fd))
1706 *fence = lima_fence_create(fd);
1707 }
1708 }
1709
1710 void
1711 lima_draw_init(struct lima_context *ctx)
1712 {
1713 ctx->base.clear = lima_clear;
1714 ctx->base.draw_vbo = lima_draw_vbo;
1715 ctx->base.flush = lima_pipe_flush;
1716 }