src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __NV50_IR_DRIVER_H__
  24 #define __NV50_IR_DRIVER_H__
  25
  26 #include "pipe/p_shader_tokens.h"
  27
  28 #include "tgsi/tgsi_util.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_scan.h"
  31
  32 /*
  33  * This struct constitutes linkage information in TGSI terminology.
  34  *
  35  * It is created by the code generator and handed to the pipe driver
  36  * for input/output slot assignment.
  37  */
  38 struct nv50_ir_varying
  39 {
  40    uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */
  41
  42    unsigned mask     : 4; /* vec4 mask */
  43    unsigned linear   : 1; /* linearly interpolated if true (and not flat) */
  44    unsigned flat     : 1;
  45    unsigned sc       : 1; /* special colour interpolation mode (SHADE_MODEL) */
  46    unsigned centroid : 1;
  47    unsigned patch    : 1; /* patch constant value */
  48    unsigned regular  : 1; /* driver-specific meaning (e.g. input in sreg) */
  49    unsigned input    : 1; /* indicates direction of system values */
  50    unsigned oread    : 1; /* true if output is read from parallel TCP */
  51
  52    ubyte id; /* TGSI register index */
  53    ubyte sn; /* TGSI semantic name */
  54    ubyte si; /* TGSI semantic index */
  55 };
  56
  57 #ifndef NDEBUG
  58 # define NV50_IR_DEBUG_BASIC     (1 << 0)
  59 # define NV50_IR_DEBUG_VERBOSE   (2 << 0)
  60 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
  61 #else
  62 # define NV50_IR_DEBUG_BASIC     0
  63 # define NV50_IR_DEBUG_VERBOSE   0
  64 # define NV50_IR_DEBUG_REG_ALLOC 0
  65 #endif
  66
  67 struct nv50_ir_prog_symbol
  68 {
  69    uint32_t label;
  70    uint32_t offset;
  71 };
  72
  73 #define NVISA_GK104_CHIPSET    0xe0
  74 #define NVISA_GK20A_CHIPSET    0xea
  75 #define NVISA_GM107_CHIPSET    0x110
  76 #define NVISA_GM200_CHIPSET    0x120
  77
  78 struct nv50_ir_prog_info
  79 {
  80    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
  81
  82    uint8_t type; /* PIPE_SHADER */
  83
  84    uint8_t optLevel; /* optimization level (0 to 3) */
  85    uint8_t dbgFlags;
  86    bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
  87
  88    struct {
  89       int16_t maxGPR;     /* may be -1 if none used */
  90       int16_t maxOutput;
  91       uint32_t tlsSpace;  /* required local memory per thread */
  92       uint32_t smemSize;  /* required shared memory per block */
  93       uint32_t *code;
  94       uint32_t codeSize;
  95       uint32_t instructions;
  96       uint8_t sourceRep;  /* PIPE_SHADER_IR_* */
  97       const void *source;
  98       void *relocData;
  99       void *fixupData;
 100       struct nv50_ir_prog_symbol *syms;
 101       uint16_t numSyms;
 102    } bin;
 103
 104    struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
 105    struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS];
 106    struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS];
 107    uint8_t numInputs;
 108    uint8_t numOutputs;
 109    uint8_t numPatchConstants; /* also included in numInputs/numOutputs */
 110    uint8_t numSysVals;
 111
 112    struct {
 113       uint32_t *buf;    /* for IMMEDIATE_ARRAY */
 114       uint16_t bufSize; /* size of immediate array */
 115       uint16_t count;   /* count of inline immediates */
 116       uint32_t *data;   /* inline immediate data */
 117       uint8_t *type;    /* for each vec4 (128 bit) */
 118    } immd;
 119
 120    union {
 121       struct {
 122          uint32_t inputMask[4]; /* mask of attributes read (1 bit per scalar) */
 123          bool usesDrawParameters;
 124       } vp;
 125       struct {
 126          uint8_t outputPatchSize;
 127          uint8_t partitioning;    /* PIPE_TESS_PART */
 128          int8_t winding;          /* +1 (clockwise) / -1 (counter-clockwise) */
 129          uint8_t domain;          /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */
 130          uint8_t outputPrim;      /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */
 131       } tp;
 132       struct {
 133          uint8_t inputPrim;
 134          uint8_t outputPrim;
 135          unsigned instanceCount;
 136          unsigned maxVertices;
 137       } gp;
 138       struct {
 139          unsigned numColourResults;
 140          bool writesDepth;
 141          bool earlyFragTests;
 142          bool postDepthCoverage;
 143          bool separateFragData;
 144          bool usesDiscard;
 145          bool persampleInvocation;
 146          bool usesSampleMaskIn;
 147          bool readsFramebuffer;
 148          bool readsSampleLocations;
 149       } fp;
 150       struct {
 151          uint32_t inputOffset; /* base address for user args */
 152          uint32_t sharedOffset; /* reserved space in s[] */
 153          uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
 154          uint16_t numThreads[3]; /* max number of threads */
 155       } cp;
 156    } prop;
 157
 158    uint8_t numBarriers;
 159
 160    struct {
 161       uint8_t clipDistances;     /* number of clip distance outputs */
 162       uint8_t cullDistances;     /* number of cull distance outputs */
 163       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 164       uint8_t auxCBSlot;         /* driver constant buffer slot */
 165       uint16_t ucpBase;          /* base address for UCPs */
 166       uint16_t drawInfoBase;     /* base address for draw parameters */
 167       uint16_t alphaRefBase;     /* base address for alpha test values */
 168       uint8_t pointSize;         /* output index for PointSize */
 169       uint8_t instanceId;        /* system value index of InstanceID */
 170       uint8_t vertexId;          /* system value index of VertexID */
 171       uint8_t edgeFlagIn;
 172       uint8_t edgeFlagOut;
 173       int8_t viewportId;         /* output index of ViewportIndex */
 174       uint8_t fragDepth;         /* output index of FragDepth */
 175       uint8_t sampleMask;        /* output index of SampleMask */
 176       uint8_t backFaceColor[2];  /* input/output indices of back face colour */
 177       uint8_t globalAccess;      /* 1 for read, 2 for wr, 3 for rw */
 178       bool fp64;                 /* program uses fp64 math */
 179       bool mul_zero_wins;        /* program wants for x*0 = 0 */
 180       bool nv50styleSurfaces;    /* generate gX[] access for raw buffers */
 181       uint16_t texBindBase;      /* base address for tex handles (nve4) */
 182       uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
 183       uint16_t suInfoBase;       /* base address for surface info (nve4) */
 184       uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
 185       uint16_t bufInfoBase;      /* base address for buffer info */
 186       uint16_t sampleInfoBase;   /* base address for sample positions */
 187       uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
 188       uint16_t msInfoBase;       /* base address for multisample info */
 189       uint16_t uboInfoBase;      /* base address for compute UBOs (gk104+) */
 190    } io;
 191
 192    /* driver callback to assign input/output locations */
 193    int (*assignSlots)(struct nv50_ir_prog_info *);
 194
 195    void *driverPriv;
 196 };
 197
 198 #ifdef __cplusplus
 199 extern "C" {
 200 #endif
 201
 202 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *);
 203
 204 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
 205                                   uint32_t codePos,
 206                                   uint32_t libPos,
 207                                   uint32_t dataPos);
 208
 209 extern void
 210 nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
 211                      bool force_per_sample, bool flatshade,
 212                      uint8_t alphatest);
 213
 214 /* obtain code that will be shared among programs */
 215 extern void nv50_ir_get_target_library(uint32_t chipset,
 216                                        const uint32_t **code, uint32_t *size);
 217
 218 #ifdef __cplusplus
 219 }
 220 #endif
 221
 222 #endif // __NV50_IR_DRIVER_H__