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nvc0/ir: add support for emitting partial min/max ops for int64
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_gk110.cpp
1 /*
2 * Copyright 2012 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 // CodeEmitter for GK110 encoding of the Fermi/Kepler ISA.
26
27 namespace nv50_ir {
28
29 class CodeEmitterGK110 : public CodeEmitter
30 {
31 public:
32 CodeEmitterGK110(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
49 void emitForm_C(const Instruction *, uint32_t opc, uint8_t ctg);
50 void emitForm_L(const Instruction *, uint32_t opc, uint8_t ctg, Modifier);
51
52 void emitPredicate(const Instruction *);
53
54 void setCAddress14(const ValueRef&);
55 void setShortImmediate(const Instruction *, const int s);
56 void setImmediate32(const Instruction *, const int s, Modifier);
57 void setSUConst16(const Instruction *, const int s);
58
59 void modNegAbsF32_3b(const Instruction *, const int s);
60
61 void emitCondCode(CondCode cc, int pos, uint8_t mask);
62 void emitInterpMode(const Instruction *);
63 void emitLoadStoreType(DataType ty, const int pos);
64 void emitCachingMode(CacheMode c, const int pos);
65 void emitSUGType(DataType, const int pos);
66 void emitSUCachingMode(CacheMode c);
67
68 inline uint8_t getSRegEncoding(const ValueRef&);
69
70 void emitRoundMode(RoundMode, const int pos, const int rintPos);
71 void emitRoundModeF(RoundMode, const int pos);
72 void emitRoundModeI(RoundMode, const int pos);
73
74 void emitNegAbs12(const Instruction *);
75
76 void emitNOP(const Instruction *);
77
78 void emitLOAD(const Instruction *);
79 void emitSTORE(const Instruction *);
80 void emitMOV(const Instruction *);
81 void emitATOM(const Instruction *);
82 void emitCCTL(const Instruction *);
83
84 void emitINTERP(const Instruction *);
85 void emitAFETCH(const Instruction *);
86 void emitPFETCH(const Instruction *);
87 void emitVFETCH(const Instruction *);
88 void emitEXPORT(const Instruction *);
89 void emitOUT(const Instruction *);
90
91 void emitUADD(const Instruction *);
92 void emitFADD(const Instruction *);
93 void emitDADD(const Instruction *);
94 void emitIMUL(const Instruction *);
95 void emitFMUL(const Instruction *);
96 void emitDMUL(const Instruction *);
97 void emitIMAD(const Instruction *);
98 void emitISAD(const Instruction *);
99 void emitSHLADD(const Instruction *);
100 void emitFMAD(const Instruction *);
101 void emitDMAD(const Instruction *);
102 void emitMADSP(const Instruction *i);
103
104 void emitNOT(const Instruction *);
105 void emitLogicOp(const Instruction *, uint8_t subOp);
106 void emitPOPC(const Instruction *);
107 void emitINSBF(const Instruction *);
108 void emitEXTBF(const Instruction *);
109 void emitBFIND(const Instruction *);
110 void emitPERMT(const Instruction *);
111 void emitShift(const Instruction *);
112
113 void emitSFnOp(const Instruction *, uint8_t subOp);
114
115 void emitCVT(const Instruction *);
116 void emitMINMAX(const Instruction *);
117 void emitPreOp(const Instruction *);
118
119 void emitSET(const CmpInstruction *);
120 void emitSLCT(const CmpInstruction *);
121 void emitSELP(const Instruction *);
122
123 void emitTEXBAR(const Instruction *);
124 void emitTEX(const TexInstruction *);
125 void emitTEXCSAA(const TexInstruction *);
126 void emitTXQ(const TexInstruction *);
127
128 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
129
130 void emitPIXLD(const Instruction *);
131
132 void emitBAR(const Instruction *);
133 void emitMEMBAR(const Instruction *);
134
135 void emitFlow(const Instruction *);
136
137 void emitVOTE(const Instruction *);
138
139 void emitSULDGB(const TexInstruction *);
140 void emitSUSTGx(const TexInstruction *);
141 void emitSUCLAMPMode(uint16_t);
142 void emitSUCalc(Instruction *);
143
144 void emitVSHL(const Instruction *);
145 void emitVectorSubOp(const Instruction *);
146
147 inline void defId(const ValueDef&, const int pos);
148 inline void srcId(const ValueRef&, const int pos);
149 inline void srcId(const ValueRef *, const int pos);
150 inline void srcId(const Instruction *, int s, const int pos);
151
152 inline void srcAddr32(const ValueRef&, const int pos); // address / 4
153
154 inline bool isLIMM(const ValueRef&, DataType ty, bool mod = false);
155 };
156
157 #define GK110_GPR_ZERO 255
158
159 #define NEG_(b, s) \
160 if (i->src(s).mod.neg()) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
161 #define ABS_(b, s) \
162 if (i->src(s).mod.abs()) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
163
164 #define NOT_(b, s) if (i->src(s).mod & Modifier(NV50_IR_MOD_NOT)) \
165 code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
166
167 #define FTZ_(b) if (i->ftz) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
168 #define DNZ_(b) if (i->dnz) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
169
170 #define SAT_(b) if (i->saturate) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
171
172 #define RND_(b, t) emitRoundMode##t(i->rnd, 0x##b)
173
174 #define SDATA(a) ((a).rep()->reg.data)
175 #define DDATA(a) ((a).rep()->reg.data)
176
177 void CodeEmitterGK110::srcId(const ValueRef& src, const int pos)
178 {
179 code[pos / 32] |= (src.get() ? SDATA(src).id : GK110_GPR_ZERO) << (pos % 32);
180 }
181
182 void CodeEmitterGK110::srcId(const ValueRef *src, const int pos)
183 {
184 code[pos / 32] |= (src ? SDATA(*src).id : GK110_GPR_ZERO) << (pos % 32);
185 }
186
187 void CodeEmitterGK110::srcId(const Instruction *insn, int s, int pos)
188 {
189 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : GK110_GPR_ZERO;
190 code[pos / 32] |= r << (pos % 32);
191 }
192
193 void CodeEmitterGK110::srcAddr32(const ValueRef& src, const int pos)
194 {
195 code[pos / 32] |= (SDATA(src).offset >> 2) << (pos % 32);
196 }
197
198 void CodeEmitterGK110::defId(const ValueDef& def, const int pos)
199 {
200 code[pos / 32] |= (def.get() ? DDATA(def).id : GK110_GPR_ZERO) << (pos % 32);
201 }
202
203 bool CodeEmitterGK110::isLIMM(const ValueRef& ref, DataType ty, bool mod)
204 {
205 const ImmediateValue *imm = ref.get()->asImm();
206
207 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
208 }
209
210 void
211 CodeEmitterGK110::emitRoundMode(RoundMode rnd, const int pos, const int rintPos)
212 {
213 bool rint = false;
214 uint8_t n;
215
216 switch (rnd) {
217 case ROUND_MI: rint = true; /* fall through */ case ROUND_M: n = 1; break;
218 case ROUND_PI: rint = true; /* fall through */ case ROUND_P: n = 2; break;
219 case ROUND_ZI: rint = true; /* fall through */ case ROUND_Z: n = 3; break;
220 default:
221 rint = rnd == ROUND_NI;
222 n = 0;
223 assert(rnd == ROUND_N || rnd == ROUND_NI);
224 break;
225 }
226 code[pos / 32] |= n << (pos % 32);
227 if (rint && rintPos >= 0)
228 code[rintPos / 32] |= 1 << (rintPos % 32);
229 }
230
231 void
232 CodeEmitterGK110::emitRoundModeF(RoundMode rnd, const int pos)
233 {
234 uint8_t n;
235
236 switch (rnd) {
237 case ROUND_M: n = 1; break;
238 case ROUND_P: n = 2; break;
239 case ROUND_Z: n = 3; break;
240 default:
241 n = 0;
242 assert(rnd == ROUND_N);
243 break;
244 }
245 code[pos / 32] |= n << (pos % 32);
246 }
247
248 void
249 CodeEmitterGK110::emitRoundModeI(RoundMode rnd, const int pos)
250 {
251 uint8_t n;
252
253 switch (rnd) {
254 case ROUND_MI: n = 1; break;
255 case ROUND_PI: n = 2; break;
256 case ROUND_ZI: n = 3; break;
257 default:
258 n = 0;
259 assert(rnd == ROUND_NI);
260 break;
261 }
262 code[pos / 32] |= n << (pos % 32);
263 }
264
265 void CodeEmitterGK110::emitCondCode(CondCode cc, int pos, uint8_t mask)
266 {
267 uint8_t n;
268
269 switch (cc) {
270 case CC_FL: n = 0x00; break;
271 case CC_LT: n = 0x01; break;
272 case CC_EQ: n = 0x02; break;
273 case CC_LE: n = 0x03; break;
274 case CC_GT: n = 0x04; break;
275 case CC_NE: n = 0x05; break;
276 case CC_GE: n = 0x06; break;
277 case CC_LTU: n = 0x09; break;
278 case CC_EQU: n = 0x0a; break;
279 case CC_LEU: n = 0x0b; break;
280 case CC_GTU: n = 0x0c; break;
281 case CC_NEU: n = 0x0d; break;
282 case CC_GEU: n = 0x0e; break;
283 case CC_TR: n = 0x0f; break;
284 case CC_NO: n = 0x10; break;
285 case CC_NC: n = 0x11; break;
286 case CC_NS: n = 0x12; break;
287 case CC_NA: n = 0x13; break;
288 case CC_A: n = 0x14; break;
289 case CC_S: n = 0x15; break;
290 case CC_C: n = 0x16; break;
291 case CC_O: n = 0x17; break;
292 default:
293 n = 0;
294 assert(!"invalid condition code");
295 break;
296 }
297 code[pos / 32] |= (n & mask) << (pos % 32);
298 }
299
300 void
301 CodeEmitterGK110::emitPredicate(const Instruction *i)
302 {
303 if (i->predSrc >= 0) {
304 srcId(i->src(i->predSrc), 18);
305 if (i->cc == CC_NOT_P)
306 code[0] |= 8 << 18; // negate
307 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
308 } else {
309 code[0] |= 7 << 18;
310 }
311 }
312
313 void
314 CodeEmitterGK110::setCAddress14(const ValueRef& src)
315 {
316 const Storage& res = src.get()->asSym()->reg;
317 const int32_t addr = res.data.offset / 4;
318
319 code[0] |= (addr & 0x01ff) << 23;
320 code[1] |= (addr & 0x3e00) >> 9;
321 code[1] |= res.fileIndex << 5;
322 }
323
324 void
325 CodeEmitterGK110::setShortImmediate(const Instruction *i, const int s)
326 {
327 const uint32_t u32 = i->getSrc(s)->asImm()->reg.data.u32;
328 const uint64_t u64 = i->getSrc(s)->asImm()->reg.data.u64;
329
330 if (i->sType == TYPE_F32) {
331 assert(!(u32 & 0x00000fff));
332 code[0] |= ((u32 & 0x001ff000) >> 12) << 23;
333 code[1] |= ((u32 & 0x7fe00000) >> 21);
334 code[1] |= ((u32 & 0x80000000) >> 4);
335 } else
336 if (i->sType == TYPE_F64) {
337 assert(!(u64 & 0x00000fffffffffffULL));
338 code[0] |= ((u64 & 0x001ff00000000000ULL) >> 44) << 23;
339 code[1] |= ((u64 & 0x7fe0000000000000ULL) >> 53);
340 code[1] |= ((u64 & 0x8000000000000000ULL) >> 36);
341 } else {
342 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
343 code[0] |= (u32 & 0x001ff) << 23;
344 code[1] |= (u32 & 0x7fe00) >> 9;
345 code[1] |= (u32 & 0x80000) << 8;
346 }
347 }
348
349 void
350 CodeEmitterGK110::setImmediate32(const Instruction *i, const int s,
351 Modifier mod)
352 {
353 uint32_t u32 = i->getSrc(s)->asImm()->reg.data.u32;
354
355 if (mod) {
356 ImmediateValue imm(i->getSrc(s)->asImm(), i->sType);
357 mod.applyTo(imm);
358 u32 = imm.reg.data.u32;
359 }
360
361 code[0] |= u32 << 23;
362 code[1] |= u32 >> 9;
363 }
364
365 void
366 CodeEmitterGK110::emitForm_L(const Instruction *i, uint32_t opc, uint8_t ctg,
367 Modifier mod)
368 {
369 code[0] = ctg;
370 code[1] = opc << 20;
371
372 emitPredicate(i);
373
374 defId(i->def(0), 2);
375
376 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
377 switch (i->src(s).getFile()) {
378 case FILE_GPR:
379 srcId(i->src(s), s ? 42 : 10);
380 break;
381 case FILE_IMMEDIATE:
382 setImmediate32(i, s, mod);
383 break;
384 default:
385 break;
386 }
387 }
388 }
389
390
391 void
392 CodeEmitterGK110::emitForm_C(const Instruction *i, uint32_t opc, uint8_t ctg)
393 {
394 code[0] = ctg;
395 code[1] = opc << 20;
396
397 emitPredicate(i);
398
399 defId(i->def(0), 2);
400
401 switch (i->src(0).getFile()) {
402 case FILE_MEMORY_CONST:
403 code[1] |= 0x4 << 28;
404 setCAddress14(i->src(0));
405 break;
406 case FILE_GPR:
407 code[1] |= 0xc << 28;
408 srcId(i->src(0), 23);
409 break;
410 default:
411 assert(0);
412 break;
413 }
414 }
415
416 // 0x2 for GPR, c[] and 0x1 for short immediate
417 void
418 CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2,
419 uint32_t opc1)
420 {
421 const bool imm = i->srcExists(1) && i->src(1).getFile() == FILE_IMMEDIATE;
422
423 int s1 = 23;
424 if (i->srcExists(2) && i->src(2).getFile() == FILE_MEMORY_CONST)
425 s1 = 42;
426
427 if (imm) {
428 code[0] = 0x1;
429 code[1] = opc1 << 20;
430 } else {
431 code[0] = 0x2;
432 code[1] = (0xc << 28) | (opc2 << 20);
433 }
434
435 emitPredicate(i);
436
437 defId(i->def(0), 2);
438
439 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
440 switch (i->src(s).getFile()) {
441 case FILE_MEMORY_CONST:
442 code[1] &= (s == 2) ? ~(0x4 << 28) : ~(0x8 << 28);
443 setCAddress14(i->src(s));
444 break;
445 case FILE_IMMEDIATE:
446 setShortImmediate(i, s);
447 break;
448 case FILE_GPR:
449 srcId(i->src(s), s ? ((s == 2) ? 42 : s1) : 10);
450 break;
451 default:
452 if (i->op == OP_SELP) {
453 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
454 srcId(i->src(s), 42);
455 }
456 // ignore here, can be predicate or flags, but must not be address
457 break;
458 }
459 }
460 // 0x0 = invalid
461 // 0xc = rrr
462 // 0x8 = rrc
463 // 0x4 = rcr
464 assert(imm || (code[1] & (0xc << 28)));
465 }
466
467 inline void
468 CodeEmitterGK110::modNegAbsF32_3b(const Instruction *i, const int s)
469 {
470 if (i->src(s).mod.abs()) code[1] &= ~(1 << 27);
471 if (i->src(s).mod.neg()) code[1] ^= (1 << 27);
472 }
473
474 void
475 CodeEmitterGK110::emitNOP(const Instruction *i)
476 {
477 code[0] = 0x00003c02;
478 code[1] = 0x85800000;
479
480 if (i)
481 emitPredicate(i);
482 else
483 code[0] = 0x001c3c02;
484 }
485
486 void
487 CodeEmitterGK110::emitFMAD(const Instruction *i)
488 {
489 assert(!isLIMM(i->src(1), TYPE_F32));
490
491 emitForm_21(i, 0x0c0, 0x940);
492
493 NEG_(34, 2);
494 SAT_(35);
495 RND_(36, F);
496 FTZ_(38);
497 DNZ_(39);
498
499 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
500
501 if (code[0] & 0x1) {
502 if (neg1)
503 code[1] ^= 1 << 27;
504 } else
505 if (neg1) {
506 code[1] |= 1 << 19;
507 }
508 }
509
510 void
511 CodeEmitterGK110::emitDMAD(const Instruction *i)
512 {
513 assert(!i->saturate);
514 assert(!i->ftz);
515
516 emitForm_21(i, 0x1b8, 0xb38);
517
518 NEG_(34, 2);
519 RND_(36, F);
520
521 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
522
523 if (code[0] & 0x1) {
524 if (neg1)
525 code[1] ^= 1 << 27;
526 } else
527 if (neg1) {
528 code[1] |= 1 << 19;
529 }
530 }
531
532 void
533 CodeEmitterGK110::emitMADSP(const Instruction *i)
534 {
535 emitForm_21(i, 0x140, 0xa40);
536
537 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
538 code[1] |= 0x00c00000;
539 } else {
540 code[1] |= (i->subOp & 0x00f) << 19; // imadp1
541 code[1] |= (i->subOp & 0x0f0) << 20; // imadp2
542 code[1] |= (i->subOp & 0x100) << 11; // imadp3
543 code[1] |= (i->subOp & 0x200) << 15; // imadp3
544 code[1] |= (i->subOp & 0xc00) << 12; // imadp3
545 }
546
547 if (i->flagsDef >= 0)
548 code[1] |= 1 << 18;
549 }
550
551 void
552 CodeEmitterGK110::emitFMUL(const Instruction *i)
553 {
554 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
555
556 assert(i->postFactor >= -3 && i->postFactor <= 3);
557
558 if (isLIMM(i->src(1), TYPE_F32)) {
559 emitForm_L(i, 0x200, 0x2, Modifier(0));
560
561 FTZ_(38);
562 DNZ_(39);
563 SAT_(3a);
564 if (neg)
565 code[1] ^= 1 << 22;
566
567 assert(i->postFactor == 0);
568 } else {
569 emitForm_21(i, 0x234, 0xc34);
570 code[1] |= ((i->postFactor > 0) ?
571 (7 - i->postFactor) : (0 - i->postFactor)) << 12;
572
573 RND_(2a, F);
574 FTZ_(2f);
575 DNZ_(30);
576 SAT_(35);
577
578 if (code[0] & 0x1) {
579 if (neg)
580 code[1] ^= 1 << 27;
581 } else
582 if (neg) {
583 code[1] |= 1 << 19;
584 }
585 }
586 }
587
588 void
589 CodeEmitterGK110::emitDMUL(const Instruction *i)
590 {
591 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
592
593 assert(!i->postFactor);
594 assert(!i->saturate);
595 assert(!i->ftz);
596 assert(!i->dnz);
597
598 emitForm_21(i, 0x240, 0xc40);
599
600 RND_(2a, F);
601
602 if (code[0] & 0x1) {
603 if (neg)
604 code[1] ^= 1 << 27;
605 } else
606 if (neg) {
607 code[1] |= 1 << 19;
608 }
609 }
610
611 void
612 CodeEmitterGK110::emitIMUL(const Instruction *i)
613 {
614 assert(!i->src(0).mod.neg() && !i->src(1).mod.neg());
615 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
616
617 if (i->src(1).getFile() == FILE_IMMEDIATE) {
618 emitForm_L(i, 0x280, 2, Modifier(0));
619
620 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
621 code[1] |= 1 << 24;
622 if (i->sType == TYPE_S32)
623 code[1] |= 3 << 25;
624 } else {
625 emitForm_21(i, 0x21c, 0xc1c);
626
627 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
628 code[1] |= 1 << 10;
629 if (i->sType == TYPE_S32)
630 code[1] |= 3 << 11;
631 }
632 }
633
634 void
635 CodeEmitterGK110::emitFADD(const Instruction *i)
636 {
637 if (isLIMM(i->src(1), TYPE_F32)) {
638 assert(i->rnd == ROUND_N);
639 assert(!i->saturate);
640
641 Modifier mod = i->src(1).mod ^
642 Modifier(i->op == OP_SUB ? NV50_IR_MOD_NEG : 0);
643
644 emitForm_L(i, 0x400, 0, mod);
645
646 FTZ_(3a);
647 NEG_(3b, 0);
648 ABS_(39, 0);
649 } else {
650 emitForm_21(i, 0x22c, 0xc2c);
651
652 FTZ_(2f);
653 RND_(2a, F);
654 ABS_(31, 0);
655 NEG_(33, 0);
656 SAT_(35);
657
658 if (code[0] & 0x1) {
659 modNegAbsF32_3b(i, 1);
660 if (i->op == OP_SUB) code[1] ^= 1 << 27;
661 } else {
662 ABS_(34, 1);
663 NEG_(30, 1);
664 if (i->op == OP_SUB) code[1] ^= 1 << 16;
665 }
666 }
667 }
668
669 void
670 CodeEmitterGK110::emitDADD(const Instruction *i)
671 {
672 assert(!i->saturate);
673 assert(!i->ftz);
674
675 emitForm_21(i, 0x238, 0xc38);
676 RND_(2a, F);
677 ABS_(31, 0);
678 NEG_(33, 0);
679 if (code[0] & 0x1) {
680 modNegAbsF32_3b(i, 1);
681 if (i->op == OP_SUB) code[1] ^= 1 << 27;
682 } else {
683 NEG_(30, 1);
684 ABS_(34, 1);
685 if (i->op == OP_SUB) code[1] ^= 1 << 16;
686 }
687 }
688
689 void
690 CodeEmitterGK110::emitUADD(const Instruction *i)
691 {
692 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(1).mod.neg();
693
694 if (i->op == OP_SUB)
695 addOp ^= 1;
696
697 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
698
699 if (isLIMM(i->src(1), TYPE_S32)) {
700 emitForm_L(i, 0x400, 1, Modifier((addOp & 1) ? NV50_IR_MOD_NEG : 0));
701
702 if (addOp & 2)
703 code[1] |= 1 << 27;
704
705 assert(!i->defExists(1));
706 assert(i->flagsSrc < 0);
707
708 SAT_(39);
709 } else {
710 emitForm_21(i, 0x208, 0xc08);
711
712 assert(addOp != 3); // would be add-plus-one
713
714 code[1] |= addOp << 19;
715
716 if (i->defExists(1))
717 code[1] |= 1 << 18; // write carry
718 if (i->flagsSrc >= 0)
719 code[1] |= 1 << 14; // add carry
720
721 SAT_(35);
722 }
723 }
724
725 void
726 CodeEmitterGK110::emitIMAD(const Instruction *i)
727 {
728 uint8_t addOp =
729 i->src(2).mod.neg() | ((i->src(0).mod.neg() ^ i->src(1).mod.neg()) << 1);
730
731 emitForm_21(i, 0x100, 0xa00);
732
733 assert(addOp != 3);
734 code[1] |= addOp << 26;
735
736 if (i->sType == TYPE_S32)
737 code[1] |= (1 << 19) | (1 << 24);
738
739 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
740 code[1] |= 1 << 25;
741
742 if (i->flagsDef >= 0) code[1] |= 1 << 18;
743 if (i->flagsSrc >= 0) code[1] |= 1 << 20;
744
745 SAT_(35);
746 }
747
748 void
749 CodeEmitterGK110::emitISAD(const Instruction *i)
750 {
751 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
752
753 emitForm_21(i, 0x1f4, 0xb74);
754
755 if (i->dType == TYPE_S32)
756 code[1] |= 1 << 19;
757 }
758
759 void
760 CodeEmitterGK110::emitSHLADD(const Instruction *i)
761 {
762 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(2).mod.neg();
763 const ImmediateValue *imm = i->src(1).get()->asImm();
764 assert(imm);
765
766 if (i->src(2).getFile() == FILE_IMMEDIATE) {
767 code[0] = 0x1;
768 code[1] = 0xc0c << 20;
769 } else {
770 code[0] = 0x2;
771 code[1] = 0x20c << 20;
772 }
773 code[1] |= addOp << 19;
774
775 emitPredicate(i);
776
777 defId(i->def(0), 2);
778 srcId(i->src(0), 10);
779
780 if (i->flagsDef >= 0)
781 code[1] |= 1 << 18;
782
783 assert(!(imm->reg.data.u32 & 0xffffffe0));
784 code[1] |= imm->reg.data.u32 << 10;
785
786 switch (i->src(2).getFile()) {
787 case FILE_GPR:
788 assert(code[0] & 0x2);
789 code[1] |= 0xc << 28;
790 srcId(i->src(2), 23);
791 break;
792 case FILE_MEMORY_CONST:
793 assert(code[0] & 0x2);
794 code[1] |= 0x4 << 28;
795 setCAddress14(i->src(2));
796 break;
797 case FILE_IMMEDIATE:
798 assert(code[0] & 0x1);
799 setShortImmediate(i, 2);
800 break;
801 default:
802 assert(!"bad src2 file");
803 break;
804 }
805 }
806
807 void
808 CodeEmitterGK110::emitNOT(const Instruction *i)
809 {
810 code[0] = 0x0003fc02; // logop(mov2) dst, 0, not src
811 code[1] = 0x22003800;
812
813 emitPredicate(i);
814
815 defId(i->def(0), 2);
816
817 switch (i->src(0).getFile()) {
818 case FILE_GPR:
819 code[1] |= 0xc << 28;
820 srcId(i->src(0), 23);
821 break;
822 case FILE_MEMORY_CONST:
823 code[1] |= 0x4 << 28;
824 setCAddress14(i->src(0));
825 break;
826 default:
827 assert(0);
828 break;
829 }
830 }
831
832 void
833 CodeEmitterGK110::emitLogicOp(const Instruction *i, uint8_t subOp)
834 {
835 if (i->def(0).getFile() == FILE_PREDICATE) {
836 code[0] = 0x00000002 | (subOp << 27);
837 code[1] = 0x84800000;
838
839 emitPredicate(i);
840
841 defId(i->def(0), 5);
842 srcId(i->src(0), 14);
843 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 17;
844 srcId(i->src(1), 32);
845 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 3;
846
847 if (i->defExists(1)) {
848 defId(i->def(1), 2);
849 } else {
850 code[0] |= 7 << 2;
851 }
852 // (a OP b) OP c
853 if (i->predSrc != 2 && i->srcExists(2)) {
854 code[1] |= subOp << 16;
855 srcId(i->src(2), 42);
856 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 13;
857 } else {
858 code[1] |= 7 << 10;
859 }
860 } else
861 if (isLIMM(i->src(1), TYPE_S32)) {
862 emitForm_L(i, 0x200, 0, i->src(1).mod);
863 code[1] |= subOp << 24;
864 NOT_(3a, 0);
865 } else {
866 emitForm_21(i, 0x220, 0xc20);
867 code[1] |= subOp << 12;
868 NOT_(2a, 0);
869 NOT_(2b, 1);
870 }
871 }
872
873 void
874 CodeEmitterGK110::emitPOPC(const Instruction *i)
875 {
876 assert(!isLIMM(i->src(1), TYPE_S32, true));
877
878 emitForm_21(i, 0x204, 0xc04);
879
880 NOT_(2a, 0);
881 if (!(code[0] & 0x1))
882 NOT_(2b, 1);
883 }
884
885 void
886 CodeEmitterGK110::emitINSBF(const Instruction *i)
887 {
888 emitForm_21(i, 0x1f8, 0xb78);
889 }
890
891 void
892 CodeEmitterGK110::emitEXTBF(const Instruction *i)
893 {
894 emitForm_21(i, 0x600, 0xc00);
895
896 if (i->dType == TYPE_S32)
897 code[1] |= 0x80000;
898 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
899 code[1] |= 0x800;
900 }
901
902 void
903 CodeEmitterGK110::emitBFIND(const Instruction *i)
904 {
905 emitForm_C(i, 0x218, 0x2);
906
907 if (i->dType == TYPE_S32)
908 code[1] |= 0x80000;
909 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
910 code[1] |= 0x800;
911 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
912 code[1] |= 0x1000;
913 }
914
915 void
916 CodeEmitterGK110::emitPERMT(const Instruction *i)
917 {
918 emitForm_21(i, 0x1e0, 0xb60);
919
920 code[1] |= i->subOp << 19;
921 }
922
923 void
924 CodeEmitterGK110::emitShift(const Instruction *i)
925 {
926 if (i->op == OP_SHR) {
927 emitForm_21(i, 0x214, 0xc14);
928 if (isSignedType(i->dType))
929 code[1] |= 1 << 19;
930 } else {
931 emitForm_21(i, 0x224, 0xc24);
932 }
933
934 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
935 code[1] |= 1 << 10;
936 }
937
938 void
939 CodeEmitterGK110::emitPreOp(const Instruction *i)
940 {
941 emitForm_C(i, 0x248, 0x2);
942
943 if (i->op == OP_PREEX2)
944 code[1] |= 1 << 10;
945
946 NEG_(30, 0);
947 ABS_(34, 0);
948 }
949
950 void
951 CodeEmitterGK110::emitSFnOp(const Instruction *i, uint8_t subOp)
952 {
953 code[0] = 0x00000002 | (subOp << 23);
954 code[1] = 0x84000000;
955
956 emitPredicate(i);
957
958 defId(i->def(0), 2);
959 srcId(i->src(0), 10);
960
961 NEG_(33, 0);
962 ABS_(31, 0);
963 SAT_(35);
964 }
965
966 void
967 CodeEmitterGK110::emitMINMAX(const Instruction *i)
968 {
969 uint32_t op2, op1;
970
971 switch (i->dType) {
972 case TYPE_U32:
973 case TYPE_S32:
974 op2 = 0x210;
975 op1 = 0xc10;
976 break;
977 case TYPE_F32:
978 op2 = 0x230;
979 op1 = 0xc30;
980 break;
981 case TYPE_F64:
982 op2 = 0x228;
983 op1 = 0xc28;
984 break;
985 default:
986 assert(0);
987 op2 = 0;
988 op1 = 0;
989 break;
990 }
991 emitForm_21(i, op2, op1);
992
993 if (i->dType == TYPE_S32)
994 code[1] |= 1 << 19;
995 code[1] |= (i->op == OP_MIN) ? 0x1c00 : 0x3c00; // [!]pt
996 code[1] |= i->subOp << 14;
997 if (i->flagsDef >= 0)
998 code[1] |= i->subOp << 18;
999
1000 FTZ_(2f);
1001 ABS_(31, 0);
1002 NEG_(33, 0);
1003 if (code[0] & 0x1) {
1004 modNegAbsF32_3b(i, 1);
1005 } else {
1006 ABS_(34, 1);
1007 NEG_(30, 1);
1008 }
1009 }
1010
1011 void
1012 CodeEmitterGK110::emitCVT(const Instruction *i)
1013 {
1014 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1015 const bool f2i = !isFloatType(i->dType) && isFloatType(i->sType);
1016 const bool i2f = isFloatType(i->dType) && !isFloatType(i->sType);
1017
1018 bool sat = i->saturate;
1019 bool abs = i->src(0).mod.abs();
1020 bool neg = i->src(0).mod.neg();
1021
1022 RoundMode rnd = i->rnd;
1023
1024 switch (i->op) {
1025 case OP_CEIL: rnd = f2f ? ROUND_PI : ROUND_P; break;
1026 case OP_FLOOR: rnd = f2f ? ROUND_MI : ROUND_M; break;
1027 case OP_TRUNC: rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1028 case OP_SAT: sat = true; break;
1029 case OP_NEG: neg = !neg; break;
1030 case OP_ABS: abs = true; neg = false; break;
1031 default:
1032 break;
1033 }
1034
1035 DataType dType;
1036
1037 if (i->op == OP_NEG && i->dType == TYPE_U32)
1038 dType = TYPE_S32;
1039 else
1040 dType = i->dType;
1041
1042
1043 uint32_t op;
1044
1045 if (f2f) op = 0x254;
1046 else if (f2i) op = 0x258;
1047 else if (i2f) op = 0x25c;
1048 else op = 0x260;
1049
1050 emitForm_C(i, op, 0x2);
1051
1052 FTZ_(2f);
1053 if (neg) code[1] |= 1 << 16;
1054 if (abs) code[1] |= 1 << 20;
1055 if (sat) code[1] |= 1 << 21;
1056
1057 emitRoundMode(rnd, 32 + 10, f2f ? (32 + 13) : -1);
1058
1059 code[0] |= typeSizeofLog2(dType) << 10;
1060 code[0] |= typeSizeofLog2(i->sType) << 12;
1061 code[1] |= i->subOp << 12;
1062
1063 if (isSignedIntType(dType))
1064 code[0] |= 0x4000;
1065 if (isSignedIntType(i->sType))
1066 code[0] |= 0x8000;
1067 }
1068
1069 void
1070 CodeEmitterGK110::emitSET(const CmpInstruction *i)
1071 {
1072 uint16_t op1, op2;
1073
1074 if (i->def(0).getFile() == FILE_PREDICATE) {
1075 switch (i->sType) {
1076 case TYPE_F32: op2 = 0x1d8; op1 = 0xb58; break;
1077 case TYPE_F64: op2 = 0x1c0; op1 = 0xb40; break;
1078 default:
1079 op2 = 0x1b0;
1080 op1 = 0xb30;
1081 break;
1082 }
1083 emitForm_21(i, op2, op1);
1084
1085 NEG_(2e, 0);
1086 ABS_(9, 0);
1087 if (!(code[0] & 0x1)) {
1088 NEG_(8, 1);
1089 ABS_(2f, 1);
1090 } else {
1091 modNegAbsF32_3b(i, 1);
1092 }
1093 FTZ_(32);
1094
1095 // normal DST field is negated predicate result
1096 code[0] = (code[0] & ~0xfc) | ((code[0] << 3) & 0xe0);
1097 if (i->defExists(1))
1098 defId(i->def(1), 2);
1099 else
1100 code[0] |= 0x1c;
1101 } else {
1102 switch (i->sType) {
1103 case TYPE_F32: op2 = 0x000; op1 = 0x800; break;
1104 case TYPE_F64: op2 = 0x080; op1 = 0x900; break;
1105 default:
1106 op2 = 0x1a8;
1107 op1 = 0xb28;
1108 break;
1109 }
1110 emitForm_21(i, op2, op1);
1111
1112 NEG_(2e, 0);
1113 ABS_(39, 0);
1114 if (!(code[0] & 0x1)) {
1115 NEG_(38, 1);
1116 ABS_(2f, 1);
1117 } else {
1118 modNegAbsF32_3b(i, 1);
1119 }
1120 FTZ_(3a);
1121
1122 if (i->dType == TYPE_F32) {
1123 if (isFloatType(i->sType))
1124 code[1] |= 1 << 23;
1125 else
1126 code[1] |= 1 << 15;
1127 }
1128 }
1129 if (i->sType == TYPE_S32)
1130 code[1] |= 1 << 19;
1131
1132 if (i->op != OP_SET) {
1133 switch (i->op) {
1134 case OP_SET_AND: code[1] |= 0x0 << 16; break;
1135 case OP_SET_OR: code[1] |= 0x1 << 16; break;
1136 case OP_SET_XOR: code[1] |= 0x2 << 16; break;
1137 default:
1138 assert(0);
1139 break;
1140 }
1141 srcId(i->src(2), 0x2a);
1142 } else {
1143 code[1] |= 0x7 << 10;
1144 }
1145 emitCondCode(i->setCond,
1146 isFloatType(i->sType) ? 0x33 : 0x34,
1147 isFloatType(i->sType) ? 0xf : 0x7);
1148 }
1149
1150 void
1151 CodeEmitterGK110::emitSLCT(const CmpInstruction *i)
1152 {
1153 CondCode cc = i->setCond;
1154 if (i->src(2).mod.neg())
1155 cc = reverseCondCode(cc);
1156
1157 if (i->dType == TYPE_F32) {
1158 emitForm_21(i, 0x1d0, 0xb50);
1159 FTZ_(32);
1160 emitCondCode(cc, 0x33, 0xf);
1161 } else {
1162 emitForm_21(i, 0x1a0, 0xb20);
1163 emitCondCode(cc, 0x34, 0x7);
1164 }
1165 }
1166
1167 static void
1168 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1169 {
1170 int loc = entry->loc;
1171 if (data.force_persample_interp)
1172 code[loc + 1] |= 1 << 13;
1173 else
1174 code[loc + 1] &= ~(1 << 13);
1175 }
1176
1177 void CodeEmitterGK110::emitSELP(const Instruction *i)
1178 {
1179 emitForm_21(i, 0x250, 0x050);
1180
1181 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1182 code[1] |= 1 << 13;
1183
1184 if (i->subOp == 1) {
1185 addInterp(0, 0, selpFlip);
1186 }
1187 }
1188
1189 void CodeEmitterGK110::emitTEXBAR(const Instruction *i)
1190 {
1191 code[0] = 0x0000003e | (i->subOp << 23);
1192 code[1] = 0x77000000;
1193
1194 emitPredicate(i);
1195 }
1196
1197 void CodeEmitterGK110::emitTEXCSAA(const TexInstruction *i)
1198 {
1199 code[0] = 0x00000002;
1200 code[1] = 0x76c00000;
1201
1202 code[1] |= i->tex.r << 9;
1203 // code[1] |= i->tex.s << (9 + 8);
1204
1205 if (i->tex.liveOnly)
1206 code[0] |= 0x80000000;
1207
1208 defId(i->def(0), 2);
1209 srcId(i->src(0), 10);
1210 }
1211
1212 static inline bool
1213 isNextIndependentTex(const TexInstruction *i)
1214 {
1215 if (!i->next || !isTextureOp(i->next->op))
1216 return false;
1217 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1218 return false;
1219 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1220 }
1221
1222 void
1223 CodeEmitterGK110::emitTEX(const TexInstruction *i)
1224 {
1225 const bool ind = i->tex.rIndirectSrc >= 0;
1226
1227 if (ind) {
1228 code[0] = 0x00000002;
1229 switch (i->op) {
1230 case OP_TXD:
1231 code[1] = 0x7e000000;
1232 break;
1233 case OP_TXLQ:
1234 code[1] = 0x7e800000;
1235 break;
1236 case OP_TXF:
1237 code[1] = 0x78000000;
1238 break;
1239 case OP_TXG:
1240 code[1] = 0x7dc00000;
1241 break;
1242 default:
1243 code[1] = 0x7d800000;
1244 break;
1245 }
1246 } else {
1247 switch (i->op) {
1248 case OP_TXD:
1249 code[0] = 0x00000002;
1250 code[1] = 0x76000000;
1251 code[1] |= i->tex.r << 9;
1252 break;
1253 case OP_TXLQ:
1254 code[0] = 0x00000002;
1255 code[1] = 0x76800000;
1256 code[1] |= i->tex.r << 9;
1257 break;
1258 case OP_TXF:
1259 code[0] = 0x00000002;
1260 code[1] = 0x70000000;
1261 code[1] |= i->tex.r << 13;
1262 break;
1263 case OP_TXG:
1264 code[0] = 0x00000001;
1265 code[1] = 0x70000000;
1266 code[1] |= i->tex.r << 15;
1267 break;
1268 default:
1269 code[0] = 0x00000001;
1270 code[1] = 0x60000000;
1271 code[1] |= i->tex.r << 15;
1272 break;
1273 }
1274 }
1275
1276 code[1] |= isNextIndependentTex(i) ? 0x1 : 0x2; // t : p mode
1277
1278 if (i->tex.liveOnly)
1279 code[0] |= 0x80000000;
1280
1281 switch (i->op) {
1282 case OP_TEX: break;
1283 case OP_TXB: code[1] |= 0x2000; break;
1284 case OP_TXL: code[1] |= 0x3000; break;
1285 case OP_TXF: break;
1286 case OP_TXG: break;
1287 case OP_TXD: break;
1288 case OP_TXLQ: break;
1289 default:
1290 assert(!"invalid texture op");
1291 break;
1292 }
1293
1294 if (i->op == OP_TXF) {
1295 if (!i->tex.levelZero)
1296 code[1] |= 0x1000;
1297 } else
1298 if (i->tex.levelZero) {
1299 code[1] |= 0x1000;
1300 }
1301
1302 if (i->op != OP_TXD && i->tex.derivAll)
1303 code[1] |= 0x200;
1304
1305 emitPredicate(i);
1306
1307 code[1] |= i->tex.mask << 2;
1308
1309 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1310
1311 defId(i->def(0), 2);
1312 srcId(i->src(0), 10);
1313 srcId(i, src1, 23);
1314
1315 if (i->op == OP_TXG) code[1] |= i->tex.gatherComp << 13;
1316
1317 // texture target:
1318 code[1] |= (i->tex.target.isCube() ? 3 : (i->tex.target.getDim() - 1)) << 7;
1319 if (i->tex.target.isArray())
1320 code[1] |= 0x40;
1321 if (i->tex.target.isShadow())
1322 code[1] |= 0x400;
1323 if (i->tex.target == TEX_TARGET_2D_MS ||
1324 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1325 code[1] |= 0x800;
1326
1327 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1328 // ?
1329 }
1330
1331 if (i->tex.useOffsets == 1) {
1332 switch (i->op) {
1333 case OP_TXF: code[1] |= 0x200; break;
1334 case OP_TXD: code[1] |= 0x00400000; break;
1335 default: code[1] |= 0x800; break;
1336 }
1337 }
1338 if (i->tex.useOffsets == 4)
1339 code[1] |= 0x1000;
1340 }
1341
1342 void
1343 CodeEmitterGK110::emitTXQ(const TexInstruction *i)
1344 {
1345 code[0] = 0x00000002;
1346 code[1] = 0x75400001;
1347
1348 switch (i->tex.query) {
1349 case TXQ_DIMS: code[0] |= 0x01 << 25; break;
1350 case TXQ_TYPE: code[0] |= 0x02 << 25; break;
1351 case TXQ_SAMPLE_POSITION: code[0] |= 0x05 << 25; break;
1352 case TXQ_FILTER: code[0] |= 0x10 << 25; break;
1353 case TXQ_LOD: code[0] |= 0x12 << 25; break;
1354 case TXQ_BORDER_COLOUR: code[0] |= 0x16 << 25; break;
1355 default:
1356 assert(!"invalid texture query");
1357 break;
1358 }
1359
1360 code[1] |= i->tex.mask << 2;
1361 code[1] |= i->tex.r << 9;
1362 if (/*i->tex.sIndirectSrc >= 0 || */i->tex.rIndirectSrc >= 0)
1363 code[1] |= 0x08000000;
1364
1365 defId(i->def(0), 2);
1366 srcId(i->src(0), 10);
1367
1368 emitPredicate(i);
1369 }
1370
1371 void
1372 CodeEmitterGK110::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1373 {
1374 code[0] = 0x00000002 | ((qOp & 1) << 31);
1375 code[1] = 0x7fc00200 | (qOp >> 1) | (laneMask << 12); // dall
1376
1377 defId(i->def(0), 2);
1378 srcId(i->src(0), 10);
1379 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 23);
1380
1381 emitPredicate(i);
1382 }
1383
1384 void
1385 CodeEmitterGK110::emitPIXLD(const Instruction *i)
1386 {
1387 emitForm_L(i, 0x7f4, 2, Modifier(0));
1388 code[1] |= i->subOp << 2;
1389 code[1] |= 0x00070000;
1390 }
1391
1392 void
1393 CodeEmitterGK110::emitBAR(const Instruction *i)
1394 {
1395 code[0] = 0x00000002;
1396 code[1] = 0x85400000;
1397
1398 switch (i->subOp) {
1399 case NV50_IR_SUBOP_BAR_ARRIVE: code[1] |= 0x08; break;
1400 case NV50_IR_SUBOP_BAR_RED_AND: code[1] |= 0x50; break;
1401 case NV50_IR_SUBOP_BAR_RED_OR: code[1] |= 0x90; break;
1402 case NV50_IR_SUBOP_BAR_RED_POPC: code[1] |= 0x10; break;
1403 default:
1404 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1405 break;
1406 }
1407
1408 emitPredicate(i);
1409
1410 // barrier id
1411 if (i->src(0).getFile() == FILE_GPR) {
1412 srcId(i->src(0), 10);
1413 } else {
1414 ImmediateValue *imm = i->getSrc(0)->asImm();
1415 assert(imm);
1416 code[0] |= imm->reg.data.u32 << 10;
1417 code[1] |= 0x8000;
1418 }
1419
1420 // thread count
1421 if (i->src(1).getFile() == FILE_GPR) {
1422 srcId(i->src(1), 23);
1423 } else {
1424 ImmediateValue *imm = i->getSrc(0)->asImm();
1425 assert(imm);
1426 assert(imm->reg.data.u32 <= 0xfff);
1427 code[0] |= imm->reg.data.u32 << 23;
1428 code[1] |= imm->reg.data.u32 >> 9;
1429 code[1] |= 0x4000;
1430 }
1431
1432 if (i->srcExists(2) && (i->predSrc != 2)) {
1433 srcId(i->src(2), 32 + 10);
1434 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1435 code[1] |= 1 << 13;
1436 } else {
1437 code[1] |= 7 << 10;
1438 }
1439 }
1440
1441 void CodeEmitterGK110::emitMEMBAR(const Instruction *i)
1442 {
1443 code[0] = 0x00000002 | NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) << 8;
1444 code[1] = 0x7cc00000;
1445
1446 emitPredicate(i);
1447 }
1448
1449 void
1450 CodeEmitterGK110::emitFlow(const Instruction *i)
1451 {
1452 const FlowInstruction *f = i->asFlow();
1453
1454 unsigned mask; // bit 0: predicate, bit 1: target
1455
1456 code[0] = 0x00000000;
1457
1458 switch (i->op) {
1459 case OP_BRA:
1460 code[1] = f->absolute ? 0x10800000 : 0x12000000;
1461 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1462 code[0] |= 0x80;
1463 mask = 3;
1464 break;
1465 case OP_CALL:
1466 code[1] = f->absolute ? 0x11000000 : 0x13000000;
1467 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1468 code[0] |= 0x80;
1469 mask = 2;
1470 break;
1471
1472 case OP_EXIT: code[1] = 0x18000000; mask = 1; break;
1473 case OP_RET: code[1] = 0x19000000; mask = 1; break;
1474 case OP_DISCARD: code[1] = 0x19800000; mask = 1; break;
1475 case OP_BREAK: code[1] = 0x1a000000; mask = 1; break;
1476 case OP_CONT: code[1] = 0x1a800000; mask = 1; break;
1477
1478 case OP_JOINAT: code[1] = 0x14800000; mask = 2; break;
1479 case OP_PREBREAK: code[1] = 0x15000000; mask = 2; break;
1480 case OP_PRECONT: code[1] = 0x15800000; mask = 2; break;
1481 case OP_PRERET: code[1] = 0x13800000; mask = 2; break;
1482
1483 case OP_QUADON: code[1] = 0x1b800000; mask = 0; break;
1484 case OP_QUADPOP: code[1] = 0x1c000000; mask = 0; break;
1485 case OP_BRKPT: code[1] = 0x00000000; mask = 0; break;
1486 default:
1487 assert(!"invalid flow operation");
1488 return;
1489 }
1490
1491 if (mask & 1) {
1492 emitPredicate(i);
1493 if (i->flagsSrc < 0)
1494 code[0] |= 0x3c;
1495 }
1496
1497 if (!f)
1498 return;
1499
1500 if (f->allWarp)
1501 code[0] |= 1 << 9;
1502 if (f->limit)
1503 code[0] |= 1 << 8;
1504
1505 if (f->op == OP_CALL) {
1506 if (f->builtin) {
1507 assert(f->absolute);
1508 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1509 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xff800000, 23);
1510 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x007fffff, -9);
1511 } else {
1512 assert(!f->absolute);
1513 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1514 code[0] |= (pcRel & 0x1ff) << 23;
1515 code[1] |= (pcRel >> 9) & 0x7fff;
1516 }
1517 } else
1518 if (mask & 2) {
1519 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1520 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1521 pcRel += 8;
1522 // currently we don't want absolute branches
1523 assert(!f->absolute);
1524 code[0] |= (pcRel & 0x1ff) << 23;
1525 code[1] |= (pcRel >> 9) & 0x7fff;
1526 }
1527 }
1528
1529 void
1530 CodeEmitterGK110::emitVOTE(const Instruction *i)
1531 {
1532 assert(i->src(0).getFile() == FILE_PREDICATE);
1533
1534 code[0] = 0x00000002;
1535 code[1] = 0x86c00000 | (i->subOp << 19);
1536
1537 emitPredicate(i);
1538
1539 unsigned rp = 0;
1540 for (int d = 0; i->defExists(d); d++) {
1541 if (i->def(d).getFile() == FILE_PREDICATE) {
1542 assert(!(rp & 2));
1543 rp |= 2;
1544 defId(i->def(d), 48);
1545 } else if (i->def(d).getFile() == FILE_GPR) {
1546 assert(!(rp & 1));
1547 rp |= 1;
1548 defId(i->def(d), 2);
1549 } else {
1550 assert(!"Unhandled def");
1551 }
1552 }
1553 if (!(rp & 1))
1554 code[0] |= 255 << 2;
1555 if (!(rp & 2))
1556 code[1] |= 7 << 16;
1557 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
1558 code[1] |= 1 << 13;
1559 srcId(i->src(0), 42);
1560 }
1561
1562 void
1563 CodeEmitterGK110::emitSUGType(DataType ty, const int pos)
1564 {
1565 uint8_t n = 0;
1566
1567 switch (ty) {
1568 case TYPE_S32: n = 1; break;
1569 case TYPE_U8: n = 2; break;
1570 case TYPE_S8: n = 3; break;
1571 default:
1572 assert(ty == TYPE_U32);
1573 break;
1574 }
1575 code[pos / 32] |= n << (pos % 32);
1576 }
1577
1578 void
1579 CodeEmitterGK110::emitSUCachingMode(CacheMode c)
1580 {
1581 uint8_t n = 0;
1582
1583 switch (c) {
1584 case CACHE_CA:
1585 // case CACHE_WB:
1586 n = 0;
1587 break;
1588 case CACHE_CG:
1589 n = 1;
1590 break;
1591 case CACHE_CS:
1592 n = 2;
1593 break;
1594 case CACHE_CV:
1595 // case CACHE_WT:
1596 n = 3;
1597 break;
1598 default:
1599 assert(!"invalid caching mode");
1600 break;
1601 }
1602 code[0] |= (n & 1) << 31;
1603 code[1] |= (n & 2) >> 1;
1604 }
1605
1606 void
1607 CodeEmitterGK110::setSUConst16(const Instruction *i, const int s)
1608 {
1609 const uint32_t offset = i->getSrc(s)->reg.data.offset;
1610
1611 assert(offset == (offset & 0xfffc));
1612
1613 code[0] |= offset << 21;
1614 code[1] |= offset >> 11;
1615 code[1] |= i->getSrc(s)->reg.fileIndex << 5;
1616 }
1617
1618 void
1619 CodeEmitterGK110::emitSULDGB(const TexInstruction *i)
1620 {
1621 code[0] = 0x00000002;
1622 code[1] = 0x30000000 | (i->subOp << 14);
1623
1624 if (i->src(1).getFile() == FILE_MEMORY_CONST) {
1625 emitLoadStoreType(i->dType, 0x38);
1626 emitCachingMode(i->cache, 0x36);
1627
1628 // format
1629 setSUConst16(i, 1);
1630 } else {
1631 assert(i->src(1).getFile() == FILE_GPR);
1632 code[1] |= 0x49800000;
1633
1634 emitLoadStoreType(i->dType, 0x21);
1635 emitSUCachingMode(i->cache);
1636
1637 srcId(i->src(1), 23);
1638 }
1639
1640 emitSUGType(i->sType, 0x34);
1641
1642 emitPredicate(i);
1643 defId(i->def(0), 2); // destination
1644 srcId(i->src(0), 10); // address
1645
1646 // surface predicate
1647 if (!i->srcExists(2) || (i->predSrc == 2)) {
1648 code[1] |= 0x7 << 10;
1649 } else {
1650 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1651 code[1] |= 1 << 13;
1652 srcId(i->src(2), 32 + 10);
1653 }
1654 }
1655
1656 void
1657 CodeEmitterGK110::emitSUSTGx(const TexInstruction *i)
1658 {
1659 assert(i->op == OP_SUSTP);
1660
1661 code[0] = 0x00000002;
1662 code[1] = 0x38000000;
1663
1664 if (i->src(1).getFile() == FILE_MEMORY_CONST) {
1665 code[0] |= i->subOp << 2;
1666
1667 if (i->op == OP_SUSTP)
1668 code[0] |= i->tex.mask << 4;
1669
1670 emitSUGType(i->sType, 0x8);
1671 emitCachingMode(i->cache, 0x36);
1672
1673 // format
1674 setSUConst16(i, 1);
1675 } else {
1676 assert(i->src(1).getFile() == FILE_GPR);
1677
1678 code[0] |= i->subOp << 23;
1679 code[1] |= 0x41c00000;
1680
1681 if (i->op == OP_SUSTP)
1682 code[0] |= i->tex.mask << 25;
1683
1684 emitSUGType(i->sType, 0x1d);
1685 emitSUCachingMode(i->cache);
1686
1687 srcId(i->src(1), 2);
1688 }
1689
1690 emitPredicate(i);
1691 srcId(i->src(0), 10); // address
1692 srcId(i->src(3), 42); // values
1693
1694 // surface predicate
1695 if (!i->srcExists(2) || (i->predSrc == 2)) {
1696 code[1] |= 0x7 << 18;
1697 } else {
1698 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1699 code[1] |= 1 << 21;
1700 srcId(i->src(2), 32 + 18);
1701 }
1702 }
1703
1704 void
1705 CodeEmitterGK110::emitSUCLAMPMode(uint16_t subOp)
1706 {
1707 uint8_t m;
1708 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
1709 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
1710 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
1711 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
1712 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
1713 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
1714 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
1715 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
1716 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
1717 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
1718 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
1719 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
1720 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
1721 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
1722 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
1723 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
1724 default:
1725 return;
1726 }
1727 code[1] |= m << 20;
1728 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
1729 code[1] |= 1 << 24;
1730 }
1731
1732 void
1733 CodeEmitterGK110::emitSUCalc(Instruction *i)
1734 {
1735 ImmediateValue *imm = NULL;
1736 uint64_t opc1, opc2;
1737
1738 if (i->srcExists(2)) {
1739 imm = i->getSrc(2)->asImm();
1740 if (imm)
1741 i->setSrc(2, NULL); // special case, make emitForm_21 not assert
1742 }
1743
1744 switch (i->op) {
1745 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break;
1746 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break;
1747 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break;
1748 default:
1749 assert(0);
1750 return;
1751 }
1752 emitForm_21(i, opc2, opc1);
1753
1754 if (i->op == OP_SUCLAMP) {
1755 if (i->dType == TYPE_S32)
1756 code[1] |= 1 << 19;
1757 emitSUCLAMPMode(i->subOp);
1758 }
1759
1760 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
1761 code[1] |= 1 << 18;
1762
1763 if (i->op != OP_SUEAU) {
1764 const uint8_t pos = i->op == OP_SUBFM ? 19 : 16;
1765 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1766 code[0] |= 255 << 2;
1767 code[1] |= i->getDef(1)->reg.data.id << pos;
1768 } else
1769 if (i->defExists(1)) { // r, p
1770 assert(i->def(1).getFile() == FILE_PREDICATE);
1771 code[1] |= i->getDef(1)->reg.data.id << pos;
1772 } else { // r, #
1773 code[1] |= 7 << pos;
1774 }
1775 }
1776
1777 if (imm) {
1778 assert(i->op == OP_SUCLAMP);
1779 i->setSrc(2, imm);
1780 code[1] |= (imm->reg.data.u32 & 0x3f) << 10; // sint6
1781 }
1782 }
1783
1784
1785 void
1786 CodeEmitterGK110::emitVectorSubOp(const Instruction *i)
1787 {
1788 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
1789 case 0:
1790 code[1] |= (i->subOp & 0x000f) << 7; // vsrc1
1791 code[1] |= (i->subOp & 0x00e0) >> 6; // vsrc2
1792 code[1] |= (i->subOp & 0x0100) << 13; // vsrc2
1793 code[1] |= (i->subOp & 0x3c00) << 12; // vdst
1794 break;
1795 default:
1796 assert(0);
1797 break;
1798 }
1799 }
1800
1801 void
1802 CodeEmitterGK110::emitVSHL(const Instruction *i)
1803 {
1804 code[0] = 0x00000002;
1805 code[1] = 0xb8000000;
1806
1807 assert(NV50_IR_SUBOP_Vn(i->subOp) == 0);
1808
1809 if (isSignedType(i->dType)) code[1] |= 1 << 25;
1810 if (isSignedType(i->sType)) code[1] |= 1 << 19;
1811
1812 emitVectorSubOp(i);
1813
1814 emitPredicate(i);
1815 defId(i->def(0), 2);
1816 srcId(i->src(0), 10);
1817
1818 if (i->getSrc(1)->reg.file == FILE_IMMEDIATE) {
1819 ImmediateValue *imm = i->getSrc(1)->asImm();
1820 assert(imm);
1821 code[0] |= (imm->reg.data.u32 & 0x01ff) << 23;
1822 code[1] |= (imm->reg.data.u32 & 0xfe00) >> 9;
1823 } else {
1824 assert(i->getSrc(1)->reg.file == FILE_GPR);
1825 code[1] |= 1 << 21;
1826 srcId(i->src(1), 23);
1827 }
1828 srcId(i->src(2), 42);
1829
1830 if (i->saturate)
1831 code[0] |= 1 << 22;
1832 if (i->flagsDef >= 0)
1833 code[1] |= 1 << 18;
1834 }
1835
1836 void
1837 CodeEmitterGK110::emitAFETCH(const Instruction *i)
1838 {
1839 uint32_t offset = i->src(0).get()->reg.data.offset & 0x7ff;
1840
1841 code[0] = 0x00000002 | (offset << 23);
1842 code[1] = 0x7d000000 | (offset >> 9);
1843
1844 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1845 code[1] |= 0x8;
1846
1847 emitPredicate(i);
1848
1849 defId(i->def(0), 2);
1850 srcId(i->src(0).getIndirect(0), 10);
1851 }
1852
1853 void
1854 CodeEmitterGK110::emitPFETCH(const Instruction *i)
1855 {
1856 uint32_t prim = i->src(0).get()->reg.data.u32;
1857
1858 code[0] = 0x00000002 | ((prim & 0xff) << 23);
1859 code[1] = 0x7f800000;
1860
1861 emitPredicate(i);
1862
1863 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1864
1865 defId(i->def(0), 2);
1866 srcId(i, src1, 10);
1867 }
1868
1869 void
1870 CodeEmitterGK110::emitVFETCH(const Instruction *i)
1871 {
1872 unsigned int size = typeSizeof(i->dType);
1873 uint32_t offset = i->src(0).get()->reg.data.offset;
1874
1875 code[0] = 0x00000002 | (offset << 23);
1876 code[1] = 0x7ec00000 | (offset >> 9);
1877 code[1] |= (size / 4 - 1) << 18;
1878
1879 if (i->perPatch)
1880 code[1] |= 0x4;
1881 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1882 code[1] |= 0x8; // yes, TCPs can read from *outputs* of other threads
1883
1884 emitPredicate(i);
1885
1886 defId(i->def(0), 2);
1887 srcId(i->src(0).getIndirect(0), 10);
1888 srcId(i->src(0).getIndirect(1), 32 + 10); // vertex address
1889 }
1890
1891 void
1892 CodeEmitterGK110::emitEXPORT(const Instruction *i)
1893 {
1894 unsigned int size = typeSizeof(i->dType);
1895 uint32_t offset = i->src(0).get()->reg.data.offset;
1896
1897 code[0] = 0x00000002 | (offset << 23);
1898 code[1] = 0x7f000000 | (offset >> 9);
1899 code[1] |= (size / 4 - 1) << 18;
1900
1901 if (i->perPatch)
1902 code[1] |= 0x4;
1903
1904 emitPredicate(i);
1905
1906 assert(i->src(1).getFile() == FILE_GPR);
1907
1908 srcId(i->src(0).getIndirect(0), 10);
1909 srcId(i->src(0).getIndirect(1), 32 + 10); // vertex base address
1910 srcId(i->src(1), 2);
1911 }
1912
1913 void
1914 CodeEmitterGK110::emitOUT(const Instruction *i)
1915 {
1916 assert(i->src(0).getFile() == FILE_GPR);
1917
1918 emitForm_21(i, 0x1f0, 0xb70);
1919
1920 if (i->op == OP_EMIT)
1921 code[1] |= 1 << 10;
1922 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1923 code[1] |= 1 << 11;
1924 }
1925
1926 void
1927 CodeEmitterGK110::emitInterpMode(const Instruction *i)
1928 {
1929 code[1] |= (i->ipa & 0x3) << 21; // TODO: INTERP_SAMPLEID
1930 code[1] |= (i->ipa & 0xc) << (19 - 2);
1931 }
1932
1933 static void
1934 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1935 {
1936 int ipa = entry->ipa;
1937 int reg = entry->reg;
1938 int loc = entry->loc;
1939
1940 if (data.flatshade &&
1941 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1942 ipa = NV50_IR_INTERP_FLAT;
1943 reg = 0xff;
1944 } else if (data.force_persample_interp &&
1945 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1946 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1947 ipa |= NV50_IR_INTERP_CENTROID;
1948 }
1949 code[loc + 1] &= ~(0xf << 19);
1950 code[loc + 1] |= (ipa & 0x3) << 21;
1951 code[loc + 1] |= (ipa & 0xc) << (19 - 2);
1952 code[loc + 0] &= ~(0xff << 23);
1953 code[loc + 0] |= reg << 23;
1954 }
1955
1956 void
1957 CodeEmitterGK110::emitINTERP(const Instruction *i)
1958 {
1959 const uint32_t base = i->getSrc(0)->reg.data.offset;
1960
1961 code[0] = 0x00000002 | (base << 31);
1962 code[1] = 0x74800000 | (base >> 1);
1963
1964 if (i->saturate)
1965 code[1] |= 1 << 18;
1966
1967 if (i->op == OP_PINTERP) {
1968 srcId(i->src(1), 23);
1969 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1970 } else {
1971 code[0] |= 0xff << 23;
1972 addInterp(i->ipa, 0xff, interpApply);
1973 }
1974
1975 srcId(i->src(0).getIndirect(0), 10);
1976 emitInterpMode(i);
1977
1978 emitPredicate(i);
1979 defId(i->def(0), 2);
1980
1981 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1982 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 10);
1983 else
1984 code[1] |= 0xff << 10;
1985 }
1986
1987 void
1988 CodeEmitterGK110::emitLoadStoreType(DataType ty, const int pos)
1989 {
1990 uint8_t n;
1991
1992 switch (ty) {
1993 case TYPE_U8:
1994 n = 0;
1995 break;
1996 case TYPE_S8:
1997 n = 1;
1998 break;
1999 case TYPE_U16:
2000 n = 2;
2001 break;
2002 case TYPE_S16:
2003 n = 3;
2004 break;
2005 case TYPE_F32:
2006 case TYPE_U32:
2007 case TYPE_S32:
2008 n = 4;
2009 break;
2010 case TYPE_F64:
2011 case TYPE_U64:
2012 case TYPE_S64:
2013 n = 5;
2014 break;
2015 case TYPE_B128:
2016 n = 6;
2017 break;
2018 default:
2019 n = 0;
2020 assert(!"invalid ld/st type");
2021 break;
2022 }
2023 code[pos / 32] |= n << (pos % 32);
2024 }
2025
2026 void
2027 CodeEmitterGK110::emitCachingMode(CacheMode c, const int pos)
2028 {
2029 uint8_t n;
2030
2031 switch (c) {
2032 case CACHE_CA:
2033 // case CACHE_WB:
2034 n = 0;
2035 break;
2036 case CACHE_CG:
2037 n = 1;
2038 break;
2039 case CACHE_CS:
2040 n = 2;
2041 break;
2042 case CACHE_CV:
2043 // case CACHE_WT:
2044 n = 3;
2045 break;
2046 default:
2047 n = 0;
2048 assert(!"invalid caching mode");
2049 break;
2050 }
2051 code[pos / 32] |= n << (pos % 32);
2052 }
2053
2054 void
2055 CodeEmitterGK110::emitSTORE(const Instruction *i)
2056 {
2057 int32_t offset = SDATA(i->src(0)).offset;
2058
2059 switch (i->src(0).getFile()) {
2060 case FILE_MEMORY_GLOBAL: code[1] = 0xe0000000; code[0] = 0x00000000; break;
2061 case FILE_MEMORY_LOCAL: code[1] = 0x7a800000; code[0] = 0x00000002; break;
2062 case FILE_MEMORY_SHARED:
2063 code[0] = 0x00000002;
2064 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED)
2065 code[1] = 0x78400000;
2066 else
2067 code[1] = 0x7ac00000;
2068 break;
2069 default:
2070 assert(!"invalid memory file");
2071 break;
2072 }
2073
2074 if (code[0] & 0x2) {
2075 offset &= 0xffffff;
2076 emitLoadStoreType(i->dType, 0x33);
2077 if (i->src(0).getFile() == FILE_MEMORY_LOCAL)
2078 emitCachingMode(i->cache, 0x2f);
2079 } else {
2080 emitLoadStoreType(i->dType, 0x38);
2081 emitCachingMode(i->cache, 0x3b);
2082 }
2083 code[0] |= offset << 23;
2084 code[1] |= offset >> 9;
2085
2086 // Unlocked store on shared memory can fail.
2087 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
2088 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
2089 assert(i->defExists(0));
2090 defId(i->def(0), 32 + 16);
2091 }
2092
2093 emitPredicate(i);
2094
2095 srcId(i->src(1), 2);
2096 srcId(i->src(0).getIndirect(0), 10);
2097 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2098 i->src(0).isIndirect(0) &&
2099 i->getIndirect(0, 0)->reg.size == 8)
2100 code[1] |= 1 << 23;
2101 }
2102
2103 void
2104 CodeEmitterGK110::emitLOAD(const Instruction *i)
2105 {
2106 int32_t offset = SDATA(i->src(0)).offset;
2107
2108 switch (i->src(0).getFile()) {
2109 case FILE_MEMORY_GLOBAL: code[1] = 0xc0000000; code[0] = 0x00000000; break;
2110 case FILE_MEMORY_LOCAL: code[1] = 0x7a000000; code[0] = 0x00000002; break;
2111 case FILE_MEMORY_SHARED:
2112 code[0] = 0x00000002;
2113 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED)
2114 code[1] = 0x77400000;
2115 else
2116 code[1] = 0x7a400000;
2117 break;
2118 case FILE_MEMORY_CONST:
2119 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
2120 emitMOV(i);
2121 return;
2122 }
2123 offset &= 0xffff;
2124 code[0] = 0x00000002;
2125 code[1] = 0x7c800000 | (i->src(0).get()->reg.fileIndex << 7);
2126 code[1] |= i->subOp << 15;
2127 break;
2128 default:
2129 assert(!"invalid memory file");
2130 break;
2131 }
2132
2133 if (code[0] & 0x2) {
2134 offset &= 0xffffff;
2135 emitLoadStoreType(i->dType, 0x33);
2136 if (i->src(0).getFile() == FILE_MEMORY_LOCAL)
2137 emitCachingMode(i->cache, 0x2f);
2138 } else {
2139 emitLoadStoreType(i->dType, 0x38);
2140 emitCachingMode(i->cache, 0x3b);
2141 }
2142 code[0] |= offset << 23;
2143 code[1] |= offset >> 9;
2144
2145 // Locked store on shared memory can fail.
2146 int r = 0, p = -1;
2147 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
2148 i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
2149 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2150 r = -1;
2151 p = 0;
2152 } else if (i->defExists(1)) { // r, p
2153 p = 1;
2154 } else {
2155 assert(!"Expected predicate dest for load locked");
2156 }
2157 }
2158
2159 emitPredicate(i);
2160
2161 if (r >= 0)
2162 defId(i->def(r), 2);
2163 else
2164 code[0] |= 255 << 2;
2165
2166 if (p >= 0)
2167 defId(i->def(p), 32 + 16);
2168
2169 if (i->getIndirect(0, 0)) {
2170 srcId(i->src(0).getIndirect(0), 10);
2171 if (i->getIndirect(0, 0)->reg.size == 8)
2172 code[1] |= 1 << 23;
2173 } else {
2174 code[0] |= 255 << 10;
2175 }
2176 }
2177
2178 uint8_t
2179 CodeEmitterGK110::getSRegEncoding(const ValueRef& ref)
2180 {
2181 switch (SDATA(ref).sv.sv) {
2182 case SV_LANEID: return 0x00;
2183 case SV_PHYSID: return 0x03;
2184 case SV_VERTEX_COUNT: return 0x10;
2185 case SV_INVOCATION_ID: return 0x11;
2186 case SV_YDIR: return 0x12;
2187 case SV_THREAD_KILL: return 0x13;
2188 case SV_TID: return 0x21 + SDATA(ref).sv.index;
2189 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
2190 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
2191 case SV_GRIDID: return 0x2c;
2192 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
2193 case SV_LBASE: return 0x34;
2194 case SV_SBASE: return 0x30;
2195 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
2196 default:
2197 assert(!"no sreg for system value");
2198 return 0;
2199 }
2200 }
2201
2202 void
2203 CodeEmitterGK110::emitMOV(const Instruction *i)
2204 {
2205 if (i->def(0).getFile() == FILE_PREDICATE) {
2206 if (i->src(0).getFile() == FILE_GPR) {
2207 // Use ISETP.NE.AND dst, PT, src, RZ, PT
2208 code[0] = 0x00000002;
2209 code[1] = 0xdb500000;
2210
2211 code[0] |= 0x7 << 2;
2212 code[0] |= 0xff << 23;
2213 code[1] |= 0x7 << 10;
2214 srcId(i->src(0), 10);
2215 } else
2216 if (i->src(0).getFile() == FILE_PREDICATE) {
2217 // Use PSETP.AND.AND dst, PT, src, PT, PT
2218 code[0] = 0x00000002;
2219 code[1] = 0x84800000;
2220
2221 code[0] |= 0x7 << 2;
2222 code[1] |= 0x7 << 0;
2223 code[1] |= 0x7 << 10;
2224
2225 srcId(i->src(0), 14);
2226 } else {
2227 assert(!"Unexpected source for predicate destination");
2228 emitNOP(i);
2229 }
2230 emitPredicate(i);
2231 defId(i->def(0), 5);
2232 } else
2233 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
2234 code[0] = 0x00000002 | (getSRegEncoding(i->src(0)) << 23);
2235 code[1] = 0x86400000;
2236 emitPredicate(i);
2237 defId(i->def(0), 2);
2238 } else
2239 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2240 code[0] = 0x00000002 | (i->lanes << 14);
2241 code[1] = 0x74000000;
2242 emitPredicate(i);
2243 defId(i->def(0), 2);
2244 setImmediate32(i, 0, Modifier(0));
2245 } else
2246 if (i->src(0).getFile() == FILE_PREDICATE) {
2247 code[0] = 0x00000002;
2248 code[1] = 0x84401c07;
2249 emitPredicate(i);
2250 defId(i->def(0), 2);
2251 srcId(i->src(0), 14);
2252 } else {
2253 emitForm_C(i, 0x24c, 2);
2254 code[1] |= i->lanes << 10;
2255 }
2256 }
2257
2258 static inline bool
2259 uses64bitAddress(const Instruction *ldst)
2260 {
2261 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2262 ldst->src(0).isIndirect(0) &&
2263 ldst->getIndirect(0, 0)->reg.size == 8;
2264 }
2265
2266 void
2267 CodeEmitterGK110::emitATOM(const Instruction *i)
2268 {
2269 const bool hasDst = i->defExists(0);
2270 const bool exch = i->subOp == NV50_IR_SUBOP_ATOM_EXCH;
2271
2272 code[0] = 0x00000002;
2273 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS)
2274 code[1] = 0x77800000;
2275 else
2276 code[1] = 0x68000000;
2277
2278 switch (i->subOp) {
2279 case NV50_IR_SUBOP_ATOM_CAS: break;
2280 case NV50_IR_SUBOP_ATOM_EXCH: code[1] |= 0x04000000; break;
2281 default: code[1] |= i->subOp << 23; break;
2282 }
2283
2284 switch (i->dType) {
2285 case TYPE_U32: break;
2286 case TYPE_S32: code[1] |= 0x00100000; break;
2287 case TYPE_U64: code[1] |= 0x00200000; break;
2288 case TYPE_F32: code[1] |= 0x00300000; break;
2289 case TYPE_B128: code[1] |= 0x00400000; break; /* TODO: U128 */
2290 case TYPE_S64: code[1] |= 0x00500000; break;
2291 default: assert(!"unsupported type"); break;
2292 }
2293
2294 emitPredicate(i);
2295
2296 /* TODO: cas: check that src regs line up */
2297 /* TODO: cas: flip bits if $r255 is used */
2298 srcId(i->src(1), 23);
2299
2300 if (hasDst) {
2301 defId(i->def(0), 2);
2302 } else
2303 if (!exch) {
2304 code[0] |= 255 << 2;
2305 }
2306
2307 if (hasDst || !exch) {
2308 const int32_t offset = SDATA(i->src(0)).offset;
2309 assert(offset < 0x80000 && offset >= -0x80000);
2310 code[0] |= (offset & 1) << 31;
2311 code[1] |= (offset & 0xffffe) >> 1;
2312 } else {
2313 srcAddr32(i->src(0), 31);
2314 }
2315
2316 if (i->getIndirect(0, 0)) {
2317 srcId(i->getIndirect(0, 0), 10);
2318 if (i->getIndirect(0, 0)->reg.size == 8)
2319 code[1] |= 1 << 19;
2320 } else {
2321 code[0] |= 255 << 10;
2322 }
2323 }
2324
2325 void
2326 CodeEmitterGK110::emitCCTL(const Instruction *i)
2327 {
2328 int32_t offset = SDATA(i->src(0)).offset;
2329
2330 code[0] = 0x00000002 | (i->subOp << 2);
2331
2332 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2333 code[1] = 0x7b000000;
2334 } else {
2335 code[1] = 0x7c000000;
2336 offset &= 0xffffff;
2337 }
2338 code[0] |= offset << 23;
2339 code[1] |= offset >> 9;
2340
2341 if (uses64bitAddress(i))
2342 code[1] |= 1 << 23;
2343 srcId(i->src(0).getIndirect(0), 10);
2344
2345 emitPredicate(i);
2346 }
2347
2348 bool
2349 CodeEmitterGK110::emitInstruction(Instruction *insn)
2350 {
2351 const unsigned int size = (writeIssueDelays && !(codeSize & 0x3f)) ? 16 : 8;
2352
2353 if (insn->encSize != 8) {
2354 ERROR("skipping unencodable instruction: ");
2355 insn->print();
2356 return false;
2357 } else
2358 if (codeSize + size > codeSizeLimit) {
2359 ERROR("code emitter output buffer too small\n");
2360 return false;
2361 }
2362
2363 if (writeIssueDelays) {
2364 int id = (codeSize & 0x3f) / 8 - 1;
2365 if (id < 0) {
2366 id += 1;
2367 code[0] = 0x00000000; // cf issue delay "instruction"
2368 code[1] = 0x08000000;
2369 code += 2;
2370 codeSize += 8;
2371 }
2372 uint32_t *data = code - (id * 2 + 2);
2373
2374 switch (id) {
2375 case 0: data[0] |= insn->sched << 2; break;
2376 case 1: data[0] |= insn->sched << 10; break;
2377 case 2: data[0] |= insn->sched << 18; break;
2378 case 3: data[0] |= insn->sched << 26; data[1] |= insn->sched >> 6; break;
2379 case 4: data[1] |= insn->sched << 2; break;
2380 case 5: data[1] |= insn->sched << 10; break;
2381 case 6: data[1] |= insn->sched << 18; break;
2382 default:
2383 assert(0);
2384 break;
2385 }
2386 }
2387
2388 // assert that instructions with multiple defs don't corrupt registers
2389 for (int d = 0; insn->defExists(d); ++d)
2390 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2391
2392 switch (insn->op) {
2393 case OP_MOV:
2394 case OP_RDSV:
2395 emitMOV(insn);
2396 break;
2397 case OP_NOP:
2398 break;
2399 case OP_LOAD:
2400 emitLOAD(insn);
2401 break;
2402 case OP_STORE:
2403 emitSTORE(insn);
2404 break;
2405 case OP_LINTERP:
2406 case OP_PINTERP:
2407 emitINTERP(insn);
2408 break;
2409 case OP_VFETCH:
2410 emitVFETCH(insn);
2411 break;
2412 case OP_EXPORT:
2413 emitEXPORT(insn);
2414 break;
2415 case OP_AFETCH:
2416 emitAFETCH(insn);
2417 break;
2418 case OP_PFETCH:
2419 emitPFETCH(insn);
2420 break;
2421 case OP_EMIT:
2422 case OP_RESTART:
2423 emitOUT(insn);
2424 break;
2425 case OP_ADD:
2426 case OP_SUB:
2427 if (insn->dType == TYPE_F64)
2428 emitDADD(insn);
2429 else if (isFloatType(insn->dType))
2430 emitFADD(insn);
2431 else
2432 emitUADD(insn);
2433 break;
2434 case OP_MUL:
2435 if (insn->dType == TYPE_F64)
2436 emitDMUL(insn);
2437 else if (isFloatType(insn->dType))
2438 emitFMUL(insn);
2439 else
2440 emitIMUL(insn);
2441 break;
2442 case OP_MAD:
2443 case OP_FMA:
2444 if (insn->dType == TYPE_F64)
2445 emitDMAD(insn);
2446 else if (isFloatType(insn->dType))
2447 emitFMAD(insn);
2448 else
2449 emitIMAD(insn);
2450 break;
2451 case OP_MADSP:
2452 emitMADSP(insn);
2453 break;
2454 case OP_SAD:
2455 emitISAD(insn);
2456 break;
2457 case OP_SHLADD:
2458 emitSHLADD(insn);
2459 break;
2460 case OP_NOT:
2461 emitNOT(insn);
2462 break;
2463 case OP_AND:
2464 emitLogicOp(insn, 0);
2465 break;
2466 case OP_OR:
2467 emitLogicOp(insn, 1);
2468 break;
2469 case OP_XOR:
2470 emitLogicOp(insn, 2);
2471 break;
2472 case OP_SHL:
2473 case OP_SHR:
2474 emitShift(insn);
2475 break;
2476 case OP_SET:
2477 case OP_SET_AND:
2478 case OP_SET_OR:
2479 case OP_SET_XOR:
2480 emitSET(insn->asCmp());
2481 break;
2482 case OP_SELP:
2483 emitSELP(insn);
2484 break;
2485 case OP_SLCT:
2486 emitSLCT(insn->asCmp());
2487 break;
2488 case OP_MIN:
2489 case OP_MAX:
2490 emitMINMAX(insn);
2491 break;
2492 case OP_ABS:
2493 case OP_NEG:
2494 case OP_CEIL:
2495 case OP_FLOOR:
2496 case OP_TRUNC:
2497 case OP_SAT:
2498 emitCVT(insn);
2499 break;
2500 case OP_CVT:
2501 if (insn->def(0).getFile() == FILE_PREDICATE ||
2502 insn->src(0).getFile() == FILE_PREDICATE)
2503 emitMOV(insn);
2504 else
2505 emitCVT(insn);
2506 break;
2507 case OP_RSQ:
2508 emitSFnOp(insn, 5 + 2 * insn->subOp);
2509 break;
2510 case OP_RCP:
2511 emitSFnOp(insn, 4 + 2 * insn->subOp);
2512 break;
2513 case OP_LG2:
2514 emitSFnOp(insn, 3);
2515 break;
2516 case OP_EX2:
2517 emitSFnOp(insn, 2);
2518 break;
2519 case OP_SIN:
2520 emitSFnOp(insn, 1);
2521 break;
2522 case OP_COS:
2523 emitSFnOp(insn, 0);
2524 break;
2525 case OP_PRESIN:
2526 case OP_PREEX2:
2527 emitPreOp(insn);
2528 break;
2529 case OP_TEX:
2530 case OP_TXB:
2531 case OP_TXL:
2532 case OP_TXD:
2533 case OP_TXF:
2534 case OP_TXG:
2535 case OP_TXLQ:
2536 emitTEX(insn->asTex());
2537 break;
2538 case OP_TXQ:
2539 emitTXQ(insn->asTex());
2540 break;
2541 case OP_TEXBAR:
2542 emitTEXBAR(insn);
2543 break;
2544 case OP_PIXLD:
2545 emitPIXLD(insn);
2546 break;
2547 case OP_BRA:
2548 case OP_CALL:
2549 case OP_PRERET:
2550 case OP_RET:
2551 case OP_DISCARD:
2552 case OP_EXIT:
2553 case OP_PRECONT:
2554 case OP_CONT:
2555 case OP_PREBREAK:
2556 case OP_BREAK:
2557 case OP_JOINAT:
2558 case OP_BRKPT:
2559 case OP_QUADON:
2560 case OP_QUADPOP:
2561 emitFlow(insn);
2562 break;
2563 case OP_QUADOP:
2564 emitQUADOP(insn, insn->subOp, insn->lanes);
2565 break;
2566 case OP_DFDX:
2567 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2568 break;
2569 case OP_DFDY:
2570 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2571 break;
2572 case OP_POPCNT:
2573 emitPOPC(insn);
2574 break;
2575 case OP_INSBF:
2576 emitINSBF(insn);
2577 break;
2578 case OP_EXTBF:
2579 emitEXTBF(insn);
2580 break;
2581 case OP_BFIND:
2582 emitBFIND(insn);
2583 break;
2584 case OP_PERMT:
2585 emitPERMT(insn);
2586 break;
2587 case OP_JOIN:
2588 emitNOP(insn);
2589 insn->join = 1;
2590 break;
2591 case OP_BAR:
2592 emitBAR(insn);
2593 break;
2594 case OP_MEMBAR:
2595 emitMEMBAR(insn);
2596 break;
2597 case OP_ATOM:
2598 emitATOM(insn);
2599 break;
2600 case OP_CCTL:
2601 emitCCTL(insn);
2602 break;
2603 case OP_VOTE:
2604 emitVOTE(insn);
2605 break;
2606 case OP_SULDB:
2607 emitSULDGB(insn->asTex());
2608 break;
2609 case OP_SUSTB:
2610 case OP_SUSTP:
2611 emitSUSTGx(insn->asTex());
2612 break;
2613 case OP_SUBFM:
2614 case OP_SUCLAMP:
2615 case OP_SUEAU:
2616 emitSUCalc(insn);
2617 break;
2618 case OP_VSHL:
2619 emitVSHL(insn);
2620 break;
2621 case OP_PHI:
2622 case OP_UNION:
2623 case OP_CONSTRAINT:
2624 ERROR("operation should have been eliminated");
2625 return false;
2626 case OP_EXP:
2627 case OP_LOG:
2628 case OP_SQRT:
2629 case OP_POW:
2630 ERROR("operation should have been lowered\n");
2631 return false;
2632 default:
2633 ERROR("unknown op: %u\n", insn->op);
2634 return false;
2635 }
2636
2637 if (insn->join)
2638 code[0] |= 1 << 22;
2639
2640 code += 2;
2641 codeSize += 8;
2642 return true;
2643 }
2644
2645 uint32_t
2646 CodeEmitterGK110::getMinEncodingSize(const Instruction *i) const
2647 {
2648 // No more short instruction encodings.
2649 return 8;
2650 }
2651
2652 void
2653 CodeEmitterGK110::prepareEmission(Function *func)
2654 {
2655 const Target *targ = func->getProgram()->getTarget();
2656
2657 CodeEmitter::prepareEmission(func);
2658
2659 if (targ->hasSWSched)
2660 calculateSchedDataNVC0(targ, func);
2661 }
2662
2663 CodeEmitterGK110::CodeEmitterGK110(const TargetNVC0 *target)
2664 : CodeEmitter(target),
2665 targNVC0(target),
2666 writeIssueDelays(target->hasSWSched)
2667 {
2668 code = NULL;
2669 codeSize = codeSizeLimit = 0;
2670 relocInfo = NULL;
2671 }
2672
2673 CodeEmitter *
2674 TargetNVC0::createCodeEmitterGK110(Program::Type type)
2675 {
2676 CodeEmitterGK110 *emit = new CodeEmitterGK110(this);
2677 emit->setProgramType(type);
2678 return emit;
2679 }
2680
2681 } // namespace nv50_ir