projects / mesa.git / blob
? search:


6a5981daadf93731f552883db1a032caec2ab06c
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_gk110.cpp
1 /*
2 * Copyright 2012 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 // CodeEmitter for GK110 encoding of the Fermi/Kepler ISA.
26
27 namespace nv50_ir {
28
29 class CodeEmitterGK110 : public CodeEmitter
30 {
31 public:
32 CodeEmitterGK110(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
49 void emitForm_C(const Instruction *, uint32_t opc, uint8_t ctg);
50 void emitForm_L(const Instruction *, uint32_t opc, uint8_t ctg, Modifier);
51
52 void emitPredicate(const Instruction *);
53
54 void setCAddress14(const ValueRef&);
55 void setShortImmediate(const Instruction *, const int s);
56 void setImmediate32(const Instruction *, const int s, Modifier);
57 void setSUConst16(const Instruction *, const int s);
58
59 void modNegAbsF32_3b(const Instruction *, const int s);
60
61 void emitCondCode(CondCode cc, int pos, uint8_t mask);
62 void emitInterpMode(const Instruction *);
63 void emitLoadStoreType(DataType ty, const int pos);
64 void emitCachingMode(CacheMode c, const int pos);
65 void emitSUGType(DataType, const int pos);
66 void emitSUCachingMode(CacheMode c);
67
68 inline uint8_t getSRegEncoding(const ValueRef&);
69
70 void emitRoundMode(RoundMode, const int pos, const int rintPos);
71 void emitRoundModeF(RoundMode, const int pos);
72 void emitRoundModeI(RoundMode, const int pos);
73
74 void emitNegAbs12(const Instruction *);
75
76 void emitNOP(const Instruction *);
77
78 void emitLOAD(const Instruction *);
79 void emitSTORE(const Instruction *);
80 void emitMOV(const Instruction *);
81 void emitATOM(const Instruction *);
82 void emitCCTL(const Instruction *);
83
84 void emitINTERP(const Instruction *);
85 void emitAFETCH(const Instruction *);
86 void emitPFETCH(const Instruction *);
87 void emitVFETCH(const Instruction *);
88 void emitEXPORT(const Instruction *);
89 void emitOUT(const Instruction *);
90
91 void emitUADD(const Instruction *);
92 void emitFADD(const Instruction *);
93 void emitDADD(const Instruction *);
94 void emitIMUL(const Instruction *);
95 void emitFMUL(const Instruction *);
96 void emitDMUL(const Instruction *);
97 void emitIMAD(const Instruction *);
98 void emitISAD(const Instruction *);
99 void emitFMAD(const Instruction *);
100 void emitDMAD(const Instruction *);
101 void emitMADSP(const Instruction *i);
102
103 void emitNOT(const Instruction *);
104 void emitLogicOp(const Instruction *, uint8_t subOp);
105 void emitPOPC(const Instruction *);
106 void emitINSBF(const Instruction *);
107 void emitEXTBF(const Instruction *);
108 void emitBFIND(const Instruction *);
109 void emitPERMT(const Instruction *);
110 void emitShift(const Instruction *);
111
112 void emitSFnOp(const Instruction *, uint8_t subOp);
113
114 void emitCVT(const Instruction *);
115 void emitMINMAX(const Instruction *);
116 void emitPreOp(const Instruction *);
117
118 void emitSET(const CmpInstruction *);
119 void emitSLCT(const CmpInstruction *);
120 void emitSELP(const Instruction *);
121
122 void emitTEXBAR(const Instruction *);
123 void emitTEX(const TexInstruction *);
124 void emitTEXCSAA(const TexInstruction *);
125 void emitTXQ(const TexInstruction *);
126
127 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
128
129 void emitPIXLD(const Instruction *);
130
131 void emitBAR(const Instruction *);
132 void emitMEMBAR(const Instruction *);
133
134 void emitFlow(const Instruction *);
135
136 void emitVOTE(const Instruction *);
137
138 void emitSULDGB(const TexInstruction *);
139 void emitSUSTGx(const TexInstruction *);
140 void emitSUCLAMPMode(uint16_t);
141 void emitSUCalc(Instruction *);
142
143 void emitVSHL(const Instruction *);
144 void emitVectorSubOp(const Instruction *);
145
146 inline void defId(const ValueDef&, const int pos);
147 inline void srcId(const ValueRef&, const int pos);
148 inline void srcId(const ValueRef *, const int pos);
149 inline void srcId(const Instruction *, int s, const int pos);
150
151 inline void srcAddr32(const ValueRef&, const int pos); // address / 4
152
153 inline bool isLIMM(const ValueRef&, DataType ty, bool mod = false);
154 };
155
156 #define GK110_GPR_ZERO 255
157
158 #define NEG_(b, s) \
159 if (i->src(s).mod.neg()) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
160 #define ABS_(b, s) \
161 if (i->src(s).mod.abs()) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
162
163 #define NOT_(b, s) if (i->src(s).mod & Modifier(NV50_IR_MOD_NOT)) \
164 code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
165
166 #define FTZ_(b) if (i->ftz) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
167 #define DNZ_(b) if (i->dnz) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
168
169 #define SAT_(b) if (i->saturate) code[(0x##b) / 32] |= 1 << ((0x##b) % 32)
170
171 #define RND_(b, t) emitRoundMode##t(i->rnd, 0x##b)
172
173 #define SDATA(a) ((a).rep()->reg.data)
174 #define DDATA(a) ((a).rep()->reg.data)
175
176 void CodeEmitterGK110::srcId(const ValueRef& src, const int pos)
177 {
178 code[pos / 32] |= (src.get() ? SDATA(src).id : GK110_GPR_ZERO) << (pos % 32);
179 }
180
181 void CodeEmitterGK110::srcId(const ValueRef *src, const int pos)
182 {
183 code[pos / 32] |= (src ? SDATA(*src).id : GK110_GPR_ZERO) << (pos % 32);
184 }
185
186 void CodeEmitterGK110::srcId(const Instruction *insn, int s, int pos)
187 {
188 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : GK110_GPR_ZERO;
189 code[pos / 32] |= r << (pos % 32);
190 }
191
192 void CodeEmitterGK110::srcAddr32(const ValueRef& src, const int pos)
193 {
194 code[pos / 32] |= (SDATA(src).offset >> 2) << (pos % 32);
195 }
196
197 void CodeEmitterGK110::defId(const ValueDef& def, const int pos)
198 {
199 code[pos / 32] |= (def.get() ? DDATA(def).id : GK110_GPR_ZERO) << (pos % 32);
200 }
201
202 bool CodeEmitterGK110::isLIMM(const ValueRef& ref, DataType ty, bool mod)
203 {
204 const ImmediateValue *imm = ref.get()->asImm();
205
206 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
207 }
208
209 void
210 CodeEmitterGK110::emitRoundMode(RoundMode rnd, const int pos, const int rintPos)
211 {
212 bool rint = false;
213 uint8_t n;
214
215 switch (rnd) {
216 case ROUND_MI: rint = true; /* fall through */ case ROUND_M: n = 1; break;
217 case ROUND_PI: rint = true; /* fall through */ case ROUND_P: n = 2; break;
218 case ROUND_ZI: rint = true; /* fall through */ case ROUND_Z: n = 3; break;
219 default:
220 rint = rnd == ROUND_NI;
221 n = 0;
222 assert(rnd == ROUND_N || rnd == ROUND_NI);
223 break;
224 }
225 code[pos / 32] |= n << (pos % 32);
226 if (rint && rintPos >= 0)
227 code[rintPos / 32] |= 1 << (rintPos % 32);
228 }
229
230 void
231 CodeEmitterGK110::emitRoundModeF(RoundMode rnd, const int pos)
232 {
233 uint8_t n;
234
235 switch (rnd) {
236 case ROUND_M: n = 1; break;
237 case ROUND_P: n = 2; break;
238 case ROUND_Z: n = 3; break;
239 default:
240 n = 0;
241 assert(rnd == ROUND_N);
242 break;
243 }
244 code[pos / 32] |= n << (pos % 32);
245 }
246
247 void
248 CodeEmitterGK110::emitRoundModeI(RoundMode rnd, const int pos)
249 {
250 uint8_t n;
251
252 switch (rnd) {
253 case ROUND_MI: n = 1; break;
254 case ROUND_PI: n = 2; break;
255 case ROUND_ZI: n = 3; break;
256 default:
257 n = 0;
258 assert(rnd == ROUND_NI);
259 break;
260 }
261 code[pos / 32] |= n << (pos % 32);
262 }
263
264 void CodeEmitterGK110::emitCondCode(CondCode cc, int pos, uint8_t mask)
265 {
266 uint8_t n;
267
268 switch (cc) {
269 case CC_FL: n = 0x00; break;
270 case CC_LT: n = 0x01; break;
271 case CC_EQ: n = 0x02; break;
272 case CC_LE: n = 0x03; break;
273 case CC_GT: n = 0x04; break;
274 case CC_NE: n = 0x05; break;
275 case CC_GE: n = 0x06; break;
276 case CC_LTU: n = 0x09; break;
277 case CC_EQU: n = 0x0a; break;
278 case CC_LEU: n = 0x0b; break;
279 case CC_GTU: n = 0x0c; break;
280 case CC_NEU: n = 0x0d; break;
281 case CC_GEU: n = 0x0e; break;
282 case CC_TR: n = 0x0f; break;
283 case CC_NO: n = 0x10; break;
284 case CC_NC: n = 0x11; break;
285 case CC_NS: n = 0x12; break;
286 case CC_NA: n = 0x13; break;
287 case CC_A: n = 0x14; break;
288 case CC_S: n = 0x15; break;
289 case CC_C: n = 0x16; break;
290 case CC_O: n = 0x17; break;
291 default:
292 n = 0;
293 assert(!"invalid condition code");
294 break;
295 }
296 code[pos / 32] |= (n & mask) << (pos % 32);
297 }
298
299 void
300 CodeEmitterGK110::emitPredicate(const Instruction *i)
301 {
302 if (i->predSrc >= 0) {
303 srcId(i->src(i->predSrc), 18);
304 if (i->cc == CC_NOT_P)
305 code[0] |= 8 << 18; // negate
306 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
307 } else {
308 code[0] |= 7 << 18;
309 }
310 }
311
312 void
313 CodeEmitterGK110::setCAddress14(const ValueRef& src)
314 {
315 const Storage& res = src.get()->asSym()->reg;
316 const int32_t addr = res.data.offset / 4;
317
318 code[0] |= (addr & 0x01ff) << 23;
319 code[1] |= (addr & 0x3e00) >> 9;
320 code[1] |= res.fileIndex << 5;
321 }
322
323 void
324 CodeEmitterGK110::setShortImmediate(const Instruction *i, const int s)
325 {
326 const uint32_t u32 = i->getSrc(s)->asImm()->reg.data.u32;
327 const uint64_t u64 = i->getSrc(s)->asImm()->reg.data.u64;
328
329 if (i->sType == TYPE_F32) {
330 assert(!(u32 & 0x00000fff));
331 code[0] |= ((u32 & 0x001ff000) >> 12) << 23;
332 code[1] |= ((u32 & 0x7fe00000) >> 21);
333 code[1] |= ((u32 & 0x80000000) >> 4);
334 } else
335 if (i->sType == TYPE_F64) {
336 assert(!(u64 & 0x00000fffffffffffULL));
337 code[0] |= ((u64 & 0x001ff00000000000ULL) >> 44) << 23;
338 code[1] |= ((u64 & 0x7fe0000000000000ULL) >> 53);
339 code[1] |= ((u64 & 0x8000000000000000ULL) >> 36);
340 } else {
341 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
342 code[0] |= (u32 & 0x001ff) << 23;
343 code[1] |= (u32 & 0x7fe00) >> 9;
344 code[1] |= (u32 & 0x80000) << 8;
345 }
346 }
347
348 void
349 CodeEmitterGK110::setImmediate32(const Instruction *i, const int s,
350 Modifier mod)
351 {
352 uint32_t u32 = i->getSrc(s)->asImm()->reg.data.u32;
353
354 if (mod) {
355 ImmediateValue imm(i->getSrc(s)->asImm(), i->sType);
356 mod.applyTo(imm);
357 u32 = imm.reg.data.u32;
358 }
359
360 code[0] |= u32 << 23;
361 code[1] |= u32 >> 9;
362 }
363
364 void
365 CodeEmitterGK110::emitForm_L(const Instruction *i, uint32_t opc, uint8_t ctg,
366 Modifier mod)
367 {
368 code[0] = ctg;
369 code[1] = opc << 20;
370
371 emitPredicate(i);
372
373 defId(i->def(0), 2);
374
375 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
376 switch (i->src(s).getFile()) {
377 case FILE_GPR:
378 srcId(i->src(s), s ? 42 : 10);
379 break;
380 case FILE_IMMEDIATE:
381 setImmediate32(i, s, mod);
382 break;
383 default:
384 break;
385 }
386 }
387 }
388
389
390 void
391 CodeEmitterGK110::emitForm_C(const Instruction *i, uint32_t opc, uint8_t ctg)
392 {
393 code[0] = ctg;
394 code[1] = opc << 20;
395
396 emitPredicate(i);
397
398 defId(i->def(0), 2);
399
400 switch (i->src(0).getFile()) {
401 case FILE_MEMORY_CONST:
402 code[1] |= 0x4 << 28;
403 setCAddress14(i->src(0));
404 break;
405 case FILE_GPR:
406 code[1] |= 0xc << 28;
407 srcId(i->src(0), 23);
408 break;
409 default:
410 assert(0);
411 break;
412 }
413 }
414
415 // 0x2 for GPR, c[] and 0x1 for short immediate
416 void
417 CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2,
418 uint32_t opc1)
419 {
420 const bool imm = i->srcExists(1) && i->src(1).getFile() == FILE_IMMEDIATE;
421
422 int s1 = 23;
423 if (i->srcExists(2) && i->src(2).getFile() == FILE_MEMORY_CONST)
424 s1 = 42;
425
426 if (imm) {
427 code[0] = 0x1;
428 code[1] = opc1 << 20;
429 } else {
430 code[0] = 0x2;
431 code[1] = (0xc << 28) | (opc2 << 20);
432 }
433
434 emitPredicate(i);
435
436 defId(i->def(0), 2);
437
438 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
439 switch (i->src(s).getFile()) {
440 case FILE_MEMORY_CONST:
441 code[1] &= (s == 2) ? ~(0x4 << 28) : ~(0x8 << 28);
442 setCAddress14(i->src(s));
443 break;
444 case FILE_IMMEDIATE:
445 setShortImmediate(i, s);
446 break;
447 case FILE_GPR:
448 srcId(i->src(s), s ? ((s == 2) ? 42 : s1) : 10);
449 break;
450 default:
451 if (i->op == OP_SELP) {
452 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
453 srcId(i->src(s), 42);
454 }
455 // ignore here, can be predicate or flags, but must not be address
456 break;
457 }
458 }
459 // 0x0 = invalid
460 // 0xc = rrr
461 // 0x8 = rrc
462 // 0x4 = rcr
463 assert(imm || (code[1] & (0xc << 28)));
464 }
465
466 inline void
467 CodeEmitterGK110::modNegAbsF32_3b(const Instruction *i, const int s)
468 {
469 if (i->src(s).mod.abs()) code[1] &= ~(1 << 27);
470 if (i->src(s).mod.neg()) code[1] ^= (1 << 27);
471 }
472
473 void
474 CodeEmitterGK110::emitNOP(const Instruction *i)
475 {
476 code[0] = 0x00003c02;
477 code[1] = 0x85800000;
478
479 if (i)
480 emitPredicate(i);
481 else
482 code[0] = 0x001c3c02;
483 }
484
485 void
486 CodeEmitterGK110::emitFMAD(const Instruction *i)
487 {
488 assert(!isLIMM(i->src(1), TYPE_F32));
489
490 emitForm_21(i, 0x0c0, 0x940);
491
492 NEG_(34, 2);
493 SAT_(35);
494 RND_(36, F);
495 FTZ_(38);
496 DNZ_(39);
497
498 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
499
500 if (code[0] & 0x1) {
501 if (neg1)
502 code[1] ^= 1 << 27;
503 } else
504 if (neg1) {
505 code[1] |= 1 << 19;
506 }
507 }
508
509 void
510 CodeEmitterGK110::emitDMAD(const Instruction *i)
511 {
512 assert(!i->saturate);
513 assert(!i->ftz);
514
515 emitForm_21(i, 0x1b8, 0xb38);
516
517 NEG_(34, 2);
518 RND_(36, F);
519
520 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
521
522 if (code[0] & 0x1) {
523 if (neg1)
524 code[1] ^= 1 << 27;
525 } else
526 if (neg1) {
527 code[1] |= 1 << 19;
528 }
529 }
530
531 void
532 CodeEmitterGK110::emitMADSP(const Instruction *i)
533 {
534 emitForm_21(i, 0x140, 0xa40);
535
536 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
537 code[1] |= 0x00c00000;
538 } else {
539 code[1] |= (i->subOp & 0x00f) << 19; // imadp1
540 code[1] |= (i->subOp & 0x0f0) << 20; // imadp2
541 code[1] |= (i->subOp & 0x100) << 11; // imadp3
542 code[1] |= (i->subOp & 0x200) << 15; // imadp3
543 code[1] |= (i->subOp & 0xc00) << 12; // imadp3
544 }
545
546 if (i->flagsDef >= 0)
547 code[1] |= 1 << 18;
548 }
549
550 void
551 CodeEmitterGK110::emitFMUL(const Instruction *i)
552 {
553 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
554
555 assert(i->postFactor >= -3 && i->postFactor <= 3);
556
557 if (isLIMM(i->src(1), TYPE_F32)) {
558 emitForm_L(i, 0x200, 0x2, Modifier(0));
559
560 FTZ_(38);
561 DNZ_(39);
562 SAT_(3a);
563 if (neg)
564 code[1] ^= 1 << 22;
565
566 assert(i->postFactor == 0);
567 } else {
568 emitForm_21(i, 0x234, 0xc34);
569 code[1] |= ((i->postFactor > 0) ?
570 (7 - i->postFactor) : (0 - i->postFactor)) << 12;
571
572 RND_(2a, F);
573 FTZ_(2f);
574 DNZ_(30);
575 SAT_(35);
576
577 if (code[0] & 0x1) {
578 if (neg)
579 code[1] ^= 1 << 27;
580 } else
581 if (neg) {
582 code[1] |= 1 << 19;
583 }
584 }
585 }
586
587 void
588 CodeEmitterGK110::emitDMUL(const Instruction *i)
589 {
590 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
591
592 assert(!i->postFactor);
593 assert(!i->saturate);
594 assert(!i->ftz);
595 assert(!i->dnz);
596
597 emitForm_21(i, 0x240, 0xc40);
598
599 RND_(2a, F);
600
601 if (code[0] & 0x1) {
602 if (neg)
603 code[1] ^= 1 << 27;
604 } else
605 if (neg) {
606 code[1] |= 1 << 19;
607 }
608 }
609
610 void
611 CodeEmitterGK110::emitIMUL(const Instruction *i)
612 {
613 assert(!i->src(0).mod.neg() && !i->src(1).mod.neg());
614 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
615
616 if (i->src(1).getFile() == FILE_IMMEDIATE) {
617 emitForm_L(i, 0x280, 2, Modifier(0));
618
619 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
620 code[1] |= 1 << 24;
621 if (i->sType == TYPE_S32)
622 code[1] |= 3 << 25;
623 } else {
624 emitForm_21(i, 0x21c, 0xc1c);
625
626 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
627 code[1] |= 1 << 10;
628 if (i->sType == TYPE_S32)
629 code[1] |= 3 << 11;
630 }
631 }
632
633 void
634 CodeEmitterGK110::emitFADD(const Instruction *i)
635 {
636 if (isLIMM(i->src(1), TYPE_F32)) {
637 assert(i->rnd == ROUND_N);
638 assert(!i->saturate);
639
640 Modifier mod = i->src(1).mod ^
641 Modifier(i->op == OP_SUB ? NV50_IR_MOD_NEG : 0);
642
643 emitForm_L(i, 0x400, 0, mod);
644
645 FTZ_(3a);
646 NEG_(3b, 0);
647 ABS_(39, 0);
648 } else {
649 emitForm_21(i, 0x22c, 0xc2c);
650
651 FTZ_(2f);
652 RND_(2a, F);
653 ABS_(31, 0);
654 NEG_(33, 0);
655 SAT_(35);
656
657 if (code[0] & 0x1) {
658 modNegAbsF32_3b(i, 1);
659 if (i->op == OP_SUB) code[1] ^= 1 << 27;
660 } else {
661 ABS_(34, 1);
662 NEG_(30, 1);
663 if (i->op == OP_SUB) code[1] ^= 1 << 16;
664 }
665 }
666 }
667
668 void
669 CodeEmitterGK110::emitDADD(const Instruction *i)
670 {
671 assert(!i->saturate);
672 assert(!i->ftz);
673
674 emitForm_21(i, 0x238, 0xc38);
675 RND_(2a, F);
676 ABS_(31, 0);
677 NEG_(33, 0);
678 if (code[0] & 0x1) {
679 modNegAbsF32_3b(i, 1);
680 if (i->op == OP_SUB) code[1] ^= 1 << 27;
681 } else {
682 NEG_(30, 1);
683 ABS_(34, 1);
684 if (i->op == OP_SUB) code[1] ^= 1 << 16;
685 }
686 }
687
688 void
689 CodeEmitterGK110::emitUADD(const Instruction *i)
690 {
691 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(1).mod.neg();
692
693 if (i->op == OP_SUB)
694 addOp ^= 1;
695
696 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
697
698 if (isLIMM(i->src(1), TYPE_S32)) {
699 emitForm_L(i, 0x400, 1, Modifier((addOp & 1) ? NV50_IR_MOD_NEG : 0));
700
701 if (addOp & 2)
702 code[1] |= 1 << 27;
703
704 assert(!i->defExists(1));
705 assert(i->flagsSrc < 0);
706
707 SAT_(39);
708 } else {
709 emitForm_21(i, 0x208, 0xc08);
710
711 assert(addOp != 3); // would be add-plus-one
712
713 code[1] |= addOp << 19;
714
715 if (i->defExists(1))
716 code[1] |= 1 << 18; // write carry
717 if (i->flagsSrc >= 0)
718 code[1] |= 1 << 14; // add carry
719
720 SAT_(35);
721 }
722 }
723
724 // TODO: shl-add
725 void
726 CodeEmitterGK110::emitIMAD(const Instruction *i)
727 {
728 uint8_t addOp =
729 (i->src(2).mod.neg() << 1) | (i->src(0).mod.neg() ^ i->src(1).mod.neg());
730
731 emitForm_21(i, 0x100, 0xa00);
732
733 assert(addOp != 3);
734 code[1] |= addOp << 26;
735
736 if (i->sType == TYPE_S32)
737 code[1] |= (1 << 19) | (1 << 24);
738
739 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
740 code[1] |= 1 << 25;
741
742 if (i->flagsDef >= 0) code[1] |= 1 << 18;
743 if (i->flagsSrc >= 0) code[1] |= 1 << 20;
744
745 SAT_(35);
746 }
747
748 void
749 CodeEmitterGK110::emitISAD(const Instruction *i)
750 {
751 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
752
753 emitForm_21(i, 0x1f4, 0xb74);
754
755 if (i->dType == TYPE_S32)
756 code[1] |= 1 << 19;
757 }
758
759 void
760 CodeEmitterGK110::emitNOT(const Instruction *i)
761 {
762 code[0] = 0x0003fc02; // logop(mov2) dst, 0, not src
763 code[1] = 0x22003800;
764
765 emitPredicate(i);
766
767 defId(i->def(0), 2);
768
769 switch (i->src(0).getFile()) {
770 case FILE_GPR:
771 code[1] |= 0xc << 28;
772 srcId(i->src(0), 23);
773 break;
774 case FILE_MEMORY_CONST:
775 code[1] |= 0x4 << 28;
776 setCAddress14(i->src(1));
777 break;
778 default:
779 assert(0);
780 break;
781 }
782 }
783
784 void
785 CodeEmitterGK110::emitLogicOp(const Instruction *i, uint8_t subOp)
786 {
787 if (i->def(0).getFile() == FILE_PREDICATE) {
788 code[0] = 0x00000002 | (subOp << 27);
789 code[1] = 0x84800000;
790
791 emitPredicate(i);
792
793 defId(i->def(0), 5);
794 srcId(i->src(0), 14);
795 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 17;
796 srcId(i->src(1), 32);
797 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 3;
798
799 if (i->defExists(1)) {
800 defId(i->def(1), 2);
801 } else {
802 code[0] |= 7 << 2;
803 }
804 // (a OP b) OP c
805 if (i->predSrc != 2 && i->srcExists(2)) {
806 code[1] |= subOp << 16;
807 srcId(i->src(2), 42);
808 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 13;
809 } else {
810 code[1] |= 7 << 10;
811 }
812 } else
813 if (isLIMM(i->src(1), TYPE_S32)) {
814 emitForm_L(i, 0x200, 0, i->src(1).mod);
815 code[1] |= subOp << 24;
816 NOT_(3a, 0);
817 } else {
818 emitForm_21(i, 0x220, 0xc20);
819 code[1] |= subOp << 12;
820 NOT_(2a, 0);
821 NOT_(2b, 1);
822 }
823 }
824
825 void
826 CodeEmitterGK110::emitPOPC(const Instruction *i)
827 {
828 assert(!isLIMM(i->src(1), TYPE_S32, true));
829
830 emitForm_21(i, 0x204, 0xc04);
831
832 NOT_(2a, 0);
833 if (!(code[0] & 0x1))
834 NOT_(2b, 1);
835 }
836
837 void
838 CodeEmitterGK110::emitINSBF(const Instruction *i)
839 {
840 emitForm_21(i, 0x1f8, 0xb78);
841 }
842
843 void
844 CodeEmitterGK110::emitEXTBF(const Instruction *i)
845 {
846 emitForm_21(i, 0x600, 0xc00);
847
848 if (i->dType == TYPE_S32)
849 code[1] |= 0x80000;
850 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
851 code[1] |= 0x800;
852 }
853
854 void
855 CodeEmitterGK110::emitBFIND(const Instruction *i)
856 {
857 emitForm_C(i, 0x218, 0x2);
858
859 if (i->dType == TYPE_S32)
860 code[1] |= 0x80000;
861 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
862 code[1] |= 0x800;
863 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
864 code[1] |= 0x1000;
865 }
866
867 void
868 CodeEmitterGK110::emitPERMT(const Instruction *i)
869 {
870 emitForm_21(i, 0x1e0, 0xb60);
871
872 code[1] |= i->subOp << 19;
873 }
874
875 void
876 CodeEmitterGK110::emitShift(const Instruction *i)
877 {
878 if (i->op == OP_SHR) {
879 emitForm_21(i, 0x214, 0xc14);
880 if (isSignedType(i->dType))
881 code[1] |= 1 << 19;
882 } else {
883 emitForm_21(i, 0x224, 0xc24);
884 }
885
886 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
887 code[1] |= 1 << 10;
888 }
889
890 void
891 CodeEmitterGK110::emitPreOp(const Instruction *i)
892 {
893 emitForm_C(i, 0x248, 0x2);
894
895 if (i->op == OP_PREEX2)
896 code[1] |= 1 << 10;
897
898 NEG_(30, 0);
899 ABS_(34, 0);
900 }
901
902 void
903 CodeEmitterGK110::emitSFnOp(const Instruction *i, uint8_t subOp)
904 {
905 code[0] = 0x00000002 | (subOp << 23);
906 code[1] = 0x84000000;
907
908 emitPredicate(i);
909
910 defId(i->def(0), 2);
911 srcId(i->src(0), 10);
912
913 NEG_(33, 0);
914 ABS_(31, 0);
915 SAT_(35);
916 }
917
918 void
919 CodeEmitterGK110::emitMINMAX(const Instruction *i)
920 {
921 uint32_t op2, op1;
922
923 switch (i->dType) {
924 case TYPE_U32:
925 case TYPE_S32:
926 op2 = 0x210;
927 op1 = 0xc10;
928 break;
929 case TYPE_F32:
930 op2 = 0x230;
931 op1 = 0xc30;
932 break;
933 case TYPE_F64:
934 op2 = 0x228;
935 op1 = 0xc28;
936 break;
937 default:
938 assert(0);
939 op2 = 0;
940 op1 = 0;
941 break;
942 }
943 emitForm_21(i, op2, op1);
944
945 if (i->dType == TYPE_S32)
946 code[1] |= 1 << 19;
947 code[1] |= (i->op == OP_MIN) ? 0x1c00 : 0x3c00; // [!]pt
948
949 FTZ_(2f);
950 ABS_(31, 0);
951 NEG_(33, 0);
952 if (code[0] & 0x1) {
953 modNegAbsF32_3b(i, 1);
954 } else {
955 ABS_(34, 1);
956 NEG_(30, 1);
957 }
958 }
959
960 void
961 CodeEmitterGK110::emitCVT(const Instruction *i)
962 {
963 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
964 const bool f2i = !isFloatType(i->dType) && isFloatType(i->sType);
965 const bool i2f = isFloatType(i->dType) && !isFloatType(i->sType);
966
967 bool sat = i->saturate;
968 bool abs = i->src(0).mod.abs();
969 bool neg = i->src(0).mod.neg();
970
971 RoundMode rnd = i->rnd;
972
973 switch (i->op) {
974 case OP_CEIL: rnd = f2f ? ROUND_PI : ROUND_P; break;
975 case OP_FLOOR: rnd = f2f ? ROUND_MI : ROUND_M; break;
976 case OP_TRUNC: rnd = f2f ? ROUND_ZI : ROUND_Z; break;
977 case OP_SAT: sat = true; break;
978 case OP_NEG: neg = !neg; break;
979 case OP_ABS: abs = true; neg = false; break;
980 default:
981 break;
982 }
983
984 DataType dType;
985
986 if (i->op == OP_NEG && i->dType == TYPE_U32)
987 dType = TYPE_S32;
988 else
989 dType = i->dType;
990
991
992 uint32_t op;
993
994 if (f2f) op = 0x254;
995 else if (f2i) op = 0x258;
996 else if (i2f) op = 0x25c;
997 else op = 0x260;
998
999 emitForm_C(i, op, 0x2);
1000
1001 FTZ_(2f);
1002 if (neg) code[1] |= 1 << 16;
1003 if (abs) code[1] |= 1 << 20;
1004 if (sat) code[1] |= 1 << 21;
1005
1006 emitRoundMode(rnd, 32 + 10, f2f ? (32 + 13) : -1);
1007
1008 code[0] |= typeSizeofLog2(dType) << 10;
1009 code[0] |= typeSizeofLog2(i->sType) << 12;
1010 code[1] |= i->subOp << 12;
1011
1012 if (isSignedIntType(dType))
1013 code[0] |= 0x4000;
1014 if (isSignedIntType(i->sType))
1015 code[0] |= 0x8000;
1016 }
1017
1018 void
1019 CodeEmitterGK110::emitSET(const CmpInstruction *i)
1020 {
1021 uint16_t op1, op2;
1022
1023 if (i->def(0).getFile() == FILE_PREDICATE) {
1024 switch (i->sType) {
1025 case TYPE_F32: op2 = 0x1d8; op1 = 0xb58; break;
1026 case TYPE_F64: op2 = 0x1c0; op1 = 0xb40; break;
1027 default:
1028 op2 = 0x1b0;
1029 op1 = 0xb30;
1030 break;
1031 }
1032 emitForm_21(i, op2, op1);
1033
1034 NEG_(2e, 0);
1035 ABS_(9, 0);
1036 if (!(code[0] & 0x1)) {
1037 NEG_(8, 1);
1038 ABS_(2f, 1);
1039 } else {
1040 modNegAbsF32_3b(i, 1);
1041 }
1042 FTZ_(32);
1043
1044 // normal DST field is negated predicate result
1045 code[0] = (code[0] & ~0xfc) | ((code[0] << 3) & 0xe0);
1046 if (i->defExists(1))
1047 defId(i->def(1), 2);
1048 else
1049 code[0] |= 0x1c;
1050 } else {
1051 switch (i->sType) {
1052 case TYPE_F32: op2 = 0x000; op1 = 0x800; break;
1053 case TYPE_F64: op2 = 0x080; op1 = 0x900; break;
1054 default:
1055 op2 = 0x1a8;
1056 op1 = 0xb28;
1057 break;
1058 }
1059 emitForm_21(i, op2, op1);
1060
1061 NEG_(2e, 0);
1062 ABS_(39, 0);
1063 if (!(code[0] & 0x1)) {
1064 NEG_(38, 1);
1065 ABS_(2f, 1);
1066 } else {
1067 modNegAbsF32_3b(i, 1);
1068 }
1069 FTZ_(3a);
1070
1071 if (i->dType == TYPE_F32) {
1072 if (isFloatType(i->sType))
1073 code[1] |= 1 << 23;
1074 else
1075 code[1] |= 1 << 15;
1076 }
1077 }
1078 if (i->sType == TYPE_S32)
1079 code[1] |= 1 << 19;
1080
1081 if (i->op != OP_SET) {
1082 switch (i->op) {
1083 case OP_SET_AND: code[1] |= 0x0 << 16; break;
1084 case OP_SET_OR: code[1] |= 0x1 << 16; break;
1085 case OP_SET_XOR: code[1] |= 0x2 << 16; break;
1086 default:
1087 assert(0);
1088 break;
1089 }
1090 srcId(i->src(2), 0x2a);
1091 } else {
1092 code[1] |= 0x7 << 10;
1093 }
1094 emitCondCode(i->setCond,
1095 isFloatType(i->sType) ? 0x33 : 0x34,
1096 isFloatType(i->sType) ? 0xf : 0x7);
1097 }
1098
1099 void
1100 CodeEmitterGK110::emitSLCT(const CmpInstruction *i)
1101 {
1102 CondCode cc = i->setCond;
1103 if (i->src(2).mod.neg())
1104 cc = reverseCondCode(cc);
1105
1106 if (i->dType == TYPE_F32) {
1107 emitForm_21(i, 0x1d0, 0xb50);
1108 FTZ_(32);
1109 emitCondCode(cc, 0x33, 0xf);
1110 } else {
1111 emitForm_21(i, 0x1a0, 0xb20);
1112 emitCondCode(cc, 0x34, 0x7);
1113 }
1114 }
1115
1116 static void
1117 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1118 {
1119 int loc = entry->loc;
1120 if (data.force_persample_interp)
1121 code[loc + 1] |= 1 << 13;
1122 else
1123 code[loc + 1] &= ~(1 << 13);
1124 }
1125
1126 void CodeEmitterGK110::emitSELP(const Instruction *i)
1127 {
1128 emitForm_21(i, 0x250, 0x050);
1129
1130 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1131 code[1] |= 1 << 13;
1132
1133 if (i->subOp == 1) {
1134 addInterp(0, 0, selpFlip);
1135 }
1136 }
1137
1138 void CodeEmitterGK110::emitTEXBAR(const Instruction *i)
1139 {
1140 code[0] = 0x0000003e | (i->subOp << 23);
1141 code[1] = 0x77000000;
1142
1143 emitPredicate(i);
1144 }
1145
1146 void CodeEmitterGK110::emitTEXCSAA(const TexInstruction *i)
1147 {
1148 code[0] = 0x00000002;
1149 code[1] = 0x76c00000;
1150
1151 code[1] |= i->tex.r << 9;
1152 // code[1] |= i->tex.s << (9 + 8);
1153
1154 if (i->tex.liveOnly)
1155 code[0] |= 0x80000000;
1156
1157 defId(i->def(0), 2);
1158 srcId(i->src(0), 10);
1159 }
1160
1161 static inline bool
1162 isNextIndependentTex(const TexInstruction *i)
1163 {
1164 if (!i->next || !isTextureOp(i->next->op))
1165 return false;
1166 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1167 return false;
1168 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1169 }
1170
1171 void
1172 CodeEmitterGK110::emitTEX(const TexInstruction *i)
1173 {
1174 const bool ind = i->tex.rIndirectSrc >= 0;
1175
1176 if (ind) {
1177 code[0] = 0x00000002;
1178 switch (i->op) {
1179 case OP_TXD:
1180 code[1] = 0x7e000000;
1181 break;
1182 case OP_TXLQ:
1183 code[1] = 0x7e800000;
1184 break;
1185 case OP_TXF:
1186 code[1] = 0x78000000;
1187 break;
1188 case OP_TXG:
1189 code[1] = 0x7dc00000;
1190 break;
1191 default:
1192 code[1] = 0x7d800000;
1193 break;
1194 }
1195 } else {
1196 switch (i->op) {
1197 case OP_TXD:
1198 code[0] = 0x00000002;
1199 code[1] = 0x76000000;
1200 code[1] |= i->tex.r << 9;
1201 break;
1202 case OP_TXLQ:
1203 code[0] = 0x00000002;
1204 code[1] = 0x76800000;
1205 code[1] |= i->tex.r << 9;
1206 break;
1207 case OP_TXF:
1208 code[0] = 0x00000002;
1209 code[1] = 0x70000000;
1210 code[1] |= i->tex.r << 13;
1211 break;
1212 case OP_TXG:
1213 code[0] = 0x00000001;
1214 code[1] = 0x70000000;
1215 code[1] |= i->tex.r << 15;
1216 break;
1217 default:
1218 code[0] = 0x00000001;
1219 code[1] = 0x60000000;
1220 code[1] |= i->tex.r << 15;
1221 break;
1222 }
1223 }
1224
1225 code[1] |= isNextIndependentTex(i) ? 0x1 : 0x2; // t : p mode
1226
1227 if (i->tex.liveOnly)
1228 code[0] |= 0x80000000;
1229
1230 switch (i->op) {
1231 case OP_TEX: break;
1232 case OP_TXB: code[1] |= 0x2000; break;
1233 case OP_TXL: code[1] |= 0x3000; break;
1234 case OP_TXF: break;
1235 case OP_TXG: break;
1236 case OP_TXD: break;
1237 case OP_TXLQ: break;
1238 default:
1239 assert(!"invalid texture op");
1240 break;
1241 }
1242
1243 if (i->op == OP_TXF) {
1244 if (!i->tex.levelZero)
1245 code[1] |= 0x1000;
1246 } else
1247 if (i->tex.levelZero) {
1248 code[1] |= 0x1000;
1249 }
1250
1251 if (i->op != OP_TXD && i->tex.derivAll)
1252 code[1] |= 0x200;
1253
1254 emitPredicate(i);
1255
1256 code[1] |= i->tex.mask << 2;
1257
1258 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1259
1260 defId(i->def(0), 2);
1261 srcId(i->src(0), 10);
1262 srcId(i, src1, 23);
1263
1264 if (i->op == OP_TXG) code[1] |= i->tex.gatherComp << 13;
1265
1266 // texture target:
1267 code[1] |= (i->tex.target.isCube() ? 3 : (i->tex.target.getDim() - 1)) << 7;
1268 if (i->tex.target.isArray())
1269 code[1] |= 0x40;
1270 if (i->tex.target.isShadow())
1271 code[1] |= 0x400;
1272 if (i->tex.target == TEX_TARGET_2D_MS ||
1273 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1274 code[1] |= 0x800;
1275
1276 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1277 // ?
1278 }
1279
1280 if (i->tex.useOffsets == 1) {
1281 switch (i->op) {
1282 case OP_TXF: code[1] |= 0x200; break;
1283 case OP_TXD: code[1] |= 0x00400000; break;
1284 default: code[1] |= 0x800; break;
1285 }
1286 }
1287 if (i->tex.useOffsets == 4)
1288 code[1] |= 0x1000;
1289 }
1290
1291 void
1292 CodeEmitterGK110::emitTXQ(const TexInstruction *i)
1293 {
1294 code[0] = 0x00000002;
1295 code[1] = 0x75400001;
1296
1297 switch (i->tex.query) {
1298 case TXQ_DIMS: code[0] |= 0x01 << 25; break;
1299 case TXQ_TYPE: code[0] |= 0x02 << 25; break;
1300 case TXQ_SAMPLE_POSITION: code[0] |= 0x05 << 25; break;
1301 case TXQ_FILTER: code[0] |= 0x10 << 25; break;
1302 case TXQ_LOD: code[0] |= 0x12 << 25; break;
1303 case TXQ_BORDER_COLOUR: code[0] |= 0x16 << 25; break;
1304 default:
1305 assert(!"invalid texture query");
1306 break;
1307 }
1308
1309 code[1] |= i->tex.mask << 2;
1310 code[1] |= i->tex.r << 9;
1311 if (/*i->tex.sIndirectSrc >= 0 || */i->tex.rIndirectSrc >= 0)
1312 code[1] |= 0x08000000;
1313
1314 defId(i->def(0), 2);
1315 srcId(i->src(0), 10);
1316
1317 emitPredicate(i);
1318 }
1319
1320 void
1321 CodeEmitterGK110::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1322 {
1323 code[0] = 0x00000002 | ((qOp & 1) << 31);
1324 code[1] = 0x7fc00000 | (qOp >> 1) | (laneMask << 12);
1325
1326 defId(i->def(0), 2);
1327 srcId(i->src(0), 10);
1328 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 23);
1329
1330 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1331 code[1] |= 1 << 9; // dall
1332
1333 emitPredicate(i);
1334 }
1335
1336 void
1337 CodeEmitterGK110::emitPIXLD(const Instruction *i)
1338 {
1339 emitForm_L(i, 0x7f4, 2, Modifier(0));
1340 code[1] |= i->subOp << 2;
1341 code[1] |= 0x00070000;
1342 }
1343
1344 void
1345 CodeEmitterGK110::emitBAR(const Instruction *i)
1346 {
1347 code[0] = 0x00000002;
1348 code[1] = 0x85400000;
1349
1350 switch (i->subOp) {
1351 case NV50_IR_SUBOP_BAR_ARRIVE: code[1] |= 0x08; break;
1352 case NV50_IR_SUBOP_BAR_RED_AND: code[1] |= 0x50; break;
1353 case NV50_IR_SUBOP_BAR_RED_OR: code[1] |= 0x90; break;
1354 case NV50_IR_SUBOP_BAR_RED_POPC: code[1] |= 0x10; break;
1355 default:
1356 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1357 break;
1358 }
1359
1360 emitPredicate(i);
1361
1362 // barrier id
1363 if (i->src(0).getFile() == FILE_GPR) {
1364 srcId(i->src(0), 10);
1365 } else {
1366 ImmediateValue *imm = i->getSrc(0)->asImm();
1367 assert(imm);
1368 code[0] |= imm->reg.data.u32 << 10;
1369 code[1] |= 0x8000;
1370 }
1371
1372 // thread count
1373 if (i->src(1).getFile() == FILE_GPR) {
1374 srcId(i->src(1), 23);
1375 } else {
1376 ImmediateValue *imm = i->getSrc(0)->asImm();
1377 assert(imm);
1378 assert(imm->reg.data.u32 <= 0xfff);
1379 code[0] |= imm->reg.data.u32 << 23;
1380 code[1] |= imm->reg.data.u32 >> 9;
1381 code[1] |= 0x4000;
1382 }
1383
1384 if (i->srcExists(2) && (i->predSrc != 2)) {
1385 srcId(i->src(2), 32 + 10);
1386 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1387 code[1] |= 1 << 13;
1388 } else {
1389 code[1] |= 7 << 10;
1390 }
1391 }
1392
1393 void CodeEmitterGK110::emitMEMBAR(const Instruction *i)
1394 {
1395 code[0] = 0x00000002 | NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) << 8;
1396 code[1] = 0x7cc00000;
1397
1398 emitPredicate(i);
1399 }
1400
1401 void
1402 CodeEmitterGK110::emitFlow(const Instruction *i)
1403 {
1404 const FlowInstruction *f = i->asFlow();
1405
1406 unsigned mask; // bit 0: predicate, bit 1: target
1407
1408 code[0] = 0x00000000;
1409
1410 switch (i->op) {
1411 case OP_BRA:
1412 code[1] = f->absolute ? 0x10800000 : 0x12000000;
1413 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1414 code[0] |= 0x80;
1415 mask = 3;
1416 break;
1417 case OP_CALL:
1418 code[1] = f->absolute ? 0x11000000 : 0x13000000;
1419 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1420 code[0] |= 0x80;
1421 mask = 2;
1422 break;
1423
1424 case OP_EXIT: code[1] = 0x18000000; mask = 1; break;
1425 case OP_RET: code[1] = 0x19000000; mask = 1; break;
1426 case OP_DISCARD: code[1] = 0x19800000; mask = 1; break;
1427 case OP_BREAK: code[1] = 0x1a000000; mask = 1; break;
1428 case OP_CONT: code[1] = 0x1a800000; mask = 1; break;
1429
1430 case OP_JOINAT: code[1] = 0x14800000; mask = 2; break;
1431 case OP_PREBREAK: code[1] = 0x15000000; mask = 2; break;
1432 case OP_PRECONT: code[1] = 0x15800000; mask = 2; break;
1433 case OP_PRERET: code[1] = 0x13800000; mask = 2; break;
1434
1435 case OP_QUADON: code[1] = 0x1b800000; mask = 0; break;
1436 case OP_QUADPOP: code[1] = 0x1c000000; mask = 0; break;
1437 case OP_BRKPT: code[1] = 0x00000000; mask = 0; break;
1438 default:
1439 assert(!"invalid flow operation");
1440 return;
1441 }
1442
1443 if (mask & 1) {
1444 emitPredicate(i);
1445 if (i->flagsSrc < 0)
1446 code[0] |= 0x3c;
1447 }
1448
1449 if (!f)
1450 return;
1451
1452 if (f->allWarp)
1453 code[0] |= 1 << 9;
1454 if (f->limit)
1455 code[0] |= 1 << 8;
1456
1457 if (f->op == OP_CALL) {
1458 if (f->builtin) {
1459 assert(f->absolute);
1460 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1461 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xff800000, 23);
1462 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x007fffff, -9);
1463 } else {
1464 assert(!f->absolute);
1465 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1466 code[0] |= (pcRel & 0x1ff) << 23;
1467 code[1] |= (pcRel >> 9) & 0x7fff;
1468 }
1469 } else
1470 if (mask & 2) {
1471 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1472 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1473 pcRel += 8;
1474 // currently we don't want absolute branches
1475 assert(!f->absolute);
1476 code[0] |= (pcRel & 0x1ff) << 23;
1477 code[1] |= (pcRel >> 9) & 0x7fff;
1478 }
1479 }
1480
1481 void
1482 CodeEmitterGK110::emitVOTE(const Instruction *i)
1483 {
1484 assert(i->src(0).getFile() == FILE_PREDICATE &&
1485 i->def(1).getFile() == FILE_PREDICATE);
1486
1487 code[0] = 0x00000002;
1488 code[1] = 0x86c00000 | (i->subOp << 19);
1489
1490 emitPredicate(i);
1491
1492 defId(i->def(0), 2);
1493 defId(i->def(1), 48);
1494 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
1495 code[1] |= 1 << 13;
1496 srcId(i->src(0), 42);
1497 }
1498
1499 void
1500 CodeEmitterGK110::emitSUGType(DataType ty, const int pos)
1501 {
1502 uint8_t n = 0;
1503
1504 switch (ty) {
1505 case TYPE_S32: n = 1; break;
1506 case TYPE_U8: n = 2; break;
1507 case TYPE_S8: n = 3; break;
1508 default:
1509 assert(ty == TYPE_U32);
1510 break;
1511 }
1512 code[pos / 32] |= n << (pos % 32);
1513 }
1514
1515 void
1516 CodeEmitterGK110::emitSUCachingMode(CacheMode c)
1517 {
1518 uint8_t n = 0;
1519
1520 switch (c) {
1521 case CACHE_CA:
1522 // case CACHE_WB:
1523 n = 0;
1524 break;
1525 case CACHE_CG:
1526 n = 1;
1527 break;
1528 case CACHE_CS:
1529 n = 2;
1530 break;
1531 case CACHE_CV:
1532 // case CACHE_WT:
1533 n = 3;
1534 break;
1535 default:
1536 assert(!"invalid caching mode");
1537 break;
1538 }
1539 code[0] |= (n & 1) << 31;
1540 code[1] |= (n & 2) >> 1;
1541 }
1542
1543 void
1544 CodeEmitterGK110::setSUConst16(const Instruction *i, const int s)
1545 {
1546 const uint32_t offset = i->getSrc(s)->reg.data.offset;
1547
1548 assert(offset == (offset & 0xfffc));
1549
1550 code[0] |= offset << 21;
1551 code[1] |= offset >> 11;
1552 code[1] |= i->getSrc(s)->reg.fileIndex << 5;
1553 }
1554
1555 void
1556 CodeEmitterGK110::emitSULDGB(const TexInstruction *i)
1557 {
1558 code[0] = 0x00000002;
1559 code[1] = 0x30000000 | (i->subOp << 14);
1560
1561 if (i->src(1).getFile() == FILE_MEMORY_CONST) {
1562 emitLoadStoreType(i->dType, 0x38);
1563 emitCachingMode(i->cache, 0x36);
1564
1565 // format
1566 setSUConst16(i, 1);
1567 } else {
1568 assert(i->src(1).getFile() == FILE_GPR);
1569 code[1] |= 0x49800000;
1570
1571 emitLoadStoreType(i->dType, 0x21);
1572 emitSUCachingMode(i->cache);
1573
1574 srcId(i->src(1), 23);
1575 }
1576
1577 emitSUGType(i->sType, 0x34);
1578
1579 emitPredicate(i);
1580 defId(i->def(0), 2); // destination
1581 srcId(i->src(0), 10); // address
1582
1583 // surface predicate
1584 if (!i->srcExists(2) || (i->predSrc == 2)) {
1585 code[1] |= 0x7 << 10;
1586 } else {
1587 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1588 code[1] |= 1 << 13;
1589 srcId(i->src(2), 32 + 10);
1590 }
1591 }
1592
1593 void
1594 CodeEmitterGK110::emitSUSTGx(const TexInstruction *i)
1595 {
1596 assert(i->op == OP_SUSTP);
1597
1598 code[0] = 0x00000002;
1599 code[1] = 0x38000000;
1600
1601 if (i->src(1).getFile() == FILE_MEMORY_CONST) {
1602 code[0] |= i->subOp << 2;
1603
1604 if (i->op == OP_SUSTP)
1605 code[0] |= i->tex.mask << 4;
1606
1607 emitSUGType(i->sType, 0x8);
1608 emitCachingMode(i->cache, 0x36);
1609
1610 // format
1611 setSUConst16(i, 1);
1612 } else {
1613 assert(i->src(1).getFile() == FILE_GPR);
1614
1615 code[0] |= i->subOp << 23;
1616 code[1] |= 0x41c00000;
1617
1618 if (i->op == OP_SUSTP)
1619 code[0] |= i->tex.mask << 25;
1620
1621 emitSUGType(i->sType, 0x1d);
1622 emitSUCachingMode(i->cache);
1623
1624 srcId(i->src(1), 2);
1625 }
1626
1627 emitPredicate(i);
1628 srcId(i->src(0), 10); // address
1629 srcId(i->src(3), 42); // values
1630
1631 // surface predicate
1632 if (!i->srcExists(2) || (i->predSrc == 2)) {
1633 code[1] |= 0x7 << 18;
1634 } else {
1635 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1636 code[1] |= 1 << 21;
1637 srcId(i->src(2), 32 + 18);
1638 }
1639 }
1640
1641 void
1642 CodeEmitterGK110::emitSUCLAMPMode(uint16_t subOp)
1643 {
1644 uint8_t m;
1645 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
1646 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
1647 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
1648 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
1649 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
1650 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
1651 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
1652 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
1653 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
1654 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
1655 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
1656 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
1657 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
1658 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
1659 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
1660 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
1661 default:
1662 return;
1663 }
1664 code[1] |= m << 20;
1665 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
1666 code[1] |= 1 << 24;
1667 }
1668
1669 void
1670 CodeEmitterGK110::emitSUCalc(Instruction *i)
1671 {
1672 ImmediateValue *imm = NULL;
1673 uint64_t opc1, opc2;
1674
1675 if (i->srcExists(2)) {
1676 imm = i->getSrc(2)->asImm();
1677 if (imm)
1678 i->setSrc(2, NULL); // special case, make emitForm_21 not assert
1679 }
1680
1681 switch (i->op) {
1682 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break;
1683 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break;
1684 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break;
1685 default:
1686 assert(0);
1687 return;
1688 }
1689 emitForm_21(i, opc2, opc1);
1690
1691 if (i->op == OP_SUCLAMP) {
1692 if (i->dType == TYPE_S32)
1693 code[1] |= 1 << 19;
1694 emitSUCLAMPMode(i->subOp);
1695 }
1696
1697 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
1698 code[1] |= 1 << 18;
1699
1700 if (i->op != OP_SUEAU) {
1701 const uint8_t pos = i->op == OP_SUBFM ? 19 : 16;
1702 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1703 code[0] |= 255 << 2;
1704 code[1] |= i->getDef(1)->reg.data.id << pos;
1705 } else
1706 if (i->defExists(1)) { // r, p
1707 assert(i->def(1).getFile() == FILE_PREDICATE);
1708 code[1] |= i->getDef(1)->reg.data.id << pos;
1709 } else { // r, #
1710 code[1] |= 7 << pos;
1711 }
1712 }
1713
1714 if (imm) {
1715 assert(i->op == OP_SUCLAMP);
1716 i->setSrc(2, imm);
1717 code[1] |= (imm->reg.data.u32 & 0x3f) << 10; // sint6
1718 }
1719 }
1720
1721
1722 void
1723 CodeEmitterGK110::emitVectorSubOp(const Instruction *i)
1724 {
1725 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
1726 case 0:
1727 code[1] |= (i->subOp & 0x000f) << 7; // vsrc1
1728 code[1] |= (i->subOp & 0x00e0) >> 6; // vsrc2
1729 code[1] |= (i->subOp & 0x0100) << 13; // vsrc2
1730 code[1] |= (i->subOp & 0x3c00) << 12; // vdst
1731 break;
1732 default:
1733 assert(0);
1734 break;
1735 }
1736 }
1737
1738 void
1739 CodeEmitterGK110::emitVSHL(const Instruction *i)
1740 {
1741 code[0] = 0x00000002;
1742 code[1] = 0xb8000000;
1743
1744 assert(NV50_IR_SUBOP_Vn(i->subOp) == 0);
1745
1746 if (isSignedType(i->dType)) code[1] |= 1 << 25;
1747 if (isSignedType(i->sType)) code[1] |= 1 << 19;
1748
1749 emitVectorSubOp(i);
1750
1751 emitPredicate(i);
1752 defId(i->def(0), 2);
1753 srcId(i->src(0), 10);
1754
1755 if (i->getSrc(1)->reg.file == FILE_IMMEDIATE) {
1756 ImmediateValue *imm = i->getSrc(1)->asImm();
1757 assert(imm);
1758 code[0] |= (imm->reg.data.u32 & 0x01ff) << 23;
1759 code[1] |= (imm->reg.data.u32 & 0xfe00) >> 9;
1760 } else {
1761 assert(i->getSrc(1)->reg.file == FILE_GPR);
1762 code[1] |= 1 << 21;
1763 srcId(i->src(1), 23);
1764 }
1765 srcId(i->src(2), 42);
1766
1767 if (i->saturate)
1768 code[0] |= 1 << 22;
1769 if (i->flagsDef >= 0)
1770 code[1] |= 1 << 18;
1771 }
1772
1773 void
1774 CodeEmitterGK110::emitAFETCH(const Instruction *i)
1775 {
1776 uint32_t offset = i->src(0).get()->reg.data.offset & 0x7ff;
1777
1778 code[0] = 0x00000002 | (offset << 23);
1779 code[1] = 0x7d000000 | (offset >> 9);
1780
1781 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1782 code[1] |= 0x8;
1783
1784 emitPredicate(i);
1785
1786 defId(i->def(0), 2);
1787 srcId(i->src(0).getIndirect(0), 10);
1788 }
1789
1790 void
1791 CodeEmitterGK110::emitPFETCH(const Instruction *i)
1792 {
1793 uint32_t prim = i->src(0).get()->reg.data.u32;
1794
1795 code[0] = 0x00000002 | ((prim & 0xff) << 23);
1796 code[1] = 0x7f800000;
1797
1798 emitPredicate(i);
1799
1800 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1801
1802 defId(i->def(0), 2);
1803 srcId(i, src1, 10);
1804 }
1805
1806 void
1807 CodeEmitterGK110::emitVFETCH(const Instruction *i)
1808 {
1809 unsigned int size = typeSizeof(i->dType);
1810 uint32_t offset = i->src(0).get()->reg.data.offset;
1811
1812 code[0] = 0x00000002 | (offset << 23);
1813 code[1] = 0x7ec00000 | (offset >> 9);
1814 code[1] |= (size / 4 - 1) << 18;
1815
1816 if (i->perPatch)
1817 code[1] |= 0x4;
1818 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1819 code[1] |= 0x8; // yes, TCPs can read from *outputs* of other threads
1820
1821 emitPredicate(i);
1822
1823 defId(i->def(0), 2);
1824 srcId(i->src(0).getIndirect(0), 10);
1825 srcId(i->src(0).getIndirect(1), 32 + 10); // vertex address
1826 }
1827
1828 void
1829 CodeEmitterGK110::emitEXPORT(const Instruction *i)
1830 {
1831 unsigned int size = typeSizeof(i->dType);
1832 uint32_t offset = i->src(0).get()->reg.data.offset;
1833
1834 code[0] = 0x00000002 | (offset << 23);
1835 code[1] = 0x7f000000 | (offset >> 9);
1836 code[1] |= (size / 4 - 1) << 18;
1837
1838 if (i->perPatch)
1839 code[1] |= 0x4;
1840
1841 emitPredicate(i);
1842
1843 assert(i->src(1).getFile() == FILE_GPR);
1844
1845 srcId(i->src(0).getIndirect(0), 10);
1846 srcId(i->src(0).getIndirect(1), 32 + 10); // vertex base address
1847 srcId(i->src(1), 2);
1848 }
1849
1850 void
1851 CodeEmitterGK110::emitOUT(const Instruction *i)
1852 {
1853 assert(i->src(0).getFile() == FILE_GPR);
1854
1855 emitForm_21(i, 0x1f0, 0xb70);
1856
1857 if (i->op == OP_EMIT)
1858 code[1] |= 1 << 10;
1859 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1860 code[1] |= 1 << 11;
1861 }
1862
1863 void
1864 CodeEmitterGK110::emitInterpMode(const Instruction *i)
1865 {
1866 code[1] |= (i->ipa & 0x3) << 21; // TODO: INTERP_SAMPLEID
1867 code[1] |= (i->ipa & 0xc) << (19 - 2);
1868 }
1869
1870 static void
1871 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1872 {
1873 int ipa = entry->ipa;
1874 int reg = entry->reg;
1875 int loc = entry->loc;
1876
1877 if (data.flatshade &&
1878 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1879 ipa = NV50_IR_INTERP_FLAT;
1880 reg = 0xff;
1881 } else if (data.force_persample_interp &&
1882 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1883 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1884 ipa |= NV50_IR_INTERP_CENTROID;
1885 }
1886 code[loc + 1] &= ~(0xf << 19);
1887 code[loc + 1] |= (ipa & 0x3) << 21;
1888 code[loc + 1] |= (ipa & 0xc) << (19 - 2);
1889 code[loc + 0] &= ~(0xff << 23);
1890 code[loc + 0] |= reg << 23;
1891 }
1892
1893 void
1894 CodeEmitterGK110::emitINTERP(const Instruction *i)
1895 {
1896 const uint32_t base = i->getSrc(0)->reg.data.offset;
1897
1898 code[0] = 0x00000002 | (base << 31);
1899 code[1] = 0x74800000 | (base >> 1);
1900
1901 if (i->saturate)
1902 code[1] |= 1 << 18;
1903
1904 if (i->op == OP_PINTERP) {
1905 srcId(i->src(1), 23);
1906 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1907 } else {
1908 code[0] |= 0xff << 23;
1909 addInterp(i->ipa, 0xff, interpApply);
1910 }
1911
1912 srcId(i->src(0).getIndirect(0), 10);
1913 emitInterpMode(i);
1914
1915 emitPredicate(i);
1916 defId(i->def(0), 2);
1917
1918 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1919 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 10);
1920 else
1921 code[1] |= 0xff << 10;
1922 }
1923
1924 void
1925 CodeEmitterGK110::emitLoadStoreType(DataType ty, const int pos)
1926 {
1927 uint8_t n;
1928
1929 switch (ty) {
1930 case TYPE_U8:
1931 n = 0;
1932 break;
1933 case TYPE_S8:
1934 n = 1;
1935 break;
1936 case TYPE_U16:
1937 n = 2;
1938 break;
1939 case TYPE_S16:
1940 n = 3;
1941 break;
1942 case TYPE_F32:
1943 case TYPE_U32:
1944 case TYPE_S32:
1945 n = 4;
1946 break;
1947 case TYPE_F64:
1948 case TYPE_U64:
1949 case TYPE_S64:
1950 n = 5;
1951 break;
1952 case TYPE_B128:
1953 n = 6;
1954 break;
1955 default:
1956 n = 0;
1957 assert(!"invalid ld/st type");
1958 break;
1959 }
1960 code[pos / 32] |= n << (pos % 32);
1961 }
1962
1963 void
1964 CodeEmitterGK110::emitCachingMode(CacheMode c, const int pos)
1965 {
1966 uint8_t n;
1967
1968 switch (c) {
1969 case CACHE_CA:
1970 // case CACHE_WB:
1971 n = 0;
1972 break;
1973 case CACHE_CG:
1974 n = 1;
1975 break;
1976 case CACHE_CS:
1977 n = 2;
1978 break;
1979 case CACHE_CV:
1980 // case CACHE_WT:
1981 n = 3;
1982 break;
1983 default:
1984 n = 0;
1985 assert(!"invalid caching mode");
1986 break;
1987 }
1988 code[pos / 32] |= n << (pos % 32);
1989 }
1990
1991 void
1992 CodeEmitterGK110::emitSTORE(const Instruction *i)
1993 {
1994 int32_t offset = SDATA(i->src(0)).offset;
1995
1996 switch (i->src(0).getFile()) {
1997 case FILE_MEMORY_GLOBAL: code[1] = 0xe0000000; code[0] = 0x00000000; break;
1998 case FILE_MEMORY_LOCAL: code[1] = 0x7a800000; code[0] = 0x00000002; break;
1999 case FILE_MEMORY_SHARED:
2000 code[0] = 0x00000002;
2001 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED)
2002 code[1] = 0x78400000;
2003 else
2004 code[1] = 0x7ac00000;
2005 break;
2006 default:
2007 assert(!"invalid memory file");
2008 break;
2009 }
2010
2011 if (code[0] & 0x2) {
2012 offset &= 0xffffff;
2013 emitLoadStoreType(i->dType, 0x33);
2014 if (i->src(0).getFile() == FILE_MEMORY_LOCAL)
2015 emitCachingMode(i->cache, 0x2f);
2016 } else {
2017 emitLoadStoreType(i->dType, 0x38);
2018 emitCachingMode(i->cache, 0x3b);
2019 }
2020 code[0] |= offset << 23;
2021 code[1] |= offset >> 9;
2022
2023 // Unlocked store on shared memory can fail.
2024 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
2025 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
2026 assert(i->defExists(0));
2027 defId(i->def(0), 32 + 16);
2028 }
2029
2030 emitPredicate(i);
2031
2032 srcId(i->src(1), 2);
2033 srcId(i->src(0).getIndirect(0), 10);
2034 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2035 i->src(0).isIndirect(0) &&
2036 i->getIndirect(0, 0)->reg.size == 8)
2037 code[1] |= 1 << 23;
2038 }
2039
2040 void
2041 CodeEmitterGK110::emitLOAD(const Instruction *i)
2042 {
2043 int32_t offset = SDATA(i->src(0)).offset;
2044
2045 switch (i->src(0).getFile()) {
2046 case FILE_MEMORY_GLOBAL: code[1] = 0xc0000000; code[0] = 0x00000000; break;
2047 case FILE_MEMORY_LOCAL: code[1] = 0x7a000000; code[0] = 0x00000002; break;
2048 case FILE_MEMORY_SHARED:
2049 code[0] = 0x00000002;
2050 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED)
2051 code[1] = 0x77400000;
2052 else
2053 code[1] = 0x7a400000;
2054 break;
2055 case FILE_MEMORY_CONST:
2056 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
2057 emitMOV(i);
2058 return;
2059 }
2060 offset &= 0xffff;
2061 code[0] = 0x00000002;
2062 code[1] = 0x7c800000 | (i->src(0).get()->reg.fileIndex << 7);
2063 code[1] |= i->subOp << 15;
2064 break;
2065 default:
2066 assert(!"invalid memory file");
2067 break;
2068 }
2069
2070 if (code[0] & 0x2) {
2071 offset &= 0xffffff;
2072 emitLoadStoreType(i->dType, 0x33);
2073 if (i->src(0).getFile() == FILE_MEMORY_LOCAL)
2074 emitCachingMode(i->cache, 0x2f);
2075 } else {
2076 emitLoadStoreType(i->dType, 0x38);
2077 emitCachingMode(i->cache, 0x3b);
2078 }
2079 code[0] |= offset << 23;
2080 code[1] |= offset >> 9;
2081
2082 // Locked store on shared memory can fail.
2083 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
2084 i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
2085 assert(i->defExists(1));
2086 defId(i->def(1), 32 + 16);
2087 }
2088
2089 emitPredicate(i);
2090
2091 defId(i->def(0), 2);
2092 if (i->getIndirect(0, 0)) {
2093 srcId(i->src(0).getIndirect(0), 10);
2094 if (i->getIndirect(0, 0)->reg.size == 8)
2095 code[1] |= 1 << 23;
2096 } else {
2097 code[0] |= 255 << 10;
2098 }
2099 }
2100
2101 uint8_t
2102 CodeEmitterGK110::getSRegEncoding(const ValueRef& ref)
2103 {
2104 switch (SDATA(ref).sv.sv) {
2105 case SV_LANEID: return 0x00;
2106 case SV_PHYSID: return 0x03;
2107 case SV_VERTEX_COUNT: return 0x10;
2108 case SV_INVOCATION_ID: return 0x11;
2109 case SV_YDIR: return 0x12;
2110 case SV_THREAD_KILL: return 0x13;
2111 case SV_TID: return 0x21 + SDATA(ref).sv.index;
2112 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
2113 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
2114 case SV_GRIDID: return 0x2c;
2115 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
2116 case SV_LBASE: return 0x34;
2117 case SV_SBASE: return 0x30;
2118 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
2119 default:
2120 assert(!"no sreg for system value");
2121 return 0;
2122 }
2123 }
2124
2125 void
2126 CodeEmitterGK110::emitMOV(const Instruction *i)
2127 {
2128 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
2129 code[0] = 0x00000002 | (getSRegEncoding(i->src(0)) << 23);
2130 code[1] = 0x86400000;
2131 emitPredicate(i);
2132 defId(i->def(0), 2);
2133 } else
2134 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2135 code[0] = 0x00000002 | (i->lanes << 14);
2136 code[1] = 0x74000000;
2137 emitPredicate(i);
2138 defId(i->def(0), 2);
2139 setImmediate32(i, 0, Modifier(0));
2140 } else
2141 if (i->src(0).getFile() == FILE_PREDICATE) {
2142 code[0] = 0x00000002;
2143 code[1] = 0x84401c07;
2144 emitPredicate(i);
2145 defId(i->def(0), 2);
2146 srcId(i->src(0), 14);
2147 } else {
2148 emitForm_C(i, 0x24c, 2);
2149 code[1] |= i->lanes << 10;
2150 }
2151 }
2152
2153 static inline bool
2154 uses64bitAddress(const Instruction *ldst)
2155 {
2156 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
2157 ldst->src(0).isIndirect(0) &&
2158 ldst->getIndirect(0, 0)->reg.size == 8;
2159 }
2160
2161 void
2162 CodeEmitterGK110::emitATOM(const Instruction *i)
2163 {
2164 const bool hasDst = i->defExists(0);
2165 const bool exch = i->subOp == NV50_IR_SUBOP_ATOM_EXCH;
2166
2167 code[0] = 0x00000002;
2168 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS)
2169 code[1] = 0x77800000;
2170 else
2171 code[1] = 0x68000000;
2172
2173 switch (i->subOp) {
2174 case NV50_IR_SUBOP_ATOM_CAS: break;
2175 case NV50_IR_SUBOP_ATOM_EXCH: code[1] |= 0x04000000; break;
2176 default: code[1] |= i->subOp << 23; break;
2177 }
2178
2179 switch (i->dType) {
2180 case TYPE_U32: break;
2181 case TYPE_S32: code[1] |= 0x00100000; break;
2182 case TYPE_U64: code[1] |= 0x00200000; break;
2183 case TYPE_F32: code[1] |= 0x00300000; break;
2184 case TYPE_B128: code[1] |= 0x00400000; break; /* TODO: U128 */
2185 case TYPE_S64: code[1] |= 0x00500000; break;
2186 default: assert(!"unsupported type"); break;
2187 }
2188
2189 emitPredicate(i);
2190
2191 /* TODO: cas: check that src regs line up */
2192 /* TODO: cas: flip bits if $r255 is used */
2193 srcId(i->src(1), 23);
2194
2195 if (hasDst) {
2196 defId(i->def(0), 2);
2197 } else
2198 if (!exch) {
2199 code[0] |= 255 << 2;
2200 }
2201
2202 if (hasDst || !exch) {
2203 const int32_t offset = SDATA(i->src(0)).offset;
2204 assert(offset < 0x80000 && offset >= -0x80000);
2205 code[0] |= (offset & 1) << 31;
2206 code[1] |= (offset & 0xffffe) >> 1;
2207 } else {
2208 srcAddr32(i->src(0), 31);
2209 }
2210
2211 if (i->getIndirect(0, 0)) {
2212 srcId(i->getIndirect(0, 0), 10);
2213 if (i->getIndirect(0, 0)->reg.size == 8)
2214 code[1] |= 1 << 19;
2215 } else {
2216 code[0] |= 255 << 10;
2217 }
2218 }
2219
2220 void
2221 CodeEmitterGK110::emitCCTL(const Instruction *i)
2222 {
2223 int32_t offset = SDATA(i->src(0)).offset;
2224
2225 code[0] = 0x00000002 | (i->subOp << 2);
2226
2227 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2228 code[1] = 0x7b000000;
2229 } else {
2230 code[1] = 0x7c000000;
2231 offset &= 0xffffff;
2232 }
2233 code[0] |= offset << 23;
2234 code[1] |= offset >> 9;
2235
2236 if (uses64bitAddress(i))
2237 code[1] |= 1 << 23;
2238 srcId(i->src(0).getIndirect(0), 10);
2239
2240 emitPredicate(i);
2241 }
2242
2243 bool
2244 CodeEmitterGK110::emitInstruction(Instruction *insn)
2245 {
2246 const unsigned int size = (writeIssueDelays && !(codeSize & 0x3f)) ? 16 : 8;
2247
2248 if (insn->encSize != 8) {
2249 ERROR("skipping unencodable instruction: ");
2250 insn->print();
2251 return false;
2252 } else
2253 if (codeSize + size > codeSizeLimit) {
2254 ERROR("code emitter output buffer too small\n");
2255 return false;
2256 }
2257
2258 if (writeIssueDelays) {
2259 int id = (codeSize & 0x3f) / 8 - 1;
2260 if (id < 0) {
2261 id += 1;
2262 code[0] = 0x00000000; // cf issue delay "instruction"
2263 code[1] = 0x08000000;
2264 code += 2;
2265 codeSize += 8;
2266 }
2267 uint32_t *data = code - (id * 2 + 2);
2268
2269 switch (id) {
2270 case 0: data[0] |= insn->sched << 2; break;
2271 case 1: data[0] |= insn->sched << 10; break;
2272 case 2: data[0] |= insn->sched << 18; break;
2273 case 3: data[0] |= insn->sched << 26; data[1] |= insn->sched >> 6; break;
2274 case 4: data[1] |= insn->sched << 2; break;
2275 case 5: data[1] |= insn->sched << 10; break;
2276 case 6: data[1] |= insn->sched << 18; break;
2277 default:
2278 assert(0);
2279 break;
2280 }
2281 }
2282
2283 // assert that instructions with multiple defs don't corrupt registers
2284 for (int d = 0; insn->defExists(d); ++d)
2285 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2286
2287 switch (insn->op) {
2288 case OP_MOV:
2289 case OP_RDSV:
2290 emitMOV(insn);
2291 break;
2292 case OP_NOP:
2293 break;
2294 case OP_LOAD:
2295 emitLOAD(insn);
2296 break;
2297 case OP_STORE:
2298 emitSTORE(insn);
2299 break;
2300 case OP_LINTERP:
2301 case OP_PINTERP:
2302 emitINTERP(insn);
2303 break;
2304 case OP_VFETCH:
2305 emitVFETCH(insn);
2306 break;
2307 case OP_EXPORT:
2308 emitEXPORT(insn);
2309 break;
2310 case OP_AFETCH:
2311 emitAFETCH(insn);
2312 break;
2313 case OP_PFETCH:
2314 emitPFETCH(insn);
2315 break;
2316 case OP_EMIT:
2317 case OP_RESTART:
2318 emitOUT(insn);
2319 break;
2320 case OP_ADD:
2321 case OP_SUB:
2322 if (insn->dType == TYPE_F64)
2323 emitDADD(insn);
2324 else if (isFloatType(insn->dType))
2325 emitFADD(insn);
2326 else
2327 emitUADD(insn);
2328 break;
2329 case OP_MUL:
2330 if (insn->dType == TYPE_F64)
2331 emitDMUL(insn);
2332 else if (isFloatType(insn->dType))
2333 emitFMUL(insn);
2334 else
2335 emitIMUL(insn);
2336 break;
2337 case OP_MAD:
2338 case OP_FMA:
2339 if (insn->dType == TYPE_F64)
2340 emitDMAD(insn);
2341 else if (isFloatType(insn->dType))
2342 emitFMAD(insn);
2343 else
2344 emitIMAD(insn);
2345 break;
2346 case OP_MADSP:
2347 emitMADSP(insn);
2348 break;
2349 case OP_SAD:
2350 emitISAD(insn);
2351 break;
2352 case OP_NOT:
2353 emitNOT(insn);
2354 break;
2355 case OP_AND:
2356 emitLogicOp(insn, 0);
2357 break;
2358 case OP_OR:
2359 emitLogicOp(insn, 1);
2360 break;
2361 case OP_XOR:
2362 emitLogicOp(insn, 2);
2363 break;
2364 case OP_SHL:
2365 case OP_SHR:
2366 emitShift(insn);
2367 break;
2368 case OP_SET:
2369 case OP_SET_AND:
2370 case OP_SET_OR:
2371 case OP_SET_XOR:
2372 emitSET(insn->asCmp());
2373 break;
2374 case OP_SELP:
2375 emitSELP(insn);
2376 break;
2377 case OP_SLCT:
2378 emitSLCT(insn->asCmp());
2379 break;
2380 case OP_MIN:
2381 case OP_MAX:
2382 emitMINMAX(insn);
2383 break;
2384 case OP_ABS:
2385 case OP_NEG:
2386 case OP_CEIL:
2387 case OP_FLOOR:
2388 case OP_TRUNC:
2389 case OP_SAT:
2390 emitCVT(insn);
2391 break;
2392 case OP_CVT:
2393 if (insn->def(0).getFile() == FILE_PREDICATE ||
2394 insn->src(0).getFile() == FILE_PREDICATE)
2395 emitMOV(insn);
2396 else
2397 emitCVT(insn);
2398 break;
2399 case OP_RSQ:
2400 emitSFnOp(insn, 5 + 2 * insn->subOp);
2401 break;
2402 case OP_RCP:
2403 emitSFnOp(insn, 4 + 2 * insn->subOp);
2404 break;
2405 case OP_LG2:
2406 emitSFnOp(insn, 3);
2407 break;
2408 case OP_EX2:
2409 emitSFnOp(insn, 2);
2410 break;
2411 case OP_SIN:
2412 emitSFnOp(insn, 1);
2413 break;
2414 case OP_COS:
2415 emitSFnOp(insn, 0);
2416 break;
2417 case OP_PRESIN:
2418 case OP_PREEX2:
2419 emitPreOp(insn);
2420 break;
2421 case OP_TEX:
2422 case OP_TXB:
2423 case OP_TXL:
2424 case OP_TXD:
2425 case OP_TXF:
2426 case OP_TXG:
2427 case OP_TXLQ:
2428 emitTEX(insn->asTex());
2429 break;
2430 case OP_TXQ:
2431 emitTXQ(insn->asTex());
2432 break;
2433 case OP_TEXBAR:
2434 emitTEXBAR(insn);
2435 break;
2436 case OP_PIXLD:
2437 emitPIXLD(insn);
2438 break;
2439 case OP_BRA:
2440 case OP_CALL:
2441 case OP_PRERET:
2442 case OP_RET:
2443 case OP_DISCARD:
2444 case OP_EXIT:
2445 case OP_PRECONT:
2446 case OP_CONT:
2447 case OP_PREBREAK:
2448 case OP_BREAK:
2449 case OP_JOINAT:
2450 case OP_BRKPT:
2451 case OP_QUADON:
2452 case OP_QUADPOP:
2453 emitFlow(insn);
2454 break;
2455 case OP_QUADOP:
2456 emitQUADOP(insn, insn->subOp, insn->lanes);
2457 break;
2458 case OP_DFDX:
2459 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2460 break;
2461 case OP_DFDY:
2462 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2463 break;
2464 case OP_POPCNT:
2465 emitPOPC(insn);
2466 break;
2467 case OP_INSBF:
2468 emitINSBF(insn);
2469 break;
2470 case OP_EXTBF:
2471 emitEXTBF(insn);
2472 break;
2473 case OP_BFIND:
2474 emitBFIND(insn);
2475 break;
2476 case OP_PERMT:
2477 emitPERMT(insn);
2478 break;
2479 case OP_JOIN:
2480 emitNOP(insn);
2481 insn->join = 1;
2482 break;
2483 case OP_BAR:
2484 emitBAR(insn);
2485 break;
2486 case OP_MEMBAR:
2487 emitMEMBAR(insn);
2488 break;
2489 case OP_ATOM:
2490 emitATOM(insn);
2491 break;
2492 case OP_CCTL:
2493 emitCCTL(insn);
2494 break;
2495 case OP_VOTE:
2496 emitVOTE(insn);
2497 break;
2498 case OP_SULDB:
2499 emitSULDGB(insn->asTex());
2500 break;
2501 case OP_SUSTB:
2502 case OP_SUSTP:
2503 emitSUSTGx(insn->asTex());
2504 break;
2505 case OP_SUBFM:
2506 case OP_SUCLAMP:
2507 case OP_SUEAU:
2508 emitSUCalc(insn);
2509 break;
2510 case OP_VSHL:
2511 emitVSHL(insn);
2512 break;
2513 case OP_PHI:
2514 case OP_UNION:
2515 case OP_CONSTRAINT:
2516 ERROR("operation should have been eliminated");
2517 return false;
2518 case OP_EXP:
2519 case OP_LOG:
2520 case OP_SQRT:
2521 case OP_POW:
2522 ERROR("operation should have been lowered\n");
2523 return false;
2524 default:
2525 ERROR("unknown op: %u\n", insn->op);
2526 return false;
2527 }
2528
2529 if (insn->join)
2530 code[0] |= 1 << 22;
2531
2532 code += 2;
2533 codeSize += 8;
2534 return true;
2535 }
2536
2537 uint32_t
2538 CodeEmitterGK110::getMinEncodingSize(const Instruction *i) const
2539 {
2540 // No more short instruction encodings.
2541 return 8;
2542 }
2543
2544 void
2545 CodeEmitterGK110::prepareEmission(Function *func)
2546 {
2547 const Target *targ = func->getProgram()->getTarget();
2548
2549 CodeEmitter::prepareEmission(func);
2550
2551 if (targ->hasSWSched)
2552 calculateSchedDataNVC0(targ, func);
2553 }
2554
2555 CodeEmitterGK110::CodeEmitterGK110(const TargetNVC0 *target)
2556 : CodeEmitter(target),
2557 targNVC0(target),
2558 writeIssueDelays(target->hasSWSched)
2559 {
2560 code = NULL;
2561 codeSize = codeSizeLimit = 0;
2562 relocInfo = NULL;
2563 }
2564
2565 CodeEmitter *
2566 TargetNVC0::createCodeEmitterGK110(Program::Type type)
2567 {
2568 CodeEmitterGK110 *emit = new CodeEmitterGK110(this);
2569 emit->setProgramType(type);
2570 return emit;
2571 }
2572
2573 } // namespace nv50_ir