projects / mesa.git / blob
? search:


145868813e31776f89e4cf7e26468d1e2d11e393
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitSUAddr(const TexInstruction *);
67 void emitSUDim(const TexInstruction *);
68 void emitCachingMode(CacheMode c);
69
70 void emitShortSrc2(const ValueRef&);
71
72 inline uint8_t getSRegEncoding(const ValueRef&);
73
74 void roundMode_A(const Instruction *);
75 void roundMode_C(const Instruction *);
76 void roundMode_CS(const Instruction *);
77
78 void emitNegAbs12(const Instruction *);
79
80 void emitNOP(const Instruction *);
81
82 void emitLOAD(const Instruction *);
83 void emitSTORE(const Instruction *);
84 void emitMOV(const Instruction *);
85 void emitATOM(const Instruction *);
86 void emitMEMBAR(const Instruction *);
87 void emitCCTL(const Instruction *);
88
89 void emitINTERP(const Instruction *);
90 void emitAFETCH(const Instruction *);
91 void emitPFETCH(const Instruction *);
92 void emitVFETCH(const Instruction *);
93 void emitEXPORT(const Instruction *);
94 void emitOUT(const Instruction *);
95
96 void emitUADD(const Instruction *);
97 void emitFADD(const Instruction *);
98 void emitDADD(const Instruction *);
99 void emitUMUL(const Instruction *);
100 void emitFMUL(const Instruction *);
101 void emitDMUL(const Instruction *);
102 void emitIMAD(const Instruction *);
103 void emitISAD(const Instruction *);
104 void emitSHLADD(const Instruction *a);
105 void emitFMAD(const Instruction *);
106 void emitDMAD(const Instruction *);
107 void emitMADSP(const Instruction *);
108
109 void emitNOT(Instruction *);
110 void emitLogicOp(const Instruction *, uint8_t subOp);
111 void emitPOPC(const Instruction *);
112 void emitINSBF(const Instruction *);
113 void emitEXTBF(const Instruction *);
114 void emitBFIND(const Instruction *);
115 void emitPERMT(const Instruction *);
116 void emitShift(const Instruction *);
117
118 void emitSFnOp(const Instruction *, uint8_t subOp);
119
120 void emitCVT(Instruction *);
121 void emitMINMAX(const Instruction *);
122 void emitPreOp(const Instruction *);
123
124 void emitSET(const CmpInstruction *);
125 void emitSLCT(const CmpInstruction *);
126 void emitSELP(const Instruction *);
127
128 void emitTEXBAR(const Instruction *);
129 void emitTEX(const TexInstruction *);
130 void emitTEXCSAA(const TexInstruction *);
131 void emitTXQ(const TexInstruction *);
132
133 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
134
135 void emitFlow(const Instruction *);
136 void emitBAR(const Instruction *);
137
138 void emitSUCLAMPMode(uint16_t);
139 void emitSUCalc(Instruction *);
140 void emitSULDGB(const TexInstruction *);
141 void emitSUSTGx(const TexInstruction *);
142
143 void emitSULDB(const TexInstruction *);
144 void emitSUSTx(const TexInstruction *);
145 void emitSULEA(const TexInstruction *);
146
147 void emitVSHL(const Instruction *);
148 void emitVectorSubOp(const Instruction *);
149
150 void emitPIXLD(const Instruction *);
151
152 void emitVOTE(const Instruction *);
153
154 inline void defId(const ValueDef&, const int pos);
155 inline void defId(const Instruction *, int d, const int pos);
156 inline void srcId(const ValueRef&, const int pos);
157 inline void srcId(const ValueRef *, const int pos);
158 inline void srcId(const Instruction *, int s, const int pos);
159 inline void srcAddr32(const ValueRef&, int pos, int shr);
160
161 inline bool isLIMM(const ValueRef&, DataType ty);
162 };
163
164 // for better visibility
165 #define HEX64(h, l) 0x##h##l##ULL
166
167 #define SDATA(a) ((a).rep()->reg.data)
168 #define DDATA(a) ((a).rep()->reg.data)
169
170 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
171 {
172 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
173 }
174
175 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
176 {
177 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
178 }
179
180 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
181 {
182 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
183 code[pos / 32] |= r << (pos % 32);
184 }
185
186 void
187 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
188 {
189 const uint32_t offset = SDATA(src).offset >> shr;
190
191 code[pos / 32] |= offset << (pos % 32);
192 if (pos && (pos < 32))
193 code[1] |= offset >> (32 - pos);
194 }
195
196 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
197 {
198 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
199 }
200
201 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
202 {
203 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
204 code[pos / 32] |= r << (pos % 32);
205 }
206
207 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
208 {
209 const ImmediateValue *imm = ref.get()->asImm();
210
211 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
212 }
213
214 void
215 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
216 {
217 switch (insn->rnd) {
218 case ROUND_M: code[1] |= 1 << 23; break;
219 case ROUND_P: code[1] |= 2 << 23; break;
220 case ROUND_Z: code[1] |= 3 << 23; break;
221 default:
222 assert(insn->rnd == ROUND_N);
223 break;
224 }
225 }
226
227 void
228 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
229 {
230 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
231 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
232 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
233 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
234 }
235
236 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
237 {
238 uint8_t val;
239
240 switch (cc) {
241 case CC_LT: val = 0x1; break;
242 case CC_LTU: val = 0x9; break;
243 case CC_EQ: val = 0x2; break;
244 case CC_EQU: val = 0xa; break;
245 case CC_LE: val = 0x3; break;
246 case CC_LEU: val = 0xb; break;
247 case CC_GT: val = 0x4; break;
248 case CC_GTU: val = 0xc; break;
249 case CC_NE: val = 0x5; break;
250 case CC_NEU: val = 0xd; break;
251 case CC_GE: val = 0x6; break;
252 case CC_GEU: val = 0xe; break;
253 case CC_TR: val = 0xf; break;
254 case CC_FL: val = 0x0; break;
255
256 case CC_A: val = 0x14; break;
257 case CC_NA: val = 0x13; break;
258 case CC_S: val = 0x15; break;
259 case CC_NS: val = 0x12; break;
260 case CC_C: val = 0x16; break;
261 case CC_NC: val = 0x11; break;
262 case CC_O: val = 0x17; break;
263 case CC_NO: val = 0x10; break;
264
265 default:
266 val = 0;
267 assert(!"invalid condition code");
268 break;
269 }
270 code[pos / 32] |= val << (pos % 32);
271 }
272
273 void
274 CodeEmitterNVC0::emitPredicate(const Instruction *i)
275 {
276 if (i->predSrc >= 0) {
277 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
278 srcId(i->src(i->predSrc), 10);
279 if (i->cc == CC_NOT_P)
280 code[0] |= 0x2000; // negate
281 } else {
282 code[0] |= 0x1c00;
283 }
284 }
285
286 void
287 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
288 {
289 switch (src.getFile()) {
290 case FILE_MEMORY_GLOBAL:
291 srcAddr32(src, 26, 0);
292 break;
293 case FILE_MEMORY_LOCAL:
294 case FILE_MEMORY_SHARED:
295 setAddress24(src);
296 break;
297 default:
298 assert(src.getFile() == FILE_MEMORY_CONST);
299 setAddress16(src);
300 break;
301 }
302 }
303
304 void
305 CodeEmitterNVC0::setAddress16(const ValueRef& src)
306 {
307 Symbol *sym = src.get()->asSym();
308
309 assert(sym);
310
311 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
312 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
313 }
314
315 void
316 CodeEmitterNVC0::setAddress24(const ValueRef& src)
317 {
318 Symbol *sym = src.get()->asSym();
319
320 assert(sym);
321
322 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
323 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
324 }
325
326 void
327 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
328 {
329 const ImmediateValue *imm = i->src(s).get()->asImm();
330 uint32_t u32;
331
332 assert(imm);
333 u32 = imm->reg.data.u32;
334
335 if ((code[0] & 0xf) == 0x1) {
336 // double immediate
337 uint64_t u64 = imm->reg.data.u64;
338 assert(!(u64 & 0x00000fffffffffffULL));
339 assert(!(code[1] & 0xc000));
340 code[0] |= ((u64 >> 44) & 0x3f) << 26;
341 code[1] |= 0xc000 | (u64 >> 50);
342 } else
343 if ((code[0] & 0xf) == 0x2) {
344 // LIMM
345 code[0] |= (u32 & 0x3f) << 26;
346 code[1] |= u32 >> 6;
347 } else
348 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
349 // integer immediate
350 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
351 assert(!(code[1] & 0xc000));
352 u32 &= 0xfffff;
353 code[0] |= (u32 & 0x3f) << 26;
354 code[1] |= 0xc000 | (u32 >> 6);
355 } else {
356 // float immediate
357 assert(!(u32 & 0x00000fff));
358 assert(!(code[1] & 0xc000));
359 code[0] |= ((u32 >> 12) & 0x3f) << 26;
360 code[1] |= 0xc000 | (u32 >> 18);
361 }
362 }
363
364 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
365 {
366 const ImmediateValue *imm = ref.get()->asImm();
367
368 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
369
370 assert(s8 == imm->reg.data.s32);
371
372 code[0] |= (s8 & 0x3f) << 26;
373 code[0] |= (s8 >> 6) << 8;
374 }
375
376 void
377 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
378 {
379 code[0] = opc;
380 code[1] = opc >> 32;
381
382 emitPredicate(i);
383
384 defId(i->def(0), 14);
385
386 int s1 = 26;
387 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
388 s1 = 49;
389
390 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
391 switch (i->getSrc(s)->reg.file) {
392 case FILE_MEMORY_CONST:
393 assert(!(code[1] & 0xc000));
394 code[1] |= (s == 2) ? 0x8000 : 0x4000;
395 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
396 setAddress16(i->src(s));
397 break;
398 case FILE_IMMEDIATE:
399 assert(s == 1 ||
400 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
401 assert(!(code[1] & 0xc000));
402 setImmediate(i, s);
403 break;
404 case FILE_GPR:
405 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
406 break;
407 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
408 break;
409 default:
410 if (i->op == OP_SELP) {
411 // OP_SELP is used to implement shared+atomics on Fermi.
412 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
413 srcId(i->src(s), 49);
414 }
415 // ignore here, can be predicate or flags, but must not be address
416 break;
417 }
418 }
419 }
420
421 void
422 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
423 {
424 code[0] = opc;
425 code[1] = opc >> 32;
426
427 emitPredicate(i);
428
429 defId(i->def(0), 14);
430
431 switch (i->src(0).getFile()) {
432 case FILE_MEMORY_CONST:
433 assert(!(code[1] & 0xc000));
434 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
435 setAddress16(i->src(0));
436 break;
437 case FILE_IMMEDIATE:
438 assert(!(code[1] & 0xc000));
439 setImmediate(i, 0);
440 break;
441 case FILE_GPR:
442 srcId(i->src(0), 26);
443 break;
444 default:
445 // ignore here, can be predicate or flags, but must not be address
446 break;
447 }
448 }
449
450 void
451 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
452 {
453 code[0] = opc;
454
455 int ss2a = 0;
456 if (opc == 0x0d || opc == 0x0e)
457 ss2a = 2;
458
459 defId(i->def(0), 14);
460 srcId(i->src(0), 20);
461
462 assert(pred || (i->predSrc < 0));
463 if (pred)
464 emitPredicate(i);
465
466 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
467 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
468 assert(!(code[0] & (0x300 >> ss2a)));
469 switch (i->src(s).get()->reg.fileIndex) {
470 case 0: code[0] |= 0x100 >> ss2a; break;
471 case 1: code[0] |= 0x200 >> ss2a; break;
472 case 16: code[0] |= 0x300 >> ss2a; break;
473 default:
474 ERROR("invalid c[] space for short form\n");
475 break;
476 }
477 if (s == 1)
478 code[0] |= i->getSrc(s)->reg.data.offset << 24;
479 else
480 code[0] |= i->getSrc(s)->reg.data.offset << 6;
481 } else
482 if (i->src(s).getFile() == FILE_IMMEDIATE) {
483 assert(s == 1);
484 setImmediateS8(i->src(s));
485 } else
486 if (i->src(s).getFile() == FILE_GPR) {
487 srcId(i->src(s), (s == 1) ? 26 : 8);
488 }
489 }
490 }
491
492 void
493 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
494 {
495 if (src.getFile() == FILE_MEMORY_CONST) {
496 switch (src.get()->reg.fileIndex) {
497 case 0: code[0] |= 0x100; break;
498 case 1: code[0] |= 0x200; break;
499 case 16: code[0] |= 0x300; break;
500 default:
501 assert(!"unsupported file index for short op");
502 break;
503 }
504 srcAddr32(src, 20, 2);
505 } else {
506 srcId(src, 20);
507 assert(src.getFile() == FILE_GPR);
508 }
509 }
510
511 void
512 CodeEmitterNVC0::emitNOP(const Instruction *i)
513 {
514 code[0] = 0x000001e4;
515 code[1] = 0x40000000;
516 emitPredicate(i);
517 }
518
519 void
520 CodeEmitterNVC0::emitFMAD(const Instruction *i)
521 {
522 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
523
524 if (i->encSize == 8) {
525 if (isLIMM(i->src(1), TYPE_F32)) {
526 emitForm_A(i, HEX64(20000000, 00000002));
527 } else {
528 emitForm_A(i, HEX64(30000000, 00000000));
529
530 if (i->src(2).mod.neg())
531 code[0] |= 1 << 8;
532 }
533 roundMode_A(i);
534
535 if (neg1)
536 code[0] |= 1 << 9;
537
538 if (i->saturate)
539 code[0] |= 1 << 5;
540
541 if (i->dnz)
542 code[0] |= 1 << 7;
543 else
544 if (i->ftz)
545 code[0] |= 1 << 6;
546 } else {
547 assert(!i->saturate && !i->src(2).mod.neg());
548 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
549 false);
550 if (neg1)
551 code[0] |= 1 << 4;
552 }
553 }
554
555 void
556 CodeEmitterNVC0::emitDMAD(const Instruction *i)
557 {
558 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
559
560 emitForm_A(i, HEX64(20000000, 00000001));
561
562 if (i->src(2).mod.neg())
563 code[0] |= 1 << 8;
564
565 roundMode_A(i);
566
567 if (neg1)
568 code[0] |= 1 << 9;
569
570 assert(!i->saturate);
571 assert(!i->ftz);
572 }
573
574 void
575 CodeEmitterNVC0::emitFMUL(const Instruction *i)
576 {
577 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
578
579 assert(i->postFactor >= -3 && i->postFactor <= 3);
580
581 if (i->encSize == 8) {
582 if (isLIMM(i->src(1), TYPE_F32)) {
583 assert(i->postFactor == 0); // constant folded, hopefully
584 emitForm_A(i, HEX64(30000000, 00000002));
585 } else {
586 emitForm_A(i, HEX64(58000000, 00000000));
587 roundMode_A(i);
588 code[1] |= ((i->postFactor > 0) ?
589 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
590 }
591 if (neg)
592 code[1] ^= 1 << 25; // aliases with LIMM sign bit
593
594 if (i->saturate)
595 code[0] |= 1 << 5;
596
597 if (i->dnz)
598 code[0] |= 1 << 7;
599 else
600 if (i->ftz)
601 code[0] |= 1 << 6;
602 } else {
603 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
604 emitForm_S(i, 0xa8, true);
605 }
606 }
607
608 void
609 CodeEmitterNVC0::emitDMUL(const Instruction *i)
610 {
611 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
612
613 emitForm_A(i, HEX64(50000000, 00000001));
614 roundMode_A(i);
615
616 if (neg)
617 code[0] |= 1 << 9;
618
619 assert(!i->saturate);
620 assert(!i->ftz);
621 assert(!i->dnz);
622 assert(!i->postFactor);
623 }
624
625 void
626 CodeEmitterNVC0::emitUMUL(const Instruction *i)
627 {
628 if (i->encSize == 8) {
629 if (i->src(1).getFile() == FILE_IMMEDIATE) {
630 emitForm_A(i, HEX64(10000000, 00000002));
631 } else {
632 emitForm_A(i, HEX64(50000000, 00000003));
633 }
634 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
635 code[0] |= 1 << 6;
636 if (i->sType == TYPE_S32)
637 code[0] |= 1 << 5;
638 if (i->dType == TYPE_S32)
639 code[0] |= 1 << 7;
640 } else {
641 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
642
643 if (i->sType == TYPE_S32)
644 code[0] |= 1 << 6;
645 }
646 }
647
648 void
649 CodeEmitterNVC0::emitFADD(const Instruction *i)
650 {
651 if (i->encSize == 8) {
652 if (isLIMM(i->src(1), TYPE_F32)) {
653 assert(!i->saturate);
654 emitForm_A(i, HEX64(28000000, 00000002));
655
656 code[0] |= i->src(0).mod.abs() << 7;
657 code[0] |= i->src(0).mod.neg() << 9;
658
659 if (i->src(1).mod.abs())
660 code[1] &= 0xfdffffff;
661 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
662 code[1] ^= 0x02000000;
663 } else {
664 emitForm_A(i, HEX64(50000000, 00000000));
665
666 roundMode_A(i);
667 if (i->saturate)
668 code[1] |= 1 << 17;
669
670 emitNegAbs12(i);
671 if (i->op == OP_SUB) code[0] ^= 1 << 8;
672 }
673 if (i->ftz)
674 code[0] |= 1 << 5;
675 } else {
676 assert(!i->saturate && i->op != OP_SUB &&
677 !i->src(0).mod.abs() &&
678 !i->src(1).mod.neg() && !i->src(1).mod.abs());
679
680 emitForm_S(i, 0x49, true);
681
682 if (i->src(0).mod.neg())
683 code[0] |= 1 << 7;
684 }
685 }
686
687 void
688 CodeEmitterNVC0::emitDADD(const Instruction *i)
689 {
690 assert(i->encSize == 8);
691 emitForm_A(i, HEX64(48000000, 00000001));
692 roundMode_A(i);
693 assert(!i->saturate);
694 assert(!i->ftz);
695 emitNegAbs12(i);
696 if (i->op == OP_SUB)
697 code[0] ^= 1 << 8;
698 }
699
700 void
701 CodeEmitterNVC0::emitUADD(const Instruction *i)
702 {
703 uint32_t addOp = 0;
704
705 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
706
707 if (i->src(0).mod.neg())
708 addOp |= 0x200;
709 if (i->src(1).mod.neg())
710 addOp |= 0x100;
711 if (i->op == OP_SUB)
712 addOp ^= 0x100;
713
714 assert(addOp != 0x300); // would be add-plus-one
715
716 if (i->encSize == 8) {
717 if (isLIMM(i->src(1), TYPE_U32)) {
718 emitForm_A(i, HEX64(08000000, 00000002));
719 if (i->defExists(1))
720 code[1] |= 1 << 26; // write carry
721 } else {
722 emitForm_A(i, HEX64(48000000, 00000003));
723 if (i->defExists(1))
724 code[1] |= 1 << 16; // write carry
725 }
726 code[0] |= addOp;
727
728 if (i->saturate)
729 code[0] |= 1 << 5;
730 if (i->flagsSrc >= 0) // add carry
731 code[0] |= 1 << 6;
732 } else {
733 assert(!(addOp & 0x100));
734 emitForm_S(i, (addOp >> 3) |
735 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
736 }
737 }
738
739 void
740 CodeEmitterNVC0::emitIMAD(const Instruction *i)
741 {
742 uint8_t addOp =
743 i->src(2).mod.neg() | ((i->src(0).mod.neg() ^ i->src(1).mod.neg()) << 1);
744
745 assert(i->encSize == 8);
746 emitForm_A(i, HEX64(20000000, 00000003));
747
748 assert(addOp != 3);
749 code[0] |= addOp << 8;
750
751 if (isSignedType(i->dType))
752 code[0] |= 1 << 7;
753 if (isSignedType(i->sType))
754 code[0] |= 1 << 5;
755
756 code[1] |= i->saturate << 24;
757
758 if (i->flagsDef >= 0) code[1] |= 1 << 16;
759 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
760
761 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
762 code[0] |= 1 << 6;
763 }
764
765 void
766 CodeEmitterNVC0::emitSHLADD(const Instruction *i)
767 {
768 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(2).mod.neg();
769 const ImmediateValue *imm = i->src(1).get()->asImm();
770 assert(imm);
771
772 code[0] = 0x00000003;
773 code[1] = 0x40000000 | addOp << 23;
774
775 emitPredicate(i);
776
777 defId(i->def(0), 14);
778 srcId(i->src(0), 20);
779
780 if (i->flagsDef >= 0)
781 code[1] |= 1 << 16;
782
783 assert(!(imm->reg.data.u32 & 0xffffffe0));
784 code[0] |= imm->reg.data.u32 << 5;
785
786 switch (i->src(2).getFile()) {
787 case FILE_GPR:
788 srcId(i->src(2), 26);
789 break;
790 case FILE_MEMORY_CONST:
791 code[1] |= 0x4000;
792 code[1] |= i->getSrc(2)->reg.fileIndex << 10;
793 setAddress16(i->src(2));
794 break;
795 case FILE_IMMEDIATE:
796 setImmediate(i, 2);
797 break;
798 default:
799 assert(!"bad src2 file");
800 break;
801 }
802 }
803
804 void
805 CodeEmitterNVC0::emitMADSP(const Instruction *i)
806 {
807 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
808
809 emitForm_A(i, HEX64(00000000, 00000003));
810
811 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
812 code[1] |= 0x01800000;
813 } else {
814 code[0] |= (i->subOp & 0x00f) << 7;
815 code[0] |= (i->subOp & 0x0f0) << 1;
816 code[0] |= (i->subOp & 0x100) >> 3;
817 code[0] |= (i->subOp & 0x200) >> 2;
818 code[1] |= (i->subOp & 0xc00) << 13;
819 }
820
821 if (i->flagsDef >= 0)
822 code[1] |= 1 << 16;
823 }
824
825 void
826 CodeEmitterNVC0::emitISAD(const Instruction *i)
827 {
828 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
829 assert(i->encSize == 8);
830
831 emitForm_A(i, HEX64(38000000, 00000003));
832
833 if (i->dType == TYPE_S32)
834 code[0] |= 1 << 5;
835 }
836
837 void
838 CodeEmitterNVC0::emitNOT(Instruction *i)
839 {
840 assert(i->encSize == 8);
841 i->setSrc(1, i->src(0));
842 emitForm_A(i, HEX64(68000000, 000001c3));
843 }
844
845 void
846 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
847 {
848 if (i->def(0).getFile() == FILE_PREDICATE) {
849 code[0] = 0x00000004 | (subOp << 30);
850 code[1] = 0x0c000000;
851
852 emitPredicate(i);
853
854 defId(i->def(0), 17);
855 srcId(i->src(0), 20);
856 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
857 srcId(i->src(1), 26);
858 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
859
860 if (i->defExists(1)) {
861 defId(i->def(1), 14);
862 } else {
863 code[0] |= 7 << 14;
864 }
865 // (a OP b) OP c
866 if (i->predSrc != 2 && i->srcExists(2)) {
867 code[1] |= subOp << 21;
868 srcId(i->src(2), 49);
869 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 20;
870 } else {
871 code[1] |= 0x000e0000;
872 }
873 } else
874 if (i->encSize == 8) {
875 if (isLIMM(i->src(1), TYPE_U32)) {
876 emitForm_A(i, HEX64(38000000, 00000002));
877
878 if (i->flagsDef >= 0)
879 code[1] |= 1 << 26;
880 } else {
881 emitForm_A(i, HEX64(68000000, 00000003));
882
883 if (i->flagsDef >= 0)
884 code[1] |= 1 << 16;
885 }
886 code[0] |= subOp << 6;
887
888 if (i->flagsSrc >= 0) // carry
889 code[0] |= 1 << 5;
890
891 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
892 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
893 } else {
894 emitForm_S(i, (subOp << 5) |
895 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
896 }
897 }
898
899 void
900 CodeEmitterNVC0::emitPOPC(const Instruction *i)
901 {
902 emitForm_A(i, HEX64(54000000, 00000004));
903
904 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
905 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
906 }
907
908 void
909 CodeEmitterNVC0::emitINSBF(const Instruction *i)
910 {
911 emitForm_A(i, HEX64(28000000, 00000003));
912 }
913
914 void
915 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
916 {
917 emitForm_A(i, HEX64(70000000, 00000003));
918
919 if (i->dType == TYPE_S32)
920 code[0] |= 1 << 5;
921 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
922 code[0] |= 1 << 8;
923 }
924
925 void
926 CodeEmitterNVC0::emitBFIND(const Instruction *i)
927 {
928 emitForm_B(i, HEX64(78000000, 00000003));
929
930 if (i->dType == TYPE_S32)
931 code[0] |= 1 << 5;
932 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
933 code[0] |= 1 << 8;
934 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
935 code[0] |= 1 << 6;
936 }
937
938 void
939 CodeEmitterNVC0::emitPERMT(const Instruction *i)
940 {
941 emitForm_A(i, HEX64(24000000, 00000004));
942
943 code[0] |= i->subOp << 5;
944 }
945
946 void
947 CodeEmitterNVC0::emitShift(const Instruction *i)
948 {
949 if (i->op == OP_SHR) {
950 emitForm_A(i, HEX64(58000000, 00000003)
951 | (isSignedType(i->dType) ? 0x20 : 0x00));
952 } else {
953 emitForm_A(i, HEX64(60000000, 00000003));
954 }
955
956 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
957 code[0] |= 1 << 9;
958 }
959
960 void
961 CodeEmitterNVC0::emitPreOp(const Instruction *i)
962 {
963 if (i->encSize == 8) {
964 emitForm_B(i, HEX64(60000000, 00000000));
965
966 if (i->op == OP_PREEX2)
967 code[0] |= 0x20;
968
969 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
970 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
971 } else {
972 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
973 }
974 }
975
976 void
977 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
978 {
979 if (i->encSize == 8) {
980 code[0] = 0x00000000 | (subOp << 26);
981 code[1] = 0xc8000000;
982
983 emitPredicate(i);
984
985 defId(i->def(0), 14);
986 srcId(i->src(0), 20);
987
988 assert(i->src(0).getFile() == FILE_GPR);
989
990 if (i->saturate) code[0] |= 1 << 5;
991
992 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
993 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
994 } else {
995 emitForm_S(i, 0x80000008 | (subOp << 26), true);
996
997 assert(!i->src(0).mod.neg());
998 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
999 }
1000 }
1001
1002 void
1003 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
1004 {
1005 uint64_t op;
1006
1007 assert(i->encSize == 8);
1008
1009 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
1010
1011 if (i->ftz)
1012 op |= 1 << 5;
1013 else
1014 if (!isFloatType(i->dType)) {
1015 op |= isSignedType(i->dType) ? 0x23 : 0x03;
1016 op |= i->subOp << 6;
1017 }
1018 if (i->dType == TYPE_F64)
1019 op |= 0x01;
1020
1021 emitForm_A(i, op);
1022 emitNegAbs12(i);
1023
1024 if (i->flagsDef >= 0)
1025 code[1] |= 1 << 16;
1026 }
1027
1028 void
1029 CodeEmitterNVC0::roundMode_C(const Instruction *i)
1030 {
1031 switch (i->rnd) {
1032 case ROUND_M: code[1] |= 1 << 17; break;
1033 case ROUND_P: code[1] |= 2 << 17; break;
1034 case ROUND_Z: code[1] |= 3 << 17; break;
1035 case ROUND_NI: code[0] |= 1 << 7; break;
1036 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
1037 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
1038 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
1039 case ROUND_N: break;
1040 default:
1041 assert(!"invalid round mode");
1042 break;
1043 }
1044 }
1045
1046 void
1047 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
1048 {
1049 switch (i->rnd) {
1050 case ROUND_M:
1051 case ROUND_MI: code[0] |= 1 << 16; break;
1052 case ROUND_P:
1053 case ROUND_PI: code[0] |= 2 << 16; break;
1054 case ROUND_Z:
1055 case ROUND_ZI: code[0] |= 3 << 16; break;
1056 default:
1057 break;
1058 }
1059 }
1060
1061 void
1062 CodeEmitterNVC0::emitCVT(Instruction *i)
1063 {
1064 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1065 DataType dType;
1066
1067 switch (i->op) {
1068 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1069 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1070 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1071 default:
1072 break;
1073 }
1074
1075 const bool sat = (i->op == OP_SAT) || i->saturate;
1076 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1077 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1078
1079 if (i->op == OP_NEG && i->dType == TYPE_U32)
1080 dType = TYPE_S32;
1081 else
1082 dType = i->dType;
1083
1084 if (i->encSize == 8) {
1085 emitForm_B(i, HEX64(10000000, 00000004));
1086
1087 roundMode_C(i);
1088
1089 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1090 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1091 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1092
1093 // for 8/16 source types, the byte/word is in subOp. word 1 is
1094 // represented as 2.
1095 if (!isFloatType(i->sType))
1096 code[1] |= i->subOp << 0x17;
1097 else
1098 code[1] |= i->subOp << 0x18;
1099
1100 if (sat)
1101 code[0] |= 0x20;
1102 if (abs)
1103 code[0] |= 1 << 6;
1104 if (neg && i->op != OP_ABS)
1105 code[0] |= 1 << 8;
1106
1107 if (i->ftz)
1108 code[1] |= 1 << 23;
1109
1110 if (isSignedIntType(dType))
1111 code[0] |= 0x080;
1112 if (isSignedIntType(i->sType))
1113 code[0] |= 0x200;
1114
1115 if (isFloatType(dType)) {
1116 if (!isFloatType(i->sType))
1117 code[1] |= 0x08000000;
1118 } else {
1119 if (isFloatType(i->sType))
1120 code[1] |= 0x04000000;
1121 else
1122 code[1] |= 0x0c000000;
1123 }
1124 } else {
1125 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1126 code[0] = 0x298;
1127 } else
1128 if (isFloatType(dType)) {
1129 if (isFloatType(i->sType))
1130 code[0] = 0x098;
1131 else
1132 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1133 } else {
1134 assert(isFloatType(i->sType));
1135
1136 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1137 }
1138
1139 if (neg) code[0] |= 1 << 16;
1140 if (sat) code[0] |= 1 << 18;
1141 if (abs) code[0] |= 1 << 19;
1142
1143 roundMode_CS(i);
1144 }
1145 }
1146
1147 void
1148 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1149 {
1150 uint32_t hi;
1151 uint32_t lo = 0;
1152
1153 if (i->sType == TYPE_F64)
1154 lo = 0x1;
1155 else
1156 if (!isFloatType(i->sType))
1157 lo = 0x3;
1158
1159 if (isSignedIntType(i->sType))
1160 lo |= 0x20;
1161 if (isFloatType(i->dType)) {
1162 if (isFloatType(i->sType))
1163 lo |= 0x20;
1164 else
1165 lo |= 0x80;
1166 }
1167
1168 switch (i->op) {
1169 case OP_SET_AND: hi = 0x10000000; break;
1170 case OP_SET_OR: hi = 0x10200000; break;
1171 case OP_SET_XOR: hi = 0x10400000; break;
1172 default:
1173 hi = 0x100e0000;
1174 break;
1175 }
1176 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1177
1178 if (i->op != OP_SET)
1179 srcId(i->src(2), 32 + 17);
1180
1181 if (i->def(0).getFile() == FILE_PREDICATE) {
1182 if (i->sType == TYPE_F32)
1183 code[1] += 0x10000000;
1184 else
1185 code[1] += 0x08000000;
1186
1187 code[0] &= ~0xfc000;
1188 defId(i->def(0), 17);
1189 if (i->defExists(1))
1190 defId(i->def(1), 14);
1191 else
1192 code[0] |= 0x1c000;
1193 }
1194
1195 if (i->ftz)
1196 code[1] |= 1 << 27;
1197 if (i->flagsSrc >= 0)
1198 code[0] |= 1 << 6;
1199
1200 emitCondCode(i->setCond, 32 + 23);
1201 emitNegAbs12(i);
1202 }
1203
1204 void
1205 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1206 {
1207 uint64_t op;
1208
1209 switch (i->dType) {
1210 case TYPE_S32:
1211 op = HEX64(30000000, 00000023);
1212 break;
1213 case TYPE_U32:
1214 op = HEX64(30000000, 00000003);
1215 break;
1216 case TYPE_F32:
1217 op = HEX64(38000000, 00000000);
1218 break;
1219 default:
1220 assert(!"invalid type for SLCT");
1221 op = 0;
1222 break;
1223 }
1224 emitForm_A(i, op);
1225
1226 CondCode cc = i->setCond;
1227
1228 if (i->src(2).mod.neg())
1229 cc = reverseCondCode(cc);
1230
1231 emitCondCode(cc, 32 + 23);
1232
1233 if (i->ftz)
1234 code[0] |= 1 << 5;
1235 }
1236
1237 static void
1238 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1239 {
1240 int loc = entry->loc;
1241 if (data.force_persample_interp)
1242 code[loc + 1] |= 1 << 20;
1243 else
1244 code[loc + 1] &= ~(1 << 20);
1245 }
1246
1247 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1248 {
1249 emitForm_A(i, HEX64(20000000, 00000004));
1250
1251 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1252 code[1] |= 1 << 20;
1253
1254 if (i->subOp == 1) {
1255 addInterp(0, 0, selpFlip);
1256 }
1257 }
1258
1259 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1260 {
1261 code[0] = 0x00000006 | (i->subOp << 26);
1262 code[1] = 0xf0000000;
1263 emitPredicate(i);
1264 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1265 }
1266
1267 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1268 {
1269 code[0] = 0x00000086;
1270 code[1] = 0xd0000000;
1271
1272 code[1] |= i->tex.r;
1273 code[1] |= i->tex.s << 8;
1274
1275 if (i->tex.liveOnly)
1276 code[0] |= 1 << 9;
1277
1278 defId(i->def(0), 14);
1279 srcId(i->src(0), 20);
1280 }
1281
1282 static inline bool
1283 isNextIndependentTex(const TexInstruction *i)
1284 {
1285 if (!i->next || !isTextureOp(i->next->op))
1286 return false;
1287 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1288 return false;
1289 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1290 }
1291
1292 void
1293 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1294 {
1295 code[0] = 0x00000006;
1296
1297 if (isNextIndependentTex(i))
1298 code[0] |= 0x080; // t mode
1299 else
1300 code[0] |= 0x100; // p mode
1301
1302 if (i->tex.liveOnly)
1303 code[0] |= 1 << 9;
1304
1305 switch (i->op) {
1306 case OP_TEX: code[1] = 0x80000000; break;
1307 case OP_TXB: code[1] = 0x84000000; break;
1308 case OP_TXL: code[1] = 0x86000000; break;
1309 case OP_TXF: code[1] = 0x90000000; break;
1310 case OP_TXG: code[1] = 0xa0000000; break;
1311 case OP_TXLQ: code[1] = 0xb0000000; break;
1312 case OP_TXD: code[1] = 0xe0000000; break;
1313 default:
1314 assert(!"invalid texture op");
1315 break;
1316 }
1317 if (i->op == OP_TXF) {
1318 if (!i->tex.levelZero)
1319 code[1] |= 0x02000000;
1320 } else
1321 if (i->tex.levelZero) {
1322 code[1] |= 0x02000000;
1323 }
1324
1325 if (i->op != OP_TXD && i->tex.derivAll)
1326 code[1] |= 1 << 13;
1327
1328 defId(i->def(0), 14);
1329 srcId(i->src(0), 20);
1330
1331 emitPredicate(i);
1332
1333 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1334
1335 code[1] |= i->tex.mask << 14;
1336
1337 code[1] |= i->tex.r;
1338 code[1] |= i->tex.s << 8;
1339 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1340 code[1] |= 1 << 18; // in 1st source (with array index)
1341
1342 // texture target:
1343 code[1] |= (i->tex.target.getDim() - 1) << 20;
1344 if (i->tex.target.isCube())
1345 code[1] += 2 << 20;
1346 if (i->tex.target.isArray())
1347 code[1] |= 1 << 19;
1348 if (i->tex.target.isShadow())
1349 code[1] |= 1 << 24;
1350
1351 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1352
1353 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1354 // lzero
1355 if (i->op == OP_TXL)
1356 code[1] &= ~(1 << 26);
1357 else
1358 if (i->op == OP_TXF)
1359 code[1] &= ~(1 << 25);
1360 }
1361 if (i->tex.target == TEX_TARGET_2D_MS ||
1362 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1363 code[1] |= 1 << 23;
1364
1365 if (i->tex.useOffsets == 1)
1366 code[1] |= 1 << 22;
1367 if (i->tex.useOffsets == 4)
1368 code[1] |= 1 << 23;
1369
1370 srcId(i, src1, 26);
1371 }
1372
1373 void
1374 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1375 {
1376 code[0] = 0x00000086;
1377 code[1] = 0xc0000000;
1378
1379 switch (i->tex.query) {
1380 case TXQ_DIMS: code[1] |= 0 << 22; break;
1381 case TXQ_TYPE: code[1] |= 1 << 22; break;
1382 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1383 case TXQ_FILTER: code[1] |= 3 << 22; break;
1384 case TXQ_LOD: code[1] |= 4 << 22; break;
1385 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1386 default:
1387 assert(!"invalid texture query");
1388 break;
1389 }
1390
1391 code[1] |= i->tex.mask << 14;
1392
1393 code[1] |= i->tex.r;
1394 code[1] |= i->tex.s << 8;
1395 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1396 code[1] |= 1 << 18;
1397
1398 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1399
1400 defId(i->def(0), 14);
1401 srcId(i->src(0), 20);
1402 srcId(i, src1, 26);
1403
1404 emitPredicate(i);
1405 }
1406
1407 void
1408 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1409 {
1410 code[0] = 0x00000200 | (laneMask << 6); // dall
1411 code[1] = 0x48000000 | qOp;
1412
1413 defId(i->def(0), 14);
1414 srcId(i->src(0), 20);
1415 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1416
1417 emitPredicate(i);
1418 }
1419
1420 void
1421 CodeEmitterNVC0::emitFlow(const Instruction *i)
1422 {
1423 const FlowInstruction *f = i->asFlow();
1424
1425 unsigned mask; // bit 0: predicate, bit 1: target
1426
1427 code[0] = 0x00000007;
1428
1429 switch (i->op) {
1430 case OP_BRA:
1431 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1432 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1433 code[0] |= 0x4000;
1434 mask = 3;
1435 break;
1436 case OP_CALL:
1437 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1438 if (f->indirect)
1439 code[0] |= 0x4000; // indirect calls always use c[] source
1440 mask = 2;
1441 break;
1442
1443 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1444 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1445 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1446 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1447 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1448
1449 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1450 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1451 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1452 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1453
1454 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1455 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1456 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1457 default:
1458 assert(!"invalid flow operation");
1459 return;
1460 }
1461
1462 if (mask & 1) {
1463 emitPredicate(i);
1464 if (i->flagsSrc < 0)
1465 code[0] |= 0x1e0;
1466 }
1467
1468 if (!f)
1469 return;
1470
1471 if (f->allWarp)
1472 code[0] |= 1 << 15;
1473 if (f->limit)
1474 code[0] |= 1 << 16;
1475
1476 if (f->indirect) {
1477 if (code[0] & 0x4000) {
1478 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1479 setAddress16(i->src(0));
1480 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1481 if (f->op == OP_BRA)
1482 srcId(f->src(0).getIndirect(0), 20);
1483 } else {
1484 srcId(f, 0, 20);
1485 }
1486 }
1487
1488 if (f->op == OP_CALL) {
1489 if (f->indirect) {
1490 // nothing
1491 } else
1492 if (f->builtin) {
1493 assert(f->absolute);
1494 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1495 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1496 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1497 } else {
1498 assert(!f->absolute);
1499 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1500 code[0] |= (pcRel & 0x3f) << 26;
1501 code[1] |= (pcRel >> 6) & 0x3ffff;
1502 }
1503 } else
1504 if (mask & 2) {
1505 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1506 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1507 pcRel += 8;
1508 // currently we don't want absolute branches
1509 assert(!f->absolute);
1510 code[0] |= (pcRel & 0x3f) << 26;
1511 code[1] |= (pcRel >> 6) & 0x3ffff;
1512 }
1513 }
1514
1515 void
1516 CodeEmitterNVC0::emitBAR(const Instruction *i)
1517 {
1518 Value *rDef = NULL, *pDef = NULL;
1519
1520 switch (i->subOp) {
1521 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1522 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1523 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1524 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1525 default:
1526 code[0] = 0x04;
1527 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1528 break;
1529 }
1530 code[1] = 0x50000000;
1531
1532 code[0] |= 63 << 14;
1533 code[1] |= 7 << 21;
1534
1535 emitPredicate(i);
1536
1537 // barrier id
1538 if (i->src(0).getFile() == FILE_GPR) {
1539 srcId(i->src(0), 20);
1540 } else {
1541 ImmediateValue *imm = i->getSrc(0)->asImm();
1542 assert(imm);
1543 code[0] |= imm->reg.data.u32 << 20;
1544 code[1] |= 0x8000;
1545 }
1546
1547 // thread count
1548 if (i->src(1).getFile() == FILE_GPR) {
1549 srcId(i->src(1), 26);
1550 } else {
1551 ImmediateValue *imm = i->getSrc(1)->asImm();
1552 assert(imm);
1553 assert(imm->reg.data.u32 <= 0xfff);
1554 code[0] |= imm->reg.data.u32 << 26;
1555 code[1] |= imm->reg.data.u32 >> 6;
1556 code[1] |= 0x4000;
1557 }
1558
1559 if (i->srcExists(2) && (i->predSrc != 2)) {
1560 srcId(i->src(2), 32 + 17);
1561 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1562 code[1] |= 1 << 20;
1563 } else {
1564 code[1] |= 7 << 17;
1565 }
1566
1567 if (i->defExists(0)) {
1568 if (i->def(0).getFile() == FILE_GPR)
1569 rDef = i->getDef(0);
1570 else
1571 pDef = i->getDef(0);
1572
1573 if (i->defExists(1)) {
1574 if (i->def(1).getFile() == FILE_GPR)
1575 rDef = i->getDef(1);
1576 else
1577 pDef = i->getDef(1);
1578 }
1579 }
1580 if (rDef) {
1581 code[0] &= ~(63 << 14);
1582 defId(rDef, 14);
1583 }
1584 if (pDef) {
1585 code[1] &= ~(7 << 21);
1586 defId(pDef, 32 + 21);
1587 }
1588 }
1589
1590 void
1591 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1592 {
1593 code[0] = 0x00000006;
1594 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1595
1596 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1597 code[0] |= 0x200;
1598
1599 emitPredicate(i);
1600
1601 defId(i->def(0), 14);
1602 srcId(i->src(0).getIndirect(0), 20);
1603 }
1604
1605 void
1606 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1607 {
1608 uint32_t prim = i->src(0).get()->reg.data.u32;
1609
1610 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1611 code[1] = 0x00000000 | (prim >> 6);
1612
1613 emitPredicate(i);
1614
1615 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1616
1617 defId(i->def(0), 14);
1618 srcId(i, src1, 20);
1619 }
1620
1621 void
1622 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1623 {
1624 code[0] = 0x00000006;
1625 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1626
1627 if (i->perPatch)
1628 code[0] |= 0x100;
1629 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1630 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1631
1632 emitPredicate(i);
1633
1634 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1635
1636 defId(i->def(0), 14);
1637 srcId(i->src(0).getIndirect(0), 20);
1638 srcId(i->src(0).getIndirect(1), 26); // vertex address
1639 }
1640
1641 void
1642 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1643 {
1644 unsigned int size = typeSizeof(i->dType);
1645
1646 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1647 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1648
1649 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1650
1651 if (i->perPatch)
1652 code[0] |= 0x100;
1653
1654 emitPredicate(i);
1655
1656 assert(i->src(1).getFile() == FILE_GPR);
1657
1658 srcId(i->src(0).getIndirect(0), 20);
1659 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1660 srcId(i->src(1), 26);
1661 }
1662
1663 void
1664 CodeEmitterNVC0::emitOUT(const Instruction *i)
1665 {
1666 code[0] = 0x00000006;
1667 code[1] = 0x1c000000;
1668
1669 emitPredicate(i);
1670
1671 defId(i->def(0), 14); // new secret address
1672 srcId(i->src(0), 20); // old secret address, should be 0 initially
1673
1674 assert(i->src(0).getFile() == FILE_GPR);
1675
1676 if (i->op == OP_EMIT)
1677 code[0] |= 1 << 5;
1678 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1679 code[0] |= 1 << 6;
1680
1681 // vertex stream
1682 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1683 unsigned int stream = SDATA(i->src(1)).u32;
1684 assert(stream < 4);
1685 if (stream) {
1686 code[1] |= 0xc000;
1687 code[0] |= stream << 26;
1688 } else {
1689 srcId(NULL, 26);
1690 }
1691 } else {
1692 srcId(i->src(1), 26);
1693 }
1694 }
1695
1696 void
1697 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1698 {
1699 if (i->encSize == 8) {
1700 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1701 } else {
1702 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1703 code[0] |= 0x80;
1704 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1705 }
1706 }
1707
1708 static void
1709 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1710 {
1711 int ipa = entry->ipa;
1712 int reg = entry->reg;
1713 int loc = entry->loc;
1714
1715 if (data.flatshade &&
1716 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1717 ipa = NV50_IR_INTERP_FLAT;
1718 reg = 0x3f;
1719 } else if (data.force_persample_interp &&
1720 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1721 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1722 ipa |= NV50_IR_INTERP_CENTROID;
1723 }
1724 code[loc + 0] &= ~(0xf << 6);
1725 code[loc + 0] |= ipa << 6;
1726 code[loc + 0] &= ~(0x3f << 26);
1727 code[loc + 0] |= reg << 26;
1728 }
1729
1730 void
1731 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1732 {
1733 const uint32_t base = i->getSrc(0)->reg.data.offset;
1734
1735 if (i->encSize == 8) {
1736 code[0] = 0x00000000;
1737 code[1] = 0xc0000000 | (base & 0xffff);
1738
1739 if (i->saturate)
1740 code[0] |= 1 << 5;
1741
1742 if (i->op == OP_PINTERP) {
1743 srcId(i->src(1), 26);
1744 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1745 } else {
1746 code[0] |= 0x3f << 26;
1747 addInterp(i->ipa, 0x3f, interpApply);
1748 }
1749
1750 srcId(i->src(0).getIndirect(0), 20);
1751 } else {
1752 assert(i->op == OP_PINTERP);
1753 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1754 srcId(i->src(1), 20);
1755 }
1756 emitInterpMode(i);
1757
1758 emitPredicate(i);
1759 defId(i->def(0), 14);
1760
1761 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1762 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1763 else
1764 code[1] |= 0x3f << 17;
1765 }
1766
1767 void
1768 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1769 {
1770 uint8_t val;
1771
1772 switch (ty) {
1773 case TYPE_U8:
1774 val = 0x00;
1775 break;
1776 case TYPE_S8:
1777 val = 0x20;
1778 break;
1779 case TYPE_F16:
1780 case TYPE_U16:
1781 val = 0x40;
1782 break;
1783 case TYPE_S16:
1784 val = 0x60;
1785 break;
1786 case TYPE_F32:
1787 case TYPE_U32:
1788 case TYPE_S32:
1789 val = 0x80;
1790 break;
1791 case TYPE_F64:
1792 case TYPE_U64:
1793 case TYPE_S64:
1794 val = 0xa0;
1795 break;
1796 case TYPE_B128:
1797 val = 0xc0;
1798 break;
1799 default:
1800 val = 0x80;
1801 assert(!"invalid type");
1802 break;
1803 }
1804 code[0] |= val;
1805 }
1806
1807 void
1808 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1809 {
1810 uint32_t val;
1811
1812 switch (c) {
1813 case CACHE_CA:
1814 // case CACHE_WB:
1815 val = 0x000;
1816 break;
1817 case CACHE_CG:
1818 val = 0x100;
1819 break;
1820 case CACHE_CS:
1821 val = 0x200;
1822 break;
1823 case CACHE_CV:
1824 // case CACHE_WT:
1825 val = 0x300;
1826 break;
1827 default:
1828 val = 0;
1829 assert(!"invalid caching mode");
1830 break;
1831 }
1832 code[0] |= val;
1833 }
1834
1835 static inline bool
1836 uses64bitAddress(const Instruction *ldst)
1837 {
1838 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1839 ldst->src(0).isIndirect(0) &&
1840 ldst->getIndirect(0, 0)->reg.size == 8;
1841 }
1842
1843 void
1844 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1845 {
1846 uint32_t opc;
1847
1848 switch (i->src(0).getFile()) {
1849 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1850 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1851 case FILE_MEMORY_SHARED:
1852 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1853 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1854 opc = 0xb8000000;
1855 else
1856 opc = 0xcc000000;
1857 } else {
1858 opc = 0xc9000000;
1859 }
1860 break;
1861 default:
1862 assert(!"invalid memory file");
1863 opc = 0;
1864 break;
1865 }
1866 code[0] = 0x00000005;
1867 code[1] = opc;
1868
1869 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1870 // Unlocked store on shared memory can fail.
1871 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1872 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1873 assert(i->defExists(0));
1874 defId(i->def(0), 8);
1875 }
1876 }
1877
1878 setAddressByFile(i->src(0));
1879 srcId(i->src(1), 14);
1880 srcId(i->src(0).getIndirect(0), 20);
1881 if (uses64bitAddress(i))
1882 code[1] |= 1 << 26;
1883
1884 emitPredicate(i);
1885
1886 emitLoadStoreType(i->dType);
1887 emitCachingMode(i->cache);
1888 }
1889
1890 void
1891 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1892 {
1893 uint32_t opc;
1894
1895 code[0] = 0x00000005;
1896
1897 switch (i->src(0).getFile()) {
1898 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1899 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1900 case FILE_MEMORY_SHARED:
1901 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1902 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1903 opc = 0xa8000000;
1904 else
1905 opc = 0xc4000000;
1906 } else {
1907 opc = 0xc1000000;
1908 }
1909 break;
1910 case FILE_MEMORY_CONST:
1911 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1912 emitMOV(i); // not sure if this is any better
1913 return;
1914 }
1915 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1916 code[0] = 0x00000006 | (i->subOp << 8);
1917 break;
1918 default:
1919 assert(!"invalid memory file");
1920 opc = 0;
1921 break;
1922 }
1923 code[1] = opc;
1924
1925 int r = 0, p = -1;
1926 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1927 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1928 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1929 r = -1;
1930 p = 0;
1931 } else if (i->defExists(1)) { // r, p
1932 p = 1;
1933 } else {
1934 assert(!"Expected predicate dest for load locked");
1935 }
1936 }
1937 }
1938
1939 if (r >= 0)
1940 defId(i->def(r), 14);
1941 else
1942 code[0] |= 63 << 14;
1943
1944 if (p >= 0) {
1945 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1946 defId(i->def(p), 8);
1947 else
1948 defId(i->def(p), 32 + 18);
1949 }
1950
1951 setAddressByFile(i->src(0));
1952 srcId(i->src(0).getIndirect(0), 20);
1953 if (uses64bitAddress(i))
1954 code[1] |= 1 << 26;
1955
1956 emitPredicate(i);
1957
1958 emitLoadStoreType(i->dType);
1959 emitCachingMode(i->cache);
1960 }
1961
1962 uint8_t
1963 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1964 {
1965 switch (SDATA(ref).sv.sv) {
1966 case SV_LANEID: return 0x00;
1967 case SV_PHYSID: return 0x03;
1968 case SV_VERTEX_COUNT: return 0x10;
1969 case SV_INVOCATION_ID: return 0x11;
1970 case SV_YDIR: return 0x12;
1971 case SV_THREAD_KILL: return 0x13;
1972 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1973 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1974 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1975 case SV_GRIDID: return 0x2c;
1976 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1977 case SV_LBASE: return 0x34;
1978 case SV_SBASE: return 0x30;
1979 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1980 default:
1981 assert(!"no sreg for system value");
1982 return 0;
1983 }
1984 }
1985
1986 void
1987 CodeEmitterNVC0::emitMOV(const Instruction *i)
1988 {
1989 if (i->def(0).getFile() == FILE_PREDICATE) {
1990 if (i->src(0).getFile() == FILE_GPR) {
1991 code[0] = 0xfc01c003;
1992 code[1] = 0x1a8e0000;
1993 srcId(i->src(0), 20);
1994 } else {
1995 code[0] = 0x0001c004;
1996 code[1] = 0x0c0e0000;
1997 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1998 code[0] |= 7 << 20;
1999 if (!i->getSrc(0)->reg.data.u32)
2000 code[0] |= 1 << 23;
2001 } else {
2002 srcId(i->src(0), 20);
2003 }
2004 }
2005 defId(i->def(0), 17);
2006 emitPredicate(i);
2007 } else
2008 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
2009 uint8_t sr = getSRegEncoding(i->src(0));
2010
2011 if (i->encSize == 8) {
2012 code[0] = 0x00000004 | (sr << 26);
2013 code[1] = 0x2c000000;
2014 } else {
2015 code[0] = 0x40000008 | (sr << 20);
2016 }
2017 defId(i->def(0), 14);
2018
2019 emitPredicate(i);
2020 } else
2021 if (i->encSize == 8) {
2022 uint64_t opc;
2023
2024 if (i->src(0).getFile() == FILE_IMMEDIATE)
2025 opc = HEX64(18000000, 000001e2);
2026 else
2027 if (i->src(0).getFile() == FILE_PREDICATE)
2028 opc = HEX64(080e0000, 1c000004);
2029 else
2030 opc = HEX64(28000000, 00000004);
2031
2032 if (i->src(0).getFile() != FILE_PREDICATE)
2033 opc |= i->lanes << 5;
2034
2035 emitForm_B(i, opc);
2036
2037 // Explicitly emit the predicate source as emitForm_B skips it.
2038 if (i->src(0).getFile() == FILE_PREDICATE)
2039 srcId(i->src(0), 20);
2040 } else {
2041 uint32_t imm;
2042
2043 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2044 imm = SDATA(i->src(0)).u32;
2045 if (imm & 0xfff00000) {
2046 assert(!(imm & 0x000fffff));
2047 code[0] = 0x00000318 | imm;
2048 } else {
2049 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
2050 code[0] = 0x00000118 | (imm << 20);
2051 }
2052 } else {
2053 code[0] = 0x0028;
2054 emitShortSrc2(i->src(0));
2055 }
2056 defId(i->def(0), 14);
2057
2058 emitPredicate(i);
2059 }
2060 }
2061
2062 void
2063 CodeEmitterNVC0::emitATOM(const Instruction *i)
2064 {
2065 const bool hasDst = i->defExists(0);
2066 const bool casOrExch =
2067 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
2068 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
2069
2070 if (i->dType == TYPE_U64) {
2071 switch (i->subOp) {
2072 case NV50_IR_SUBOP_ATOM_ADD:
2073 code[0] = 0x205;
2074 if (hasDst)
2075 code[1] = 0x507e0000;
2076 else
2077 code[1] = 0x10000000;
2078 break;
2079 case NV50_IR_SUBOP_ATOM_EXCH:
2080 code[0] = 0x305;
2081 code[1] = 0x507e0000;
2082 break;
2083 case NV50_IR_SUBOP_ATOM_CAS:
2084 code[0] = 0x325;
2085 code[1] = 0x50000000;
2086 break;
2087 default:
2088 assert(!"invalid u64 red op");
2089 break;
2090 }
2091 } else
2092 if (i->dType == TYPE_U32) {
2093 switch (i->subOp) {
2094 case NV50_IR_SUBOP_ATOM_EXCH:
2095 code[0] = 0x105;
2096 code[1] = 0x507e0000;
2097 break;
2098 case NV50_IR_SUBOP_ATOM_CAS:
2099 code[0] = 0x125;
2100 code[1] = 0x50000000;
2101 break;
2102 default:
2103 code[0] = 0x5 | (i->subOp << 5);
2104 if (hasDst)
2105 code[1] = 0x507e0000;
2106 else
2107 code[1] = 0x10000000;
2108 break;
2109 }
2110 } else
2111 if (i->dType == TYPE_S32) {
2112 assert(i->subOp <= 2);
2113 code[0] = 0x205 | (i->subOp << 5);
2114 if (hasDst)
2115 code[1] = 0x587e0000;
2116 else
2117 code[1] = 0x18000000;
2118 } else
2119 if (i->dType == TYPE_F32) {
2120 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2121 code[0] = 0x205;
2122 if (hasDst)
2123 code[1] = 0x687e0000;
2124 else
2125 code[1] = 0x28000000;
2126 }
2127
2128 emitPredicate(i);
2129
2130 srcId(i->src(1), 14);
2131
2132 if (hasDst)
2133 defId(i->def(0), 32 + 11);
2134 else
2135 if (casOrExch)
2136 code[1] |= 63 << 11;
2137
2138 if (hasDst || casOrExch) {
2139 const int32_t offset = SDATA(i->src(0)).offset;
2140 assert(offset < 0x80000 && offset >= -0x80000);
2141 code[0] |= offset << 26;
2142 code[1] |= (offset & 0x1ffc0) >> 6;
2143 code[1] |= (offset & 0xe0000) << 6;
2144 } else {
2145 srcAddr32(i->src(0), 26, 0);
2146 }
2147 if (i->getIndirect(0, 0)) {
2148 srcId(i->getIndirect(0, 0), 20);
2149 if (i->getIndirect(0, 0)->reg.size == 8)
2150 code[1] |= 1 << 26;
2151 } else {
2152 code[0] |= 63 << 20;
2153 }
2154
2155 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2156 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2157 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2158 }
2159 }
2160
2161 void
2162 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2163 {
2164 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2165 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2166 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2167 default:
2168 code[0] = 0x45;
2169 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2170 break;
2171 }
2172 code[1] = 0xe0000000;
2173
2174 emitPredicate(i);
2175 }
2176
2177 void
2178 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2179 {
2180 code[0] = 0x00000005 | (i->subOp << 5);
2181
2182 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2183 code[1] = 0x98000000;
2184 srcAddr32(i->src(0), 28, 2);
2185 } else {
2186 code[1] = 0xd0000000;
2187 setAddress24(i->src(0));
2188 }
2189 if (uses64bitAddress(i))
2190 code[1] |= 1 << 26;
2191 srcId(i->src(0).getIndirect(0), 20);
2192
2193 emitPredicate(i);
2194
2195 defId(i, 0, 14);
2196 }
2197
2198 void
2199 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2200 {
2201 uint8_t m;
2202 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2203 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2204 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2205 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2206 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2207 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2208 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2209 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2210 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2211 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2212 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2213 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2214 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2215 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2216 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2217 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2218 default:
2219 return;
2220 }
2221 code[0] |= m << 5;
2222 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2223 code[1] |= 1 << 16;
2224 }
2225
2226 void
2227 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2228 {
2229 ImmediateValue *imm = NULL;
2230 uint64_t opc;
2231
2232 if (i->srcExists(2)) {
2233 imm = i->getSrc(2)->asImm();
2234 if (imm)
2235 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2236 }
2237
2238 switch (i->op) {
2239 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2240 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2241 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2242 default:
2243 assert(0);
2244 return;
2245 }
2246 emitForm_A(i, opc);
2247
2248 if (i->op == OP_SUCLAMP) {
2249 if (i->dType == TYPE_S32)
2250 code[0] |= 1 << 9;
2251 emitSUCLAMPMode(i->subOp);
2252 }
2253
2254 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2255 code[1] |= 1 << 16;
2256
2257 if (i->op != OP_SUEAU) {
2258 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2259 code[0] |= 63 << 14;
2260 code[1] |= i->getDef(0)->reg.data.id << 23;
2261 } else
2262 if (i->defExists(1)) { // r, p
2263 assert(i->def(1).getFile() == FILE_PREDICATE);
2264 code[1] |= i->getDef(1)->reg.data.id << 23;
2265 } else { // r, #
2266 code[1] |= 7 << 23;
2267 }
2268 }
2269 if (imm) {
2270 assert(i->op == OP_SUCLAMP);
2271 i->setSrc(2, imm);
2272 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2273 }
2274 }
2275
2276 void
2277 CodeEmitterNVC0::emitSUGType(DataType ty)
2278 {
2279 switch (ty) {
2280 case TYPE_S32: code[1] |= 1 << 13; break;
2281 case TYPE_U8: code[1] |= 2 << 13; break;
2282 case TYPE_S8: code[1] |= 3 << 13; break;
2283 default:
2284 assert(ty == TYPE_U32);
2285 break;
2286 }
2287 }
2288
2289 void
2290 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2291 {
2292 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2293
2294 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2295 assert(offset == (offset & 0xfffc));
2296
2297 code[1] |= 1 << 21;
2298 code[0] |= offset << 24;
2299 code[1] |= offset >> 8;
2300 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2301 }
2302
2303 void
2304 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2305 {
2306 if (!i->srcExists(s) || (i->predSrc == s)) {
2307 code[1] |= 0x7 << 17;
2308 } else {
2309 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2310 code[1] |= 1 << 20;
2311 srcId(i->src(s), 32 + 17);
2312 }
2313 }
2314
2315 void
2316 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2317 {
2318 code[0] = 0x5;
2319 code[1] = 0xd4000000 | (i->subOp << 15);
2320
2321 emitLoadStoreType(i->dType);
2322 emitSUGType(i->sType);
2323 emitCachingMode(i->cache);
2324
2325 emitPredicate(i);
2326 defId(i->def(0), 14); // destination
2327 srcId(i->src(0), 20); // address
2328 // format
2329 if (i->src(1).getFile() == FILE_GPR)
2330 srcId(i->src(1), 26);
2331 else
2332 setSUConst16(i, 1);
2333 setSUPred(i, 2);
2334 }
2335
2336 void
2337 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2338 {
2339 code[0] = 0x5;
2340 code[1] = 0xdc000000 | (i->subOp << 15);
2341
2342 if (i->op == OP_SUSTP)
2343 code[1] |= i->tex.mask << 22;
2344 else
2345 emitLoadStoreType(i->dType);
2346 emitSUGType(i->sType);
2347 emitCachingMode(i->cache);
2348
2349 emitPredicate(i);
2350 srcId(i->src(0), 20); // address
2351 // format
2352 if (i->src(1).getFile() == FILE_GPR)
2353 srcId(i->src(1), 26);
2354 else
2355 setSUConst16(i, 1);
2356 srcId(i->src(3), 14); // values
2357 setSUPred(i, 2);
2358 }
2359
2360 void
2361 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
2362 {
2363 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2364
2365 if (i->tex.rIndirectSrc < 0) {
2366 code[1] |= 0x00004000;
2367 code[0] |= i->tex.r << 26;
2368 } else {
2369 srcId(i, i->tex.rIndirectSrc, 26);
2370 }
2371 }
2372
2373 void
2374 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
2375 {
2376 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2377
2378 code[1] |= (i->tex.target.getDim() - 1) << 12;
2379 if (i->tex.target.isArray() || i->tex.target.isCube() ||
2380 i->tex.target.getDim() == 3) {
2381 // use e2d mode for 3-dim images, arrays and cubes.
2382 code[1] |= 3 << 12;
2383 }
2384
2385 srcId(i->src(0), 20);
2386 }
2387
2388 void
2389 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
2390 {
2391 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2392
2393 code[0] = 0x5;
2394 code[1] = 0xf0000000;
2395
2396 emitPredicate(i);
2397 emitLoadStoreType(i->sType);
2398
2399 defId(i->def(0), 14);
2400
2401 if (i->defExists(1)) {
2402 defId(i->def(1), 32 + 22);
2403 } else {
2404 code[1] |= 7 << 22;
2405 }
2406
2407 emitSUAddr(i);
2408 emitSUDim(i);
2409 }
2410
2411 void
2412 CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
2413 {
2414 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2415
2416 code[0] = 0x5;
2417 code[1] = 0xd4000000 | (i->subOp << 15);
2418
2419 emitPredicate(i);
2420 emitLoadStoreType(i->dType);
2421
2422 defId(i->def(0), 14);
2423
2424 emitCachingMode(i->cache);
2425 emitSUAddr(i);
2426 emitSUDim(i);
2427 }
2428
2429 void
2430 CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
2431 {
2432 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2433
2434 code[0] = 0x5;
2435 code[1] = 0xdc000000 | (i->subOp << 15);
2436
2437 if (i->op == OP_SUSTP)
2438 code[1] |= i->tex.mask << 17;
2439 else
2440 emitLoadStoreType(i->dType);
2441
2442 emitPredicate(i);
2443
2444 srcId(i->src(1), 14);
2445
2446 emitCachingMode(i->cache);
2447 emitSUAddr(i);
2448 emitSUDim(i);
2449 }
2450
2451 void
2452 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2453 {
2454 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2455 case 0:
2456 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2457 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2458 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2459 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2460 break;
2461 case 1:
2462 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2463 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2464 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2465 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2466 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2467 code[1] |= (i->mask & 0x3) << 2;
2468 break;
2469 case 2:
2470 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2471 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2472 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2473 code[1] |= (i->mask & 0x3) << 2;
2474 code[1] |= (i->mask & 0xc) << 21;
2475 break;
2476 default:
2477 assert(0);
2478 break;
2479 }
2480 }
2481
2482 void
2483 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2484 {
2485 uint64_t opc = 0x4;
2486
2487 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2488 case 0: opc |= 0xe8ULL << 56; break;
2489 case 1: opc |= 0xb4ULL << 56; break;
2490 case 2: opc |= 0x94ULL << 56; break;
2491 default:
2492 assert(0);
2493 break;
2494 }
2495 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2496 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2497 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2498 } else {
2499 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2500 if (isSignedType(i->sType)) opc |= 1 << 6;
2501 }
2502 emitForm_A(i, opc);
2503 emitVectorSubOp(i);
2504
2505 if (i->saturate)
2506 code[0] |= 1 << 9;
2507 if (i->flagsDef >= 0)
2508 code[1] |= 1 << 16;
2509 }
2510
2511 void
2512 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2513 {
2514 assert(i->encSize == 8);
2515 emitForm_A(i, HEX64(10000000, 00000006));
2516 code[0] |= i->subOp << 5;
2517 code[1] |= 0x00e00000;
2518 }
2519
2520 void
2521 CodeEmitterNVC0::emitVOTE(const Instruction *i)
2522 {
2523 assert(i->src(0).getFile() == FILE_PREDICATE);
2524
2525 code[0] = 0x00000004 | (i->subOp << 5);
2526 code[1] = 0x48000000;
2527
2528 emitPredicate(i);
2529
2530 unsigned rp = 0;
2531 for (int d = 0; i->defExists(d); d++) {
2532 if (i->def(d).getFile() == FILE_PREDICATE) {
2533 assert(!(rp & 2));
2534 rp |= 2;
2535 defId(i->def(d), 32 + 22);
2536 } else if (i->def(d).getFile() == FILE_GPR) {
2537 assert(!(rp & 1));
2538 rp |= 1;
2539 defId(i->def(d), 14);
2540 } else {
2541 assert(!"Unhandled def");
2542 }
2543 }
2544 if (!(rp & 1))
2545 code[0] |= 63 << 14;
2546 if (!(rp & 2))
2547 code[1] |= 7 << 22;
2548 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
2549 code[0] |= 1 << 23;
2550 srcId(i->src(0), 20);
2551 }
2552
2553 bool
2554 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2555 {
2556 unsigned int size = insn->encSize;
2557
2558 if (writeIssueDelays && !(codeSize & 0x3f))
2559 size += 8;
2560
2561 if (!insn->encSize) {
2562 ERROR("skipping unencodable instruction: "); insn->print();
2563 return false;
2564 } else
2565 if (codeSize + size > codeSizeLimit) {
2566 ERROR("code emitter output buffer too small\n");
2567 return false;
2568 }
2569
2570 if (writeIssueDelays) {
2571 if (!(codeSize & 0x3f)) {
2572 code[0] = 0x00000007; // cf issue delay "instruction"
2573 code[1] = 0x20000000;
2574 code += 2;
2575 codeSize += 8;
2576 }
2577 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2578 uint32_t *data = code - (id * 2 + 2);
2579 if (id <= 2) {
2580 data[0] |= insn->sched << (id * 8 + 4);
2581 } else
2582 if (id == 3) {
2583 data[0] |= insn->sched << 28;
2584 data[1] |= insn->sched >> 4;
2585 } else {
2586 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2587 }
2588 }
2589
2590 // assert that instructions with multiple defs don't corrupt registers
2591 for (int d = 0; insn->defExists(d); ++d)
2592 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2593
2594 switch (insn->op) {
2595 case OP_MOV:
2596 case OP_RDSV:
2597 emitMOV(insn);
2598 break;
2599 case OP_NOP:
2600 break;
2601 case OP_LOAD:
2602 emitLOAD(insn);
2603 break;
2604 case OP_STORE:
2605 emitSTORE(insn);
2606 break;
2607 case OP_LINTERP:
2608 case OP_PINTERP:
2609 emitINTERP(insn);
2610 break;
2611 case OP_VFETCH:
2612 emitVFETCH(insn);
2613 break;
2614 case OP_EXPORT:
2615 emitEXPORT(insn);
2616 break;
2617 case OP_PFETCH:
2618 emitPFETCH(insn);
2619 break;
2620 case OP_AFETCH:
2621 emitAFETCH(insn);
2622 break;
2623 case OP_EMIT:
2624 case OP_RESTART:
2625 emitOUT(insn);
2626 break;
2627 case OP_ADD:
2628 case OP_SUB:
2629 if (insn->dType == TYPE_F64)
2630 emitDADD(insn);
2631 else if (isFloatType(insn->dType))
2632 emitFADD(insn);
2633 else
2634 emitUADD(insn);
2635 break;
2636 case OP_MUL:
2637 if (insn->dType == TYPE_F64)
2638 emitDMUL(insn);
2639 else if (isFloatType(insn->dType))
2640 emitFMUL(insn);
2641 else
2642 emitUMUL(insn);
2643 break;
2644 case OP_MAD:
2645 case OP_FMA:
2646 if (insn->dType == TYPE_F64)
2647 emitDMAD(insn);
2648 else if (isFloatType(insn->dType))
2649 emitFMAD(insn);
2650 else
2651 emitIMAD(insn);
2652 break;
2653 case OP_SAD:
2654 emitISAD(insn);
2655 break;
2656 case OP_SHLADD:
2657 emitSHLADD(insn);
2658 break;
2659 case OP_NOT:
2660 emitNOT(insn);
2661 break;
2662 case OP_AND:
2663 emitLogicOp(insn, 0);
2664 break;
2665 case OP_OR:
2666 emitLogicOp(insn, 1);
2667 break;
2668 case OP_XOR:
2669 emitLogicOp(insn, 2);
2670 break;
2671 case OP_SHL:
2672 case OP_SHR:
2673 emitShift(insn);
2674 break;
2675 case OP_SET:
2676 case OP_SET_AND:
2677 case OP_SET_OR:
2678 case OP_SET_XOR:
2679 emitSET(insn->asCmp());
2680 break;
2681 case OP_SELP:
2682 emitSELP(insn);
2683 break;
2684 case OP_SLCT:
2685 emitSLCT(insn->asCmp());
2686 break;
2687 case OP_MIN:
2688 case OP_MAX:
2689 emitMINMAX(insn);
2690 break;
2691 case OP_ABS:
2692 case OP_NEG:
2693 case OP_CEIL:
2694 case OP_FLOOR:
2695 case OP_TRUNC:
2696 case OP_SAT:
2697 emitCVT(insn);
2698 break;
2699 case OP_CVT:
2700 if (insn->def(0).getFile() == FILE_PREDICATE ||
2701 insn->src(0).getFile() == FILE_PREDICATE)
2702 emitMOV(insn);
2703 else
2704 emitCVT(insn);
2705 break;
2706 case OP_RSQ:
2707 emitSFnOp(insn, 5 + 2 * insn->subOp);
2708 break;
2709 case OP_RCP:
2710 emitSFnOp(insn, 4 + 2 * insn->subOp);
2711 break;
2712 case OP_LG2:
2713 emitSFnOp(insn, 3);
2714 break;
2715 case OP_EX2:
2716 emitSFnOp(insn, 2);
2717 break;
2718 case OP_SIN:
2719 emitSFnOp(insn, 1);
2720 break;
2721 case OP_COS:
2722 emitSFnOp(insn, 0);
2723 break;
2724 case OP_PRESIN:
2725 case OP_PREEX2:
2726 emitPreOp(insn);
2727 break;
2728 case OP_TEX:
2729 case OP_TXB:
2730 case OP_TXL:
2731 case OP_TXD:
2732 case OP_TXF:
2733 case OP_TXG:
2734 case OP_TXLQ:
2735 emitTEX(insn->asTex());
2736 break;
2737 case OP_TXQ:
2738 emitTXQ(insn->asTex());
2739 break;
2740 case OP_TEXBAR:
2741 emitTEXBAR(insn);
2742 break;
2743 case OP_SUBFM:
2744 case OP_SUCLAMP:
2745 case OP_SUEAU:
2746 emitSUCalc(insn);
2747 break;
2748 case OP_MADSP:
2749 emitMADSP(insn);
2750 break;
2751 case OP_SULDB:
2752 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2753 emitSULDGB(insn->asTex());
2754 else
2755 emitSULDB(insn->asTex());
2756 break;
2757 case OP_SUSTB:
2758 case OP_SUSTP:
2759 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2760 emitSUSTGx(insn->asTex());
2761 else
2762 emitSUSTx(insn->asTex());
2763 break;
2764 case OP_SULEA:
2765 emitSULEA(insn->asTex());
2766 break;
2767 case OP_ATOM:
2768 emitATOM(insn);
2769 break;
2770 case OP_BRA:
2771 case OP_CALL:
2772 case OP_PRERET:
2773 case OP_RET:
2774 case OP_DISCARD:
2775 case OP_EXIT:
2776 case OP_PRECONT:
2777 case OP_CONT:
2778 case OP_PREBREAK:
2779 case OP_BREAK:
2780 case OP_JOINAT:
2781 case OP_BRKPT:
2782 case OP_QUADON:
2783 case OP_QUADPOP:
2784 emitFlow(insn);
2785 break;
2786 case OP_QUADOP:
2787 emitQUADOP(insn, insn->subOp, insn->lanes);
2788 break;
2789 case OP_DFDX:
2790 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2791 break;
2792 case OP_DFDY:
2793 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2794 break;
2795 case OP_POPCNT:
2796 emitPOPC(insn);
2797 break;
2798 case OP_INSBF:
2799 emitINSBF(insn);
2800 break;
2801 case OP_EXTBF:
2802 emitEXTBF(insn);
2803 break;
2804 case OP_BFIND:
2805 emitBFIND(insn);
2806 break;
2807 case OP_PERMT:
2808 emitPERMT(insn);
2809 break;
2810 case OP_JOIN:
2811 emitNOP(insn);
2812 insn->join = 1;
2813 break;
2814 case OP_BAR:
2815 emitBAR(insn);
2816 break;
2817 case OP_MEMBAR:
2818 emitMEMBAR(insn);
2819 break;
2820 case OP_CCTL:
2821 emitCCTL(insn);
2822 break;
2823 case OP_VSHL:
2824 emitVSHL(insn);
2825 break;
2826 case OP_PIXLD:
2827 emitPIXLD(insn);
2828 break;
2829 case OP_VOTE:
2830 emitVOTE(insn);
2831 break;
2832 case OP_PHI:
2833 case OP_UNION:
2834 case OP_CONSTRAINT:
2835 ERROR("operation should have been eliminated");
2836 return false;
2837 case OP_EXP:
2838 case OP_LOG:
2839 case OP_SQRT:
2840 case OP_POW:
2841 ERROR("operation should have been lowered\n");
2842 return false;
2843 default:
2844 ERROR("unknown op: %u\n", insn->op);
2845 return false;
2846 }
2847
2848 if (insn->join) {
2849 code[0] |= 0x10;
2850 assert(insn->encSize == 8);
2851 }
2852
2853 code += insn->encSize / 4;
2854 codeSize += insn->encSize;
2855 return true;
2856 }
2857
2858 uint32_t
2859 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2860 {
2861 const Target::OpInfo &info = targ->getOpInfo(i);
2862
2863 if (writeIssueDelays || info.minEncSize == 8 || 1)
2864 return 8;
2865
2866 if (i->ftz || i->saturate || i->join)
2867 return 8;
2868 if (i->rnd != ROUND_N)
2869 return 8;
2870 if (i->predSrc >= 0 && i->op == OP_MAD)
2871 return 8;
2872
2873 if (i->op == OP_PINTERP) {
2874 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2875 return 8;
2876 } else
2877 if (i->op == OP_MOV && i->lanes != 0xf) {
2878 return 8;
2879 }
2880
2881 for (int s = 0; i->srcExists(s); ++s) {
2882 if (i->src(s).isIndirect(0))
2883 return 8;
2884
2885 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2886 if (SDATA(i->src(s)).offset >= 0x100)
2887 return 8;
2888 if (i->getSrc(s)->reg.fileIndex > 1 &&
2889 i->getSrc(s)->reg.fileIndex != 16)
2890 return 8;
2891 } else
2892 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2893 if (i->dType == TYPE_F32) {
2894 if (SDATA(i->src(s)).u32 >= 0x100)
2895 return 8;
2896 } else {
2897 if (SDATA(i->src(s)).u32 > 0xff)
2898 return 8;
2899 }
2900 }
2901
2902 if (i->op == OP_CVT)
2903 continue;
2904 if (i->src(s).mod != Modifier(0)) {
2905 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2906 if (i->op != OP_RSQ)
2907 return 8;
2908 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2909 if (i->op != OP_ADD || s != 0)
2910 return 8;
2911 }
2912 }
2913
2914 return 4;
2915 }
2916
2917 // Simplified, erring on safe side.
2918 class SchedDataCalculator : public Pass
2919 {
2920 public:
2921 SchedDataCalculator(const Target *targ) : targ(targ) { }
2922
2923 private:
2924 struct RegScores
2925 {
2926 struct Resource {
2927 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2928 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2929 int tex; // TEX to non-TEX delay 17 (0x11)
2930 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2931 int imul; // integer MUL to MUL delay 3
2932 } res;
2933 struct ScoreData {
2934 int r[256];
2935 int p[8];
2936 int c;
2937 } rd, wr;
2938 int base;
2939 int regs;
2940
2941 void rebase(const int base)
2942 {
2943 const int delta = this->base - base;
2944 if (!delta)
2945 return;
2946 this->base = 0;
2947
2948 for (int i = 0; i < regs; ++i) {
2949 rd.r[i] += delta;
2950 wr.r[i] += delta;
2951 }
2952 for (int i = 0; i < 8; ++i) {
2953 rd.p[i] += delta;
2954 wr.p[i] += delta;
2955 }
2956 rd.c += delta;
2957 wr.c += delta;
2958
2959 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2960 res.ld[f] += delta;
2961 res.st[f] += delta;
2962 }
2963 res.sfu += delta;
2964 res.imul += delta;
2965 res.tex += delta;
2966 }
2967 void wipe(int regs)
2968 {
2969 memset(&rd, 0, sizeof(rd));
2970 memset(&wr, 0, sizeof(wr));
2971 memset(&res, 0, sizeof(res));
2972 this->regs = regs;
2973 }
2974 int getLatest(const ScoreData& d) const
2975 {
2976 int max = 0;
2977 for (int i = 0; i < regs; ++i)
2978 if (d.r[i] > max)
2979 max = d.r[i];
2980 for (int i = 0; i < 8; ++i)
2981 if (d.p[i] > max)
2982 max = d.p[i];
2983 if (d.c > max)
2984 max = d.c;
2985 return max;
2986 }
2987 inline int getLatestRd() const
2988 {
2989 return getLatest(rd);
2990 }
2991 inline int getLatestWr() const
2992 {
2993 return getLatest(wr);
2994 }
2995 inline int getLatest() const
2996 {
2997 const int a = getLatestRd();
2998 const int b = getLatestWr();
2999
3000 int max = MAX2(a, b);
3001 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3002 max = MAX2(res.ld[f], max);
3003 max = MAX2(res.st[f], max);
3004 }
3005 max = MAX2(res.sfu, max);
3006 max = MAX2(res.imul, max);
3007 max = MAX2(res.tex, max);
3008 return max;
3009 }
3010 void setMax(const RegScores *that)
3011 {
3012 for (int i = 0; i < regs; ++i) {
3013 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
3014 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
3015 }
3016 for (int i = 0; i < 8; ++i) {
3017 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
3018 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
3019 }
3020 rd.c = MAX2(rd.c, that->rd.c);
3021 wr.c = MAX2(wr.c, that->wr.c);
3022
3023 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3024 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
3025 res.st[f] = MAX2(res.st[f], that->res.st[f]);
3026 }
3027 res.sfu = MAX2(res.sfu, that->res.sfu);
3028 res.imul = MAX2(res.imul, that->res.imul);
3029 res.tex = MAX2(res.tex, that->res.tex);
3030 }
3031 void print(int cycle)
3032 {
3033 for (int i = 0; i < regs; ++i) {
3034 if (rd.r[i] > cycle)
3035 INFO("rd $r%i @ %i\n", i, rd.r[i]);
3036 if (wr.r[i] > cycle)
3037 INFO("wr $r%i @ %i\n", i, wr.r[i]);
3038 }
3039 for (int i = 0; i < 8; ++i) {
3040 if (rd.p[i] > cycle)
3041 INFO("rd $p%i @ %i\n", i, rd.p[i]);
3042 if (wr.p[i] > cycle)
3043 INFO("wr $p%i @ %i\n", i, wr.p[i]);
3044 }
3045 if (rd.c > cycle)
3046 INFO("rd $c @ %i\n", rd.c);
3047 if (wr.c > cycle)
3048 INFO("wr $c @ %i\n", wr.c);
3049 if (res.sfu > cycle)
3050 INFO("sfu @ %i\n", res.sfu);
3051 if (res.imul > cycle)
3052 INFO("imul @ %i\n", res.imul);
3053 if (res.tex > cycle)
3054 INFO("tex @ %i\n", res.tex);
3055 }
3056 };
3057
3058 RegScores *score; // for current BB
3059 std::vector<RegScores> scoreBoards;
3060 int prevData;
3061 operation prevOp;
3062
3063 const Target *targ;
3064
3065 bool visit(Function *);
3066 bool visit(BasicBlock *);
3067
3068 void commitInsn(const Instruction *, int cycle);
3069 int calcDelay(const Instruction *, int cycle) const;
3070 void setDelay(Instruction *, int delay, Instruction *next);
3071
3072 void recordRd(const Value *, const int ready);
3073 void recordWr(const Value *, const int ready);
3074 void checkRd(const Value *, int cycle, int& delay) const;
3075 void checkWr(const Value *, int cycle, int& delay) const;
3076
3077 int getCycles(const Instruction *, int origDelay) const;
3078 };
3079
3080 void
3081 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
3082 {
3083 if (insn->op == OP_EXIT || insn->op == OP_RET)
3084 delay = MAX2(delay, 14);
3085
3086 if (insn->op == OP_TEXBAR) {
3087 // TODO: except if results not used before EXIT
3088 insn->sched = 0xc2;
3089 } else
3090 if (insn->op == OP_JOIN || insn->join) {
3091 insn->sched = 0x00;
3092 } else
3093 if (delay >= 0 || prevData == 0x04 ||
3094 !next || !targ->canDualIssue(insn, next)) {
3095 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
3096 if (prevOp == OP_EXPORT)
3097 insn->sched |= 0x40;
3098 else
3099 insn->sched |= 0x20;
3100 } else {
3101 insn->sched = 0x04; // dual-issue
3102 }
3103
3104 if (prevData != 0x04 || prevOp != OP_EXPORT)
3105 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
3106 prevOp = insn->op;
3107
3108 prevData = insn->sched;
3109 }
3110
3111 int
3112 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
3113 {
3114 if (insn->sched & 0x80) {
3115 int c = (insn->sched & 0x0f) * 2 + 1;
3116 if (insn->op == OP_TEXBAR && origDelay > 0)
3117 c += origDelay;
3118 return c;
3119 }
3120 if (insn->sched & 0x60)
3121 return (insn->sched & 0x1f) + 1;
3122 return (insn->sched == 0x04) ? 0 : 32;
3123 }
3124
3125 bool
3126 SchedDataCalculator::visit(Function *func)
3127 {
3128 int regs = targ->getFileSize(FILE_GPR) + 1;
3129 scoreBoards.resize(func->cfg.getSize());
3130 for (size_t i = 0; i < scoreBoards.size(); ++i)
3131 scoreBoards[i].wipe(regs);
3132 return true;
3133 }
3134
3135 bool
3136 SchedDataCalculator::visit(BasicBlock *bb)
3137 {
3138 Instruction *insn;
3139 Instruction *next = NULL;
3140
3141 int cycle = 0;
3142
3143 prevData = 0x00;
3144 prevOp = OP_NOP;
3145 score = &scoreBoards.at(bb->getId());
3146
3147 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
3148 // back branches will wait until all target dependencies are satisfied
3149 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
3150 continue;
3151 BasicBlock *in = BasicBlock::get(ei.getNode());
3152 if (in->getExit()) {
3153 if (prevData != 0x04)
3154 prevData = in->getExit()->sched;
3155 prevOp = in->getExit()->op;
3156 }
3157 score->setMax(&scoreBoards.at(in->getId()));
3158 }
3159 if (bb->cfg.incidentCount() > 1)
3160 prevOp = OP_NOP;
3161
3162 #ifdef NVC0_DEBUG_SCHED_DATA
3163 INFO("=== BB:%i initial scores\n", bb->getId());
3164 score->print(cycle);
3165 #endif
3166
3167 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
3168 next = insn->next;
3169
3170 commitInsn(insn, cycle);
3171 int delay = calcDelay(next, cycle);
3172 setDelay(insn, delay, next);
3173 cycle += getCycles(insn, delay);
3174
3175 #ifdef NVC0_DEBUG_SCHED_DATA
3176 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
3177 insn->print();
3178 next->print();
3179 #endif
3180 }
3181 if (!insn)
3182 return true;
3183 commitInsn(insn, cycle);
3184
3185 int bbDelay = -1;
3186
3187 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
3188 BasicBlock *out = BasicBlock::get(ei.getNode());
3189
3190 if (ei.getType() != Graph::Edge::BACK) {
3191 // only test the first instruction of the outgoing block
3192 next = out->getEntry();
3193 if (next)
3194 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
3195 } else {
3196 // wait until all dependencies are satisfied
3197 const int regsFree = score->getLatest();
3198 next = out->getFirst();
3199 for (int c = cycle; next && c < regsFree; next = next->next) {
3200 bbDelay = MAX2(bbDelay, calcDelay(next, c));
3201 c += getCycles(next, bbDelay);
3202 }
3203 next = NULL;
3204 }
3205 }
3206 if (bb->cfg.outgoingCount() != 1)
3207 next = NULL;
3208 setDelay(insn, bbDelay, next);
3209 cycle += getCycles(insn, bbDelay);
3210
3211 score->rebase(cycle); // common base for initializing out blocks' scores
3212 return true;
3213 }
3214
3215 #define NVE4_MAX_ISSUE_DELAY 0x1f
3216 int
3217 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
3218 {
3219 int delay = 0, ready = cycle;
3220
3221 for (int s = 0; insn->srcExists(s); ++s)
3222 checkRd(insn->getSrc(s), cycle, delay);
3223 // WAR & WAW don't seem to matter
3224 // for (int s = 0; insn->srcExists(s); ++s)
3225 // recordRd(insn->getSrc(s), cycle);
3226
3227 switch (Target::getOpClass(insn->op)) {
3228 case OPCLASS_SFU:
3229 ready = score->res.sfu;
3230 break;
3231 case OPCLASS_ARITH:
3232 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3233 ready = score->res.imul;
3234 break;
3235 case OPCLASS_TEXTURE:
3236 ready = score->res.tex;
3237 break;
3238 case OPCLASS_LOAD:
3239 ready = score->res.ld[insn->src(0).getFile()];
3240 break;
3241 case OPCLASS_STORE:
3242 ready = score->res.st[insn->src(0).getFile()];
3243 break;
3244 default:
3245 break;
3246 }
3247 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3248 ready = MAX2(ready, score->res.tex);
3249
3250 delay = MAX2(delay, ready - cycle);
3251
3252 // if can issue next cycle, delay is 0, not 1
3253 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3254 }
3255
3256 void
3257 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3258 {
3259 const int ready = cycle + targ->getLatency(insn);
3260
3261 for (int d = 0; insn->defExists(d); ++d)
3262 recordWr(insn->getDef(d), ready);
3263 // WAR & WAW don't seem to matter
3264 // for (int s = 0; insn->srcExists(s); ++s)
3265 // recordRd(insn->getSrc(s), cycle);
3266
3267 switch (Target::getOpClass(insn->op)) {
3268 case OPCLASS_SFU:
3269 score->res.sfu = cycle + 4;
3270 break;
3271 case OPCLASS_ARITH:
3272 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3273 score->res.imul = cycle + 4;
3274 break;
3275 case OPCLASS_TEXTURE:
3276 score->res.tex = cycle + 18;
3277 break;
3278 case OPCLASS_LOAD:
3279 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3280 break;
3281 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3282 score->res.st[insn->src(0).getFile()] = ready;
3283 break;
3284 case OPCLASS_STORE:
3285 score->res.st[insn->src(0).getFile()] = cycle + 4;
3286 score->res.ld[insn->src(0).getFile()] = ready;
3287 break;
3288 case OPCLASS_OTHER:
3289 if (insn->op == OP_TEXBAR)
3290 score->res.tex = cycle;
3291 break;
3292 default:
3293 break;
3294 }
3295
3296 #ifdef NVC0_DEBUG_SCHED_DATA
3297 score->print(cycle);
3298 #endif
3299 }
3300
3301 void
3302 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3303 {
3304 int ready = cycle;
3305 int a, b;
3306
3307 switch (v->reg.file) {
3308 case FILE_GPR:
3309 a = v->reg.data.id;
3310 b = a + v->reg.size / 4;
3311 for (int r = a; r < b; ++r)
3312 ready = MAX2(ready, score->rd.r[r]);
3313 break;
3314 case FILE_PREDICATE:
3315 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3316 break;
3317 case FILE_FLAGS:
3318 ready = MAX2(ready, score->rd.c);
3319 break;
3320 case FILE_SHADER_INPUT:
3321 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3322 case FILE_MEMORY_LOCAL:
3323 case FILE_MEMORY_CONST:
3324 case FILE_MEMORY_SHARED:
3325 case FILE_MEMORY_GLOBAL:
3326 case FILE_SYSTEM_VALUE:
3327 // TODO: any restrictions here ?
3328 break;
3329 case FILE_IMMEDIATE:
3330 break;
3331 default:
3332 assert(0);
3333 break;
3334 }
3335 if (cycle < ready)
3336 delay = MAX2(delay, ready - cycle);
3337 }
3338
3339 void
3340 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3341 {
3342 int ready = cycle;
3343 int a, b;
3344
3345 switch (v->reg.file) {
3346 case FILE_GPR:
3347 a = v->reg.data.id;
3348 b = a + v->reg.size / 4;
3349 for (int r = a; r < b; ++r)
3350 ready = MAX2(ready, score->wr.r[r]);
3351 break;
3352 case FILE_PREDICATE:
3353 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3354 break;
3355 default:
3356 assert(v->reg.file == FILE_FLAGS);
3357 ready = MAX2(ready, score->wr.c);
3358 break;
3359 }
3360 if (cycle < ready)
3361 delay = MAX2(delay, ready - cycle);
3362 }
3363
3364 void
3365 SchedDataCalculator::recordWr(const Value *v, const int ready)
3366 {
3367 int a = v->reg.data.id;
3368
3369 if (v->reg.file == FILE_GPR) {
3370 int b = a + v->reg.size / 4;
3371 for (int r = a; r < b; ++r)
3372 score->rd.r[r] = ready;
3373 } else
3374 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3375 if (v->reg.file == FILE_PREDICATE) {
3376 score->rd.p[a] = ready + 4;
3377 } else {
3378 assert(v->reg.file == FILE_FLAGS);
3379 score->rd.c = ready + 4;
3380 }
3381 }
3382
3383 void
3384 SchedDataCalculator::recordRd(const Value *v, const int ready)
3385 {
3386 int a = v->reg.data.id;
3387
3388 if (v->reg.file == FILE_GPR) {
3389 int b = a + v->reg.size / 4;
3390 for (int r = a; r < b; ++r)
3391 score->wr.r[r] = ready;
3392 } else
3393 if (v->reg.file == FILE_PREDICATE) {
3394 score->wr.p[a] = ready;
3395 } else
3396 if (v->reg.file == FILE_FLAGS) {
3397 score->wr.c = ready;
3398 }
3399 }
3400
3401 bool
3402 calculateSchedDataNVC0(const Target *targ, Function *func)
3403 {
3404 SchedDataCalculator sched(targ);
3405 return sched.run(func, true, true);
3406 }
3407
3408 void
3409 CodeEmitterNVC0::prepareEmission(Function *func)
3410 {
3411 CodeEmitter::prepareEmission(func);
3412
3413 if (targ->hasSWSched)
3414 calculateSchedDataNVC0(targ, func);
3415 }
3416
3417 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3418 : CodeEmitter(target),
3419 targNVC0(target),
3420 writeIssueDelays(target->hasSWSched)
3421 {
3422 code = NULL;
3423 codeSize = codeSizeLimit = 0;
3424 relocInfo = NULL;
3425 }
3426
3427 CodeEmitter *
3428 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3429 {
3430 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3431 emit->setProgramType(type);
3432 return emit;
3433 }
3434
3435 CodeEmitter *
3436 TargetNVC0::getCodeEmitter(Program::Type type)
3437 {
3438 if (chipset >= NVISA_GK20A_CHIPSET)
3439 return createCodeEmitterGK110(type);
3440 return createCodeEmitterNVC0(type);
3441 }
3442
3443 } // namespace nv50_ir