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3ed815bad39fcbc5b4a2da08d9a69788304cd07f
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitAFETCH(const Instruction *);
89 void emitPFETCH(const Instruction *);
90 void emitVFETCH(const Instruction *);
91 void emitEXPORT(const Instruction *);
92 void emitOUT(const Instruction *);
93
94 void emitUADD(const Instruction *);
95 void emitFADD(const Instruction *);
96 void emitDADD(const Instruction *);
97 void emitUMUL(const Instruction *);
98 void emitFMUL(const Instruction *);
99 void emitDMUL(const Instruction *);
100 void emitIMAD(const Instruction *);
101 void emitISAD(const Instruction *);
102 void emitFMAD(const Instruction *);
103 void emitDMAD(const Instruction *);
104 void emitMADSP(const Instruction *);
105
106 void emitNOT(Instruction *);
107 void emitLogicOp(const Instruction *, uint8_t subOp);
108 void emitPOPC(const Instruction *);
109 void emitINSBF(const Instruction *);
110 void emitEXTBF(const Instruction *);
111 void emitBFIND(const Instruction *);
112 void emitPERMT(const Instruction *);
113 void emitShift(const Instruction *);
114
115 void emitSFnOp(const Instruction *, uint8_t subOp);
116
117 void emitCVT(Instruction *);
118 void emitMINMAX(const Instruction *);
119 void emitPreOp(const Instruction *);
120
121 void emitSET(const CmpInstruction *);
122 void emitSLCT(const CmpInstruction *);
123 void emitSELP(const Instruction *);
124
125 void emitTEXBAR(const Instruction *);
126 void emitTEX(const TexInstruction *);
127 void emitTEXCSAA(const TexInstruction *);
128 void emitTXQ(const TexInstruction *);
129
130 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
131
132 void emitFlow(const Instruction *);
133 void emitBAR(const Instruction *);
134
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction *);
137 void emitSULDGB(const TexInstruction *);
138 void emitSUSTGx(const TexInstruction *);
139
140 void emitVSHL(const Instruction *);
141 void emitVectorSubOp(const Instruction *);
142
143 void emitPIXLD(const Instruction *);
144
145 inline void defId(const ValueDef&, const int pos);
146 inline void defId(const Instruction *, int d, const int pos);
147 inline void srcId(const ValueRef&, const int pos);
148 inline void srcId(const ValueRef *, const int pos);
149 inline void srcId(const Instruction *, int s, const int pos);
150 inline void srcAddr32(const ValueRef&, int pos, int shr);
151
152 inline bool isLIMM(const ValueRef&, DataType ty);
153 };
154
155 // for better visibility
156 #define HEX64(h, l) 0x##h##l##ULL
157
158 #define SDATA(a) ((a).rep()->reg.data)
159 #define DDATA(a) ((a).rep()->reg.data)
160
161 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
162 {
163 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
164 }
165
166 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
167 {
168 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
169 }
170
171 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
172 {
173 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
174 code[pos / 32] |= r << (pos % 32);
175 }
176
177 void
178 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
179 {
180 const uint32_t offset = SDATA(src).offset >> shr;
181
182 code[pos / 32] |= offset << (pos % 32);
183 if (pos && (pos < 32))
184 code[1] |= offset >> (32 - pos);
185 }
186
187 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
188 {
189 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
190 }
191
192 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
193 {
194 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
195 code[pos / 32] |= r << (pos % 32);
196 }
197
198 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
199 {
200 const ImmediateValue *imm = ref.get()->asImm();
201
202 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
203 }
204
205 void
206 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
207 {
208 switch (insn->rnd) {
209 case ROUND_M: code[1] |= 1 << 23; break;
210 case ROUND_P: code[1] |= 2 << 23; break;
211 case ROUND_Z: code[1] |= 3 << 23; break;
212 default:
213 assert(insn->rnd == ROUND_N);
214 break;
215 }
216 }
217
218 void
219 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
220 {
221 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
222 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
223 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
224 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
225 }
226
227 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
228 {
229 uint8_t val;
230
231 switch (cc) {
232 case CC_LT: val = 0x1; break;
233 case CC_LTU: val = 0x9; break;
234 case CC_EQ: val = 0x2; break;
235 case CC_EQU: val = 0xa; break;
236 case CC_LE: val = 0x3; break;
237 case CC_LEU: val = 0xb; break;
238 case CC_GT: val = 0x4; break;
239 case CC_GTU: val = 0xc; break;
240 case CC_NE: val = 0x5; break;
241 case CC_NEU: val = 0xd; break;
242 case CC_GE: val = 0x6; break;
243 case CC_GEU: val = 0xe; break;
244 case CC_TR: val = 0xf; break;
245 case CC_FL: val = 0x0; break;
246
247 case CC_A: val = 0x14; break;
248 case CC_NA: val = 0x13; break;
249 case CC_S: val = 0x15; break;
250 case CC_NS: val = 0x12; break;
251 case CC_C: val = 0x16; break;
252 case CC_NC: val = 0x11; break;
253 case CC_O: val = 0x17; break;
254 case CC_NO: val = 0x10; break;
255
256 default:
257 val = 0;
258 assert(!"invalid condition code");
259 break;
260 }
261 code[pos / 32] |= val << (pos % 32);
262 }
263
264 void
265 CodeEmitterNVC0::emitPredicate(const Instruction *i)
266 {
267 if (i->predSrc >= 0) {
268 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
269 srcId(i->src(i->predSrc), 10);
270 if (i->cc == CC_NOT_P)
271 code[0] |= 0x2000; // negate
272 } else {
273 code[0] |= 0x1c00;
274 }
275 }
276
277 void
278 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
279 {
280 switch (src.getFile()) {
281 case FILE_MEMORY_GLOBAL:
282 srcAddr32(src, 26, 0);
283 break;
284 case FILE_MEMORY_LOCAL:
285 case FILE_MEMORY_SHARED:
286 setAddress24(src);
287 break;
288 default:
289 assert(src.getFile() == FILE_MEMORY_CONST);
290 setAddress16(src);
291 break;
292 }
293 }
294
295 void
296 CodeEmitterNVC0::setAddress16(const ValueRef& src)
297 {
298 Symbol *sym = src.get()->asSym();
299
300 assert(sym);
301
302 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
303 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
304 }
305
306 void
307 CodeEmitterNVC0::setAddress24(const ValueRef& src)
308 {
309 Symbol *sym = src.get()->asSym();
310
311 assert(sym);
312
313 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
314 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
315 }
316
317 void
318 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
319 {
320 const ImmediateValue *imm = i->src(s).get()->asImm();
321 uint32_t u32;
322
323 assert(imm);
324 u32 = imm->reg.data.u32;
325
326 if ((code[0] & 0xf) == 0x2) {
327 // LIMM
328 code[0] |= (u32 & 0x3f) << 26;
329 code[1] |= u32 >> 6;
330 } else
331 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
332 // integer immediate
333 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
334 assert(!(code[1] & 0xc000));
335 u32 &= 0xfffff;
336 code[0] |= (u32 & 0x3f) << 26;
337 code[1] |= 0xc000 | (u32 >> 6);
338 } else {
339 // float immediate
340 assert(!(u32 & 0x00000fff));
341 assert(!(code[1] & 0xc000));
342 code[0] |= ((u32 >> 12) & 0x3f) << 26;
343 code[1] |= 0xc000 | (u32 >> 18);
344 }
345 }
346
347 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
348 {
349 const ImmediateValue *imm = ref.get()->asImm();
350
351 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
352
353 assert(s8 == imm->reg.data.s32);
354
355 code[0] |= (s8 & 0x3f) << 26;
356 code[0] |= (s8 >> 6) << 8;
357 }
358
359 void
360 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
361 {
362 code[0] = opc;
363 code[1] = opc >> 32;
364
365 emitPredicate(i);
366
367 defId(i->def(0), 14);
368
369 int s1 = 26;
370 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
371 s1 = 49;
372
373 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
374 switch (i->getSrc(s)->reg.file) {
375 case FILE_MEMORY_CONST:
376 assert(!(code[1] & 0xc000));
377 code[1] |= (s == 2) ? 0x8000 : 0x4000;
378 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
379 setAddress16(i->src(s));
380 break;
381 case FILE_IMMEDIATE:
382 assert(s == 1 ||
383 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
384 assert(!(code[1] & 0xc000));
385 setImmediate(i, s);
386 break;
387 case FILE_GPR:
388 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
389 break;
390 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
391 break;
392 default:
393 // ignore here, can be predicate or flags, but must not be address
394 break;
395 }
396 }
397 }
398
399 void
400 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
401 {
402 code[0] = opc;
403 code[1] = opc >> 32;
404
405 emitPredicate(i);
406
407 defId(i->def(0), 14);
408
409 switch (i->src(0).getFile()) {
410 case FILE_MEMORY_CONST:
411 assert(!(code[1] & 0xc000));
412 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
413 setAddress16(i->src(0));
414 break;
415 case FILE_IMMEDIATE:
416 assert(!(code[1] & 0xc000));
417 setImmediate(i, 0);
418 break;
419 case FILE_GPR:
420 srcId(i->src(0), 26);
421 break;
422 default:
423 // ignore here, can be predicate or flags, but must not be address
424 break;
425 }
426 }
427
428 void
429 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
430 {
431 code[0] = opc;
432
433 int ss2a = 0;
434 if (opc == 0x0d || opc == 0x0e)
435 ss2a = 2;
436
437 defId(i->def(0), 14);
438 srcId(i->src(0), 20);
439
440 assert(pred || (i->predSrc < 0));
441 if (pred)
442 emitPredicate(i);
443
444 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
445 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
446 assert(!(code[0] & (0x300 >> ss2a)));
447 switch (i->src(s).get()->reg.fileIndex) {
448 case 0: code[0] |= 0x100 >> ss2a; break;
449 case 1: code[0] |= 0x200 >> ss2a; break;
450 case 16: code[0] |= 0x300 >> ss2a; break;
451 default:
452 ERROR("invalid c[] space for short form\n");
453 break;
454 }
455 if (s == 1)
456 code[0] |= i->getSrc(s)->reg.data.offset << 24;
457 else
458 code[0] |= i->getSrc(s)->reg.data.offset << 6;
459 } else
460 if (i->src(s).getFile() == FILE_IMMEDIATE) {
461 assert(s == 1);
462 setImmediateS8(i->src(s));
463 } else
464 if (i->src(s).getFile() == FILE_GPR) {
465 srcId(i->src(s), (s == 1) ? 26 : 8);
466 }
467 }
468 }
469
470 void
471 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
472 {
473 if (src.getFile() == FILE_MEMORY_CONST) {
474 switch (src.get()->reg.fileIndex) {
475 case 0: code[0] |= 0x100; break;
476 case 1: code[0] |= 0x200; break;
477 case 16: code[0] |= 0x300; break;
478 default:
479 assert(!"unsupported file index for short op");
480 break;
481 }
482 srcAddr32(src, 20, 2);
483 } else {
484 srcId(src, 20);
485 assert(src.getFile() == FILE_GPR);
486 }
487 }
488
489 void
490 CodeEmitterNVC0::emitNOP(const Instruction *i)
491 {
492 code[0] = 0x000001e4;
493 code[1] = 0x40000000;
494 emitPredicate(i);
495 }
496
497 void
498 CodeEmitterNVC0::emitFMAD(const Instruction *i)
499 {
500 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
501
502 if (i->encSize == 8) {
503 if (isLIMM(i->src(1), TYPE_F32)) {
504 emitForm_A(i, HEX64(20000000, 00000002));
505 } else {
506 emitForm_A(i, HEX64(30000000, 00000000));
507
508 if (i->src(2).mod.neg())
509 code[0] |= 1 << 8;
510 }
511 roundMode_A(i);
512
513 if (neg1)
514 code[0] |= 1 << 9;
515
516 if (i->saturate)
517 code[0] |= 1 << 5;
518 if (i->ftz)
519 code[0] |= 1 << 6;
520 } else {
521 assert(!i->saturate && !i->src(2).mod.neg());
522 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
523 false);
524 if (neg1)
525 code[0] |= 1 << 4;
526 }
527 }
528
529 void
530 CodeEmitterNVC0::emitDMAD(const Instruction *i)
531 {
532 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
533
534 emitForm_A(i, HEX64(20000000, 00000001));
535
536 if (i->src(2).mod.neg())
537 code[0] |= 1 << 8;
538
539 roundMode_A(i);
540
541 if (neg1)
542 code[0] |= 1 << 9;
543
544 assert(!i->saturate);
545 assert(!i->ftz);
546 }
547
548 void
549 CodeEmitterNVC0::emitFMUL(const Instruction *i)
550 {
551 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
552
553 assert(i->postFactor >= -3 && i->postFactor <= 3);
554
555 if (i->encSize == 8) {
556 if (isLIMM(i->src(1), TYPE_F32)) {
557 assert(i->postFactor == 0); // constant folded, hopefully
558 emitForm_A(i, HEX64(30000000, 00000002));
559 } else {
560 emitForm_A(i, HEX64(58000000, 00000000));
561 roundMode_A(i);
562 code[1] |= ((i->postFactor > 0) ?
563 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
564 }
565 if (neg)
566 code[1] ^= 1 << 25; // aliases with LIMM sign bit
567
568 if (i->saturate)
569 code[0] |= 1 << 5;
570
571 if (i->dnz)
572 code[0] |= 1 << 7;
573 else
574 if (i->ftz)
575 code[0] |= 1 << 6;
576 } else {
577 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
578 emitForm_S(i, 0xa8, true);
579 }
580 }
581
582 void
583 CodeEmitterNVC0::emitDMUL(const Instruction *i)
584 {
585 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
586
587 emitForm_A(i, HEX64(50000000, 00000001));
588 roundMode_A(i);
589
590 if (neg)
591 code[0] |= 1 << 9;
592
593 assert(!i->saturate);
594 assert(!i->ftz);
595 assert(!i->dnz);
596 assert(!i->postFactor);
597 }
598
599 void
600 CodeEmitterNVC0::emitUMUL(const Instruction *i)
601 {
602 if (i->encSize == 8) {
603 if (i->src(1).getFile() == FILE_IMMEDIATE) {
604 emitForm_A(i, HEX64(10000000, 00000002));
605 } else {
606 emitForm_A(i, HEX64(50000000, 00000003));
607 }
608 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
609 code[0] |= 1 << 6;
610 if (i->sType == TYPE_S32)
611 code[0] |= 1 << 5;
612 if (i->dType == TYPE_S32)
613 code[0] |= 1 << 7;
614 } else {
615 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
616
617 if (i->sType == TYPE_S32)
618 code[0] |= 1 << 6;
619 }
620 }
621
622 void
623 CodeEmitterNVC0::emitFADD(const Instruction *i)
624 {
625 if (i->encSize == 8) {
626 if (isLIMM(i->src(1), TYPE_F32)) {
627 assert(!i->saturate);
628 emitForm_A(i, HEX64(28000000, 00000002));
629
630 code[0] |= i->src(0).mod.abs() << 7;
631 code[0] |= i->src(0).mod.neg() << 9;
632
633 if (i->src(1).mod.abs())
634 code[1] &= 0xfdffffff;
635 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
636 code[1] ^= 0x02000000;
637 } else {
638 emitForm_A(i, HEX64(50000000, 00000000));
639
640 roundMode_A(i);
641 if (i->saturate)
642 code[1] |= 1 << 17;
643
644 emitNegAbs12(i);
645 if (i->op == OP_SUB) code[0] ^= 1 << 8;
646 }
647 if (i->ftz)
648 code[0] |= 1 << 5;
649 } else {
650 assert(!i->saturate && i->op != OP_SUB &&
651 !i->src(0).mod.abs() &&
652 !i->src(1).mod.neg() && !i->src(1).mod.abs());
653
654 emitForm_S(i, 0x49, true);
655
656 if (i->src(0).mod.neg())
657 code[0] |= 1 << 7;
658 }
659 }
660
661 void
662 CodeEmitterNVC0::emitDADD(const Instruction *i)
663 {
664 assert(i->encSize == 8);
665 emitForm_A(i, HEX64(48000000, 00000001));
666 roundMode_A(i);
667 assert(!i->saturate);
668 assert(!i->ftz);
669 emitNegAbs12(i);
670 if (i->op == OP_SUB)
671 code[0] ^= 1 << 8;
672 }
673
674 void
675 CodeEmitterNVC0::emitUADD(const Instruction *i)
676 {
677 uint32_t addOp = 0;
678
679 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
680 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
681
682 if (i->src(0).mod.neg())
683 addOp |= 0x200;
684 if (i->src(1).mod.neg())
685 addOp |= 0x100;
686 if (i->op == OP_SUB) {
687 addOp ^= 0x100;
688 assert(addOp != 0x300); // would be add-plus-one
689 }
690
691 if (i->encSize == 8) {
692 if (isLIMM(i->src(1), TYPE_U32)) {
693 emitForm_A(i, HEX64(08000000, 00000002));
694 if (i->defExists(1))
695 code[1] |= 1 << 26; // write carry
696 } else {
697 emitForm_A(i, HEX64(48000000, 00000003));
698 if (i->defExists(1))
699 code[1] |= 1 << 16; // write carry
700 }
701 code[0] |= addOp;
702
703 if (i->saturate)
704 code[0] |= 1 << 5;
705 if (i->flagsSrc >= 0) // add carry
706 code[0] |= 1 << 6;
707 } else {
708 assert(!(addOp & 0x100));
709 emitForm_S(i, (addOp >> 3) |
710 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
711 }
712 }
713
714 // TODO: shl-add
715 void
716 CodeEmitterNVC0::emitIMAD(const Instruction *i)
717 {
718 assert(i->encSize == 8);
719 emitForm_A(i, HEX64(20000000, 00000003));
720
721 if (isSignedType(i->dType))
722 code[0] |= 1 << 7;
723 if (isSignedType(i->sType))
724 code[0] |= 1 << 5;
725
726 code[1] |= i->saturate << 24;
727
728 if (i->flagsDef >= 0) code[1] |= 1 << 16;
729 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
730
731 if (i->src(2).mod.neg()) code[0] |= 0x10;
732 if (i->src(1).mod.neg() ^
733 i->src(0).mod.neg()) code[0] |= 0x20;
734
735 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
736 code[0] |= 1 << 6;
737 }
738
739 void
740 CodeEmitterNVC0::emitMADSP(const Instruction *i)
741 {
742 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
743
744 emitForm_A(i, HEX64(00000000, 00000003));
745
746 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
747 code[1] |= 0x01800000;
748 } else {
749 code[0] |= (i->subOp & 0x00f) << 7;
750 code[0] |= (i->subOp & 0x0f0) << 1;
751 code[0] |= (i->subOp & 0x100) >> 3;
752 code[0] |= (i->subOp & 0x200) >> 2;
753 code[1] |= (i->subOp & 0xc00) << 13;
754 }
755
756 if (i->flagsDef >= 0)
757 code[1] |= 1 << 16;
758 }
759
760 void
761 CodeEmitterNVC0::emitISAD(const Instruction *i)
762 {
763 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
764 assert(i->encSize == 8);
765
766 emitForm_A(i, HEX64(38000000, 00000003));
767
768 if (i->dType == TYPE_S32)
769 code[0] |= 1 << 5;
770 }
771
772 void
773 CodeEmitterNVC0::emitNOT(Instruction *i)
774 {
775 assert(i->encSize == 8);
776 i->setSrc(1, i->src(0));
777 emitForm_A(i, HEX64(68000000, 000001c3));
778 }
779
780 void
781 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
782 {
783 if (i->def(0).getFile() == FILE_PREDICATE) {
784 code[0] = 0x00000004 | (subOp << 30);
785 code[1] = 0x0c000000;
786
787 emitPredicate(i);
788
789 defId(i->def(0), 17);
790 srcId(i->src(0), 20);
791 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
792 srcId(i->src(1), 26);
793 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
794
795 if (i->defExists(1)) {
796 defId(i->def(1), 14);
797 } else {
798 code[0] |= 7 << 14;
799 }
800 // (a OP b) OP c
801 if (i->predSrc != 2 && i->srcExists(2)) {
802 code[1] |= subOp << 21;
803 srcId(i->src(2), 17);
804 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
805 } else {
806 code[1] |= 0x000e0000;
807 }
808 } else
809 if (i->encSize == 8) {
810 if (isLIMM(i->src(1), TYPE_U32)) {
811 emitForm_A(i, HEX64(38000000, 00000002));
812
813 if (i->flagsDef >= 0)
814 code[1] |= 1 << 26;
815 } else {
816 emitForm_A(i, HEX64(68000000, 00000003));
817
818 if (i->flagsDef >= 0)
819 code[1] |= 1 << 16;
820 }
821 code[0] |= subOp << 6;
822
823 if (i->flagsSrc >= 0) // carry
824 code[0] |= 1 << 5;
825
826 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
827 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
828 } else {
829 emitForm_S(i, (subOp << 5) |
830 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
831 }
832 }
833
834 void
835 CodeEmitterNVC0::emitPOPC(const Instruction *i)
836 {
837 emitForm_A(i, HEX64(54000000, 00000004));
838
839 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
840 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
841 }
842
843 void
844 CodeEmitterNVC0::emitINSBF(const Instruction *i)
845 {
846 emitForm_A(i, HEX64(28000000, 00000003));
847 }
848
849 void
850 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
851 {
852 emitForm_A(i, HEX64(70000000, 00000003));
853
854 if (i->dType == TYPE_S32)
855 code[0] |= 1 << 5;
856 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
857 code[0] |= 1 << 8;
858 }
859
860 void
861 CodeEmitterNVC0::emitBFIND(const Instruction *i)
862 {
863 emitForm_B(i, HEX64(78000000, 00000003));
864
865 if (i->dType == TYPE_S32)
866 code[0] |= 1 << 5;
867 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
868 code[0] |= 1 << 8;
869 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
870 code[0] |= 1 << 6;
871 }
872
873 void
874 CodeEmitterNVC0::emitPERMT(const Instruction *i)
875 {
876 emitForm_A(i, HEX64(24000000, 00000004));
877
878 code[0] |= i->subOp << 5;
879 }
880
881 void
882 CodeEmitterNVC0::emitShift(const Instruction *i)
883 {
884 if (i->op == OP_SHR) {
885 emitForm_A(i, HEX64(58000000, 00000003)
886 | (isSignedType(i->dType) ? 0x20 : 0x00));
887 } else {
888 emitForm_A(i, HEX64(60000000, 00000003));
889 }
890
891 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
892 code[0] |= 1 << 9;
893 }
894
895 void
896 CodeEmitterNVC0::emitPreOp(const Instruction *i)
897 {
898 if (i->encSize == 8) {
899 emitForm_B(i, HEX64(60000000, 00000000));
900
901 if (i->op == OP_PREEX2)
902 code[0] |= 0x20;
903
904 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
905 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
906 } else {
907 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
908 }
909 }
910
911 void
912 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
913 {
914 if (i->encSize == 8) {
915 code[0] = 0x00000000 | (subOp << 26);
916 code[1] = 0xc8000000;
917
918 emitPredicate(i);
919
920 defId(i->def(0), 14);
921 srcId(i->src(0), 20);
922
923 assert(i->src(0).getFile() == FILE_GPR);
924
925 if (i->saturate) code[0] |= 1 << 5;
926
927 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
928 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
929 } else {
930 emitForm_S(i, 0x80000008 | (subOp << 26), true);
931
932 assert(!i->src(0).mod.neg());
933 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
934 }
935 }
936
937 void
938 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
939 {
940 uint64_t op;
941
942 assert(i->encSize == 8);
943
944 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
945
946 if (i->ftz)
947 op |= 1 << 5;
948 else
949 if (!isFloatType(i->dType))
950 op |= isSignedType(i->dType) ? 0x23 : 0x03;
951 if (i->dType == TYPE_F64)
952 op |= 0x01;
953
954 emitForm_A(i, op);
955 emitNegAbs12(i);
956 }
957
958 void
959 CodeEmitterNVC0::roundMode_C(const Instruction *i)
960 {
961 switch (i->rnd) {
962 case ROUND_M: code[1] |= 1 << 17; break;
963 case ROUND_P: code[1] |= 2 << 17; break;
964 case ROUND_Z: code[1] |= 3 << 17; break;
965 case ROUND_NI: code[0] |= 1 << 7; break;
966 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
967 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
968 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
969 case ROUND_N: break;
970 default:
971 assert(!"invalid round mode");
972 break;
973 }
974 }
975
976 void
977 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
978 {
979 switch (i->rnd) {
980 case ROUND_M:
981 case ROUND_MI: code[0] |= 1 << 16; break;
982 case ROUND_P:
983 case ROUND_PI: code[0] |= 2 << 16; break;
984 case ROUND_Z:
985 case ROUND_ZI: code[0] |= 3 << 16; break;
986 default:
987 break;
988 }
989 }
990
991 void
992 CodeEmitterNVC0::emitCVT(Instruction *i)
993 {
994 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
995 DataType dType;
996
997 switch (i->op) {
998 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
999 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1000 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1001 default:
1002 break;
1003 }
1004
1005 const bool sat = (i->op == OP_SAT) || i->saturate;
1006 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1007 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1008
1009 if (i->op == OP_NEG && i->dType == TYPE_U32)
1010 dType = TYPE_S32;
1011 else
1012 dType = i->dType;
1013
1014 if (i->encSize == 8) {
1015 emitForm_B(i, HEX64(10000000, 00000004));
1016
1017 roundMode_C(i);
1018
1019 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1020 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1021 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1022
1023 if (sat)
1024 code[0] |= 0x20;
1025 if (abs)
1026 code[0] |= 1 << 6;
1027 if (neg && i->op != OP_ABS)
1028 code[0] |= 1 << 8;
1029
1030 if (i->ftz)
1031 code[1] |= 1 << 23;
1032
1033 if (isSignedIntType(dType))
1034 code[0] |= 0x080;
1035 if (isSignedIntType(i->sType))
1036 code[0] |= 0x200;
1037
1038 if (isFloatType(dType)) {
1039 if (!isFloatType(i->sType))
1040 code[1] |= 0x08000000;
1041 } else {
1042 if (isFloatType(i->sType))
1043 code[1] |= 0x04000000;
1044 else
1045 code[1] |= 0x0c000000;
1046 }
1047 } else {
1048 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1049 code[0] = 0x298;
1050 } else
1051 if (isFloatType(dType)) {
1052 if (isFloatType(i->sType))
1053 code[0] = 0x098;
1054 else
1055 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1056 } else {
1057 assert(isFloatType(i->sType));
1058
1059 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1060 }
1061
1062 if (neg) code[0] |= 1 << 16;
1063 if (sat) code[0] |= 1 << 18;
1064 if (abs) code[0] |= 1 << 19;
1065
1066 roundMode_CS(i);
1067 }
1068 }
1069
1070 void
1071 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1072 {
1073 uint32_t hi;
1074 uint32_t lo = 0;
1075
1076 if (i->sType == TYPE_F64)
1077 lo = 0x1;
1078 else
1079 if (!isFloatType(i->sType))
1080 lo = 0x3;
1081
1082 if (isSignedIntType(i->sType))
1083 lo |= 0x20;
1084 if (isFloatType(i->dType)) {
1085 if (isFloatType(i->sType))
1086 lo |= 0x20;
1087 else
1088 lo |= 0x80;
1089 }
1090
1091 switch (i->op) {
1092 case OP_SET_AND: hi = 0x10000000; break;
1093 case OP_SET_OR: hi = 0x10200000; break;
1094 case OP_SET_XOR: hi = 0x10400000; break;
1095 default:
1096 hi = 0x100e0000;
1097 break;
1098 }
1099 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1100
1101 if (i->op != OP_SET)
1102 srcId(i->src(2), 32 + 17);
1103
1104 if (i->def(0).getFile() == FILE_PREDICATE) {
1105 if (i->sType == TYPE_F32)
1106 code[1] += 0x10000000;
1107 else
1108 code[1] += 0x08000000;
1109
1110 code[0] &= ~0xfc000;
1111 defId(i->def(0), 17);
1112 if (i->defExists(1))
1113 defId(i->def(1), 14);
1114 else
1115 code[0] |= 0x1c000;
1116 }
1117
1118 if (i->ftz)
1119 code[1] |= 1 << 27;
1120
1121 emitCondCode(i->setCond, 32 + 23);
1122 emitNegAbs12(i);
1123 }
1124
1125 void
1126 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1127 {
1128 uint64_t op;
1129
1130 switch (i->dType) {
1131 case TYPE_S32:
1132 op = HEX64(30000000, 00000023);
1133 break;
1134 case TYPE_U32:
1135 op = HEX64(30000000, 00000003);
1136 break;
1137 case TYPE_F32:
1138 op = HEX64(38000000, 00000000);
1139 break;
1140 default:
1141 assert(!"invalid type for SLCT");
1142 op = 0;
1143 break;
1144 }
1145 emitForm_A(i, op);
1146
1147 CondCode cc = i->setCond;
1148
1149 if (i->src(2).mod.neg())
1150 cc = reverseCondCode(cc);
1151
1152 emitCondCode(cc, 32 + 23);
1153
1154 if (i->ftz)
1155 code[0] |= 1 << 5;
1156 }
1157
1158 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1159 {
1160 emitForm_A(i, HEX64(20000000, 00000004));
1161
1162 if (i->cc == CC_NOT_P || i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1163 code[1] |= 1 << 20;
1164 }
1165
1166 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1167 {
1168 code[0] = 0x00000006 | (i->subOp << 26);
1169 code[1] = 0xf0000000;
1170 emitPredicate(i);
1171 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1172 }
1173
1174 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1175 {
1176 code[0] = 0x00000086;
1177 code[1] = 0xd0000000;
1178
1179 code[1] |= i->tex.r;
1180 code[1] |= i->tex.s << 8;
1181
1182 if (i->tex.liveOnly)
1183 code[0] |= 1 << 9;
1184
1185 defId(i->def(0), 14);
1186 srcId(i->src(0), 20);
1187 }
1188
1189 static inline bool
1190 isNextIndependentTex(const TexInstruction *i)
1191 {
1192 if (!i->next || !isTextureOp(i->next->op))
1193 return false;
1194 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1195 return false;
1196 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1197 }
1198
1199 void
1200 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1201 {
1202 code[0] = 0x00000006;
1203
1204 if (isNextIndependentTex(i))
1205 code[0] |= 0x080; // t mode
1206 else
1207 code[0] |= 0x100; // p mode
1208
1209 if (i->tex.liveOnly)
1210 code[0] |= 1 << 9;
1211
1212 switch (i->op) {
1213 case OP_TEX: code[1] = 0x80000000; break;
1214 case OP_TXB: code[1] = 0x84000000; break;
1215 case OP_TXL: code[1] = 0x86000000; break;
1216 case OP_TXF: code[1] = 0x90000000; break;
1217 case OP_TXG: code[1] = 0xa0000000; break;
1218 case OP_TXLQ: code[1] = 0xb0000000; break;
1219 case OP_TXD: code[1] = 0xe0000000; break;
1220 default:
1221 assert(!"invalid texture op");
1222 break;
1223 }
1224 if (i->op == OP_TXF) {
1225 if (!i->tex.levelZero)
1226 code[1] |= 0x02000000;
1227 } else
1228 if (i->tex.levelZero) {
1229 code[1] |= 0x02000000;
1230 }
1231
1232 if (i->op != OP_TXD && i->tex.derivAll)
1233 code[1] |= 1 << 13;
1234
1235 defId(i->def(0), 14);
1236 srcId(i->src(0), 20);
1237
1238 emitPredicate(i);
1239
1240 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1241
1242 code[1] |= i->tex.mask << 14;
1243
1244 code[1] |= i->tex.r;
1245 code[1] |= i->tex.s << 8;
1246 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1247 code[1] |= 1 << 18; // in 1st source (with array index)
1248
1249 // texture target:
1250 code[1] |= (i->tex.target.getDim() - 1) << 20;
1251 if (i->tex.target.isCube())
1252 code[1] += 2 << 20;
1253 if (i->tex.target.isArray())
1254 code[1] |= 1 << 19;
1255 if (i->tex.target.isShadow())
1256 code[1] |= 1 << 24;
1257
1258 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1259
1260 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1261 // lzero
1262 if (i->op == OP_TXL)
1263 code[1] &= ~(1 << 26);
1264 else
1265 if (i->op == OP_TXF)
1266 code[1] &= ~(1 << 25);
1267 }
1268 if (i->tex.target == TEX_TARGET_2D_MS ||
1269 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1270 code[1] |= 1 << 23;
1271
1272 if (i->tex.useOffsets == 1)
1273 code[1] |= 1 << 22;
1274 if (i->tex.useOffsets == 4)
1275 code[1] |= 1 << 23;
1276
1277 srcId(i, src1, 26);
1278 }
1279
1280 void
1281 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1282 {
1283 code[0] = 0x00000086;
1284 code[1] = 0xc0000000;
1285
1286 switch (i->tex.query) {
1287 case TXQ_DIMS: code[1] |= 0 << 22; break;
1288 case TXQ_TYPE: code[1] |= 1 << 22; break;
1289 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1290 case TXQ_FILTER: code[1] |= 3 << 22; break;
1291 case TXQ_LOD: code[1] |= 4 << 22; break;
1292 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1293 default:
1294 assert(!"invalid texture query");
1295 break;
1296 }
1297
1298 code[1] |= i->tex.mask << 14;
1299
1300 code[1] |= i->tex.r;
1301 code[1] |= i->tex.s << 8;
1302 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1303 code[1] |= 1 << 18;
1304
1305 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1306
1307 defId(i->def(0), 14);
1308 srcId(i->src(0), 20);
1309 srcId(i, src1, 26);
1310
1311 emitPredicate(i);
1312 }
1313
1314 void
1315 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1316 {
1317 code[0] = 0x00000000 | (laneMask << 6);
1318 code[1] = 0x48000000 | qOp;
1319
1320 defId(i->def(0), 14);
1321 srcId(i->src(0), 20);
1322 srcId(i->srcExists(1) ? i->src(1) : i->src(0), 26);
1323
1324 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1325 code[0] |= 1 << 9; // dall
1326
1327 emitPredicate(i);
1328 }
1329
1330 void
1331 CodeEmitterNVC0::emitFlow(const Instruction *i)
1332 {
1333 const FlowInstruction *f = i->asFlow();
1334
1335 unsigned mask; // bit 0: predicate, bit 1: target
1336
1337 code[0] = 0x00000007;
1338
1339 switch (i->op) {
1340 case OP_BRA:
1341 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1342 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1343 code[0] |= 0x4000;
1344 mask = 3;
1345 break;
1346 case OP_CALL:
1347 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1348 if (f->indirect)
1349 code[0] |= 0x4000; // indirect calls always use c[] source
1350 mask = 2;
1351 break;
1352
1353 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1354 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1355 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1356 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1357 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1358
1359 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1360 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1361 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1362 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1363
1364 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1365 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1366 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1367 default:
1368 assert(!"invalid flow operation");
1369 return;
1370 }
1371
1372 if (mask & 1) {
1373 emitPredicate(i);
1374 if (i->flagsSrc < 0)
1375 code[0] |= 0x1e0;
1376 }
1377
1378 if (!f)
1379 return;
1380
1381 if (f->allWarp)
1382 code[0] |= 1 << 15;
1383 if (f->limit)
1384 code[0] |= 1 << 16;
1385
1386 if (f->indirect) {
1387 if (code[0] & 0x4000) {
1388 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1389 setAddress16(i->src(0));
1390 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1391 if (f->op == OP_BRA)
1392 srcId(f->src(0).getIndirect(0), 20);
1393 } else {
1394 srcId(f, 0, 20);
1395 }
1396 }
1397
1398 if (f->op == OP_CALL) {
1399 if (f->indirect) {
1400 // nothing
1401 } else
1402 if (f->builtin) {
1403 assert(f->absolute);
1404 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1405 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1406 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1407 } else {
1408 assert(!f->absolute);
1409 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1410 code[0] |= (pcRel & 0x3f) << 26;
1411 code[1] |= (pcRel >> 6) & 0x3ffff;
1412 }
1413 } else
1414 if (mask & 2) {
1415 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1416 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1417 pcRel += 8;
1418 // currently we don't want absolute branches
1419 assert(!f->absolute);
1420 code[0] |= (pcRel & 0x3f) << 26;
1421 code[1] |= (pcRel >> 6) & 0x3ffff;
1422 }
1423 }
1424
1425 void
1426 CodeEmitterNVC0::emitBAR(const Instruction *i)
1427 {
1428 Value *rDef = NULL, *pDef = NULL;
1429
1430 switch (i->subOp) {
1431 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1432 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1433 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1434 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1435 default:
1436 code[0] = 0x04;
1437 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1438 break;
1439 }
1440 code[1] = 0x50000000;
1441
1442 code[0] |= 63 << 14;
1443 code[1] |= 7 << 21;
1444
1445 emitPredicate(i);
1446
1447 // barrier id
1448 if (i->src(0).getFile() == FILE_GPR) {
1449 srcId(i->src(0), 20);
1450 } else {
1451 ImmediateValue *imm = i->getSrc(0)->asImm();
1452 assert(imm);
1453 code[0] |= imm->reg.data.u32 << 20;
1454 }
1455
1456 // thread count
1457 if (i->src(1).getFile() == FILE_GPR) {
1458 srcId(i->src(1), 26);
1459 } else {
1460 ImmediateValue *imm = i->getSrc(1)->asImm();
1461 assert(imm);
1462 code[0] |= imm->reg.data.u32 << 26;
1463 code[1] |= imm->reg.data.u32 >> 6;
1464 }
1465
1466 if (i->srcExists(2) && (i->predSrc != 2)) {
1467 srcId(i->src(2), 32 + 17);
1468 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1469 code[1] |= 1 << 20;
1470 } else {
1471 code[1] |= 7 << 17;
1472 }
1473
1474 if (i->defExists(0)) {
1475 if (i->def(0).getFile() == FILE_GPR)
1476 rDef = i->getDef(0);
1477 else
1478 pDef = i->getDef(0);
1479
1480 if (i->defExists(1)) {
1481 if (i->def(1).getFile() == FILE_GPR)
1482 rDef = i->getDef(1);
1483 else
1484 pDef = i->getDef(1);
1485 }
1486 }
1487 if (rDef) {
1488 code[0] &= ~(63 << 14);
1489 defId(rDef, 14);
1490 }
1491 if (pDef) {
1492 code[1] &= ~(7 << 21);
1493 defId(pDef, 32 + 21);
1494 }
1495 }
1496
1497 void
1498 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1499 {
1500 code[0] = 0x00000006;
1501 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1502
1503 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1504 code[0] |= 0x200;
1505
1506 emitPredicate(i);
1507
1508 defId(i->def(0), 14);
1509 srcId(i->src(0).getIndirect(0), 20);
1510 }
1511
1512 void
1513 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1514 {
1515 uint32_t prim = i->src(0).get()->reg.data.u32;
1516
1517 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1518 code[1] = 0x00000000 | (prim >> 6);
1519
1520 emitPredicate(i);
1521
1522 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1523
1524 defId(i->def(0), 14);
1525 srcId(i, src1, 20);
1526 }
1527
1528 void
1529 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1530 {
1531 code[0] = 0x00000006;
1532 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1533
1534 if (i->perPatch)
1535 code[0] |= 0x100;
1536 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1537 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1538
1539 emitPredicate(i);
1540
1541 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1542
1543 defId(i->def(0), 14);
1544 srcId(i->src(0).getIndirect(0), 20);
1545 srcId(i->src(0).getIndirect(1), 26); // vertex address
1546 }
1547
1548 void
1549 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1550 {
1551 unsigned int size = typeSizeof(i->dType);
1552
1553 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1554 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1555
1556 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1557
1558 if (i->perPatch)
1559 code[0] |= 0x100;
1560
1561 emitPredicate(i);
1562
1563 assert(i->src(1).getFile() == FILE_GPR);
1564
1565 srcId(i->src(0).getIndirect(0), 20);
1566 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1567 srcId(i->src(1), 26);
1568 }
1569
1570 void
1571 CodeEmitterNVC0::emitOUT(const Instruction *i)
1572 {
1573 code[0] = 0x00000006;
1574 code[1] = 0x1c000000;
1575
1576 emitPredicate(i);
1577
1578 defId(i->def(0), 14); // new secret address
1579 srcId(i->src(0), 20); // old secret address, should be 0 initially
1580
1581 assert(i->src(0).getFile() == FILE_GPR);
1582
1583 if (i->op == OP_EMIT)
1584 code[0] |= 1 << 5;
1585 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1586 code[0] |= 1 << 6;
1587
1588 // vertex stream
1589 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1590 unsigned int stream = SDATA(i->src(1)).u32;
1591 assert(stream < 4);
1592 if (stream) {
1593 code[1] |= 0xc000;
1594 code[0] |= stream << 26;
1595 } else {
1596 srcId(NULL, 26);
1597 }
1598 } else {
1599 srcId(i->src(1), 26);
1600 }
1601 }
1602
1603 void
1604 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1605 {
1606 if (i->encSize == 8) {
1607 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1608 } else {
1609 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1610 code[0] |= 0x80;
1611 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1612 }
1613 }
1614
1615 void
1616 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1617 {
1618 const uint32_t base = i->getSrc(0)->reg.data.offset;
1619
1620 if (i->encSize == 8) {
1621 code[0] = 0x00000000;
1622 code[1] = 0xc0000000 | (base & 0xffff);
1623
1624 if (i->saturate)
1625 code[0] |= 1 << 5;
1626
1627 if (i->op == OP_PINTERP)
1628 srcId(i->src(1), 26);
1629 else
1630 code[0] |= 0x3f << 26;
1631
1632 srcId(i->src(0).getIndirect(0), 20);
1633 } else {
1634 assert(i->op == OP_PINTERP);
1635 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1636 srcId(i->src(1), 20);
1637 }
1638 emitInterpMode(i);
1639
1640 emitPredicate(i);
1641 defId(i->def(0), 14);
1642
1643 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1644 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1645 else
1646 code[1] |= 0x3f << 17;
1647 }
1648
1649 void
1650 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1651 {
1652 uint8_t val;
1653
1654 switch (ty) {
1655 case TYPE_U8:
1656 val = 0x00;
1657 break;
1658 case TYPE_S8:
1659 val = 0x20;
1660 break;
1661 case TYPE_F16:
1662 case TYPE_U16:
1663 val = 0x40;
1664 break;
1665 case TYPE_S16:
1666 val = 0x60;
1667 break;
1668 case TYPE_F32:
1669 case TYPE_U32:
1670 case TYPE_S32:
1671 val = 0x80;
1672 break;
1673 case TYPE_F64:
1674 case TYPE_U64:
1675 case TYPE_S64:
1676 val = 0xa0;
1677 break;
1678 case TYPE_B128:
1679 val = 0xc0;
1680 break;
1681 default:
1682 val = 0x80;
1683 assert(!"invalid type");
1684 break;
1685 }
1686 code[0] |= val;
1687 }
1688
1689 void
1690 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1691 {
1692 uint32_t val;
1693
1694 switch (c) {
1695 case CACHE_CA:
1696 // case CACHE_WB:
1697 val = 0x000;
1698 break;
1699 case CACHE_CG:
1700 val = 0x100;
1701 break;
1702 case CACHE_CS:
1703 val = 0x200;
1704 break;
1705 case CACHE_CV:
1706 // case CACHE_WT:
1707 val = 0x300;
1708 break;
1709 default:
1710 val = 0;
1711 assert(!"invalid caching mode");
1712 break;
1713 }
1714 code[0] |= val;
1715 }
1716
1717 static inline bool
1718 uses64bitAddress(const Instruction *ldst)
1719 {
1720 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1721 ldst->src(0).isIndirect(0) &&
1722 ldst->getIndirect(0, 0)->reg.size == 8;
1723 }
1724
1725 void
1726 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1727 {
1728 uint32_t opc;
1729
1730 switch (i->src(0).getFile()) {
1731 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1732 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1733 case FILE_MEMORY_SHARED: opc = 0xc9000000; break;
1734 default:
1735 assert(!"invalid memory file");
1736 opc = 0;
1737 break;
1738 }
1739 code[0] = 0x00000005;
1740 code[1] = opc;
1741
1742 setAddressByFile(i->src(0));
1743 srcId(i->src(1), 14);
1744 srcId(i->src(0).getIndirect(0), 20);
1745 if (uses64bitAddress(i))
1746 code[1] |= 1 << 26;
1747
1748 emitPredicate(i);
1749
1750 emitLoadStoreType(i->dType);
1751 emitCachingMode(i->cache);
1752 }
1753
1754 void
1755 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1756 {
1757 uint32_t opc;
1758
1759 code[0] = 0x00000005;
1760
1761 switch (i->src(0).getFile()) {
1762 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1763 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1764 case FILE_MEMORY_SHARED: opc = 0xc1000000; break;
1765 case FILE_MEMORY_CONST:
1766 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1767 emitMOV(i); // not sure if this is any better
1768 return;
1769 }
1770 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1771 code[0] = 0x00000006 | (i->subOp << 8);
1772 break;
1773 default:
1774 assert(!"invalid memory file");
1775 opc = 0;
1776 break;
1777 }
1778 code[1] = opc;
1779
1780 defId(i->def(0), 14);
1781
1782 setAddressByFile(i->src(0));
1783 srcId(i->src(0).getIndirect(0), 20);
1784 if (uses64bitAddress(i))
1785 code[1] |= 1 << 26;
1786
1787 emitPredicate(i);
1788
1789 emitLoadStoreType(i->dType);
1790 emitCachingMode(i->cache);
1791 }
1792
1793 uint8_t
1794 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1795 {
1796 switch (SDATA(ref).sv.sv) {
1797 case SV_LANEID: return 0x00;
1798 case SV_PHYSID: return 0x03;
1799 case SV_VERTEX_COUNT: return 0x10;
1800 case SV_INVOCATION_ID: return 0x11;
1801 case SV_YDIR: return 0x12;
1802 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1803 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1804 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1805 case SV_GRIDID: return 0x2c;
1806 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1807 case SV_LBASE: return 0x34;
1808 case SV_SBASE: return 0x30;
1809 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1810 default:
1811 assert(!"no sreg for system value");
1812 return 0;
1813 }
1814 }
1815
1816 void
1817 CodeEmitterNVC0::emitMOV(const Instruction *i)
1818 {
1819 if (i->def(0).getFile() == FILE_PREDICATE) {
1820 if (i->src(0).getFile() == FILE_GPR) {
1821 code[0] = 0xfc01c003;
1822 code[1] = 0x1a8e0000;
1823 srcId(i->src(0), 20);
1824 } else {
1825 code[0] = 0x0001c004;
1826 code[1] = 0x0c0e0000;
1827 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1828 code[0] |= 7 << 20;
1829 if (!i->getSrc(0)->reg.data.u32)
1830 code[0] |= 1 << 23;
1831 } else {
1832 srcId(i->src(0), 20);
1833 }
1834 }
1835 defId(i->def(0), 17);
1836 emitPredicate(i);
1837 } else
1838 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1839 uint8_t sr = getSRegEncoding(i->src(0));
1840
1841 if (i->encSize == 8) {
1842 code[0] = 0x00000004 | (sr << 26);
1843 code[1] = 0x2c000000;
1844 } else {
1845 code[0] = 0x40000008 | (sr << 20);
1846 }
1847 defId(i->def(0), 14);
1848
1849 emitPredicate(i);
1850 } else
1851 if (i->encSize == 8) {
1852 uint64_t opc;
1853
1854 if (i->src(0).getFile() == FILE_IMMEDIATE)
1855 opc = HEX64(18000000, 000001e2);
1856 else
1857 if (i->src(0).getFile() == FILE_PREDICATE)
1858 opc = HEX64(080e0000, 1c000004);
1859 else
1860 opc = HEX64(28000000, 00000004);
1861
1862 opc |= i->lanes << 5;
1863
1864 emitForm_B(i, opc);
1865 } else {
1866 uint32_t imm;
1867
1868 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1869 imm = SDATA(i->src(0)).u32;
1870 if (imm & 0xfff00000) {
1871 assert(!(imm & 0x000fffff));
1872 code[0] = 0x00000318 | imm;
1873 } else {
1874 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1875 code[0] = 0x00000118 | (imm << 20);
1876 }
1877 } else {
1878 code[0] = 0x0028;
1879 emitShortSrc2(i->src(0));
1880 }
1881 defId(i->def(0), 14);
1882
1883 emitPredicate(i);
1884 }
1885 }
1886
1887 void
1888 CodeEmitterNVC0::emitATOM(const Instruction *i)
1889 {
1890 const bool hasDst = i->defExists(0);
1891 const bool casOrExch =
1892 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1893 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1894
1895 if (i->dType == TYPE_U64) {
1896 switch (i->subOp) {
1897 case NV50_IR_SUBOP_ATOM_ADD:
1898 code[0] = 0x205;
1899 if (hasDst)
1900 code[1] = 0x507e0000;
1901 else
1902 code[1] = 0x10000000;
1903 break;
1904 case NV50_IR_SUBOP_ATOM_EXCH:
1905 code[0] = 0x305;
1906 code[1] = 0x507e0000;
1907 break;
1908 case NV50_IR_SUBOP_ATOM_CAS:
1909 code[0] = 0x325;
1910 code[1] = 0x50000000;
1911 break;
1912 default:
1913 assert(!"invalid u64 red op");
1914 break;
1915 }
1916 } else
1917 if (i->dType == TYPE_U32) {
1918 switch (i->subOp) {
1919 case NV50_IR_SUBOP_ATOM_EXCH:
1920 code[0] = 0x105;
1921 code[1] = 0x507e0000;
1922 break;
1923 case NV50_IR_SUBOP_ATOM_CAS:
1924 code[0] = 0x125;
1925 code[1] = 0x50000000;
1926 break;
1927 default:
1928 code[0] = 0x5 | (i->subOp << 5);
1929 if (hasDst)
1930 code[1] = 0x507e0000;
1931 else
1932 code[1] = 0x10000000;
1933 break;
1934 }
1935 } else
1936 if (i->dType == TYPE_S32) {
1937 assert(i->subOp <= 2);
1938 code[0] = 0x205 | (i->subOp << 5);
1939 if (hasDst)
1940 code[1] = 0x587e0000;
1941 else
1942 code[1] = 0x18000000;
1943 } else
1944 if (i->dType == TYPE_F32) {
1945 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
1946 code[0] = 0x205;
1947 if (hasDst)
1948 code[1] = 0x687e0000;
1949 else
1950 code[1] = 0x28000000;
1951 }
1952
1953 emitPredicate(i);
1954
1955 srcId(i->src(1), 14);
1956
1957 if (hasDst)
1958 defId(i->def(0), 32 + 11);
1959 else
1960 if (casOrExch)
1961 code[1] |= 63 << 11;
1962
1963 if (hasDst || casOrExch) {
1964 const int32_t offset = SDATA(i->src(0)).offset;
1965 assert(offset < 0x80000 && offset >= -0x80000);
1966 code[0] |= offset << 26;
1967 code[1] |= (offset & 0x1ffc0) >> 6;
1968 code[1] |= (offset & 0xe0000) << 6;
1969 } else {
1970 srcAddr32(i->src(0), 26, 0);
1971 }
1972 if (i->getIndirect(0, 0)) {
1973 srcId(i->getIndirect(0, 0), 20);
1974 if (i->getIndirect(0, 0)->reg.size == 8)
1975 code[1] |= 1 << 26;
1976 } else {
1977 code[0] |= 63 << 20;
1978 }
1979
1980 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS)
1981 srcId(i->src(2), 32 + 17);
1982 }
1983
1984 void
1985 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
1986 {
1987 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
1988 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
1989 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
1990 default:
1991 code[0] = 0x45;
1992 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
1993 break;
1994 }
1995 code[1] = 0xe0000000;
1996
1997 emitPredicate(i);
1998 }
1999
2000 void
2001 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2002 {
2003 code[0] = 0x00000005 | (i->subOp << 5);
2004
2005 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2006 code[1] = 0x98000000;
2007 srcAddr32(i->src(0), 28, 2);
2008 } else {
2009 code[1] = 0xd0000000;
2010 setAddress24(i->src(0));
2011 }
2012 if (uses64bitAddress(i))
2013 code[1] |= 1 << 26;
2014 srcId(i->src(0).getIndirect(0), 20);
2015
2016 emitPredicate(i);
2017
2018 defId(i, 0, 14);
2019 }
2020
2021 void
2022 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2023 {
2024 uint8_t m;
2025 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2026 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2027 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2028 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2029 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2030 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2031 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2032 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2033 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2034 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2035 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2036 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2037 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2038 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2039 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2040 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2041 default:
2042 return;
2043 }
2044 code[0] |= m << 5;
2045 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2046 code[1] |= 1 << 16;
2047 }
2048
2049 void
2050 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2051 {
2052 ImmediateValue *imm = NULL;
2053 uint64_t opc;
2054
2055 if (i->srcExists(2)) {
2056 imm = i->getSrc(2)->asImm();
2057 if (imm)
2058 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2059 }
2060
2061 switch (i->op) {
2062 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2063 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2064 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2065 default:
2066 assert(0);
2067 return;
2068 }
2069 emitForm_A(i, opc);
2070
2071 if (i->op == OP_SUCLAMP) {
2072 if (i->dType == TYPE_S32)
2073 code[0] |= 1 << 9;
2074 emitSUCLAMPMode(i->subOp);
2075 }
2076
2077 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2078 code[1] |= 1 << 16;
2079
2080 if (i->op != OP_SUEAU) {
2081 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2082 code[0] |= 63 << 14;
2083 code[1] |= i->getDef(0)->reg.data.id << 23;
2084 } else
2085 if (i->defExists(1)) { // r, p
2086 assert(i->def(1).getFile() == FILE_PREDICATE);
2087 code[1] |= i->getDef(1)->reg.data.id << 23;
2088 } else { // r, #
2089 code[1] |= 7 << 23;
2090 }
2091 }
2092 if (imm) {
2093 assert(i->op == OP_SUCLAMP);
2094 i->setSrc(2, imm);
2095 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2096 }
2097 }
2098
2099 void
2100 CodeEmitterNVC0::emitSUGType(DataType ty)
2101 {
2102 switch (ty) {
2103 case TYPE_S32: code[1] |= 1 << 13; break;
2104 case TYPE_U8: code[1] |= 2 << 13; break;
2105 case TYPE_S8: code[1] |= 3 << 13; break;
2106 default:
2107 assert(ty == TYPE_U32);
2108 break;
2109 }
2110 }
2111
2112 void
2113 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2114 {
2115 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2116
2117 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2118 assert(offset == (offset & 0xfffc));
2119
2120 code[1] |= 1 << 21;
2121 code[0] |= offset << 24;
2122 code[1] |= offset >> 8;
2123 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2124 }
2125
2126 void
2127 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2128 {
2129 if (!i->srcExists(s) || (i->predSrc == s)) {
2130 code[1] |= 0x7 << 17;
2131 } else {
2132 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2133 code[1] |= 1 << 20;
2134 srcId(i->src(s), 32 + 17);
2135 }
2136 }
2137
2138 void
2139 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2140 {
2141 code[0] = 0x5;
2142 code[1] = 0xd4000000 | (i->subOp << 15);
2143
2144 emitLoadStoreType(i->dType);
2145 emitSUGType(i->sType);
2146 emitCachingMode(i->cache);
2147
2148 emitPredicate(i);
2149 defId(i->def(0), 14); // destination
2150 srcId(i->src(0), 20); // address
2151 // format
2152 if (i->src(1).getFile() == FILE_GPR)
2153 srcId(i->src(1), 26);
2154 else
2155 setSUConst16(i, 1);
2156 setSUPred(i, 2);
2157 }
2158
2159 void
2160 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2161 {
2162 code[0] = 0x5;
2163 code[1] = 0xdc000000 | (i->subOp << 15);
2164
2165 if (i->op == OP_SUSTP)
2166 code[1] |= i->tex.mask << 22;
2167 else
2168 emitLoadStoreType(i->dType);
2169 emitSUGType(i->sType);
2170 emitCachingMode(i->cache);
2171
2172 emitPredicate(i);
2173 srcId(i->src(0), 20); // address
2174 // format
2175 if (i->src(1).getFile() == FILE_GPR)
2176 srcId(i->src(1), 26);
2177 else
2178 setSUConst16(i, 1);
2179 srcId(i->src(3), 14); // values
2180 setSUPred(i, 2);
2181 }
2182
2183 void
2184 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2185 {
2186 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2187 case 0:
2188 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2189 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2190 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2191 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2192 break;
2193 case 1:
2194 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2195 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2196 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2197 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2198 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2199 code[1] |= (i->mask & 0x3) << 2;
2200 break;
2201 case 2:
2202 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2203 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2204 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2205 code[1] |= (i->mask & 0x3) << 2;
2206 code[1] |= (i->mask & 0xc) << 21;
2207 break;
2208 default:
2209 assert(0);
2210 break;
2211 }
2212 }
2213
2214 void
2215 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2216 {
2217 uint64_t opc = 0x4;
2218
2219 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2220 case 0: opc |= 0xe8ULL << 56; break;
2221 case 1: opc |= 0xb4ULL << 56; break;
2222 case 2: opc |= 0x94ULL << 56; break;
2223 default:
2224 assert(0);
2225 break;
2226 }
2227 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2228 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2229 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2230 } else {
2231 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2232 if (isSignedType(i->sType)) opc |= 1 << 6;
2233 }
2234 emitForm_A(i, opc);
2235 emitVectorSubOp(i);
2236
2237 if (i->saturate)
2238 code[0] |= 1 << 9;
2239 if (i->flagsDef >= 0)
2240 code[1] |= 1 << 16;
2241 }
2242
2243 void
2244 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2245 {
2246 assert(i->encSize == 8);
2247 emitForm_A(i, HEX64(10000000, 00000006));
2248 code[0] |= i->subOp << 5;
2249 code[1] |= 0x00e00000;
2250 }
2251
2252 bool
2253 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2254 {
2255 unsigned int size = insn->encSize;
2256
2257 if (writeIssueDelays && !(codeSize & 0x3f))
2258 size += 8;
2259
2260 if (!insn->encSize) {
2261 ERROR("skipping unencodable instruction: "); insn->print();
2262 return false;
2263 } else
2264 if (codeSize + size > codeSizeLimit) {
2265 ERROR("code emitter output buffer too small\n");
2266 return false;
2267 }
2268
2269 if (writeIssueDelays) {
2270 if (!(codeSize & 0x3f)) {
2271 code[0] = 0x00000007; // cf issue delay "instruction"
2272 code[1] = 0x20000000;
2273 code += 2;
2274 codeSize += 8;
2275 }
2276 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2277 uint32_t *data = code - (id * 2 + 2);
2278 if (id <= 2) {
2279 data[0] |= insn->sched << (id * 8 + 4);
2280 } else
2281 if (id == 3) {
2282 data[0] |= insn->sched << 28;
2283 data[1] |= insn->sched >> 4;
2284 } else {
2285 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2286 }
2287 }
2288
2289 // assert that instructions with multiple defs don't corrupt registers
2290 for (int d = 0; insn->defExists(d); ++d)
2291 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2292
2293 switch (insn->op) {
2294 case OP_MOV:
2295 case OP_RDSV:
2296 emitMOV(insn);
2297 break;
2298 case OP_NOP:
2299 break;
2300 case OP_LOAD:
2301 emitLOAD(insn);
2302 break;
2303 case OP_STORE:
2304 emitSTORE(insn);
2305 break;
2306 case OP_LINTERP:
2307 case OP_PINTERP:
2308 emitINTERP(insn);
2309 break;
2310 case OP_VFETCH:
2311 emitVFETCH(insn);
2312 break;
2313 case OP_EXPORT:
2314 emitEXPORT(insn);
2315 break;
2316 case OP_PFETCH:
2317 emitPFETCH(insn);
2318 break;
2319 case OP_EMIT:
2320 case OP_RESTART:
2321 emitOUT(insn);
2322 break;
2323 case OP_ADD:
2324 case OP_SUB:
2325 if (insn->dType == TYPE_F64)
2326 emitDADD(insn);
2327 else if (isFloatType(insn->dType))
2328 emitFADD(insn);
2329 else
2330 emitUADD(insn);
2331 break;
2332 case OP_MUL:
2333 if (insn->dType == TYPE_F64)
2334 emitDMUL(insn);
2335 else if (isFloatType(insn->dType))
2336 emitFMUL(insn);
2337 else
2338 emitUMUL(insn);
2339 break;
2340 case OP_MAD:
2341 case OP_FMA:
2342 if (insn->dType == TYPE_F64)
2343 emitDMAD(insn);
2344 else if (isFloatType(insn->dType))
2345 emitFMAD(insn);
2346 else
2347 emitIMAD(insn);
2348 break;
2349 case OP_SAD:
2350 emitISAD(insn);
2351 break;
2352 case OP_NOT:
2353 emitNOT(insn);
2354 break;
2355 case OP_AND:
2356 emitLogicOp(insn, 0);
2357 break;
2358 case OP_OR:
2359 emitLogicOp(insn, 1);
2360 break;
2361 case OP_XOR:
2362 emitLogicOp(insn, 2);
2363 break;
2364 case OP_SHL:
2365 case OP_SHR:
2366 emitShift(insn);
2367 break;
2368 case OP_SET:
2369 case OP_SET_AND:
2370 case OP_SET_OR:
2371 case OP_SET_XOR:
2372 emitSET(insn->asCmp());
2373 break;
2374 case OP_SELP:
2375 emitSELP(insn);
2376 break;
2377 case OP_SLCT:
2378 emitSLCT(insn->asCmp());
2379 break;
2380 case OP_MIN:
2381 case OP_MAX:
2382 emitMINMAX(insn);
2383 break;
2384 case OP_ABS:
2385 case OP_NEG:
2386 case OP_CEIL:
2387 case OP_FLOOR:
2388 case OP_TRUNC:
2389 case OP_CVT:
2390 case OP_SAT:
2391 emitCVT(insn);
2392 break;
2393 case OP_RSQ:
2394 emitSFnOp(insn, 5 + 2 * insn->subOp);
2395 break;
2396 case OP_RCP:
2397 emitSFnOp(insn, 4 + 2 * insn->subOp);
2398 break;
2399 case OP_LG2:
2400 emitSFnOp(insn, 3);
2401 break;
2402 case OP_EX2:
2403 emitSFnOp(insn, 2);
2404 break;
2405 case OP_SIN:
2406 emitSFnOp(insn, 1);
2407 break;
2408 case OP_COS:
2409 emitSFnOp(insn, 0);
2410 break;
2411 case OP_PRESIN:
2412 case OP_PREEX2:
2413 emitPreOp(insn);
2414 break;
2415 case OP_TEX:
2416 case OP_TXB:
2417 case OP_TXL:
2418 case OP_TXD:
2419 case OP_TXF:
2420 case OP_TXG:
2421 case OP_TXLQ:
2422 emitTEX(insn->asTex());
2423 break;
2424 case OP_TXQ:
2425 emitTXQ(insn->asTex());
2426 break;
2427 case OP_TEXBAR:
2428 emitTEXBAR(insn);
2429 break;
2430 case OP_SUBFM:
2431 case OP_SUCLAMP:
2432 case OP_SUEAU:
2433 emitSUCalc(insn);
2434 break;
2435 case OP_MADSP:
2436 emitMADSP(insn);
2437 break;
2438 case OP_SULDB:
2439 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2440 emitSULDGB(insn->asTex());
2441 else
2442 ERROR("SULDB not yet supported on < nve4\n");
2443 break;
2444 case OP_SUSTB:
2445 case OP_SUSTP:
2446 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2447 emitSUSTGx(insn->asTex());
2448 else
2449 ERROR("SUSTx not yet supported on < nve4\n");
2450 break;
2451 case OP_ATOM:
2452 emitATOM(insn);
2453 break;
2454 case OP_BRA:
2455 case OP_CALL:
2456 case OP_PRERET:
2457 case OP_RET:
2458 case OP_DISCARD:
2459 case OP_EXIT:
2460 case OP_PRECONT:
2461 case OP_CONT:
2462 case OP_PREBREAK:
2463 case OP_BREAK:
2464 case OP_JOINAT:
2465 case OP_BRKPT:
2466 case OP_QUADON:
2467 case OP_QUADPOP:
2468 emitFlow(insn);
2469 break;
2470 case OP_QUADOP:
2471 emitQUADOP(insn, insn->subOp, insn->lanes);
2472 break;
2473 case OP_DFDX:
2474 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2475 break;
2476 case OP_DFDY:
2477 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2478 break;
2479 case OP_POPCNT:
2480 emitPOPC(insn);
2481 break;
2482 case OP_INSBF:
2483 emitINSBF(insn);
2484 break;
2485 case OP_EXTBF:
2486 emitEXTBF(insn);
2487 break;
2488 case OP_BFIND:
2489 emitBFIND(insn);
2490 break;
2491 case OP_PERMT:
2492 emitPERMT(insn);
2493 break;
2494 case OP_JOIN:
2495 emitNOP(insn);
2496 insn->join = 1;
2497 break;
2498 case OP_BAR:
2499 emitBAR(insn);
2500 break;
2501 case OP_MEMBAR:
2502 emitMEMBAR(insn);
2503 break;
2504 case OP_CCTL:
2505 emitCCTL(insn);
2506 break;
2507 case OP_VSHL:
2508 emitVSHL(insn);
2509 break;
2510 case OP_PIXLD:
2511 emitPIXLD(insn);
2512 break;
2513 case OP_PHI:
2514 case OP_UNION:
2515 case OP_CONSTRAINT:
2516 ERROR("operation should have been eliminated");
2517 return false;
2518 case OP_EXP:
2519 case OP_LOG:
2520 case OP_SQRT:
2521 case OP_POW:
2522 ERROR("operation should have been lowered\n");
2523 return false;
2524 default:
2525 ERROR("unknow op\n");
2526 return false;
2527 }
2528
2529 if (insn->join) {
2530 code[0] |= 0x10;
2531 assert(insn->encSize == 8);
2532 }
2533
2534 code += insn->encSize / 4;
2535 codeSize += insn->encSize;
2536 return true;
2537 }
2538
2539 uint32_t
2540 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2541 {
2542 const Target::OpInfo &info = targ->getOpInfo(i);
2543
2544 if (writeIssueDelays || info.minEncSize == 8 || 1)
2545 return 8;
2546
2547 if (i->ftz || i->saturate || i->join)
2548 return 8;
2549 if (i->rnd != ROUND_N)
2550 return 8;
2551 if (i->predSrc >= 0 && i->op == OP_MAD)
2552 return 8;
2553
2554 if (i->op == OP_PINTERP) {
2555 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2556 return 8;
2557 } else
2558 if (i->op == OP_MOV && i->lanes != 0xf) {
2559 return 8;
2560 }
2561
2562 for (int s = 0; i->srcExists(s); ++s) {
2563 if (i->src(s).isIndirect(0))
2564 return 8;
2565
2566 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2567 if (SDATA(i->src(s)).offset >= 0x100)
2568 return 8;
2569 if (i->getSrc(s)->reg.fileIndex > 1 &&
2570 i->getSrc(s)->reg.fileIndex != 16)
2571 return 8;
2572 } else
2573 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2574 if (i->dType == TYPE_F32) {
2575 if (SDATA(i->src(s)).u32 >= 0x100)
2576 return 8;
2577 } else {
2578 if (SDATA(i->src(s)).u32 > 0xff)
2579 return 8;
2580 }
2581 }
2582
2583 if (i->op == OP_CVT)
2584 continue;
2585 if (i->src(s).mod != Modifier(0)) {
2586 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2587 if (i->op != OP_RSQ)
2588 return 8;
2589 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2590 if (i->op != OP_ADD || s != 0)
2591 return 8;
2592 }
2593 }
2594
2595 return 4;
2596 }
2597
2598 // Simplified, erring on safe side.
2599 class SchedDataCalculator : public Pass
2600 {
2601 public:
2602 SchedDataCalculator(const Target *targ) : targ(targ) { }
2603
2604 private:
2605 struct RegScores
2606 {
2607 struct Resource {
2608 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2609 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2610 int tex; // TEX to non-TEX delay 17 (0x11)
2611 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2612 int imul; // integer MUL to MUL delay 3
2613 } res;
2614 struct ScoreData {
2615 int r[64];
2616 int p[8];
2617 int c;
2618 } rd, wr;
2619 int base;
2620
2621 void rebase(const int base)
2622 {
2623 const int delta = this->base - base;
2624 if (!delta)
2625 return;
2626 this->base = 0;
2627
2628 for (int i = 0; i < 64; ++i) {
2629 rd.r[i] += delta;
2630 wr.r[i] += delta;
2631 }
2632 for (int i = 0; i < 8; ++i) {
2633 rd.p[i] += delta;
2634 wr.p[i] += delta;
2635 }
2636 rd.c += delta;
2637 wr.c += delta;
2638
2639 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2640 res.ld[f] += delta;
2641 res.st[f] += delta;
2642 }
2643 res.sfu += delta;
2644 res.imul += delta;
2645 res.tex += delta;
2646 }
2647 void wipe()
2648 {
2649 memset(&rd, 0, sizeof(rd));
2650 memset(&wr, 0, sizeof(wr));
2651 memset(&res, 0, sizeof(res));
2652 }
2653 int getLatest(const ScoreData& d) const
2654 {
2655 int max = 0;
2656 for (int i = 0; i < 64; ++i)
2657 if (d.r[i] > max)
2658 max = d.r[i];
2659 for (int i = 0; i < 8; ++i)
2660 if (d.p[i] > max)
2661 max = d.p[i];
2662 if (d.c > max)
2663 max = d.c;
2664 return max;
2665 }
2666 inline int getLatestRd() const
2667 {
2668 return getLatest(rd);
2669 }
2670 inline int getLatestWr() const
2671 {
2672 return getLatest(wr);
2673 }
2674 inline int getLatest() const
2675 {
2676 const int a = getLatestRd();
2677 const int b = getLatestWr();
2678
2679 int max = MAX2(a, b);
2680 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2681 max = MAX2(res.ld[f], max);
2682 max = MAX2(res.st[f], max);
2683 }
2684 max = MAX2(res.sfu, max);
2685 max = MAX2(res.imul, max);
2686 max = MAX2(res.tex, max);
2687 return max;
2688 }
2689 void setMax(const RegScores *that)
2690 {
2691 for (int i = 0; i < 64; ++i) {
2692 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2693 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2694 }
2695 for (int i = 0; i < 8; ++i) {
2696 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2697 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2698 }
2699 rd.c = MAX2(rd.c, that->rd.c);
2700 wr.c = MAX2(wr.c, that->wr.c);
2701
2702 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2703 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2704 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2705 }
2706 res.sfu = MAX2(res.sfu, that->res.sfu);
2707 res.imul = MAX2(res.imul, that->res.imul);
2708 res.tex = MAX2(res.tex, that->res.tex);
2709 }
2710 void print(int cycle)
2711 {
2712 for (int i = 0; i < 64; ++i) {
2713 if (rd.r[i] > cycle)
2714 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2715 if (wr.r[i] > cycle)
2716 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2717 }
2718 for (int i = 0; i < 8; ++i) {
2719 if (rd.p[i] > cycle)
2720 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2721 if (wr.p[i] > cycle)
2722 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2723 }
2724 if (rd.c > cycle)
2725 INFO("rd $c @ %i\n", rd.c);
2726 if (wr.c > cycle)
2727 INFO("wr $c @ %i\n", wr.c);
2728 if (res.sfu > cycle)
2729 INFO("sfu @ %i\n", res.sfu);
2730 if (res.imul > cycle)
2731 INFO("imul @ %i\n", res.imul);
2732 if (res.tex > cycle)
2733 INFO("tex @ %i\n", res.tex);
2734 }
2735 };
2736
2737 RegScores *score; // for current BB
2738 std::vector<RegScores> scoreBoards;
2739 int prevData;
2740 operation prevOp;
2741
2742 const Target *targ;
2743
2744 bool visit(Function *);
2745 bool visit(BasicBlock *);
2746
2747 void commitInsn(const Instruction *, int cycle);
2748 int calcDelay(const Instruction *, int cycle) const;
2749 void setDelay(Instruction *, int delay, Instruction *next);
2750
2751 void recordRd(const Value *, const int ready);
2752 void recordWr(const Value *, const int ready);
2753 void checkRd(const Value *, int cycle, int& delay) const;
2754 void checkWr(const Value *, int cycle, int& delay) const;
2755
2756 int getCycles(const Instruction *, int origDelay) const;
2757 };
2758
2759 void
2760 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2761 {
2762 if (insn->op == OP_EXIT || insn->op == OP_RET)
2763 delay = MAX2(delay, 14);
2764
2765 if (insn->op == OP_TEXBAR) {
2766 // TODO: except if results not used before EXIT
2767 insn->sched = 0xc2;
2768 } else
2769 if (insn->op == OP_JOIN || insn->join) {
2770 insn->sched = 0x00;
2771 } else
2772 if (delay >= 0 || prevData == 0x04 ||
2773 !next || !targ->canDualIssue(insn, next)) {
2774 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2775 if (prevOp == OP_EXPORT)
2776 insn->sched |= 0x40;
2777 else
2778 insn->sched |= 0x20;
2779 } else {
2780 insn->sched = 0x04; // dual-issue
2781 }
2782
2783 if (prevData != 0x04 || prevOp != OP_EXPORT)
2784 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2785 prevOp = insn->op;
2786
2787 prevData = insn->sched;
2788 }
2789
2790 int
2791 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2792 {
2793 if (insn->sched & 0x80) {
2794 int c = (insn->sched & 0x0f) * 2 + 1;
2795 if (insn->op == OP_TEXBAR && origDelay > 0)
2796 c += origDelay;
2797 return c;
2798 }
2799 if (insn->sched & 0x60)
2800 return (insn->sched & 0x1f) + 1;
2801 return (insn->sched == 0x04) ? 0 : 32;
2802 }
2803
2804 bool
2805 SchedDataCalculator::visit(Function *func)
2806 {
2807 scoreBoards.resize(func->cfg.getSize());
2808 for (size_t i = 0; i < scoreBoards.size(); ++i)
2809 scoreBoards[i].wipe();
2810 return true;
2811 }
2812
2813 bool
2814 SchedDataCalculator::visit(BasicBlock *bb)
2815 {
2816 Instruction *insn;
2817 Instruction *next = NULL;
2818
2819 int cycle = 0;
2820
2821 prevData = 0x00;
2822 prevOp = OP_NOP;
2823 score = &scoreBoards.at(bb->getId());
2824
2825 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2826 // back branches will wait until all target dependencies are satisfied
2827 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2828 continue;
2829 BasicBlock *in = BasicBlock::get(ei.getNode());
2830 if (in->getExit()) {
2831 if (prevData != 0x04)
2832 prevData = in->getExit()->sched;
2833 prevOp = in->getExit()->op;
2834 }
2835 score->setMax(&scoreBoards.at(in->getId()));
2836 }
2837 if (bb->cfg.incidentCount() > 1)
2838 prevOp = OP_NOP;
2839
2840 #ifdef NVC0_DEBUG_SCHED_DATA
2841 INFO("=== BB:%i initial scores\n", bb->getId());
2842 score->print(cycle);
2843 #endif
2844
2845 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2846 next = insn->next;
2847
2848 commitInsn(insn, cycle);
2849 int delay = calcDelay(next, cycle);
2850 setDelay(insn, delay, next);
2851 cycle += getCycles(insn, delay);
2852
2853 #ifdef NVC0_DEBUG_SCHED_DATA
2854 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2855 insn->print();
2856 next->print();
2857 #endif
2858 }
2859 if (!insn)
2860 return true;
2861 commitInsn(insn, cycle);
2862
2863 int bbDelay = -1;
2864
2865 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2866 BasicBlock *out = BasicBlock::get(ei.getNode());
2867
2868 if (ei.getType() != Graph::Edge::BACK) {
2869 // only test the first instruction of the outgoing block
2870 next = out->getEntry();
2871 if (next)
2872 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2873 } else {
2874 // wait until all dependencies are satisfied
2875 const int regsFree = score->getLatest();
2876 next = out->getFirst();
2877 for (int c = cycle; next && c < regsFree; next = next->next) {
2878 bbDelay = MAX2(bbDelay, calcDelay(next, c));
2879 c += getCycles(next, bbDelay);
2880 }
2881 next = NULL;
2882 }
2883 }
2884 if (bb->cfg.outgoingCount() != 1)
2885 next = NULL;
2886 setDelay(insn, bbDelay, next);
2887 cycle += getCycles(insn, bbDelay);
2888
2889 score->rebase(cycle); // common base for initializing out blocks' scores
2890 return true;
2891 }
2892
2893 #define NVE4_MAX_ISSUE_DELAY 0x1f
2894 int
2895 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
2896 {
2897 int delay = 0, ready = cycle;
2898
2899 for (int s = 0; insn->srcExists(s); ++s)
2900 checkRd(insn->getSrc(s), cycle, delay);
2901 // WAR & WAW don't seem to matter
2902 // for (int s = 0; insn->srcExists(s); ++s)
2903 // recordRd(insn->getSrc(s), cycle);
2904
2905 switch (Target::getOpClass(insn->op)) {
2906 case OPCLASS_SFU:
2907 ready = score->res.sfu;
2908 break;
2909 case OPCLASS_ARITH:
2910 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2911 ready = score->res.imul;
2912 break;
2913 case OPCLASS_TEXTURE:
2914 ready = score->res.tex;
2915 break;
2916 case OPCLASS_LOAD:
2917 ready = score->res.ld[insn->src(0).getFile()];
2918 break;
2919 case OPCLASS_STORE:
2920 ready = score->res.st[insn->src(0).getFile()];
2921 break;
2922 default:
2923 break;
2924 }
2925 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
2926 ready = MAX2(ready, score->res.tex);
2927
2928 delay = MAX2(delay, ready - cycle);
2929
2930 // if can issue next cycle, delay is 0, not 1
2931 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
2932 }
2933
2934 void
2935 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
2936 {
2937 const int ready = cycle + targ->getLatency(insn);
2938
2939 for (int d = 0; insn->defExists(d); ++d)
2940 recordWr(insn->getDef(d), ready);
2941 // WAR & WAW don't seem to matter
2942 // for (int s = 0; insn->srcExists(s); ++s)
2943 // recordRd(insn->getSrc(s), cycle);
2944
2945 switch (Target::getOpClass(insn->op)) {
2946 case OPCLASS_SFU:
2947 score->res.sfu = cycle + 4;
2948 break;
2949 case OPCLASS_ARITH:
2950 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2951 score->res.imul = cycle + 4;
2952 break;
2953 case OPCLASS_TEXTURE:
2954 score->res.tex = cycle + 18;
2955 break;
2956 case OPCLASS_LOAD:
2957 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
2958 break;
2959 score->res.ld[insn->src(0).getFile()] = cycle + 4;
2960 score->res.st[insn->src(0).getFile()] = ready;
2961 break;
2962 case OPCLASS_STORE:
2963 score->res.st[insn->src(0).getFile()] = cycle + 4;
2964 score->res.ld[insn->src(0).getFile()] = ready;
2965 break;
2966 case OPCLASS_OTHER:
2967 if (insn->op == OP_TEXBAR)
2968 score->res.tex = cycle;
2969 break;
2970 default:
2971 break;
2972 }
2973
2974 #ifdef NVC0_DEBUG_SCHED_DATA
2975 score->print(cycle);
2976 #endif
2977 }
2978
2979 void
2980 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
2981 {
2982 int ready = cycle;
2983 int a, b;
2984
2985 switch (v->reg.file) {
2986 case FILE_GPR:
2987 a = v->reg.data.id;
2988 b = a + v->reg.size / 4;
2989 for (int r = a; r < b; ++r)
2990 ready = MAX2(ready, score->rd.r[r]);
2991 break;
2992 case FILE_PREDICATE:
2993 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
2994 break;
2995 case FILE_FLAGS:
2996 ready = MAX2(ready, score->rd.c);
2997 break;
2998 case FILE_SHADER_INPUT:
2999 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3000 case FILE_MEMORY_LOCAL:
3001 case FILE_MEMORY_CONST:
3002 case FILE_MEMORY_SHARED:
3003 case FILE_MEMORY_GLOBAL:
3004 case FILE_SYSTEM_VALUE:
3005 // TODO: any restrictions here ?
3006 break;
3007 case FILE_IMMEDIATE:
3008 break;
3009 default:
3010 assert(0);
3011 break;
3012 }
3013 if (cycle < ready)
3014 delay = MAX2(delay, ready - cycle);
3015 }
3016
3017 void
3018 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3019 {
3020 int ready = cycle;
3021 int a, b;
3022
3023 switch (v->reg.file) {
3024 case FILE_GPR:
3025 a = v->reg.data.id;
3026 b = a + v->reg.size / 4;
3027 for (int r = a; r < b; ++r)
3028 ready = MAX2(ready, score->wr.r[r]);
3029 break;
3030 case FILE_PREDICATE:
3031 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3032 break;
3033 default:
3034 assert(v->reg.file == FILE_FLAGS);
3035 ready = MAX2(ready, score->wr.c);
3036 break;
3037 }
3038 if (cycle < ready)
3039 delay = MAX2(delay, ready - cycle);
3040 }
3041
3042 void
3043 SchedDataCalculator::recordWr(const Value *v, const int ready)
3044 {
3045 int a = v->reg.data.id;
3046
3047 if (v->reg.file == FILE_GPR) {
3048 int b = a + v->reg.size / 4;
3049 for (int r = a; r < b; ++r)
3050 score->rd.r[r] = ready;
3051 } else
3052 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3053 if (v->reg.file == FILE_PREDICATE) {
3054 score->rd.p[a] = ready + 4;
3055 } else {
3056 assert(v->reg.file == FILE_FLAGS);
3057 score->rd.c = ready + 4;
3058 }
3059 }
3060
3061 void
3062 SchedDataCalculator::recordRd(const Value *v, const int ready)
3063 {
3064 int a = v->reg.data.id;
3065
3066 if (v->reg.file == FILE_GPR) {
3067 int b = a + v->reg.size / 4;
3068 for (int r = a; r < b; ++r)
3069 score->wr.r[r] = ready;
3070 } else
3071 if (v->reg.file == FILE_PREDICATE) {
3072 score->wr.p[a] = ready;
3073 } else
3074 if (v->reg.file == FILE_FLAGS) {
3075 score->wr.c = ready;
3076 }
3077 }
3078
3079 bool
3080 calculateSchedDataNVC0(const Target *targ, Function *func)
3081 {
3082 SchedDataCalculator sched(targ);
3083 return sched.run(func, true, true);
3084 }
3085
3086 void
3087 CodeEmitterNVC0::prepareEmission(Function *func)
3088 {
3089 CodeEmitter::prepareEmission(func);
3090
3091 if (targ->hasSWSched)
3092 calculateSchedDataNVC0(targ, func);
3093 }
3094
3095 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3096 : CodeEmitter(target),
3097 targNVC0(target),
3098 writeIssueDelays(target->hasSWSched)
3099 {
3100 code = NULL;
3101 codeSize = codeSizeLimit = 0;
3102 relocInfo = NULL;
3103 }
3104
3105 CodeEmitter *
3106 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3107 {
3108 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3109 emit->setProgramType(type);
3110 return emit;
3111 }
3112
3113 CodeEmitter *
3114 TargetNVC0::getCodeEmitter(Program::Type type)
3115 {
3116 if (chipset >= NVISA_GK20A_CHIPSET)
3117 return createCodeEmitterGK110(type);
3118 return createCodeEmitterNVC0(type);
3119 }
3120
3121 } // namespace nv50_ir