2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir_target_nvc0.h"
27 // Argh, all these assertions ...
29 class CodeEmitterNVC0
: public CodeEmitter
32 CodeEmitterNVC0(const TargetNVC0
*);
34 virtual bool emitInstruction(Instruction
*);
35 virtual uint32_t getMinEncodingSize(const Instruction
*) const;
36 virtual void prepareEmission(Function
*);
38 inline void setProgramType(Program::Type pType
) { progType
= pType
; }
41 const TargetNVC0
*targNVC0
;
43 Program::Type progType
;
45 const bool writeIssueDelays
;
48 void emitForm_A(const Instruction
*, uint64_t);
49 void emitForm_B(const Instruction
*, uint64_t);
50 void emitForm_S(const Instruction
*, uint32_t, bool pred
);
52 void emitPredicate(const Instruction
*);
54 void setAddress16(const ValueRef
&);
55 void setAddress24(const ValueRef
&);
56 void setAddressByFile(const ValueRef
&);
57 void setImmediate(const Instruction
*, const int s
); // needs op already set
58 void setImmediateS8(const ValueRef
&);
59 void setSUConst16(const Instruction
*, const int s
);
60 void setSUPred(const Instruction
*, const int s
);
61 void setPDSTL(const Instruction
*, const int d
);
63 void emitCondCode(CondCode cc
, int pos
);
64 void emitInterpMode(const Instruction
*);
65 void emitLoadStoreType(DataType ty
);
66 void emitSUGType(DataType
);
67 void emitSUAddr(const TexInstruction
*);
68 void emitSUDim(const TexInstruction
*);
69 void emitCachingMode(CacheMode c
);
71 void emitShortSrc2(const ValueRef
&);
73 inline uint8_t getSRegEncoding(const ValueRef
&);
75 void roundMode_A(const Instruction
*);
76 void roundMode_C(const Instruction
*);
77 void roundMode_CS(const Instruction
*);
79 void emitNegAbs12(const Instruction
*);
81 void emitNOP(const Instruction
*);
83 void emitLOAD(const Instruction
*);
84 void emitSTORE(const Instruction
*);
85 void emitMOV(const Instruction
*);
86 void emitATOM(const Instruction
*);
87 void emitMEMBAR(const Instruction
*);
88 void emitCCTL(const Instruction
*);
90 void emitINTERP(const Instruction
*);
91 void emitAFETCH(const Instruction
*);
92 void emitPFETCH(const Instruction
*);
93 void emitVFETCH(const Instruction
*);
94 void emitEXPORT(const Instruction
*);
95 void emitOUT(const Instruction
*);
97 void emitUADD(const Instruction
*);
98 void emitFADD(const Instruction
*);
99 void emitDADD(const Instruction
*);
100 void emitUMUL(const Instruction
*);
101 void emitFMUL(const Instruction
*);
102 void emitDMUL(const Instruction
*);
103 void emitIMAD(const Instruction
*);
104 void emitISAD(const Instruction
*);
105 void emitSHLADD(const Instruction
*a
);
106 void emitFMAD(const Instruction
*);
107 void emitDMAD(const Instruction
*);
108 void emitMADSP(const Instruction
*);
110 void emitNOT(Instruction
*);
111 void emitLogicOp(const Instruction
*, uint8_t subOp
);
112 void emitPOPC(const Instruction
*);
113 void emitINSBF(const Instruction
*);
114 void emitEXTBF(const Instruction
*);
115 void emitBFIND(const Instruction
*);
116 void emitPERMT(const Instruction
*);
117 void emitShift(const Instruction
*);
119 void emitSFnOp(const Instruction
*, uint8_t subOp
);
121 void emitCVT(Instruction
*);
122 void emitMINMAX(const Instruction
*);
123 void emitPreOp(const Instruction
*);
125 void emitSET(const CmpInstruction
*);
126 void emitSLCT(const CmpInstruction
*);
127 void emitSELP(const Instruction
*);
129 void emitTEXBAR(const Instruction
*);
130 void emitTEX(const TexInstruction
*);
131 void emitTEXCSAA(const TexInstruction
*);
132 void emitTXQ(const TexInstruction
*);
134 void emitQUADOP(const Instruction
*, uint8_t qOp
, uint8_t laneMask
);
136 void emitFlow(const Instruction
*);
137 void emitBAR(const Instruction
*);
139 void emitSUCLAMPMode(uint16_t);
140 void emitSUCalc(Instruction
*);
141 void emitSULDGB(const TexInstruction
*);
142 void emitSUSTGx(const TexInstruction
*);
144 void emitSULDB(const TexInstruction
*);
145 void emitSUSTx(const TexInstruction
*);
146 void emitSULEA(const TexInstruction
*);
148 void emitVSHL(const Instruction
*);
149 void emitVectorSubOp(const Instruction
*);
151 void emitPIXLD(const Instruction
*);
153 void emitSHFL(const Instruction
*);
155 void emitVOTE(const Instruction
*);
157 inline void defId(const ValueDef
&, const int pos
);
158 inline void defId(const Instruction
*, int d
, const int pos
);
159 inline void srcId(const ValueRef
&, const int pos
);
160 inline void srcId(const ValueRef
*, const int pos
);
161 inline void srcId(const Instruction
*, int s
, const int pos
);
162 inline void srcAddr32(const ValueRef
&, int pos
, int shr
);
164 inline bool isLIMM(const ValueRef
&, DataType ty
);
167 // for better visibility
168 #define HEX64(h, l) 0x##h##l##ULL
170 #define SDATA(a) ((a).rep()->reg.data)
171 #define DDATA(a) ((a).rep()->reg.data)
173 void CodeEmitterNVC0::srcId(const ValueRef
& src
, const int pos
)
175 code
[pos
/ 32] |= (src
.get() ? SDATA(src
).id
: 63) << (pos
% 32);
178 void CodeEmitterNVC0::srcId(const ValueRef
*src
, const int pos
)
180 code
[pos
/ 32] |= (src
? SDATA(*src
).id
: 63) << (pos
% 32);
183 void CodeEmitterNVC0::srcId(const Instruction
*insn
, int s
, int pos
)
185 int r
= insn
->srcExists(s
) ? SDATA(insn
->src(s
)).id
: 63;
186 code
[pos
/ 32] |= r
<< (pos
% 32);
190 CodeEmitterNVC0::srcAddr32(const ValueRef
& src
, int pos
, int shr
)
192 const uint32_t offset
= SDATA(src
).offset
>> shr
;
194 code
[pos
/ 32] |= offset
<< (pos
% 32);
195 if (pos
&& (pos
< 32))
196 code
[1] |= offset
>> (32 - pos
);
199 void CodeEmitterNVC0::defId(const ValueDef
& def
, const int pos
)
201 code
[pos
/ 32] |= (def
.get() && def
.getFile() != FILE_FLAGS
? DDATA(def
).id
: 63) << (pos
% 32);
204 void CodeEmitterNVC0::defId(const Instruction
*insn
, int d
, const int pos
)
206 if (insn
->defExists(d
))
207 defId(insn
->def(d
), pos
);
209 code
[pos
/ 32] |= 63 << (pos
% 32);
212 bool CodeEmitterNVC0::isLIMM(const ValueRef
& ref
, DataType ty
)
214 const ImmediateValue
*imm
= ref
.get()->asImm();
216 return imm
&& (imm
->reg
.data
.u32
& ((ty
== TYPE_F32
) ? 0xfff : 0xfff00000));
220 CodeEmitterNVC0::roundMode_A(const Instruction
*insn
)
223 case ROUND_M
: code
[1] |= 1 << 23; break;
224 case ROUND_P
: code
[1] |= 2 << 23; break;
225 case ROUND_Z
: code
[1] |= 3 << 23; break;
227 assert(insn
->rnd
== ROUND_N
);
233 CodeEmitterNVC0::emitNegAbs12(const Instruction
*i
)
235 if (i
->src(1).mod
.abs()) code
[0] |= 1 << 6;
236 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 7;
237 if (i
->src(1).mod
.neg()) code
[0] |= 1 << 8;
238 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 9;
241 void CodeEmitterNVC0::emitCondCode(CondCode cc
, int pos
)
246 case CC_LT
: val
= 0x1; break;
247 case CC_LTU
: val
= 0x9; break;
248 case CC_EQ
: val
= 0x2; break;
249 case CC_EQU
: val
= 0xa; break;
250 case CC_LE
: val
= 0x3; break;
251 case CC_LEU
: val
= 0xb; break;
252 case CC_GT
: val
= 0x4; break;
253 case CC_GTU
: val
= 0xc; break;
254 case CC_NE
: val
= 0x5; break;
255 case CC_NEU
: val
= 0xd; break;
256 case CC_GE
: val
= 0x6; break;
257 case CC_GEU
: val
= 0xe; break;
258 case CC_TR
: val
= 0xf; break;
259 case CC_FL
: val
= 0x0; break;
261 case CC_A
: val
= 0x14; break;
262 case CC_NA
: val
= 0x13; break;
263 case CC_S
: val
= 0x15; break;
264 case CC_NS
: val
= 0x12; break;
265 case CC_C
: val
= 0x16; break;
266 case CC_NC
: val
= 0x11; break;
267 case CC_O
: val
= 0x17; break;
268 case CC_NO
: val
= 0x10; break;
272 assert(!"invalid condition code");
275 code
[pos
/ 32] |= val
<< (pos
% 32);
279 CodeEmitterNVC0::emitPredicate(const Instruction
*i
)
281 if (i
->predSrc
>= 0) {
282 assert(i
->getPredicate()->reg
.file
== FILE_PREDICATE
);
283 srcId(i
->src(i
->predSrc
), 10);
284 if (i
->cc
== CC_NOT_P
)
285 code
[0] |= 0x2000; // negate
292 CodeEmitterNVC0::setAddressByFile(const ValueRef
& src
)
294 switch (src
.getFile()) {
295 case FILE_MEMORY_GLOBAL
:
296 srcAddr32(src
, 26, 0);
298 case FILE_MEMORY_LOCAL
:
299 case FILE_MEMORY_SHARED
:
303 assert(src
.getFile() == FILE_MEMORY_CONST
);
310 CodeEmitterNVC0::setAddress16(const ValueRef
& src
)
312 Symbol
*sym
= src
.get()->asSym();
316 code
[0] |= (sym
->reg
.data
.offset
& 0x003f) << 26;
317 code
[1] |= (sym
->reg
.data
.offset
& 0xffc0) >> 6;
321 CodeEmitterNVC0::setAddress24(const ValueRef
& src
)
323 Symbol
*sym
= src
.get()->asSym();
327 code
[0] |= (sym
->reg
.data
.offset
& 0x00003f) << 26;
328 code
[1] |= (sym
->reg
.data
.offset
& 0xffffc0) >> 6;
332 CodeEmitterNVC0::setImmediate(const Instruction
*i
, const int s
)
334 const ImmediateValue
*imm
= i
->src(s
).get()->asImm();
338 u32
= imm
->reg
.data
.u32
;
340 if ((code
[0] & 0xf) == 0x1) {
342 uint64_t u64
= imm
->reg
.data
.u64
;
343 assert(!(u64
& 0x00000fffffffffffULL
));
344 assert(!(code
[1] & 0xc000));
345 code
[0] |= ((u64
>> 44) & 0x3f) << 26;
346 code
[1] |= 0xc000 | (u64
>> 50);
348 if ((code
[0] & 0xf) == 0x2) {
350 code
[0] |= (u32
& 0x3f) << 26;
353 if ((code
[0] & 0xf) == 0x3 || (code
[0] & 0xf) == 4) {
355 assert((u32
& 0xfff00000) == 0 || (u32
& 0xfff00000) == 0xfff00000);
356 assert(!(code
[1] & 0xc000));
358 code
[0] |= (u32
& 0x3f) << 26;
359 code
[1] |= 0xc000 | (u32
>> 6);
362 assert(!(u32
& 0x00000fff));
363 assert(!(code
[1] & 0xc000));
364 code
[0] |= ((u32
>> 12) & 0x3f) << 26;
365 code
[1] |= 0xc000 | (u32
>> 18);
369 void CodeEmitterNVC0::setImmediateS8(const ValueRef
&ref
)
371 const ImmediateValue
*imm
= ref
.get()->asImm();
373 int8_t s8
= static_cast<int8_t>(imm
->reg
.data
.s32
);
375 assert(s8
== imm
->reg
.data
.s32
);
377 code
[0] |= (s8
& 0x3f) << 26;
378 code
[0] |= (s8
>> 6) << 8;
381 void CodeEmitterNVC0::setPDSTL(const Instruction
*i
, const int d
)
383 assert(d
< 0 || (i
->defExists(d
) && i
->def(d
).getFile() == FILE_PREDICATE
));
385 uint32_t pred
= d
>= 0 ? DDATA(i
->def(d
)).id
: 7;
387 code
[0] |= (pred
& 3) << 8;
388 code
[1] |= (pred
& 4) << (26 - 2);
392 CodeEmitterNVC0::emitForm_A(const Instruction
*i
, uint64_t opc
)
399 defId(i
->def(0), 14);
402 if (i
->srcExists(2) && i
->getSrc(2)->reg
.file
== FILE_MEMORY_CONST
)
405 for (int s
= 0; s
< 3 && i
->srcExists(s
); ++s
) {
406 switch (i
->getSrc(s
)->reg
.file
) {
407 case FILE_MEMORY_CONST
:
408 assert(!(code
[1] & 0xc000));
409 code
[1] |= (s
== 2) ? 0x8000 : 0x4000;
410 code
[1] |= i
->getSrc(s
)->reg
.fileIndex
<< 10;
411 setAddress16(i
->src(s
));
415 i
->op
== OP_MOV
|| i
->op
== OP_PRESIN
|| i
->op
== OP_PREEX2
);
416 assert(!(code
[1] & 0xc000));
420 if ((s
== 2) && ((code
[0] & 0x7) == 2)) // LIMM: 3rd src == dst
422 srcId(i
->src(s
), s
? ((s
== 2) ? 49 : s1
) : 20);
425 if (i
->op
== OP_SELP
) {
426 // OP_SELP is used to implement shared+atomics on Fermi.
427 assert(s
== 2 && i
->src(s
).getFile() == FILE_PREDICATE
);
428 srcId(i
->src(s
), 49);
430 // ignore here, can be predicate or flags, but must not be address
437 CodeEmitterNVC0::emitForm_B(const Instruction
*i
, uint64_t opc
)
444 defId(i
->def(0), 14);
446 switch (i
->src(0).getFile()) {
447 case FILE_MEMORY_CONST
:
448 assert(!(code
[1] & 0xc000));
449 code
[1] |= 0x4000 | (i
->src(0).get()->reg
.fileIndex
<< 10);
450 setAddress16(i
->src(0));
453 assert(!(code
[1] & 0xc000));
457 srcId(i
->src(0), 26);
460 // ignore here, can be predicate or flags, but must not be address
466 CodeEmitterNVC0::emitForm_S(const Instruction
*i
, uint32_t opc
, bool pred
)
471 if (opc
== 0x0d || opc
== 0x0e)
474 defId(i
->def(0), 14);
475 srcId(i
->src(0), 20);
477 assert(pred
|| (i
->predSrc
< 0));
481 for (int s
= 1; s
< 3 && i
->srcExists(s
); ++s
) {
482 if (i
->src(s
).get()->reg
.file
== FILE_MEMORY_CONST
) {
483 assert(!(code
[0] & (0x300 >> ss2a
)));
484 switch (i
->src(s
).get()->reg
.fileIndex
) {
485 case 0: code
[0] |= 0x100 >> ss2a
; break;
486 case 1: code
[0] |= 0x200 >> ss2a
; break;
487 case 16: code
[0] |= 0x300 >> ss2a
; break;
489 ERROR("invalid c[] space for short form\n");
493 code
[0] |= i
->getSrc(s
)->reg
.data
.offset
<< 24;
495 code
[0] |= i
->getSrc(s
)->reg
.data
.offset
<< 6;
497 if (i
->src(s
).getFile() == FILE_IMMEDIATE
) {
499 setImmediateS8(i
->src(s
));
501 if (i
->src(s
).getFile() == FILE_GPR
) {
502 srcId(i
->src(s
), (s
== 1) ? 26 : 8);
508 CodeEmitterNVC0::emitShortSrc2(const ValueRef
&src
)
510 if (src
.getFile() == FILE_MEMORY_CONST
) {
511 switch (src
.get()->reg
.fileIndex
) {
512 case 0: code
[0] |= 0x100; break;
513 case 1: code
[0] |= 0x200; break;
514 case 16: code
[0] |= 0x300; break;
516 assert(!"unsupported file index for short op");
519 srcAddr32(src
, 20, 2);
522 assert(src
.getFile() == FILE_GPR
);
527 CodeEmitterNVC0::emitNOP(const Instruction
*i
)
529 code
[0] = 0x000001e4;
530 code
[1] = 0x40000000;
535 CodeEmitterNVC0::emitFMAD(const Instruction
*i
)
537 bool neg1
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
539 if (i
->encSize
== 8) {
540 if (isLIMM(i
->src(1), TYPE_F32
)) {
541 emitForm_A(i
, HEX64(20000000, 00000002));
543 emitForm_A(i
, HEX64(30000000, 00000000));
545 if (i
->src(2).mod
.neg())
562 assert(!i
->saturate
&& !i
->src(2).mod
.neg());
563 emitForm_S(i
, (i
->src(2).getFile() == FILE_MEMORY_CONST
) ? 0x2e : 0x0e,
571 CodeEmitterNVC0::emitDMAD(const Instruction
*i
)
573 bool neg1
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
575 emitForm_A(i
, HEX64(20000000, 00000001));
577 if (i
->src(2).mod
.neg())
585 assert(!i
->saturate
);
590 CodeEmitterNVC0::emitFMUL(const Instruction
*i
)
592 bool neg
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
594 assert(i
->postFactor
>= -3 && i
->postFactor
<= 3);
596 if (i
->encSize
== 8) {
597 if (isLIMM(i
->src(1), TYPE_F32
)) {
598 assert(i
->postFactor
== 0); // constant folded, hopefully
599 emitForm_A(i
, HEX64(30000000, 00000002));
601 emitForm_A(i
, HEX64(58000000, 00000000));
603 code
[1] |= ((i
->postFactor
> 0) ?
604 (7 - i
->postFactor
) : (0 - i
->postFactor
)) << 17;
607 code
[1] ^= 1 << 25; // aliases with LIMM sign bit
618 assert(!neg
&& !i
->saturate
&& !i
->ftz
&& !i
->postFactor
);
619 emitForm_S(i
, 0xa8, true);
624 CodeEmitterNVC0::emitDMUL(const Instruction
*i
)
626 bool neg
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
628 emitForm_A(i
, HEX64(50000000, 00000001));
634 assert(!i
->saturate
);
637 assert(!i
->postFactor
);
641 CodeEmitterNVC0::emitUMUL(const Instruction
*i
)
643 if (i
->encSize
== 8) {
644 if (i
->src(1).getFile() == FILE_IMMEDIATE
) {
645 emitForm_A(i
, HEX64(10000000, 00000002));
647 emitForm_A(i
, HEX64(50000000, 00000003));
649 if (i
->subOp
== NV50_IR_SUBOP_MUL_HIGH
)
651 if (i
->sType
== TYPE_S32
)
653 if (i
->dType
== TYPE_S32
)
656 emitForm_S(i
, i
->src(1).getFile() == FILE_IMMEDIATE
? 0xaa : 0x2a, true);
658 if (i
->sType
== TYPE_S32
)
664 CodeEmitterNVC0::emitFADD(const Instruction
*i
)
666 if (i
->encSize
== 8) {
667 if (isLIMM(i
->src(1), TYPE_F32
)) {
668 assert(!i
->saturate
);
669 emitForm_A(i
, HEX64(28000000, 00000002));
671 code
[0] |= i
->src(0).mod
.abs() << 7;
672 code
[0] |= i
->src(0).mod
.neg() << 9;
674 if (i
->src(1).mod
.abs())
675 code
[1] &= 0xfdffffff;
676 if ((i
->op
== OP_SUB
) != static_cast<bool>(i
->src(1).mod
.neg()))
677 code
[1] ^= 0x02000000;
679 emitForm_A(i
, HEX64(50000000, 00000000));
686 if (i
->op
== OP_SUB
) code
[0] ^= 1 << 8;
691 assert(!i
->saturate
&& i
->op
!= OP_SUB
&&
692 !i
->src(0).mod
.abs() &&
693 !i
->src(1).mod
.neg() && !i
->src(1).mod
.abs());
695 emitForm_S(i
, 0x49, true);
697 if (i
->src(0).mod
.neg())
703 CodeEmitterNVC0::emitDADD(const Instruction
*i
)
705 assert(i
->encSize
== 8);
706 emitForm_A(i
, HEX64(48000000, 00000001));
708 assert(!i
->saturate
);
716 CodeEmitterNVC0::emitUADD(const Instruction
*i
)
720 assert(!i
->src(0).mod
.abs() && !i
->src(1).mod
.abs());
722 if (i
->src(0).mod
.neg())
724 if (i
->src(1).mod
.neg())
729 assert(addOp
!= 0x300); // would be add-plus-one
731 if (i
->encSize
== 8) {
732 if (isLIMM(i
->src(1), TYPE_U32
)) {
733 emitForm_A(i
, HEX64(08000000, 00000002));
734 if (i
->flagsDef
>= 0)
735 code
[1] |= 1 << 26; // write carry
737 emitForm_A(i
, HEX64(48000000, 00000003));
738 if (i
->flagsDef
>= 0)
739 code
[1] |= 1 << 16; // write carry
745 if (i
->flagsSrc
>= 0) // add carry
748 assert(!(addOp
& 0x100));
749 emitForm_S(i
, (addOp
>> 3) |
750 ((i
->src(1).getFile() == FILE_IMMEDIATE
) ? 0xac : 0x2c), true);
755 CodeEmitterNVC0::emitIMAD(const Instruction
*i
)
758 i
->src(2).mod
.neg() | ((i
->src(0).mod
.neg() ^ i
->src(1).mod
.neg()) << 1);
760 assert(i
->encSize
== 8);
761 emitForm_A(i
, HEX64(20000000, 00000003));
764 code
[0] |= addOp
<< 8;
766 if (isSignedType(i
->dType
))
768 if (isSignedType(i
->sType
))
771 code
[1] |= i
->saturate
<< 24;
773 if (i
->flagsDef
>= 0) code
[1] |= 1 << 16;
774 if (i
->flagsSrc
>= 0) code
[1] |= 1 << 23;
776 if (i
->subOp
== NV50_IR_SUBOP_MUL_HIGH
)
781 CodeEmitterNVC0::emitSHLADD(const Instruction
*i
)
783 uint8_t addOp
= (i
->src(0).mod
.neg() << 1) | i
->src(2).mod
.neg();
784 const ImmediateValue
*imm
= i
->src(1).get()->asImm();
787 code
[0] = 0x00000003;
788 code
[1] = 0x40000000 | addOp
<< 23;
792 defId(i
->def(0), 14);
793 srcId(i
->src(0), 20);
795 if (i
->flagsDef
>= 0)
798 assert(!(imm
->reg
.data
.u32
& 0xffffffe0));
799 code
[0] |= imm
->reg
.data
.u32
<< 5;
801 switch (i
->src(2).getFile()) {
803 srcId(i
->src(2), 26);
805 case FILE_MEMORY_CONST
:
807 code
[1] |= i
->getSrc(2)->reg
.fileIndex
<< 10;
808 setAddress16(i
->src(2));
814 assert(!"bad src2 file");
820 CodeEmitterNVC0::emitMADSP(const Instruction
*i
)
822 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
);
824 emitForm_A(i
, HEX64(00000000, 00000003));
826 if (i
->subOp
== NV50_IR_SUBOP_MADSP_SD
) {
827 code
[1] |= 0x01800000;
829 code
[0] |= (i
->subOp
& 0x00f) << 7;
830 code
[0] |= (i
->subOp
& 0x0f0) << 1;
831 code
[0] |= (i
->subOp
& 0x100) >> 3;
832 code
[0] |= (i
->subOp
& 0x200) >> 2;
833 code
[1] |= (i
->subOp
& 0xc00) << 13;
836 if (i
->flagsDef
>= 0)
841 CodeEmitterNVC0::emitISAD(const Instruction
*i
)
843 assert(i
->dType
== TYPE_S32
|| i
->dType
== TYPE_U32
);
844 assert(i
->encSize
== 8);
846 emitForm_A(i
, HEX64(38000000, 00000003));
848 if (i
->dType
== TYPE_S32
)
853 CodeEmitterNVC0::emitNOT(Instruction
*i
)
855 assert(i
->encSize
== 8);
856 i
->setSrc(1, i
->src(0));
857 emitForm_A(i
, HEX64(68000000, 000001c3
));
861 CodeEmitterNVC0::emitLogicOp(const Instruction
*i
, uint8_t subOp
)
863 if (i
->def(0).getFile() == FILE_PREDICATE
) {
864 code
[0] = 0x00000004 | (subOp
<< 30);
865 code
[1] = 0x0c000000;
869 defId(i
->def(0), 17);
870 srcId(i
->src(0), 20);
871 if (i
->src(0).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 23;
872 srcId(i
->src(1), 26);
873 if (i
->src(1).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 29;
875 if (i
->defExists(1)) {
876 defId(i
->def(1), 14);
881 if (i
->predSrc
!= 2 && i
->srcExists(2)) {
882 code
[1] |= subOp
<< 21;
883 srcId(i
->src(2), 49);
884 if (i
->src(2).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[1] |= 1 << 20;
886 code
[1] |= 0x000e0000;
889 if (i
->encSize
== 8) {
890 if (isLIMM(i
->src(1), TYPE_U32
)) {
891 emitForm_A(i
, HEX64(38000000, 00000002));
893 if (i
->flagsDef
>= 0)
896 emitForm_A(i
, HEX64(68000000, 00000003));
898 if (i
->flagsDef
>= 0)
901 code
[0] |= subOp
<< 6;
903 if (i
->flagsSrc
>= 0) // carry
906 if (i
->src(0).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 9;
907 if (i
->src(1).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 8;
909 emitForm_S(i
, (subOp
<< 5) |
910 ((i
->src(1).getFile() == FILE_IMMEDIATE
) ? 0x1d : 0x8d), true);
915 CodeEmitterNVC0::emitPOPC(const Instruction
*i
)
917 emitForm_A(i
, HEX64(54000000, 00000004));
919 if (i
->src(0).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 9;
920 if (i
->src(1).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 8;
924 CodeEmitterNVC0::emitINSBF(const Instruction
*i
)
926 emitForm_A(i
, HEX64(28000000, 00000003));
930 CodeEmitterNVC0::emitEXTBF(const Instruction
*i
)
932 emitForm_A(i
, HEX64(70000000, 00000003));
934 if (i
->dType
== TYPE_S32
)
936 if (i
->subOp
== NV50_IR_SUBOP_EXTBF_REV
)
941 CodeEmitterNVC0::emitBFIND(const Instruction
*i
)
943 emitForm_B(i
, HEX64(78000000, 00000003));
945 if (i
->dType
== TYPE_S32
)
947 if (i
->src(0).mod
== Modifier(NV50_IR_MOD_NOT
))
949 if (i
->subOp
== NV50_IR_SUBOP_BFIND_SAMT
)
954 CodeEmitterNVC0::emitPERMT(const Instruction
*i
)
956 emitForm_A(i
, HEX64(24000000, 00000004));
958 code
[0] |= i
->subOp
<< 5;
962 CodeEmitterNVC0::emitShift(const Instruction
*i
)
964 if (i
->op
== OP_SHR
) {
965 emitForm_A(i
, HEX64(58000000, 00000003)
966 | (isSignedType(i
->dType
) ? 0x20 : 0x00));
968 emitForm_A(i
, HEX64(60000000, 00000003));
971 if (i
->subOp
== NV50_IR_SUBOP_SHIFT_WRAP
)
976 CodeEmitterNVC0::emitPreOp(const Instruction
*i
)
978 if (i
->encSize
== 8) {
979 emitForm_B(i
, HEX64(60000000, 00000000));
981 if (i
->op
== OP_PREEX2
)
984 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 6;
985 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 8;
987 emitForm_S(i
, i
->op
== OP_PREEX2
? 0x74000008 : 0x70000008, true);
992 CodeEmitterNVC0::emitSFnOp(const Instruction
*i
, uint8_t subOp
)
994 if (i
->encSize
== 8) {
995 code
[0] = 0x00000000 | (subOp
<< 26);
996 code
[1] = 0xc8000000;
1000 defId(i
->def(0), 14);
1001 srcId(i
->src(0), 20);
1003 assert(i
->src(0).getFile() == FILE_GPR
);
1005 if (i
->saturate
) code
[0] |= 1 << 5;
1007 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 7;
1008 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 9;
1010 emitForm_S(i
, 0x80000008 | (subOp
<< 26), true);
1012 assert(!i
->src(0).mod
.neg());
1013 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 30;
1018 CodeEmitterNVC0::emitMINMAX(const Instruction
*i
)
1022 assert(i
->encSize
== 8);
1024 op
= (i
->op
== OP_MIN
) ? 0x080e000000000000ULL
: 0x081e000000000000ULL
;
1029 if (!isFloatType(i
->dType
)) {
1030 op
|= isSignedType(i
->dType
) ? 0x23 : 0x03;
1031 op
|= i
->subOp
<< 6;
1033 if (i
->dType
== TYPE_F64
)
1039 if (i
->flagsDef
>= 0)
1044 CodeEmitterNVC0::roundMode_C(const Instruction
*i
)
1047 case ROUND_M
: code
[1] |= 1 << 17; break;
1048 case ROUND_P
: code
[1] |= 2 << 17; break;
1049 case ROUND_Z
: code
[1] |= 3 << 17; break;
1050 case ROUND_NI
: code
[0] |= 1 << 7; break;
1051 case ROUND_MI
: code
[0] |= 1 << 7; code
[1] |= 1 << 17; break;
1052 case ROUND_PI
: code
[0] |= 1 << 7; code
[1] |= 2 << 17; break;
1053 case ROUND_ZI
: code
[0] |= 1 << 7; code
[1] |= 3 << 17; break;
1054 case ROUND_N
: break;
1056 assert(!"invalid round mode");
1062 CodeEmitterNVC0::roundMode_CS(const Instruction
*i
)
1066 case ROUND_MI
: code
[0] |= 1 << 16; break;
1068 case ROUND_PI
: code
[0] |= 2 << 16; break;
1070 case ROUND_ZI
: code
[0] |= 3 << 16; break;
1077 CodeEmitterNVC0::emitCVT(Instruction
*i
)
1079 const bool f2f
= isFloatType(i
->dType
) && isFloatType(i
->sType
);
1083 case OP_CEIL
: i
->rnd
= f2f
? ROUND_PI
: ROUND_P
; break;
1084 case OP_FLOOR
: i
->rnd
= f2f
? ROUND_MI
: ROUND_M
; break;
1085 case OP_TRUNC
: i
->rnd
= f2f
? ROUND_ZI
: ROUND_Z
; break;
1090 const bool sat
= (i
->op
== OP_SAT
) || i
->saturate
;
1091 const bool abs
= (i
->op
== OP_ABS
) || i
->src(0).mod
.abs();
1092 const bool neg
= (i
->op
== OP_NEG
) || i
->src(0).mod
.neg();
1094 if (i
->op
== OP_NEG
&& i
->dType
== TYPE_U32
)
1099 if (i
->encSize
== 8) {
1100 emitForm_B(i
, HEX64(10000000, 00000004));
1104 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1105 code
[0] |= util_logbase2(typeSizeof(dType
)) << 20;
1106 code
[0] |= util_logbase2(typeSizeof(i
->sType
)) << 23;
1108 // for 8/16 source types, the byte/word is in subOp. word 1 is
1109 // represented as 2.
1110 if (!isFloatType(i
->sType
))
1111 code
[1] |= i
->subOp
<< 0x17;
1113 code
[1] |= i
->subOp
<< 0x18;
1119 if (neg
&& i
->op
!= OP_ABS
)
1125 if (isSignedIntType(dType
))
1127 if (isSignedIntType(i
->sType
))
1130 if (isFloatType(dType
)) {
1131 if (!isFloatType(i
->sType
))
1132 code
[1] |= 0x08000000;
1134 if (isFloatType(i
->sType
))
1135 code
[1] |= 0x04000000;
1137 code
[1] |= 0x0c000000;
1140 if (i
->op
== OP_CEIL
|| i
->op
== OP_FLOOR
|| i
->op
== OP_TRUNC
) {
1143 if (isFloatType(dType
)) {
1144 if (isFloatType(i
->sType
))
1147 code
[0] = 0x088 | (isSignedType(i
->sType
) ? (1 << 8) : 0);
1149 assert(isFloatType(i
->sType
));
1151 code
[0] = 0x288 | (isSignedType(i
->sType
) ? (1 << 8) : 0);
1154 if (neg
) code
[0] |= 1 << 16;
1155 if (sat
) code
[0] |= 1 << 18;
1156 if (abs
) code
[0] |= 1 << 19;
1163 CodeEmitterNVC0::emitSET(const CmpInstruction
*i
)
1168 if (i
->sType
== TYPE_F64
)
1171 if (!isFloatType(i
->sType
))
1174 if (isSignedIntType(i
->sType
))
1176 if (isFloatType(i
->dType
)) {
1177 if (isFloatType(i
->sType
))
1184 case OP_SET_AND
: hi
= 0x10000000; break;
1185 case OP_SET_OR
: hi
= 0x10200000; break;
1186 case OP_SET_XOR
: hi
= 0x10400000; break;
1191 emitForm_A(i
, (static_cast<uint64_t>(hi
) << 32) | lo
);
1193 if (i
->op
!= OP_SET
)
1194 srcId(i
->src(2), 32 + 17);
1196 if (i
->def(0).getFile() == FILE_PREDICATE
) {
1197 if (i
->sType
== TYPE_F32
)
1198 code
[1] += 0x10000000;
1200 code
[1] += 0x08000000;
1202 code
[0] &= ~0xfc000;
1203 defId(i
->def(0), 17);
1204 if (i
->defExists(1))
1205 defId(i
->def(1), 14);
1212 if (i
->flagsSrc
>= 0)
1215 emitCondCode(i
->setCond
, 32 + 23);
1220 CodeEmitterNVC0::emitSLCT(const CmpInstruction
*i
)
1226 op
= HEX64(30000000, 00000023);
1229 op
= HEX64(30000000, 00000003);
1232 op
= HEX64(38000000, 00000000);
1235 assert(!"invalid type for SLCT");
1241 CondCode cc
= i
->setCond
;
1243 if (i
->src(2).mod
.neg())
1244 cc
= reverseCondCode(cc
);
1246 emitCondCode(cc
, 32 + 23);
1253 selpFlip(const FixupEntry
*entry
, uint32_t *code
, const FixupData
& data
)
1255 int loc
= entry
->loc
;
1256 if (data
.force_persample_interp
)
1257 code
[loc
+ 1] |= 1 << 20;
1259 code
[loc
+ 1] &= ~(1 << 20);
1262 void CodeEmitterNVC0::emitSELP(const Instruction
*i
)
1264 emitForm_A(i
, HEX64(20000000, 00000004));
1266 if (i
->src(2).mod
& Modifier(NV50_IR_MOD_NOT
))
1269 if (i
->subOp
== 1) {
1270 addInterp(0, 0, selpFlip
);
1274 void CodeEmitterNVC0::emitTEXBAR(const Instruction
*i
)
1276 code
[0] = 0x00000006 | (i
->subOp
<< 26);
1277 code
[1] = 0xf0000000;
1279 emitCondCode(i
->flagsSrc
>= 0 ? i
->cc
: CC_ALWAYS
, 5);
1282 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction
*i
)
1284 code
[0] = 0x00000086;
1285 code
[1] = 0xd0000000;
1287 code
[1] |= i
->tex
.r
;
1288 code
[1] |= i
->tex
.s
<< 8;
1290 if (i
->tex
.liveOnly
)
1293 defId(i
->def(0), 14);
1294 srcId(i
->src(0), 20);
1298 isNextIndependentTex(const TexInstruction
*i
)
1300 if (!i
->next
|| !isTextureOp(i
->next
->op
))
1302 if (i
->getDef(0)->interfers(i
->next
->getSrc(0)))
1304 return !i
->next
->srcExists(1) || !i
->getDef(0)->interfers(i
->next
->getSrc(1));
1308 CodeEmitterNVC0::emitTEX(const TexInstruction
*i
)
1310 code
[0] = 0x00000006;
1312 if (isNextIndependentTex(i
))
1313 code
[0] |= 0x080; // t mode
1315 code
[0] |= 0x100; // p mode
1317 if (i
->tex
.liveOnly
)
1321 case OP_TEX
: code
[1] = 0x80000000; break;
1322 case OP_TXB
: code
[1] = 0x84000000; break;
1323 case OP_TXL
: code
[1] = 0x86000000; break;
1324 case OP_TXF
: code
[1] = 0x90000000; break;
1325 case OP_TXG
: code
[1] = 0xa0000000; break;
1326 case OP_TXLQ
: code
[1] = 0xb0000000; break;
1327 case OP_TXD
: code
[1] = 0xe0000000; break;
1329 assert(!"invalid texture op");
1332 if (i
->op
== OP_TXF
) {
1333 if (!i
->tex
.levelZero
)
1334 code
[1] |= 0x02000000;
1336 if (i
->tex
.levelZero
) {
1337 code
[1] |= 0x02000000;
1340 if (i
->op
!= OP_TXD
&& i
->tex
.derivAll
)
1343 defId(i
->def(0), 14);
1344 srcId(i
->src(0), 20);
1348 if (i
->op
== OP_TXG
) code
[0] |= i
->tex
.gatherComp
<< 5;
1350 code
[1] |= i
->tex
.mask
<< 14;
1352 code
[1] |= i
->tex
.r
;
1353 code
[1] |= i
->tex
.s
<< 8;
1354 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0)
1355 code
[1] |= 1 << 18; // in 1st source (with array index)
1358 code
[1] |= (i
->tex
.target
.getDim() - 1) << 20;
1359 if (i
->tex
.target
.isCube())
1361 if (i
->tex
.target
.isArray())
1363 if (i
->tex
.target
.isShadow())
1366 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1368 if (i
->srcExists(src1
) && i
->src(src1
).getFile() == FILE_IMMEDIATE
) {
1370 if (i
->op
== OP_TXL
)
1371 code
[1] &= ~(1 << 26);
1373 if (i
->op
== OP_TXF
)
1374 code
[1] &= ~(1 << 25);
1376 if (i
->tex
.target
== TEX_TARGET_2D_MS
||
1377 i
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1380 if (i
->tex
.useOffsets
== 1)
1382 if (i
->tex
.useOffsets
== 4)
1389 CodeEmitterNVC0::emitTXQ(const TexInstruction
*i
)
1391 code
[0] = 0x00000086;
1392 code
[1] = 0xc0000000;
1394 switch (i
->tex
.query
) {
1395 case TXQ_DIMS
: code
[1] |= 0 << 22; break;
1396 case TXQ_TYPE
: code
[1] |= 1 << 22; break;
1397 case TXQ_SAMPLE_POSITION
: code
[1] |= 2 << 22; break;
1398 case TXQ_FILTER
: code
[1] |= 3 << 22; break;
1399 case TXQ_LOD
: code
[1] |= 4 << 22; break;
1400 case TXQ_BORDER_COLOUR
: code
[1] |= 5 << 22; break;
1402 assert(!"invalid texture query");
1406 code
[1] |= i
->tex
.mask
<< 14;
1408 code
[1] |= i
->tex
.r
;
1409 code
[1] |= i
->tex
.s
<< 8;
1410 if (i
->tex
.sIndirectSrc
>= 0 || i
->tex
.rIndirectSrc
>= 0)
1413 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1415 defId(i
->def(0), 14);
1416 srcId(i
->src(0), 20);
1423 CodeEmitterNVC0::emitQUADOP(const Instruction
*i
, uint8_t qOp
, uint8_t laneMask
)
1425 code
[0] = 0x00000200 | (laneMask
<< 6); // dall
1426 code
[1] = 0x48000000 | qOp
;
1428 defId(i
->def(0), 14);
1429 srcId(i
->src(0), 20);
1430 srcId((i
->srcExists(1) && i
->predSrc
!= 1) ? i
->src(1) : i
->src(0), 26);
1436 CodeEmitterNVC0::emitFlow(const Instruction
*i
)
1438 const FlowInstruction
*f
= i
->asFlow();
1440 unsigned mask
; // bit 0: predicate, bit 1: target
1442 code
[0] = 0x00000007;
1446 code
[1] = f
->absolute
? 0x00000000 : 0x40000000;
1447 if (i
->srcExists(0) && i
->src(0).getFile() == FILE_MEMORY_CONST
)
1452 code
[1] = f
->absolute
? 0x10000000 : 0x50000000;
1454 code
[0] |= 0x4000; // indirect calls always use c[] source
1458 case OP_EXIT
: code
[1] = 0x80000000; mask
= 1; break;
1459 case OP_RET
: code
[1] = 0x90000000; mask
= 1; break;
1460 case OP_DISCARD
: code
[1] = 0x98000000; mask
= 1; break;
1461 case OP_BREAK
: code
[1] = 0xa8000000; mask
= 1; break;
1462 case OP_CONT
: code
[1] = 0xb0000000; mask
= 1; break;
1464 case OP_JOINAT
: code
[1] = 0x60000000; mask
= 2; break;
1465 case OP_PREBREAK
: code
[1] = 0x68000000; mask
= 2; break;
1466 case OP_PRECONT
: code
[1] = 0x70000000; mask
= 2; break;
1467 case OP_PRERET
: code
[1] = 0x78000000; mask
= 2; break;
1469 case OP_QUADON
: code
[1] = 0xc0000000; mask
= 0; break;
1470 case OP_QUADPOP
: code
[1] = 0xc8000000; mask
= 0; break;
1471 case OP_BRKPT
: code
[1] = 0xd0000000; mask
= 0; break;
1473 assert(!"invalid flow operation");
1479 if (i
->flagsSrc
< 0)
1492 if (code
[0] & 0x4000) {
1493 assert(i
->srcExists(0) && i
->src(0).getFile() == FILE_MEMORY_CONST
);
1494 setAddress16(i
->src(0));
1495 code
[1] |= i
->getSrc(0)->reg
.fileIndex
<< 10;
1496 if (f
->op
== OP_BRA
)
1497 srcId(f
->src(0).getIndirect(0), 20);
1503 if (f
->op
== OP_CALL
) {
1508 assert(f
->absolute
);
1509 uint32_t pcAbs
= targNVC0
->getBuiltinOffset(f
->target
.builtin
);
1510 addReloc(RelocEntry::TYPE_BUILTIN
, 0, pcAbs
, 0xfc000000, 26);
1511 addReloc(RelocEntry::TYPE_BUILTIN
, 1, pcAbs
, 0x03ffffff, -6);
1513 assert(!f
->absolute
);
1514 int32_t pcRel
= f
->target
.fn
->binPos
- (codeSize
+ 8);
1515 code
[0] |= (pcRel
& 0x3f) << 26;
1516 code
[1] |= (pcRel
>> 6) & 0x3ffff;
1520 int32_t pcRel
= f
->target
.bb
->binPos
- (codeSize
+ 8);
1521 if (writeIssueDelays
&& !(f
->target
.bb
->binPos
& 0x3f))
1523 // currently we don't want absolute branches
1524 assert(!f
->absolute
);
1525 code
[0] |= (pcRel
& 0x3f) << 26;
1526 code
[1] |= (pcRel
>> 6) & 0x3ffff;
1531 CodeEmitterNVC0::emitBAR(const Instruction
*i
)
1533 Value
*rDef
= NULL
, *pDef
= NULL
;
1536 case NV50_IR_SUBOP_BAR_ARRIVE
: code
[0] = 0x84; break;
1537 case NV50_IR_SUBOP_BAR_RED_AND
: code
[0] = 0x24; break;
1538 case NV50_IR_SUBOP_BAR_RED_OR
: code
[0] = 0x44; break;
1539 case NV50_IR_SUBOP_BAR_RED_POPC
: code
[0] = 0x04; break;
1542 assert(i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
);
1545 code
[1] = 0x50000000;
1547 code
[0] |= 63 << 14;
1553 if (i
->src(0).getFile() == FILE_GPR
) {
1554 srcId(i
->src(0), 20);
1556 ImmediateValue
*imm
= i
->getSrc(0)->asImm();
1558 code
[0] |= imm
->reg
.data
.u32
<< 20;
1563 if (i
->src(1).getFile() == FILE_GPR
) {
1564 srcId(i
->src(1), 26);
1566 ImmediateValue
*imm
= i
->getSrc(1)->asImm();
1568 assert(imm
->reg
.data
.u32
<= 0xfff);
1569 code
[0] |= imm
->reg
.data
.u32
<< 26;
1570 code
[1] |= imm
->reg
.data
.u32
>> 6;
1574 if (i
->srcExists(2) && (i
->predSrc
!= 2)) {
1575 srcId(i
->src(2), 32 + 17);
1576 if (i
->src(2).mod
== Modifier(NV50_IR_MOD_NOT
))
1582 if (i
->defExists(0)) {
1583 if (i
->def(0).getFile() == FILE_GPR
)
1584 rDef
= i
->getDef(0);
1586 pDef
= i
->getDef(0);
1588 if (i
->defExists(1)) {
1589 if (i
->def(1).getFile() == FILE_GPR
)
1590 rDef
= i
->getDef(1);
1592 pDef
= i
->getDef(1);
1596 code
[0] &= ~(63 << 14);
1600 code
[1] &= ~(7 << 21);
1601 defId(pDef
, 32 + 21);
1606 CodeEmitterNVC0::emitAFETCH(const Instruction
*i
)
1608 code
[0] = 0x00000006;
1609 code
[1] = 0x0c000000 | (i
->src(0).get()->reg
.data
.offset
& 0x7ff);
1611 if (i
->getSrc(0)->reg
.file
== FILE_SHADER_OUTPUT
)
1616 defId(i
->def(0), 14);
1617 srcId(i
->src(0).getIndirect(0), 20);
1621 CodeEmitterNVC0::emitPFETCH(const Instruction
*i
)
1623 uint32_t prim
= i
->src(0).get()->reg
.data
.u32
;
1625 code
[0] = 0x00000006 | ((prim
& 0x3f) << 26);
1626 code
[1] = 0x00000000 | (prim
>> 6);
1630 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1632 defId(i
->def(0), 14);
1637 CodeEmitterNVC0::emitVFETCH(const Instruction
*i
)
1639 code
[0] = 0x00000006;
1640 code
[1] = 0x06000000 | i
->src(0).get()->reg
.data
.offset
;
1644 if (i
->getSrc(0)->reg
.file
== FILE_SHADER_OUTPUT
)
1645 code
[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1649 code
[0] |= ((i
->getDef(0)->reg
.size
/ 4) - 1) << 5;
1651 defId(i
->def(0), 14);
1652 srcId(i
->src(0).getIndirect(0), 20);
1653 srcId(i
->src(0).getIndirect(1), 26); // vertex address
1657 CodeEmitterNVC0::emitEXPORT(const Instruction
*i
)
1659 unsigned int size
= typeSizeof(i
->dType
);
1661 code
[0] = 0x00000006 | ((size
/ 4 - 1) << 5);
1662 code
[1] = 0x0a000000 | i
->src(0).get()->reg
.data
.offset
;
1664 assert(!(code
[1] & ((size
== 12) ? 15 : (size
- 1))));
1671 assert(i
->src(1).getFile() == FILE_GPR
);
1673 srcId(i
->src(0).getIndirect(0), 20);
1674 srcId(i
->src(0).getIndirect(1), 32 + 17); // vertex base address
1675 srcId(i
->src(1), 26);
1679 CodeEmitterNVC0::emitOUT(const Instruction
*i
)
1681 code
[0] = 0x00000006;
1682 code
[1] = 0x1c000000;
1686 defId(i
->def(0), 14); // new secret address
1687 srcId(i
->src(0), 20); // old secret address, should be 0 initially
1689 assert(i
->src(0).getFile() == FILE_GPR
);
1691 if (i
->op
== OP_EMIT
)
1693 if (i
->op
== OP_RESTART
|| i
->subOp
== NV50_IR_SUBOP_EMIT_RESTART
)
1697 if (i
->src(1).getFile() == FILE_IMMEDIATE
) {
1698 unsigned int stream
= SDATA(i
->src(1)).u32
;
1702 code
[0] |= stream
<< 26;
1707 srcId(i
->src(1), 26);
1712 CodeEmitterNVC0::emitInterpMode(const Instruction
*i
)
1714 if (i
->encSize
== 8) {
1715 code
[0] |= i
->ipa
<< 6; // TODO: INTERP_SAMPLEID
1717 if (i
->getInterpMode() == NV50_IR_INTERP_SC
)
1719 assert(i
->op
== OP_PINTERP
&& i
->getSampleMode() == 0);
1724 interpApply(const FixupEntry
*entry
, uint32_t *code
, const FixupData
& data
)
1726 int ipa
= entry
->ipa
;
1727 int reg
= entry
->reg
;
1728 int loc
= entry
->loc
;
1730 if (data
.flatshade
&&
1731 (ipa
& NV50_IR_INTERP_MODE_MASK
) == NV50_IR_INTERP_SC
) {
1732 ipa
= NV50_IR_INTERP_FLAT
;
1734 } else if (data
.force_persample_interp
&&
1735 (ipa
& NV50_IR_INTERP_SAMPLE_MASK
) == NV50_IR_INTERP_DEFAULT
&&
1736 (ipa
& NV50_IR_INTERP_MODE_MASK
) != NV50_IR_INTERP_FLAT
) {
1737 ipa
|= NV50_IR_INTERP_CENTROID
;
1739 code
[loc
+ 0] &= ~(0xf << 6);
1740 code
[loc
+ 0] |= ipa
<< 6;
1741 code
[loc
+ 0] &= ~(0x3f << 26);
1742 code
[loc
+ 0] |= reg
<< 26;
1746 CodeEmitterNVC0::emitINTERP(const Instruction
*i
)
1748 const uint32_t base
= i
->getSrc(0)->reg
.data
.offset
;
1750 if (i
->encSize
== 8) {
1751 code
[0] = 0x00000000;
1752 code
[1] = 0xc0000000 | (base
& 0xffff);
1757 if (i
->op
== OP_PINTERP
) {
1758 srcId(i
->src(1), 26);
1759 addInterp(i
->ipa
, SDATA(i
->src(1)).id
, interpApply
);
1761 code
[0] |= 0x3f << 26;
1762 addInterp(i
->ipa
, 0x3f, interpApply
);
1765 srcId(i
->src(0).getIndirect(0), 20);
1767 assert(i
->op
== OP_PINTERP
);
1768 code
[0] = 0x00000009 | ((base
& 0xc) << 6) | ((base
>> 4) << 26);
1769 srcId(i
->src(1), 20);
1774 defId(i
->def(0), 14);
1776 if (i
->getSampleMode() == NV50_IR_INTERP_OFFSET
)
1777 srcId(i
->src(i
->op
== OP_PINTERP
? 2 : 1), 32 + 17);
1779 code
[1] |= 0x3f << 17;
1783 CodeEmitterNVC0::emitLoadStoreType(DataType ty
)
1816 assert(!"invalid type");
1823 CodeEmitterNVC0::emitCachingMode(CacheMode c
)
1844 assert(!"invalid caching mode");
1851 uses64bitAddress(const Instruction
*ldst
)
1853 return ldst
->src(0).getFile() == FILE_MEMORY_GLOBAL
&&
1854 ldst
->src(0).isIndirect(0) &&
1855 ldst
->getIndirect(0, 0)->reg
.size
== 8;
1859 CodeEmitterNVC0::emitSTORE(const Instruction
*i
)
1863 switch (i
->src(0).getFile()) {
1864 case FILE_MEMORY_GLOBAL
: opc
= 0x90000000; break;
1865 case FILE_MEMORY_LOCAL
: opc
= 0xc8000000; break;
1866 case FILE_MEMORY_SHARED
:
1867 if (i
->subOp
== NV50_IR_SUBOP_STORE_UNLOCKED
) {
1868 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1877 assert(!"invalid memory file");
1881 code
[0] = 0x00000005;
1884 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
) {
1885 // Unlocked store on shared memory can fail.
1886 if (i
->src(0).getFile() == FILE_MEMORY_SHARED
&&
1887 i
->subOp
== NV50_IR_SUBOP_STORE_UNLOCKED
) {
1888 assert(i
->defExists(0));
1893 setAddressByFile(i
->src(0));
1894 srcId(i
->src(1), 14);
1895 srcId(i
->src(0).getIndirect(0), 20);
1896 if (uses64bitAddress(i
))
1901 emitLoadStoreType(i
->dType
);
1902 emitCachingMode(i
->cache
);
1906 CodeEmitterNVC0::emitLOAD(const Instruction
*i
)
1910 code
[0] = 0x00000005;
1912 switch (i
->src(0).getFile()) {
1913 case FILE_MEMORY_GLOBAL
: opc
= 0x80000000; break;
1914 case FILE_MEMORY_LOCAL
: opc
= 0xc0000000; break;
1915 case FILE_MEMORY_SHARED
:
1916 if (i
->subOp
== NV50_IR_SUBOP_LOAD_LOCKED
) {
1917 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1925 case FILE_MEMORY_CONST
:
1926 if (!i
->src(0).isIndirect(0) && typeSizeof(i
->dType
) == 4) {
1927 emitMOV(i
); // not sure if this is any better
1930 opc
= 0x14000000 | (i
->src(0).get()->reg
.fileIndex
<< 10);
1931 code
[0] = 0x00000006 | (i
->subOp
<< 8);
1934 assert(!"invalid memory file");
1941 if (i
->src(0).getFile() == FILE_MEMORY_SHARED
) {
1942 if (i
->subOp
== NV50_IR_SUBOP_LOAD_LOCKED
) {
1943 if (i
->def(0).getFile() == FILE_PREDICATE
) { // p, #
1946 } else if (i
->defExists(1)) { // r, p
1949 assert(!"Expected predicate dest for load locked");
1955 defId(i
->def(r
), 14);
1957 code
[0] |= 63 << 14;
1960 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
1963 defId(i
->def(p
), 32 + 18);
1966 setAddressByFile(i
->src(0));
1967 srcId(i
->src(0).getIndirect(0), 20);
1968 if (uses64bitAddress(i
))
1973 emitLoadStoreType(i
->dType
);
1974 emitCachingMode(i
->cache
);
1978 CodeEmitterNVC0::getSRegEncoding(const ValueRef
& ref
)
1980 switch (SDATA(ref
).sv
.sv
) {
1981 case SV_LANEID
: return 0x00;
1982 case SV_PHYSID
: return 0x03;
1983 case SV_VERTEX_COUNT
: return 0x10;
1984 case SV_INVOCATION_ID
: return 0x11;
1985 case SV_YDIR
: return 0x12;
1986 case SV_THREAD_KILL
: return 0x13;
1987 case SV_TID
: return 0x21 + SDATA(ref
).sv
.index
;
1988 case SV_CTAID
: return 0x25 + SDATA(ref
).sv
.index
;
1989 case SV_NTID
: return 0x29 + SDATA(ref
).sv
.index
;
1990 case SV_GRIDID
: return 0x2c;
1991 case SV_NCTAID
: return 0x2d + SDATA(ref
).sv
.index
;
1992 case SV_LBASE
: return 0x34;
1993 case SV_SBASE
: return 0x30;
1994 case SV_LANEMASK_EQ
: return 0x38;
1995 case SV_LANEMASK_LT
: return 0x39;
1996 case SV_LANEMASK_LE
: return 0x3a;
1997 case SV_LANEMASK_GT
: return 0x3b;
1998 case SV_LANEMASK_GE
: return 0x3c;
1999 case SV_CLOCK
: return 0x50 + SDATA(ref
).sv
.index
;
2001 assert(!"no sreg for system value");
2007 CodeEmitterNVC0::emitMOV(const Instruction
*i
)
2009 assert(!i
->saturate
);
2010 if (i
->def(0).getFile() == FILE_PREDICATE
) {
2011 if (i
->src(0).getFile() == FILE_GPR
) {
2012 code
[0] = 0xfc01c003;
2013 code
[1] = 0x1a8e0000;
2014 srcId(i
->src(0), 20);
2016 code
[0] = 0x0001c004;
2017 code
[1] = 0x0c0e0000;
2018 if (i
->src(0).getFile() == FILE_IMMEDIATE
) {
2020 if (!i
->getSrc(0)->reg
.data
.u32
)
2023 srcId(i
->src(0), 20);
2026 defId(i
->def(0), 17);
2029 if (i
->src(0).getFile() == FILE_SYSTEM_VALUE
) {
2030 uint8_t sr
= getSRegEncoding(i
->src(0));
2032 if (i
->encSize
== 8) {
2033 code
[0] = 0x00000004 | (sr
<< 26);
2034 code
[1] = 0x2c000000;
2036 code
[0] = 0x40000008 | (sr
<< 20);
2038 defId(i
->def(0), 14);
2042 if (i
->encSize
== 8) {
2045 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
2046 opc
= HEX64(18000000, 000001e2
);
2048 if (i
->src(0).getFile() == FILE_PREDICATE
)
2049 opc
= HEX64(080e0000
, 1c000004
);
2051 opc
= HEX64(28000000, 00000004);
2053 if (i
->src(0).getFile() != FILE_PREDICATE
)
2054 opc
|= i
->lanes
<< 5;
2058 // Explicitly emit the predicate source as emitForm_B skips it.
2059 if (i
->src(0).getFile() == FILE_PREDICATE
)
2060 srcId(i
->src(0), 20);
2064 if (i
->src(0).getFile() == FILE_IMMEDIATE
) {
2065 imm
= SDATA(i
->src(0)).u32
;
2066 if (imm
& 0xfff00000) {
2067 assert(!(imm
& 0x000fffff));
2068 code
[0] = 0x00000318 | imm
;
2070 assert(imm
< 0x800 || ((int32_t)imm
>= -0x800));
2071 code
[0] = 0x00000118 | (imm
<< 20);
2075 emitShortSrc2(i
->src(0));
2077 defId(i
->def(0), 14);
2084 CodeEmitterNVC0::emitATOM(const Instruction
*i
)
2086 const bool hasDst
= i
->defExists(0);
2087 const bool casOrExch
=
2088 i
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
||
2089 i
->subOp
== NV50_IR_SUBOP_ATOM_CAS
;
2091 if (i
->dType
== TYPE_U64
) {
2093 case NV50_IR_SUBOP_ATOM_ADD
:
2096 code
[1] = 0x507e0000;
2098 code
[1] = 0x10000000;
2100 case NV50_IR_SUBOP_ATOM_EXCH
:
2102 code
[1] = 0x507e0000;
2104 case NV50_IR_SUBOP_ATOM_CAS
:
2106 code
[1] = 0x50000000;
2109 assert(!"invalid u64 red op");
2113 if (i
->dType
== TYPE_U32
) {
2115 case NV50_IR_SUBOP_ATOM_EXCH
:
2117 code
[1] = 0x507e0000;
2119 case NV50_IR_SUBOP_ATOM_CAS
:
2121 code
[1] = 0x50000000;
2124 code
[0] = 0x5 | (i
->subOp
<< 5);
2126 code
[1] = 0x507e0000;
2128 code
[1] = 0x10000000;
2132 if (i
->dType
== TYPE_S32
) {
2133 assert(i
->subOp
<= 2);
2134 code
[0] = 0x205 | (i
->subOp
<< 5);
2136 code
[1] = 0x587e0000;
2138 code
[1] = 0x18000000;
2140 if (i
->dType
== TYPE_F32
) {
2141 assert(i
->subOp
== NV50_IR_SUBOP_ATOM_ADD
);
2144 code
[1] = 0x687e0000;
2146 code
[1] = 0x28000000;
2151 srcId(i
->src(1), 14);
2154 defId(i
->def(0), 32 + 11);
2157 code
[1] |= 63 << 11;
2159 if (hasDst
|| casOrExch
) {
2160 const int32_t offset
= SDATA(i
->src(0)).offset
;
2161 assert(offset
< 0x80000 && offset
>= -0x80000);
2162 code
[0] |= offset
<< 26;
2163 code
[1] |= (offset
& 0x1ffc0) >> 6;
2164 code
[1] |= (offset
& 0xe0000) << 6;
2166 srcAddr32(i
->src(0), 26, 0);
2168 if (i
->getIndirect(0, 0)) {
2169 srcId(i
->getIndirect(0, 0), 20);
2170 if (i
->getIndirect(0, 0)->reg
.size
== 8)
2173 code
[0] |= 63 << 20;
2176 if (i
->subOp
== NV50_IR_SUBOP_ATOM_CAS
) {
2177 assert(i
->src(1).getSize() == 2 * typeSizeof(i
->sType
));
2178 code
[1] |= (SDATA(i
->src(1)).id
+ 1) << 17;
2183 CodeEmitterNVC0::emitMEMBAR(const Instruction
*i
)
2185 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i
->subOp
)) {
2186 case NV50_IR_SUBOP_MEMBAR_CTA
: code
[0] = 0x05; break;
2187 case NV50_IR_SUBOP_MEMBAR_GL
: code
[0] = 0x25; break;
2190 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i
->subOp
) == NV50_IR_SUBOP_MEMBAR_SYS
);
2193 code
[1] = 0xe0000000;
2199 CodeEmitterNVC0::emitCCTL(const Instruction
*i
)
2201 code
[0] = 0x00000005 | (i
->subOp
<< 5);
2203 if (i
->src(0).getFile() == FILE_MEMORY_GLOBAL
) {
2204 code
[1] = 0x98000000;
2205 srcAddr32(i
->src(0), 28, 2);
2207 code
[1] = 0xd0000000;
2208 setAddress24(i
->src(0));
2210 if (uses64bitAddress(i
))
2212 srcId(i
->src(0).getIndirect(0), 20);
2220 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp
)
2223 switch (subOp
& ~NV50_IR_SUBOP_SUCLAMP_2D
) {
2224 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m
= 0; break;
2225 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m
= 1; break;
2226 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m
= 2; break;
2227 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m
= 3; break;
2228 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m
= 4; break;
2229 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m
= 5; break;
2230 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m
= 6; break;
2231 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m
= 7; break;
2232 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m
= 8; break;
2233 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m
= 9; break;
2234 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m
= 10; break;
2235 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m
= 11; break;
2236 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m
= 12; break;
2237 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m
= 13; break;
2238 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m
= 14; break;
2243 if (subOp
& NV50_IR_SUBOP_SUCLAMP_2D
)
2248 CodeEmitterNVC0::emitSUCalc(Instruction
*i
)
2250 ImmediateValue
*imm
= NULL
;
2253 if (i
->srcExists(2)) {
2254 imm
= i
->getSrc(2)->asImm();
2256 i
->setSrc(2, NULL
); // special case, make emitForm_A not assert
2260 case OP_SUCLAMP
: opc
= HEX64(58000000, 00000004); break;
2261 case OP_SUBFM
: opc
= HEX64(5c000000
, 00000004); break;
2262 case OP_SUEAU
: opc
= HEX64(60000000, 00000004); break;
2269 if (i
->op
== OP_SUCLAMP
) {
2270 if (i
->dType
== TYPE_S32
)
2272 emitSUCLAMPMode(i
->subOp
);
2275 if (i
->op
== OP_SUBFM
&& i
->subOp
== NV50_IR_SUBOP_SUBFM_3D
)
2278 if (i
->op
!= OP_SUEAU
) {
2279 if (i
->def(0).getFile() == FILE_PREDICATE
) { // p, #
2280 code
[0] |= 63 << 14;
2281 code
[1] |= i
->getDef(0)->reg
.data
.id
<< 23;
2283 if (i
->defExists(1)) { // r, p
2284 assert(i
->def(1).getFile() == FILE_PREDICATE
);
2285 code
[1] |= i
->getDef(1)->reg
.data
.id
<< 23;
2291 assert(i
->op
== OP_SUCLAMP
);
2293 code
[1] |= (imm
->reg
.data
.u32
& 0x3f) << 17; // sint6
2298 CodeEmitterNVC0::emitSUGType(DataType ty
)
2301 case TYPE_S32
: code
[1] |= 1 << 13; break;
2302 case TYPE_U8
: code
[1] |= 2 << 13; break;
2303 case TYPE_S8
: code
[1] |= 3 << 13; break;
2305 assert(ty
== TYPE_U32
);
2311 CodeEmitterNVC0::setSUConst16(const Instruction
*i
, const int s
)
2313 const uint32_t offset
= i
->getSrc(s
)->reg
.data
.offset
;
2315 assert(i
->src(s
).getFile() == FILE_MEMORY_CONST
);
2316 assert(offset
== (offset
& 0xfffc));
2319 code
[0] |= offset
<< 24;
2320 code
[1] |= offset
>> 8;
2321 code
[1] |= i
->getSrc(s
)->reg
.fileIndex
<< 8;
2325 CodeEmitterNVC0::setSUPred(const Instruction
*i
, const int s
)
2327 if (!i
->srcExists(s
) || (i
->predSrc
== s
)) {
2328 code
[1] |= 0x7 << 17;
2330 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_NOT
))
2332 srcId(i
->src(s
), 32 + 17);
2337 CodeEmitterNVC0::emitSULDGB(const TexInstruction
*i
)
2340 code
[1] = 0xd4000000 | (i
->subOp
<< 15);
2342 emitLoadStoreType(i
->dType
);
2343 emitSUGType(i
->sType
);
2344 emitCachingMode(i
->cache
);
2347 defId(i
->def(0), 14); // destination
2348 srcId(i
->src(0), 20); // address
2350 if (i
->src(1).getFile() == FILE_GPR
)
2351 srcId(i
->src(1), 26);
2358 CodeEmitterNVC0::emitSUSTGx(const TexInstruction
*i
)
2361 code
[1] = 0xdc000000 | (i
->subOp
<< 15);
2363 if (i
->op
== OP_SUSTP
)
2364 code
[1] |= i
->tex
.mask
<< 22;
2366 emitLoadStoreType(i
->dType
);
2367 emitSUGType(i
->sType
);
2368 emitCachingMode(i
->cache
);
2371 srcId(i
->src(0), 20); // address
2373 if (i
->src(1).getFile() == FILE_GPR
)
2374 srcId(i
->src(1), 26);
2377 srcId(i
->src(3), 14); // values
2382 CodeEmitterNVC0::emitSUAddr(const TexInstruction
*i
)
2384 assert(targ
->getChipset() < NVISA_GK104_CHIPSET
);
2386 if (i
->tex
.rIndirectSrc
< 0) {
2387 code
[1] |= 0x00004000;
2388 code
[0] |= i
->tex
.r
<< 26;
2390 srcId(i
, i
->tex
.rIndirectSrc
, 26);
2395 CodeEmitterNVC0::emitSUDim(const TexInstruction
*i
)
2397 assert(targ
->getChipset() < NVISA_GK104_CHIPSET
);
2399 code
[1] |= (i
->tex
.target
.getDim() - 1) << 12;
2400 if (i
->tex
.target
.isArray() || i
->tex
.target
.isCube() ||
2401 i
->tex
.target
.getDim() == 3) {
2402 // use e2d mode for 3-dim images, arrays and cubes.
2406 srcId(i
->src(0), 20);
2410 CodeEmitterNVC0::emitSULEA(const TexInstruction
*i
)
2412 assert(targ
->getChipset() < NVISA_GK104_CHIPSET
);
2415 code
[1] = 0xf0000000;
2418 emitLoadStoreType(i
->sType
);
2420 defId(i
->def(0), 14);
2422 if (i
->defExists(1)) {
2423 defId(i
->def(1), 32 + 22);
2433 CodeEmitterNVC0::emitSULDB(const TexInstruction
*i
)
2435 assert(targ
->getChipset() < NVISA_GK104_CHIPSET
);
2438 code
[1] = 0xd4000000 | (i
->subOp
<< 15);
2441 emitLoadStoreType(i
->dType
);
2443 defId(i
->def(0), 14);
2445 emitCachingMode(i
->cache
);
2451 CodeEmitterNVC0::emitSUSTx(const TexInstruction
*i
)
2453 assert(targ
->getChipset() < NVISA_GK104_CHIPSET
);
2456 code
[1] = 0xdc000000 | (i
->subOp
<< 15);
2458 if (i
->op
== OP_SUSTP
)
2459 code
[1] |= i
->tex
.mask
<< 17;
2461 emitLoadStoreType(i
->dType
);
2465 srcId(i
->src(1), 14);
2467 emitCachingMode(i
->cache
);
2473 CodeEmitterNVC0::emitVectorSubOp(const Instruction
*i
)
2475 switch (NV50_IR_SUBOP_Vn(i
->subOp
)) {
2477 code
[1] |= (i
->subOp
& 0x000f) << 12; // vsrc1
2478 code
[1] |= (i
->subOp
& 0x00e0) >> 5; // vsrc2
2479 code
[1] |= (i
->subOp
& 0x0100) << 7; // vsrc2
2480 code
[1] |= (i
->subOp
& 0x3c00) << 13; // vdst
2483 code
[1] |= (i
->subOp
& 0x000f) << 8; // v2src1
2484 code
[1] |= (i
->subOp
& 0x0010) << 11; // v2src1
2485 code
[1] |= (i
->subOp
& 0x01e0) >> 1; // v2src2
2486 code
[1] |= (i
->subOp
& 0x0200) << 6; // v2src2
2487 code
[1] |= (i
->subOp
& 0x3c00) << 2; // v4dst
2488 code
[1] |= (i
->mask
& 0x3) << 2;
2491 code
[1] |= (i
->subOp
& 0x000f) << 8; // v4src1
2492 code
[1] |= (i
->subOp
& 0x01e0) >> 1; // v4src2
2493 code
[1] |= (i
->subOp
& 0x3c00) << 2; // v4dst
2494 code
[1] |= (i
->mask
& 0x3) << 2;
2495 code
[1] |= (i
->mask
& 0xc) << 21;
2504 CodeEmitterNVC0::emitVSHL(const Instruction
*i
)
2508 switch (NV50_IR_SUBOP_Vn(i
->subOp
)) {
2509 case 0: opc
|= 0xe8ULL
<< 56; break;
2510 case 1: opc
|= 0xb4ULL
<< 56; break;
2511 case 2: opc
|= 0x94ULL
<< 56; break;
2516 if (NV50_IR_SUBOP_Vn(i
->subOp
) == 1) {
2517 if (isSignedType(i
->dType
)) opc
|= 1ULL << 0x2a;
2518 if (isSignedType(i
->sType
)) opc
|= (1 << 6) | (1 << 5);
2520 if (isSignedType(i
->dType
)) opc
|= 1ULL << 0x39;
2521 if (isSignedType(i
->sType
)) opc
|= 1 << 6;
2528 if (i
->flagsDef
>= 0)
2533 CodeEmitterNVC0::emitPIXLD(const Instruction
*i
)
2535 assert(i
->encSize
== 8);
2536 emitForm_A(i
, HEX64(10000000, 00000006));
2537 code
[0] |= i
->subOp
<< 5;
2538 code
[1] |= 0x00e00000;
2542 CodeEmitterNVC0::emitSHFL(const Instruction
*i
)
2544 const ImmediateValue
*imm
;
2546 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
);
2548 code
[0] = 0x00000005;
2549 code
[1] = 0x88000000 | (i
->subOp
<< 23);
2553 defId(i
->def(0), 14);
2554 srcId(i
->src(0), 20);
2556 switch (i
->src(1).getFile()) {
2558 srcId(i
->src(1), 26);
2560 case FILE_IMMEDIATE
:
2561 imm
= i
->getSrc(1)->asImm();
2562 assert(imm
&& imm
->reg
.data
.u32
< 0x20);
2563 code
[0] |= imm
->reg
.data
.u32
<< 26;
2567 assert(!"invalid src1 file");
2571 switch (i
->src(2).getFile()) {
2573 srcId(i
->src(2), 49);
2575 case FILE_IMMEDIATE
:
2576 imm
= i
->getSrc(2)->asImm();
2577 assert(imm
&& imm
->reg
.data
.u32
< 0x2000);
2578 code
[1] |= imm
->reg
.data
.u32
<< 10;
2582 assert(!"invalid src2 file");
2586 setPDSTL(i
, i
->defExists(1) ? 1 : -1);
2590 CodeEmitterNVC0::emitVOTE(const Instruction
*i
)
2592 const ImmediateValue
*imm
;
2595 code
[0] = 0x00000004 | (i
->subOp
<< 5);
2596 code
[1] = 0x48000000;
2601 for (int d
= 0; i
->defExists(d
); d
++) {
2602 if (i
->def(d
).getFile() == FILE_PREDICATE
) {
2605 defId(i
->def(d
), 32 + 22);
2606 } else if (i
->def(d
).getFile() == FILE_GPR
) {
2609 defId(i
->def(d
), 14);
2611 assert(!"Unhandled def");
2615 code
[0] |= 63 << 14;
2619 switch (i
->src(0).getFile()) {
2620 case FILE_PREDICATE
:
2621 if (i
->src(0).mod
== Modifier(NV50_IR_MOD_NOT
))
2623 srcId(i
->src(0), 20);
2625 case FILE_IMMEDIATE
:
2626 imm
= i
->getSrc(0)->asImm();
2628 u32
= imm
->reg
.data
.u32
;
2629 assert(u32
== 0 || u32
== 1);
2630 code
[0] |= (u32
== 1 ? 0x7 : 0xf) << 20;
2633 assert(!"Unhandled src");
2639 CodeEmitterNVC0::emitInstruction(Instruction
*insn
)
2641 unsigned int size
= insn
->encSize
;
2643 if (writeIssueDelays
&& !(codeSize
& 0x3f))
2646 if (!insn
->encSize
) {
2647 ERROR("skipping unencodable instruction: "); insn
->print();
2650 if (codeSize
+ size
> codeSizeLimit
) {
2651 ERROR("code emitter output buffer too small\n");
2655 if (writeIssueDelays
) {
2656 if (!(codeSize
& 0x3f)) {
2657 code
[0] = 0x00000007; // cf issue delay "instruction"
2658 code
[1] = 0x20000000;
2662 const unsigned int id
= (codeSize
& 0x3f) / 8 - 1;
2663 uint32_t *data
= code
- (id
* 2 + 2);
2665 data
[0] |= insn
->sched
<< (id
* 8 + 4);
2668 data
[0] |= insn
->sched
<< 28;
2669 data
[1] |= insn
->sched
>> 4;
2671 data
[1] |= insn
->sched
<< ((id
- 4) * 8 + 4);
2675 // assert that instructions with multiple defs don't corrupt registers
2676 for (int d
= 0; insn
->defExists(d
); ++d
)
2677 assert(insn
->asTex() || insn
->def(d
).rep()->reg
.data
.id
>= 0);
2714 if (insn
->dType
== TYPE_F64
)
2716 else if (isFloatType(insn
->dType
))
2722 if (insn
->dType
== TYPE_F64
)
2724 else if (isFloatType(insn
->dType
))
2731 if (insn
->dType
== TYPE_F64
)
2733 else if (isFloatType(insn
->dType
))
2748 emitLogicOp(insn
, 0);
2751 emitLogicOp(insn
, 1);
2754 emitLogicOp(insn
, 2);
2764 emitSET(insn
->asCmp());
2770 emitSLCT(insn
->asCmp());
2785 if (insn
->def(0).getFile() == FILE_PREDICATE
||
2786 insn
->src(0).getFile() == FILE_PREDICATE
)
2792 emitSFnOp(insn
, 5 + 2 * insn
->subOp
);
2795 emitSFnOp(insn
, 4 + 2 * insn
->subOp
);
2820 emitTEX(insn
->asTex());
2823 emitTXQ(insn
->asTex());
2837 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2838 emitSULDGB(insn
->asTex());
2840 emitSULDB(insn
->asTex());
2844 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2845 emitSUSTGx(insn
->asTex());
2847 emitSUSTx(insn
->asTex());
2850 emitSULEA(insn
->asTex());
2872 emitQUADOP(insn
, insn
->subOp
, insn
->lanes
);
2875 emitQUADOP(insn
, insn
->src(0).mod
.neg() ? 0x66 : 0x99, 0x4);
2878 emitQUADOP(insn
, insn
->src(0).mod
.neg() ? 0x5a : 0xa5, 0x5);
2923 ERROR("operation should have been eliminated");
2929 ERROR("operation should have been lowered\n");
2932 ERROR("unknown op: %u\n", insn
->op
);
2938 assert(insn
->encSize
== 8);
2941 code
+= insn
->encSize
/ 4;
2942 codeSize
+= insn
->encSize
;
2947 CodeEmitterNVC0::getMinEncodingSize(const Instruction
*i
) const
2949 const Target::OpInfo
&info
= targ
->getOpInfo(i
);
2951 if (writeIssueDelays
|| info
.minEncSize
== 8 || 1)
2954 if (i
->ftz
|| i
->saturate
|| i
->join
)
2956 if (i
->rnd
!= ROUND_N
)
2958 if (i
->predSrc
>= 0 && i
->op
== OP_MAD
)
2961 if (i
->op
== OP_PINTERP
) {
2962 if (i
->getSampleMode() || 1) // XXX: grr, short op doesn't work
2965 if (i
->op
== OP_MOV
&& i
->lanes
!= 0xf) {
2969 for (int s
= 0; i
->srcExists(s
); ++s
) {
2970 if (i
->src(s
).isIndirect(0))
2973 if (i
->src(s
).getFile() == FILE_MEMORY_CONST
) {
2974 if (SDATA(i
->src(s
)).offset
>= 0x100)
2976 if (i
->getSrc(s
)->reg
.fileIndex
> 1 &&
2977 i
->getSrc(s
)->reg
.fileIndex
!= 16)
2980 if (i
->src(s
).getFile() == FILE_IMMEDIATE
) {
2981 if (i
->dType
== TYPE_F32
) {
2982 if (SDATA(i
->src(s
)).u32
>= 0x100)
2985 if (SDATA(i
->src(s
)).u32
> 0xff)
2990 if (i
->op
== OP_CVT
)
2992 if (i
->src(s
).mod
!= Modifier(0)) {
2993 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_ABS
))
2994 if (i
->op
!= OP_RSQ
)
2996 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_NEG
))
2997 if (i
->op
!= OP_ADD
|| s
!= 0)
3005 // Simplified, erring on safe side.
3006 class SchedDataCalculator
: public Pass
3009 SchedDataCalculator(const Target
*targ
) : targ(targ
) { }
3015 int st
[DATA_FILE_COUNT
]; // LD to LD delay 3
3016 int ld
[DATA_FILE_COUNT
]; // ST to ST delay 3
3017 int tex
; // TEX to non-TEX delay 17 (0x11)
3018 int sfu
; // SFU to SFU delay 3 (except PRE-ops)
3019 int imul
; // integer MUL to MUL delay 3
3029 void rebase(const int base
)
3031 const int delta
= this->base
- base
;
3036 for (int i
= 0; i
< regs
; ++i
) {
3040 for (int i
= 0; i
< 8; ++i
) {
3047 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
3057 memset(&rd
, 0, sizeof(rd
));
3058 memset(&wr
, 0, sizeof(wr
));
3059 memset(&res
, 0, sizeof(res
));
3062 int getLatest(const ScoreData
& d
) const
3065 for (int i
= 0; i
< regs
; ++i
)
3068 for (int i
= 0; i
< 8; ++i
)
3075 inline int getLatestRd() const
3077 return getLatest(rd
);
3079 inline int getLatestWr() const
3081 return getLatest(wr
);
3083 inline int getLatest() const
3085 const int a
= getLatestRd();
3086 const int b
= getLatestWr();
3088 int max
= MAX2(a
, b
);
3089 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
3090 max
= MAX2(res
.ld
[f
], max
);
3091 max
= MAX2(res
.st
[f
], max
);
3093 max
= MAX2(res
.sfu
, max
);
3094 max
= MAX2(res
.imul
, max
);
3095 max
= MAX2(res
.tex
, max
);
3098 void setMax(const RegScores
*that
)
3100 for (int i
= 0; i
< regs
; ++i
) {
3101 rd
.r
[i
] = MAX2(rd
.r
[i
], that
->rd
.r
[i
]);
3102 wr
.r
[i
] = MAX2(wr
.r
[i
], that
->wr
.r
[i
]);
3104 for (int i
= 0; i
< 8; ++i
) {
3105 rd
.p
[i
] = MAX2(rd
.p
[i
], that
->rd
.p
[i
]);
3106 wr
.p
[i
] = MAX2(wr
.p
[i
], that
->wr
.p
[i
]);
3108 rd
.c
= MAX2(rd
.c
, that
->rd
.c
);
3109 wr
.c
= MAX2(wr
.c
, that
->wr
.c
);
3111 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
3112 res
.ld
[f
] = MAX2(res
.ld
[f
], that
->res
.ld
[f
]);
3113 res
.st
[f
] = MAX2(res
.st
[f
], that
->res
.st
[f
]);
3115 res
.sfu
= MAX2(res
.sfu
, that
->res
.sfu
);
3116 res
.imul
= MAX2(res
.imul
, that
->res
.imul
);
3117 res
.tex
= MAX2(res
.tex
, that
->res
.tex
);
3119 void print(int cycle
)
3121 for (int i
= 0; i
< regs
; ++i
) {
3122 if (rd
.r
[i
] > cycle
)
3123 INFO("rd $r%i @ %i\n", i
, rd
.r
[i
]);
3124 if (wr
.r
[i
] > cycle
)
3125 INFO("wr $r%i @ %i\n", i
, wr
.r
[i
]);
3127 for (int i
= 0; i
< 8; ++i
) {
3128 if (rd
.p
[i
] > cycle
)
3129 INFO("rd $p%i @ %i\n", i
, rd
.p
[i
]);
3130 if (wr
.p
[i
] > cycle
)
3131 INFO("wr $p%i @ %i\n", i
, wr
.p
[i
]);
3134 INFO("rd $c @ %i\n", rd
.c
);
3136 INFO("wr $c @ %i\n", wr
.c
);
3137 if (res
.sfu
> cycle
)
3138 INFO("sfu @ %i\n", res
.sfu
);
3139 if (res
.imul
> cycle
)
3140 INFO("imul @ %i\n", res
.imul
);
3141 if (res
.tex
> cycle
)
3142 INFO("tex @ %i\n", res
.tex
);
3146 RegScores
*score
; // for current BB
3147 std::vector
<RegScores
> scoreBoards
;
3153 bool visit(Function
*);
3154 bool visit(BasicBlock
*);
3156 void commitInsn(const Instruction
*, int cycle
);
3157 int calcDelay(const Instruction
*, int cycle
) const;
3158 void setDelay(Instruction
*, int delay
, Instruction
*next
);
3160 void recordRd(const Value
*, const int ready
);
3161 void recordWr(const Value
*, const int ready
);
3162 void checkRd(const Value
*, int cycle
, int& delay
) const;
3163 void checkWr(const Value
*, int cycle
, int& delay
) const;
3165 int getCycles(const Instruction
*, int origDelay
) const;
3169 SchedDataCalculator::setDelay(Instruction
*insn
, int delay
, Instruction
*next
)
3171 if (insn
->op
== OP_EXIT
|| insn
->op
== OP_RET
)
3172 delay
= MAX2(delay
, 14);
3174 if (insn
->op
== OP_TEXBAR
) {
3175 // TODO: except if results not used before EXIT
3178 if (insn
->op
== OP_JOIN
|| insn
->join
) {
3181 if (delay
>= 0 || prevData
== 0x04 ||
3182 !next
|| !targ
->canDualIssue(insn
, next
)) {
3183 insn
->sched
= static_cast<uint8_t>(MAX2(delay
, 0));
3184 if (prevOp
== OP_EXPORT
)
3185 insn
->sched
|= 0x40;
3187 insn
->sched
|= 0x20;
3189 insn
->sched
= 0x04; // dual-issue
3192 if (prevData
!= 0x04 || prevOp
!= OP_EXPORT
)
3193 if (insn
->sched
!= 0x04 || insn
->op
== OP_EXPORT
)
3196 prevData
= insn
->sched
;
3200 SchedDataCalculator::getCycles(const Instruction
*insn
, int origDelay
) const
3202 if (insn
->sched
& 0x80) {
3203 int c
= (insn
->sched
& 0x0f) * 2 + 1;
3204 if (insn
->op
== OP_TEXBAR
&& origDelay
> 0)
3208 if (insn
->sched
& 0x60)
3209 return (insn
->sched
& 0x1f) + 1;
3210 return (insn
->sched
== 0x04) ? 0 : 32;
3214 SchedDataCalculator::visit(Function
*func
)
3216 int regs
= targ
->getFileSize(FILE_GPR
) + 1;
3217 scoreBoards
.resize(func
->cfg
.getSize());
3218 for (size_t i
= 0; i
< scoreBoards
.size(); ++i
)
3219 scoreBoards
[i
].wipe(regs
);
3224 SchedDataCalculator::visit(BasicBlock
*bb
)
3227 Instruction
*next
= NULL
;
3233 score
= &scoreBoards
.at(bb
->getId());
3235 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
3236 // back branches will wait until all target dependencies are satisfied
3237 if (ei
.getType() == Graph::Edge::BACK
) // sched would be uninitialized
3239 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
3240 if (in
->getExit()) {
3241 if (prevData
!= 0x04)
3242 prevData
= in
->getExit()->sched
;
3243 prevOp
= in
->getExit()->op
;
3245 score
->setMax(&scoreBoards
.at(in
->getId()));
3247 if (bb
->cfg
.incidentCount() > 1)
3250 #ifdef NVC0_DEBUG_SCHED_DATA
3251 INFO("=== BB:%i initial scores\n", bb
->getId());
3252 score
->print(cycle
);
3255 for (insn
= bb
->getEntry(); insn
&& insn
->next
; insn
= insn
->next
) {
3258 commitInsn(insn
, cycle
);
3259 int delay
= calcDelay(next
, cycle
);
3260 setDelay(insn
, delay
, next
);
3261 cycle
+= getCycles(insn
, delay
);
3263 #ifdef NVC0_DEBUG_SCHED_DATA
3264 INFO("cycle %i, sched %02x\n", cycle
, insn
->sched
);
3271 commitInsn(insn
, cycle
);
3275 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
3276 BasicBlock
*out
= BasicBlock::get(ei
.getNode());
3278 if (ei
.getType() != Graph::Edge::BACK
) {
3279 // only test the first instruction of the outgoing block
3280 next
= out
->getEntry();
3282 bbDelay
= MAX2(bbDelay
, calcDelay(next
, cycle
));
3284 // wait until all dependencies are satisfied
3285 const int regsFree
= score
->getLatest();
3286 next
= out
->getFirst();
3287 for (int c
= cycle
; next
&& c
< regsFree
; next
= next
->next
) {
3288 bbDelay
= MAX2(bbDelay
, calcDelay(next
, c
));
3289 c
+= getCycles(next
, bbDelay
);
3294 if (bb
->cfg
.outgoingCount() != 1)
3296 setDelay(insn
, bbDelay
, next
);
3297 cycle
+= getCycles(insn
, bbDelay
);
3299 score
->rebase(cycle
); // common base for initializing out blocks' scores
3303 #define NVE4_MAX_ISSUE_DELAY 0x1f
3305 SchedDataCalculator::calcDelay(const Instruction
*insn
, int cycle
) const
3307 int delay
= 0, ready
= cycle
;
3309 for (int s
= 0; insn
->srcExists(s
); ++s
)
3310 checkRd(insn
->getSrc(s
), cycle
, delay
);
3311 // WAR & WAW don't seem to matter
3312 // for (int s = 0; insn->srcExists(s); ++s)
3313 // recordRd(insn->getSrc(s), cycle);
3315 switch (Target::getOpClass(insn
->op
)) {
3317 ready
= score
->res
.sfu
;
3320 if (insn
->op
== OP_MUL
&& !isFloatType(insn
->dType
))
3321 ready
= score
->res
.imul
;
3323 case OPCLASS_TEXTURE
:
3324 ready
= score
->res
.tex
;
3327 ready
= score
->res
.ld
[insn
->src(0).getFile()];
3330 ready
= score
->res
.st
[insn
->src(0).getFile()];
3335 if (Target::getOpClass(insn
->op
) != OPCLASS_TEXTURE
)
3336 ready
= MAX2(ready
, score
->res
.tex
);
3338 delay
= MAX2(delay
, ready
- cycle
);
3340 // if can issue next cycle, delay is 0, not 1
3341 return MIN2(delay
- 1, NVE4_MAX_ISSUE_DELAY
);
3345 SchedDataCalculator::commitInsn(const Instruction
*insn
, int cycle
)
3347 const int ready
= cycle
+ targ
->getLatency(insn
);
3349 for (int d
= 0; insn
->defExists(d
); ++d
)
3350 recordWr(insn
->getDef(d
), ready
);
3351 // WAR & WAW don't seem to matter
3352 // for (int s = 0; insn->srcExists(s); ++s)
3353 // recordRd(insn->getSrc(s), cycle);
3355 switch (Target::getOpClass(insn
->op
)) {
3357 score
->res
.sfu
= cycle
+ 4;
3360 if (insn
->op
== OP_MUL
&& !isFloatType(insn
->dType
))
3361 score
->res
.imul
= cycle
+ 4;
3363 case OPCLASS_TEXTURE
:
3364 score
->res
.tex
= cycle
+ 18;
3367 if (insn
->src(0).getFile() == FILE_MEMORY_CONST
)
3369 score
->res
.ld
[insn
->src(0).getFile()] = cycle
+ 4;
3370 score
->res
.st
[insn
->src(0).getFile()] = ready
;
3373 score
->res
.st
[insn
->src(0).getFile()] = cycle
+ 4;
3374 score
->res
.ld
[insn
->src(0).getFile()] = ready
;
3377 if (insn
->op
== OP_TEXBAR
)
3378 score
->res
.tex
= cycle
;
3384 #ifdef NVC0_DEBUG_SCHED_DATA
3385 score
->print(cycle
);
3390 SchedDataCalculator::checkRd(const Value
*v
, int cycle
, int& delay
) const
3395 switch (v
->reg
.file
) {
3398 b
= a
+ v
->reg
.size
/ 4;
3399 for (int r
= a
; r
< b
; ++r
)
3400 ready
= MAX2(ready
, score
->rd
.r
[r
]);
3402 case FILE_PREDICATE
:
3403 ready
= MAX2(ready
, score
->rd
.p
[v
->reg
.data
.id
]);
3406 ready
= MAX2(ready
, score
->rd
.c
);
3408 case FILE_SHADER_INPUT
:
3409 case FILE_SHADER_OUTPUT
: // yes, TCPs can read outputs
3410 case FILE_MEMORY_LOCAL
:
3411 case FILE_MEMORY_CONST
:
3412 case FILE_MEMORY_SHARED
:
3413 case FILE_MEMORY_GLOBAL
:
3414 case FILE_SYSTEM_VALUE
:
3415 // TODO: any restrictions here ?
3417 case FILE_IMMEDIATE
:
3424 delay
= MAX2(delay
, ready
- cycle
);
3428 SchedDataCalculator::checkWr(const Value
*v
, int cycle
, int& delay
) const
3433 switch (v
->reg
.file
) {
3436 b
= a
+ v
->reg
.size
/ 4;
3437 for (int r
= a
; r
< b
; ++r
)
3438 ready
= MAX2(ready
, score
->wr
.r
[r
]);
3440 case FILE_PREDICATE
:
3441 ready
= MAX2(ready
, score
->wr
.p
[v
->reg
.data
.id
]);
3444 assert(v
->reg
.file
== FILE_FLAGS
);
3445 ready
= MAX2(ready
, score
->wr
.c
);
3449 delay
= MAX2(delay
, ready
- cycle
);
3453 SchedDataCalculator::recordWr(const Value
*v
, const int ready
)
3455 int a
= v
->reg
.data
.id
;
3457 if (v
->reg
.file
== FILE_GPR
) {
3458 int b
= a
+ v
->reg
.size
/ 4;
3459 for (int r
= a
; r
< b
; ++r
)
3460 score
->rd
.r
[r
] = ready
;
3462 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3463 if (v
->reg
.file
== FILE_PREDICATE
) {
3464 score
->rd
.p
[a
] = ready
+ 4;
3466 assert(v
->reg
.file
== FILE_FLAGS
);
3467 score
->rd
.c
= ready
+ 4;
3472 SchedDataCalculator::recordRd(const Value
*v
, const int ready
)
3474 int a
= v
->reg
.data
.id
;
3476 if (v
->reg
.file
== FILE_GPR
) {
3477 int b
= a
+ v
->reg
.size
/ 4;
3478 for (int r
= a
; r
< b
; ++r
)
3479 score
->wr
.r
[r
] = ready
;
3481 if (v
->reg
.file
== FILE_PREDICATE
) {
3482 score
->wr
.p
[a
] = ready
;
3484 if (v
->reg
.file
== FILE_FLAGS
) {
3485 score
->wr
.c
= ready
;
3490 calculateSchedDataNVC0(const Target
*targ
, Function
*func
)
3492 SchedDataCalculator
sched(targ
);
3493 return sched
.run(func
, true, true);
3497 CodeEmitterNVC0::prepareEmission(Function
*func
)
3499 CodeEmitter::prepareEmission(func
);
3501 if (targ
->hasSWSched
)
3502 calculateSchedDataNVC0(targ
, func
);
3505 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0
*target
)
3506 : CodeEmitter(target
),
3508 writeIssueDelays(target
->hasSWSched
)
3511 codeSize
= codeSizeLimit
= 0;
3516 TargetNVC0::createCodeEmitterNVC0(Program::Type type
)
3518 CodeEmitterNVC0
*emit
= new CodeEmitterNVC0(this);
3519 emit
->setProgramType(type
);
3524 TargetNVC0::getCodeEmitter(Program::Type type
)
3526 if (chipset
>= NVISA_GK20A_CHIPSET
)
3527 return createCodeEmitterGK110(type
);
3528 return createCodeEmitterNVC0(type
);
3531 } // namespace nv50_ir