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nv50/ir: enable early fragment test with explicit user control
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitAFETCH(const Instruction *);
89 void emitPFETCH(const Instruction *);
90 void emitVFETCH(const Instruction *);
91 void emitEXPORT(const Instruction *);
92 void emitOUT(const Instruction *);
93
94 void emitUADD(const Instruction *);
95 void emitFADD(const Instruction *);
96 void emitDADD(const Instruction *);
97 void emitUMUL(const Instruction *);
98 void emitFMUL(const Instruction *);
99 void emitDMUL(const Instruction *);
100 void emitIMAD(const Instruction *);
101 void emitISAD(const Instruction *);
102 void emitFMAD(const Instruction *);
103 void emitDMAD(const Instruction *);
104 void emitMADSP(const Instruction *);
105
106 void emitNOT(Instruction *);
107 void emitLogicOp(const Instruction *, uint8_t subOp);
108 void emitPOPC(const Instruction *);
109 void emitINSBF(const Instruction *);
110 void emitEXTBF(const Instruction *);
111 void emitBFIND(const Instruction *);
112 void emitPERMT(const Instruction *);
113 void emitShift(const Instruction *);
114
115 void emitSFnOp(const Instruction *, uint8_t subOp);
116
117 void emitCVT(Instruction *);
118 void emitMINMAX(const Instruction *);
119 void emitPreOp(const Instruction *);
120
121 void emitSET(const CmpInstruction *);
122 void emitSLCT(const CmpInstruction *);
123 void emitSELP(const Instruction *);
124
125 void emitTEXBAR(const Instruction *);
126 void emitTEX(const TexInstruction *);
127 void emitTEXCSAA(const TexInstruction *);
128 void emitTXQ(const TexInstruction *);
129
130 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
131
132 void emitFlow(const Instruction *);
133 void emitBAR(const Instruction *);
134
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction *);
137 void emitSULDGB(const TexInstruction *);
138 void emitSUSTGx(const TexInstruction *);
139
140 void emitVSHL(const Instruction *);
141 void emitVectorSubOp(const Instruction *);
142
143 void emitPIXLD(const Instruction *);
144
145 void emitVOTE(const Instruction *);
146
147 inline void defId(const ValueDef&, const int pos);
148 inline void defId(const Instruction *, int d, const int pos);
149 inline void srcId(const ValueRef&, const int pos);
150 inline void srcId(const ValueRef *, const int pos);
151 inline void srcId(const Instruction *, int s, const int pos);
152 inline void srcAddr32(const ValueRef&, int pos, int shr);
153
154 inline bool isLIMM(const ValueRef&, DataType ty);
155 };
156
157 // for better visibility
158 #define HEX64(h, l) 0x##h##l##ULL
159
160 #define SDATA(a) ((a).rep()->reg.data)
161 #define DDATA(a) ((a).rep()->reg.data)
162
163 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
164 {
165 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
166 }
167
168 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
169 {
170 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
171 }
172
173 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
174 {
175 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
176 code[pos / 32] |= r << (pos % 32);
177 }
178
179 void
180 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
181 {
182 const uint32_t offset = SDATA(src).offset >> shr;
183
184 code[pos / 32] |= offset << (pos % 32);
185 if (pos && (pos < 32))
186 code[1] |= offset >> (32 - pos);
187 }
188
189 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
190 {
191 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
192 }
193
194 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
195 {
196 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
197 code[pos / 32] |= r << (pos % 32);
198 }
199
200 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
201 {
202 const ImmediateValue *imm = ref.get()->asImm();
203
204 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
205 }
206
207 void
208 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
209 {
210 switch (insn->rnd) {
211 case ROUND_M: code[1] |= 1 << 23; break;
212 case ROUND_P: code[1] |= 2 << 23; break;
213 case ROUND_Z: code[1] |= 3 << 23; break;
214 default:
215 assert(insn->rnd == ROUND_N);
216 break;
217 }
218 }
219
220 void
221 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
222 {
223 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
224 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
225 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
226 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
227 }
228
229 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
230 {
231 uint8_t val;
232
233 switch (cc) {
234 case CC_LT: val = 0x1; break;
235 case CC_LTU: val = 0x9; break;
236 case CC_EQ: val = 0x2; break;
237 case CC_EQU: val = 0xa; break;
238 case CC_LE: val = 0x3; break;
239 case CC_LEU: val = 0xb; break;
240 case CC_GT: val = 0x4; break;
241 case CC_GTU: val = 0xc; break;
242 case CC_NE: val = 0x5; break;
243 case CC_NEU: val = 0xd; break;
244 case CC_GE: val = 0x6; break;
245 case CC_GEU: val = 0xe; break;
246 case CC_TR: val = 0xf; break;
247 case CC_FL: val = 0x0; break;
248
249 case CC_A: val = 0x14; break;
250 case CC_NA: val = 0x13; break;
251 case CC_S: val = 0x15; break;
252 case CC_NS: val = 0x12; break;
253 case CC_C: val = 0x16; break;
254 case CC_NC: val = 0x11; break;
255 case CC_O: val = 0x17; break;
256 case CC_NO: val = 0x10; break;
257
258 default:
259 val = 0;
260 assert(!"invalid condition code");
261 break;
262 }
263 code[pos / 32] |= val << (pos % 32);
264 }
265
266 void
267 CodeEmitterNVC0::emitPredicate(const Instruction *i)
268 {
269 if (i->predSrc >= 0) {
270 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
271 srcId(i->src(i->predSrc), 10);
272 if (i->cc == CC_NOT_P)
273 code[0] |= 0x2000; // negate
274 } else {
275 code[0] |= 0x1c00;
276 }
277 }
278
279 void
280 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
281 {
282 switch (src.getFile()) {
283 case FILE_MEMORY_GLOBAL:
284 srcAddr32(src, 26, 0);
285 break;
286 case FILE_MEMORY_LOCAL:
287 case FILE_MEMORY_SHARED:
288 setAddress24(src);
289 break;
290 default:
291 assert(src.getFile() == FILE_MEMORY_CONST);
292 setAddress16(src);
293 break;
294 }
295 }
296
297 void
298 CodeEmitterNVC0::setAddress16(const ValueRef& src)
299 {
300 Symbol *sym = src.get()->asSym();
301
302 assert(sym);
303
304 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
305 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
306 }
307
308 void
309 CodeEmitterNVC0::setAddress24(const ValueRef& src)
310 {
311 Symbol *sym = src.get()->asSym();
312
313 assert(sym);
314
315 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
316 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
317 }
318
319 void
320 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
321 {
322 const ImmediateValue *imm = i->src(s).get()->asImm();
323 uint32_t u32;
324
325 assert(imm);
326 u32 = imm->reg.data.u32;
327
328 if ((code[0] & 0xf) == 0x1) {
329 // double immediate
330 uint64_t u64 = imm->reg.data.u64;
331 assert(!(u64 & 0x00000fffffffffffULL));
332 assert(!(code[1] & 0xc000));
333 code[0] |= ((u64 >> 44) & 0x3f) << 26;
334 code[1] |= 0xc000 | (u64 >> 50);
335 } else
336 if ((code[0] & 0xf) == 0x2) {
337 // LIMM
338 code[0] |= (u32 & 0x3f) << 26;
339 code[1] |= u32 >> 6;
340 } else
341 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
342 // integer immediate
343 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
344 assert(!(code[1] & 0xc000));
345 u32 &= 0xfffff;
346 code[0] |= (u32 & 0x3f) << 26;
347 code[1] |= 0xc000 | (u32 >> 6);
348 } else {
349 // float immediate
350 assert(!(u32 & 0x00000fff));
351 assert(!(code[1] & 0xc000));
352 code[0] |= ((u32 >> 12) & 0x3f) << 26;
353 code[1] |= 0xc000 | (u32 >> 18);
354 }
355 }
356
357 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
358 {
359 const ImmediateValue *imm = ref.get()->asImm();
360
361 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
362
363 assert(s8 == imm->reg.data.s32);
364
365 code[0] |= (s8 & 0x3f) << 26;
366 code[0] |= (s8 >> 6) << 8;
367 }
368
369 void
370 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
371 {
372 code[0] = opc;
373 code[1] = opc >> 32;
374
375 emitPredicate(i);
376
377 defId(i->def(0), 14);
378
379 int s1 = 26;
380 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
381 s1 = 49;
382
383 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
384 switch (i->getSrc(s)->reg.file) {
385 case FILE_MEMORY_CONST:
386 assert(!(code[1] & 0xc000));
387 code[1] |= (s == 2) ? 0x8000 : 0x4000;
388 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
389 setAddress16(i->src(s));
390 break;
391 case FILE_IMMEDIATE:
392 assert(s == 1 ||
393 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
394 assert(!(code[1] & 0xc000));
395 setImmediate(i, s);
396 break;
397 case FILE_GPR:
398 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
399 break;
400 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
401 break;
402 default:
403 if (i->op == OP_SELP) {
404 // OP_SELP is used to implement shared+atomics on Fermi.
405 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
406 srcId(i->src(s), 49);
407 }
408 // ignore here, can be predicate or flags, but must not be address
409 break;
410 }
411 }
412 }
413
414 void
415 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
416 {
417 code[0] = opc;
418 code[1] = opc >> 32;
419
420 emitPredicate(i);
421
422 defId(i->def(0), 14);
423
424 switch (i->src(0).getFile()) {
425 case FILE_MEMORY_CONST:
426 assert(!(code[1] & 0xc000));
427 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
428 setAddress16(i->src(0));
429 break;
430 case FILE_IMMEDIATE:
431 assert(!(code[1] & 0xc000));
432 setImmediate(i, 0);
433 break;
434 case FILE_GPR:
435 srcId(i->src(0), 26);
436 break;
437 default:
438 // ignore here, can be predicate or flags, but must not be address
439 break;
440 }
441 }
442
443 void
444 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
445 {
446 code[0] = opc;
447
448 int ss2a = 0;
449 if (opc == 0x0d || opc == 0x0e)
450 ss2a = 2;
451
452 defId(i->def(0), 14);
453 srcId(i->src(0), 20);
454
455 assert(pred || (i->predSrc < 0));
456 if (pred)
457 emitPredicate(i);
458
459 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
460 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
461 assert(!(code[0] & (0x300 >> ss2a)));
462 switch (i->src(s).get()->reg.fileIndex) {
463 case 0: code[0] |= 0x100 >> ss2a; break;
464 case 1: code[0] |= 0x200 >> ss2a; break;
465 case 16: code[0] |= 0x300 >> ss2a; break;
466 default:
467 ERROR("invalid c[] space for short form\n");
468 break;
469 }
470 if (s == 1)
471 code[0] |= i->getSrc(s)->reg.data.offset << 24;
472 else
473 code[0] |= i->getSrc(s)->reg.data.offset << 6;
474 } else
475 if (i->src(s).getFile() == FILE_IMMEDIATE) {
476 assert(s == 1);
477 setImmediateS8(i->src(s));
478 } else
479 if (i->src(s).getFile() == FILE_GPR) {
480 srcId(i->src(s), (s == 1) ? 26 : 8);
481 }
482 }
483 }
484
485 void
486 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
487 {
488 if (src.getFile() == FILE_MEMORY_CONST) {
489 switch (src.get()->reg.fileIndex) {
490 case 0: code[0] |= 0x100; break;
491 case 1: code[0] |= 0x200; break;
492 case 16: code[0] |= 0x300; break;
493 default:
494 assert(!"unsupported file index for short op");
495 break;
496 }
497 srcAddr32(src, 20, 2);
498 } else {
499 srcId(src, 20);
500 assert(src.getFile() == FILE_GPR);
501 }
502 }
503
504 void
505 CodeEmitterNVC0::emitNOP(const Instruction *i)
506 {
507 code[0] = 0x000001e4;
508 code[1] = 0x40000000;
509 emitPredicate(i);
510 }
511
512 void
513 CodeEmitterNVC0::emitFMAD(const Instruction *i)
514 {
515 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
516
517 if (i->encSize == 8) {
518 if (isLIMM(i->src(1), TYPE_F32)) {
519 emitForm_A(i, HEX64(20000000, 00000002));
520 } else {
521 emitForm_A(i, HEX64(30000000, 00000000));
522
523 if (i->src(2).mod.neg())
524 code[0] |= 1 << 8;
525 }
526 roundMode_A(i);
527
528 if (neg1)
529 code[0] |= 1 << 9;
530
531 if (i->saturate)
532 code[0] |= 1 << 5;
533 if (i->ftz)
534 code[0] |= 1 << 6;
535 } else {
536 assert(!i->saturate && !i->src(2).mod.neg());
537 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
538 false);
539 if (neg1)
540 code[0] |= 1 << 4;
541 }
542 }
543
544 void
545 CodeEmitterNVC0::emitDMAD(const Instruction *i)
546 {
547 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
548
549 emitForm_A(i, HEX64(20000000, 00000001));
550
551 if (i->src(2).mod.neg())
552 code[0] |= 1 << 8;
553
554 roundMode_A(i);
555
556 if (neg1)
557 code[0] |= 1 << 9;
558
559 assert(!i->saturate);
560 assert(!i->ftz);
561 }
562
563 void
564 CodeEmitterNVC0::emitFMUL(const Instruction *i)
565 {
566 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
567
568 assert(i->postFactor >= -3 && i->postFactor <= 3);
569
570 if (i->encSize == 8) {
571 if (isLIMM(i->src(1), TYPE_F32)) {
572 assert(i->postFactor == 0); // constant folded, hopefully
573 emitForm_A(i, HEX64(30000000, 00000002));
574 } else {
575 emitForm_A(i, HEX64(58000000, 00000000));
576 roundMode_A(i);
577 code[1] |= ((i->postFactor > 0) ?
578 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
579 }
580 if (neg)
581 code[1] ^= 1 << 25; // aliases with LIMM sign bit
582
583 if (i->saturate)
584 code[0] |= 1 << 5;
585
586 if (i->dnz)
587 code[0] |= 1 << 7;
588 else
589 if (i->ftz)
590 code[0] |= 1 << 6;
591 } else {
592 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
593 emitForm_S(i, 0xa8, true);
594 }
595 }
596
597 void
598 CodeEmitterNVC0::emitDMUL(const Instruction *i)
599 {
600 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
601
602 emitForm_A(i, HEX64(50000000, 00000001));
603 roundMode_A(i);
604
605 if (neg)
606 code[0] |= 1 << 9;
607
608 assert(!i->saturate);
609 assert(!i->ftz);
610 assert(!i->dnz);
611 assert(!i->postFactor);
612 }
613
614 void
615 CodeEmitterNVC0::emitUMUL(const Instruction *i)
616 {
617 if (i->encSize == 8) {
618 if (i->src(1).getFile() == FILE_IMMEDIATE) {
619 emitForm_A(i, HEX64(10000000, 00000002));
620 } else {
621 emitForm_A(i, HEX64(50000000, 00000003));
622 }
623 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
624 code[0] |= 1 << 6;
625 if (i->sType == TYPE_S32)
626 code[0] |= 1 << 5;
627 if (i->dType == TYPE_S32)
628 code[0] |= 1 << 7;
629 } else {
630 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
631
632 if (i->sType == TYPE_S32)
633 code[0] |= 1 << 6;
634 }
635 }
636
637 void
638 CodeEmitterNVC0::emitFADD(const Instruction *i)
639 {
640 if (i->encSize == 8) {
641 if (isLIMM(i->src(1), TYPE_F32)) {
642 assert(!i->saturate);
643 emitForm_A(i, HEX64(28000000, 00000002));
644
645 code[0] |= i->src(0).mod.abs() << 7;
646 code[0] |= i->src(0).mod.neg() << 9;
647
648 if (i->src(1).mod.abs())
649 code[1] &= 0xfdffffff;
650 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
651 code[1] ^= 0x02000000;
652 } else {
653 emitForm_A(i, HEX64(50000000, 00000000));
654
655 roundMode_A(i);
656 if (i->saturate)
657 code[1] |= 1 << 17;
658
659 emitNegAbs12(i);
660 if (i->op == OP_SUB) code[0] ^= 1 << 8;
661 }
662 if (i->ftz)
663 code[0] |= 1 << 5;
664 } else {
665 assert(!i->saturate && i->op != OP_SUB &&
666 !i->src(0).mod.abs() &&
667 !i->src(1).mod.neg() && !i->src(1).mod.abs());
668
669 emitForm_S(i, 0x49, true);
670
671 if (i->src(0).mod.neg())
672 code[0] |= 1 << 7;
673 }
674 }
675
676 void
677 CodeEmitterNVC0::emitDADD(const Instruction *i)
678 {
679 assert(i->encSize == 8);
680 emitForm_A(i, HEX64(48000000, 00000001));
681 roundMode_A(i);
682 assert(!i->saturate);
683 assert(!i->ftz);
684 emitNegAbs12(i);
685 if (i->op == OP_SUB)
686 code[0] ^= 1 << 8;
687 }
688
689 void
690 CodeEmitterNVC0::emitUADD(const Instruction *i)
691 {
692 uint32_t addOp = 0;
693
694 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
695 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
696
697 if (i->src(0).mod.neg())
698 addOp |= 0x200;
699 if (i->src(1).mod.neg())
700 addOp |= 0x100;
701 if (i->op == OP_SUB) {
702 addOp ^= 0x100;
703 assert(addOp != 0x300); // would be add-plus-one
704 }
705
706 if (i->encSize == 8) {
707 if (isLIMM(i->src(1), TYPE_U32)) {
708 emitForm_A(i, HEX64(08000000, 00000002));
709 if (i->defExists(1))
710 code[1] |= 1 << 26; // write carry
711 } else {
712 emitForm_A(i, HEX64(48000000, 00000003));
713 if (i->defExists(1))
714 code[1] |= 1 << 16; // write carry
715 }
716 code[0] |= addOp;
717
718 if (i->saturate)
719 code[0] |= 1 << 5;
720 if (i->flagsSrc >= 0) // add carry
721 code[0] |= 1 << 6;
722 } else {
723 assert(!(addOp & 0x100));
724 emitForm_S(i, (addOp >> 3) |
725 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
726 }
727 }
728
729 // TODO: shl-add
730 void
731 CodeEmitterNVC0::emitIMAD(const Instruction *i)
732 {
733 assert(i->encSize == 8);
734 emitForm_A(i, HEX64(20000000, 00000003));
735
736 if (isSignedType(i->dType))
737 code[0] |= 1 << 7;
738 if (isSignedType(i->sType))
739 code[0] |= 1 << 5;
740
741 code[1] |= i->saturate << 24;
742
743 if (i->flagsDef >= 0) code[1] |= 1 << 16;
744 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
745
746 if (i->src(2).mod.neg()) code[0] |= 0x10;
747 if (i->src(1).mod.neg() ^
748 i->src(0).mod.neg()) code[0] |= 0x20;
749
750 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
751 code[0] |= 1 << 6;
752 }
753
754 void
755 CodeEmitterNVC0::emitMADSP(const Instruction *i)
756 {
757 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
758
759 emitForm_A(i, HEX64(00000000, 00000003));
760
761 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
762 code[1] |= 0x01800000;
763 } else {
764 code[0] |= (i->subOp & 0x00f) << 7;
765 code[0] |= (i->subOp & 0x0f0) << 1;
766 code[0] |= (i->subOp & 0x100) >> 3;
767 code[0] |= (i->subOp & 0x200) >> 2;
768 code[1] |= (i->subOp & 0xc00) << 13;
769 }
770
771 if (i->flagsDef >= 0)
772 code[1] |= 1 << 16;
773 }
774
775 void
776 CodeEmitterNVC0::emitISAD(const Instruction *i)
777 {
778 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
779 assert(i->encSize == 8);
780
781 emitForm_A(i, HEX64(38000000, 00000003));
782
783 if (i->dType == TYPE_S32)
784 code[0] |= 1 << 5;
785 }
786
787 void
788 CodeEmitterNVC0::emitNOT(Instruction *i)
789 {
790 assert(i->encSize == 8);
791 i->setSrc(1, i->src(0));
792 emitForm_A(i, HEX64(68000000, 000001c3));
793 }
794
795 void
796 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
797 {
798 if (i->def(0).getFile() == FILE_PREDICATE) {
799 code[0] = 0x00000004 | (subOp << 30);
800 code[1] = 0x0c000000;
801
802 emitPredicate(i);
803
804 defId(i->def(0), 17);
805 srcId(i->src(0), 20);
806 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
807 srcId(i->src(1), 26);
808 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
809
810 if (i->defExists(1)) {
811 defId(i->def(1), 14);
812 } else {
813 code[0] |= 7 << 14;
814 }
815 // (a OP b) OP c
816 if (i->predSrc != 2 && i->srcExists(2)) {
817 code[1] |= subOp << 21;
818 srcId(i->src(2), 49);
819 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 20;
820 } else {
821 code[1] |= 0x000e0000;
822 }
823 } else
824 if (i->encSize == 8) {
825 if (isLIMM(i->src(1), TYPE_U32)) {
826 emitForm_A(i, HEX64(38000000, 00000002));
827
828 if (i->flagsDef >= 0)
829 code[1] |= 1 << 26;
830 } else {
831 emitForm_A(i, HEX64(68000000, 00000003));
832
833 if (i->flagsDef >= 0)
834 code[1] |= 1 << 16;
835 }
836 code[0] |= subOp << 6;
837
838 if (i->flagsSrc >= 0) // carry
839 code[0] |= 1 << 5;
840
841 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
842 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
843 } else {
844 emitForm_S(i, (subOp << 5) |
845 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
846 }
847 }
848
849 void
850 CodeEmitterNVC0::emitPOPC(const Instruction *i)
851 {
852 emitForm_A(i, HEX64(54000000, 00000004));
853
854 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
855 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
856 }
857
858 void
859 CodeEmitterNVC0::emitINSBF(const Instruction *i)
860 {
861 emitForm_A(i, HEX64(28000000, 00000003));
862 }
863
864 void
865 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
866 {
867 emitForm_A(i, HEX64(70000000, 00000003));
868
869 if (i->dType == TYPE_S32)
870 code[0] |= 1 << 5;
871 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
872 code[0] |= 1 << 8;
873 }
874
875 void
876 CodeEmitterNVC0::emitBFIND(const Instruction *i)
877 {
878 emitForm_B(i, HEX64(78000000, 00000003));
879
880 if (i->dType == TYPE_S32)
881 code[0] |= 1 << 5;
882 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
883 code[0] |= 1 << 8;
884 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
885 code[0] |= 1 << 6;
886 }
887
888 void
889 CodeEmitterNVC0::emitPERMT(const Instruction *i)
890 {
891 emitForm_A(i, HEX64(24000000, 00000004));
892
893 code[0] |= i->subOp << 5;
894 }
895
896 void
897 CodeEmitterNVC0::emitShift(const Instruction *i)
898 {
899 if (i->op == OP_SHR) {
900 emitForm_A(i, HEX64(58000000, 00000003)
901 | (isSignedType(i->dType) ? 0x20 : 0x00));
902 } else {
903 emitForm_A(i, HEX64(60000000, 00000003));
904 }
905
906 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
907 code[0] |= 1 << 9;
908 }
909
910 void
911 CodeEmitterNVC0::emitPreOp(const Instruction *i)
912 {
913 if (i->encSize == 8) {
914 emitForm_B(i, HEX64(60000000, 00000000));
915
916 if (i->op == OP_PREEX2)
917 code[0] |= 0x20;
918
919 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
920 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
921 } else {
922 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
923 }
924 }
925
926 void
927 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
928 {
929 if (i->encSize == 8) {
930 code[0] = 0x00000000 | (subOp << 26);
931 code[1] = 0xc8000000;
932
933 emitPredicate(i);
934
935 defId(i->def(0), 14);
936 srcId(i->src(0), 20);
937
938 assert(i->src(0).getFile() == FILE_GPR);
939
940 if (i->saturate) code[0] |= 1 << 5;
941
942 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
943 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
944 } else {
945 emitForm_S(i, 0x80000008 | (subOp << 26), true);
946
947 assert(!i->src(0).mod.neg());
948 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
949 }
950 }
951
952 void
953 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
954 {
955 uint64_t op;
956
957 assert(i->encSize == 8);
958
959 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
960
961 if (i->ftz)
962 op |= 1 << 5;
963 else
964 if (!isFloatType(i->dType))
965 op |= isSignedType(i->dType) ? 0x23 : 0x03;
966 if (i->dType == TYPE_F64)
967 op |= 0x01;
968
969 emitForm_A(i, op);
970 emitNegAbs12(i);
971 }
972
973 void
974 CodeEmitterNVC0::roundMode_C(const Instruction *i)
975 {
976 switch (i->rnd) {
977 case ROUND_M: code[1] |= 1 << 17; break;
978 case ROUND_P: code[1] |= 2 << 17; break;
979 case ROUND_Z: code[1] |= 3 << 17; break;
980 case ROUND_NI: code[0] |= 1 << 7; break;
981 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
982 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
983 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
984 case ROUND_N: break;
985 default:
986 assert(!"invalid round mode");
987 break;
988 }
989 }
990
991 void
992 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
993 {
994 switch (i->rnd) {
995 case ROUND_M:
996 case ROUND_MI: code[0] |= 1 << 16; break;
997 case ROUND_P:
998 case ROUND_PI: code[0] |= 2 << 16; break;
999 case ROUND_Z:
1000 case ROUND_ZI: code[0] |= 3 << 16; break;
1001 default:
1002 break;
1003 }
1004 }
1005
1006 void
1007 CodeEmitterNVC0::emitCVT(Instruction *i)
1008 {
1009 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1010 DataType dType;
1011
1012 switch (i->op) {
1013 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1014 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1015 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1016 default:
1017 break;
1018 }
1019
1020 const bool sat = (i->op == OP_SAT) || i->saturate;
1021 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1022 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1023
1024 if (i->op == OP_NEG && i->dType == TYPE_U32)
1025 dType = TYPE_S32;
1026 else
1027 dType = i->dType;
1028
1029 if (i->encSize == 8) {
1030 emitForm_B(i, HEX64(10000000, 00000004));
1031
1032 roundMode_C(i);
1033
1034 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1035 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1036 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1037
1038 // for 8/16 source types, the byte/word is in subOp. word 1 is
1039 // represented as 2.
1040 if (!isFloatType(i->sType))
1041 code[1] |= i->subOp << 0x17;
1042 else
1043 code[1] |= i->subOp << 0x18;
1044
1045 if (sat)
1046 code[0] |= 0x20;
1047 if (abs)
1048 code[0] |= 1 << 6;
1049 if (neg && i->op != OP_ABS)
1050 code[0] |= 1 << 8;
1051
1052 if (i->ftz)
1053 code[1] |= 1 << 23;
1054
1055 if (isSignedIntType(dType))
1056 code[0] |= 0x080;
1057 if (isSignedIntType(i->sType))
1058 code[0] |= 0x200;
1059
1060 if (isFloatType(dType)) {
1061 if (!isFloatType(i->sType))
1062 code[1] |= 0x08000000;
1063 } else {
1064 if (isFloatType(i->sType))
1065 code[1] |= 0x04000000;
1066 else
1067 code[1] |= 0x0c000000;
1068 }
1069 } else {
1070 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1071 code[0] = 0x298;
1072 } else
1073 if (isFloatType(dType)) {
1074 if (isFloatType(i->sType))
1075 code[0] = 0x098;
1076 else
1077 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1078 } else {
1079 assert(isFloatType(i->sType));
1080
1081 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1082 }
1083
1084 if (neg) code[0] |= 1 << 16;
1085 if (sat) code[0] |= 1 << 18;
1086 if (abs) code[0] |= 1 << 19;
1087
1088 roundMode_CS(i);
1089 }
1090 }
1091
1092 void
1093 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1094 {
1095 uint32_t hi;
1096 uint32_t lo = 0;
1097
1098 if (i->sType == TYPE_F64)
1099 lo = 0x1;
1100 else
1101 if (!isFloatType(i->sType))
1102 lo = 0x3;
1103
1104 if (isSignedIntType(i->sType))
1105 lo |= 0x20;
1106 if (isFloatType(i->dType)) {
1107 if (isFloatType(i->sType))
1108 lo |= 0x20;
1109 else
1110 lo |= 0x80;
1111 }
1112
1113 switch (i->op) {
1114 case OP_SET_AND: hi = 0x10000000; break;
1115 case OP_SET_OR: hi = 0x10200000; break;
1116 case OP_SET_XOR: hi = 0x10400000; break;
1117 default:
1118 hi = 0x100e0000;
1119 break;
1120 }
1121 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1122
1123 if (i->op != OP_SET)
1124 srcId(i->src(2), 32 + 17);
1125
1126 if (i->def(0).getFile() == FILE_PREDICATE) {
1127 if (i->sType == TYPE_F32)
1128 code[1] += 0x10000000;
1129 else
1130 code[1] += 0x08000000;
1131
1132 code[0] &= ~0xfc000;
1133 defId(i->def(0), 17);
1134 if (i->defExists(1))
1135 defId(i->def(1), 14);
1136 else
1137 code[0] |= 0x1c000;
1138 }
1139
1140 if (i->ftz)
1141 code[1] |= 1 << 27;
1142
1143 emitCondCode(i->setCond, 32 + 23);
1144 emitNegAbs12(i);
1145 }
1146
1147 void
1148 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1149 {
1150 uint64_t op;
1151
1152 switch (i->dType) {
1153 case TYPE_S32:
1154 op = HEX64(30000000, 00000023);
1155 break;
1156 case TYPE_U32:
1157 op = HEX64(30000000, 00000003);
1158 break;
1159 case TYPE_F32:
1160 op = HEX64(38000000, 00000000);
1161 break;
1162 default:
1163 assert(!"invalid type for SLCT");
1164 op = 0;
1165 break;
1166 }
1167 emitForm_A(i, op);
1168
1169 CondCode cc = i->setCond;
1170
1171 if (i->src(2).mod.neg())
1172 cc = reverseCondCode(cc);
1173
1174 emitCondCode(cc, 32 + 23);
1175
1176 if (i->ftz)
1177 code[0] |= 1 << 5;
1178 }
1179
1180 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1181 {
1182 emitForm_A(i, HEX64(20000000, 00000004));
1183
1184 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1185 code[1] |= 1 << 20;
1186 }
1187
1188 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1189 {
1190 code[0] = 0x00000006 | (i->subOp << 26);
1191 code[1] = 0xf0000000;
1192 emitPredicate(i);
1193 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1194 }
1195
1196 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1197 {
1198 code[0] = 0x00000086;
1199 code[1] = 0xd0000000;
1200
1201 code[1] |= i->tex.r;
1202 code[1] |= i->tex.s << 8;
1203
1204 if (i->tex.liveOnly)
1205 code[0] |= 1 << 9;
1206
1207 defId(i->def(0), 14);
1208 srcId(i->src(0), 20);
1209 }
1210
1211 static inline bool
1212 isNextIndependentTex(const TexInstruction *i)
1213 {
1214 if (!i->next || !isTextureOp(i->next->op))
1215 return false;
1216 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1217 return false;
1218 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1219 }
1220
1221 void
1222 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1223 {
1224 code[0] = 0x00000006;
1225
1226 if (isNextIndependentTex(i))
1227 code[0] |= 0x080; // t mode
1228 else
1229 code[0] |= 0x100; // p mode
1230
1231 if (i->tex.liveOnly)
1232 code[0] |= 1 << 9;
1233
1234 switch (i->op) {
1235 case OP_TEX: code[1] = 0x80000000; break;
1236 case OP_TXB: code[1] = 0x84000000; break;
1237 case OP_TXL: code[1] = 0x86000000; break;
1238 case OP_TXF: code[1] = 0x90000000; break;
1239 case OP_TXG: code[1] = 0xa0000000; break;
1240 case OP_TXLQ: code[1] = 0xb0000000; break;
1241 case OP_TXD: code[1] = 0xe0000000; break;
1242 default:
1243 assert(!"invalid texture op");
1244 break;
1245 }
1246 if (i->op == OP_TXF) {
1247 if (!i->tex.levelZero)
1248 code[1] |= 0x02000000;
1249 } else
1250 if (i->tex.levelZero) {
1251 code[1] |= 0x02000000;
1252 }
1253
1254 if (i->op != OP_TXD && i->tex.derivAll)
1255 code[1] |= 1 << 13;
1256
1257 defId(i->def(0), 14);
1258 srcId(i->src(0), 20);
1259
1260 emitPredicate(i);
1261
1262 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1263
1264 code[1] |= i->tex.mask << 14;
1265
1266 code[1] |= i->tex.r;
1267 code[1] |= i->tex.s << 8;
1268 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1269 code[1] |= 1 << 18; // in 1st source (with array index)
1270
1271 // texture target:
1272 code[1] |= (i->tex.target.getDim() - 1) << 20;
1273 if (i->tex.target.isCube())
1274 code[1] += 2 << 20;
1275 if (i->tex.target.isArray())
1276 code[1] |= 1 << 19;
1277 if (i->tex.target.isShadow())
1278 code[1] |= 1 << 24;
1279
1280 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1281
1282 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1283 // lzero
1284 if (i->op == OP_TXL)
1285 code[1] &= ~(1 << 26);
1286 else
1287 if (i->op == OP_TXF)
1288 code[1] &= ~(1 << 25);
1289 }
1290 if (i->tex.target == TEX_TARGET_2D_MS ||
1291 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1292 code[1] |= 1 << 23;
1293
1294 if (i->tex.useOffsets == 1)
1295 code[1] |= 1 << 22;
1296 if (i->tex.useOffsets == 4)
1297 code[1] |= 1 << 23;
1298
1299 srcId(i, src1, 26);
1300 }
1301
1302 void
1303 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1304 {
1305 code[0] = 0x00000086;
1306 code[1] = 0xc0000000;
1307
1308 switch (i->tex.query) {
1309 case TXQ_DIMS: code[1] |= 0 << 22; break;
1310 case TXQ_TYPE: code[1] |= 1 << 22; break;
1311 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1312 case TXQ_FILTER: code[1] |= 3 << 22; break;
1313 case TXQ_LOD: code[1] |= 4 << 22; break;
1314 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1315 default:
1316 assert(!"invalid texture query");
1317 break;
1318 }
1319
1320 code[1] |= i->tex.mask << 14;
1321
1322 code[1] |= i->tex.r;
1323 code[1] |= i->tex.s << 8;
1324 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1325 code[1] |= 1 << 18;
1326
1327 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1328
1329 defId(i->def(0), 14);
1330 srcId(i->src(0), 20);
1331 srcId(i, src1, 26);
1332
1333 emitPredicate(i);
1334 }
1335
1336 void
1337 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1338 {
1339 code[0] = 0x00000000 | (laneMask << 6);
1340 code[1] = 0x48000000 | qOp;
1341
1342 defId(i->def(0), 14);
1343 srcId(i->src(0), 20);
1344 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1345
1346 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1347 code[0] |= 1 << 9; // dall
1348
1349 emitPredicate(i);
1350 }
1351
1352 void
1353 CodeEmitterNVC0::emitFlow(const Instruction *i)
1354 {
1355 const FlowInstruction *f = i->asFlow();
1356
1357 unsigned mask; // bit 0: predicate, bit 1: target
1358
1359 code[0] = 0x00000007;
1360
1361 switch (i->op) {
1362 case OP_BRA:
1363 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1364 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1365 code[0] |= 0x4000;
1366 mask = 3;
1367 break;
1368 case OP_CALL:
1369 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1370 if (f->indirect)
1371 code[0] |= 0x4000; // indirect calls always use c[] source
1372 mask = 2;
1373 break;
1374
1375 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1376 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1377 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1378 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1379 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1380
1381 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1382 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1383 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1384 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1385
1386 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1387 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1388 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1389 default:
1390 assert(!"invalid flow operation");
1391 return;
1392 }
1393
1394 if (mask & 1) {
1395 emitPredicate(i);
1396 if (i->flagsSrc < 0)
1397 code[0] |= 0x1e0;
1398 }
1399
1400 if (!f)
1401 return;
1402
1403 if (f->allWarp)
1404 code[0] |= 1 << 15;
1405 if (f->limit)
1406 code[0] |= 1 << 16;
1407
1408 if (f->indirect) {
1409 if (code[0] & 0x4000) {
1410 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1411 setAddress16(i->src(0));
1412 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1413 if (f->op == OP_BRA)
1414 srcId(f->src(0).getIndirect(0), 20);
1415 } else {
1416 srcId(f, 0, 20);
1417 }
1418 }
1419
1420 if (f->op == OP_CALL) {
1421 if (f->indirect) {
1422 // nothing
1423 } else
1424 if (f->builtin) {
1425 assert(f->absolute);
1426 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1427 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1428 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1429 } else {
1430 assert(!f->absolute);
1431 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1432 code[0] |= (pcRel & 0x3f) << 26;
1433 code[1] |= (pcRel >> 6) & 0x3ffff;
1434 }
1435 } else
1436 if (mask & 2) {
1437 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1438 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1439 pcRel += 8;
1440 // currently we don't want absolute branches
1441 assert(!f->absolute);
1442 code[0] |= (pcRel & 0x3f) << 26;
1443 code[1] |= (pcRel >> 6) & 0x3ffff;
1444 }
1445 }
1446
1447 void
1448 CodeEmitterNVC0::emitBAR(const Instruction *i)
1449 {
1450 Value *rDef = NULL, *pDef = NULL;
1451
1452 switch (i->subOp) {
1453 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1454 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1455 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1456 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1457 default:
1458 code[0] = 0x04;
1459 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1460 break;
1461 }
1462 code[1] = 0x50000000;
1463
1464 code[0] |= 63 << 14;
1465 code[1] |= 7 << 21;
1466
1467 emitPredicate(i);
1468
1469 // barrier id
1470 if (i->src(0).getFile() == FILE_GPR) {
1471 srcId(i->src(0), 20);
1472 } else {
1473 ImmediateValue *imm = i->getSrc(0)->asImm();
1474 assert(imm);
1475 code[0] |= imm->reg.data.u32 << 20;
1476 code[1] |= 0x8000;
1477 }
1478
1479 // thread count
1480 if (i->src(1).getFile() == FILE_GPR) {
1481 srcId(i->src(1), 26);
1482 } else {
1483 ImmediateValue *imm = i->getSrc(1)->asImm();
1484 assert(imm);
1485 assert(imm->reg.data.u32 <= 0xfff);
1486 code[0] |= imm->reg.data.u32 << 26;
1487 code[1] |= imm->reg.data.u32 >> 6;
1488 code[1] |= 0x4000;
1489 }
1490
1491 if (i->srcExists(2) && (i->predSrc != 2)) {
1492 srcId(i->src(2), 32 + 17);
1493 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1494 code[1] |= 1 << 20;
1495 } else {
1496 code[1] |= 7 << 17;
1497 }
1498
1499 if (i->defExists(0)) {
1500 if (i->def(0).getFile() == FILE_GPR)
1501 rDef = i->getDef(0);
1502 else
1503 pDef = i->getDef(0);
1504
1505 if (i->defExists(1)) {
1506 if (i->def(1).getFile() == FILE_GPR)
1507 rDef = i->getDef(1);
1508 else
1509 pDef = i->getDef(1);
1510 }
1511 }
1512 if (rDef) {
1513 code[0] &= ~(63 << 14);
1514 defId(rDef, 14);
1515 }
1516 if (pDef) {
1517 code[1] &= ~(7 << 21);
1518 defId(pDef, 32 + 21);
1519 }
1520 }
1521
1522 void
1523 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1524 {
1525 code[0] = 0x00000006;
1526 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1527
1528 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1529 code[0] |= 0x200;
1530
1531 emitPredicate(i);
1532
1533 defId(i->def(0), 14);
1534 srcId(i->src(0).getIndirect(0), 20);
1535 }
1536
1537 void
1538 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1539 {
1540 uint32_t prim = i->src(0).get()->reg.data.u32;
1541
1542 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1543 code[1] = 0x00000000 | (prim >> 6);
1544
1545 emitPredicate(i);
1546
1547 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1548
1549 defId(i->def(0), 14);
1550 srcId(i, src1, 20);
1551 }
1552
1553 void
1554 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1555 {
1556 code[0] = 0x00000006;
1557 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1558
1559 if (i->perPatch)
1560 code[0] |= 0x100;
1561 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1562 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1563
1564 emitPredicate(i);
1565
1566 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1567
1568 defId(i->def(0), 14);
1569 srcId(i->src(0).getIndirect(0), 20);
1570 srcId(i->src(0).getIndirect(1), 26); // vertex address
1571 }
1572
1573 void
1574 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1575 {
1576 unsigned int size = typeSizeof(i->dType);
1577
1578 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1579 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1580
1581 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1582
1583 if (i->perPatch)
1584 code[0] |= 0x100;
1585
1586 emitPredicate(i);
1587
1588 assert(i->src(1).getFile() == FILE_GPR);
1589
1590 srcId(i->src(0).getIndirect(0), 20);
1591 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1592 srcId(i->src(1), 26);
1593 }
1594
1595 void
1596 CodeEmitterNVC0::emitOUT(const Instruction *i)
1597 {
1598 code[0] = 0x00000006;
1599 code[1] = 0x1c000000;
1600
1601 emitPredicate(i);
1602
1603 defId(i->def(0), 14); // new secret address
1604 srcId(i->src(0), 20); // old secret address, should be 0 initially
1605
1606 assert(i->src(0).getFile() == FILE_GPR);
1607
1608 if (i->op == OP_EMIT)
1609 code[0] |= 1 << 5;
1610 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1611 code[0] |= 1 << 6;
1612
1613 // vertex stream
1614 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1615 unsigned int stream = SDATA(i->src(1)).u32;
1616 assert(stream < 4);
1617 if (stream) {
1618 code[1] |= 0xc000;
1619 code[0] |= stream << 26;
1620 } else {
1621 srcId(NULL, 26);
1622 }
1623 } else {
1624 srcId(i->src(1), 26);
1625 }
1626 }
1627
1628 void
1629 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1630 {
1631 if (i->encSize == 8) {
1632 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1633 } else {
1634 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1635 code[0] |= 0x80;
1636 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1637 }
1638 }
1639
1640 static void
1641 interpApply(const InterpEntry *entry, uint32_t *code,
1642 bool force_persample_interp, bool flatshade)
1643 {
1644 int ipa = entry->ipa;
1645 int reg = entry->reg;
1646 int loc = entry->loc;
1647
1648 if (flatshade &&
1649 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1650 ipa = NV50_IR_INTERP_FLAT;
1651 reg = 0x3f;
1652 } else if (force_persample_interp &&
1653 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1654 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1655 ipa |= NV50_IR_INTERP_CENTROID;
1656 }
1657 code[loc + 0] &= ~(0xf << 6);
1658 code[loc + 0] |= ipa << 6;
1659 code[loc + 0] &= ~(0x3f << 26);
1660 code[loc + 0] |= reg << 26;
1661 }
1662
1663 void
1664 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1665 {
1666 const uint32_t base = i->getSrc(0)->reg.data.offset;
1667
1668 if (i->encSize == 8) {
1669 code[0] = 0x00000000;
1670 code[1] = 0xc0000000 | (base & 0xffff);
1671
1672 if (i->saturate)
1673 code[0] |= 1 << 5;
1674
1675 if (i->op == OP_PINTERP) {
1676 srcId(i->src(1), 26);
1677 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1678 } else {
1679 code[0] |= 0x3f << 26;
1680 addInterp(i->ipa, 0x3f, interpApply);
1681 }
1682
1683 srcId(i->src(0).getIndirect(0), 20);
1684 } else {
1685 assert(i->op == OP_PINTERP);
1686 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1687 srcId(i->src(1), 20);
1688 }
1689 emitInterpMode(i);
1690
1691 emitPredicate(i);
1692 defId(i->def(0), 14);
1693
1694 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1695 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1696 else
1697 code[1] |= 0x3f << 17;
1698 }
1699
1700 void
1701 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1702 {
1703 uint8_t val;
1704
1705 switch (ty) {
1706 case TYPE_U8:
1707 val = 0x00;
1708 break;
1709 case TYPE_S8:
1710 val = 0x20;
1711 break;
1712 case TYPE_F16:
1713 case TYPE_U16:
1714 val = 0x40;
1715 break;
1716 case TYPE_S16:
1717 val = 0x60;
1718 break;
1719 case TYPE_F32:
1720 case TYPE_U32:
1721 case TYPE_S32:
1722 val = 0x80;
1723 break;
1724 case TYPE_F64:
1725 case TYPE_U64:
1726 case TYPE_S64:
1727 val = 0xa0;
1728 break;
1729 case TYPE_B128:
1730 val = 0xc0;
1731 break;
1732 default:
1733 val = 0x80;
1734 assert(!"invalid type");
1735 break;
1736 }
1737 code[0] |= val;
1738 }
1739
1740 void
1741 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1742 {
1743 uint32_t val;
1744
1745 switch (c) {
1746 case CACHE_CA:
1747 // case CACHE_WB:
1748 val = 0x000;
1749 break;
1750 case CACHE_CG:
1751 val = 0x100;
1752 break;
1753 case CACHE_CS:
1754 val = 0x200;
1755 break;
1756 case CACHE_CV:
1757 // case CACHE_WT:
1758 val = 0x300;
1759 break;
1760 default:
1761 val = 0;
1762 assert(!"invalid caching mode");
1763 break;
1764 }
1765 code[0] |= val;
1766 }
1767
1768 static inline bool
1769 uses64bitAddress(const Instruction *ldst)
1770 {
1771 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1772 ldst->src(0).isIndirect(0) &&
1773 ldst->getIndirect(0, 0)->reg.size == 8;
1774 }
1775
1776 void
1777 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1778 {
1779 uint32_t opc;
1780
1781 switch (i->src(0).getFile()) {
1782 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1783 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1784 case FILE_MEMORY_SHARED:
1785 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1786 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1787 opc = 0xb8000000;
1788 else
1789 opc = 0xcc000000;
1790 } else {
1791 opc = 0xc9000000;
1792 }
1793 break;
1794 default:
1795 assert(!"invalid memory file");
1796 opc = 0;
1797 break;
1798 }
1799 code[0] = 0x00000005;
1800 code[1] = opc;
1801
1802 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1803 // Unlocked store on shared memory can fail.
1804 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1805 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1806 assert(i->defExists(0));
1807 defId(i->def(0), 8);
1808 }
1809 }
1810
1811 setAddressByFile(i->src(0));
1812 srcId(i->src(1), 14);
1813 srcId(i->src(0).getIndirect(0), 20);
1814 if (uses64bitAddress(i))
1815 code[1] |= 1 << 26;
1816
1817 emitPredicate(i);
1818
1819 emitLoadStoreType(i->dType);
1820 emitCachingMode(i->cache);
1821 }
1822
1823 void
1824 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1825 {
1826 uint32_t opc;
1827
1828 code[0] = 0x00000005;
1829
1830 switch (i->src(0).getFile()) {
1831 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1832 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1833 case FILE_MEMORY_SHARED:
1834 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1835 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1836 opc = 0xa8000000;
1837 else
1838 opc = 0xc4000000;
1839 } else {
1840 opc = 0xc1000000;
1841 }
1842 break;
1843 case FILE_MEMORY_CONST:
1844 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1845 emitMOV(i); // not sure if this is any better
1846 return;
1847 }
1848 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1849 code[0] = 0x00000006 | (i->subOp << 8);
1850 break;
1851 default:
1852 assert(!"invalid memory file");
1853 opc = 0;
1854 break;
1855 }
1856 code[1] = opc;
1857
1858 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1859 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1860 assert(i->defExists(1));
1861 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1862 defId(i->def(1), 8);
1863 else
1864 defId(i->def(1), 32 + 18);
1865 }
1866 }
1867
1868 defId(i->def(0), 14);
1869
1870 setAddressByFile(i->src(0));
1871 srcId(i->src(0).getIndirect(0), 20);
1872 if (uses64bitAddress(i))
1873 code[1] |= 1 << 26;
1874
1875 emitPredicate(i);
1876
1877 emitLoadStoreType(i->dType);
1878 emitCachingMode(i->cache);
1879 }
1880
1881 uint8_t
1882 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1883 {
1884 switch (SDATA(ref).sv.sv) {
1885 case SV_LANEID: return 0x00;
1886 case SV_PHYSID: return 0x03;
1887 case SV_VERTEX_COUNT: return 0x10;
1888 case SV_INVOCATION_ID: return 0x11;
1889 case SV_YDIR: return 0x12;
1890 case SV_THREAD_KILL: return 0x13;
1891 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1892 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1893 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1894 case SV_GRIDID: return 0x2c;
1895 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1896 case SV_LBASE: return 0x34;
1897 case SV_SBASE: return 0x30;
1898 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1899 default:
1900 assert(!"no sreg for system value");
1901 return 0;
1902 }
1903 }
1904
1905 void
1906 CodeEmitterNVC0::emitMOV(const Instruction *i)
1907 {
1908 if (i->def(0).getFile() == FILE_PREDICATE) {
1909 if (i->src(0).getFile() == FILE_GPR) {
1910 code[0] = 0xfc01c003;
1911 code[1] = 0x1a8e0000;
1912 srcId(i->src(0), 20);
1913 } else {
1914 code[0] = 0x0001c004;
1915 code[1] = 0x0c0e0000;
1916 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1917 code[0] |= 7 << 20;
1918 if (!i->getSrc(0)->reg.data.u32)
1919 code[0] |= 1 << 23;
1920 } else {
1921 srcId(i->src(0), 20);
1922 }
1923 }
1924 defId(i->def(0), 17);
1925 emitPredicate(i);
1926 } else
1927 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1928 uint8_t sr = getSRegEncoding(i->src(0));
1929
1930 if (i->encSize == 8) {
1931 code[0] = 0x00000004 | (sr << 26);
1932 code[1] = 0x2c000000;
1933 } else {
1934 code[0] = 0x40000008 | (sr << 20);
1935 }
1936 defId(i->def(0), 14);
1937
1938 emitPredicate(i);
1939 } else
1940 if (i->encSize == 8) {
1941 uint64_t opc;
1942
1943 if (i->src(0).getFile() == FILE_IMMEDIATE)
1944 opc = HEX64(18000000, 000001e2);
1945 else
1946 if (i->src(0).getFile() == FILE_PREDICATE)
1947 opc = HEX64(080e0000, 1c000004);
1948 else
1949 opc = HEX64(28000000, 00000004);
1950
1951 opc |= i->lanes << 5;
1952
1953 emitForm_B(i, opc);
1954 } else {
1955 uint32_t imm;
1956
1957 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1958 imm = SDATA(i->src(0)).u32;
1959 if (imm & 0xfff00000) {
1960 assert(!(imm & 0x000fffff));
1961 code[0] = 0x00000318 | imm;
1962 } else {
1963 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1964 code[0] = 0x00000118 | (imm << 20);
1965 }
1966 } else {
1967 code[0] = 0x0028;
1968 emitShortSrc2(i->src(0));
1969 }
1970 defId(i->def(0), 14);
1971
1972 emitPredicate(i);
1973 }
1974 }
1975
1976 void
1977 CodeEmitterNVC0::emitATOM(const Instruction *i)
1978 {
1979 const bool hasDst = i->defExists(0);
1980 const bool casOrExch =
1981 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1982 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1983
1984 if (i->dType == TYPE_U64) {
1985 switch (i->subOp) {
1986 case NV50_IR_SUBOP_ATOM_ADD:
1987 code[0] = 0x205;
1988 if (hasDst)
1989 code[1] = 0x507e0000;
1990 else
1991 code[1] = 0x10000000;
1992 break;
1993 case NV50_IR_SUBOP_ATOM_EXCH:
1994 code[0] = 0x305;
1995 code[1] = 0x507e0000;
1996 break;
1997 case NV50_IR_SUBOP_ATOM_CAS:
1998 code[0] = 0x325;
1999 code[1] = 0x50000000;
2000 break;
2001 default:
2002 assert(!"invalid u64 red op");
2003 break;
2004 }
2005 } else
2006 if (i->dType == TYPE_U32) {
2007 switch (i->subOp) {
2008 case NV50_IR_SUBOP_ATOM_EXCH:
2009 code[0] = 0x105;
2010 code[1] = 0x507e0000;
2011 break;
2012 case NV50_IR_SUBOP_ATOM_CAS:
2013 code[0] = 0x125;
2014 code[1] = 0x50000000;
2015 break;
2016 default:
2017 code[0] = 0x5 | (i->subOp << 5);
2018 if (hasDst)
2019 code[1] = 0x507e0000;
2020 else
2021 code[1] = 0x10000000;
2022 break;
2023 }
2024 } else
2025 if (i->dType == TYPE_S32) {
2026 assert(i->subOp <= 2);
2027 code[0] = 0x205 | (i->subOp << 5);
2028 if (hasDst)
2029 code[1] = 0x587e0000;
2030 else
2031 code[1] = 0x18000000;
2032 } else
2033 if (i->dType == TYPE_F32) {
2034 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2035 code[0] = 0x205;
2036 if (hasDst)
2037 code[1] = 0x687e0000;
2038 else
2039 code[1] = 0x28000000;
2040 }
2041
2042 emitPredicate(i);
2043
2044 srcId(i->src(1), 14);
2045
2046 if (hasDst)
2047 defId(i->def(0), 32 + 11);
2048 else
2049 if (casOrExch)
2050 code[1] |= 63 << 11;
2051
2052 if (hasDst || casOrExch) {
2053 const int32_t offset = SDATA(i->src(0)).offset;
2054 assert(offset < 0x80000 && offset >= -0x80000);
2055 code[0] |= offset << 26;
2056 code[1] |= (offset & 0x1ffc0) >> 6;
2057 code[1] |= (offset & 0xe0000) << 6;
2058 } else {
2059 srcAddr32(i->src(0), 26, 0);
2060 }
2061 if (i->getIndirect(0, 0)) {
2062 srcId(i->getIndirect(0, 0), 20);
2063 if (i->getIndirect(0, 0)->reg.size == 8)
2064 code[1] |= 1 << 26;
2065 } else {
2066 code[0] |= 63 << 20;
2067 }
2068
2069 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2070 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2071 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2072 }
2073 }
2074
2075 void
2076 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2077 {
2078 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2079 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2080 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2081 default:
2082 code[0] = 0x45;
2083 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2084 break;
2085 }
2086 code[1] = 0xe0000000;
2087
2088 emitPredicate(i);
2089 }
2090
2091 void
2092 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2093 {
2094 code[0] = 0x00000005 | (i->subOp << 5);
2095
2096 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2097 code[1] = 0x98000000;
2098 srcAddr32(i->src(0), 28, 2);
2099 } else {
2100 code[1] = 0xd0000000;
2101 setAddress24(i->src(0));
2102 }
2103 if (uses64bitAddress(i))
2104 code[1] |= 1 << 26;
2105 srcId(i->src(0).getIndirect(0), 20);
2106
2107 emitPredicate(i);
2108
2109 defId(i, 0, 14);
2110 }
2111
2112 void
2113 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2114 {
2115 uint8_t m;
2116 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2117 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2118 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2119 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2120 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2121 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2122 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2123 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2124 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2125 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2126 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2127 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2128 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2129 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2130 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2131 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2132 default:
2133 return;
2134 }
2135 code[0] |= m << 5;
2136 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2137 code[1] |= 1 << 16;
2138 }
2139
2140 void
2141 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2142 {
2143 ImmediateValue *imm = NULL;
2144 uint64_t opc;
2145
2146 if (i->srcExists(2)) {
2147 imm = i->getSrc(2)->asImm();
2148 if (imm)
2149 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2150 }
2151
2152 switch (i->op) {
2153 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2154 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2155 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2156 default:
2157 assert(0);
2158 return;
2159 }
2160 emitForm_A(i, opc);
2161
2162 if (i->op == OP_SUCLAMP) {
2163 if (i->dType == TYPE_S32)
2164 code[0] |= 1 << 9;
2165 emitSUCLAMPMode(i->subOp);
2166 }
2167
2168 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2169 code[1] |= 1 << 16;
2170
2171 if (i->op != OP_SUEAU) {
2172 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2173 code[0] |= 63 << 14;
2174 code[1] |= i->getDef(0)->reg.data.id << 23;
2175 } else
2176 if (i->defExists(1)) { // r, p
2177 assert(i->def(1).getFile() == FILE_PREDICATE);
2178 code[1] |= i->getDef(1)->reg.data.id << 23;
2179 } else { // r, #
2180 code[1] |= 7 << 23;
2181 }
2182 }
2183 if (imm) {
2184 assert(i->op == OP_SUCLAMP);
2185 i->setSrc(2, imm);
2186 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2187 }
2188 }
2189
2190 void
2191 CodeEmitterNVC0::emitSUGType(DataType ty)
2192 {
2193 switch (ty) {
2194 case TYPE_S32: code[1] |= 1 << 13; break;
2195 case TYPE_U8: code[1] |= 2 << 13; break;
2196 case TYPE_S8: code[1] |= 3 << 13; break;
2197 default:
2198 assert(ty == TYPE_U32);
2199 break;
2200 }
2201 }
2202
2203 void
2204 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2205 {
2206 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2207
2208 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2209 assert(offset == (offset & 0xfffc));
2210
2211 code[1] |= 1 << 21;
2212 code[0] |= offset << 24;
2213 code[1] |= offset >> 8;
2214 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2215 }
2216
2217 void
2218 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2219 {
2220 if (!i->srcExists(s) || (i->predSrc == s)) {
2221 code[1] |= 0x7 << 17;
2222 } else {
2223 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2224 code[1] |= 1 << 20;
2225 srcId(i->src(s), 32 + 17);
2226 }
2227 }
2228
2229 void
2230 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2231 {
2232 code[0] = 0x5;
2233 code[1] = 0xd4000000 | (i->subOp << 15);
2234
2235 emitLoadStoreType(i->dType);
2236 emitSUGType(i->sType);
2237 emitCachingMode(i->cache);
2238
2239 emitPredicate(i);
2240 defId(i->def(0), 14); // destination
2241 srcId(i->src(0), 20); // address
2242 // format
2243 if (i->src(1).getFile() == FILE_GPR)
2244 srcId(i->src(1), 26);
2245 else
2246 setSUConst16(i, 1);
2247 setSUPred(i, 2);
2248 }
2249
2250 void
2251 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2252 {
2253 code[0] = 0x5;
2254 code[1] = 0xdc000000 | (i->subOp << 15);
2255
2256 if (i->op == OP_SUSTP)
2257 code[1] |= i->tex.mask << 22;
2258 else
2259 emitLoadStoreType(i->dType);
2260 emitSUGType(i->sType);
2261 emitCachingMode(i->cache);
2262
2263 emitPredicate(i);
2264 srcId(i->src(0), 20); // address
2265 // format
2266 if (i->src(1).getFile() == FILE_GPR)
2267 srcId(i->src(1), 26);
2268 else
2269 setSUConst16(i, 1);
2270 srcId(i->src(3), 14); // values
2271 setSUPred(i, 2);
2272 }
2273
2274 void
2275 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2276 {
2277 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2278 case 0:
2279 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2280 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2281 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2282 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2283 break;
2284 case 1:
2285 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2286 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2287 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2288 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2289 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2290 code[1] |= (i->mask & 0x3) << 2;
2291 break;
2292 case 2:
2293 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2294 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2295 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2296 code[1] |= (i->mask & 0x3) << 2;
2297 code[1] |= (i->mask & 0xc) << 21;
2298 break;
2299 default:
2300 assert(0);
2301 break;
2302 }
2303 }
2304
2305 void
2306 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2307 {
2308 uint64_t opc = 0x4;
2309
2310 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2311 case 0: opc |= 0xe8ULL << 56; break;
2312 case 1: opc |= 0xb4ULL << 56; break;
2313 case 2: opc |= 0x94ULL << 56; break;
2314 default:
2315 assert(0);
2316 break;
2317 }
2318 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2319 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2320 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2321 } else {
2322 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2323 if (isSignedType(i->sType)) opc |= 1 << 6;
2324 }
2325 emitForm_A(i, opc);
2326 emitVectorSubOp(i);
2327
2328 if (i->saturate)
2329 code[0] |= 1 << 9;
2330 if (i->flagsDef >= 0)
2331 code[1] |= 1 << 16;
2332 }
2333
2334 void
2335 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2336 {
2337 assert(i->encSize == 8);
2338 emitForm_A(i, HEX64(10000000, 00000006));
2339 code[0] |= i->subOp << 5;
2340 code[1] |= 0x00e00000;
2341 }
2342
2343 void
2344 CodeEmitterNVC0::emitVOTE(const Instruction *i)
2345 {
2346 assert(i->src(0).getFile() == FILE_PREDICATE &&
2347 i->def(1).getFile() == FILE_PREDICATE);
2348
2349 code[0] = 0x00000004 | (i->subOp << 5);
2350 code[1] = 0x48000000;
2351
2352 emitPredicate(i);
2353
2354 defId(i->def(0), 14);
2355 defId(i->def(1), 32 + 22);
2356 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
2357 code[0] |= 1 << 23;
2358 srcId(i->src(0), 20);
2359 }
2360
2361 bool
2362 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2363 {
2364 unsigned int size = insn->encSize;
2365
2366 if (writeIssueDelays && !(codeSize & 0x3f))
2367 size += 8;
2368
2369 if (!insn->encSize) {
2370 ERROR("skipping unencodable instruction: "); insn->print();
2371 return false;
2372 } else
2373 if (codeSize + size > codeSizeLimit) {
2374 ERROR("code emitter output buffer too small\n");
2375 return false;
2376 }
2377
2378 if (writeIssueDelays) {
2379 if (!(codeSize & 0x3f)) {
2380 code[0] = 0x00000007; // cf issue delay "instruction"
2381 code[1] = 0x20000000;
2382 code += 2;
2383 codeSize += 8;
2384 }
2385 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2386 uint32_t *data = code - (id * 2 + 2);
2387 if (id <= 2) {
2388 data[0] |= insn->sched << (id * 8 + 4);
2389 } else
2390 if (id == 3) {
2391 data[0] |= insn->sched << 28;
2392 data[1] |= insn->sched >> 4;
2393 } else {
2394 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2395 }
2396 }
2397
2398 // assert that instructions with multiple defs don't corrupt registers
2399 for (int d = 0; insn->defExists(d); ++d)
2400 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2401
2402 switch (insn->op) {
2403 case OP_MOV:
2404 case OP_RDSV:
2405 emitMOV(insn);
2406 break;
2407 case OP_NOP:
2408 break;
2409 case OP_LOAD:
2410 emitLOAD(insn);
2411 break;
2412 case OP_STORE:
2413 emitSTORE(insn);
2414 break;
2415 case OP_LINTERP:
2416 case OP_PINTERP:
2417 emitINTERP(insn);
2418 break;
2419 case OP_VFETCH:
2420 emitVFETCH(insn);
2421 break;
2422 case OP_EXPORT:
2423 emitEXPORT(insn);
2424 break;
2425 case OP_PFETCH:
2426 emitPFETCH(insn);
2427 break;
2428 case OP_AFETCH:
2429 emitAFETCH(insn);
2430 break;
2431 case OP_EMIT:
2432 case OP_RESTART:
2433 emitOUT(insn);
2434 break;
2435 case OP_ADD:
2436 case OP_SUB:
2437 if (insn->dType == TYPE_F64)
2438 emitDADD(insn);
2439 else if (isFloatType(insn->dType))
2440 emitFADD(insn);
2441 else
2442 emitUADD(insn);
2443 break;
2444 case OP_MUL:
2445 if (insn->dType == TYPE_F64)
2446 emitDMUL(insn);
2447 else if (isFloatType(insn->dType))
2448 emitFMUL(insn);
2449 else
2450 emitUMUL(insn);
2451 break;
2452 case OP_MAD:
2453 case OP_FMA:
2454 if (insn->dType == TYPE_F64)
2455 emitDMAD(insn);
2456 else if (isFloatType(insn->dType))
2457 emitFMAD(insn);
2458 else
2459 emitIMAD(insn);
2460 break;
2461 case OP_SAD:
2462 emitISAD(insn);
2463 break;
2464 case OP_NOT:
2465 emitNOT(insn);
2466 break;
2467 case OP_AND:
2468 emitLogicOp(insn, 0);
2469 break;
2470 case OP_OR:
2471 emitLogicOp(insn, 1);
2472 break;
2473 case OP_XOR:
2474 emitLogicOp(insn, 2);
2475 break;
2476 case OP_SHL:
2477 case OP_SHR:
2478 emitShift(insn);
2479 break;
2480 case OP_SET:
2481 case OP_SET_AND:
2482 case OP_SET_OR:
2483 case OP_SET_XOR:
2484 emitSET(insn->asCmp());
2485 break;
2486 case OP_SELP:
2487 emitSELP(insn);
2488 break;
2489 case OP_SLCT:
2490 emitSLCT(insn->asCmp());
2491 break;
2492 case OP_MIN:
2493 case OP_MAX:
2494 emitMINMAX(insn);
2495 break;
2496 case OP_ABS:
2497 case OP_NEG:
2498 case OP_CEIL:
2499 case OP_FLOOR:
2500 case OP_TRUNC:
2501 case OP_SAT:
2502 emitCVT(insn);
2503 break;
2504 case OP_CVT:
2505 if (insn->def(0).getFile() == FILE_PREDICATE ||
2506 insn->src(0).getFile() == FILE_PREDICATE)
2507 emitMOV(insn);
2508 else
2509 emitCVT(insn);
2510 break;
2511 case OP_RSQ:
2512 emitSFnOp(insn, 5 + 2 * insn->subOp);
2513 break;
2514 case OP_RCP:
2515 emitSFnOp(insn, 4 + 2 * insn->subOp);
2516 break;
2517 case OP_LG2:
2518 emitSFnOp(insn, 3);
2519 break;
2520 case OP_EX2:
2521 emitSFnOp(insn, 2);
2522 break;
2523 case OP_SIN:
2524 emitSFnOp(insn, 1);
2525 break;
2526 case OP_COS:
2527 emitSFnOp(insn, 0);
2528 break;
2529 case OP_PRESIN:
2530 case OP_PREEX2:
2531 emitPreOp(insn);
2532 break;
2533 case OP_TEX:
2534 case OP_TXB:
2535 case OP_TXL:
2536 case OP_TXD:
2537 case OP_TXF:
2538 case OP_TXG:
2539 case OP_TXLQ:
2540 emitTEX(insn->asTex());
2541 break;
2542 case OP_TXQ:
2543 emitTXQ(insn->asTex());
2544 break;
2545 case OP_TEXBAR:
2546 emitTEXBAR(insn);
2547 break;
2548 case OP_SUBFM:
2549 case OP_SUCLAMP:
2550 case OP_SUEAU:
2551 emitSUCalc(insn);
2552 break;
2553 case OP_MADSP:
2554 emitMADSP(insn);
2555 break;
2556 case OP_SULDB:
2557 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2558 emitSULDGB(insn->asTex());
2559 else
2560 ERROR("SULDB not yet supported on < nve4\n");
2561 break;
2562 case OP_SUSTB:
2563 case OP_SUSTP:
2564 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2565 emitSUSTGx(insn->asTex());
2566 else
2567 ERROR("SUSTx not yet supported on < nve4\n");
2568 break;
2569 case OP_ATOM:
2570 emitATOM(insn);
2571 break;
2572 case OP_BRA:
2573 case OP_CALL:
2574 case OP_PRERET:
2575 case OP_RET:
2576 case OP_DISCARD:
2577 case OP_EXIT:
2578 case OP_PRECONT:
2579 case OP_CONT:
2580 case OP_PREBREAK:
2581 case OP_BREAK:
2582 case OP_JOINAT:
2583 case OP_BRKPT:
2584 case OP_QUADON:
2585 case OP_QUADPOP:
2586 emitFlow(insn);
2587 break;
2588 case OP_QUADOP:
2589 emitQUADOP(insn, insn->subOp, insn->lanes);
2590 break;
2591 case OP_DFDX:
2592 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2593 break;
2594 case OP_DFDY:
2595 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2596 break;
2597 case OP_POPCNT:
2598 emitPOPC(insn);
2599 break;
2600 case OP_INSBF:
2601 emitINSBF(insn);
2602 break;
2603 case OP_EXTBF:
2604 emitEXTBF(insn);
2605 break;
2606 case OP_BFIND:
2607 emitBFIND(insn);
2608 break;
2609 case OP_PERMT:
2610 emitPERMT(insn);
2611 break;
2612 case OP_JOIN:
2613 emitNOP(insn);
2614 insn->join = 1;
2615 break;
2616 case OP_BAR:
2617 emitBAR(insn);
2618 break;
2619 case OP_MEMBAR:
2620 emitMEMBAR(insn);
2621 break;
2622 case OP_CCTL:
2623 emitCCTL(insn);
2624 break;
2625 case OP_VSHL:
2626 emitVSHL(insn);
2627 break;
2628 case OP_PIXLD:
2629 emitPIXLD(insn);
2630 break;
2631 case OP_VOTE:
2632 emitVOTE(insn);
2633 break;
2634 case OP_PHI:
2635 case OP_UNION:
2636 case OP_CONSTRAINT:
2637 ERROR("operation should have been eliminated");
2638 return false;
2639 case OP_EXP:
2640 case OP_LOG:
2641 case OP_SQRT:
2642 case OP_POW:
2643 ERROR("operation should have been lowered\n");
2644 return false;
2645 default:
2646 ERROR("unknown op: %u\n", insn->op);
2647 return false;
2648 }
2649
2650 if (insn->join) {
2651 code[0] |= 0x10;
2652 assert(insn->encSize == 8);
2653 }
2654
2655 code += insn->encSize / 4;
2656 codeSize += insn->encSize;
2657 return true;
2658 }
2659
2660 uint32_t
2661 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2662 {
2663 const Target::OpInfo &info = targ->getOpInfo(i);
2664
2665 if (writeIssueDelays || info.minEncSize == 8 || 1)
2666 return 8;
2667
2668 if (i->ftz || i->saturate || i->join)
2669 return 8;
2670 if (i->rnd != ROUND_N)
2671 return 8;
2672 if (i->predSrc >= 0 && i->op == OP_MAD)
2673 return 8;
2674
2675 if (i->op == OP_PINTERP) {
2676 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2677 return 8;
2678 } else
2679 if (i->op == OP_MOV && i->lanes != 0xf) {
2680 return 8;
2681 }
2682
2683 for (int s = 0; i->srcExists(s); ++s) {
2684 if (i->src(s).isIndirect(0))
2685 return 8;
2686
2687 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2688 if (SDATA(i->src(s)).offset >= 0x100)
2689 return 8;
2690 if (i->getSrc(s)->reg.fileIndex > 1 &&
2691 i->getSrc(s)->reg.fileIndex != 16)
2692 return 8;
2693 } else
2694 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2695 if (i->dType == TYPE_F32) {
2696 if (SDATA(i->src(s)).u32 >= 0x100)
2697 return 8;
2698 } else {
2699 if (SDATA(i->src(s)).u32 > 0xff)
2700 return 8;
2701 }
2702 }
2703
2704 if (i->op == OP_CVT)
2705 continue;
2706 if (i->src(s).mod != Modifier(0)) {
2707 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2708 if (i->op != OP_RSQ)
2709 return 8;
2710 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2711 if (i->op != OP_ADD || s != 0)
2712 return 8;
2713 }
2714 }
2715
2716 return 4;
2717 }
2718
2719 // Simplified, erring on safe side.
2720 class SchedDataCalculator : public Pass
2721 {
2722 public:
2723 SchedDataCalculator(const Target *targ) : targ(targ) { }
2724
2725 private:
2726 struct RegScores
2727 {
2728 struct Resource {
2729 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2730 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2731 int tex; // TEX to non-TEX delay 17 (0x11)
2732 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2733 int imul; // integer MUL to MUL delay 3
2734 } res;
2735 struct ScoreData {
2736 int r[256];
2737 int p[8];
2738 int c;
2739 } rd, wr;
2740 int base;
2741 int regs;
2742
2743 void rebase(const int base)
2744 {
2745 const int delta = this->base - base;
2746 if (!delta)
2747 return;
2748 this->base = 0;
2749
2750 for (int i = 0; i < regs; ++i) {
2751 rd.r[i] += delta;
2752 wr.r[i] += delta;
2753 }
2754 for (int i = 0; i < 8; ++i) {
2755 rd.p[i] += delta;
2756 wr.p[i] += delta;
2757 }
2758 rd.c += delta;
2759 wr.c += delta;
2760
2761 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2762 res.ld[f] += delta;
2763 res.st[f] += delta;
2764 }
2765 res.sfu += delta;
2766 res.imul += delta;
2767 res.tex += delta;
2768 }
2769 void wipe(int regs)
2770 {
2771 memset(&rd, 0, sizeof(rd));
2772 memset(&wr, 0, sizeof(wr));
2773 memset(&res, 0, sizeof(res));
2774 this->regs = regs;
2775 }
2776 int getLatest(const ScoreData& d) const
2777 {
2778 int max = 0;
2779 for (int i = 0; i < regs; ++i)
2780 if (d.r[i] > max)
2781 max = d.r[i];
2782 for (int i = 0; i < 8; ++i)
2783 if (d.p[i] > max)
2784 max = d.p[i];
2785 if (d.c > max)
2786 max = d.c;
2787 return max;
2788 }
2789 inline int getLatestRd() const
2790 {
2791 return getLatest(rd);
2792 }
2793 inline int getLatestWr() const
2794 {
2795 return getLatest(wr);
2796 }
2797 inline int getLatest() const
2798 {
2799 const int a = getLatestRd();
2800 const int b = getLatestWr();
2801
2802 int max = MAX2(a, b);
2803 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2804 max = MAX2(res.ld[f], max);
2805 max = MAX2(res.st[f], max);
2806 }
2807 max = MAX2(res.sfu, max);
2808 max = MAX2(res.imul, max);
2809 max = MAX2(res.tex, max);
2810 return max;
2811 }
2812 void setMax(const RegScores *that)
2813 {
2814 for (int i = 0; i < regs; ++i) {
2815 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2816 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2817 }
2818 for (int i = 0; i < 8; ++i) {
2819 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2820 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2821 }
2822 rd.c = MAX2(rd.c, that->rd.c);
2823 wr.c = MAX2(wr.c, that->wr.c);
2824
2825 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2826 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2827 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2828 }
2829 res.sfu = MAX2(res.sfu, that->res.sfu);
2830 res.imul = MAX2(res.imul, that->res.imul);
2831 res.tex = MAX2(res.tex, that->res.tex);
2832 }
2833 void print(int cycle)
2834 {
2835 for (int i = 0; i < regs; ++i) {
2836 if (rd.r[i] > cycle)
2837 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2838 if (wr.r[i] > cycle)
2839 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2840 }
2841 for (int i = 0; i < 8; ++i) {
2842 if (rd.p[i] > cycle)
2843 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2844 if (wr.p[i] > cycle)
2845 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2846 }
2847 if (rd.c > cycle)
2848 INFO("rd $c @ %i\n", rd.c);
2849 if (wr.c > cycle)
2850 INFO("wr $c @ %i\n", wr.c);
2851 if (res.sfu > cycle)
2852 INFO("sfu @ %i\n", res.sfu);
2853 if (res.imul > cycle)
2854 INFO("imul @ %i\n", res.imul);
2855 if (res.tex > cycle)
2856 INFO("tex @ %i\n", res.tex);
2857 }
2858 };
2859
2860 RegScores *score; // for current BB
2861 std::vector<RegScores> scoreBoards;
2862 int prevData;
2863 operation prevOp;
2864
2865 const Target *targ;
2866
2867 bool visit(Function *);
2868 bool visit(BasicBlock *);
2869
2870 void commitInsn(const Instruction *, int cycle);
2871 int calcDelay(const Instruction *, int cycle) const;
2872 void setDelay(Instruction *, int delay, Instruction *next);
2873
2874 void recordRd(const Value *, const int ready);
2875 void recordWr(const Value *, const int ready);
2876 void checkRd(const Value *, int cycle, int& delay) const;
2877 void checkWr(const Value *, int cycle, int& delay) const;
2878
2879 int getCycles(const Instruction *, int origDelay) const;
2880 };
2881
2882 void
2883 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2884 {
2885 if (insn->op == OP_EXIT || insn->op == OP_RET)
2886 delay = MAX2(delay, 14);
2887
2888 if (insn->op == OP_TEXBAR) {
2889 // TODO: except if results not used before EXIT
2890 insn->sched = 0xc2;
2891 } else
2892 if (insn->op == OP_JOIN || insn->join) {
2893 insn->sched = 0x00;
2894 } else
2895 if (delay >= 0 || prevData == 0x04 ||
2896 !next || !targ->canDualIssue(insn, next)) {
2897 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2898 if (prevOp == OP_EXPORT)
2899 insn->sched |= 0x40;
2900 else
2901 insn->sched |= 0x20;
2902 } else {
2903 insn->sched = 0x04; // dual-issue
2904 }
2905
2906 if (prevData != 0x04 || prevOp != OP_EXPORT)
2907 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2908 prevOp = insn->op;
2909
2910 prevData = insn->sched;
2911 }
2912
2913 int
2914 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2915 {
2916 if (insn->sched & 0x80) {
2917 int c = (insn->sched & 0x0f) * 2 + 1;
2918 if (insn->op == OP_TEXBAR && origDelay > 0)
2919 c += origDelay;
2920 return c;
2921 }
2922 if (insn->sched & 0x60)
2923 return (insn->sched & 0x1f) + 1;
2924 return (insn->sched == 0x04) ? 0 : 32;
2925 }
2926
2927 bool
2928 SchedDataCalculator::visit(Function *func)
2929 {
2930 int regs = targ->getFileSize(FILE_GPR) + 1;
2931 scoreBoards.resize(func->cfg.getSize());
2932 for (size_t i = 0; i < scoreBoards.size(); ++i)
2933 scoreBoards[i].wipe(regs);
2934 return true;
2935 }
2936
2937 bool
2938 SchedDataCalculator::visit(BasicBlock *bb)
2939 {
2940 Instruction *insn;
2941 Instruction *next = NULL;
2942
2943 int cycle = 0;
2944
2945 prevData = 0x00;
2946 prevOp = OP_NOP;
2947 score = &scoreBoards.at(bb->getId());
2948
2949 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2950 // back branches will wait until all target dependencies are satisfied
2951 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2952 continue;
2953 BasicBlock *in = BasicBlock::get(ei.getNode());
2954 if (in->getExit()) {
2955 if (prevData != 0x04)
2956 prevData = in->getExit()->sched;
2957 prevOp = in->getExit()->op;
2958 }
2959 score->setMax(&scoreBoards.at(in->getId()));
2960 }
2961 if (bb->cfg.incidentCount() > 1)
2962 prevOp = OP_NOP;
2963
2964 #ifdef NVC0_DEBUG_SCHED_DATA
2965 INFO("=== BB:%i initial scores\n", bb->getId());
2966 score->print(cycle);
2967 #endif
2968
2969 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2970 next = insn->next;
2971
2972 commitInsn(insn, cycle);
2973 int delay = calcDelay(next, cycle);
2974 setDelay(insn, delay, next);
2975 cycle += getCycles(insn, delay);
2976
2977 #ifdef NVC0_DEBUG_SCHED_DATA
2978 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2979 insn->print();
2980 next->print();
2981 #endif
2982 }
2983 if (!insn)
2984 return true;
2985 commitInsn(insn, cycle);
2986
2987 int bbDelay = -1;
2988
2989 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2990 BasicBlock *out = BasicBlock::get(ei.getNode());
2991
2992 if (ei.getType() != Graph::Edge::BACK) {
2993 // only test the first instruction of the outgoing block
2994 next = out->getEntry();
2995 if (next)
2996 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2997 } else {
2998 // wait until all dependencies are satisfied
2999 const int regsFree = score->getLatest();
3000 next = out->getFirst();
3001 for (int c = cycle; next && c < regsFree; next = next->next) {
3002 bbDelay = MAX2(bbDelay, calcDelay(next, c));
3003 c += getCycles(next, bbDelay);
3004 }
3005 next = NULL;
3006 }
3007 }
3008 if (bb->cfg.outgoingCount() != 1)
3009 next = NULL;
3010 setDelay(insn, bbDelay, next);
3011 cycle += getCycles(insn, bbDelay);
3012
3013 score->rebase(cycle); // common base for initializing out blocks' scores
3014 return true;
3015 }
3016
3017 #define NVE4_MAX_ISSUE_DELAY 0x1f
3018 int
3019 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
3020 {
3021 int delay = 0, ready = cycle;
3022
3023 for (int s = 0; insn->srcExists(s); ++s)
3024 checkRd(insn->getSrc(s), cycle, delay);
3025 // WAR & WAW don't seem to matter
3026 // for (int s = 0; insn->srcExists(s); ++s)
3027 // recordRd(insn->getSrc(s), cycle);
3028
3029 switch (Target::getOpClass(insn->op)) {
3030 case OPCLASS_SFU:
3031 ready = score->res.sfu;
3032 break;
3033 case OPCLASS_ARITH:
3034 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3035 ready = score->res.imul;
3036 break;
3037 case OPCLASS_TEXTURE:
3038 ready = score->res.tex;
3039 break;
3040 case OPCLASS_LOAD:
3041 ready = score->res.ld[insn->src(0).getFile()];
3042 break;
3043 case OPCLASS_STORE:
3044 ready = score->res.st[insn->src(0).getFile()];
3045 break;
3046 default:
3047 break;
3048 }
3049 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3050 ready = MAX2(ready, score->res.tex);
3051
3052 delay = MAX2(delay, ready - cycle);
3053
3054 // if can issue next cycle, delay is 0, not 1
3055 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3056 }
3057
3058 void
3059 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3060 {
3061 const int ready = cycle + targ->getLatency(insn);
3062
3063 for (int d = 0; insn->defExists(d); ++d)
3064 recordWr(insn->getDef(d), ready);
3065 // WAR & WAW don't seem to matter
3066 // for (int s = 0; insn->srcExists(s); ++s)
3067 // recordRd(insn->getSrc(s), cycle);
3068
3069 switch (Target::getOpClass(insn->op)) {
3070 case OPCLASS_SFU:
3071 score->res.sfu = cycle + 4;
3072 break;
3073 case OPCLASS_ARITH:
3074 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3075 score->res.imul = cycle + 4;
3076 break;
3077 case OPCLASS_TEXTURE:
3078 score->res.tex = cycle + 18;
3079 break;
3080 case OPCLASS_LOAD:
3081 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3082 break;
3083 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3084 score->res.st[insn->src(0).getFile()] = ready;
3085 break;
3086 case OPCLASS_STORE:
3087 score->res.st[insn->src(0).getFile()] = cycle + 4;
3088 score->res.ld[insn->src(0).getFile()] = ready;
3089 break;
3090 case OPCLASS_OTHER:
3091 if (insn->op == OP_TEXBAR)
3092 score->res.tex = cycle;
3093 break;
3094 default:
3095 break;
3096 }
3097
3098 #ifdef NVC0_DEBUG_SCHED_DATA
3099 score->print(cycle);
3100 #endif
3101 }
3102
3103 void
3104 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3105 {
3106 int ready = cycle;
3107 int a, b;
3108
3109 switch (v->reg.file) {
3110 case FILE_GPR:
3111 a = v->reg.data.id;
3112 b = a + v->reg.size / 4;
3113 for (int r = a; r < b; ++r)
3114 ready = MAX2(ready, score->rd.r[r]);
3115 break;
3116 case FILE_PREDICATE:
3117 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3118 break;
3119 case FILE_FLAGS:
3120 ready = MAX2(ready, score->rd.c);
3121 break;
3122 case FILE_SHADER_INPUT:
3123 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3124 case FILE_MEMORY_LOCAL:
3125 case FILE_MEMORY_CONST:
3126 case FILE_MEMORY_SHARED:
3127 case FILE_MEMORY_GLOBAL:
3128 case FILE_SYSTEM_VALUE:
3129 // TODO: any restrictions here ?
3130 break;
3131 case FILE_IMMEDIATE:
3132 break;
3133 default:
3134 assert(0);
3135 break;
3136 }
3137 if (cycle < ready)
3138 delay = MAX2(delay, ready - cycle);
3139 }
3140
3141 void
3142 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3143 {
3144 int ready = cycle;
3145 int a, b;
3146
3147 switch (v->reg.file) {
3148 case FILE_GPR:
3149 a = v->reg.data.id;
3150 b = a + v->reg.size / 4;
3151 for (int r = a; r < b; ++r)
3152 ready = MAX2(ready, score->wr.r[r]);
3153 break;
3154 case FILE_PREDICATE:
3155 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3156 break;
3157 default:
3158 assert(v->reg.file == FILE_FLAGS);
3159 ready = MAX2(ready, score->wr.c);
3160 break;
3161 }
3162 if (cycle < ready)
3163 delay = MAX2(delay, ready - cycle);
3164 }
3165
3166 void
3167 SchedDataCalculator::recordWr(const Value *v, const int ready)
3168 {
3169 int a = v->reg.data.id;
3170
3171 if (v->reg.file == FILE_GPR) {
3172 int b = a + v->reg.size / 4;
3173 for (int r = a; r < b; ++r)
3174 score->rd.r[r] = ready;
3175 } else
3176 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3177 if (v->reg.file == FILE_PREDICATE) {
3178 score->rd.p[a] = ready + 4;
3179 } else {
3180 assert(v->reg.file == FILE_FLAGS);
3181 score->rd.c = ready + 4;
3182 }
3183 }
3184
3185 void
3186 SchedDataCalculator::recordRd(const Value *v, const int ready)
3187 {
3188 int a = v->reg.data.id;
3189
3190 if (v->reg.file == FILE_GPR) {
3191 int b = a + v->reg.size / 4;
3192 for (int r = a; r < b; ++r)
3193 score->wr.r[r] = ready;
3194 } else
3195 if (v->reg.file == FILE_PREDICATE) {
3196 score->wr.p[a] = ready;
3197 } else
3198 if (v->reg.file == FILE_FLAGS) {
3199 score->wr.c = ready;
3200 }
3201 }
3202
3203 bool
3204 calculateSchedDataNVC0(const Target *targ, Function *func)
3205 {
3206 SchedDataCalculator sched(targ);
3207 return sched.run(func, true, true);
3208 }
3209
3210 void
3211 CodeEmitterNVC0::prepareEmission(Function *func)
3212 {
3213 CodeEmitter::prepareEmission(func);
3214
3215 if (targ->hasSWSched)
3216 calculateSchedDataNVC0(targ, func);
3217 }
3218
3219 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3220 : CodeEmitter(target),
3221 targNVC0(target),
3222 writeIssueDelays(target->hasSWSched)
3223 {
3224 code = NULL;
3225 codeSize = codeSizeLimit = 0;
3226 relocInfo = NULL;
3227 }
3228
3229 CodeEmitter *
3230 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3231 {
3232 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3233 emit->setProgramType(type);
3234 return emit;
3235 }
3236
3237 CodeEmitter *
3238 TargetNVC0::getCodeEmitter(Program::Type type)
3239 {
3240 if (chipset >= NVISA_GK20A_CHIPSET)
3241 return createCodeEmitterGK110(type);
3242 return createCodeEmitterNVC0(type);
3243 }
3244
3245 } // namespace nv50_ir