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nvc0/ir: Properly handle a "split form" of predicate destination
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61 void setPDSTL(const Instruction *, const int d);
62
63 void emitCondCode(CondCode cc, int pos);
64 void emitInterpMode(const Instruction *);
65 void emitLoadStoreType(DataType ty);
66 void emitSUGType(DataType);
67 void emitSUAddr(const TexInstruction *);
68 void emitSUDim(const TexInstruction *);
69 void emitCachingMode(CacheMode c);
70
71 void emitShortSrc2(const ValueRef&);
72
73 inline uint8_t getSRegEncoding(const ValueRef&);
74
75 void roundMode_A(const Instruction *);
76 void roundMode_C(const Instruction *);
77 void roundMode_CS(const Instruction *);
78
79 void emitNegAbs12(const Instruction *);
80
81 void emitNOP(const Instruction *);
82
83 void emitLOAD(const Instruction *);
84 void emitSTORE(const Instruction *);
85 void emitMOV(const Instruction *);
86 void emitATOM(const Instruction *);
87 void emitMEMBAR(const Instruction *);
88 void emitCCTL(const Instruction *);
89
90 void emitINTERP(const Instruction *);
91 void emitAFETCH(const Instruction *);
92 void emitPFETCH(const Instruction *);
93 void emitVFETCH(const Instruction *);
94 void emitEXPORT(const Instruction *);
95 void emitOUT(const Instruction *);
96
97 void emitUADD(const Instruction *);
98 void emitFADD(const Instruction *);
99 void emitDADD(const Instruction *);
100 void emitUMUL(const Instruction *);
101 void emitFMUL(const Instruction *);
102 void emitDMUL(const Instruction *);
103 void emitIMAD(const Instruction *);
104 void emitISAD(const Instruction *);
105 void emitSHLADD(const Instruction *a);
106 void emitFMAD(const Instruction *);
107 void emitDMAD(const Instruction *);
108 void emitMADSP(const Instruction *);
109
110 void emitNOT(Instruction *);
111 void emitLogicOp(const Instruction *, uint8_t subOp);
112 void emitPOPC(const Instruction *);
113 void emitINSBF(const Instruction *);
114 void emitEXTBF(const Instruction *);
115 void emitBFIND(const Instruction *);
116 void emitPERMT(const Instruction *);
117 void emitShift(const Instruction *);
118
119 void emitSFnOp(const Instruction *, uint8_t subOp);
120
121 void emitCVT(Instruction *);
122 void emitMINMAX(const Instruction *);
123 void emitPreOp(const Instruction *);
124
125 void emitSET(const CmpInstruction *);
126 void emitSLCT(const CmpInstruction *);
127 void emitSELP(const Instruction *);
128
129 void emitTEXBAR(const Instruction *);
130 void emitTEX(const TexInstruction *);
131 void emitTEXCSAA(const TexInstruction *);
132 void emitTXQ(const TexInstruction *);
133
134 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
135
136 void emitFlow(const Instruction *);
137 void emitBAR(const Instruction *);
138
139 void emitSUCLAMPMode(uint16_t);
140 void emitSUCalc(Instruction *);
141 void emitSULDGB(const TexInstruction *);
142 void emitSUSTGx(const TexInstruction *);
143
144 void emitSULDB(const TexInstruction *);
145 void emitSUSTx(const TexInstruction *);
146 void emitSULEA(const TexInstruction *);
147
148 void emitVSHL(const Instruction *);
149 void emitVectorSubOp(const Instruction *);
150
151 void emitPIXLD(const Instruction *);
152
153 void emitVOTE(const Instruction *);
154
155 inline void defId(const ValueDef&, const int pos);
156 inline void defId(const Instruction *, int d, const int pos);
157 inline void srcId(const ValueRef&, const int pos);
158 inline void srcId(const ValueRef *, const int pos);
159 inline void srcId(const Instruction *, int s, const int pos);
160 inline void srcAddr32(const ValueRef&, int pos, int shr);
161
162 inline bool isLIMM(const ValueRef&, DataType ty);
163 };
164
165 // for better visibility
166 #define HEX64(h, l) 0x##h##l##ULL
167
168 #define SDATA(a) ((a).rep()->reg.data)
169 #define DDATA(a) ((a).rep()->reg.data)
170
171 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
172 {
173 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
174 }
175
176 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
177 {
178 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
179 }
180
181 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
182 {
183 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
184 code[pos / 32] |= r << (pos % 32);
185 }
186
187 void
188 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
189 {
190 const uint32_t offset = SDATA(src).offset >> shr;
191
192 code[pos / 32] |= offset << (pos % 32);
193 if (pos && (pos < 32))
194 code[1] |= offset >> (32 - pos);
195 }
196
197 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
198 {
199 code[pos / 32] |= (def.get() && def.getFile() != FILE_FLAGS ? DDATA(def).id : 63) << (pos % 32);
200 }
201
202 void CodeEmitterNVC0::defId(const Instruction *insn, int d, const int pos)
203 {
204 if (insn->defExists(d))
205 defId(insn->def(d), pos);
206 else
207 code[pos / 32] |= 63 << (pos % 32);
208 }
209
210 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
211 {
212 const ImmediateValue *imm = ref.get()->asImm();
213
214 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
215 }
216
217 void
218 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
219 {
220 switch (insn->rnd) {
221 case ROUND_M: code[1] |= 1 << 23; break;
222 case ROUND_P: code[1] |= 2 << 23; break;
223 case ROUND_Z: code[1] |= 3 << 23; break;
224 default:
225 assert(insn->rnd == ROUND_N);
226 break;
227 }
228 }
229
230 void
231 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
232 {
233 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
234 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
235 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
236 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
237 }
238
239 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
240 {
241 uint8_t val;
242
243 switch (cc) {
244 case CC_LT: val = 0x1; break;
245 case CC_LTU: val = 0x9; break;
246 case CC_EQ: val = 0x2; break;
247 case CC_EQU: val = 0xa; break;
248 case CC_LE: val = 0x3; break;
249 case CC_LEU: val = 0xb; break;
250 case CC_GT: val = 0x4; break;
251 case CC_GTU: val = 0xc; break;
252 case CC_NE: val = 0x5; break;
253 case CC_NEU: val = 0xd; break;
254 case CC_GE: val = 0x6; break;
255 case CC_GEU: val = 0xe; break;
256 case CC_TR: val = 0xf; break;
257 case CC_FL: val = 0x0; break;
258
259 case CC_A: val = 0x14; break;
260 case CC_NA: val = 0x13; break;
261 case CC_S: val = 0x15; break;
262 case CC_NS: val = 0x12; break;
263 case CC_C: val = 0x16; break;
264 case CC_NC: val = 0x11; break;
265 case CC_O: val = 0x17; break;
266 case CC_NO: val = 0x10; break;
267
268 default:
269 val = 0;
270 assert(!"invalid condition code");
271 break;
272 }
273 code[pos / 32] |= val << (pos % 32);
274 }
275
276 void
277 CodeEmitterNVC0::emitPredicate(const Instruction *i)
278 {
279 if (i->predSrc >= 0) {
280 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
281 srcId(i->src(i->predSrc), 10);
282 if (i->cc == CC_NOT_P)
283 code[0] |= 0x2000; // negate
284 } else {
285 code[0] |= 0x1c00;
286 }
287 }
288
289 void
290 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
291 {
292 switch (src.getFile()) {
293 case FILE_MEMORY_GLOBAL:
294 srcAddr32(src, 26, 0);
295 break;
296 case FILE_MEMORY_LOCAL:
297 case FILE_MEMORY_SHARED:
298 setAddress24(src);
299 break;
300 default:
301 assert(src.getFile() == FILE_MEMORY_CONST);
302 setAddress16(src);
303 break;
304 }
305 }
306
307 void
308 CodeEmitterNVC0::setAddress16(const ValueRef& src)
309 {
310 Symbol *sym = src.get()->asSym();
311
312 assert(sym);
313
314 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
315 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
316 }
317
318 void
319 CodeEmitterNVC0::setAddress24(const ValueRef& src)
320 {
321 Symbol *sym = src.get()->asSym();
322
323 assert(sym);
324
325 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
326 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
327 }
328
329 void
330 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
331 {
332 const ImmediateValue *imm = i->src(s).get()->asImm();
333 uint32_t u32;
334
335 assert(imm);
336 u32 = imm->reg.data.u32;
337
338 if ((code[0] & 0xf) == 0x1) {
339 // double immediate
340 uint64_t u64 = imm->reg.data.u64;
341 assert(!(u64 & 0x00000fffffffffffULL));
342 assert(!(code[1] & 0xc000));
343 code[0] |= ((u64 >> 44) & 0x3f) << 26;
344 code[1] |= 0xc000 | (u64 >> 50);
345 } else
346 if ((code[0] & 0xf) == 0x2) {
347 // LIMM
348 code[0] |= (u32 & 0x3f) << 26;
349 code[1] |= u32 >> 6;
350 } else
351 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
352 // integer immediate
353 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
354 assert(!(code[1] & 0xc000));
355 u32 &= 0xfffff;
356 code[0] |= (u32 & 0x3f) << 26;
357 code[1] |= 0xc000 | (u32 >> 6);
358 } else {
359 // float immediate
360 assert(!(u32 & 0x00000fff));
361 assert(!(code[1] & 0xc000));
362 code[0] |= ((u32 >> 12) & 0x3f) << 26;
363 code[1] |= 0xc000 | (u32 >> 18);
364 }
365 }
366
367 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
368 {
369 const ImmediateValue *imm = ref.get()->asImm();
370
371 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
372
373 assert(s8 == imm->reg.data.s32);
374
375 code[0] |= (s8 & 0x3f) << 26;
376 code[0] |= (s8 >> 6) << 8;
377 }
378
379 void CodeEmitterNVC0::setPDSTL(const Instruction *i, const int d)
380 {
381 assert(d < 0 || (i->defExists(d) && i->def(d).getFile() == FILE_PREDICATE));
382
383 uint32_t pred = d >= 0 ? DDATA(i->def(d)).id : 7;
384
385 code[0] |= (pred & 3) << 8;
386 code[1] |= (pred & 4) << (26 - 2);
387 }
388
389 void
390 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
391 {
392 code[0] = opc;
393 code[1] = opc >> 32;
394
395 emitPredicate(i);
396
397 defId(i->def(0), 14);
398
399 int s1 = 26;
400 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
401 s1 = 49;
402
403 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
404 switch (i->getSrc(s)->reg.file) {
405 case FILE_MEMORY_CONST:
406 assert(!(code[1] & 0xc000));
407 code[1] |= (s == 2) ? 0x8000 : 0x4000;
408 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
409 setAddress16(i->src(s));
410 break;
411 case FILE_IMMEDIATE:
412 assert(s == 1 ||
413 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
414 assert(!(code[1] & 0xc000));
415 setImmediate(i, s);
416 break;
417 case FILE_GPR:
418 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
419 break;
420 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
421 break;
422 default:
423 if (i->op == OP_SELP) {
424 // OP_SELP is used to implement shared+atomics on Fermi.
425 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
426 srcId(i->src(s), 49);
427 }
428 // ignore here, can be predicate or flags, but must not be address
429 break;
430 }
431 }
432 }
433
434 void
435 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
436 {
437 code[0] = opc;
438 code[1] = opc >> 32;
439
440 emitPredicate(i);
441
442 defId(i->def(0), 14);
443
444 switch (i->src(0).getFile()) {
445 case FILE_MEMORY_CONST:
446 assert(!(code[1] & 0xc000));
447 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
448 setAddress16(i->src(0));
449 break;
450 case FILE_IMMEDIATE:
451 assert(!(code[1] & 0xc000));
452 setImmediate(i, 0);
453 break;
454 case FILE_GPR:
455 srcId(i->src(0), 26);
456 break;
457 default:
458 // ignore here, can be predicate or flags, but must not be address
459 break;
460 }
461 }
462
463 void
464 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
465 {
466 code[0] = opc;
467
468 int ss2a = 0;
469 if (opc == 0x0d || opc == 0x0e)
470 ss2a = 2;
471
472 defId(i->def(0), 14);
473 srcId(i->src(0), 20);
474
475 assert(pred || (i->predSrc < 0));
476 if (pred)
477 emitPredicate(i);
478
479 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
480 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
481 assert(!(code[0] & (0x300 >> ss2a)));
482 switch (i->src(s).get()->reg.fileIndex) {
483 case 0: code[0] |= 0x100 >> ss2a; break;
484 case 1: code[0] |= 0x200 >> ss2a; break;
485 case 16: code[0] |= 0x300 >> ss2a; break;
486 default:
487 ERROR("invalid c[] space for short form\n");
488 break;
489 }
490 if (s == 1)
491 code[0] |= i->getSrc(s)->reg.data.offset << 24;
492 else
493 code[0] |= i->getSrc(s)->reg.data.offset << 6;
494 } else
495 if (i->src(s).getFile() == FILE_IMMEDIATE) {
496 assert(s == 1);
497 setImmediateS8(i->src(s));
498 } else
499 if (i->src(s).getFile() == FILE_GPR) {
500 srcId(i->src(s), (s == 1) ? 26 : 8);
501 }
502 }
503 }
504
505 void
506 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
507 {
508 if (src.getFile() == FILE_MEMORY_CONST) {
509 switch (src.get()->reg.fileIndex) {
510 case 0: code[0] |= 0x100; break;
511 case 1: code[0] |= 0x200; break;
512 case 16: code[0] |= 0x300; break;
513 default:
514 assert(!"unsupported file index for short op");
515 break;
516 }
517 srcAddr32(src, 20, 2);
518 } else {
519 srcId(src, 20);
520 assert(src.getFile() == FILE_GPR);
521 }
522 }
523
524 void
525 CodeEmitterNVC0::emitNOP(const Instruction *i)
526 {
527 code[0] = 0x000001e4;
528 code[1] = 0x40000000;
529 emitPredicate(i);
530 }
531
532 void
533 CodeEmitterNVC0::emitFMAD(const Instruction *i)
534 {
535 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
536
537 if (i->encSize == 8) {
538 if (isLIMM(i->src(1), TYPE_F32)) {
539 emitForm_A(i, HEX64(20000000, 00000002));
540 } else {
541 emitForm_A(i, HEX64(30000000, 00000000));
542
543 if (i->src(2).mod.neg())
544 code[0] |= 1 << 8;
545 }
546 roundMode_A(i);
547
548 if (neg1)
549 code[0] |= 1 << 9;
550
551 if (i->saturate)
552 code[0] |= 1 << 5;
553
554 if (i->dnz)
555 code[0] |= 1 << 7;
556 else
557 if (i->ftz)
558 code[0] |= 1 << 6;
559 } else {
560 assert(!i->saturate && !i->src(2).mod.neg());
561 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
562 false);
563 if (neg1)
564 code[0] |= 1 << 4;
565 }
566 }
567
568 void
569 CodeEmitterNVC0::emitDMAD(const Instruction *i)
570 {
571 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
572
573 emitForm_A(i, HEX64(20000000, 00000001));
574
575 if (i->src(2).mod.neg())
576 code[0] |= 1 << 8;
577
578 roundMode_A(i);
579
580 if (neg1)
581 code[0] |= 1 << 9;
582
583 assert(!i->saturate);
584 assert(!i->ftz);
585 }
586
587 void
588 CodeEmitterNVC0::emitFMUL(const Instruction *i)
589 {
590 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
591
592 assert(i->postFactor >= -3 && i->postFactor <= 3);
593
594 if (i->encSize == 8) {
595 if (isLIMM(i->src(1), TYPE_F32)) {
596 assert(i->postFactor == 0); // constant folded, hopefully
597 emitForm_A(i, HEX64(30000000, 00000002));
598 } else {
599 emitForm_A(i, HEX64(58000000, 00000000));
600 roundMode_A(i);
601 code[1] |= ((i->postFactor > 0) ?
602 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
603 }
604 if (neg)
605 code[1] ^= 1 << 25; // aliases with LIMM sign bit
606
607 if (i->saturate)
608 code[0] |= 1 << 5;
609
610 if (i->dnz)
611 code[0] |= 1 << 7;
612 else
613 if (i->ftz)
614 code[0] |= 1 << 6;
615 } else {
616 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
617 emitForm_S(i, 0xa8, true);
618 }
619 }
620
621 void
622 CodeEmitterNVC0::emitDMUL(const Instruction *i)
623 {
624 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
625
626 emitForm_A(i, HEX64(50000000, 00000001));
627 roundMode_A(i);
628
629 if (neg)
630 code[0] |= 1 << 9;
631
632 assert(!i->saturate);
633 assert(!i->ftz);
634 assert(!i->dnz);
635 assert(!i->postFactor);
636 }
637
638 void
639 CodeEmitterNVC0::emitUMUL(const Instruction *i)
640 {
641 if (i->encSize == 8) {
642 if (i->src(1).getFile() == FILE_IMMEDIATE) {
643 emitForm_A(i, HEX64(10000000, 00000002));
644 } else {
645 emitForm_A(i, HEX64(50000000, 00000003));
646 }
647 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
648 code[0] |= 1 << 6;
649 if (i->sType == TYPE_S32)
650 code[0] |= 1 << 5;
651 if (i->dType == TYPE_S32)
652 code[0] |= 1 << 7;
653 } else {
654 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
655
656 if (i->sType == TYPE_S32)
657 code[0] |= 1 << 6;
658 }
659 }
660
661 void
662 CodeEmitterNVC0::emitFADD(const Instruction *i)
663 {
664 if (i->encSize == 8) {
665 if (isLIMM(i->src(1), TYPE_F32)) {
666 assert(!i->saturate);
667 emitForm_A(i, HEX64(28000000, 00000002));
668
669 code[0] |= i->src(0).mod.abs() << 7;
670 code[0] |= i->src(0).mod.neg() << 9;
671
672 if (i->src(1).mod.abs())
673 code[1] &= 0xfdffffff;
674 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
675 code[1] ^= 0x02000000;
676 } else {
677 emitForm_A(i, HEX64(50000000, 00000000));
678
679 roundMode_A(i);
680 if (i->saturate)
681 code[1] |= 1 << 17;
682
683 emitNegAbs12(i);
684 if (i->op == OP_SUB) code[0] ^= 1 << 8;
685 }
686 if (i->ftz)
687 code[0] |= 1 << 5;
688 } else {
689 assert(!i->saturate && i->op != OP_SUB &&
690 !i->src(0).mod.abs() &&
691 !i->src(1).mod.neg() && !i->src(1).mod.abs());
692
693 emitForm_S(i, 0x49, true);
694
695 if (i->src(0).mod.neg())
696 code[0] |= 1 << 7;
697 }
698 }
699
700 void
701 CodeEmitterNVC0::emitDADD(const Instruction *i)
702 {
703 assert(i->encSize == 8);
704 emitForm_A(i, HEX64(48000000, 00000001));
705 roundMode_A(i);
706 assert(!i->saturate);
707 assert(!i->ftz);
708 emitNegAbs12(i);
709 if (i->op == OP_SUB)
710 code[0] ^= 1 << 8;
711 }
712
713 void
714 CodeEmitterNVC0::emitUADD(const Instruction *i)
715 {
716 uint32_t addOp = 0;
717
718 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
719
720 if (i->src(0).mod.neg())
721 addOp |= 0x200;
722 if (i->src(1).mod.neg())
723 addOp |= 0x100;
724 if (i->op == OP_SUB)
725 addOp ^= 0x100;
726
727 assert(addOp != 0x300); // would be add-plus-one
728
729 if (i->encSize == 8) {
730 if (isLIMM(i->src(1), TYPE_U32)) {
731 emitForm_A(i, HEX64(08000000, 00000002));
732 if (i->flagsDef >= 0)
733 code[1] |= 1 << 26; // write carry
734 } else {
735 emitForm_A(i, HEX64(48000000, 00000003));
736 if (i->flagsDef >= 0)
737 code[1] |= 1 << 16; // write carry
738 }
739 code[0] |= addOp;
740
741 if (i->saturate)
742 code[0] |= 1 << 5;
743 if (i->flagsSrc >= 0) // add carry
744 code[0] |= 1 << 6;
745 } else {
746 assert(!(addOp & 0x100));
747 emitForm_S(i, (addOp >> 3) |
748 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
749 }
750 }
751
752 void
753 CodeEmitterNVC0::emitIMAD(const Instruction *i)
754 {
755 uint8_t addOp =
756 i->src(2).mod.neg() | ((i->src(0).mod.neg() ^ i->src(1).mod.neg()) << 1);
757
758 assert(i->encSize == 8);
759 emitForm_A(i, HEX64(20000000, 00000003));
760
761 assert(addOp != 3);
762 code[0] |= addOp << 8;
763
764 if (isSignedType(i->dType))
765 code[0] |= 1 << 7;
766 if (isSignedType(i->sType))
767 code[0] |= 1 << 5;
768
769 code[1] |= i->saturate << 24;
770
771 if (i->flagsDef >= 0) code[1] |= 1 << 16;
772 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
773
774 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
775 code[0] |= 1 << 6;
776 }
777
778 void
779 CodeEmitterNVC0::emitSHLADD(const Instruction *i)
780 {
781 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(2).mod.neg();
782 const ImmediateValue *imm = i->src(1).get()->asImm();
783 assert(imm);
784
785 code[0] = 0x00000003;
786 code[1] = 0x40000000 | addOp << 23;
787
788 emitPredicate(i);
789
790 defId(i->def(0), 14);
791 srcId(i->src(0), 20);
792
793 if (i->flagsDef >= 0)
794 code[1] |= 1 << 16;
795
796 assert(!(imm->reg.data.u32 & 0xffffffe0));
797 code[0] |= imm->reg.data.u32 << 5;
798
799 switch (i->src(2).getFile()) {
800 case FILE_GPR:
801 srcId(i->src(2), 26);
802 break;
803 case FILE_MEMORY_CONST:
804 code[1] |= 0x4000;
805 code[1] |= i->getSrc(2)->reg.fileIndex << 10;
806 setAddress16(i->src(2));
807 break;
808 case FILE_IMMEDIATE:
809 setImmediate(i, 2);
810 break;
811 default:
812 assert(!"bad src2 file");
813 break;
814 }
815 }
816
817 void
818 CodeEmitterNVC0::emitMADSP(const Instruction *i)
819 {
820 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
821
822 emitForm_A(i, HEX64(00000000, 00000003));
823
824 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
825 code[1] |= 0x01800000;
826 } else {
827 code[0] |= (i->subOp & 0x00f) << 7;
828 code[0] |= (i->subOp & 0x0f0) << 1;
829 code[0] |= (i->subOp & 0x100) >> 3;
830 code[0] |= (i->subOp & 0x200) >> 2;
831 code[1] |= (i->subOp & 0xc00) << 13;
832 }
833
834 if (i->flagsDef >= 0)
835 code[1] |= 1 << 16;
836 }
837
838 void
839 CodeEmitterNVC0::emitISAD(const Instruction *i)
840 {
841 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
842 assert(i->encSize == 8);
843
844 emitForm_A(i, HEX64(38000000, 00000003));
845
846 if (i->dType == TYPE_S32)
847 code[0] |= 1 << 5;
848 }
849
850 void
851 CodeEmitterNVC0::emitNOT(Instruction *i)
852 {
853 assert(i->encSize == 8);
854 i->setSrc(1, i->src(0));
855 emitForm_A(i, HEX64(68000000, 000001c3));
856 }
857
858 void
859 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
860 {
861 if (i->def(0).getFile() == FILE_PREDICATE) {
862 code[0] = 0x00000004 | (subOp << 30);
863 code[1] = 0x0c000000;
864
865 emitPredicate(i);
866
867 defId(i->def(0), 17);
868 srcId(i->src(0), 20);
869 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
870 srcId(i->src(1), 26);
871 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
872
873 if (i->defExists(1)) {
874 defId(i->def(1), 14);
875 } else {
876 code[0] |= 7 << 14;
877 }
878 // (a OP b) OP c
879 if (i->predSrc != 2 && i->srcExists(2)) {
880 code[1] |= subOp << 21;
881 srcId(i->src(2), 49);
882 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 20;
883 } else {
884 code[1] |= 0x000e0000;
885 }
886 } else
887 if (i->encSize == 8) {
888 if (isLIMM(i->src(1), TYPE_U32)) {
889 emitForm_A(i, HEX64(38000000, 00000002));
890
891 if (i->flagsDef >= 0)
892 code[1] |= 1 << 26;
893 } else {
894 emitForm_A(i, HEX64(68000000, 00000003));
895
896 if (i->flagsDef >= 0)
897 code[1] |= 1 << 16;
898 }
899 code[0] |= subOp << 6;
900
901 if (i->flagsSrc >= 0) // carry
902 code[0] |= 1 << 5;
903
904 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
905 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
906 } else {
907 emitForm_S(i, (subOp << 5) |
908 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
909 }
910 }
911
912 void
913 CodeEmitterNVC0::emitPOPC(const Instruction *i)
914 {
915 emitForm_A(i, HEX64(54000000, 00000004));
916
917 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
918 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
919 }
920
921 void
922 CodeEmitterNVC0::emitINSBF(const Instruction *i)
923 {
924 emitForm_A(i, HEX64(28000000, 00000003));
925 }
926
927 void
928 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
929 {
930 emitForm_A(i, HEX64(70000000, 00000003));
931
932 if (i->dType == TYPE_S32)
933 code[0] |= 1 << 5;
934 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
935 code[0] |= 1 << 8;
936 }
937
938 void
939 CodeEmitterNVC0::emitBFIND(const Instruction *i)
940 {
941 emitForm_B(i, HEX64(78000000, 00000003));
942
943 if (i->dType == TYPE_S32)
944 code[0] |= 1 << 5;
945 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
946 code[0] |= 1 << 8;
947 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
948 code[0] |= 1 << 6;
949 }
950
951 void
952 CodeEmitterNVC0::emitPERMT(const Instruction *i)
953 {
954 emitForm_A(i, HEX64(24000000, 00000004));
955
956 code[0] |= i->subOp << 5;
957 }
958
959 void
960 CodeEmitterNVC0::emitShift(const Instruction *i)
961 {
962 if (i->op == OP_SHR) {
963 emitForm_A(i, HEX64(58000000, 00000003)
964 | (isSignedType(i->dType) ? 0x20 : 0x00));
965 } else {
966 emitForm_A(i, HEX64(60000000, 00000003));
967 }
968
969 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
970 code[0] |= 1 << 9;
971 }
972
973 void
974 CodeEmitterNVC0::emitPreOp(const Instruction *i)
975 {
976 if (i->encSize == 8) {
977 emitForm_B(i, HEX64(60000000, 00000000));
978
979 if (i->op == OP_PREEX2)
980 code[0] |= 0x20;
981
982 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
983 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
984 } else {
985 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
986 }
987 }
988
989 void
990 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
991 {
992 if (i->encSize == 8) {
993 code[0] = 0x00000000 | (subOp << 26);
994 code[1] = 0xc8000000;
995
996 emitPredicate(i);
997
998 defId(i->def(0), 14);
999 srcId(i->src(0), 20);
1000
1001 assert(i->src(0).getFile() == FILE_GPR);
1002
1003 if (i->saturate) code[0] |= 1 << 5;
1004
1005 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
1006 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
1007 } else {
1008 emitForm_S(i, 0x80000008 | (subOp << 26), true);
1009
1010 assert(!i->src(0).mod.neg());
1011 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
1012 }
1013 }
1014
1015 void
1016 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
1017 {
1018 uint64_t op;
1019
1020 assert(i->encSize == 8);
1021
1022 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
1023
1024 if (i->ftz)
1025 op |= 1 << 5;
1026 else
1027 if (!isFloatType(i->dType)) {
1028 op |= isSignedType(i->dType) ? 0x23 : 0x03;
1029 op |= i->subOp << 6;
1030 }
1031 if (i->dType == TYPE_F64)
1032 op |= 0x01;
1033
1034 emitForm_A(i, op);
1035 emitNegAbs12(i);
1036
1037 if (i->flagsDef >= 0)
1038 code[1] |= 1 << 16;
1039 }
1040
1041 void
1042 CodeEmitterNVC0::roundMode_C(const Instruction *i)
1043 {
1044 switch (i->rnd) {
1045 case ROUND_M: code[1] |= 1 << 17; break;
1046 case ROUND_P: code[1] |= 2 << 17; break;
1047 case ROUND_Z: code[1] |= 3 << 17; break;
1048 case ROUND_NI: code[0] |= 1 << 7; break;
1049 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
1050 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
1051 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
1052 case ROUND_N: break;
1053 default:
1054 assert(!"invalid round mode");
1055 break;
1056 }
1057 }
1058
1059 void
1060 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
1061 {
1062 switch (i->rnd) {
1063 case ROUND_M:
1064 case ROUND_MI: code[0] |= 1 << 16; break;
1065 case ROUND_P:
1066 case ROUND_PI: code[0] |= 2 << 16; break;
1067 case ROUND_Z:
1068 case ROUND_ZI: code[0] |= 3 << 16; break;
1069 default:
1070 break;
1071 }
1072 }
1073
1074 void
1075 CodeEmitterNVC0::emitCVT(Instruction *i)
1076 {
1077 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1078 DataType dType;
1079
1080 switch (i->op) {
1081 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1082 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1083 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1084 default:
1085 break;
1086 }
1087
1088 const bool sat = (i->op == OP_SAT) || i->saturate;
1089 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1090 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1091
1092 if (i->op == OP_NEG && i->dType == TYPE_U32)
1093 dType = TYPE_S32;
1094 else
1095 dType = i->dType;
1096
1097 if (i->encSize == 8) {
1098 emitForm_B(i, HEX64(10000000, 00000004));
1099
1100 roundMode_C(i);
1101
1102 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1103 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1104 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1105
1106 // for 8/16 source types, the byte/word is in subOp. word 1 is
1107 // represented as 2.
1108 if (!isFloatType(i->sType))
1109 code[1] |= i->subOp << 0x17;
1110 else
1111 code[1] |= i->subOp << 0x18;
1112
1113 if (sat)
1114 code[0] |= 0x20;
1115 if (abs)
1116 code[0] |= 1 << 6;
1117 if (neg && i->op != OP_ABS)
1118 code[0] |= 1 << 8;
1119
1120 if (i->ftz)
1121 code[1] |= 1 << 23;
1122
1123 if (isSignedIntType(dType))
1124 code[0] |= 0x080;
1125 if (isSignedIntType(i->sType))
1126 code[0] |= 0x200;
1127
1128 if (isFloatType(dType)) {
1129 if (!isFloatType(i->sType))
1130 code[1] |= 0x08000000;
1131 } else {
1132 if (isFloatType(i->sType))
1133 code[1] |= 0x04000000;
1134 else
1135 code[1] |= 0x0c000000;
1136 }
1137 } else {
1138 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1139 code[0] = 0x298;
1140 } else
1141 if (isFloatType(dType)) {
1142 if (isFloatType(i->sType))
1143 code[0] = 0x098;
1144 else
1145 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1146 } else {
1147 assert(isFloatType(i->sType));
1148
1149 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1150 }
1151
1152 if (neg) code[0] |= 1 << 16;
1153 if (sat) code[0] |= 1 << 18;
1154 if (abs) code[0] |= 1 << 19;
1155
1156 roundMode_CS(i);
1157 }
1158 }
1159
1160 void
1161 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1162 {
1163 uint32_t hi;
1164 uint32_t lo = 0;
1165
1166 if (i->sType == TYPE_F64)
1167 lo = 0x1;
1168 else
1169 if (!isFloatType(i->sType))
1170 lo = 0x3;
1171
1172 if (isSignedIntType(i->sType))
1173 lo |= 0x20;
1174 if (isFloatType(i->dType)) {
1175 if (isFloatType(i->sType))
1176 lo |= 0x20;
1177 else
1178 lo |= 0x80;
1179 }
1180
1181 switch (i->op) {
1182 case OP_SET_AND: hi = 0x10000000; break;
1183 case OP_SET_OR: hi = 0x10200000; break;
1184 case OP_SET_XOR: hi = 0x10400000; break;
1185 default:
1186 hi = 0x100e0000;
1187 break;
1188 }
1189 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1190
1191 if (i->op != OP_SET)
1192 srcId(i->src(2), 32 + 17);
1193
1194 if (i->def(0).getFile() == FILE_PREDICATE) {
1195 if (i->sType == TYPE_F32)
1196 code[1] += 0x10000000;
1197 else
1198 code[1] += 0x08000000;
1199
1200 code[0] &= ~0xfc000;
1201 defId(i->def(0), 17);
1202 if (i->defExists(1))
1203 defId(i->def(1), 14);
1204 else
1205 code[0] |= 0x1c000;
1206 }
1207
1208 if (i->ftz)
1209 code[1] |= 1 << 27;
1210 if (i->flagsSrc >= 0)
1211 code[0] |= 1 << 6;
1212
1213 emitCondCode(i->setCond, 32 + 23);
1214 emitNegAbs12(i);
1215 }
1216
1217 void
1218 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1219 {
1220 uint64_t op;
1221
1222 switch (i->dType) {
1223 case TYPE_S32:
1224 op = HEX64(30000000, 00000023);
1225 break;
1226 case TYPE_U32:
1227 op = HEX64(30000000, 00000003);
1228 break;
1229 case TYPE_F32:
1230 op = HEX64(38000000, 00000000);
1231 break;
1232 default:
1233 assert(!"invalid type for SLCT");
1234 op = 0;
1235 break;
1236 }
1237 emitForm_A(i, op);
1238
1239 CondCode cc = i->setCond;
1240
1241 if (i->src(2).mod.neg())
1242 cc = reverseCondCode(cc);
1243
1244 emitCondCode(cc, 32 + 23);
1245
1246 if (i->ftz)
1247 code[0] |= 1 << 5;
1248 }
1249
1250 static void
1251 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1252 {
1253 int loc = entry->loc;
1254 if (data.force_persample_interp)
1255 code[loc + 1] |= 1 << 20;
1256 else
1257 code[loc + 1] &= ~(1 << 20);
1258 }
1259
1260 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1261 {
1262 emitForm_A(i, HEX64(20000000, 00000004));
1263
1264 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1265 code[1] |= 1 << 20;
1266
1267 if (i->subOp == 1) {
1268 addInterp(0, 0, selpFlip);
1269 }
1270 }
1271
1272 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1273 {
1274 code[0] = 0x00000006 | (i->subOp << 26);
1275 code[1] = 0xf0000000;
1276 emitPredicate(i);
1277 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1278 }
1279
1280 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1281 {
1282 code[0] = 0x00000086;
1283 code[1] = 0xd0000000;
1284
1285 code[1] |= i->tex.r;
1286 code[1] |= i->tex.s << 8;
1287
1288 if (i->tex.liveOnly)
1289 code[0] |= 1 << 9;
1290
1291 defId(i->def(0), 14);
1292 srcId(i->src(0), 20);
1293 }
1294
1295 static inline bool
1296 isNextIndependentTex(const TexInstruction *i)
1297 {
1298 if (!i->next || !isTextureOp(i->next->op))
1299 return false;
1300 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1301 return false;
1302 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1303 }
1304
1305 void
1306 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1307 {
1308 code[0] = 0x00000006;
1309
1310 if (isNextIndependentTex(i))
1311 code[0] |= 0x080; // t mode
1312 else
1313 code[0] |= 0x100; // p mode
1314
1315 if (i->tex.liveOnly)
1316 code[0] |= 1 << 9;
1317
1318 switch (i->op) {
1319 case OP_TEX: code[1] = 0x80000000; break;
1320 case OP_TXB: code[1] = 0x84000000; break;
1321 case OP_TXL: code[1] = 0x86000000; break;
1322 case OP_TXF: code[1] = 0x90000000; break;
1323 case OP_TXG: code[1] = 0xa0000000; break;
1324 case OP_TXLQ: code[1] = 0xb0000000; break;
1325 case OP_TXD: code[1] = 0xe0000000; break;
1326 default:
1327 assert(!"invalid texture op");
1328 break;
1329 }
1330 if (i->op == OP_TXF) {
1331 if (!i->tex.levelZero)
1332 code[1] |= 0x02000000;
1333 } else
1334 if (i->tex.levelZero) {
1335 code[1] |= 0x02000000;
1336 }
1337
1338 if (i->op != OP_TXD && i->tex.derivAll)
1339 code[1] |= 1 << 13;
1340
1341 defId(i->def(0), 14);
1342 srcId(i->src(0), 20);
1343
1344 emitPredicate(i);
1345
1346 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1347
1348 code[1] |= i->tex.mask << 14;
1349
1350 code[1] |= i->tex.r;
1351 code[1] |= i->tex.s << 8;
1352 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1353 code[1] |= 1 << 18; // in 1st source (with array index)
1354
1355 // texture target:
1356 code[1] |= (i->tex.target.getDim() - 1) << 20;
1357 if (i->tex.target.isCube())
1358 code[1] += 2 << 20;
1359 if (i->tex.target.isArray())
1360 code[1] |= 1 << 19;
1361 if (i->tex.target.isShadow())
1362 code[1] |= 1 << 24;
1363
1364 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1365
1366 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1367 // lzero
1368 if (i->op == OP_TXL)
1369 code[1] &= ~(1 << 26);
1370 else
1371 if (i->op == OP_TXF)
1372 code[1] &= ~(1 << 25);
1373 }
1374 if (i->tex.target == TEX_TARGET_2D_MS ||
1375 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1376 code[1] |= 1 << 23;
1377
1378 if (i->tex.useOffsets == 1)
1379 code[1] |= 1 << 22;
1380 if (i->tex.useOffsets == 4)
1381 code[1] |= 1 << 23;
1382
1383 srcId(i, src1, 26);
1384 }
1385
1386 void
1387 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1388 {
1389 code[0] = 0x00000086;
1390 code[1] = 0xc0000000;
1391
1392 switch (i->tex.query) {
1393 case TXQ_DIMS: code[1] |= 0 << 22; break;
1394 case TXQ_TYPE: code[1] |= 1 << 22; break;
1395 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1396 case TXQ_FILTER: code[1] |= 3 << 22; break;
1397 case TXQ_LOD: code[1] |= 4 << 22; break;
1398 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1399 default:
1400 assert(!"invalid texture query");
1401 break;
1402 }
1403
1404 code[1] |= i->tex.mask << 14;
1405
1406 code[1] |= i->tex.r;
1407 code[1] |= i->tex.s << 8;
1408 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1409 code[1] |= 1 << 18;
1410
1411 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1412
1413 defId(i->def(0), 14);
1414 srcId(i->src(0), 20);
1415 srcId(i, src1, 26);
1416
1417 emitPredicate(i);
1418 }
1419
1420 void
1421 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1422 {
1423 code[0] = 0x00000200 | (laneMask << 6); // dall
1424 code[1] = 0x48000000 | qOp;
1425
1426 defId(i->def(0), 14);
1427 srcId(i->src(0), 20);
1428 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1429
1430 emitPredicate(i);
1431 }
1432
1433 void
1434 CodeEmitterNVC0::emitFlow(const Instruction *i)
1435 {
1436 const FlowInstruction *f = i->asFlow();
1437
1438 unsigned mask; // bit 0: predicate, bit 1: target
1439
1440 code[0] = 0x00000007;
1441
1442 switch (i->op) {
1443 case OP_BRA:
1444 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1445 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1446 code[0] |= 0x4000;
1447 mask = 3;
1448 break;
1449 case OP_CALL:
1450 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1451 if (f->indirect)
1452 code[0] |= 0x4000; // indirect calls always use c[] source
1453 mask = 2;
1454 break;
1455
1456 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1457 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1458 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1459 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1460 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1461
1462 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1463 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1464 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1465 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1466
1467 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1468 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1469 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1470 default:
1471 assert(!"invalid flow operation");
1472 return;
1473 }
1474
1475 if (mask & 1) {
1476 emitPredicate(i);
1477 if (i->flagsSrc < 0)
1478 code[0] |= 0x1e0;
1479 }
1480
1481 if (!f)
1482 return;
1483
1484 if (f->allWarp)
1485 code[0] |= 1 << 15;
1486 if (f->limit)
1487 code[0] |= 1 << 16;
1488
1489 if (f->indirect) {
1490 if (code[0] & 0x4000) {
1491 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1492 setAddress16(i->src(0));
1493 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1494 if (f->op == OP_BRA)
1495 srcId(f->src(0).getIndirect(0), 20);
1496 } else {
1497 srcId(f, 0, 20);
1498 }
1499 }
1500
1501 if (f->op == OP_CALL) {
1502 if (f->indirect) {
1503 // nothing
1504 } else
1505 if (f->builtin) {
1506 assert(f->absolute);
1507 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1508 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1509 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1510 } else {
1511 assert(!f->absolute);
1512 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1513 code[0] |= (pcRel & 0x3f) << 26;
1514 code[1] |= (pcRel >> 6) & 0x3ffff;
1515 }
1516 } else
1517 if (mask & 2) {
1518 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1519 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1520 pcRel += 8;
1521 // currently we don't want absolute branches
1522 assert(!f->absolute);
1523 code[0] |= (pcRel & 0x3f) << 26;
1524 code[1] |= (pcRel >> 6) & 0x3ffff;
1525 }
1526 }
1527
1528 void
1529 CodeEmitterNVC0::emitBAR(const Instruction *i)
1530 {
1531 Value *rDef = NULL, *pDef = NULL;
1532
1533 switch (i->subOp) {
1534 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1535 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1536 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1537 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1538 default:
1539 code[0] = 0x04;
1540 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1541 break;
1542 }
1543 code[1] = 0x50000000;
1544
1545 code[0] |= 63 << 14;
1546 code[1] |= 7 << 21;
1547
1548 emitPredicate(i);
1549
1550 // barrier id
1551 if (i->src(0).getFile() == FILE_GPR) {
1552 srcId(i->src(0), 20);
1553 } else {
1554 ImmediateValue *imm = i->getSrc(0)->asImm();
1555 assert(imm);
1556 code[0] |= imm->reg.data.u32 << 20;
1557 code[1] |= 0x8000;
1558 }
1559
1560 // thread count
1561 if (i->src(1).getFile() == FILE_GPR) {
1562 srcId(i->src(1), 26);
1563 } else {
1564 ImmediateValue *imm = i->getSrc(1)->asImm();
1565 assert(imm);
1566 assert(imm->reg.data.u32 <= 0xfff);
1567 code[0] |= imm->reg.data.u32 << 26;
1568 code[1] |= imm->reg.data.u32 >> 6;
1569 code[1] |= 0x4000;
1570 }
1571
1572 if (i->srcExists(2) && (i->predSrc != 2)) {
1573 srcId(i->src(2), 32 + 17);
1574 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1575 code[1] |= 1 << 20;
1576 } else {
1577 code[1] |= 7 << 17;
1578 }
1579
1580 if (i->defExists(0)) {
1581 if (i->def(0).getFile() == FILE_GPR)
1582 rDef = i->getDef(0);
1583 else
1584 pDef = i->getDef(0);
1585
1586 if (i->defExists(1)) {
1587 if (i->def(1).getFile() == FILE_GPR)
1588 rDef = i->getDef(1);
1589 else
1590 pDef = i->getDef(1);
1591 }
1592 }
1593 if (rDef) {
1594 code[0] &= ~(63 << 14);
1595 defId(rDef, 14);
1596 }
1597 if (pDef) {
1598 code[1] &= ~(7 << 21);
1599 defId(pDef, 32 + 21);
1600 }
1601 }
1602
1603 void
1604 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1605 {
1606 code[0] = 0x00000006;
1607 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1608
1609 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1610 code[0] |= 0x200;
1611
1612 emitPredicate(i);
1613
1614 defId(i->def(0), 14);
1615 srcId(i->src(0).getIndirect(0), 20);
1616 }
1617
1618 void
1619 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1620 {
1621 uint32_t prim = i->src(0).get()->reg.data.u32;
1622
1623 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1624 code[1] = 0x00000000 | (prim >> 6);
1625
1626 emitPredicate(i);
1627
1628 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1629
1630 defId(i->def(0), 14);
1631 srcId(i, src1, 20);
1632 }
1633
1634 void
1635 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1636 {
1637 code[0] = 0x00000006;
1638 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1639
1640 if (i->perPatch)
1641 code[0] |= 0x100;
1642 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1643 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1644
1645 emitPredicate(i);
1646
1647 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1648
1649 defId(i->def(0), 14);
1650 srcId(i->src(0).getIndirect(0), 20);
1651 srcId(i->src(0).getIndirect(1), 26); // vertex address
1652 }
1653
1654 void
1655 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1656 {
1657 unsigned int size = typeSizeof(i->dType);
1658
1659 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1660 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1661
1662 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1663
1664 if (i->perPatch)
1665 code[0] |= 0x100;
1666
1667 emitPredicate(i);
1668
1669 assert(i->src(1).getFile() == FILE_GPR);
1670
1671 srcId(i->src(0).getIndirect(0), 20);
1672 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1673 srcId(i->src(1), 26);
1674 }
1675
1676 void
1677 CodeEmitterNVC0::emitOUT(const Instruction *i)
1678 {
1679 code[0] = 0x00000006;
1680 code[1] = 0x1c000000;
1681
1682 emitPredicate(i);
1683
1684 defId(i->def(0), 14); // new secret address
1685 srcId(i->src(0), 20); // old secret address, should be 0 initially
1686
1687 assert(i->src(0).getFile() == FILE_GPR);
1688
1689 if (i->op == OP_EMIT)
1690 code[0] |= 1 << 5;
1691 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1692 code[0] |= 1 << 6;
1693
1694 // vertex stream
1695 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1696 unsigned int stream = SDATA(i->src(1)).u32;
1697 assert(stream < 4);
1698 if (stream) {
1699 code[1] |= 0xc000;
1700 code[0] |= stream << 26;
1701 } else {
1702 srcId(NULL, 26);
1703 }
1704 } else {
1705 srcId(i->src(1), 26);
1706 }
1707 }
1708
1709 void
1710 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1711 {
1712 if (i->encSize == 8) {
1713 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1714 } else {
1715 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1716 code[0] |= 0x80;
1717 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1718 }
1719 }
1720
1721 static void
1722 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1723 {
1724 int ipa = entry->ipa;
1725 int reg = entry->reg;
1726 int loc = entry->loc;
1727
1728 if (data.flatshade &&
1729 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1730 ipa = NV50_IR_INTERP_FLAT;
1731 reg = 0x3f;
1732 } else if (data.force_persample_interp &&
1733 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1734 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1735 ipa |= NV50_IR_INTERP_CENTROID;
1736 }
1737 code[loc + 0] &= ~(0xf << 6);
1738 code[loc + 0] |= ipa << 6;
1739 code[loc + 0] &= ~(0x3f << 26);
1740 code[loc + 0] |= reg << 26;
1741 }
1742
1743 void
1744 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1745 {
1746 const uint32_t base = i->getSrc(0)->reg.data.offset;
1747
1748 if (i->encSize == 8) {
1749 code[0] = 0x00000000;
1750 code[1] = 0xc0000000 | (base & 0xffff);
1751
1752 if (i->saturate)
1753 code[0] |= 1 << 5;
1754
1755 if (i->op == OP_PINTERP) {
1756 srcId(i->src(1), 26);
1757 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1758 } else {
1759 code[0] |= 0x3f << 26;
1760 addInterp(i->ipa, 0x3f, interpApply);
1761 }
1762
1763 srcId(i->src(0).getIndirect(0), 20);
1764 } else {
1765 assert(i->op == OP_PINTERP);
1766 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1767 srcId(i->src(1), 20);
1768 }
1769 emitInterpMode(i);
1770
1771 emitPredicate(i);
1772 defId(i->def(0), 14);
1773
1774 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1775 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1776 else
1777 code[1] |= 0x3f << 17;
1778 }
1779
1780 void
1781 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1782 {
1783 uint8_t val;
1784
1785 switch (ty) {
1786 case TYPE_U8:
1787 val = 0x00;
1788 break;
1789 case TYPE_S8:
1790 val = 0x20;
1791 break;
1792 case TYPE_F16:
1793 case TYPE_U16:
1794 val = 0x40;
1795 break;
1796 case TYPE_S16:
1797 val = 0x60;
1798 break;
1799 case TYPE_F32:
1800 case TYPE_U32:
1801 case TYPE_S32:
1802 val = 0x80;
1803 break;
1804 case TYPE_F64:
1805 case TYPE_U64:
1806 case TYPE_S64:
1807 val = 0xa0;
1808 break;
1809 case TYPE_B128:
1810 val = 0xc0;
1811 break;
1812 default:
1813 val = 0x80;
1814 assert(!"invalid type");
1815 break;
1816 }
1817 code[0] |= val;
1818 }
1819
1820 void
1821 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1822 {
1823 uint32_t val;
1824
1825 switch (c) {
1826 case CACHE_CA:
1827 // case CACHE_WB:
1828 val = 0x000;
1829 break;
1830 case CACHE_CG:
1831 val = 0x100;
1832 break;
1833 case CACHE_CS:
1834 val = 0x200;
1835 break;
1836 case CACHE_CV:
1837 // case CACHE_WT:
1838 val = 0x300;
1839 break;
1840 default:
1841 val = 0;
1842 assert(!"invalid caching mode");
1843 break;
1844 }
1845 code[0] |= val;
1846 }
1847
1848 static inline bool
1849 uses64bitAddress(const Instruction *ldst)
1850 {
1851 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1852 ldst->src(0).isIndirect(0) &&
1853 ldst->getIndirect(0, 0)->reg.size == 8;
1854 }
1855
1856 void
1857 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1858 {
1859 uint32_t opc;
1860
1861 switch (i->src(0).getFile()) {
1862 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1863 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1864 case FILE_MEMORY_SHARED:
1865 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1866 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1867 opc = 0xb8000000;
1868 else
1869 opc = 0xcc000000;
1870 } else {
1871 opc = 0xc9000000;
1872 }
1873 break;
1874 default:
1875 assert(!"invalid memory file");
1876 opc = 0;
1877 break;
1878 }
1879 code[0] = 0x00000005;
1880 code[1] = opc;
1881
1882 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1883 // Unlocked store on shared memory can fail.
1884 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1885 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1886 assert(i->defExists(0));
1887 setPDSTL(i, 0);
1888 }
1889 }
1890
1891 setAddressByFile(i->src(0));
1892 srcId(i->src(1), 14);
1893 srcId(i->src(0).getIndirect(0), 20);
1894 if (uses64bitAddress(i))
1895 code[1] |= 1 << 26;
1896
1897 emitPredicate(i);
1898
1899 emitLoadStoreType(i->dType);
1900 emitCachingMode(i->cache);
1901 }
1902
1903 void
1904 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1905 {
1906 uint32_t opc;
1907
1908 code[0] = 0x00000005;
1909
1910 switch (i->src(0).getFile()) {
1911 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1912 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1913 case FILE_MEMORY_SHARED:
1914 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1915 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1916 opc = 0xa8000000;
1917 else
1918 opc = 0xc4000000;
1919 } else {
1920 opc = 0xc1000000;
1921 }
1922 break;
1923 case FILE_MEMORY_CONST:
1924 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1925 emitMOV(i); // not sure if this is any better
1926 return;
1927 }
1928 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1929 code[0] = 0x00000006 | (i->subOp << 8);
1930 break;
1931 default:
1932 assert(!"invalid memory file");
1933 opc = 0;
1934 break;
1935 }
1936 code[1] = opc;
1937
1938 int r = 0, p = -1;
1939 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1940 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1941 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1942 r = -1;
1943 p = 0;
1944 } else if (i->defExists(1)) { // r, p
1945 p = 1;
1946 } else {
1947 assert(!"Expected predicate dest for load locked");
1948 }
1949 }
1950 }
1951
1952 if (r >= 0)
1953 defId(i->def(r), 14);
1954 else
1955 code[0] |= 63 << 14;
1956
1957 if (p >= 0) {
1958 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1959 setPDSTL(i, p);
1960 else
1961 defId(i->def(p), 32 + 18);
1962 }
1963
1964 setAddressByFile(i->src(0));
1965 srcId(i->src(0).getIndirect(0), 20);
1966 if (uses64bitAddress(i))
1967 code[1] |= 1 << 26;
1968
1969 emitPredicate(i);
1970
1971 emitLoadStoreType(i->dType);
1972 emitCachingMode(i->cache);
1973 }
1974
1975 uint8_t
1976 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1977 {
1978 switch (SDATA(ref).sv.sv) {
1979 case SV_LANEID: return 0x00;
1980 case SV_PHYSID: return 0x03;
1981 case SV_VERTEX_COUNT: return 0x10;
1982 case SV_INVOCATION_ID: return 0x11;
1983 case SV_YDIR: return 0x12;
1984 case SV_THREAD_KILL: return 0x13;
1985 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1986 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1987 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1988 case SV_GRIDID: return 0x2c;
1989 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1990 case SV_LBASE: return 0x34;
1991 case SV_SBASE: return 0x30;
1992 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1993 default:
1994 assert(!"no sreg for system value");
1995 return 0;
1996 }
1997 }
1998
1999 void
2000 CodeEmitterNVC0::emitMOV(const Instruction *i)
2001 {
2002 if (i->def(0).getFile() == FILE_PREDICATE) {
2003 if (i->src(0).getFile() == FILE_GPR) {
2004 code[0] = 0xfc01c003;
2005 code[1] = 0x1a8e0000;
2006 srcId(i->src(0), 20);
2007 } else {
2008 code[0] = 0x0001c004;
2009 code[1] = 0x0c0e0000;
2010 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2011 code[0] |= 7 << 20;
2012 if (!i->getSrc(0)->reg.data.u32)
2013 code[0] |= 1 << 23;
2014 } else {
2015 srcId(i->src(0), 20);
2016 }
2017 }
2018 defId(i->def(0), 17);
2019 emitPredicate(i);
2020 } else
2021 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
2022 uint8_t sr = getSRegEncoding(i->src(0));
2023
2024 if (i->encSize == 8) {
2025 code[0] = 0x00000004 | (sr << 26);
2026 code[1] = 0x2c000000;
2027 } else {
2028 code[0] = 0x40000008 | (sr << 20);
2029 }
2030 defId(i->def(0), 14);
2031
2032 emitPredicate(i);
2033 } else
2034 if (i->encSize == 8) {
2035 uint64_t opc;
2036
2037 if (i->src(0).getFile() == FILE_IMMEDIATE)
2038 opc = HEX64(18000000, 000001e2);
2039 else
2040 if (i->src(0).getFile() == FILE_PREDICATE)
2041 opc = HEX64(080e0000, 1c000004);
2042 else
2043 opc = HEX64(28000000, 00000004);
2044
2045 if (i->src(0).getFile() != FILE_PREDICATE)
2046 opc |= i->lanes << 5;
2047
2048 emitForm_B(i, opc);
2049
2050 // Explicitly emit the predicate source as emitForm_B skips it.
2051 if (i->src(0).getFile() == FILE_PREDICATE)
2052 srcId(i->src(0), 20);
2053 } else {
2054 uint32_t imm;
2055
2056 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2057 imm = SDATA(i->src(0)).u32;
2058 if (imm & 0xfff00000) {
2059 assert(!(imm & 0x000fffff));
2060 code[0] = 0x00000318 | imm;
2061 } else {
2062 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
2063 code[0] = 0x00000118 | (imm << 20);
2064 }
2065 } else {
2066 code[0] = 0x0028;
2067 emitShortSrc2(i->src(0));
2068 }
2069 defId(i->def(0), 14);
2070
2071 emitPredicate(i);
2072 }
2073 }
2074
2075 void
2076 CodeEmitterNVC0::emitATOM(const Instruction *i)
2077 {
2078 const bool hasDst = i->defExists(0);
2079 const bool casOrExch =
2080 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
2081 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
2082
2083 if (i->dType == TYPE_U64) {
2084 switch (i->subOp) {
2085 case NV50_IR_SUBOP_ATOM_ADD:
2086 code[0] = 0x205;
2087 if (hasDst)
2088 code[1] = 0x507e0000;
2089 else
2090 code[1] = 0x10000000;
2091 break;
2092 case NV50_IR_SUBOP_ATOM_EXCH:
2093 code[0] = 0x305;
2094 code[1] = 0x507e0000;
2095 break;
2096 case NV50_IR_SUBOP_ATOM_CAS:
2097 code[0] = 0x325;
2098 code[1] = 0x50000000;
2099 break;
2100 default:
2101 assert(!"invalid u64 red op");
2102 break;
2103 }
2104 } else
2105 if (i->dType == TYPE_U32) {
2106 switch (i->subOp) {
2107 case NV50_IR_SUBOP_ATOM_EXCH:
2108 code[0] = 0x105;
2109 code[1] = 0x507e0000;
2110 break;
2111 case NV50_IR_SUBOP_ATOM_CAS:
2112 code[0] = 0x125;
2113 code[1] = 0x50000000;
2114 break;
2115 default:
2116 code[0] = 0x5 | (i->subOp << 5);
2117 if (hasDst)
2118 code[1] = 0x507e0000;
2119 else
2120 code[1] = 0x10000000;
2121 break;
2122 }
2123 } else
2124 if (i->dType == TYPE_S32) {
2125 assert(i->subOp <= 2);
2126 code[0] = 0x205 | (i->subOp << 5);
2127 if (hasDst)
2128 code[1] = 0x587e0000;
2129 else
2130 code[1] = 0x18000000;
2131 } else
2132 if (i->dType == TYPE_F32) {
2133 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2134 code[0] = 0x205;
2135 if (hasDst)
2136 code[1] = 0x687e0000;
2137 else
2138 code[1] = 0x28000000;
2139 }
2140
2141 emitPredicate(i);
2142
2143 srcId(i->src(1), 14);
2144
2145 if (hasDst)
2146 defId(i->def(0), 32 + 11);
2147 else
2148 if (casOrExch)
2149 code[1] |= 63 << 11;
2150
2151 if (hasDst || casOrExch) {
2152 const int32_t offset = SDATA(i->src(0)).offset;
2153 assert(offset < 0x80000 && offset >= -0x80000);
2154 code[0] |= offset << 26;
2155 code[1] |= (offset & 0x1ffc0) >> 6;
2156 code[1] |= (offset & 0xe0000) << 6;
2157 } else {
2158 srcAddr32(i->src(0), 26, 0);
2159 }
2160 if (i->getIndirect(0, 0)) {
2161 srcId(i->getIndirect(0, 0), 20);
2162 if (i->getIndirect(0, 0)->reg.size == 8)
2163 code[1] |= 1 << 26;
2164 } else {
2165 code[0] |= 63 << 20;
2166 }
2167
2168 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2169 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2170 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2171 }
2172 }
2173
2174 void
2175 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2176 {
2177 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2178 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2179 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2180 default:
2181 code[0] = 0x45;
2182 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2183 break;
2184 }
2185 code[1] = 0xe0000000;
2186
2187 emitPredicate(i);
2188 }
2189
2190 void
2191 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2192 {
2193 code[0] = 0x00000005 | (i->subOp << 5);
2194
2195 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2196 code[1] = 0x98000000;
2197 srcAddr32(i->src(0), 28, 2);
2198 } else {
2199 code[1] = 0xd0000000;
2200 setAddress24(i->src(0));
2201 }
2202 if (uses64bitAddress(i))
2203 code[1] |= 1 << 26;
2204 srcId(i->src(0).getIndirect(0), 20);
2205
2206 emitPredicate(i);
2207
2208 defId(i, 0, 14);
2209 }
2210
2211 void
2212 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2213 {
2214 uint8_t m;
2215 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2216 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2217 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2218 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2219 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2220 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2221 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2222 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2223 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2224 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2225 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2226 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2227 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2228 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2229 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2230 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2231 default:
2232 return;
2233 }
2234 code[0] |= m << 5;
2235 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2236 code[1] |= 1 << 16;
2237 }
2238
2239 void
2240 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2241 {
2242 ImmediateValue *imm = NULL;
2243 uint64_t opc;
2244
2245 if (i->srcExists(2)) {
2246 imm = i->getSrc(2)->asImm();
2247 if (imm)
2248 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2249 }
2250
2251 switch (i->op) {
2252 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2253 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2254 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2255 default:
2256 assert(0);
2257 return;
2258 }
2259 emitForm_A(i, opc);
2260
2261 if (i->op == OP_SUCLAMP) {
2262 if (i->dType == TYPE_S32)
2263 code[0] |= 1 << 9;
2264 emitSUCLAMPMode(i->subOp);
2265 }
2266
2267 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2268 code[1] |= 1 << 16;
2269
2270 if (i->op != OP_SUEAU) {
2271 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2272 code[0] |= 63 << 14;
2273 code[1] |= i->getDef(0)->reg.data.id << 23;
2274 } else
2275 if (i->defExists(1)) { // r, p
2276 assert(i->def(1).getFile() == FILE_PREDICATE);
2277 code[1] |= i->getDef(1)->reg.data.id << 23;
2278 } else { // r, #
2279 code[1] |= 7 << 23;
2280 }
2281 }
2282 if (imm) {
2283 assert(i->op == OP_SUCLAMP);
2284 i->setSrc(2, imm);
2285 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2286 }
2287 }
2288
2289 void
2290 CodeEmitterNVC0::emitSUGType(DataType ty)
2291 {
2292 switch (ty) {
2293 case TYPE_S32: code[1] |= 1 << 13; break;
2294 case TYPE_U8: code[1] |= 2 << 13; break;
2295 case TYPE_S8: code[1] |= 3 << 13; break;
2296 default:
2297 assert(ty == TYPE_U32);
2298 break;
2299 }
2300 }
2301
2302 void
2303 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2304 {
2305 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2306
2307 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2308 assert(offset == (offset & 0xfffc));
2309
2310 code[1] |= 1 << 21;
2311 code[0] |= offset << 24;
2312 code[1] |= offset >> 8;
2313 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2314 }
2315
2316 void
2317 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2318 {
2319 if (!i->srcExists(s) || (i->predSrc == s)) {
2320 code[1] |= 0x7 << 17;
2321 } else {
2322 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2323 code[1] |= 1 << 20;
2324 srcId(i->src(s), 32 + 17);
2325 }
2326 }
2327
2328 void
2329 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2330 {
2331 code[0] = 0x5;
2332 code[1] = 0xd4000000 | (i->subOp << 15);
2333
2334 emitLoadStoreType(i->dType);
2335 emitSUGType(i->sType);
2336 emitCachingMode(i->cache);
2337
2338 emitPredicate(i);
2339 defId(i->def(0), 14); // destination
2340 srcId(i->src(0), 20); // address
2341 // format
2342 if (i->src(1).getFile() == FILE_GPR)
2343 srcId(i->src(1), 26);
2344 else
2345 setSUConst16(i, 1);
2346 setSUPred(i, 2);
2347 }
2348
2349 void
2350 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2351 {
2352 code[0] = 0x5;
2353 code[1] = 0xdc000000 | (i->subOp << 15);
2354
2355 if (i->op == OP_SUSTP)
2356 code[1] |= i->tex.mask << 22;
2357 else
2358 emitLoadStoreType(i->dType);
2359 emitSUGType(i->sType);
2360 emitCachingMode(i->cache);
2361
2362 emitPredicate(i);
2363 srcId(i->src(0), 20); // address
2364 // format
2365 if (i->src(1).getFile() == FILE_GPR)
2366 srcId(i->src(1), 26);
2367 else
2368 setSUConst16(i, 1);
2369 srcId(i->src(3), 14); // values
2370 setSUPred(i, 2);
2371 }
2372
2373 void
2374 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
2375 {
2376 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2377
2378 if (i->tex.rIndirectSrc < 0) {
2379 code[1] |= 0x00004000;
2380 code[0] |= i->tex.r << 26;
2381 } else {
2382 srcId(i, i->tex.rIndirectSrc, 26);
2383 }
2384 }
2385
2386 void
2387 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
2388 {
2389 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2390
2391 code[1] |= (i->tex.target.getDim() - 1) << 12;
2392 if (i->tex.target.isArray() || i->tex.target.isCube() ||
2393 i->tex.target.getDim() == 3) {
2394 // use e2d mode for 3-dim images, arrays and cubes.
2395 code[1] |= 3 << 12;
2396 }
2397
2398 srcId(i->src(0), 20);
2399 }
2400
2401 void
2402 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
2403 {
2404 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2405
2406 code[0] = 0x5;
2407 code[1] = 0xf0000000;
2408
2409 emitPredicate(i);
2410 emitLoadStoreType(i->sType);
2411
2412 defId(i->def(0), 14);
2413
2414 if (i->defExists(1)) {
2415 defId(i->def(1), 32 + 22);
2416 } else {
2417 code[1] |= 7 << 22;
2418 }
2419
2420 emitSUAddr(i);
2421 emitSUDim(i);
2422 }
2423
2424 void
2425 CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
2426 {
2427 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2428
2429 code[0] = 0x5;
2430 code[1] = 0xd4000000 | (i->subOp << 15);
2431
2432 emitPredicate(i);
2433 emitLoadStoreType(i->dType);
2434
2435 defId(i->def(0), 14);
2436
2437 emitCachingMode(i->cache);
2438 emitSUAddr(i);
2439 emitSUDim(i);
2440 }
2441
2442 void
2443 CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
2444 {
2445 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2446
2447 code[0] = 0x5;
2448 code[1] = 0xdc000000 | (i->subOp << 15);
2449
2450 if (i->op == OP_SUSTP)
2451 code[1] |= i->tex.mask << 17;
2452 else
2453 emitLoadStoreType(i->dType);
2454
2455 emitPredicate(i);
2456
2457 srcId(i->src(1), 14);
2458
2459 emitCachingMode(i->cache);
2460 emitSUAddr(i);
2461 emitSUDim(i);
2462 }
2463
2464 void
2465 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2466 {
2467 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2468 case 0:
2469 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2470 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2471 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2472 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2473 break;
2474 case 1:
2475 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2476 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2477 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2478 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2479 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2480 code[1] |= (i->mask & 0x3) << 2;
2481 break;
2482 case 2:
2483 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2484 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2485 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2486 code[1] |= (i->mask & 0x3) << 2;
2487 code[1] |= (i->mask & 0xc) << 21;
2488 break;
2489 default:
2490 assert(0);
2491 break;
2492 }
2493 }
2494
2495 void
2496 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2497 {
2498 uint64_t opc = 0x4;
2499
2500 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2501 case 0: opc |= 0xe8ULL << 56; break;
2502 case 1: opc |= 0xb4ULL << 56; break;
2503 case 2: opc |= 0x94ULL << 56; break;
2504 default:
2505 assert(0);
2506 break;
2507 }
2508 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2509 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2510 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2511 } else {
2512 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2513 if (isSignedType(i->sType)) opc |= 1 << 6;
2514 }
2515 emitForm_A(i, opc);
2516 emitVectorSubOp(i);
2517
2518 if (i->saturate)
2519 code[0] |= 1 << 9;
2520 if (i->flagsDef >= 0)
2521 code[1] |= 1 << 16;
2522 }
2523
2524 void
2525 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2526 {
2527 assert(i->encSize == 8);
2528 emitForm_A(i, HEX64(10000000, 00000006));
2529 code[0] |= i->subOp << 5;
2530 code[1] |= 0x00e00000;
2531 }
2532
2533 void
2534 CodeEmitterNVC0::emitVOTE(const Instruction *i)
2535 {
2536 assert(i->src(0).getFile() == FILE_PREDICATE);
2537
2538 code[0] = 0x00000004 | (i->subOp << 5);
2539 code[1] = 0x48000000;
2540
2541 emitPredicate(i);
2542
2543 unsigned rp = 0;
2544 for (int d = 0; i->defExists(d); d++) {
2545 if (i->def(d).getFile() == FILE_PREDICATE) {
2546 assert(!(rp & 2));
2547 rp |= 2;
2548 defId(i->def(d), 32 + 22);
2549 } else if (i->def(d).getFile() == FILE_GPR) {
2550 assert(!(rp & 1));
2551 rp |= 1;
2552 defId(i->def(d), 14);
2553 } else {
2554 assert(!"Unhandled def");
2555 }
2556 }
2557 if (!(rp & 1))
2558 code[0] |= 63 << 14;
2559 if (!(rp & 2))
2560 code[1] |= 7 << 22;
2561 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
2562 code[0] |= 1 << 23;
2563 srcId(i->src(0), 20);
2564 }
2565
2566 bool
2567 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2568 {
2569 unsigned int size = insn->encSize;
2570
2571 if (writeIssueDelays && !(codeSize & 0x3f))
2572 size += 8;
2573
2574 if (!insn->encSize) {
2575 ERROR("skipping unencodable instruction: "); insn->print();
2576 return false;
2577 } else
2578 if (codeSize + size > codeSizeLimit) {
2579 ERROR("code emitter output buffer too small\n");
2580 return false;
2581 }
2582
2583 if (writeIssueDelays) {
2584 if (!(codeSize & 0x3f)) {
2585 code[0] = 0x00000007; // cf issue delay "instruction"
2586 code[1] = 0x20000000;
2587 code += 2;
2588 codeSize += 8;
2589 }
2590 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2591 uint32_t *data = code - (id * 2 + 2);
2592 if (id <= 2) {
2593 data[0] |= insn->sched << (id * 8 + 4);
2594 } else
2595 if (id == 3) {
2596 data[0] |= insn->sched << 28;
2597 data[1] |= insn->sched >> 4;
2598 } else {
2599 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2600 }
2601 }
2602
2603 // assert that instructions with multiple defs don't corrupt registers
2604 for (int d = 0; insn->defExists(d); ++d)
2605 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2606
2607 switch (insn->op) {
2608 case OP_MOV:
2609 case OP_RDSV:
2610 emitMOV(insn);
2611 break;
2612 case OP_NOP:
2613 break;
2614 case OP_LOAD:
2615 emitLOAD(insn);
2616 break;
2617 case OP_STORE:
2618 emitSTORE(insn);
2619 break;
2620 case OP_LINTERP:
2621 case OP_PINTERP:
2622 emitINTERP(insn);
2623 break;
2624 case OP_VFETCH:
2625 emitVFETCH(insn);
2626 break;
2627 case OP_EXPORT:
2628 emitEXPORT(insn);
2629 break;
2630 case OP_PFETCH:
2631 emitPFETCH(insn);
2632 break;
2633 case OP_AFETCH:
2634 emitAFETCH(insn);
2635 break;
2636 case OP_EMIT:
2637 case OP_RESTART:
2638 emitOUT(insn);
2639 break;
2640 case OP_ADD:
2641 case OP_SUB:
2642 if (insn->dType == TYPE_F64)
2643 emitDADD(insn);
2644 else if (isFloatType(insn->dType))
2645 emitFADD(insn);
2646 else
2647 emitUADD(insn);
2648 break;
2649 case OP_MUL:
2650 if (insn->dType == TYPE_F64)
2651 emitDMUL(insn);
2652 else if (isFloatType(insn->dType))
2653 emitFMUL(insn);
2654 else
2655 emitUMUL(insn);
2656 break;
2657 case OP_MAD:
2658 case OP_FMA:
2659 if (insn->dType == TYPE_F64)
2660 emitDMAD(insn);
2661 else if (isFloatType(insn->dType))
2662 emitFMAD(insn);
2663 else
2664 emitIMAD(insn);
2665 break;
2666 case OP_SAD:
2667 emitISAD(insn);
2668 break;
2669 case OP_SHLADD:
2670 emitSHLADD(insn);
2671 break;
2672 case OP_NOT:
2673 emitNOT(insn);
2674 break;
2675 case OP_AND:
2676 emitLogicOp(insn, 0);
2677 break;
2678 case OP_OR:
2679 emitLogicOp(insn, 1);
2680 break;
2681 case OP_XOR:
2682 emitLogicOp(insn, 2);
2683 break;
2684 case OP_SHL:
2685 case OP_SHR:
2686 emitShift(insn);
2687 break;
2688 case OP_SET:
2689 case OP_SET_AND:
2690 case OP_SET_OR:
2691 case OP_SET_XOR:
2692 emitSET(insn->asCmp());
2693 break;
2694 case OP_SELP:
2695 emitSELP(insn);
2696 break;
2697 case OP_SLCT:
2698 emitSLCT(insn->asCmp());
2699 break;
2700 case OP_MIN:
2701 case OP_MAX:
2702 emitMINMAX(insn);
2703 break;
2704 case OP_ABS:
2705 case OP_NEG:
2706 case OP_CEIL:
2707 case OP_FLOOR:
2708 case OP_TRUNC:
2709 case OP_SAT:
2710 emitCVT(insn);
2711 break;
2712 case OP_CVT:
2713 if (insn->def(0).getFile() == FILE_PREDICATE ||
2714 insn->src(0).getFile() == FILE_PREDICATE)
2715 emitMOV(insn);
2716 else
2717 emitCVT(insn);
2718 break;
2719 case OP_RSQ:
2720 emitSFnOp(insn, 5 + 2 * insn->subOp);
2721 break;
2722 case OP_RCP:
2723 emitSFnOp(insn, 4 + 2 * insn->subOp);
2724 break;
2725 case OP_LG2:
2726 emitSFnOp(insn, 3);
2727 break;
2728 case OP_EX2:
2729 emitSFnOp(insn, 2);
2730 break;
2731 case OP_SIN:
2732 emitSFnOp(insn, 1);
2733 break;
2734 case OP_COS:
2735 emitSFnOp(insn, 0);
2736 break;
2737 case OP_PRESIN:
2738 case OP_PREEX2:
2739 emitPreOp(insn);
2740 break;
2741 case OP_TEX:
2742 case OP_TXB:
2743 case OP_TXL:
2744 case OP_TXD:
2745 case OP_TXF:
2746 case OP_TXG:
2747 case OP_TXLQ:
2748 emitTEX(insn->asTex());
2749 break;
2750 case OP_TXQ:
2751 emitTXQ(insn->asTex());
2752 break;
2753 case OP_TEXBAR:
2754 emitTEXBAR(insn);
2755 break;
2756 case OP_SUBFM:
2757 case OP_SUCLAMP:
2758 case OP_SUEAU:
2759 emitSUCalc(insn);
2760 break;
2761 case OP_MADSP:
2762 emitMADSP(insn);
2763 break;
2764 case OP_SULDB:
2765 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2766 emitSULDGB(insn->asTex());
2767 else
2768 emitSULDB(insn->asTex());
2769 break;
2770 case OP_SUSTB:
2771 case OP_SUSTP:
2772 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2773 emitSUSTGx(insn->asTex());
2774 else
2775 emitSUSTx(insn->asTex());
2776 break;
2777 case OP_SULEA:
2778 emitSULEA(insn->asTex());
2779 break;
2780 case OP_ATOM:
2781 emitATOM(insn);
2782 break;
2783 case OP_BRA:
2784 case OP_CALL:
2785 case OP_PRERET:
2786 case OP_RET:
2787 case OP_DISCARD:
2788 case OP_EXIT:
2789 case OP_PRECONT:
2790 case OP_CONT:
2791 case OP_PREBREAK:
2792 case OP_BREAK:
2793 case OP_JOINAT:
2794 case OP_BRKPT:
2795 case OP_QUADON:
2796 case OP_QUADPOP:
2797 emitFlow(insn);
2798 break;
2799 case OP_QUADOP:
2800 emitQUADOP(insn, insn->subOp, insn->lanes);
2801 break;
2802 case OP_DFDX:
2803 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2804 break;
2805 case OP_DFDY:
2806 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2807 break;
2808 case OP_POPCNT:
2809 emitPOPC(insn);
2810 break;
2811 case OP_INSBF:
2812 emitINSBF(insn);
2813 break;
2814 case OP_EXTBF:
2815 emitEXTBF(insn);
2816 break;
2817 case OP_BFIND:
2818 emitBFIND(insn);
2819 break;
2820 case OP_PERMT:
2821 emitPERMT(insn);
2822 break;
2823 case OP_JOIN:
2824 emitNOP(insn);
2825 insn->join = 1;
2826 break;
2827 case OP_BAR:
2828 emitBAR(insn);
2829 break;
2830 case OP_MEMBAR:
2831 emitMEMBAR(insn);
2832 break;
2833 case OP_CCTL:
2834 emitCCTL(insn);
2835 break;
2836 case OP_VSHL:
2837 emitVSHL(insn);
2838 break;
2839 case OP_PIXLD:
2840 emitPIXLD(insn);
2841 break;
2842 case OP_VOTE:
2843 emitVOTE(insn);
2844 break;
2845 case OP_PHI:
2846 case OP_UNION:
2847 case OP_CONSTRAINT:
2848 ERROR("operation should have been eliminated");
2849 return false;
2850 case OP_EXP:
2851 case OP_LOG:
2852 case OP_SQRT:
2853 case OP_POW:
2854 ERROR("operation should have been lowered\n");
2855 return false;
2856 default:
2857 ERROR("unknown op: %u\n", insn->op);
2858 return false;
2859 }
2860
2861 if (insn->join) {
2862 code[0] |= 0x10;
2863 assert(insn->encSize == 8);
2864 }
2865
2866 code += insn->encSize / 4;
2867 codeSize += insn->encSize;
2868 return true;
2869 }
2870
2871 uint32_t
2872 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2873 {
2874 const Target::OpInfo &info = targ->getOpInfo(i);
2875
2876 if (writeIssueDelays || info.minEncSize == 8 || 1)
2877 return 8;
2878
2879 if (i->ftz || i->saturate || i->join)
2880 return 8;
2881 if (i->rnd != ROUND_N)
2882 return 8;
2883 if (i->predSrc >= 0 && i->op == OP_MAD)
2884 return 8;
2885
2886 if (i->op == OP_PINTERP) {
2887 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2888 return 8;
2889 } else
2890 if (i->op == OP_MOV && i->lanes != 0xf) {
2891 return 8;
2892 }
2893
2894 for (int s = 0; i->srcExists(s); ++s) {
2895 if (i->src(s).isIndirect(0))
2896 return 8;
2897
2898 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2899 if (SDATA(i->src(s)).offset >= 0x100)
2900 return 8;
2901 if (i->getSrc(s)->reg.fileIndex > 1 &&
2902 i->getSrc(s)->reg.fileIndex != 16)
2903 return 8;
2904 } else
2905 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2906 if (i->dType == TYPE_F32) {
2907 if (SDATA(i->src(s)).u32 >= 0x100)
2908 return 8;
2909 } else {
2910 if (SDATA(i->src(s)).u32 > 0xff)
2911 return 8;
2912 }
2913 }
2914
2915 if (i->op == OP_CVT)
2916 continue;
2917 if (i->src(s).mod != Modifier(0)) {
2918 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2919 if (i->op != OP_RSQ)
2920 return 8;
2921 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2922 if (i->op != OP_ADD || s != 0)
2923 return 8;
2924 }
2925 }
2926
2927 return 4;
2928 }
2929
2930 // Simplified, erring on safe side.
2931 class SchedDataCalculator : public Pass
2932 {
2933 public:
2934 SchedDataCalculator(const Target *targ) : targ(targ) { }
2935
2936 private:
2937 struct RegScores
2938 {
2939 struct Resource {
2940 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2941 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2942 int tex; // TEX to non-TEX delay 17 (0x11)
2943 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2944 int imul; // integer MUL to MUL delay 3
2945 } res;
2946 struct ScoreData {
2947 int r[256];
2948 int p[8];
2949 int c;
2950 } rd, wr;
2951 int base;
2952 int regs;
2953
2954 void rebase(const int base)
2955 {
2956 const int delta = this->base - base;
2957 if (!delta)
2958 return;
2959 this->base = 0;
2960
2961 for (int i = 0; i < regs; ++i) {
2962 rd.r[i] += delta;
2963 wr.r[i] += delta;
2964 }
2965 for (int i = 0; i < 8; ++i) {
2966 rd.p[i] += delta;
2967 wr.p[i] += delta;
2968 }
2969 rd.c += delta;
2970 wr.c += delta;
2971
2972 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2973 res.ld[f] += delta;
2974 res.st[f] += delta;
2975 }
2976 res.sfu += delta;
2977 res.imul += delta;
2978 res.tex += delta;
2979 }
2980 void wipe(int regs)
2981 {
2982 memset(&rd, 0, sizeof(rd));
2983 memset(&wr, 0, sizeof(wr));
2984 memset(&res, 0, sizeof(res));
2985 this->regs = regs;
2986 }
2987 int getLatest(const ScoreData& d) const
2988 {
2989 int max = 0;
2990 for (int i = 0; i < regs; ++i)
2991 if (d.r[i] > max)
2992 max = d.r[i];
2993 for (int i = 0; i < 8; ++i)
2994 if (d.p[i] > max)
2995 max = d.p[i];
2996 if (d.c > max)
2997 max = d.c;
2998 return max;
2999 }
3000 inline int getLatestRd() const
3001 {
3002 return getLatest(rd);
3003 }
3004 inline int getLatestWr() const
3005 {
3006 return getLatest(wr);
3007 }
3008 inline int getLatest() const
3009 {
3010 const int a = getLatestRd();
3011 const int b = getLatestWr();
3012
3013 int max = MAX2(a, b);
3014 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3015 max = MAX2(res.ld[f], max);
3016 max = MAX2(res.st[f], max);
3017 }
3018 max = MAX2(res.sfu, max);
3019 max = MAX2(res.imul, max);
3020 max = MAX2(res.tex, max);
3021 return max;
3022 }
3023 void setMax(const RegScores *that)
3024 {
3025 for (int i = 0; i < regs; ++i) {
3026 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
3027 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
3028 }
3029 for (int i = 0; i < 8; ++i) {
3030 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
3031 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
3032 }
3033 rd.c = MAX2(rd.c, that->rd.c);
3034 wr.c = MAX2(wr.c, that->wr.c);
3035
3036 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3037 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
3038 res.st[f] = MAX2(res.st[f], that->res.st[f]);
3039 }
3040 res.sfu = MAX2(res.sfu, that->res.sfu);
3041 res.imul = MAX2(res.imul, that->res.imul);
3042 res.tex = MAX2(res.tex, that->res.tex);
3043 }
3044 void print(int cycle)
3045 {
3046 for (int i = 0; i < regs; ++i) {
3047 if (rd.r[i] > cycle)
3048 INFO("rd $r%i @ %i\n", i, rd.r[i]);
3049 if (wr.r[i] > cycle)
3050 INFO("wr $r%i @ %i\n", i, wr.r[i]);
3051 }
3052 for (int i = 0; i < 8; ++i) {
3053 if (rd.p[i] > cycle)
3054 INFO("rd $p%i @ %i\n", i, rd.p[i]);
3055 if (wr.p[i] > cycle)
3056 INFO("wr $p%i @ %i\n", i, wr.p[i]);
3057 }
3058 if (rd.c > cycle)
3059 INFO("rd $c @ %i\n", rd.c);
3060 if (wr.c > cycle)
3061 INFO("wr $c @ %i\n", wr.c);
3062 if (res.sfu > cycle)
3063 INFO("sfu @ %i\n", res.sfu);
3064 if (res.imul > cycle)
3065 INFO("imul @ %i\n", res.imul);
3066 if (res.tex > cycle)
3067 INFO("tex @ %i\n", res.tex);
3068 }
3069 };
3070
3071 RegScores *score; // for current BB
3072 std::vector<RegScores> scoreBoards;
3073 int prevData;
3074 operation prevOp;
3075
3076 const Target *targ;
3077
3078 bool visit(Function *);
3079 bool visit(BasicBlock *);
3080
3081 void commitInsn(const Instruction *, int cycle);
3082 int calcDelay(const Instruction *, int cycle) const;
3083 void setDelay(Instruction *, int delay, Instruction *next);
3084
3085 void recordRd(const Value *, const int ready);
3086 void recordWr(const Value *, const int ready);
3087 void checkRd(const Value *, int cycle, int& delay) const;
3088 void checkWr(const Value *, int cycle, int& delay) const;
3089
3090 int getCycles(const Instruction *, int origDelay) const;
3091 };
3092
3093 void
3094 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
3095 {
3096 if (insn->op == OP_EXIT || insn->op == OP_RET)
3097 delay = MAX2(delay, 14);
3098
3099 if (insn->op == OP_TEXBAR) {
3100 // TODO: except if results not used before EXIT
3101 insn->sched = 0xc2;
3102 } else
3103 if (insn->op == OP_JOIN || insn->join) {
3104 insn->sched = 0x00;
3105 } else
3106 if (delay >= 0 || prevData == 0x04 ||
3107 !next || !targ->canDualIssue(insn, next)) {
3108 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
3109 if (prevOp == OP_EXPORT)
3110 insn->sched |= 0x40;
3111 else
3112 insn->sched |= 0x20;
3113 } else {
3114 insn->sched = 0x04; // dual-issue
3115 }
3116
3117 if (prevData != 0x04 || prevOp != OP_EXPORT)
3118 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
3119 prevOp = insn->op;
3120
3121 prevData = insn->sched;
3122 }
3123
3124 int
3125 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
3126 {
3127 if (insn->sched & 0x80) {
3128 int c = (insn->sched & 0x0f) * 2 + 1;
3129 if (insn->op == OP_TEXBAR && origDelay > 0)
3130 c += origDelay;
3131 return c;
3132 }
3133 if (insn->sched & 0x60)
3134 return (insn->sched & 0x1f) + 1;
3135 return (insn->sched == 0x04) ? 0 : 32;
3136 }
3137
3138 bool
3139 SchedDataCalculator::visit(Function *func)
3140 {
3141 int regs = targ->getFileSize(FILE_GPR) + 1;
3142 scoreBoards.resize(func->cfg.getSize());
3143 for (size_t i = 0; i < scoreBoards.size(); ++i)
3144 scoreBoards[i].wipe(regs);
3145 return true;
3146 }
3147
3148 bool
3149 SchedDataCalculator::visit(BasicBlock *bb)
3150 {
3151 Instruction *insn;
3152 Instruction *next = NULL;
3153
3154 int cycle = 0;
3155
3156 prevData = 0x00;
3157 prevOp = OP_NOP;
3158 score = &scoreBoards.at(bb->getId());
3159
3160 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
3161 // back branches will wait until all target dependencies are satisfied
3162 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
3163 continue;
3164 BasicBlock *in = BasicBlock::get(ei.getNode());
3165 if (in->getExit()) {
3166 if (prevData != 0x04)
3167 prevData = in->getExit()->sched;
3168 prevOp = in->getExit()->op;
3169 }
3170 score->setMax(&scoreBoards.at(in->getId()));
3171 }
3172 if (bb->cfg.incidentCount() > 1)
3173 prevOp = OP_NOP;
3174
3175 #ifdef NVC0_DEBUG_SCHED_DATA
3176 INFO("=== BB:%i initial scores\n", bb->getId());
3177 score->print(cycle);
3178 #endif
3179
3180 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
3181 next = insn->next;
3182
3183 commitInsn(insn, cycle);
3184 int delay = calcDelay(next, cycle);
3185 setDelay(insn, delay, next);
3186 cycle += getCycles(insn, delay);
3187
3188 #ifdef NVC0_DEBUG_SCHED_DATA
3189 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
3190 insn->print();
3191 next->print();
3192 #endif
3193 }
3194 if (!insn)
3195 return true;
3196 commitInsn(insn, cycle);
3197
3198 int bbDelay = -1;
3199
3200 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
3201 BasicBlock *out = BasicBlock::get(ei.getNode());
3202
3203 if (ei.getType() != Graph::Edge::BACK) {
3204 // only test the first instruction of the outgoing block
3205 next = out->getEntry();
3206 if (next)
3207 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
3208 } else {
3209 // wait until all dependencies are satisfied
3210 const int regsFree = score->getLatest();
3211 next = out->getFirst();
3212 for (int c = cycle; next && c < regsFree; next = next->next) {
3213 bbDelay = MAX2(bbDelay, calcDelay(next, c));
3214 c += getCycles(next, bbDelay);
3215 }
3216 next = NULL;
3217 }
3218 }
3219 if (bb->cfg.outgoingCount() != 1)
3220 next = NULL;
3221 setDelay(insn, bbDelay, next);
3222 cycle += getCycles(insn, bbDelay);
3223
3224 score->rebase(cycle); // common base for initializing out blocks' scores
3225 return true;
3226 }
3227
3228 #define NVE4_MAX_ISSUE_DELAY 0x1f
3229 int
3230 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
3231 {
3232 int delay = 0, ready = cycle;
3233
3234 for (int s = 0; insn->srcExists(s); ++s)
3235 checkRd(insn->getSrc(s), cycle, delay);
3236 // WAR & WAW don't seem to matter
3237 // for (int s = 0; insn->srcExists(s); ++s)
3238 // recordRd(insn->getSrc(s), cycle);
3239
3240 switch (Target::getOpClass(insn->op)) {
3241 case OPCLASS_SFU:
3242 ready = score->res.sfu;
3243 break;
3244 case OPCLASS_ARITH:
3245 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3246 ready = score->res.imul;
3247 break;
3248 case OPCLASS_TEXTURE:
3249 ready = score->res.tex;
3250 break;
3251 case OPCLASS_LOAD:
3252 ready = score->res.ld[insn->src(0).getFile()];
3253 break;
3254 case OPCLASS_STORE:
3255 ready = score->res.st[insn->src(0).getFile()];
3256 break;
3257 default:
3258 break;
3259 }
3260 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3261 ready = MAX2(ready, score->res.tex);
3262
3263 delay = MAX2(delay, ready - cycle);
3264
3265 // if can issue next cycle, delay is 0, not 1
3266 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3267 }
3268
3269 void
3270 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3271 {
3272 const int ready = cycle + targ->getLatency(insn);
3273
3274 for (int d = 0; insn->defExists(d); ++d)
3275 recordWr(insn->getDef(d), ready);
3276 // WAR & WAW don't seem to matter
3277 // for (int s = 0; insn->srcExists(s); ++s)
3278 // recordRd(insn->getSrc(s), cycle);
3279
3280 switch (Target::getOpClass(insn->op)) {
3281 case OPCLASS_SFU:
3282 score->res.sfu = cycle + 4;
3283 break;
3284 case OPCLASS_ARITH:
3285 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3286 score->res.imul = cycle + 4;
3287 break;
3288 case OPCLASS_TEXTURE:
3289 score->res.tex = cycle + 18;
3290 break;
3291 case OPCLASS_LOAD:
3292 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3293 break;
3294 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3295 score->res.st[insn->src(0).getFile()] = ready;
3296 break;
3297 case OPCLASS_STORE:
3298 score->res.st[insn->src(0).getFile()] = cycle + 4;
3299 score->res.ld[insn->src(0).getFile()] = ready;
3300 break;
3301 case OPCLASS_OTHER:
3302 if (insn->op == OP_TEXBAR)
3303 score->res.tex = cycle;
3304 break;
3305 default:
3306 break;
3307 }
3308
3309 #ifdef NVC0_DEBUG_SCHED_DATA
3310 score->print(cycle);
3311 #endif
3312 }
3313
3314 void
3315 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3316 {
3317 int ready = cycle;
3318 int a, b;
3319
3320 switch (v->reg.file) {
3321 case FILE_GPR:
3322 a = v->reg.data.id;
3323 b = a + v->reg.size / 4;
3324 for (int r = a; r < b; ++r)
3325 ready = MAX2(ready, score->rd.r[r]);
3326 break;
3327 case FILE_PREDICATE:
3328 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3329 break;
3330 case FILE_FLAGS:
3331 ready = MAX2(ready, score->rd.c);
3332 break;
3333 case FILE_SHADER_INPUT:
3334 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3335 case FILE_MEMORY_LOCAL:
3336 case FILE_MEMORY_CONST:
3337 case FILE_MEMORY_SHARED:
3338 case FILE_MEMORY_GLOBAL:
3339 case FILE_SYSTEM_VALUE:
3340 // TODO: any restrictions here ?
3341 break;
3342 case FILE_IMMEDIATE:
3343 break;
3344 default:
3345 assert(0);
3346 break;
3347 }
3348 if (cycle < ready)
3349 delay = MAX2(delay, ready - cycle);
3350 }
3351
3352 void
3353 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3354 {
3355 int ready = cycle;
3356 int a, b;
3357
3358 switch (v->reg.file) {
3359 case FILE_GPR:
3360 a = v->reg.data.id;
3361 b = a + v->reg.size / 4;
3362 for (int r = a; r < b; ++r)
3363 ready = MAX2(ready, score->wr.r[r]);
3364 break;
3365 case FILE_PREDICATE:
3366 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3367 break;
3368 default:
3369 assert(v->reg.file == FILE_FLAGS);
3370 ready = MAX2(ready, score->wr.c);
3371 break;
3372 }
3373 if (cycle < ready)
3374 delay = MAX2(delay, ready - cycle);
3375 }
3376
3377 void
3378 SchedDataCalculator::recordWr(const Value *v, const int ready)
3379 {
3380 int a = v->reg.data.id;
3381
3382 if (v->reg.file == FILE_GPR) {
3383 int b = a + v->reg.size / 4;
3384 for (int r = a; r < b; ++r)
3385 score->rd.r[r] = ready;
3386 } else
3387 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3388 if (v->reg.file == FILE_PREDICATE) {
3389 score->rd.p[a] = ready + 4;
3390 } else {
3391 assert(v->reg.file == FILE_FLAGS);
3392 score->rd.c = ready + 4;
3393 }
3394 }
3395
3396 void
3397 SchedDataCalculator::recordRd(const Value *v, const int ready)
3398 {
3399 int a = v->reg.data.id;
3400
3401 if (v->reg.file == FILE_GPR) {
3402 int b = a + v->reg.size / 4;
3403 for (int r = a; r < b; ++r)
3404 score->wr.r[r] = ready;
3405 } else
3406 if (v->reg.file == FILE_PREDICATE) {
3407 score->wr.p[a] = ready;
3408 } else
3409 if (v->reg.file == FILE_FLAGS) {
3410 score->wr.c = ready;
3411 }
3412 }
3413
3414 bool
3415 calculateSchedDataNVC0(const Target *targ, Function *func)
3416 {
3417 SchedDataCalculator sched(targ);
3418 return sched.run(func, true, true);
3419 }
3420
3421 void
3422 CodeEmitterNVC0::prepareEmission(Function *func)
3423 {
3424 CodeEmitter::prepareEmission(func);
3425
3426 if (targ->hasSWSched)
3427 calculateSchedDataNVC0(targ, func);
3428 }
3429
3430 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3431 : CodeEmitter(target),
3432 targNVC0(target),
3433 writeIssueDelays(target->hasSWSched)
3434 {
3435 code = NULL;
3436 codeSize = codeSizeLimit = 0;
3437 relocInfo = NULL;
3438 }
3439
3440 CodeEmitter *
3441 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3442 {
3443 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3444 emit->setProgramType(type);
3445 return emit;
3446 }
3447
3448 CodeEmitter *
3449 TargetNVC0::getCodeEmitter(Program::Type type)
3450 {
3451 if (chipset >= NVISA_GK20A_CHIPSET)
3452 return createCodeEmitterGK110(type);
3453 return createCodeEmitterNVC0(type);
3454 }
3455
3456 } // namespace nv50_ir