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[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitSUAddr(const TexInstruction *);
67 void emitSUDim(const TexInstruction *);
68 void emitCachingMode(CacheMode c);
69
70 void emitShortSrc2(const ValueRef&);
71
72 inline uint8_t getSRegEncoding(const ValueRef&);
73
74 void roundMode_A(const Instruction *);
75 void roundMode_C(const Instruction *);
76 void roundMode_CS(const Instruction *);
77
78 void emitNegAbs12(const Instruction *);
79
80 void emitNOP(const Instruction *);
81
82 void emitLOAD(const Instruction *);
83 void emitSTORE(const Instruction *);
84 void emitMOV(const Instruction *);
85 void emitATOM(const Instruction *);
86 void emitMEMBAR(const Instruction *);
87 void emitCCTL(const Instruction *);
88
89 void emitINTERP(const Instruction *);
90 void emitAFETCH(const Instruction *);
91 void emitPFETCH(const Instruction *);
92 void emitVFETCH(const Instruction *);
93 void emitEXPORT(const Instruction *);
94 void emitOUT(const Instruction *);
95
96 void emitUADD(const Instruction *);
97 void emitFADD(const Instruction *);
98 void emitDADD(const Instruction *);
99 void emitUMUL(const Instruction *);
100 void emitFMUL(const Instruction *);
101 void emitDMUL(const Instruction *);
102 void emitIMAD(const Instruction *);
103 void emitISAD(const Instruction *);
104 void emitFMAD(const Instruction *);
105 void emitDMAD(const Instruction *);
106 void emitMADSP(const Instruction *);
107
108 void emitNOT(Instruction *);
109 void emitLogicOp(const Instruction *, uint8_t subOp);
110 void emitPOPC(const Instruction *);
111 void emitINSBF(const Instruction *);
112 void emitEXTBF(const Instruction *);
113 void emitBFIND(const Instruction *);
114 void emitPERMT(const Instruction *);
115 void emitShift(const Instruction *);
116
117 void emitSFnOp(const Instruction *, uint8_t subOp);
118
119 void emitCVT(Instruction *);
120 void emitMINMAX(const Instruction *);
121 void emitPreOp(const Instruction *);
122
123 void emitSET(const CmpInstruction *);
124 void emitSLCT(const CmpInstruction *);
125 void emitSELP(const Instruction *);
126
127 void emitTEXBAR(const Instruction *);
128 void emitTEX(const TexInstruction *);
129 void emitTEXCSAA(const TexInstruction *);
130 void emitTXQ(const TexInstruction *);
131
132 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
133
134 void emitFlow(const Instruction *);
135 void emitBAR(const Instruction *);
136
137 void emitSUCLAMPMode(uint16_t);
138 void emitSUCalc(Instruction *);
139 void emitSULDGB(const TexInstruction *);
140 void emitSUSTGx(const TexInstruction *);
141
142 void emitSULDB(const TexInstruction *);
143 void emitSUSTx(const TexInstruction *);
144 void emitSULEA(const TexInstruction *);
145
146 void emitVSHL(const Instruction *);
147 void emitVectorSubOp(const Instruction *);
148
149 void emitPIXLD(const Instruction *);
150
151 void emitVOTE(const Instruction *);
152
153 inline void defId(const ValueDef&, const int pos);
154 inline void defId(const Instruction *, int d, const int pos);
155 inline void srcId(const ValueRef&, const int pos);
156 inline void srcId(const ValueRef *, const int pos);
157 inline void srcId(const Instruction *, int s, const int pos);
158 inline void srcAddr32(const ValueRef&, int pos, int shr);
159
160 inline bool isLIMM(const ValueRef&, DataType ty);
161 };
162
163 // for better visibility
164 #define HEX64(h, l) 0x##h##l##ULL
165
166 #define SDATA(a) ((a).rep()->reg.data)
167 #define DDATA(a) ((a).rep()->reg.data)
168
169 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
170 {
171 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
172 }
173
174 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
175 {
176 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
177 }
178
179 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
180 {
181 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
182 code[pos / 32] |= r << (pos % 32);
183 }
184
185 void
186 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
187 {
188 const uint32_t offset = SDATA(src).offset >> shr;
189
190 code[pos / 32] |= offset << (pos % 32);
191 if (pos && (pos < 32))
192 code[1] |= offset >> (32 - pos);
193 }
194
195 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
196 {
197 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
198 }
199
200 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
201 {
202 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
203 code[pos / 32] |= r << (pos % 32);
204 }
205
206 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
207 {
208 const ImmediateValue *imm = ref.get()->asImm();
209
210 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
211 }
212
213 void
214 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
215 {
216 switch (insn->rnd) {
217 case ROUND_M: code[1] |= 1 << 23; break;
218 case ROUND_P: code[1] |= 2 << 23; break;
219 case ROUND_Z: code[1] |= 3 << 23; break;
220 default:
221 assert(insn->rnd == ROUND_N);
222 break;
223 }
224 }
225
226 void
227 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
228 {
229 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
230 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
231 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
232 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
233 }
234
235 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
236 {
237 uint8_t val;
238
239 switch (cc) {
240 case CC_LT: val = 0x1; break;
241 case CC_LTU: val = 0x9; break;
242 case CC_EQ: val = 0x2; break;
243 case CC_EQU: val = 0xa; break;
244 case CC_LE: val = 0x3; break;
245 case CC_LEU: val = 0xb; break;
246 case CC_GT: val = 0x4; break;
247 case CC_GTU: val = 0xc; break;
248 case CC_NE: val = 0x5; break;
249 case CC_NEU: val = 0xd; break;
250 case CC_GE: val = 0x6; break;
251 case CC_GEU: val = 0xe; break;
252 case CC_TR: val = 0xf; break;
253 case CC_FL: val = 0x0; break;
254
255 case CC_A: val = 0x14; break;
256 case CC_NA: val = 0x13; break;
257 case CC_S: val = 0x15; break;
258 case CC_NS: val = 0x12; break;
259 case CC_C: val = 0x16; break;
260 case CC_NC: val = 0x11; break;
261 case CC_O: val = 0x17; break;
262 case CC_NO: val = 0x10; break;
263
264 default:
265 val = 0;
266 assert(!"invalid condition code");
267 break;
268 }
269 code[pos / 32] |= val << (pos % 32);
270 }
271
272 void
273 CodeEmitterNVC0::emitPredicate(const Instruction *i)
274 {
275 if (i->predSrc >= 0) {
276 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
277 srcId(i->src(i->predSrc), 10);
278 if (i->cc == CC_NOT_P)
279 code[0] |= 0x2000; // negate
280 } else {
281 code[0] |= 0x1c00;
282 }
283 }
284
285 void
286 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
287 {
288 switch (src.getFile()) {
289 case FILE_MEMORY_GLOBAL:
290 srcAddr32(src, 26, 0);
291 break;
292 case FILE_MEMORY_LOCAL:
293 case FILE_MEMORY_SHARED:
294 setAddress24(src);
295 break;
296 default:
297 assert(src.getFile() == FILE_MEMORY_CONST);
298 setAddress16(src);
299 break;
300 }
301 }
302
303 void
304 CodeEmitterNVC0::setAddress16(const ValueRef& src)
305 {
306 Symbol *sym = src.get()->asSym();
307
308 assert(sym);
309
310 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
311 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
312 }
313
314 void
315 CodeEmitterNVC0::setAddress24(const ValueRef& src)
316 {
317 Symbol *sym = src.get()->asSym();
318
319 assert(sym);
320
321 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
322 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
323 }
324
325 void
326 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
327 {
328 const ImmediateValue *imm = i->src(s).get()->asImm();
329 uint32_t u32;
330
331 assert(imm);
332 u32 = imm->reg.data.u32;
333
334 if ((code[0] & 0xf) == 0x1) {
335 // double immediate
336 uint64_t u64 = imm->reg.data.u64;
337 assert(!(u64 & 0x00000fffffffffffULL));
338 assert(!(code[1] & 0xc000));
339 code[0] |= ((u64 >> 44) & 0x3f) << 26;
340 code[1] |= 0xc000 | (u64 >> 50);
341 } else
342 if ((code[0] & 0xf) == 0x2) {
343 // LIMM
344 code[0] |= (u32 & 0x3f) << 26;
345 code[1] |= u32 >> 6;
346 } else
347 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
348 // integer immediate
349 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
350 assert(!(code[1] & 0xc000));
351 u32 &= 0xfffff;
352 code[0] |= (u32 & 0x3f) << 26;
353 code[1] |= 0xc000 | (u32 >> 6);
354 } else {
355 // float immediate
356 assert(!(u32 & 0x00000fff));
357 assert(!(code[1] & 0xc000));
358 code[0] |= ((u32 >> 12) & 0x3f) << 26;
359 code[1] |= 0xc000 | (u32 >> 18);
360 }
361 }
362
363 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
364 {
365 const ImmediateValue *imm = ref.get()->asImm();
366
367 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
368
369 assert(s8 == imm->reg.data.s32);
370
371 code[0] |= (s8 & 0x3f) << 26;
372 code[0] |= (s8 >> 6) << 8;
373 }
374
375 void
376 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
377 {
378 code[0] = opc;
379 code[1] = opc >> 32;
380
381 emitPredicate(i);
382
383 defId(i->def(0), 14);
384
385 int s1 = 26;
386 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
387 s1 = 49;
388
389 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
390 switch (i->getSrc(s)->reg.file) {
391 case FILE_MEMORY_CONST:
392 assert(!(code[1] & 0xc000));
393 code[1] |= (s == 2) ? 0x8000 : 0x4000;
394 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
395 setAddress16(i->src(s));
396 break;
397 case FILE_IMMEDIATE:
398 assert(s == 1 ||
399 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
400 assert(!(code[1] & 0xc000));
401 setImmediate(i, s);
402 break;
403 case FILE_GPR:
404 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
405 break;
406 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
407 break;
408 default:
409 if (i->op == OP_SELP) {
410 // OP_SELP is used to implement shared+atomics on Fermi.
411 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
412 srcId(i->src(s), 49);
413 }
414 // ignore here, can be predicate or flags, but must not be address
415 break;
416 }
417 }
418 }
419
420 void
421 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
422 {
423 code[0] = opc;
424 code[1] = opc >> 32;
425
426 emitPredicate(i);
427
428 defId(i->def(0), 14);
429
430 switch (i->src(0).getFile()) {
431 case FILE_MEMORY_CONST:
432 assert(!(code[1] & 0xc000));
433 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
434 setAddress16(i->src(0));
435 break;
436 case FILE_IMMEDIATE:
437 assert(!(code[1] & 0xc000));
438 setImmediate(i, 0);
439 break;
440 case FILE_GPR:
441 srcId(i->src(0), 26);
442 break;
443 default:
444 // ignore here, can be predicate or flags, but must not be address
445 break;
446 }
447 }
448
449 void
450 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
451 {
452 code[0] = opc;
453
454 int ss2a = 0;
455 if (opc == 0x0d || opc == 0x0e)
456 ss2a = 2;
457
458 defId(i->def(0), 14);
459 srcId(i->src(0), 20);
460
461 assert(pred || (i->predSrc < 0));
462 if (pred)
463 emitPredicate(i);
464
465 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
466 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
467 assert(!(code[0] & (0x300 >> ss2a)));
468 switch (i->src(s).get()->reg.fileIndex) {
469 case 0: code[0] |= 0x100 >> ss2a; break;
470 case 1: code[0] |= 0x200 >> ss2a; break;
471 case 16: code[0] |= 0x300 >> ss2a; break;
472 default:
473 ERROR("invalid c[] space for short form\n");
474 break;
475 }
476 if (s == 1)
477 code[0] |= i->getSrc(s)->reg.data.offset << 24;
478 else
479 code[0] |= i->getSrc(s)->reg.data.offset << 6;
480 } else
481 if (i->src(s).getFile() == FILE_IMMEDIATE) {
482 assert(s == 1);
483 setImmediateS8(i->src(s));
484 } else
485 if (i->src(s).getFile() == FILE_GPR) {
486 srcId(i->src(s), (s == 1) ? 26 : 8);
487 }
488 }
489 }
490
491 void
492 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
493 {
494 if (src.getFile() == FILE_MEMORY_CONST) {
495 switch (src.get()->reg.fileIndex) {
496 case 0: code[0] |= 0x100; break;
497 case 1: code[0] |= 0x200; break;
498 case 16: code[0] |= 0x300; break;
499 default:
500 assert(!"unsupported file index for short op");
501 break;
502 }
503 srcAddr32(src, 20, 2);
504 } else {
505 srcId(src, 20);
506 assert(src.getFile() == FILE_GPR);
507 }
508 }
509
510 void
511 CodeEmitterNVC0::emitNOP(const Instruction *i)
512 {
513 code[0] = 0x000001e4;
514 code[1] = 0x40000000;
515 emitPredicate(i);
516 }
517
518 void
519 CodeEmitterNVC0::emitFMAD(const Instruction *i)
520 {
521 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
522
523 if (i->encSize == 8) {
524 if (isLIMM(i->src(1), TYPE_F32)) {
525 emitForm_A(i, HEX64(20000000, 00000002));
526 } else {
527 emitForm_A(i, HEX64(30000000, 00000000));
528
529 if (i->src(2).mod.neg())
530 code[0] |= 1 << 8;
531 }
532 roundMode_A(i);
533
534 if (neg1)
535 code[0] |= 1 << 9;
536
537 if (i->saturate)
538 code[0] |= 1 << 5;
539 if (i->ftz)
540 code[0] |= 1 << 6;
541 } else {
542 assert(!i->saturate && !i->src(2).mod.neg());
543 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
544 false);
545 if (neg1)
546 code[0] |= 1 << 4;
547 }
548 }
549
550 void
551 CodeEmitterNVC0::emitDMAD(const Instruction *i)
552 {
553 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
554
555 emitForm_A(i, HEX64(20000000, 00000001));
556
557 if (i->src(2).mod.neg())
558 code[0] |= 1 << 8;
559
560 roundMode_A(i);
561
562 if (neg1)
563 code[0] |= 1 << 9;
564
565 assert(!i->saturate);
566 assert(!i->ftz);
567 }
568
569 void
570 CodeEmitterNVC0::emitFMUL(const Instruction *i)
571 {
572 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
573
574 assert(i->postFactor >= -3 && i->postFactor <= 3);
575
576 if (i->encSize == 8) {
577 if (isLIMM(i->src(1), TYPE_F32)) {
578 assert(i->postFactor == 0); // constant folded, hopefully
579 emitForm_A(i, HEX64(30000000, 00000002));
580 } else {
581 emitForm_A(i, HEX64(58000000, 00000000));
582 roundMode_A(i);
583 code[1] |= ((i->postFactor > 0) ?
584 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
585 }
586 if (neg)
587 code[1] ^= 1 << 25; // aliases with LIMM sign bit
588
589 if (i->saturate)
590 code[0] |= 1 << 5;
591
592 if (i->dnz)
593 code[0] |= 1 << 7;
594 else
595 if (i->ftz)
596 code[0] |= 1 << 6;
597 } else {
598 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
599 emitForm_S(i, 0xa8, true);
600 }
601 }
602
603 void
604 CodeEmitterNVC0::emitDMUL(const Instruction *i)
605 {
606 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
607
608 emitForm_A(i, HEX64(50000000, 00000001));
609 roundMode_A(i);
610
611 if (neg)
612 code[0] |= 1 << 9;
613
614 assert(!i->saturate);
615 assert(!i->ftz);
616 assert(!i->dnz);
617 assert(!i->postFactor);
618 }
619
620 void
621 CodeEmitterNVC0::emitUMUL(const Instruction *i)
622 {
623 if (i->encSize == 8) {
624 if (i->src(1).getFile() == FILE_IMMEDIATE) {
625 emitForm_A(i, HEX64(10000000, 00000002));
626 } else {
627 emitForm_A(i, HEX64(50000000, 00000003));
628 }
629 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
630 code[0] |= 1 << 6;
631 if (i->sType == TYPE_S32)
632 code[0] |= 1 << 5;
633 if (i->dType == TYPE_S32)
634 code[0] |= 1 << 7;
635 } else {
636 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
637
638 if (i->sType == TYPE_S32)
639 code[0] |= 1 << 6;
640 }
641 }
642
643 void
644 CodeEmitterNVC0::emitFADD(const Instruction *i)
645 {
646 if (i->encSize == 8) {
647 if (isLIMM(i->src(1), TYPE_F32)) {
648 assert(!i->saturate);
649 emitForm_A(i, HEX64(28000000, 00000002));
650
651 code[0] |= i->src(0).mod.abs() << 7;
652 code[0] |= i->src(0).mod.neg() << 9;
653
654 if (i->src(1).mod.abs())
655 code[1] &= 0xfdffffff;
656 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
657 code[1] ^= 0x02000000;
658 } else {
659 emitForm_A(i, HEX64(50000000, 00000000));
660
661 roundMode_A(i);
662 if (i->saturate)
663 code[1] |= 1 << 17;
664
665 emitNegAbs12(i);
666 if (i->op == OP_SUB) code[0] ^= 1 << 8;
667 }
668 if (i->ftz)
669 code[0] |= 1 << 5;
670 } else {
671 assert(!i->saturate && i->op != OP_SUB &&
672 !i->src(0).mod.abs() &&
673 !i->src(1).mod.neg() && !i->src(1).mod.abs());
674
675 emitForm_S(i, 0x49, true);
676
677 if (i->src(0).mod.neg())
678 code[0] |= 1 << 7;
679 }
680 }
681
682 void
683 CodeEmitterNVC0::emitDADD(const Instruction *i)
684 {
685 assert(i->encSize == 8);
686 emitForm_A(i, HEX64(48000000, 00000001));
687 roundMode_A(i);
688 assert(!i->saturate);
689 assert(!i->ftz);
690 emitNegAbs12(i);
691 if (i->op == OP_SUB)
692 code[0] ^= 1 << 8;
693 }
694
695 void
696 CodeEmitterNVC0::emitUADD(const Instruction *i)
697 {
698 uint32_t addOp = 0;
699
700 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
701
702 if (i->src(0).mod.neg())
703 addOp |= 0x200;
704 if (i->src(1).mod.neg())
705 addOp |= 0x100;
706 if (i->op == OP_SUB)
707 addOp ^= 0x100;
708
709 assert(addOp != 0x300); // would be add-plus-one
710
711 if (i->encSize == 8) {
712 if (isLIMM(i->src(1), TYPE_U32)) {
713 emitForm_A(i, HEX64(08000000, 00000002));
714 if (i->defExists(1))
715 code[1] |= 1 << 26; // write carry
716 } else {
717 emitForm_A(i, HEX64(48000000, 00000003));
718 if (i->defExists(1))
719 code[1] |= 1 << 16; // write carry
720 }
721 code[0] |= addOp;
722
723 if (i->saturate)
724 code[0] |= 1 << 5;
725 if (i->flagsSrc >= 0) // add carry
726 code[0] |= 1 << 6;
727 } else {
728 assert(!(addOp & 0x100));
729 emitForm_S(i, (addOp >> 3) |
730 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
731 }
732 }
733
734 // TODO: shl-add
735 void
736 CodeEmitterNVC0::emitIMAD(const Instruction *i)
737 {
738 uint8_t addOp =
739 (i->src(2).mod.neg() << 1) | (i->src(0).mod.neg() ^ i->src(1).mod.neg());
740
741 assert(i->encSize == 8);
742 emitForm_A(i, HEX64(20000000, 00000003));
743
744 assert(addOp != 3);
745 code[0] |= addOp << 8;
746
747 if (isSignedType(i->dType))
748 code[0] |= 1 << 7;
749 if (isSignedType(i->sType))
750 code[0] |= 1 << 5;
751
752 code[1] |= i->saturate << 24;
753
754 if (i->flagsDef >= 0) code[1] |= 1 << 16;
755 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
756
757 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
758 code[0] |= 1 << 6;
759 }
760
761 void
762 CodeEmitterNVC0::emitMADSP(const Instruction *i)
763 {
764 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
765
766 emitForm_A(i, HEX64(00000000, 00000003));
767
768 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
769 code[1] |= 0x01800000;
770 } else {
771 code[0] |= (i->subOp & 0x00f) << 7;
772 code[0] |= (i->subOp & 0x0f0) << 1;
773 code[0] |= (i->subOp & 0x100) >> 3;
774 code[0] |= (i->subOp & 0x200) >> 2;
775 code[1] |= (i->subOp & 0xc00) << 13;
776 }
777
778 if (i->flagsDef >= 0)
779 code[1] |= 1 << 16;
780 }
781
782 void
783 CodeEmitterNVC0::emitISAD(const Instruction *i)
784 {
785 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
786 assert(i->encSize == 8);
787
788 emitForm_A(i, HEX64(38000000, 00000003));
789
790 if (i->dType == TYPE_S32)
791 code[0] |= 1 << 5;
792 }
793
794 void
795 CodeEmitterNVC0::emitNOT(Instruction *i)
796 {
797 assert(i->encSize == 8);
798 i->setSrc(1, i->src(0));
799 emitForm_A(i, HEX64(68000000, 000001c3));
800 }
801
802 void
803 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
804 {
805 if (i->def(0).getFile() == FILE_PREDICATE) {
806 code[0] = 0x00000004 | (subOp << 30);
807 code[1] = 0x0c000000;
808
809 emitPredicate(i);
810
811 defId(i->def(0), 17);
812 srcId(i->src(0), 20);
813 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
814 srcId(i->src(1), 26);
815 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
816
817 if (i->defExists(1)) {
818 defId(i->def(1), 14);
819 } else {
820 code[0] |= 7 << 14;
821 }
822 // (a OP b) OP c
823 if (i->predSrc != 2 && i->srcExists(2)) {
824 code[1] |= subOp << 21;
825 srcId(i->src(2), 49);
826 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 20;
827 } else {
828 code[1] |= 0x000e0000;
829 }
830 } else
831 if (i->encSize == 8) {
832 if (isLIMM(i->src(1), TYPE_U32)) {
833 emitForm_A(i, HEX64(38000000, 00000002));
834
835 if (i->flagsDef >= 0)
836 code[1] |= 1 << 26;
837 } else {
838 emitForm_A(i, HEX64(68000000, 00000003));
839
840 if (i->flagsDef >= 0)
841 code[1] |= 1 << 16;
842 }
843 code[0] |= subOp << 6;
844
845 if (i->flagsSrc >= 0) // carry
846 code[0] |= 1 << 5;
847
848 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
849 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
850 } else {
851 emitForm_S(i, (subOp << 5) |
852 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
853 }
854 }
855
856 void
857 CodeEmitterNVC0::emitPOPC(const Instruction *i)
858 {
859 emitForm_A(i, HEX64(54000000, 00000004));
860
861 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
862 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
863 }
864
865 void
866 CodeEmitterNVC0::emitINSBF(const Instruction *i)
867 {
868 emitForm_A(i, HEX64(28000000, 00000003));
869 }
870
871 void
872 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
873 {
874 emitForm_A(i, HEX64(70000000, 00000003));
875
876 if (i->dType == TYPE_S32)
877 code[0] |= 1 << 5;
878 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
879 code[0] |= 1 << 8;
880 }
881
882 void
883 CodeEmitterNVC0::emitBFIND(const Instruction *i)
884 {
885 emitForm_B(i, HEX64(78000000, 00000003));
886
887 if (i->dType == TYPE_S32)
888 code[0] |= 1 << 5;
889 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
890 code[0] |= 1 << 8;
891 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
892 code[0] |= 1 << 6;
893 }
894
895 void
896 CodeEmitterNVC0::emitPERMT(const Instruction *i)
897 {
898 emitForm_A(i, HEX64(24000000, 00000004));
899
900 code[0] |= i->subOp << 5;
901 }
902
903 void
904 CodeEmitterNVC0::emitShift(const Instruction *i)
905 {
906 if (i->op == OP_SHR) {
907 emitForm_A(i, HEX64(58000000, 00000003)
908 | (isSignedType(i->dType) ? 0x20 : 0x00));
909 } else {
910 emitForm_A(i, HEX64(60000000, 00000003));
911 }
912
913 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
914 code[0] |= 1 << 9;
915 }
916
917 void
918 CodeEmitterNVC0::emitPreOp(const Instruction *i)
919 {
920 if (i->encSize == 8) {
921 emitForm_B(i, HEX64(60000000, 00000000));
922
923 if (i->op == OP_PREEX2)
924 code[0] |= 0x20;
925
926 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
927 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
928 } else {
929 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
930 }
931 }
932
933 void
934 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
935 {
936 if (i->encSize == 8) {
937 code[0] = 0x00000000 | (subOp << 26);
938 code[1] = 0xc8000000;
939
940 emitPredicate(i);
941
942 defId(i->def(0), 14);
943 srcId(i->src(0), 20);
944
945 assert(i->src(0).getFile() == FILE_GPR);
946
947 if (i->saturate) code[0] |= 1 << 5;
948
949 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
950 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
951 } else {
952 emitForm_S(i, 0x80000008 | (subOp << 26), true);
953
954 assert(!i->src(0).mod.neg());
955 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
956 }
957 }
958
959 void
960 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
961 {
962 uint64_t op;
963
964 assert(i->encSize == 8);
965
966 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
967
968 if (i->ftz)
969 op |= 1 << 5;
970 else
971 if (!isFloatType(i->dType))
972 op |= isSignedType(i->dType) ? 0x23 : 0x03;
973 if (i->dType == TYPE_F64)
974 op |= 0x01;
975
976 emitForm_A(i, op);
977 emitNegAbs12(i);
978 }
979
980 void
981 CodeEmitterNVC0::roundMode_C(const Instruction *i)
982 {
983 switch (i->rnd) {
984 case ROUND_M: code[1] |= 1 << 17; break;
985 case ROUND_P: code[1] |= 2 << 17; break;
986 case ROUND_Z: code[1] |= 3 << 17; break;
987 case ROUND_NI: code[0] |= 1 << 7; break;
988 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
989 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
990 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
991 case ROUND_N: break;
992 default:
993 assert(!"invalid round mode");
994 break;
995 }
996 }
997
998 void
999 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
1000 {
1001 switch (i->rnd) {
1002 case ROUND_M:
1003 case ROUND_MI: code[0] |= 1 << 16; break;
1004 case ROUND_P:
1005 case ROUND_PI: code[0] |= 2 << 16; break;
1006 case ROUND_Z:
1007 case ROUND_ZI: code[0] |= 3 << 16; break;
1008 default:
1009 break;
1010 }
1011 }
1012
1013 void
1014 CodeEmitterNVC0::emitCVT(Instruction *i)
1015 {
1016 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1017 DataType dType;
1018
1019 switch (i->op) {
1020 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1021 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1022 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1023 default:
1024 break;
1025 }
1026
1027 const bool sat = (i->op == OP_SAT) || i->saturate;
1028 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1029 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1030
1031 if (i->op == OP_NEG && i->dType == TYPE_U32)
1032 dType = TYPE_S32;
1033 else
1034 dType = i->dType;
1035
1036 if (i->encSize == 8) {
1037 emitForm_B(i, HEX64(10000000, 00000004));
1038
1039 roundMode_C(i);
1040
1041 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1042 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1043 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1044
1045 // for 8/16 source types, the byte/word is in subOp. word 1 is
1046 // represented as 2.
1047 if (!isFloatType(i->sType))
1048 code[1] |= i->subOp << 0x17;
1049 else
1050 code[1] |= i->subOp << 0x18;
1051
1052 if (sat)
1053 code[0] |= 0x20;
1054 if (abs)
1055 code[0] |= 1 << 6;
1056 if (neg && i->op != OP_ABS)
1057 code[0] |= 1 << 8;
1058
1059 if (i->ftz)
1060 code[1] |= 1 << 23;
1061
1062 if (isSignedIntType(dType))
1063 code[0] |= 0x080;
1064 if (isSignedIntType(i->sType))
1065 code[0] |= 0x200;
1066
1067 if (isFloatType(dType)) {
1068 if (!isFloatType(i->sType))
1069 code[1] |= 0x08000000;
1070 } else {
1071 if (isFloatType(i->sType))
1072 code[1] |= 0x04000000;
1073 else
1074 code[1] |= 0x0c000000;
1075 }
1076 } else {
1077 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1078 code[0] = 0x298;
1079 } else
1080 if (isFloatType(dType)) {
1081 if (isFloatType(i->sType))
1082 code[0] = 0x098;
1083 else
1084 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1085 } else {
1086 assert(isFloatType(i->sType));
1087
1088 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1089 }
1090
1091 if (neg) code[0] |= 1 << 16;
1092 if (sat) code[0] |= 1 << 18;
1093 if (abs) code[0] |= 1 << 19;
1094
1095 roundMode_CS(i);
1096 }
1097 }
1098
1099 void
1100 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1101 {
1102 uint32_t hi;
1103 uint32_t lo = 0;
1104
1105 if (i->sType == TYPE_F64)
1106 lo = 0x1;
1107 else
1108 if (!isFloatType(i->sType))
1109 lo = 0x3;
1110
1111 if (isSignedIntType(i->sType))
1112 lo |= 0x20;
1113 if (isFloatType(i->dType)) {
1114 if (isFloatType(i->sType))
1115 lo |= 0x20;
1116 else
1117 lo |= 0x80;
1118 }
1119
1120 switch (i->op) {
1121 case OP_SET_AND: hi = 0x10000000; break;
1122 case OP_SET_OR: hi = 0x10200000; break;
1123 case OP_SET_XOR: hi = 0x10400000; break;
1124 default:
1125 hi = 0x100e0000;
1126 break;
1127 }
1128 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1129
1130 if (i->op != OP_SET)
1131 srcId(i->src(2), 32 + 17);
1132
1133 if (i->def(0).getFile() == FILE_PREDICATE) {
1134 if (i->sType == TYPE_F32)
1135 code[1] += 0x10000000;
1136 else
1137 code[1] += 0x08000000;
1138
1139 code[0] &= ~0xfc000;
1140 defId(i->def(0), 17);
1141 if (i->defExists(1))
1142 defId(i->def(1), 14);
1143 else
1144 code[0] |= 0x1c000;
1145 }
1146
1147 if (i->ftz)
1148 code[1] |= 1 << 27;
1149
1150 emitCondCode(i->setCond, 32 + 23);
1151 emitNegAbs12(i);
1152 }
1153
1154 void
1155 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1156 {
1157 uint64_t op;
1158
1159 switch (i->dType) {
1160 case TYPE_S32:
1161 op = HEX64(30000000, 00000023);
1162 break;
1163 case TYPE_U32:
1164 op = HEX64(30000000, 00000003);
1165 break;
1166 case TYPE_F32:
1167 op = HEX64(38000000, 00000000);
1168 break;
1169 default:
1170 assert(!"invalid type for SLCT");
1171 op = 0;
1172 break;
1173 }
1174 emitForm_A(i, op);
1175
1176 CondCode cc = i->setCond;
1177
1178 if (i->src(2).mod.neg())
1179 cc = reverseCondCode(cc);
1180
1181 emitCondCode(cc, 32 + 23);
1182
1183 if (i->ftz)
1184 code[0] |= 1 << 5;
1185 }
1186
1187 static void
1188 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1189 {
1190 int loc = entry->loc;
1191 if (data.force_persample_interp)
1192 code[loc + 1] |= 1 << 20;
1193 else
1194 code[loc + 1] &= ~(1 << 20);
1195 }
1196
1197 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1198 {
1199 emitForm_A(i, HEX64(20000000, 00000004));
1200
1201 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1202 code[1] |= 1 << 20;
1203
1204 if (i->subOp == 1) {
1205 addInterp(0, 0, selpFlip);
1206 }
1207 }
1208
1209 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1210 {
1211 code[0] = 0x00000006 | (i->subOp << 26);
1212 code[1] = 0xf0000000;
1213 emitPredicate(i);
1214 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1215 }
1216
1217 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1218 {
1219 code[0] = 0x00000086;
1220 code[1] = 0xd0000000;
1221
1222 code[1] |= i->tex.r;
1223 code[1] |= i->tex.s << 8;
1224
1225 if (i->tex.liveOnly)
1226 code[0] |= 1 << 9;
1227
1228 defId(i->def(0), 14);
1229 srcId(i->src(0), 20);
1230 }
1231
1232 static inline bool
1233 isNextIndependentTex(const TexInstruction *i)
1234 {
1235 if (!i->next || !isTextureOp(i->next->op))
1236 return false;
1237 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1238 return false;
1239 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1240 }
1241
1242 void
1243 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1244 {
1245 code[0] = 0x00000006;
1246
1247 if (isNextIndependentTex(i))
1248 code[0] |= 0x080; // t mode
1249 else
1250 code[0] |= 0x100; // p mode
1251
1252 if (i->tex.liveOnly)
1253 code[0] |= 1 << 9;
1254
1255 switch (i->op) {
1256 case OP_TEX: code[1] = 0x80000000; break;
1257 case OP_TXB: code[1] = 0x84000000; break;
1258 case OP_TXL: code[1] = 0x86000000; break;
1259 case OP_TXF: code[1] = 0x90000000; break;
1260 case OP_TXG: code[1] = 0xa0000000; break;
1261 case OP_TXLQ: code[1] = 0xb0000000; break;
1262 case OP_TXD: code[1] = 0xe0000000; break;
1263 default:
1264 assert(!"invalid texture op");
1265 break;
1266 }
1267 if (i->op == OP_TXF) {
1268 if (!i->tex.levelZero)
1269 code[1] |= 0x02000000;
1270 } else
1271 if (i->tex.levelZero) {
1272 code[1] |= 0x02000000;
1273 }
1274
1275 if (i->op != OP_TXD && i->tex.derivAll)
1276 code[1] |= 1 << 13;
1277
1278 defId(i->def(0), 14);
1279 srcId(i->src(0), 20);
1280
1281 emitPredicate(i);
1282
1283 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1284
1285 code[1] |= i->tex.mask << 14;
1286
1287 code[1] |= i->tex.r;
1288 code[1] |= i->tex.s << 8;
1289 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1290 code[1] |= 1 << 18; // in 1st source (with array index)
1291
1292 // texture target:
1293 code[1] |= (i->tex.target.getDim() - 1) << 20;
1294 if (i->tex.target.isCube())
1295 code[1] += 2 << 20;
1296 if (i->tex.target.isArray())
1297 code[1] |= 1 << 19;
1298 if (i->tex.target.isShadow())
1299 code[1] |= 1 << 24;
1300
1301 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1302
1303 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1304 // lzero
1305 if (i->op == OP_TXL)
1306 code[1] &= ~(1 << 26);
1307 else
1308 if (i->op == OP_TXF)
1309 code[1] &= ~(1 << 25);
1310 }
1311 if (i->tex.target == TEX_TARGET_2D_MS ||
1312 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1313 code[1] |= 1 << 23;
1314
1315 if (i->tex.useOffsets == 1)
1316 code[1] |= 1 << 22;
1317 if (i->tex.useOffsets == 4)
1318 code[1] |= 1 << 23;
1319
1320 srcId(i, src1, 26);
1321 }
1322
1323 void
1324 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1325 {
1326 code[0] = 0x00000086;
1327 code[1] = 0xc0000000;
1328
1329 switch (i->tex.query) {
1330 case TXQ_DIMS: code[1] |= 0 << 22; break;
1331 case TXQ_TYPE: code[1] |= 1 << 22; break;
1332 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1333 case TXQ_FILTER: code[1] |= 3 << 22; break;
1334 case TXQ_LOD: code[1] |= 4 << 22; break;
1335 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1336 default:
1337 assert(!"invalid texture query");
1338 break;
1339 }
1340
1341 code[1] |= i->tex.mask << 14;
1342
1343 code[1] |= i->tex.r;
1344 code[1] |= i->tex.s << 8;
1345 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1346 code[1] |= 1 << 18;
1347
1348 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1349
1350 defId(i->def(0), 14);
1351 srcId(i->src(0), 20);
1352 srcId(i, src1, 26);
1353
1354 emitPredicate(i);
1355 }
1356
1357 void
1358 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1359 {
1360 code[0] = 0x00000200 | (laneMask << 6); // dall
1361 code[1] = 0x48000000 | qOp;
1362
1363 defId(i->def(0), 14);
1364 srcId(i->src(0), 20);
1365 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1366
1367 emitPredicate(i);
1368 }
1369
1370 void
1371 CodeEmitterNVC0::emitFlow(const Instruction *i)
1372 {
1373 const FlowInstruction *f = i->asFlow();
1374
1375 unsigned mask; // bit 0: predicate, bit 1: target
1376
1377 code[0] = 0x00000007;
1378
1379 switch (i->op) {
1380 case OP_BRA:
1381 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1382 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1383 code[0] |= 0x4000;
1384 mask = 3;
1385 break;
1386 case OP_CALL:
1387 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1388 if (f->indirect)
1389 code[0] |= 0x4000; // indirect calls always use c[] source
1390 mask = 2;
1391 break;
1392
1393 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1394 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1395 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1396 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1397 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1398
1399 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1400 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1401 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1402 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1403
1404 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1405 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1406 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1407 default:
1408 assert(!"invalid flow operation");
1409 return;
1410 }
1411
1412 if (mask & 1) {
1413 emitPredicate(i);
1414 if (i->flagsSrc < 0)
1415 code[0] |= 0x1e0;
1416 }
1417
1418 if (!f)
1419 return;
1420
1421 if (f->allWarp)
1422 code[0] |= 1 << 15;
1423 if (f->limit)
1424 code[0] |= 1 << 16;
1425
1426 if (f->indirect) {
1427 if (code[0] & 0x4000) {
1428 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1429 setAddress16(i->src(0));
1430 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1431 if (f->op == OP_BRA)
1432 srcId(f->src(0).getIndirect(0), 20);
1433 } else {
1434 srcId(f, 0, 20);
1435 }
1436 }
1437
1438 if (f->op == OP_CALL) {
1439 if (f->indirect) {
1440 // nothing
1441 } else
1442 if (f->builtin) {
1443 assert(f->absolute);
1444 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1445 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1446 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1447 } else {
1448 assert(!f->absolute);
1449 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1450 code[0] |= (pcRel & 0x3f) << 26;
1451 code[1] |= (pcRel >> 6) & 0x3ffff;
1452 }
1453 } else
1454 if (mask & 2) {
1455 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1456 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1457 pcRel += 8;
1458 // currently we don't want absolute branches
1459 assert(!f->absolute);
1460 code[0] |= (pcRel & 0x3f) << 26;
1461 code[1] |= (pcRel >> 6) & 0x3ffff;
1462 }
1463 }
1464
1465 void
1466 CodeEmitterNVC0::emitBAR(const Instruction *i)
1467 {
1468 Value *rDef = NULL, *pDef = NULL;
1469
1470 switch (i->subOp) {
1471 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1472 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1473 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1474 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1475 default:
1476 code[0] = 0x04;
1477 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1478 break;
1479 }
1480 code[1] = 0x50000000;
1481
1482 code[0] |= 63 << 14;
1483 code[1] |= 7 << 21;
1484
1485 emitPredicate(i);
1486
1487 // barrier id
1488 if (i->src(0).getFile() == FILE_GPR) {
1489 srcId(i->src(0), 20);
1490 } else {
1491 ImmediateValue *imm = i->getSrc(0)->asImm();
1492 assert(imm);
1493 code[0] |= imm->reg.data.u32 << 20;
1494 code[1] |= 0x8000;
1495 }
1496
1497 // thread count
1498 if (i->src(1).getFile() == FILE_GPR) {
1499 srcId(i->src(1), 26);
1500 } else {
1501 ImmediateValue *imm = i->getSrc(1)->asImm();
1502 assert(imm);
1503 assert(imm->reg.data.u32 <= 0xfff);
1504 code[0] |= imm->reg.data.u32 << 26;
1505 code[1] |= imm->reg.data.u32 >> 6;
1506 code[1] |= 0x4000;
1507 }
1508
1509 if (i->srcExists(2) && (i->predSrc != 2)) {
1510 srcId(i->src(2), 32 + 17);
1511 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1512 code[1] |= 1 << 20;
1513 } else {
1514 code[1] |= 7 << 17;
1515 }
1516
1517 if (i->defExists(0)) {
1518 if (i->def(0).getFile() == FILE_GPR)
1519 rDef = i->getDef(0);
1520 else
1521 pDef = i->getDef(0);
1522
1523 if (i->defExists(1)) {
1524 if (i->def(1).getFile() == FILE_GPR)
1525 rDef = i->getDef(1);
1526 else
1527 pDef = i->getDef(1);
1528 }
1529 }
1530 if (rDef) {
1531 code[0] &= ~(63 << 14);
1532 defId(rDef, 14);
1533 }
1534 if (pDef) {
1535 code[1] &= ~(7 << 21);
1536 defId(pDef, 32 + 21);
1537 }
1538 }
1539
1540 void
1541 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1542 {
1543 code[0] = 0x00000006;
1544 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1545
1546 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1547 code[0] |= 0x200;
1548
1549 emitPredicate(i);
1550
1551 defId(i->def(0), 14);
1552 srcId(i->src(0).getIndirect(0), 20);
1553 }
1554
1555 void
1556 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1557 {
1558 uint32_t prim = i->src(0).get()->reg.data.u32;
1559
1560 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1561 code[1] = 0x00000000 | (prim >> 6);
1562
1563 emitPredicate(i);
1564
1565 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1566
1567 defId(i->def(0), 14);
1568 srcId(i, src1, 20);
1569 }
1570
1571 void
1572 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1573 {
1574 code[0] = 0x00000006;
1575 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1576
1577 if (i->perPatch)
1578 code[0] |= 0x100;
1579 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1580 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1581
1582 emitPredicate(i);
1583
1584 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1585
1586 defId(i->def(0), 14);
1587 srcId(i->src(0).getIndirect(0), 20);
1588 srcId(i->src(0).getIndirect(1), 26); // vertex address
1589 }
1590
1591 void
1592 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1593 {
1594 unsigned int size = typeSizeof(i->dType);
1595
1596 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1597 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1598
1599 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1600
1601 if (i->perPatch)
1602 code[0] |= 0x100;
1603
1604 emitPredicate(i);
1605
1606 assert(i->src(1).getFile() == FILE_GPR);
1607
1608 srcId(i->src(0).getIndirect(0), 20);
1609 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1610 srcId(i->src(1), 26);
1611 }
1612
1613 void
1614 CodeEmitterNVC0::emitOUT(const Instruction *i)
1615 {
1616 code[0] = 0x00000006;
1617 code[1] = 0x1c000000;
1618
1619 emitPredicate(i);
1620
1621 defId(i->def(0), 14); // new secret address
1622 srcId(i->src(0), 20); // old secret address, should be 0 initially
1623
1624 assert(i->src(0).getFile() == FILE_GPR);
1625
1626 if (i->op == OP_EMIT)
1627 code[0] |= 1 << 5;
1628 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1629 code[0] |= 1 << 6;
1630
1631 // vertex stream
1632 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1633 unsigned int stream = SDATA(i->src(1)).u32;
1634 assert(stream < 4);
1635 if (stream) {
1636 code[1] |= 0xc000;
1637 code[0] |= stream << 26;
1638 } else {
1639 srcId(NULL, 26);
1640 }
1641 } else {
1642 srcId(i->src(1), 26);
1643 }
1644 }
1645
1646 void
1647 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1648 {
1649 if (i->encSize == 8) {
1650 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1651 } else {
1652 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1653 code[0] |= 0x80;
1654 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1655 }
1656 }
1657
1658 static void
1659 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1660 {
1661 int ipa = entry->ipa;
1662 int reg = entry->reg;
1663 int loc = entry->loc;
1664
1665 if (data.flatshade &&
1666 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1667 ipa = NV50_IR_INTERP_FLAT;
1668 reg = 0x3f;
1669 } else if (data.force_persample_interp &&
1670 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1671 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1672 ipa |= NV50_IR_INTERP_CENTROID;
1673 }
1674 code[loc + 0] &= ~(0xf << 6);
1675 code[loc + 0] |= ipa << 6;
1676 code[loc + 0] &= ~(0x3f << 26);
1677 code[loc + 0] |= reg << 26;
1678 }
1679
1680 void
1681 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1682 {
1683 const uint32_t base = i->getSrc(0)->reg.data.offset;
1684
1685 if (i->encSize == 8) {
1686 code[0] = 0x00000000;
1687 code[1] = 0xc0000000 | (base & 0xffff);
1688
1689 if (i->saturate)
1690 code[0] |= 1 << 5;
1691
1692 if (i->op == OP_PINTERP) {
1693 srcId(i->src(1), 26);
1694 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1695 } else {
1696 code[0] |= 0x3f << 26;
1697 addInterp(i->ipa, 0x3f, interpApply);
1698 }
1699
1700 srcId(i->src(0).getIndirect(0), 20);
1701 } else {
1702 assert(i->op == OP_PINTERP);
1703 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1704 srcId(i->src(1), 20);
1705 }
1706 emitInterpMode(i);
1707
1708 emitPredicate(i);
1709 defId(i->def(0), 14);
1710
1711 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1712 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1713 else
1714 code[1] |= 0x3f << 17;
1715 }
1716
1717 void
1718 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1719 {
1720 uint8_t val;
1721
1722 switch (ty) {
1723 case TYPE_U8:
1724 val = 0x00;
1725 break;
1726 case TYPE_S8:
1727 val = 0x20;
1728 break;
1729 case TYPE_F16:
1730 case TYPE_U16:
1731 val = 0x40;
1732 break;
1733 case TYPE_S16:
1734 val = 0x60;
1735 break;
1736 case TYPE_F32:
1737 case TYPE_U32:
1738 case TYPE_S32:
1739 val = 0x80;
1740 break;
1741 case TYPE_F64:
1742 case TYPE_U64:
1743 case TYPE_S64:
1744 val = 0xa0;
1745 break;
1746 case TYPE_B128:
1747 val = 0xc0;
1748 break;
1749 default:
1750 val = 0x80;
1751 assert(!"invalid type");
1752 break;
1753 }
1754 code[0] |= val;
1755 }
1756
1757 void
1758 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1759 {
1760 uint32_t val;
1761
1762 switch (c) {
1763 case CACHE_CA:
1764 // case CACHE_WB:
1765 val = 0x000;
1766 break;
1767 case CACHE_CG:
1768 val = 0x100;
1769 break;
1770 case CACHE_CS:
1771 val = 0x200;
1772 break;
1773 case CACHE_CV:
1774 // case CACHE_WT:
1775 val = 0x300;
1776 break;
1777 default:
1778 val = 0;
1779 assert(!"invalid caching mode");
1780 break;
1781 }
1782 code[0] |= val;
1783 }
1784
1785 static inline bool
1786 uses64bitAddress(const Instruction *ldst)
1787 {
1788 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1789 ldst->src(0).isIndirect(0) &&
1790 ldst->getIndirect(0, 0)->reg.size == 8;
1791 }
1792
1793 void
1794 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1795 {
1796 uint32_t opc;
1797
1798 switch (i->src(0).getFile()) {
1799 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1800 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1801 case FILE_MEMORY_SHARED:
1802 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1803 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1804 opc = 0xb8000000;
1805 else
1806 opc = 0xcc000000;
1807 } else {
1808 opc = 0xc9000000;
1809 }
1810 break;
1811 default:
1812 assert(!"invalid memory file");
1813 opc = 0;
1814 break;
1815 }
1816 code[0] = 0x00000005;
1817 code[1] = opc;
1818
1819 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1820 // Unlocked store on shared memory can fail.
1821 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1822 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1823 assert(i->defExists(0));
1824 defId(i->def(0), 8);
1825 }
1826 }
1827
1828 setAddressByFile(i->src(0));
1829 srcId(i->src(1), 14);
1830 srcId(i->src(0).getIndirect(0), 20);
1831 if (uses64bitAddress(i))
1832 code[1] |= 1 << 26;
1833
1834 emitPredicate(i);
1835
1836 emitLoadStoreType(i->dType);
1837 emitCachingMode(i->cache);
1838 }
1839
1840 void
1841 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1842 {
1843 uint32_t opc;
1844
1845 code[0] = 0x00000005;
1846
1847 switch (i->src(0).getFile()) {
1848 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1849 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1850 case FILE_MEMORY_SHARED:
1851 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1852 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1853 opc = 0xa8000000;
1854 else
1855 opc = 0xc4000000;
1856 } else {
1857 opc = 0xc1000000;
1858 }
1859 break;
1860 case FILE_MEMORY_CONST:
1861 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1862 emitMOV(i); // not sure if this is any better
1863 return;
1864 }
1865 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1866 code[0] = 0x00000006 | (i->subOp << 8);
1867 break;
1868 default:
1869 assert(!"invalid memory file");
1870 opc = 0;
1871 break;
1872 }
1873 code[1] = opc;
1874
1875 int r = 0, p = -1;
1876 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1877 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1878 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1879 r = -1;
1880 p = 0;
1881 } else if (i->defExists(1)) { // r, p
1882 p = 1;
1883 } else {
1884 assert(!"Expected predicate dest for load locked");
1885 }
1886 }
1887 }
1888
1889 if (r >= 0)
1890 defId(i->def(r), 14);
1891 else
1892 code[0] |= 63 << 14;
1893
1894 if (p >= 0) {
1895 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1896 defId(i->def(p), 8);
1897 else
1898 defId(i->def(p), 32 + 18);
1899 }
1900
1901 setAddressByFile(i->src(0));
1902 srcId(i->src(0).getIndirect(0), 20);
1903 if (uses64bitAddress(i))
1904 code[1] |= 1 << 26;
1905
1906 emitPredicate(i);
1907
1908 emitLoadStoreType(i->dType);
1909 emitCachingMode(i->cache);
1910 }
1911
1912 uint8_t
1913 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1914 {
1915 switch (SDATA(ref).sv.sv) {
1916 case SV_LANEID: return 0x00;
1917 case SV_PHYSID: return 0x03;
1918 case SV_VERTEX_COUNT: return 0x10;
1919 case SV_INVOCATION_ID: return 0x11;
1920 case SV_YDIR: return 0x12;
1921 case SV_THREAD_KILL: return 0x13;
1922 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1923 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1924 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1925 case SV_GRIDID: return 0x2c;
1926 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1927 case SV_LBASE: return 0x34;
1928 case SV_SBASE: return 0x30;
1929 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1930 default:
1931 assert(!"no sreg for system value");
1932 return 0;
1933 }
1934 }
1935
1936 void
1937 CodeEmitterNVC0::emitMOV(const Instruction *i)
1938 {
1939 if (i->def(0).getFile() == FILE_PREDICATE) {
1940 if (i->src(0).getFile() == FILE_GPR) {
1941 code[0] = 0xfc01c003;
1942 code[1] = 0x1a8e0000;
1943 srcId(i->src(0), 20);
1944 } else {
1945 code[0] = 0x0001c004;
1946 code[1] = 0x0c0e0000;
1947 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1948 code[0] |= 7 << 20;
1949 if (!i->getSrc(0)->reg.data.u32)
1950 code[0] |= 1 << 23;
1951 } else {
1952 srcId(i->src(0), 20);
1953 }
1954 }
1955 defId(i->def(0), 17);
1956 emitPredicate(i);
1957 } else
1958 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1959 uint8_t sr = getSRegEncoding(i->src(0));
1960
1961 if (i->encSize == 8) {
1962 code[0] = 0x00000004 | (sr << 26);
1963 code[1] = 0x2c000000;
1964 } else {
1965 code[0] = 0x40000008 | (sr << 20);
1966 }
1967 defId(i->def(0), 14);
1968
1969 emitPredicate(i);
1970 } else
1971 if (i->encSize == 8) {
1972 uint64_t opc;
1973
1974 if (i->src(0).getFile() == FILE_IMMEDIATE)
1975 opc = HEX64(18000000, 000001e2);
1976 else
1977 if (i->src(0).getFile() == FILE_PREDICATE)
1978 opc = HEX64(080e0000, 1c000004);
1979 else
1980 opc = HEX64(28000000, 00000004);
1981
1982 if (i->src(0).getFile() != FILE_PREDICATE)
1983 opc |= i->lanes << 5;
1984
1985 emitForm_B(i, opc);
1986
1987 // Explicitly emit the predicate source as emitForm_B skips it.
1988 if (i->src(0).getFile() == FILE_PREDICATE)
1989 srcId(i->src(0), 20);
1990 } else {
1991 uint32_t imm;
1992
1993 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1994 imm = SDATA(i->src(0)).u32;
1995 if (imm & 0xfff00000) {
1996 assert(!(imm & 0x000fffff));
1997 code[0] = 0x00000318 | imm;
1998 } else {
1999 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
2000 code[0] = 0x00000118 | (imm << 20);
2001 }
2002 } else {
2003 code[0] = 0x0028;
2004 emitShortSrc2(i->src(0));
2005 }
2006 defId(i->def(0), 14);
2007
2008 emitPredicate(i);
2009 }
2010 }
2011
2012 void
2013 CodeEmitterNVC0::emitATOM(const Instruction *i)
2014 {
2015 const bool hasDst = i->defExists(0);
2016 const bool casOrExch =
2017 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
2018 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
2019
2020 if (i->dType == TYPE_U64) {
2021 switch (i->subOp) {
2022 case NV50_IR_SUBOP_ATOM_ADD:
2023 code[0] = 0x205;
2024 if (hasDst)
2025 code[1] = 0x507e0000;
2026 else
2027 code[1] = 0x10000000;
2028 break;
2029 case NV50_IR_SUBOP_ATOM_EXCH:
2030 code[0] = 0x305;
2031 code[1] = 0x507e0000;
2032 break;
2033 case NV50_IR_SUBOP_ATOM_CAS:
2034 code[0] = 0x325;
2035 code[1] = 0x50000000;
2036 break;
2037 default:
2038 assert(!"invalid u64 red op");
2039 break;
2040 }
2041 } else
2042 if (i->dType == TYPE_U32) {
2043 switch (i->subOp) {
2044 case NV50_IR_SUBOP_ATOM_EXCH:
2045 code[0] = 0x105;
2046 code[1] = 0x507e0000;
2047 break;
2048 case NV50_IR_SUBOP_ATOM_CAS:
2049 code[0] = 0x125;
2050 code[1] = 0x50000000;
2051 break;
2052 default:
2053 code[0] = 0x5 | (i->subOp << 5);
2054 if (hasDst)
2055 code[1] = 0x507e0000;
2056 else
2057 code[1] = 0x10000000;
2058 break;
2059 }
2060 } else
2061 if (i->dType == TYPE_S32) {
2062 assert(i->subOp <= 2);
2063 code[0] = 0x205 | (i->subOp << 5);
2064 if (hasDst)
2065 code[1] = 0x587e0000;
2066 else
2067 code[1] = 0x18000000;
2068 } else
2069 if (i->dType == TYPE_F32) {
2070 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2071 code[0] = 0x205;
2072 if (hasDst)
2073 code[1] = 0x687e0000;
2074 else
2075 code[1] = 0x28000000;
2076 }
2077
2078 emitPredicate(i);
2079
2080 srcId(i->src(1), 14);
2081
2082 if (hasDst)
2083 defId(i->def(0), 32 + 11);
2084 else
2085 if (casOrExch)
2086 code[1] |= 63 << 11;
2087
2088 if (hasDst || casOrExch) {
2089 const int32_t offset = SDATA(i->src(0)).offset;
2090 assert(offset < 0x80000 && offset >= -0x80000);
2091 code[0] |= offset << 26;
2092 code[1] |= (offset & 0x1ffc0) >> 6;
2093 code[1] |= (offset & 0xe0000) << 6;
2094 } else {
2095 srcAddr32(i->src(0), 26, 0);
2096 }
2097 if (i->getIndirect(0, 0)) {
2098 srcId(i->getIndirect(0, 0), 20);
2099 if (i->getIndirect(0, 0)->reg.size == 8)
2100 code[1] |= 1 << 26;
2101 } else {
2102 code[0] |= 63 << 20;
2103 }
2104
2105 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2106 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2107 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2108 }
2109 }
2110
2111 void
2112 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2113 {
2114 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2115 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2116 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2117 default:
2118 code[0] = 0x45;
2119 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2120 break;
2121 }
2122 code[1] = 0xe0000000;
2123
2124 emitPredicate(i);
2125 }
2126
2127 void
2128 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2129 {
2130 code[0] = 0x00000005 | (i->subOp << 5);
2131
2132 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2133 code[1] = 0x98000000;
2134 srcAddr32(i->src(0), 28, 2);
2135 } else {
2136 code[1] = 0xd0000000;
2137 setAddress24(i->src(0));
2138 }
2139 if (uses64bitAddress(i))
2140 code[1] |= 1 << 26;
2141 srcId(i->src(0).getIndirect(0), 20);
2142
2143 emitPredicate(i);
2144
2145 defId(i, 0, 14);
2146 }
2147
2148 void
2149 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2150 {
2151 uint8_t m;
2152 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2153 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2154 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2155 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2156 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2157 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2158 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2159 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2160 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2161 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2162 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2163 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2164 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2165 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2166 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2167 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2168 default:
2169 return;
2170 }
2171 code[0] |= m << 5;
2172 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2173 code[1] |= 1 << 16;
2174 }
2175
2176 void
2177 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2178 {
2179 ImmediateValue *imm = NULL;
2180 uint64_t opc;
2181
2182 if (i->srcExists(2)) {
2183 imm = i->getSrc(2)->asImm();
2184 if (imm)
2185 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2186 }
2187
2188 switch (i->op) {
2189 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2190 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2191 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2192 default:
2193 assert(0);
2194 return;
2195 }
2196 emitForm_A(i, opc);
2197
2198 if (i->op == OP_SUCLAMP) {
2199 if (i->dType == TYPE_S32)
2200 code[0] |= 1 << 9;
2201 emitSUCLAMPMode(i->subOp);
2202 }
2203
2204 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2205 code[1] |= 1 << 16;
2206
2207 if (i->op != OP_SUEAU) {
2208 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2209 code[0] |= 63 << 14;
2210 code[1] |= i->getDef(0)->reg.data.id << 23;
2211 } else
2212 if (i->defExists(1)) { // r, p
2213 assert(i->def(1).getFile() == FILE_PREDICATE);
2214 code[1] |= i->getDef(1)->reg.data.id << 23;
2215 } else { // r, #
2216 code[1] |= 7 << 23;
2217 }
2218 }
2219 if (imm) {
2220 assert(i->op == OP_SUCLAMP);
2221 i->setSrc(2, imm);
2222 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2223 }
2224 }
2225
2226 void
2227 CodeEmitterNVC0::emitSUGType(DataType ty)
2228 {
2229 switch (ty) {
2230 case TYPE_S32: code[1] |= 1 << 13; break;
2231 case TYPE_U8: code[1] |= 2 << 13; break;
2232 case TYPE_S8: code[1] |= 3 << 13; break;
2233 default:
2234 assert(ty == TYPE_U32);
2235 break;
2236 }
2237 }
2238
2239 void
2240 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2241 {
2242 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2243
2244 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2245 assert(offset == (offset & 0xfffc));
2246
2247 code[1] |= 1 << 21;
2248 code[0] |= offset << 24;
2249 code[1] |= offset >> 8;
2250 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2251 }
2252
2253 void
2254 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2255 {
2256 if (!i->srcExists(s) || (i->predSrc == s)) {
2257 code[1] |= 0x7 << 17;
2258 } else {
2259 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2260 code[1] |= 1 << 20;
2261 srcId(i->src(s), 32 + 17);
2262 }
2263 }
2264
2265 void
2266 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2267 {
2268 code[0] = 0x5;
2269 code[1] = 0xd4000000 | (i->subOp << 15);
2270
2271 emitLoadStoreType(i->dType);
2272 emitSUGType(i->sType);
2273 emitCachingMode(i->cache);
2274
2275 emitPredicate(i);
2276 defId(i->def(0), 14); // destination
2277 srcId(i->src(0), 20); // address
2278 // format
2279 if (i->src(1).getFile() == FILE_GPR)
2280 srcId(i->src(1), 26);
2281 else
2282 setSUConst16(i, 1);
2283 setSUPred(i, 2);
2284 }
2285
2286 void
2287 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2288 {
2289 code[0] = 0x5;
2290 code[1] = 0xdc000000 | (i->subOp << 15);
2291
2292 if (i->op == OP_SUSTP)
2293 code[1] |= i->tex.mask << 22;
2294 else
2295 emitLoadStoreType(i->dType);
2296 emitSUGType(i->sType);
2297 emitCachingMode(i->cache);
2298
2299 emitPredicate(i);
2300 srcId(i->src(0), 20); // address
2301 // format
2302 if (i->src(1).getFile() == FILE_GPR)
2303 srcId(i->src(1), 26);
2304 else
2305 setSUConst16(i, 1);
2306 srcId(i->src(3), 14); // values
2307 setSUPred(i, 2);
2308 }
2309
2310 void
2311 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
2312 {
2313 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2314
2315 if (i->tex.rIndirectSrc < 0) {
2316 code[1] |= 0x00004000;
2317 code[0] |= i->tex.r << 26;
2318 } else {
2319 srcId(i, i->tex.rIndirectSrc, 26);
2320 }
2321 }
2322
2323 void
2324 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
2325 {
2326 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2327
2328 code[1] |= (i->tex.target.getDim() - 1) << 12;
2329 if (i->tex.target.isArray() || i->tex.target.isCube() ||
2330 i->tex.target.getDim() == 3) {
2331 // use e2d mode for 3-dim images, arrays and cubes.
2332 code[1] |= 3 << 12;
2333 }
2334
2335 srcId(i->src(0), 20);
2336 }
2337
2338 void
2339 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
2340 {
2341 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2342
2343 code[0] = 0x5;
2344 code[1] = 0xf0000000;
2345
2346 emitPredicate(i);
2347 emitLoadStoreType(i->sType);
2348
2349 defId(i->def(0), 14);
2350
2351 if (i->defExists(1)) {
2352 defId(i->def(1), 32 + 22);
2353 } else {
2354 code[1] |= 7 << 22;
2355 }
2356
2357 emitSUAddr(i);
2358 emitSUDim(i);
2359 }
2360
2361 void
2362 CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
2363 {
2364 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2365
2366 code[0] = 0x5;
2367 code[1] = 0xd4000000 | (i->subOp << 15);
2368
2369 emitPredicate(i);
2370 emitLoadStoreType(i->dType);
2371
2372 defId(i->def(0), 14);
2373
2374 emitCachingMode(i->cache);
2375 emitSUAddr(i);
2376 emitSUDim(i);
2377 }
2378
2379 void
2380 CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
2381 {
2382 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2383
2384 code[0] = 0x5;
2385 code[1] = 0xdc000000 | (i->subOp << 15);
2386
2387 if (i->op == OP_SUSTP)
2388 code[1] |= i->tex.mask << 17;
2389 else
2390 emitLoadStoreType(i->dType);
2391
2392 emitPredicate(i);
2393
2394 srcId(i->src(1), 14);
2395
2396 emitCachingMode(i->cache);
2397 emitSUAddr(i);
2398 emitSUDim(i);
2399 }
2400
2401 void
2402 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2403 {
2404 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2405 case 0:
2406 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2407 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2408 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2409 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2410 break;
2411 case 1:
2412 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2413 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2414 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2415 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2416 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2417 code[1] |= (i->mask & 0x3) << 2;
2418 break;
2419 case 2:
2420 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2421 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2422 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2423 code[1] |= (i->mask & 0x3) << 2;
2424 code[1] |= (i->mask & 0xc) << 21;
2425 break;
2426 default:
2427 assert(0);
2428 break;
2429 }
2430 }
2431
2432 void
2433 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2434 {
2435 uint64_t opc = 0x4;
2436
2437 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2438 case 0: opc |= 0xe8ULL << 56; break;
2439 case 1: opc |= 0xb4ULL << 56; break;
2440 case 2: opc |= 0x94ULL << 56; break;
2441 default:
2442 assert(0);
2443 break;
2444 }
2445 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2446 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2447 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2448 } else {
2449 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2450 if (isSignedType(i->sType)) opc |= 1 << 6;
2451 }
2452 emitForm_A(i, opc);
2453 emitVectorSubOp(i);
2454
2455 if (i->saturate)
2456 code[0] |= 1 << 9;
2457 if (i->flagsDef >= 0)
2458 code[1] |= 1 << 16;
2459 }
2460
2461 void
2462 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2463 {
2464 assert(i->encSize == 8);
2465 emitForm_A(i, HEX64(10000000, 00000006));
2466 code[0] |= i->subOp << 5;
2467 code[1] |= 0x00e00000;
2468 }
2469
2470 void
2471 CodeEmitterNVC0::emitVOTE(const Instruction *i)
2472 {
2473 assert(i->src(0).getFile() == FILE_PREDICATE);
2474
2475 code[0] = 0x00000004 | (i->subOp << 5);
2476 code[1] = 0x48000000;
2477
2478 emitPredicate(i);
2479
2480 unsigned rp = 0;
2481 for (int d = 0; i->defExists(d); d++) {
2482 if (i->def(d).getFile() == FILE_PREDICATE) {
2483 assert(!(rp & 2));
2484 rp |= 2;
2485 defId(i->def(d), 32 + 22);
2486 } else if (i->def(d).getFile() == FILE_GPR) {
2487 assert(!(rp & 1));
2488 rp |= 1;
2489 defId(i->def(d), 14);
2490 } else {
2491 assert(!"Unhandled def");
2492 }
2493 }
2494 if (!(rp & 1))
2495 code[0] |= 63 << 14;
2496 if (!(rp & 2))
2497 code[1] |= 7 << 22;
2498 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
2499 code[0] |= 1 << 23;
2500 srcId(i->src(0), 20);
2501 }
2502
2503 bool
2504 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2505 {
2506 unsigned int size = insn->encSize;
2507
2508 if (writeIssueDelays && !(codeSize & 0x3f))
2509 size += 8;
2510
2511 if (!insn->encSize) {
2512 ERROR("skipping unencodable instruction: "); insn->print();
2513 return false;
2514 } else
2515 if (codeSize + size > codeSizeLimit) {
2516 ERROR("code emitter output buffer too small\n");
2517 return false;
2518 }
2519
2520 if (writeIssueDelays) {
2521 if (!(codeSize & 0x3f)) {
2522 code[0] = 0x00000007; // cf issue delay "instruction"
2523 code[1] = 0x20000000;
2524 code += 2;
2525 codeSize += 8;
2526 }
2527 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2528 uint32_t *data = code - (id * 2 + 2);
2529 if (id <= 2) {
2530 data[0] |= insn->sched << (id * 8 + 4);
2531 } else
2532 if (id == 3) {
2533 data[0] |= insn->sched << 28;
2534 data[1] |= insn->sched >> 4;
2535 } else {
2536 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2537 }
2538 }
2539
2540 // assert that instructions with multiple defs don't corrupt registers
2541 for (int d = 0; insn->defExists(d); ++d)
2542 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2543
2544 switch (insn->op) {
2545 case OP_MOV:
2546 case OP_RDSV:
2547 emitMOV(insn);
2548 break;
2549 case OP_NOP:
2550 break;
2551 case OP_LOAD:
2552 emitLOAD(insn);
2553 break;
2554 case OP_STORE:
2555 emitSTORE(insn);
2556 break;
2557 case OP_LINTERP:
2558 case OP_PINTERP:
2559 emitINTERP(insn);
2560 break;
2561 case OP_VFETCH:
2562 emitVFETCH(insn);
2563 break;
2564 case OP_EXPORT:
2565 emitEXPORT(insn);
2566 break;
2567 case OP_PFETCH:
2568 emitPFETCH(insn);
2569 break;
2570 case OP_AFETCH:
2571 emitAFETCH(insn);
2572 break;
2573 case OP_EMIT:
2574 case OP_RESTART:
2575 emitOUT(insn);
2576 break;
2577 case OP_ADD:
2578 case OP_SUB:
2579 if (insn->dType == TYPE_F64)
2580 emitDADD(insn);
2581 else if (isFloatType(insn->dType))
2582 emitFADD(insn);
2583 else
2584 emitUADD(insn);
2585 break;
2586 case OP_MUL:
2587 if (insn->dType == TYPE_F64)
2588 emitDMUL(insn);
2589 else if (isFloatType(insn->dType))
2590 emitFMUL(insn);
2591 else
2592 emitUMUL(insn);
2593 break;
2594 case OP_MAD:
2595 case OP_FMA:
2596 if (insn->dType == TYPE_F64)
2597 emitDMAD(insn);
2598 else if (isFloatType(insn->dType))
2599 emitFMAD(insn);
2600 else
2601 emitIMAD(insn);
2602 break;
2603 case OP_SAD:
2604 emitISAD(insn);
2605 break;
2606 case OP_NOT:
2607 emitNOT(insn);
2608 break;
2609 case OP_AND:
2610 emitLogicOp(insn, 0);
2611 break;
2612 case OP_OR:
2613 emitLogicOp(insn, 1);
2614 break;
2615 case OP_XOR:
2616 emitLogicOp(insn, 2);
2617 break;
2618 case OP_SHL:
2619 case OP_SHR:
2620 emitShift(insn);
2621 break;
2622 case OP_SET:
2623 case OP_SET_AND:
2624 case OP_SET_OR:
2625 case OP_SET_XOR:
2626 emitSET(insn->asCmp());
2627 break;
2628 case OP_SELP:
2629 emitSELP(insn);
2630 break;
2631 case OP_SLCT:
2632 emitSLCT(insn->asCmp());
2633 break;
2634 case OP_MIN:
2635 case OP_MAX:
2636 emitMINMAX(insn);
2637 break;
2638 case OP_ABS:
2639 case OP_NEG:
2640 case OP_CEIL:
2641 case OP_FLOOR:
2642 case OP_TRUNC:
2643 case OP_SAT:
2644 emitCVT(insn);
2645 break;
2646 case OP_CVT:
2647 if (insn->def(0).getFile() == FILE_PREDICATE ||
2648 insn->src(0).getFile() == FILE_PREDICATE)
2649 emitMOV(insn);
2650 else
2651 emitCVT(insn);
2652 break;
2653 case OP_RSQ:
2654 emitSFnOp(insn, 5 + 2 * insn->subOp);
2655 break;
2656 case OP_RCP:
2657 emitSFnOp(insn, 4 + 2 * insn->subOp);
2658 break;
2659 case OP_LG2:
2660 emitSFnOp(insn, 3);
2661 break;
2662 case OP_EX2:
2663 emitSFnOp(insn, 2);
2664 break;
2665 case OP_SIN:
2666 emitSFnOp(insn, 1);
2667 break;
2668 case OP_COS:
2669 emitSFnOp(insn, 0);
2670 break;
2671 case OP_PRESIN:
2672 case OP_PREEX2:
2673 emitPreOp(insn);
2674 break;
2675 case OP_TEX:
2676 case OP_TXB:
2677 case OP_TXL:
2678 case OP_TXD:
2679 case OP_TXF:
2680 case OP_TXG:
2681 case OP_TXLQ:
2682 emitTEX(insn->asTex());
2683 break;
2684 case OP_TXQ:
2685 emitTXQ(insn->asTex());
2686 break;
2687 case OP_TEXBAR:
2688 emitTEXBAR(insn);
2689 break;
2690 case OP_SUBFM:
2691 case OP_SUCLAMP:
2692 case OP_SUEAU:
2693 emitSUCalc(insn);
2694 break;
2695 case OP_MADSP:
2696 emitMADSP(insn);
2697 break;
2698 case OP_SULDB:
2699 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2700 emitSULDGB(insn->asTex());
2701 else
2702 emitSULDB(insn->asTex());
2703 break;
2704 case OP_SUSTB:
2705 case OP_SUSTP:
2706 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2707 emitSUSTGx(insn->asTex());
2708 else
2709 emitSUSTx(insn->asTex());
2710 break;
2711 case OP_SULEA:
2712 emitSULEA(insn->asTex());
2713 break;
2714 case OP_ATOM:
2715 emitATOM(insn);
2716 break;
2717 case OP_BRA:
2718 case OP_CALL:
2719 case OP_PRERET:
2720 case OP_RET:
2721 case OP_DISCARD:
2722 case OP_EXIT:
2723 case OP_PRECONT:
2724 case OP_CONT:
2725 case OP_PREBREAK:
2726 case OP_BREAK:
2727 case OP_JOINAT:
2728 case OP_BRKPT:
2729 case OP_QUADON:
2730 case OP_QUADPOP:
2731 emitFlow(insn);
2732 break;
2733 case OP_QUADOP:
2734 emitQUADOP(insn, insn->subOp, insn->lanes);
2735 break;
2736 case OP_DFDX:
2737 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2738 break;
2739 case OP_DFDY:
2740 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2741 break;
2742 case OP_POPCNT:
2743 emitPOPC(insn);
2744 break;
2745 case OP_INSBF:
2746 emitINSBF(insn);
2747 break;
2748 case OP_EXTBF:
2749 emitEXTBF(insn);
2750 break;
2751 case OP_BFIND:
2752 emitBFIND(insn);
2753 break;
2754 case OP_PERMT:
2755 emitPERMT(insn);
2756 break;
2757 case OP_JOIN:
2758 emitNOP(insn);
2759 insn->join = 1;
2760 break;
2761 case OP_BAR:
2762 emitBAR(insn);
2763 break;
2764 case OP_MEMBAR:
2765 emitMEMBAR(insn);
2766 break;
2767 case OP_CCTL:
2768 emitCCTL(insn);
2769 break;
2770 case OP_VSHL:
2771 emitVSHL(insn);
2772 break;
2773 case OP_PIXLD:
2774 emitPIXLD(insn);
2775 break;
2776 case OP_VOTE:
2777 emitVOTE(insn);
2778 break;
2779 case OP_PHI:
2780 case OP_UNION:
2781 case OP_CONSTRAINT:
2782 ERROR("operation should have been eliminated");
2783 return false;
2784 case OP_EXP:
2785 case OP_LOG:
2786 case OP_SQRT:
2787 case OP_POW:
2788 ERROR("operation should have been lowered\n");
2789 return false;
2790 default:
2791 ERROR("unknown op: %u\n", insn->op);
2792 return false;
2793 }
2794
2795 if (insn->join) {
2796 code[0] |= 0x10;
2797 assert(insn->encSize == 8);
2798 }
2799
2800 code += insn->encSize / 4;
2801 codeSize += insn->encSize;
2802 return true;
2803 }
2804
2805 uint32_t
2806 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2807 {
2808 const Target::OpInfo &info = targ->getOpInfo(i);
2809
2810 if (writeIssueDelays || info.minEncSize == 8 || 1)
2811 return 8;
2812
2813 if (i->ftz || i->saturate || i->join)
2814 return 8;
2815 if (i->rnd != ROUND_N)
2816 return 8;
2817 if (i->predSrc >= 0 && i->op == OP_MAD)
2818 return 8;
2819
2820 if (i->op == OP_PINTERP) {
2821 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2822 return 8;
2823 } else
2824 if (i->op == OP_MOV && i->lanes != 0xf) {
2825 return 8;
2826 }
2827
2828 for (int s = 0; i->srcExists(s); ++s) {
2829 if (i->src(s).isIndirect(0))
2830 return 8;
2831
2832 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2833 if (SDATA(i->src(s)).offset >= 0x100)
2834 return 8;
2835 if (i->getSrc(s)->reg.fileIndex > 1 &&
2836 i->getSrc(s)->reg.fileIndex != 16)
2837 return 8;
2838 } else
2839 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2840 if (i->dType == TYPE_F32) {
2841 if (SDATA(i->src(s)).u32 >= 0x100)
2842 return 8;
2843 } else {
2844 if (SDATA(i->src(s)).u32 > 0xff)
2845 return 8;
2846 }
2847 }
2848
2849 if (i->op == OP_CVT)
2850 continue;
2851 if (i->src(s).mod != Modifier(0)) {
2852 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2853 if (i->op != OP_RSQ)
2854 return 8;
2855 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2856 if (i->op != OP_ADD || s != 0)
2857 return 8;
2858 }
2859 }
2860
2861 return 4;
2862 }
2863
2864 // Simplified, erring on safe side.
2865 class SchedDataCalculator : public Pass
2866 {
2867 public:
2868 SchedDataCalculator(const Target *targ) : targ(targ) { }
2869
2870 private:
2871 struct RegScores
2872 {
2873 struct Resource {
2874 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2875 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2876 int tex; // TEX to non-TEX delay 17 (0x11)
2877 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2878 int imul; // integer MUL to MUL delay 3
2879 } res;
2880 struct ScoreData {
2881 int r[256];
2882 int p[8];
2883 int c;
2884 } rd, wr;
2885 int base;
2886 int regs;
2887
2888 void rebase(const int base)
2889 {
2890 const int delta = this->base - base;
2891 if (!delta)
2892 return;
2893 this->base = 0;
2894
2895 for (int i = 0; i < regs; ++i) {
2896 rd.r[i] += delta;
2897 wr.r[i] += delta;
2898 }
2899 for (int i = 0; i < 8; ++i) {
2900 rd.p[i] += delta;
2901 wr.p[i] += delta;
2902 }
2903 rd.c += delta;
2904 wr.c += delta;
2905
2906 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2907 res.ld[f] += delta;
2908 res.st[f] += delta;
2909 }
2910 res.sfu += delta;
2911 res.imul += delta;
2912 res.tex += delta;
2913 }
2914 void wipe(int regs)
2915 {
2916 memset(&rd, 0, sizeof(rd));
2917 memset(&wr, 0, sizeof(wr));
2918 memset(&res, 0, sizeof(res));
2919 this->regs = regs;
2920 }
2921 int getLatest(const ScoreData& d) const
2922 {
2923 int max = 0;
2924 for (int i = 0; i < regs; ++i)
2925 if (d.r[i] > max)
2926 max = d.r[i];
2927 for (int i = 0; i < 8; ++i)
2928 if (d.p[i] > max)
2929 max = d.p[i];
2930 if (d.c > max)
2931 max = d.c;
2932 return max;
2933 }
2934 inline int getLatestRd() const
2935 {
2936 return getLatest(rd);
2937 }
2938 inline int getLatestWr() const
2939 {
2940 return getLatest(wr);
2941 }
2942 inline int getLatest() const
2943 {
2944 const int a = getLatestRd();
2945 const int b = getLatestWr();
2946
2947 int max = MAX2(a, b);
2948 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2949 max = MAX2(res.ld[f], max);
2950 max = MAX2(res.st[f], max);
2951 }
2952 max = MAX2(res.sfu, max);
2953 max = MAX2(res.imul, max);
2954 max = MAX2(res.tex, max);
2955 return max;
2956 }
2957 void setMax(const RegScores *that)
2958 {
2959 for (int i = 0; i < regs; ++i) {
2960 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2961 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2962 }
2963 for (int i = 0; i < 8; ++i) {
2964 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2965 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2966 }
2967 rd.c = MAX2(rd.c, that->rd.c);
2968 wr.c = MAX2(wr.c, that->wr.c);
2969
2970 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2971 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2972 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2973 }
2974 res.sfu = MAX2(res.sfu, that->res.sfu);
2975 res.imul = MAX2(res.imul, that->res.imul);
2976 res.tex = MAX2(res.tex, that->res.tex);
2977 }
2978 void print(int cycle)
2979 {
2980 for (int i = 0; i < regs; ++i) {
2981 if (rd.r[i] > cycle)
2982 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2983 if (wr.r[i] > cycle)
2984 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2985 }
2986 for (int i = 0; i < 8; ++i) {
2987 if (rd.p[i] > cycle)
2988 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2989 if (wr.p[i] > cycle)
2990 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2991 }
2992 if (rd.c > cycle)
2993 INFO("rd $c @ %i\n", rd.c);
2994 if (wr.c > cycle)
2995 INFO("wr $c @ %i\n", wr.c);
2996 if (res.sfu > cycle)
2997 INFO("sfu @ %i\n", res.sfu);
2998 if (res.imul > cycle)
2999 INFO("imul @ %i\n", res.imul);
3000 if (res.tex > cycle)
3001 INFO("tex @ %i\n", res.tex);
3002 }
3003 };
3004
3005 RegScores *score; // for current BB
3006 std::vector<RegScores> scoreBoards;
3007 int prevData;
3008 operation prevOp;
3009
3010 const Target *targ;
3011
3012 bool visit(Function *);
3013 bool visit(BasicBlock *);
3014
3015 void commitInsn(const Instruction *, int cycle);
3016 int calcDelay(const Instruction *, int cycle) const;
3017 void setDelay(Instruction *, int delay, Instruction *next);
3018
3019 void recordRd(const Value *, const int ready);
3020 void recordWr(const Value *, const int ready);
3021 void checkRd(const Value *, int cycle, int& delay) const;
3022 void checkWr(const Value *, int cycle, int& delay) const;
3023
3024 int getCycles(const Instruction *, int origDelay) const;
3025 };
3026
3027 void
3028 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
3029 {
3030 if (insn->op == OP_EXIT || insn->op == OP_RET)
3031 delay = MAX2(delay, 14);
3032
3033 if (insn->op == OP_TEXBAR) {
3034 // TODO: except if results not used before EXIT
3035 insn->sched = 0xc2;
3036 } else
3037 if (insn->op == OP_JOIN || insn->join) {
3038 insn->sched = 0x00;
3039 } else
3040 if (delay >= 0 || prevData == 0x04 ||
3041 !next || !targ->canDualIssue(insn, next)) {
3042 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
3043 if (prevOp == OP_EXPORT)
3044 insn->sched |= 0x40;
3045 else
3046 insn->sched |= 0x20;
3047 } else {
3048 insn->sched = 0x04; // dual-issue
3049 }
3050
3051 if (prevData != 0x04 || prevOp != OP_EXPORT)
3052 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
3053 prevOp = insn->op;
3054
3055 prevData = insn->sched;
3056 }
3057
3058 int
3059 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
3060 {
3061 if (insn->sched & 0x80) {
3062 int c = (insn->sched & 0x0f) * 2 + 1;
3063 if (insn->op == OP_TEXBAR && origDelay > 0)
3064 c += origDelay;
3065 return c;
3066 }
3067 if (insn->sched & 0x60)
3068 return (insn->sched & 0x1f) + 1;
3069 return (insn->sched == 0x04) ? 0 : 32;
3070 }
3071
3072 bool
3073 SchedDataCalculator::visit(Function *func)
3074 {
3075 int regs = targ->getFileSize(FILE_GPR) + 1;
3076 scoreBoards.resize(func->cfg.getSize());
3077 for (size_t i = 0; i < scoreBoards.size(); ++i)
3078 scoreBoards[i].wipe(regs);
3079 return true;
3080 }
3081
3082 bool
3083 SchedDataCalculator::visit(BasicBlock *bb)
3084 {
3085 Instruction *insn;
3086 Instruction *next = NULL;
3087
3088 int cycle = 0;
3089
3090 prevData = 0x00;
3091 prevOp = OP_NOP;
3092 score = &scoreBoards.at(bb->getId());
3093
3094 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
3095 // back branches will wait until all target dependencies are satisfied
3096 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
3097 continue;
3098 BasicBlock *in = BasicBlock::get(ei.getNode());
3099 if (in->getExit()) {
3100 if (prevData != 0x04)
3101 prevData = in->getExit()->sched;
3102 prevOp = in->getExit()->op;
3103 }
3104 score->setMax(&scoreBoards.at(in->getId()));
3105 }
3106 if (bb->cfg.incidentCount() > 1)
3107 prevOp = OP_NOP;
3108
3109 #ifdef NVC0_DEBUG_SCHED_DATA
3110 INFO("=== BB:%i initial scores\n", bb->getId());
3111 score->print(cycle);
3112 #endif
3113
3114 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
3115 next = insn->next;
3116
3117 commitInsn(insn, cycle);
3118 int delay = calcDelay(next, cycle);
3119 setDelay(insn, delay, next);
3120 cycle += getCycles(insn, delay);
3121
3122 #ifdef NVC0_DEBUG_SCHED_DATA
3123 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
3124 insn->print();
3125 next->print();
3126 #endif
3127 }
3128 if (!insn)
3129 return true;
3130 commitInsn(insn, cycle);
3131
3132 int bbDelay = -1;
3133
3134 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
3135 BasicBlock *out = BasicBlock::get(ei.getNode());
3136
3137 if (ei.getType() != Graph::Edge::BACK) {
3138 // only test the first instruction of the outgoing block
3139 next = out->getEntry();
3140 if (next)
3141 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
3142 } else {
3143 // wait until all dependencies are satisfied
3144 const int regsFree = score->getLatest();
3145 next = out->getFirst();
3146 for (int c = cycle; next && c < regsFree; next = next->next) {
3147 bbDelay = MAX2(bbDelay, calcDelay(next, c));
3148 c += getCycles(next, bbDelay);
3149 }
3150 next = NULL;
3151 }
3152 }
3153 if (bb->cfg.outgoingCount() != 1)
3154 next = NULL;
3155 setDelay(insn, bbDelay, next);
3156 cycle += getCycles(insn, bbDelay);
3157
3158 score->rebase(cycle); // common base for initializing out blocks' scores
3159 return true;
3160 }
3161
3162 #define NVE4_MAX_ISSUE_DELAY 0x1f
3163 int
3164 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
3165 {
3166 int delay = 0, ready = cycle;
3167
3168 for (int s = 0; insn->srcExists(s); ++s)
3169 checkRd(insn->getSrc(s), cycle, delay);
3170 // WAR & WAW don't seem to matter
3171 // for (int s = 0; insn->srcExists(s); ++s)
3172 // recordRd(insn->getSrc(s), cycle);
3173
3174 switch (Target::getOpClass(insn->op)) {
3175 case OPCLASS_SFU:
3176 ready = score->res.sfu;
3177 break;
3178 case OPCLASS_ARITH:
3179 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3180 ready = score->res.imul;
3181 break;
3182 case OPCLASS_TEXTURE:
3183 ready = score->res.tex;
3184 break;
3185 case OPCLASS_LOAD:
3186 ready = score->res.ld[insn->src(0).getFile()];
3187 break;
3188 case OPCLASS_STORE:
3189 ready = score->res.st[insn->src(0).getFile()];
3190 break;
3191 default:
3192 break;
3193 }
3194 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3195 ready = MAX2(ready, score->res.tex);
3196
3197 delay = MAX2(delay, ready - cycle);
3198
3199 // if can issue next cycle, delay is 0, not 1
3200 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3201 }
3202
3203 void
3204 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3205 {
3206 const int ready = cycle + targ->getLatency(insn);
3207
3208 for (int d = 0; insn->defExists(d); ++d)
3209 recordWr(insn->getDef(d), ready);
3210 // WAR & WAW don't seem to matter
3211 // for (int s = 0; insn->srcExists(s); ++s)
3212 // recordRd(insn->getSrc(s), cycle);
3213
3214 switch (Target::getOpClass(insn->op)) {
3215 case OPCLASS_SFU:
3216 score->res.sfu = cycle + 4;
3217 break;
3218 case OPCLASS_ARITH:
3219 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3220 score->res.imul = cycle + 4;
3221 break;
3222 case OPCLASS_TEXTURE:
3223 score->res.tex = cycle + 18;
3224 break;
3225 case OPCLASS_LOAD:
3226 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3227 break;
3228 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3229 score->res.st[insn->src(0).getFile()] = ready;
3230 break;
3231 case OPCLASS_STORE:
3232 score->res.st[insn->src(0).getFile()] = cycle + 4;
3233 score->res.ld[insn->src(0).getFile()] = ready;
3234 break;
3235 case OPCLASS_OTHER:
3236 if (insn->op == OP_TEXBAR)
3237 score->res.tex = cycle;
3238 break;
3239 default:
3240 break;
3241 }
3242
3243 #ifdef NVC0_DEBUG_SCHED_DATA
3244 score->print(cycle);
3245 #endif
3246 }
3247
3248 void
3249 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3250 {
3251 int ready = cycle;
3252 int a, b;
3253
3254 switch (v->reg.file) {
3255 case FILE_GPR:
3256 a = v->reg.data.id;
3257 b = a + v->reg.size / 4;
3258 for (int r = a; r < b; ++r)
3259 ready = MAX2(ready, score->rd.r[r]);
3260 break;
3261 case FILE_PREDICATE:
3262 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3263 break;
3264 case FILE_FLAGS:
3265 ready = MAX2(ready, score->rd.c);
3266 break;
3267 case FILE_SHADER_INPUT:
3268 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3269 case FILE_MEMORY_LOCAL:
3270 case FILE_MEMORY_CONST:
3271 case FILE_MEMORY_SHARED:
3272 case FILE_MEMORY_GLOBAL:
3273 case FILE_SYSTEM_VALUE:
3274 // TODO: any restrictions here ?
3275 break;
3276 case FILE_IMMEDIATE:
3277 break;
3278 default:
3279 assert(0);
3280 break;
3281 }
3282 if (cycle < ready)
3283 delay = MAX2(delay, ready - cycle);
3284 }
3285
3286 void
3287 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3288 {
3289 int ready = cycle;
3290 int a, b;
3291
3292 switch (v->reg.file) {
3293 case FILE_GPR:
3294 a = v->reg.data.id;
3295 b = a + v->reg.size / 4;
3296 for (int r = a; r < b; ++r)
3297 ready = MAX2(ready, score->wr.r[r]);
3298 break;
3299 case FILE_PREDICATE:
3300 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3301 break;
3302 default:
3303 assert(v->reg.file == FILE_FLAGS);
3304 ready = MAX2(ready, score->wr.c);
3305 break;
3306 }
3307 if (cycle < ready)
3308 delay = MAX2(delay, ready - cycle);
3309 }
3310
3311 void
3312 SchedDataCalculator::recordWr(const Value *v, const int ready)
3313 {
3314 int a = v->reg.data.id;
3315
3316 if (v->reg.file == FILE_GPR) {
3317 int b = a + v->reg.size / 4;
3318 for (int r = a; r < b; ++r)
3319 score->rd.r[r] = ready;
3320 } else
3321 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3322 if (v->reg.file == FILE_PREDICATE) {
3323 score->rd.p[a] = ready + 4;
3324 } else {
3325 assert(v->reg.file == FILE_FLAGS);
3326 score->rd.c = ready + 4;
3327 }
3328 }
3329
3330 void
3331 SchedDataCalculator::recordRd(const Value *v, const int ready)
3332 {
3333 int a = v->reg.data.id;
3334
3335 if (v->reg.file == FILE_GPR) {
3336 int b = a + v->reg.size / 4;
3337 for (int r = a; r < b; ++r)
3338 score->wr.r[r] = ready;
3339 } else
3340 if (v->reg.file == FILE_PREDICATE) {
3341 score->wr.p[a] = ready;
3342 } else
3343 if (v->reg.file == FILE_FLAGS) {
3344 score->wr.c = ready;
3345 }
3346 }
3347
3348 bool
3349 calculateSchedDataNVC0(const Target *targ, Function *func)
3350 {
3351 SchedDataCalculator sched(targ);
3352 return sched.run(func, true, true);
3353 }
3354
3355 void
3356 CodeEmitterNVC0::prepareEmission(Function *func)
3357 {
3358 CodeEmitter::prepareEmission(func);
3359
3360 if (targ->hasSWSched)
3361 calculateSchedDataNVC0(targ, func);
3362 }
3363
3364 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3365 : CodeEmitter(target),
3366 targNVC0(target),
3367 writeIssueDelays(target->hasSWSched)
3368 {
3369 code = NULL;
3370 codeSize = codeSizeLimit = 0;
3371 relocInfo = NULL;
3372 }
3373
3374 CodeEmitter *
3375 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3376 {
3377 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3378 emit->setProgramType(type);
3379 return emit;
3380 }
3381
3382 CodeEmitter *
3383 TargetNVC0::getCodeEmitter(Program::Type type)
3384 {
3385 if (chipset >= NVISA_GK20A_CHIPSET)
3386 return createCodeEmitterGK110(type);
3387 return createCodeEmitterNVC0(type);
3388 }
3389
3390 } // namespace nv50_ir