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radeon: enable Hyper-Z on r600g and radeonsi by default
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitPFETCH(const Instruction *);
89 void emitVFETCH(const Instruction *);
90 void emitEXPORT(const Instruction *);
91 void emitOUT(const Instruction *);
92
93 void emitUADD(const Instruction *);
94 void emitFADD(const Instruction *);
95 void emitUMUL(const Instruction *);
96 void emitFMUL(const Instruction *);
97 void emitIMAD(const Instruction *);
98 void emitISAD(const Instruction *);
99 void emitFMAD(const Instruction *);
100 void emitMADSP(const Instruction *);
101
102 void emitNOT(Instruction *);
103 void emitLogicOp(const Instruction *, uint8_t subOp);
104 void emitPOPC(const Instruction *);
105 void emitINSBF(const Instruction *);
106 void emitEXTBF(const Instruction *);
107 void emitBFIND(const Instruction *);
108 void emitPERMT(const Instruction *);
109 void emitShift(const Instruction *);
110
111 void emitSFnOp(const Instruction *, uint8_t subOp);
112
113 void emitCVT(Instruction *);
114 void emitMINMAX(const Instruction *);
115 void emitPreOp(const Instruction *);
116
117 void emitSET(const CmpInstruction *);
118 void emitSLCT(const CmpInstruction *);
119 void emitSELP(const Instruction *);
120
121 void emitTEXBAR(const Instruction *);
122 void emitTEX(const TexInstruction *);
123 void emitTEXCSAA(const TexInstruction *);
124 void emitTXQ(const TexInstruction *);
125
126 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
127
128 void emitFlow(const Instruction *);
129 void emitBAR(const Instruction *);
130
131 void emitSUCLAMPMode(uint16_t);
132 void emitSUCalc(Instruction *);
133 void emitSULDGB(const TexInstruction *);
134 void emitSUSTGx(const TexInstruction *);
135
136 void emitVSHL(const Instruction *);
137 void emitVectorSubOp(const Instruction *);
138
139 void emitPIXLD(const Instruction *);
140
141 inline void defId(const ValueDef&, const int pos);
142 inline void defId(const Instruction *, int d, const int pos);
143 inline void srcId(const ValueRef&, const int pos);
144 inline void srcId(const ValueRef *, const int pos);
145 inline void srcId(const Instruction *, int s, const int pos);
146 inline void srcAddr32(const ValueRef&, int pos, int shr);
147
148 inline bool isLIMM(const ValueRef&, DataType ty);
149 };
150
151 // for better visibility
152 #define HEX64(h, l) 0x##h##l##ULL
153
154 #define SDATA(a) ((a).rep()->reg.data)
155 #define DDATA(a) ((a).rep()->reg.data)
156
157 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
158 {
159 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
160 }
161
162 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
163 {
164 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
165 }
166
167 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
168 {
169 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
170 code[pos / 32] |= r << (pos % 32);
171 }
172
173 void
174 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
175 {
176 const uint32_t offset = SDATA(src).offset >> shr;
177
178 code[pos / 32] |= offset << (pos % 32);
179 if (pos && (pos < 32))
180 code[1] |= offset >> (32 - pos);
181 }
182
183 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
184 {
185 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
186 }
187
188 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
189 {
190 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
191 code[pos / 32] |= r << (pos % 32);
192 }
193
194 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
195 {
196 const ImmediateValue *imm = ref.get()->asImm();
197
198 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
199 }
200
201 void
202 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
203 {
204 switch (insn->rnd) {
205 case ROUND_M: code[1] |= 1 << 23; break;
206 case ROUND_P: code[1] |= 2 << 23; break;
207 case ROUND_Z: code[1] |= 3 << 23; break;
208 default:
209 assert(insn->rnd == ROUND_N);
210 break;
211 }
212 }
213
214 void
215 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
216 {
217 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
218 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
219 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
220 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
221 }
222
223 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
224 {
225 uint8_t val;
226
227 switch (cc) {
228 case CC_LT: val = 0x1; break;
229 case CC_LTU: val = 0x9; break;
230 case CC_EQ: val = 0x2; break;
231 case CC_EQU: val = 0xa; break;
232 case CC_LE: val = 0x3; break;
233 case CC_LEU: val = 0xb; break;
234 case CC_GT: val = 0x4; break;
235 case CC_GTU: val = 0xc; break;
236 case CC_NE: val = 0x5; break;
237 case CC_NEU: val = 0xd; break;
238 case CC_GE: val = 0x6; break;
239 case CC_GEU: val = 0xe; break;
240 case CC_TR: val = 0xf; break;
241 case CC_FL: val = 0x0; break;
242
243 case CC_A: val = 0x14; break;
244 case CC_NA: val = 0x13; break;
245 case CC_S: val = 0x15; break;
246 case CC_NS: val = 0x12; break;
247 case CC_C: val = 0x16; break;
248 case CC_NC: val = 0x11; break;
249 case CC_O: val = 0x17; break;
250 case CC_NO: val = 0x10; break;
251
252 default:
253 val = 0;
254 assert(!"invalid condition code");
255 break;
256 }
257 code[pos / 32] |= val << (pos % 32);
258 }
259
260 void
261 CodeEmitterNVC0::emitPredicate(const Instruction *i)
262 {
263 if (i->predSrc >= 0) {
264 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
265 srcId(i->src(i->predSrc), 10);
266 if (i->cc == CC_NOT_P)
267 code[0] |= 0x2000; // negate
268 } else {
269 code[0] |= 0x1c00;
270 }
271 }
272
273 void
274 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
275 {
276 switch (src.getFile()) {
277 case FILE_MEMORY_GLOBAL:
278 srcAddr32(src, 26, 0);
279 break;
280 case FILE_MEMORY_LOCAL:
281 case FILE_MEMORY_SHARED:
282 setAddress24(src);
283 break;
284 default:
285 assert(src.getFile() == FILE_MEMORY_CONST);
286 setAddress16(src);
287 break;
288 }
289 }
290
291 void
292 CodeEmitterNVC0::setAddress16(const ValueRef& src)
293 {
294 Symbol *sym = src.get()->asSym();
295
296 assert(sym);
297
298 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
299 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
300 }
301
302 void
303 CodeEmitterNVC0::setAddress24(const ValueRef& src)
304 {
305 Symbol *sym = src.get()->asSym();
306
307 assert(sym);
308
309 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
310 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
311 }
312
313 void
314 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
315 {
316 const ImmediateValue *imm = i->src(s).get()->asImm();
317 uint32_t u32;
318
319 assert(imm);
320 u32 = imm->reg.data.u32;
321
322 if ((code[0] & 0xf) == 0x2) {
323 // LIMM
324 code[0] |= (u32 & 0x3f) << 26;
325 code[1] |= u32 >> 6;
326 } else
327 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
328 // integer immediate
329 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
330 assert(!(code[1] & 0xc000));
331 u32 &= 0xfffff;
332 code[0] |= (u32 & 0x3f) << 26;
333 code[1] |= 0xc000 | (u32 >> 6);
334 } else {
335 // float immediate
336 assert(!(u32 & 0x00000fff));
337 assert(!(code[1] & 0xc000));
338 code[0] |= ((u32 >> 12) & 0x3f) << 26;
339 code[1] |= 0xc000 | (u32 >> 18);
340 }
341 }
342
343 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
344 {
345 const ImmediateValue *imm = ref.get()->asImm();
346
347 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
348
349 assert(s8 == imm->reg.data.s32);
350
351 code[0] |= (s8 & 0x3f) << 26;
352 code[0] |= (s8 >> 6) << 8;
353 }
354
355 void
356 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
357 {
358 code[0] = opc;
359 code[1] = opc >> 32;
360
361 emitPredicate(i);
362
363 defId(i->def(0), 14);
364
365 int s1 = 26;
366 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
367 s1 = 49;
368
369 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
370 switch (i->getSrc(s)->reg.file) {
371 case FILE_MEMORY_CONST:
372 assert(!(code[1] & 0xc000));
373 code[1] |= (s == 2) ? 0x8000 : 0x4000;
374 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
375 setAddress16(i->src(s));
376 break;
377 case FILE_IMMEDIATE:
378 assert(s == 1 ||
379 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
380 assert(!(code[1] & 0xc000));
381 setImmediate(i, s);
382 break;
383 case FILE_GPR:
384 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
385 break;
386 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
387 break;
388 default:
389 // ignore here, can be predicate or flags, but must not be address
390 break;
391 }
392 }
393 }
394
395 void
396 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
397 {
398 code[0] = opc;
399 code[1] = opc >> 32;
400
401 emitPredicate(i);
402
403 defId(i->def(0), 14);
404
405 switch (i->src(0).getFile()) {
406 case FILE_MEMORY_CONST:
407 assert(!(code[1] & 0xc000));
408 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
409 setAddress16(i->src(0));
410 break;
411 case FILE_IMMEDIATE:
412 assert(!(code[1] & 0xc000));
413 setImmediate(i, 0);
414 break;
415 case FILE_GPR:
416 srcId(i->src(0), 26);
417 break;
418 default:
419 // ignore here, can be predicate or flags, but must not be address
420 break;
421 }
422 }
423
424 void
425 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
426 {
427 code[0] = opc;
428
429 int ss2a = 0;
430 if (opc == 0x0d || opc == 0x0e)
431 ss2a = 2;
432
433 defId(i->def(0), 14);
434 srcId(i->src(0), 20);
435
436 assert(pred || (i->predSrc < 0));
437 if (pred)
438 emitPredicate(i);
439
440 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
441 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
442 assert(!(code[0] & (0x300 >> ss2a)));
443 switch (i->src(s).get()->reg.fileIndex) {
444 case 0: code[0] |= 0x100 >> ss2a; break;
445 case 1: code[0] |= 0x200 >> ss2a; break;
446 case 16: code[0] |= 0x300 >> ss2a; break;
447 default:
448 ERROR("invalid c[] space for short form\n");
449 break;
450 }
451 if (s == 1)
452 code[0] |= i->getSrc(s)->reg.data.offset << 24;
453 else
454 code[0] |= i->getSrc(s)->reg.data.offset << 6;
455 } else
456 if (i->src(s).getFile() == FILE_IMMEDIATE) {
457 assert(s == 1);
458 setImmediateS8(i->src(s));
459 } else
460 if (i->src(s).getFile() == FILE_GPR) {
461 srcId(i->src(s), (s == 1) ? 26 : 8);
462 }
463 }
464 }
465
466 void
467 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
468 {
469 if (src.getFile() == FILE_MEMORY_CONST) {
470 switch (src.get()->reg.fileIndex) {
471 case 0: code[0] |= 0x100; break;
472 case 1: code[0] |= 0x200; break;
473 case 16: code[0] |= 0x300; break;
474 default:
475 assert(!"unsupported file index for short op");
476 break;
477 }
478 srcAddr32(src, 20, 2);
479 } else {
480 srcId(src, 20);
481 assert(src.getFile() == FILE_GPR);
482 }
483 }
484
485 void
486 CodeEmitterNVC0::emitNOP(const Instruction *i)
487 {
488 code[0] = 0x000001e4;
489 code[1] = 0x40000000;
490 emitPredicate(i);
491 }
492
493 void
494 CodeEmitterNVC0::emitFMAD(const Instruction *i)
495 {
496 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
497
498 if (i->encSize == 8) {
499 if (isLIMM(i->src(1), TYPE_F32)) {
500 emitForm_A(i, HEX64(20000000, 00000002));
501 } else {
502 emitForm_A(i, HEX64(30000000, 00000000));
503
504 if (i->src(2).mod.neg())
505 code[0] |= 1 << 8;
506 }
507 roundMode_A(i);
508
509 if (neg1)
510 code[0] |= 1 << 9;
511
512 if (i->saturate)
513 code[0] |= 1 << 5;
514 if (i->ftz)
515 code[0] |= 1 << 6;
516 } else {
517 assert(!i->saturate && !i->src(2).mod.neg());
518 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
519 false);
520 if (neg1)
521 code[0] |= 1 << 4;
522 }
523 }
524
525 void
526 CodeEmitterNVC0::emitFMUL(const Instruction *i)
527 {
528 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
529
530 assert(i->postFactor >= -3 && i->postFactor <= 3);
531
532 if (i->encSize == 8) {
533 if (isLIMM(i->src(1), TYPE_F32)) {
534 assert(i->postFactor == 0); // constant folded, hopefully
535 emitForm_A(i, HEX64(30000000, 00000002));
536 } else {
537 emitForm_A(i, HEX64(58000000, 00000000));
538 roundMode_A(i);
539 code[1] |= ((i->postFactor > 0) ?
540 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
541 }
542 if (neg)
543 code[1] ^= 1 << 25; // aliases with LIMM sign bit
544
545 if (i->saturate)
546 code[0] |= 1 << 5;
547
548 if (i->dnz)
549 code[0] |= 1 << 7;
550 else
551 if (i->ftz)
552 code[0] |= 1 << 6;
553 } else {
554 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
555 emitForm_S(i, 0xa8, true);
556 }
557 }
558
559 void
560 CodeEmitterNVC0::emitUMUL(const Instruction *i)
561 {
562 if (i->encSize == 8) {
563 if (i->src(1).getFile() == FILE_IMMEDIATE) {
564 emitForm_A(i, HEX64(10000000, 00000002));
565 } else {
566 emitForm_A(i, HEX64(50000000, 00000003));
567 }
568 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
569 code[0] |= 1 << 6;
570 if (i->sType == TYPE_S32)
571 code[0] |= 1 << 5;
572 if (i->dType == TYPE_S32)
573 code[0] |= 1 << 7;
574 } else {
575 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
576
577 if (i->sType == TYPE_S32)
578 code[0] |= 1 << 6;
579 }
580 }
581
582 void
583 CodeEmitterNVC0::emitFADD(const Instruction *i)
584 {
585 if (i->encSize == 8) {
586 if (isLIMM(i->src(1), TYPE_F32)) {
587 assert(!i->saturate);
588 emitForm_A(i, HEX64(28000000, 00000002));
589
590 code[0] |= i->src(0).mod.abs() << 7;
591 code[0] |= i->src(0).mod.neg() << 9;
592
593 if (i->src(1).mod.abs())
594 code[1] &= 0xfdffffff;
595 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
596 code[1] ^= 0x02000000;
597 } else {
598 emitForm_A(i, HEX64(50000000, 00000000));
599
600 roundMode_A(i);
601 if (i->saturate)
602 code[1] |= 1 << 17;
603
604 emitNegAbs12(i);
605 if (i->op == OP_SUB) code[0] ^= 1 << 8;
606 }
607 if (i->ftz)
608 code[0] |= 1 << 5;
609 } else {
610 assert(!i->saturate && i->op != OP_SUB &&
611 !i->src(0).mod.abs() &&
612 !i->src(1).mod.neg() && !i->src(1).mod.abs());
613
614 emitForm_S(i, 0x49, true);
615
616 if (i->src(0).mod.neg())
617 code[0] |= 1 << 7;
618 }
619 }
620
621 void
622 CodeEmitterNVC0::emitUADD(const Instruction *i)
623 {
624 uint32_t addOp = 0;
625
626 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
627 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
628
629 if (i->src(0).mod.neg())
630 addOp |= 0x200;
631 if (i->src(1).mod.neg())
632 addOp |= 0x100;
633 if (i->op == OP_SUB) {
634 addOp ^= 0x100;
635 assert(addOp != 0x300); // would be add-plus-one
636 }
637
638 if (i->encSize == 8) {
639 if (isLIMM(i->src(1), TYPE_U32)) {
640 emitForm_A(i, HEX64(08000000, 00000002));
641 if (i->defExists(1))
642 code[1] |= 1 << 26; // write carry
643 } else {
644 emitForm_A(i, HEX64(48000000, 00000003));
645 if (i->defExists(1))
646 code[1] |= 1 << 16; // write carry
647 }
648 code[0] |= addOp;
649
650 if (i->saturate)
651 code[0] |= 1 << 5;
652 if (i->flagsSrc >= 0) // add carry
653 code[0] |= 1 << 6;
654 } else {
655 assert(!(addOp & 0x100));
656 emitForm_S(i, (addOp >> 3) |
657 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
658 }
659 }
660
661 // TODO: shl-add
662 void
663 CodeEmitterNVC0::emitIMAD(const Instruction *i)
664 {
665 assert(i->encSize == 8);
666 emitForm_A(i, HEX64(20000000, 00000003));
667
668 if (isSignedType(i->dType))
669 code[0] |= 1 << 7;
670 if (isSignedType(i->sType))
671 code[0] |= 1 << 5;
672
673 code[1] |= i->saturate << 24;
674
675 if (i->flagsDef >= 0) code[1] |= 1 << 16;
676 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
677
678 if (i->src(2).mod.neg()) code[0] |= 0x10;
679 if (i->src(1).mod.neg() ^
680 i->src(0).mod.neg()) code[0] |= 0x20;
681
682 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
683 code[0] |= 1 << 6;
684 }
685
686 void
687 CodeEmitterNVC0::emitMADSP(const Instruction *i)
688 {
689 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
690
691 emitForm_A(i, HEX64(00000000, 00000003));
692
693 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
694 code[1] |= 0x01800000;
695 } else {
696 code[0] |= (i->subOp & 0x00f) << 7;
697 code[0] |= (i->subOp & 0x0f0) << 1;
698 code[0] |= (i->subOp & 0x100) >> 3;
699 code[0] |= (i->subOp & 0x200) >> 2;
700 code[1] |= (i->subOp & 0xc00) << 13;
701 }
702
703 if (i->flagsDef >= 0)
704 code[1] |= 1 << 16;
705 }
706
707 void
708 CodeEmitterNVC0::emitISAD(const Instruction *i)
709 {
710 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
711 assert(i->encSize == 8);
712
713 emitForm_A(i, HEX64(38000000, 00000003));
714
715 if (i->dType == TYPE_S32)
716 code[0] |= 1 << 5;
717 }
718
719 void
720 CodeEmitterNVC0::emitNOT(Instruction *i)
721 {
722 assert(i->encSize == 8);
723 i->setSrc(1, i->src(0));
724 emitForm_A(i, HEX64(68000000, 000001c3));
725 }
726
727 void
728 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
729 {
730 if (i->def(0).getFile() == FILE_PREDICATE) {
731 code[0] = 0x00000004 | (subOp << 30);
732 code[1] = 0x0c000000;
733
734 emitPredicate(i);
735
736 defId(i->def(0), 17);
737 srcId(i->src(0), 20);
738 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
739 srcId(i->src(1), 26);
740 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
741
742 if (i->defExists(1)) {
743 defId(i->def(1), 14);
744 } else {
745 code[0] |= 7 << 14;
746 }
747 // (a OP b) OP c
748 if (i->predSrc != 2 && i->srcExists(2)) {
749 code[1] |= subOp << 21;
750 srcId(i->src(2), 17);
751 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
752 } else {
753 code[1] |= 0x000e0000;
754 }
755 } else
756 if (i->encSize == 8) {
757 if (isLIMM(i->src(1), TYPE_U32)) {
758 emitForm_A(i, HEX64(38000000, 00000002));
759
760 if (i->flagsDef >= 0)
761 code[1] |= 1 << 26;
762 } else {
763 emitForm_A(i, HEX64(68000000, 00000003));
764
765 if (i->flagsDef >= 0)
766 code[1] |= 1 << 16;
767 }
768 code[0] |= subOp << 6;
769
770 if (i->flagsSrc >= 0) // carry
771 code[0] |= 1 << 5;
772
773 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
774 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
775 } else {
776 emitForm_S(i, (subOp << 5) |
777 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
778 }
779 }
780
781 void
782 CodeEmitterNVC0::emitPOPC(const Instruction *i)
783 {
784 emitForm_A(i, HEX64(54000000, 00000004));
785
786 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
787 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
788 }
789
790 void
791 CodeEmitterNVC0::emitINSBF(const Instruction *i)
792 {
793 emitForm_A(i, HEX64(28000000, 00000003));
794 }
795
796 void
797 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
798 {
799 emitForm_A(i, HEX64(70000000, 00000003));
800
801 if (i->dType == TYPE_S32)
802 code[0] |= 1 << 5;
803 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
804 code[0] |= 1 << 8;
805 }
806
807 void
808 CodeEmitterNVC0::emitBFIND(const Instruction *i)
809 {
810 emitForm_B(i, HEX64(78000000, 00000003));
811
812 if (i->dType == TYPE_S32)
813 code[0] |= 1 << 5;
814 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
815 code[0] |= 1 << 8;
816 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
817 code[0] |= 1 << 6;
818 }
819
820 void
821 CodeEmitterNVC0::emitPERMT(const Instruction *i)
822 {
823 emitForm_A(i, HEX64(24000000, 00000004));
824
825 code[0] |= i->subOp << 5;
826 }
827
828 void
829 CodeEmitterNVC0::emitShift(const Instruction *i)
830 {
831 if (i->op == OP_SHR) {
832 emitForm_A(i, HEX64(58000000, 00000003)
833 | (isSignedType(i->dType) ? 0x20 : 0x00));
834 } else {
835 emitForm_A(i, HEX64(60000000, 00000003));
836 }
837
838 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
839 code[0] |= 1 << 9;
840 }
841
842 void
843 CodeEmitterNVC0::emitPreOp(const Instruction *i)
844 {
845 if (i->encSize == 8) {
846 emitForm_B(i, HEX64(60000000, 00000000));
847
848 if (i->op == OP_PREEX2)
849 code[0] |= 0x20;
850
851 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
852 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
853 } else {
854 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
855 }
856 }
857
858 void
859 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
860 {
861 if (i->encSize == 8) {
862 code[0] = 0x00000000 | (subOp << 26);
863 code[1] = 0xc8000000;
864
865 emitPredicate(i);
866
867 defId(i->def(0), 14);
868 srcId(i->src(0), 20);
869
870 assert(i->src(0).getFile() == FILE_GPR);
871
872 if (i->saturate) code[0] |= 1 << 5;
873
874 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
875 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
876 } else {
877 emitForm_S(i, 0x80000008 | (subOp << 26), true);
878
879 assert(!i->src(0).mod.neg());
880 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
881 }
882 }
883
884 void
885 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
886 {
887 uint64_t op;
888
889 assert(i->encSize == 8);
890
891 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
892
893 if (i->ftz)
894 op |= 1 << 5;
895 else
896 if (!isFloatType(i->dType))
897 op |= isSignedType(i->dType) ? 0x23 : 0x03;
898
899 emitForm_A(i, op);
900 emitNegAbs12(i);
901 }
902
903 void
904 CodeEmitterNVC0::roundMode_C(const Instruction *i)
905 {
906 switch (i->rnd) {
907 case ROUND_M: code[1] |= 1 << 17; break;
908 case ROUND_P: code[1] |= 2 << 17; break;
909 case ROUND_Z: code[1] |= 3 << 17; break;
910 case ROUND_NI: code[0] |= 1 << 7; break;
911 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
912 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
913 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
914 case ROUND_N: break;
915 default:
916 assert(!"invalid round mode");
917 break;
918 }
919 }
920
921 void
922 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
923 {
924 switch (i->rnd) {
925 case ROUND_M:
926 case ROUND_MI: code[0] |= 1 << 16; break;
927 case ROUND_P:
928 case ROUND_PI: code[0] |= 2 << 16; break;
929 case ROUND_Z:
930 case ROUND_ZI: code[0] |= 3 << 16; break;
931 default:
932 break;
933 }
934 }
935
936 void
937 CodeEmitterNVC0::emitCVT(Instruction *i)
938 {
939 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
940 DataType dType;
941
942 switch (i->op) {
943 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
944 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
945 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
946 default:
947 break;
948 }
949
950 const bool sat = (i->op == OP_SAT) || i->saturate;
951 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
952 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
953
954 if (i->op == OP_NEG && i->dType == TYPE_U32)
955 dType = TYPE_S32;
956 else
957 dType = i->dType;
958
959 if (i->encSize == 8) {
960 emitForm_B(i, HEX64(10000000, 00000004));
961
962 roundMode_C(i);
963
964 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
965 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
966 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
967
968 if (sat)
969 code[0] |= 0x20;
970 if (abs)
971 code[0] |= 1 << 6;
972 if (neg && i->op != OP_ABS)
973 code[0] |= 1 << 8;
974
975 if (i->ftz)
976 code[1] |= 1 << 23;
977
978 if (isSignedIntType(dType))
979 code[0] |= 0x080;
980 if (isSignedIntType(i->sType))
981 code[0] |= 0x200;
982
983 if (isFloatType(dType)) {
984 if (!isFloatType(i->sType))
985 code[1] |= 0x08000000;
986 } else {
987 if (isFloatType(i->sType))
988 code[1] |= 0x04000000;
989 else
990 code[1] |= 0x0c000000;
991 }
992 } else {
993 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
994 code[0] = 0x298;
995 } else
996 if (isFloatType(dType)) {
997 if (isFloatType(i->sType))
998 code[0] = 0x098;
999 else
1000 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1001 } else {
1002 assert(isFloatType(i->sType));
1003
1004 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1005 }
1006
1007 if (neg) code[0] |= 1 << 16;
1008 if (sat) code[0] |= 1 << 18;
1009 if (abs) code[0] |= 1 << 19;
1010
1011 roundMode_CS(i);
1012 }
1013 }
1014
1015 void
1016 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1017 {
1018 uint32_t hi;
1019 uint32_t lo = 0;
1020
1021 if (i->sType == TYPE_F64)
1022 lo = 0x1;
1023 else
1024 if (!isFloatType(i->sType))
1025 lo = 0x3;
1026
1027 if (isFloatType(i->dType) || isSignedIntType(i->sType))
1028 lo |= 0x20;
1029
1030 switch (i->op) {
1031 case OP_SET_AND: hi = 0x10000000; break;
1032 case OP_SET_OR: hi = 0x10200000; break;
1033 case OP_SET_XOR: hi = 0x10400000; break;
1034 default:
1035 hi = 0x100e0000;
1036 break;
1037 }
1038 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1039
1040 if (i->op != OP_SET)
1041 srcId(i->src(2), 32 + 17);
1042
1043 if (i->def(0).getFile() == FILE_PREDICATE) {
1044 if (i->sType == TYPE_F32)
1045 code[1] += 0x10000000;
1046 else
1047 code[1] += 0x08000000;
1048
1049 code[0] &= ~0xfc000;
1050 defId(i->def(0), 17);
1051 if (i->defExists(1))
1052 defId(i->def(1), 14);
1053 else
1054 code[0] |= 0x1c000;
1055 }
1056
1057 if (i->ftz)
1058 code[1] |= 1 << 27;
1059
1060 emitCondCode(i->setCond, 32 + 23);
1061 emitNegAbs12(i);
1062 }
1063
1064 void
1065 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1066 {
1067 uint64_t op;
1068
1069 switch (i->dType) {
1070 case TYPE_S32:
1071 op = HEX64(30000000, 00000023);
1072 break;
1073 case TYPE_U32:
1074 op = HEX64(30000000, 00000003);
1075 break;
1076 case TYPE_F32:
1077 op = HEX64(38000000, 00000000);
1078 break;
1079 default:
1080 assert(!"invalid type for SLCT");
1081 op = 0;
1082 break;
1083 }
1084 emitForm_A(i, op);
1085
1086 CondCode cc = i->setCond;
1087
1088 if (i->src(2).mod.neg())
1089 cc = reverseCondCode(cc);
1090
1091 emitCondCode(cc, 32 + 23);
1092
1093 if (i->ftz)
1094 code[0] |= 1 << 5;
1095 }
1096
1097 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1098 {
1099 emitForm_A(i, HEX64(20000000, 00000004));
1100
1101 if (i->cc == CC_NOT_P || i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1102 code[1] |= 1 << 20;
1103 }
1104
1105 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1106 {
1107 code[0] = 0x00000006 | (i->subOp << 26);
1108 code[1] = 0xf0000000;
1109 emitPredicate(i);
1110 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1111 }
1112
1113 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1114 {
1115 code[0] = 0x00000086;
1116 code[1] = 0xd0000000;
1117
1118 code[1] |= i->tex.r;
1119 code[1] |= i->tex.s << 8;
1120
1121 if (i->tex.liveOnly)
1122 code[0] |= 1 << 9;
1123
1124 defId(i->def(0), 14);
1125 srcId(i->src(0), 20);
1126 }
1127
1128 static inline bool
1129 isNextIndependentTex(const TexInstruction *i)
1130 {
1131 if (!i->next || !isTextureOp(i->next->op))
1132 return false;
1133 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1134 return false;
1135 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1136 }
1137
1138 void
1139 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1140 {
1141 code[0] = 0x00000006;
1142
1143 if (isNextIndependentTex(i))
1144 code[0] |= 0x080; // t mode
1145 else
1146 code[0] |= 0x100; // p mode
1147
1148 if (i->tex.liveOnly)
1149 code[0] |= 1 << 9;
1150
1151 switch (i->op) {
1152 case OP_TEX: code[1] = 0x80000000; break;
1153 case OP_TXB: code[1] = 0x84000000; break;
1154 case OP_TXL: code[1] = 0x86000000; break;
1155 case OP_TXF: code[1] = 0x90000000; break;
1156 case OP_TXG: code[1] = 0xa0000000; break;
1157 case OP_TXLQ: code[1] = 0xb0000000; break;
1158 case OP_TXD: code[1] = 0xe0000000; break;
1159 default:
1160 assert(!"invalid texture op");
1161 break;
1162 }
1163 if (i->op == OP_TXF) {
1164 if (!i->tex.levelZero)
1165 code[1] |= 0x02000000;
1166 } else
1167 if (i->tex.levelZero) {
1168 code[1] |= 0x02000000;
1169 }
1170
1171 if (i->op != OP_TXD && i->tex.derivAll)
1172 code[1] |= 1 << 13;
1173
1174 defId(i->def(0), 14);
1175 srcId(i->src(0), 20);
1176
1177 emitPredicate(i);
1178
1179 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1180
1181 code[1] |= i->tex.mask << 14;
1182
1183 code[1] |= i->tex.r;
1184 code[1] |= i->tex.s << 8;
1185 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1186 code[1] |= 1 << 18; // in 1st source (with array index)
1187
1188 // texture target:
1189 code[1] |= (i->tex.target.getDim() - 1) << 20;
1190 if (i->tex.target.isCube())
1191 code[1] += 2 << 20;
1192 if (i->tex.target.isArray())
1193 code[1] |= 1 << 19;
1194 if (i->tex.target.isShadow())
1195 code[1] |= 1 << 24;
1196
1197 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1198
1199 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1200 // lzero
1201 if (i->op == OP_TXL)
1202 code[1] &= ~(1 << 26);
1203 else
1204 if (i->op == OP_TXF)
1205 code[1] &= ~(1 << 25);
1206 }
1207 if (i->tex.target == TEX_TARGET_2D_MS ||
1208 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1209 code[1] |= 1 << 23;
1210
1211 if (i->tex.useOffsets == 1)
1212 code[1] |= 1 << 22;
1213 if (i->tex.useOffsets == 4)
1214 code[1] |= 1 << 23;
1215
1216 srcId(i, src1, 26);
1217 }
1218
1219 void
1220 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1221 {
1222 code[0] = 0x00000086;
1223 code[1] = 0xc0000000;
1224
1225 switch (i->tex.query) {
1226 case TXQ_DIMS: code[1] |= 0 << 22; break;
1227 case TXQ_TYPE: code[1] |= 1 << 22; break;
1228 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1229 case TXQ_FILTER: code[1] |= 3 << 22; break;
1230 case TXQ_LOD: code[1] |= 4 << 22; break;
1231 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1232 default:
1233 assert(!"invalid texture query");
1234 break;
1235 }
1236
1237 code[1] |= i->tex.mask << 14;
1238
1239 code[1] |= i->tex.r;
1240 code[1] |= i->tex.s << 8;
1241 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1242 code[1] |= 1 << 18;
1243
1244 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1245
1246 defId(i->def(0), 14);
1247 srcId(i->src(0), 20);
1248 srcId(i, src1, 26);
1249
1250 emitPredicate(i);
1251 }
1252
1253 void
1254 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1255 {
1256 code[0] = 0x00000000 | (laneMask << 6);
1257 code[1] = 0x48000000 | qOp;
1258
1259 defId(i->def(0), 14);
1260 srcId(i->src(0), 20);
1261 srcId(i->srcExists(1) ? i->src(1) : i->src(0), 26);
1262
1263 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1264 code[0] |= 1 << 9; // dall
1265
1266 emitPredicate(i);
1267 }
1268
1269 void
1270 CodeEmitterNVC0::emitFlow(const Instruction *i)
1271 {
1272 const FlowInstruction *f = i->asFlow();
1273
1274 unsigned mask; // bit 0: predicate, bit 1: target
1275
1276 code[0] = 0x00000007;
1277
1278 switch (i->op) {
1279 case OP_BRA:
1280 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1281 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1282 code[0] |= 0x4000;
1283 mask = 3;
1284 break;
1285 case OP_CALL:
1286 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1287 if (f->indirect)
1288 code[0] |= 0x4000; // indirect calls always use c[] source
1289 mask = 2;
1290 break;
1291
1292 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1293 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1294 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1295 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1296 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1297
1298 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1299 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1300 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1301 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1302
1303 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1304 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1305 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1306 default:
1307 assert(!"invalid flow operation");
1308 return;
1309 }
1310
1311 if (mask & 1) {
1312 emitPredicate(i);
1313 if (i->flagsSrc < 0)
1314 code[0] |= 0x1e0;
1315 }
1316
1317 if (!f)
1318 return;
1319
1320 if (f->allWarp)
1321 code[0] |= 1 << 15;
1322 if (f->limit)
1323 code[0] |= 1 << 16;
1324
1325 if (f->indirect) {
1326 if (code[0] & 0x4000) {
1327 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1328 setAddress16(i->src(0));
1329 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1330 if (f->op == OP_BRA)
1331 srcId(f->src(0).getIndirect(0), 20);
1332 } else {
1333 srcId(f, 0, 20);
1334 }
1335 }
1336
1337 if (f->op == OP_CALL) {
1338 if (f->indirect) {
1339 // nothing
1340 } else
1341 if (f->builtin) {
1342 assert(f->absolute);
1343 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1344 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1345 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1346 } else {
1347 assert(!f->absolute);
1348 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1349 code[0] |= (pcRel & 0x3f) << 26;
1350 code[1] |= (pcRel >> 6) & 0x3ffff;
1351 }
1352 } else
1353 if (mask & 2) {
1354 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1355 // currently we don't want absolute branches
1356 assert(!f->absolute);
1357 code[0] |= (pcRel & 0x3f) << 26;
1358 code[1] |= (pcRel >> 6) & 0x3ffff;
1359 }
1360 }
1361
1362 void
1363 CodeEmitterNVC0::emitBAR(const Instruction *i)
1364 {
1365 Value *rDef = NULL, *pDef = NULL;
1366
1367 switch (i->subOp) {
1368 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1369 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1370 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1371 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1372 default:
1373 code[0] = 0x04;
1374 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1375 break;
1376 }
1377 code[1] = 0x50000000;
1378
1379 code[0] |= 63 << 14;
1380 code[1] |= 7 << 21;
1381
1382 emitPredicate(i);
1383
1384 // barrier id
1385 if (i->src(0).getFile() == FILE_GPR) {
1386 srcId(i->src(0), 20);
1387 } else {
1388 ImmediateValue *imm = i->getSrc(0)->asImm();
1389 assert(imm);
1390 code[0] |= imm->reg.data.u32 << 20;
1391 }
1392
1393 // thread count
1394 if (i->src(1).getFile() == FILE_GPR) {
1395 srcId(i->src(1), 26);
1396 } else {
1397 ImmediateValue *imm = i->getSrc(1)->asImm();
1398 assert(imm);
1399 code[0] |= imm->reg.data.u32 << 26;
1400 code[1] |= imm->reg.data.u32 >> 6;
1401 }
1402
1403 if (i->srcExists(2) && (i->predSrc != 2)) {
1404 srcId(i->src(2), 32 + 17);
1405 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1406 code[1] |= 1 << 20;
1407 } else {
1408 code[1] |= 7 << 17;
1409 }
1410
1411 if (i->defExists(0)) {
1412 if (i->def(0).getFile() == FILE_GPR)
1413 rDef = i->getDef(0);
1414 else
1415 pDef = i->getDef(0);
1416
1417 if (i->defExists(1)) {
1418 if (i->def(1).getFile() == FILE_GPR)
1419 rDef = i->getDef(1);
1420 else
1421 pDef = i->getDef(1);
1422 }
1423 }
1424 if (rDef) {
1425 code[0] &= ~(63 << 14);
1426 defId(rDef, 14);
1427 }
1428 if (pDef) {
1429 code[1] &= ~(7 << 21);
1430 defId(pDef, 32 + 21);
1431 }
1432 }
1433
1434 void
1435 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1436 {
1437 uint32_t prim = i->src(0).get()->reg.data.u32;
1438
1439 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1440 code[1] = 0x00000000 | (prim >> 6);
1441
1442 emitPredicate(i);
1443
1444 defId(i->def(0), 14);
1445 srcId(i->src(1), 20);
1446 }
1447
1448 void
1449 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1450 {
1451 code[0] = 0x00000006;
1452 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1453
1454 if (i->perPatch)
1455 code[0] |= 0x100;
1456 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1457 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1458
1459 emitPredicate(i);
1460
1461 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1462
1463 defId(i->def(0), 14);
1464 srcId(i->src(0).getIndirect(0), 20);
1465 srcId(i->src(0).getIndirect(1), 26); // vertex address
1466 }
1467
1468 void
1469 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1470 {
1471 unsigned int size = typeSizeof(i->dType);
1472
1473 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1474 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1475
1476 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1477
1478 if (i->perPatch)
1479 code[0] |= 0x100;
1480
1481 emitPredicate(i);
1482
1483 assert(i->src(1).getFile() == FILE_GPR);
1484
1485 srcId(i->src(0).getIndirect(0), 20);
1486 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1487 srcId(i->src(1), 26);
1488 }
1489
1490 void
1491 CodeEmitterNVC0::emitOUT(const Instruction *i)
1492 {
1493 code[0] = 0x00000006;
1494 code[1] = 0x1c000000;
1495
1496 emitPredicate(i);
1497
1498 defId(i->def(0), 14); // new secret address
1499 srcId(i->src(0), 20); // old secret address, should be 0 initially
1500
1501 assert(i->src(0).getFile() == FILE_GPR);
1502
1503 if (i->op == OP_EMIT)
1504 code[0] |= 1 << 5;
1505 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1506 code[0] |= 1 << 6;
1507
1508 // vertex stream
1509 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1510 unsigned int stream = SDATA(i->src(1)).u32;
1511 assert(stream < 4);
1512 if (stream) {
1513 code[1] |= 0xc000;
1514 code[0] |= stream << 26;
1515 } else {
1516 srcId(NULL, 26);
1517 }
1518 } else {
1519 srcId(i->src(1), 26);
1520 }
1521 }
1522
1523 void
1524 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1525 {
1526 if (i->encSize == 8) {
1527 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1528 } else {
1529 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1530 code[0] |= 0x80;
1531 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1532 }
1533 }
1534
1535 void
1536 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1537 {
1538 const uint32_t base = i->getSrc(0)->reg.data.offset;
1539
1540 if (i->encSize == 8) {
1541 code[0] = 0x00000000;
1542 code[1] = 0xc0000000 | (base & 0xffff);
1543
1544 if (i->saturate)
1545 code[0] |= 1 << 5;
1546
1547 if (i->op == OP_PINTERP)
1548 srcId(i->src(1), 26);
1549 else
1550 code[0] |= 0x3f << 26;
1551
1552 srcId(i->src(0).getIndirect(0), 20);
1553 } else {
1554 assert(i->op == OP_PINTERP);
1555 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1556 srcId(i->src(1), 20);
1557 }
1558 emitInterpMode(i);
1559
1560 emitPredicate(i);
1561 defId(i->def(0), 14);
1562
1563 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1564 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1565 else
1566 code[1] |= 0x3f << 17;
1567 }
1568
1569 void
1570 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1571 {
1572 uint8_t val;
1573
1574 switch (ty) {
1575 case TYPE_U8:
1576 val = 0x00;
1577 break;
1578 case TYPE_S8:
1579 val = 0x20;
1580 break;
1581 case TYPE_F16:
1582 case TYPE_U16:
1583 val = 0x40;
1584 break;
1585 case TYPE_S16:
1586 val = 0x60;
1587 break;
1588 case TYPE_F32:
1589 case TYPE_U32:
1590 case TYPE_S32:
1591 val = 0x80;
1592 break;
1593 case TYPE_F64:
1594 case TYPE_U64:
1595 case TYPE_S64:
1596 val = 0xa0;
1597 break;
1598 case TYPE_B128:
1599 val = 0xc0;
1600 break;
1601 default:
1602 val = 0x80;
1603 assert(!"invalid type");
1604 break;
1605 }
1606 code[0] |= val;
1607 }
1608
1609 void
1610 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1611 {
1612 uint32_t val;
1613
1614 switch (c) {
1615 case CACHE_CA:
1616 // case CACHE_WB:
1617 val = 0x000;
1618 break;
1619 case CACHE_CG:
1620 val = 0x100;
1621 break;
1622 case CACHE_CS:
1623 val = 0x200;
1624 break;
1625 case CACHE_CV:
1626 // case CACHE_WT:
1627 val = 0x300;
1628 break;
1629 default:
1630 val = 0;
1631 assert(!"invalid caching mode");
1632 break;
1633 }
1634 code[0] |= val;
1635 }
1636
1637 static inline bool
1638 uses64bitAddress(const Instruction *ldst)
1639 {
1640 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1641 ldst->src(0).isIndirect(0) &&
1642 ldst->getIndirect(0, 0)->reg.size == 8;
1643 }
1644
1645 void
1646 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1647 {
1648 uint32_t opc;
1649
1650 switch (i->src(0).getFile()) {
1651 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1652 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1653 case FILE_MEMORY_SHARED: opc = 0xc9000000; break;
1654 default:
1655 assert(!"invalid memory file");
1656 opc = 0;
1657 break;
1658 }
1659 code[0] = 0x00000005;
1660 code[1] = opc;
1661
1662 setAddressByFile(i->src(0));
1663 srcId(i->src(1), 14);
1664 srcId(i->src(0).getIndirect(0), 20);
1665 if (uses64bitAddress(i))
1666 code[1] |= 1 << 26;
1667
1668 emitPredicate(i);
1669
1670 emitLoadStoreType(i->dType);
1671 emitCachingMode(i->cache);
1672 }
1673
1674 void
1675 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1676 {
1677 uint32_t opc;
1678
1679 code[0] = 0x00000005;
1680
1681 switch (i->src(0).getFile()) {
1682 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1683 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1684 case FILE_MEMORY_SHARED: opc = 0xc1000000; break;
1685 case FILE_MEMORY_CONST:
1686 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1687 emitMOV(i); // not sure if this is any better
1688 return;
1689 }
1690 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1691 code[0] = 0x00000006 | (i->subOp << 8);
1692 break;
1693 default:
1694 assert(!"invalid memory file");
1695 opc = 0;
1696 break;
1697 }
1698 code[1] = opc;
1699
1700 defId(i->def(0), 14);
1701
1702 setAddressByFile(i->src(0));
1703 srcId(i->src(0).getIndirect(0), 20);
1704 if (uses64bitAddress(i))
1705 code[1] |= 1 << 26;
1706
1707 emitPredicate(i);
1708
1709 emitLoadStoreType(i->dType);
1710 emitCachingMode(i->cache);
1711 }
1712
1713 uint8_t
1714 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1715 {
1716 switch (SDATA(ref).sv.sv) {
1717 case SV_LANEID: return 0x00;
1718 case SV_PHYSID: return 0x03;
1719 case SV_VERTEX_COUNT: return 0x10;
1720 case SV_INVOCATION_ID: return 0x11;
1721 case SV_YDIR: return 0x12;
1722 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1723 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1724 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1725 case SV_GRIDID: return 0x2c;
1726 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1727 case SV_LBASE: return 0x34;
1728 case SV_SBASE: return 0x30;
1729 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1730 default:
1731 assert(!"no sreg for system value");
1732 return 0;
1733 }
1734 }
1735
1736 void
1737 CodeEmitterNVC0::emitMOV(const Instruction *i)
1738 {
1739 if (i->def(0).getFile() == FILE_PREDICATE) {
1740 if (i->src(0).getFile() == FILE_GPR) {
1741 code[0] = 0xfc01c003;
1742 code[1] = 0x1a8e0000;
1743 srcId(i->src(0), 20);
1744 } else {
1745 code[0] = 0x0001c004;
1746 code[1] = 0x0c0e0000;
1747 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1748 code[0] |= 7 << 20;
1749 if (!i->getSrc(0)->reg.data.u32)
1750 code[0] |= 1 << 23;
1751 } else {
1752 srcId(i->src(0), 20);
1753 }
1754 }
1755 defId(i->def(0), 17);
1756 emitPredicate(i);
1757 } else
1758 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1759 uint8_t sr = getSRegEncoding(i->src(0));
1760
1761 if (i->encSize == 8) {
1762 code[0] = 0x00000004 | (sr << 26);
1763 code[1] = 0x2c000000;
1764 } else {
1765 code[0] = 0x40000008 | (sr << 20);
1766 }
1767 defId(i->def(0), 14);
1768
1769 emitPredicate(i);
1770 } else
1771 if (i->encSize == 8) {
1772 uint64_t opc;
1773
1774 if (i->src(0).getFile() == FILE_IMMEDIATE)
1775 opc = HEX64(18000000, 000001e2);
1776 else
1777 if (i->src(0).getFile() == FILE_PREDICATE)
1778 opc = HEX64(080e0000, 1c000004);
1779 else
1780 opc = HEX64(28000000, 00000004);
1781
1782 opc |= i->lanes << 5;
1783
1784 emitForm_B(i, opc);
1785 } else {
1786 uint32_t imm;
1787
1788 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1789 imm = SDATA(i->src(0)).u32;
1790 if (imm & 0xfff00000) {
1791 assert(!(imm & 0x000fffff));
1792 code[0] = 0x00000318 | imm;
1793 } else {
1794 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1795 code[0] = 0x00000118 | (imm << 20);
1796 }
1797 } else {
1798 code[0] = 0x0028;
1799 emitShortSrc2(i->src(0));
1800 }
1801 defId(i->def(0), 14);
1802
1803 emitPredicate(i);
1804 }
1805 }
1806
1807 void
1808 CodeEmitterNVC0::emitATOM(const Instruction *i)
1809 {
1810 const bool hasDst = i->defExists(0);
1811 const bool casOrExch =
1812 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1813 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1814
1815 if (i->dType == TYPE_U64) {
1816 switch (i->subOp) {
1817 case NV50_IR_SUBOP_ATOM_ADD:
1818 code[0] = 0x205;
1819 if (hasDst)
1820 code[1] = 0x507e0000;
1821 else
1822 code[1] = 0x10000000;
1823 break;
1824 case NV50_IR_SUBOP_ATOM_EXCH:
1825 code[0] = 0x305;
1826 code[1] = 0x507e0000;
1827 break;
1828 case NV50_IR_SUBOP_ATOM_CAS:
1829 code[0] = 0x325;
1830 code[1] = 0x50000000;
1831 break;
1832 default:
1833 assert(!"invalid u64 red op");
1834 break;
1835 }
1836 } else
1837 if (i->dType == TYPE_U32) {
1838 switch (i->subOp) {
1839 case NV50_IR_SUBOP_ATOM_EXCH:
1840 code[0] = 0x105;
1841 code[1] = 0x507e0000;
1842 break;
1843 case NV50_IR_SUBOP_ATOM_CAS:
1844 code[0] = 0x125;
1845 code[1] = 0x50000000;
1846 break;
1847 default:
1848 code[0] = 0x5 | (i->subOp << 5);
1849 if (hasDst)
1850 code[1] = 0x507e0000;
1851 else
1852 code[1] = 0x10000000;
1853 break;
1854 }
1855 } else
1856 if (i->dType == TYPE_S32) {
1857 assert(i->subOp <= 2);
1858 code[0] = 0x205 | (i->subOp << 5);
1859 if (hasDst)
1860 code[1] = 0x587e0000;
1861 else
1862 code[1] = 0x18000000;
1863 } else
1864 if (i->dType == TYPE_F32) {
1865 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
1866 code[0] = 0x205;
1867 if (hasDst)
1868 code[1] = 0x687e0000;
1869 else
1870 code[1] = 0x28000000;
1871 }
1872
1873 emitPredicate(i);
1874
1875 srcId(i->src(1), 14);
1876
1877 if (hasDst)
1878 defId(i->def(0), 32 + 11);
1879 else
1880 if (casOrExch)
1881 code[1] |= 63 << 11;
1882
1883 if (hasDst || casOrExch) {
1884 const int32_t offset = SDATA(i->src(0)).offset;
1885 assert(offset < 0x80000 && offset >= -0x80000);
1886 code[0] |= offset << 26;
1887 code[1] |= (offset & 0x1ffc0) >> 6;
1888 code[1] |= (offset & 0xe0000) << 6;
1889 } else {
1890 srcAddr32(i->src(0), 26, 0);
1891 }
1892 if (i->getIndirect(0, 0)) {
1893 srcId(i->getIndirect(0, 0), 20);
1894 if (i->getIndirect(0, 0)->reg.size == 8)
1895 code[1] |= 1 << 26;
1896 } else {
1897 code[0] |= 63 << 20;
1898 }
1899
1900 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS)
1901 srcId(i->src(2), 32 + 17);
1902 }
1903
1904 void
1905 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
1906 {
1907 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
1908 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
1909 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
1910 default:
1911 code[0] = 0x45;
1912 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
1913 break;
1914 }
1915 code[1] = 0xe0000000;
1916
1917 emitPredicate(i);
1918 }
1919
1920 void
1921 CodeEmitterNVC0::emitCCTL(const Instruction *i)
1922 {
1923 code[0] = 0x00000005 | (i->subOp << 5);
1924
1925 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
1926 code[1] = 0x98000000;
1927 srcAddr32(i->src(0), 28, 2);
1928 } else {
1929 code[1] = 0xd0000000;
1930 setAddress24(i->src(0));
1931 }
1932 if (uses64bitAddress(i))
1933 code[1] |= 1 << 26;
1934 srcId(i->src(0).getIndirect(0), 20);
1935
1936 emitPredicate(i);
1937
1938 defId(i, 0, 14);
1939 }
1940
1941 void
1942 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
1943 {
1944 uint8_t m;
1945 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
1946 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
1947 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
1948 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
1949 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
1950 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
1951 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
1952 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
1953 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
1954 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
1955 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
1956 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
1957 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
1958 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
1959 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
1960 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
1961 default:
1962 return;
1963 }
1964 code[0] |= m << 5;
1965 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
1966 code[1] |= 1 << 16;
1967 }
1968
1969 void
1970 CodeEmitterNVC0::emitSUCalc(Instruction *i)
1971 {
1972 ImmediateValue *imm = NULL;
1973 uint64_t opc;
1974
1975 if (i->srcExists(2)) {
1976 imm = i->getSrc(2)->asImm();
1977 if (imm)
1978 i->setSrc(2, NULL); // special case, make emitForm_A not assert
1979 }
1980
1981 switch (i->op) {
1982 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
1983 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
1984 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
1985 default:
1986 assert(0);
1987 return;
1988 }
1989 emitForm_A(i, opc);
1990
1991 if (i->op == OP_SUCLAMP) {
1992 if (i->dType == TYPE_S32)
1993 code[0] |= 1 << 9;
1994 emitSUCLAMPMode(i->subOp);
1995 }
1996
1997 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
1998 code[1] |= 1 << 16;
1999
2000 if (i->op != OP_SUEAU) {
2001 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2002 code[0] |= 63 << 14;
2003 code[1] |= i->getDef(0)->reg.data.id << 23;
2004 } else
2005 if (i->defExists(1)) { // r, p
2006 assert(i->def(1).getFile() == FILE_PREDICATE);
2007 code[1] |= i->getDef(1)->reg.data.id << 23;
2008 } else { // r, #
2009 code[1] |= 7 << 23;
2010 }
2011 }
2012 if (imm) {
2013 assert(i->op == OP_SUCLAMP);
2014 i->setSrc(2, imm);
2015 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2016 }
2017 }
2018
2019 void
2020 CodeEmitterNVC0::emitSUGType(DataType ty)
2021 {
2022 switch (ty) {
2023 case TYPE_S32: code[1] |= 1 << 13; break;
2024 case TYPE_U8: code[1] |= 2 << 13; break;
2025 case TYPE_S8: code[1] |= 3 << 13; break;
2026 default:
2027 assert(ty == TYPE_U32);
2028 break;
2029 }
2030 }
2031
2032 void
2033 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2034 {
2035 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2036
2037 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2038 assert(offset == (offset & 0xfffc));
2039
2040 code[1] |= 1 << 21;
2041 code[0] |= offset << 24;
2042 code[1] |= offset >> 8;
2043 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2044 }
2045
2046 void
2047 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2048 {
2049 if (!i->srcExists(s) || (i->predSrc == s)) {
2050 code[1] |= 0x7 << 17;
2051 } else {
2052 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2053 code[1] |= 1 << 20;
2054 srcId(i->src(s), 32 + 17);
2055 }
2056 }
2057
2058 void
2059 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2060 {
2061 code[0] = 0x5;
2062 code[1] = 0xd4000000 | (i->subOp << 15);
2063
2064 emitLoadStoreType(i->dType);
2065 emitSUGType(i->sType);
2066 emitCachingMode(i->cache);
2067
2068 emitPredicate(i);
2069 defId(i->def(0), 14); // destination
2070 srcId(i->src(0), 20); // address
2071 // format
2072 if (i->src(1).getFile() == FILE_GPR)
2073 srcId(i->src(1), 26);
2074 else
2075 setSUConst16(i, 1);
2076 setSUPred(i, 2);
2077 }
2078
2079 void
2080 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2081 {
2082 code[0] = 0x5;
2083 code[1] = 0xdc000000 | (i->subOp << 15);
2084
2085 if (i->op == OP_SUSTP)
2086 code[1] |= i->tex.mask << 22;
2087 else
2088 emitLoadStoreType(i->dType);
2089 emitSUGType(i->sType);
2090 emitCachingMode(i->cache);
2091
2092 emitPredicate(i);
2093 srcId(i->src(0), 20); // address
2094 // format
2095 if (i->src(1).getFile() == FILE_GPR)
2096 srcId(i->src(1), 26);
2097 else
2098 setSUConst16(i, 1);
2099 srcId(i->src(3), 14); // values
2100 setSUPred(i, 2);
2101 }
2102
2103 void
2104 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2105 {
2106 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2107 case 0:
2108 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2109 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2110 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2111 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2112 break;
2113 case 1:
2114 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2115 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2116 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2117 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2118 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2119 code[1] |= (i->mask & 0x3) << 2;
2120 break;
2121 case 2:
2122 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2123 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2124 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2125 code[1] |= (i->mask & 0x3) << 2;
2126 code[1] |= (i->mask & 0xc) << 21;
2127 break;
2128 default:
2129 assert(0);
2130 break;
2131 }
2132 }
2133
2134 void
2135 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2136 {
2137 uint64_t opc = 0x4;
2138
2139 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2140 case 0: opc |= 0xe8ULL << 56; break;
2141 case 1: opc |= 0xb4ULL << 56; break;
2142 case 2: opc |= 0x94ULL << 56; break;
2143 default:
2144 assert(0);
2145 break;
2146 }
2147 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2148 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2149 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2150 } else {
2151 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2152 if (isSignedType(i->sType)) opc |= 1 << 6;
2153 }
2154 emitForm_A(i, opc);
2155 emitVectorSubOp(i);
2156
2157 if (i->saturate)
2158 code[0] |= 1 << 9;
2159 if (i->flagsDef >= 0)
2160 code[1] |= 1 << 16;
2161 }
2162
2163 void
2164 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2165 {
2166 assert(i->encSize == 8);
2167 emitForm_A(i, HEX64(10000000, 00000006));
2168 code[0] |= i->subOp << 5;
2169 code[1] |= 0x00e00000;
2170 }
2171
2172 bool
2173 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2174 {
2175 unsigned int size = insn->encSize;
2176
2177 if (writeIssueDelays && !(codeSize & 0x3f))
2178 size += 8;
2179
2180 if (!insn->encSize) {
2181 ERROR("skipping unencodable instruction: "); insn->print();
2182 return false;
2183 } else
2184 if (codeSize + size > codeSizeLimit) {
2185 ERROR("code emitter output buffer too small\n");
2186 return false;
2187 }
2188
2189 if (writeIssueDelays) {
2190 if (!(codeSize & 0x3f)) {
2191 code[0] = 0x00000007; // cf issue delay "instruction"
2192 code[1] = 0x20000000;
2193 code += 2;
2194 codeSize += 8;
2195 }
2196 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2197 uint32_t *data = code - (id * 2 + 2);
2198 if (id <= 2) {
2199 data[0] |= insn->sched << (id * 8 + 4);
2200 } else
2201 if (id == 3) {
2202 data[0] |= insn->sched << 28;
2203 data[1] |= insn->sched >> 4;
2204 } else {
2205 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2206 }
2207 }
2208
2209 // assert that instructions with multiple defs don't corrupt registers
2210 for (int d = 0; insn->defExists(d); ++d)
2211 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2212
2213 switch (insn->op) {
2214 case OP_MOV:
2215 case OP_RDSV:
2216 emitMOV(insn);
2217 break;
2218 case OP_NOP:
2219 break;
2220 case OP_LOAD:
2221 emitLOAD(insn);
2222 break;
2223 case OP_STORE:
2224 emitSTORE(insn);
2225 break;
2226 case OP_LINTERP:
2227 case OP_PINTERP:
2228 emitINTERP(insn);
2229 break;
2230 case OP_VFETCH:
2231 emitVFETCH(insn);
2232 break;
2233 case OP_EXPORT:
2234 emitEXPORT(insn);
2235 break;
2236 case OP_PFETCH:
2237 emitPFETCH(insn);
2238 break;
2239 case OP_EMIT:
2240 case OP_RESTART:
2241 emitOUT(insn);
2242 break;
2243 case OP_ADD:
2244 case OP_SUB:
2245 if (isFloatType(insn->dType))
2246 emitFADD(insn);
2247 else
2248 emitUADD(insn);
2249 break;
2250 case OP_MUL:
2251 if (isFloatType(insn->dType))
2252 emitFMUL(insn);
2253 else
2254 emitUMUL(insn);
2255 break;
2256 case OP_MAD:
2257 case OP_FMA:
2258 if (isFloatType(insn->dType))
2259 emitFMAD(insn);
2260 else
2261 emitIMAD(insn);
2262 break;
2263 case OP_SAD:
2264 emitISAD(insn);
2265 break;
2266 case OP_NOT:
2267 emitNOT(insn);
2268 break;
2269 case OP_AND:
2270 emitLogicOp(insn, 0);
2271 break;
2272 case OP_OR:
2273 emitLogicOp(insn, 1);
2274 break;
2275 case OP_XOR:
2276 emitLogicOp(insn, 2);
2277 break;
2278 case OP_SHL:
2279 case OP_SHR:
2280 emitShift(insn);
2281 break;
2282 case OP_SET:
2283 case OP_SET_AND:
2284 case OP_SET_OR:
2285 case OP_SET_XOR:
2286 emitSET(insn->asCmp());
2287 break;
2288 case OP_SELP:
2289 emitSELP(insn);
2290 break;
2291 case OP_SLCT:
2292 emitSLCT(insn->asCmp());
2293 break;
2294 case OP_MIN:
2295 case OP_MAX:
2296 emitMINMAX(insn);
2297 break;
2298 case OP_ABS:
2299 case OP_NEG:
2300 case OP_CEIL:
2301 case OP_FLOOR:
2302 case OP_TRUNC:
2303 case OP_CVT:
2304 case OP_SAT:
2305 emitCVT(insn);
2306 break;
2307 case OP_RSQ:
2308 emitSFnOp(insn, 5);
2309 break;
2310 case OP_RCP:
2311 emitSFnOp(insn, 4);
2312 break;
2313 case OP_LG2:
2314 emitSFnOp(insn, 3);
2315 break;
2316 case OP_EX2:
2317 emitSFnOp(insn, 2);
2318 break;
2319 case OP_SIN:
2320 emitSFnOp(insn, 1);
2321 break;
2322 case OP_COS:
2323 emitSFnOp(insn, 0);
2324 break;
2325 case OP_PRESIN:
2326 case OP_PREEX2:
2327 emitPreOp(insn);
2328 break;
2329 case OP_TEX:
2330 case OP_TXB:
2331 case OP_TXL:
2332 case OP_TXD:
2333 case OP_TXF:
2334 case OP_TXG:
2335 case OP_TXLQ:
2336 emitTEX(insn->asTex());
2337 break;
2338 case OP_TXQ:
2339 emitTXQ(insn->asTex());
2340 break;
2341 case OP_TEXBAR:
2342 emitTEXBAR(insn);
2343 break;
2344 case OP_SUBFM:
2345 case OP_SUCLAMP:
2346 case OP_SUEAU:
2347 emitSUCalc(insn);
2348 break;
2349 case OP_MADSP:
2350 emitMADSP(insn);
2351 break;
2352 case OP_SULDB:
2353 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2354 emitSULDGB(insn->asTex());
2355 else
2356 ERROR("SULDB not yet supported on < nve4\n");
2357 break;
2358 case OP_SUSTB:
2359 case OP_SUSTP:
2360 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2361 emitSUSTGx(insn->asTex());
2362 else
2363 ERROR("SUSTx not yet supported on < nve4\n");
2364 break;
2365 case OP_ATOM:
2366 emitATOM(insn);
2367 break;
2368 case OP_BRA:
2369 case OP_CALL:
2370 case OP_PRERET:
2371 case OP_RET:
2372 case OP_DISCARD:
2373 case OP_EXIT:
2374 case OP_PRECONT:
2375 case OP_CONT:
2376 case OP_PREBREAK:
2377 case OP_BREAK:
2378 case OP_JOINAT:
2379 case OP_BRKPT:
2380 case OP_QUADON:
2381 case OP_QUADPOP:
2382 emitFlow(insn);
2383 break;
2384 case OP_QUADOP:
2385 emitQUADOP(insn, insn->subOp, insn->lanes);
2386 break;
2387 case OP_DFDX:
2388 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2389 break;
2390 case OP_DFDY:
2391 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2392 break;
2393 case OP_POPCNT:
2394 emitPOPC(insn);
2395 break;
2396 case OP_INSBF:
2397 emitINSBF(insn);
2398 break;
2399 case OP_EXTBF:
2400 emitEXTBF(insn);
2401 break;
2402 case OP_BFIND:
2403 emitBFIND(insn);
2404 break;
2405 case OP_PERMT:
2406 emitPERMT(insn);
2407 break;
2408 case OP_JOIN:
2409 emitNOP(insn);
2410 insn->join = 1;
2411 break;
2412 case OP_BAR:
2413 emitBAR(insn);
2414 break;
2415 case OP_MEMBAR:
2416 emitMEMBAR(insn);
2417 break;
2418 case OP_CCTL:
2419 emitCCTL(insn);
2420 break;
2421 case OP_VSHL:
2422 emitVSHL(insn);
2423 break;
2424 case OP_PIXLD:
2425 emitPIXLD(insn);
2426 break;
2427 case OP_PHI:
2428 case OP_UNION:
2429 case OP_CONSTRAINT:
2430 ERROR("operation should have been eliminated");
2431 return false;
2432 case OP_EXP:
2433 case OP_LOG:
2434 case OP_SQRT:
2435 case OP_POW:
2436 ERROR("operation should have been lowered\n");
2437 return false;
2438 default:
2439 ERROR("unknow op\n");
2440 return false;
2441 }
2442
2443 if (insn->join) {
2444 code[0] |= 0x10;
2445 assert(insn->encSize == 8);
2446 }
2447
2448 code += insn->encSize / 4;
2449 codeSize += insn->encSize;
2450 return true;
2451 }
2452
2453 uint32_t
2454 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2455 {
2456 const Target::OpInfo &info = targ->getOpInfo(i);
2457
2458 if (writeIssueDelays || info.minEncSize == 8 || 1)
2459 return 8;
2460
2461 if (i->ftz || i->saturate || i->join)
2462 return 8;
2463 if (i->rnd != ROUND_N)
2464 return 8;
2465 if (i->predSrc >= 0 && i->op == OP_MAD)
2466 return 8;
2467
2468 if (i->op == OP_PINTERP) {
2469 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2470 return 8;
2471 } else
2472 if (i->op == OP_MOV && i->lanes != 0xf) {
2473 return 8;
2474 }
2475
2476 for (int s = 0; i->srcExists(s); ++s) {
2477 if (i->src(s).isIndirect(0))
2478 return 8;
2479
2480 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2481 if (SDATA(i->src(s)).offset >= 0x100)
2482 return 8;
2483 if (i->getSrc(s)->reg.fileIndex > 1 &&
2484 i->getSrc(s)->reg.fileIndex != 16)
2485 return 8;
2486 } else
2487 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2488 if (i->dType == TYPE_F32) {
2489 if (SDATA(i->src(s)).u32 >= 0x100)
2490 return 8;
2491 } else {
2492 if (SDATA(i->src(s)).u32 > 0xff)
2493 return 8;
2494 }
2495 }
2496
2497 if (i->op == OP_CVT)
2498 continue;
2499 if (i->src(s).mod != Modifier(0)) {
2500 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2501 if (i->op != OP_RSQ)
2502 return 8;
2503 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2504 if (i->op != OP_ADD || s != 0)
2505 return 8;
2506 }
2507 }
2508
2509 return 4;
2510 }
2511
2512 // Simplified, erring on safe side.
2513 class SchedDataCalculator : public Pass
2514 {
2515 public:
2516 SchedDataCalculator(const Target *targ) : targ(targ) { }
2517
2518 private:
2519 struct RegScores
2520 {
2521 struct Resource {
2522 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2523 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2524 int tex; // TEX to non-TEX delay 17 (0x11)
2525 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2526 int imul; // integer MUL to MUL delay 3
2527 } res;
2528 struct ScoreData {
2529 int r[64];
2530 int p[8];
2531 int c;
2532 } rd, wr;
2533 int base;
2534
2535 void rebase(const int base)
2536 {
2537 const int delta = this->base - base;
2538 if (!delta)
2539 return;
2540 this->base = 0;
2541
2542 for (int i = 0; i < 64; ++i) {
2543 rd.r[i] += delta;
2544 wr.r[i] += delta;
2545 }
2546 for (int i = 0; i < 8; ++i) {
2547 rd.p[i] += delta;
2548 wr.p[i] += delta;
2549 }
2550 rd.c += delta;
2551 wr.c += delta;
2552
2553 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2554 res.ld[f] += delta;
2555 res.st[f] += delta;
2556 }
2557 res.sfu += delta;
2558 res.imul += delta;
2559 res.tex += delta;
2560 }
2561 void wipe()
2562 {
2563 memset(&rd, 0, sizeof(rd));
2564 memset(&wr, 0, sizeof(wr));
2565 memset(&res, 0, sizeof(res));
2566 }
2567 int getLatest(const ScoreData& d) const
2568 {
2569 int max = 0;
2570 for (int i = 0; i < 64; ++i)
2571 if (d.r[i] > max)
2572 max = d.r[i];
2573 for (int i = 0; i < 8; ++i)
2574 if (d.p[i] > max)
2575 max = d.p[i];
2576 if (d.c > max)
2577 max = d.c;
2578 return max;
2579 }
2580 inline int getLatestRd() const
2581 {
2582 return getLatest(rd);
2583 }
2584 inline int getLatestWr() const
2585 {
2586 return getLatest(wr);
2587 }
2588 inline int getLatest() const
2589 {
2590 const int a = getLatestRd();
2591 const int b = getLatestWr();
2592
2593 int max = MAX2(a, b);
2594 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2595 max = MAX2(res.ld[f], max);
2596 max = MAX2(res.st[f], max);
2597 }
2598 max = MAX2(res.sfu, max);
2599 max = MAX2(res.imul, max);
2600 max = MAX2(res.tex, max);
2601 return max;
2602 }
2603 void setMax(const RegScores *that)
2604 {
2605 for (int i = 0; i < 64; ++i) {
2606 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2607 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2608 }
2609 for (int i = 0; i < 8; ++i) {
2610 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2611 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2612 }
2613 rd.c = MAX2(rd.c, that->rd.c);
2614 wr.c = MAX2(wr.c, that->wr.c);
2615
2616 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2617 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2618 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2619 }
2620 res.sfu = MAX2(res.sfu, that->res.sfu);
2621 res.imul = MAX2(res.imul, that->res.imul);
2622 res.tex = MAX2(res.tex, that->res.tex);
2623 }
2624 void print(int cycle)
2625 {
2626 for (int i = 0; i < 64; ++i) {
2627 if (rd.r[i] > cycle)
2628 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2629 if (wr.r[i] > cycle)
2630 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2631 }
2632 for (int i = 0; i < 8; ++i) {
2633 if (rd.p[i] > cycle)
2634 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2635 if (wr.p[i] > cycle)
2636 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2637 }
2638 if (rd.c > cycle)
2639 INFO("rd $c @ %i\n", rd.c);
2640 if (wr.c > cycle)
2641 INFO("wr $c @ %i\n", wr.c);
2642 if (res.sfu > cycle)
2643 INFO("sfu @ %i\n", res.sfu);
2644 if (res.imul > cycle)
2645 INFO("imul @ %i\n", res.imul);
2646 if (res.tex > cycle)
2647 INFO("tex @ %i\n", res.tex);
2648 }
2649 };
2650
2651 RegScores *score; // for current BB
2652 std::vector<RegScores> scoreBoards;
2653 int cycle;
2654 int prevData;
2655 operation prevOp;
2656
2657 const Target *targ;
2658
2659 bool visit(Function *);
2660 bool visit(BasicBlock *);
2661
2662 void commitInsn(const Instruction *, int cycle);
2663 int calcDelay(const Instruction *, int cycle) const;
2664 void setDelay(Instruction *, int delay, Instruction *next);
2665
2666 void recordRd(const Value *, const int ready);
2667 void recordWr(const Value *, const int ready);
2668 void checkRd(const Value *, int cycle, int& delay) const;
2669 void checkWr(const Value *, int cycle, int& delay) const;
2670
2671 int getCycles(const Instruction *, int origDelay) const;
2672 };
2673
2674 void
2675 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2676 {
2677 if (insn->op == OP_EXIT || insn->op == OP_RET)
2678 delay = MAX2(delay, 14);
2679
2680 if (insn->op == OP_TEXBAR) {
2681 // TODO: except if results not used before EXIT
2682 insn->sched = 0xc2;
2683 } else
2684 if (insn->op == OP_JOIN || insn->join) {
2685 insn->sched = 0x00;
2686 } else
2687 if (delay >= 0 || prevData == 0x04 ||
2688 !next || !targ->canDualIssue(insn, next)) {
2689 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2690 if (prevOp == OP_EXPORT)
2691 insn->sched |= 0x40;
2692 else
2693 insn->sched |= 0x20;
2694 } else {
2695 insn->sched = 0x04; // dual-issue
2696 }
2697
2698 if (prevData != 0x04 || prevOp != OP_EXPORT)
2699 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2700 prevOp = insn->op;
2701
2702 prevData = insn->sched;
2703 }
2704
2705 int
2706 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2707 {
2708 if (insn->sched & 0x80) {
2709 int c = (insn->sched & 0x0f) * 2 + 1;
2710 if (insn->op == OP_TEXBAR && origDelay > 0)
2711 c += origDelay;
2712 return c;
2713 }
2714 if (insn->sched & 0x60)
2715 return (insn->sched & 0x1f) + 1;
2716 return (insn->sched == 0x04) ? 0 : 32;
2717 }
2718
2719 bool
2720 SchedDataCalculator::visit(Function *func)
2721 {
2722 scoreBoards.resize(func->cfg.getSize());
2723 for (size_t i = 0; i < scoreBoards.size(); ++i)
2724 scoreBoards[i].wipe();
2725 return true;
2726 }
2727
2728 bool
2729 SchedDataCalculator::visit(BasicBlock *bb)
2730 {
2731 Instruction *insn;
2732 Instruction *next = NULL;
2733
2734 int cycle = 0;
2735
2736 prevData = 0x00;
2737 prevOp = OP_NOP;
2738 score = &scoreBoards.at(bb->getId());
2739
2740 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2741 // back branches will wait until all target dependencies are satisfied
2742 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2743 continue;
2744 BasicBlock *in = BasicBlock::get(ei.getNode());
2745 if (in->getExit()) {
2746 if (prevData != 0x04)
2747 prevData = in->getExit()->sched;
2748 prevOp = in->getExit()->op;
2749 }
2750 score->setMax(&scoreBoards.at(in->getId()));
2751 }
2752 if (bb->cfg.incidentCount() > 1)
2753 prevOp = OP_NOP;
2754
2755 #ifdef NVC0_DEBUG_SCHED_DATA
2756 INFO("=== BB:%i initial scores\n", bb->getId());
2757 score->print(cycle);
2758 #endif
2759
2760 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2761 next = insn->next;
2762
2763 commitInsn(insn, cycle);
2764 int delay = calcDelay(next, cycle);
2765 setDelay(insn, delay, next);
2766 cycle += getCycles(insn, delay);
2767
2768 #ifdef NVC0_DEBUG_SCHED_DATA
2769 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2770 insn->print();
2771 next->print();
2772 #endif
2773 }
2774 if (!insn)
2775 return true;
2776 commitInsn(insn, cycle);
2777
2778 int bbDelay = -1;
2779
2780 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2781 BasicBlock *out = BasicBlock::get(ei.getNode());
2782
2783 if (ei.getType() != Graph::Edge::BACK) {
2784 // only test the first instruction of the outgoing block
2785 next = out->getEntry();
2786 if (next)
2787 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2788 } else {
2789 // wait until all dependencies are satisfied
2790 const int regsFree = score->getLatest();
2791 next = out->getFirst();
2792 for (int c = cycle; next && c < regsFree; next = next->next) {
2793 bbDelay = MAX2(bbDelay, calcDelay(next, c));
2794 c += getCycles(next, bbDelay);
2795 }
2796 next = NULL;
2797 }
2798 }
2799 if (bb->cfg.outgoingCount() != 1)
2800 next = NULL;
2801 setDelay(insn, bbDelay, next);
2802 cycle += getCycles(insn, bbDelay);
2803
2804 score->rebase(cycle); // common base for initializing out blocks' scores
2805 return true;
2806 }
2807
2808 #define NVE4_MAX_ISSUE_DELAY 0x1f
2809 int
2810 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
2811 {
2812 int delay = 0, ready = cycle;
2813
2814 for (int s = 0; insn->srcExists(s); ++s)
2815 checkRd(insn->getSrc(s), cycle, delay);
2816 // WAR & WAW don't seem to matter
2817 // for (int s = 0; insn->srcExists(s); ++s)
2818 // recordRd(insn->getSrc(s), cycle);
2819
2820 switch (Target::getOpClass(insn->op)) {
2821 case OPCLASS_SFU:
2822 ready = score->res.sfu;
2823 break;
2824 case OPCLASS_ARITH:
2825 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2826 ready = score->res.imul;
2827 break;
2828 case OPCLASS_TEXTURE:
2829 ready = score->res.tex;
2830 break;
2831 case OPCLASS_LOAD:
2832 ready = score->res.ld[insn->src(0).getFile()];
2833 break;
2834 case OPCLASS_STORE:
2835 ready = score->res.st[insn->src(0).getFile()];
2836 break;
2837 default:
2838 break;
2839 }
2840 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
2841 ready = MAX2(ready, score->res.tex);
2842
2843 delay = MAX2(delay, ready - cycle);
2844
2845 // if can issue next cycle, delay is 0, not 1
2846 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
2847 }
2848
2849 void
2850 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
2851 {
2852 const int ready = cycle + targ->getLatency(insn);
2853
2854 for (int d = 0; insn->defExists(d); ++d)
2855 recordWr(insn->getDef(d), ready);
2856 // WAR & WAW don't seem to matter
2857 // for (int s = 0; insn->srcExists(s); ++s)
2858 // recordRd(insn->getSrc(s), cycle);
2859
2860 switch (Target::getOpClass(insn->op)) {
2861 case OPCLASS_SFU:
2862 score->res.sfu = cycle + 4;
2863 break;
2864 case OPCLASS_ARITH:
2865 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2866 score->res.imul = cycle + 4;
2867 break;
2868 case OPCLASS_TEXTURE:
2869 score->res.tex = cycle + 18;
2870 break;
2871 case OPCLASS_LOAD:
2872 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
2873 break;
2874 score->res.ld[insn->src(0).getFile()] = cycle + 4;
2875 score->res.st[insn->src(0).getFile()] = ready;
2876 break;
2877 case OPCLASS_STORE:
2878 score->res.st[insn->src(0).getFile()] = cycle + 4;
2879 score->res.ld[insn->src(0).getFile()] = ready;
2880 break;
2881 case OPCLASS_OTHER:
2882 if (insn->op == OP_TEXBAR)
2883 score->res.tex = cycle;
2884 break;
2885 default:
2886 break;
2887 }
2888
2889 #ifdef NVC0_DEBUG_SCHED_DATA
2890 score->print(cycle);
2891 #endif
2892 }
2893
2894 void
2895 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
2896 {
2897 int ready = cycle;
2898 int a, b;
2899
2900 switch (v->reg.file) {
2901 case FILE_GPR:
2902 a = v->reg.data.id;
2903 b = a + v->reg.size / 4;
2904 for (int r = a; r < b; ++r)
2905 ready = MAX2(ready, score->rd.r[r]);
2906 break;
2907 case FILE_PREDICATE:
2908 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
2909 break;
2910 case FILE_FLAGS:
2911 ready = MAX2(ready, score->rd.c);
2912 break;
2913 case FILE_SHADER_INPUT:
2914 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
2915 case FILE_MEMORY_LOCAL:
2916 case FILE_MEMORY_CONST:
2917 case FILE_MEMORY_SHARED:
2918 case FILE_MEMORY_GLOBAL:
2919 case FILE_SYSTEM_VALUE:
2920 // TODO: any restrictions here ?
2921 break;
2922 case FILE_IMMEDIATE:
2923 break;
2924 default:
2925 assert(0);
2926 break;
2927 }
2928 if (cycle < ready)
2929 delay = MAX2(delay, ready - cycle);
2930 }
2931
2932 void
2933 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
2934 {
2935 int ready = cycle;
2936 int a, b;
2937
2938 switch (v->reg.file) {
2939 case FILE_GPR:
2940 a = v->reg.data.id;
2941 b = a + v->reg.size / 4;
2942 for (int r = a; r < b; ++r)
2943 ready = MAX2(ready, score->wr.r[r]);
2944 break;
2945 case FILE_PREDICATE:
2946 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
2947 break;
2948 default:
2949 assert(v->reg.file == FILE_FLAGS);
2950 ready = MAX2(ready, score->wr.c);
2951 break;
2952 }
2953 if (cycle < ready)
2954 delay = MAX2(delay, ready - cycle);
2955 }
2956
2957 void
2958 SchedDataCalculator::recordWr(const Value *v, const int ready)
2959 {
2960 int a = v->reg.data.id;
2961
2962 if (v->reg.file == FILE_GPR) {
2963 int b = a + v->reg.size / 4;
2964 for (int r = a; r < b; ++r)
2965 score->rd.r[r] = ready;
2966 } else
2967 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
2968 if (v->reg.file == FILE_PREDICATE) {
2969 score->rd.p[a] = ready + 4;
2970 } else {
2971 assert(v->reg.file == FILE_FLAGS);
2972 score->rd.c = ready + 4;
2973 }
2974 }
2975
2976 void
2977 SchedDataCalculator::recordRd(const Value *v, const int ready)
2978 {
2979 int a = v->reg.data.id;
2980
2981 if (v->reg.file == FILE_GPR) {
2982 int b = a + v->reg.size / 4;
2983 for (int r = a; r < b; ++r)
2984 score->wr.r[r] = ready;
2985 } else
2986 if (v->reg.file == FILE_PREDICATE) {
2987 score->wr.p[a] = ready;
2988 } else
2989 if (v->reg.file == FILE_FLAGS) {
2990 score->wr.c = ready;
2991 }
2992 }
2993
2994 bool
2995 calculateSchedDataNVC0(const Target *targ, Function *func)
2996 {
2997 SchedDataCalculator sched(targ);
2998 return sched.run(func, true, true);
2999 }
3000
3001 void
3002 CodeEmitterNVC0::prepareEmission(Function *func)
3003 {
3004 CodeEmitter::prepareEmission(func);
3005
3006 if (targ->hasSWSched)
3007 calculateSchedDataNVC0(targ, func);
3008 }
3009
3010 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3011 : CodeEmitter(target),
3012 targNVC0(target),
3013 writeIssueDelays(target->hasSWSched)
3014 {
3015 code = NULL;
3016 codeSize = codeSizeLimit = 0;
3017 relocInfo = NULL;
3018 }
3019
3020 CodeEmitter *
3021 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3022 {
3023 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3024 emit->setProgramType(type);
3025 return emit;
3026 }
3027
3028 CodeEmitter *
3029 TargetNVC0::getCodeEmitter(Program::Type type)
3030 {
3031 if (chipset >= NVISA_GK20A_CHIPSET)
3032 return createCodeEmitterGK110(type);
3033 return createCodeEmitterNVC0(type);
3034 }
3035
3036 } // namespace nv50_ir