2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "codegen/nv50_ir_target_nvc0.h"
27 // Argh, all these assertions ...
29 class CodeEmitterNVC0
: public CodeEmitter
32 CodeEmitterNVC0(const TargetNVC0
*);
34 virtual bool emitInstruction(Instruction
*);
35 virtual uint32_t getMinEncodingSize(const Instruction
*) const;
36 virtual void prepareEmission(Function
*);
38 inline void setProgramType(Program::Type pType
) { progType
= pType
; }
41 const TargetNVC0
*targNVC0
;
43 Program::Type progType
;
45 const bool writeIssueDelays
;
48 void emitForm_A(const Instruction
*, uint64_t);
49 void emitForm_B(const Instruction
*, uint64_t);
50 void emitForm_S(const Instruction
*, uint32_t, bool pred
);
52 void emitPredicate(const Instruction
*);
54 void setAddress16(const ValueRef
&);
55 void setAddress24(const ValueRef
&);
56 void setAddressByFile(const ValueRef
&);
57 void setImmediate(const Instruction
*, const int s
); // needs op already set
58 void setImmediateS8(const ValueRef
&);
59 void setSUConst16(const Instruction
*, const int s
);
60 void setSUPred(const Instruction
*, const int s
);
62 void emitCondCode(CondCode cc
, int pos
);
63 void emitInterpMode(const Instruction
*);
64 void emitLoadStoreType(DataType ty
);
65 void emitSUGType(DataType
);
66 void emitCachingMode(CacheMode c
);
68 void emitShortSrc2(const ValueRef
&);
70 inline uint8_t getSRegEncoding(const ValueRef
&);
72 void roundMode_A(const Instruction
*);
73 void roundMode_C(const Instruction
*);
74 void roundMode_CS(const Instruction
*);
76 void emitNegAbs12(const Instruction
*);
78 void emitNOP(const Instruction
*);
80 void emitLOAD(const Instruction
*);
81 void emitSTORE(const Instruction
*);
82 void emitMOV(const Instruction
*);
83 void emitATOM(const Instruction
*);
84 void emitMEMBAR(const Instruction
*);
85 void emitCCTL(const Instruction
*);
87 void emitINTERP(const Instruction
*);
88 void emitAFETCH(const Instruction
*);
89 void emitPFETCH(const Instruction
*);
90 void emitVFETCH(const Instruction
*);
91 void emitEXPORT(const Instruction
*);
92 void emitOUT(const Instruction
*);
94 void emitUADD(const Instruction
*);
95 void emitFADD(const Instruction
*);
96 void emitDADD(const Instruction
*);
97 void emitUMUL(const Instruction
*);
98 void emitFMUL(const Instruction
*);
99 void emitDMUL(const Instruction
*);
100 void emitIMAD(const Instruction
*);
101 void emitISAD(const Instruction
*);
102 void emitFMAD(const Instruction
*);
103 void emitDMAD(const Instruction
*);
104 void emitMADSP(const Instruction
*);
106 void emitNOT(Instruction
*);
107 void emitLogicOp(const Instruction
*, uint8_t subOp
);
108 void emitPOPC(const Instruction
*);
109 void emitINSBF(const Instruction
*);
110 void emitEXTBF(const Instruction
*);
111 void emitBFIND(const Instruction
*);
112 void emitPERMT(const Instruction
*);
113 void emitShift(const Instruction
*);
115 void emitSFnOp(const Instruction
*, uint8_t subOp
);
117 void emitCVT(Instruction
*);
118 void emitMINMAX(const Instruction
*);
119 void emitPreOp(const Instruction
*);
121 void emitSET(const CmpInstruction
*);
122 void emitSLCT(const CmpInstruction
*);
123 void emitSELP(const Instruction
*);
125 void emitTEXBAR(const Instruction
*);
126 void emitTEX(const TexInstruction
*);
127 void emitTEXCSAA(const TexInstruction
*);
128 void emitTXQ(const TexInstruction
*);
130 void emitQUADOP(const Instruction
*, uint8_t qOp
, uint8_t laneMask
);
132 void emitFlow(const Instruction
*);
133 void emitBAR(const Instruction
*);
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction
*);
137 void emitSULDGB(const TexInstruction
*);
138 void emitSUSTGx(const TexInstruction
*);
140 void emitVSHL(const Instruction
*);
141 void emitVectorSubOp(const Instruction
*);
143 void emitPIXLD(const Instruction
*);
145 inline void defId(const ValueDef
&, const int pos
);
146 inline void defId(const Instruction
*, int d
, const int pos
);
147 inline void srcId(const ValueRef
&, const int pos
);
148 inline void srcId(const ValueRef
*, const int pos
);
149 inline void srcId(const Instruction
*, int s
, const int pos
);
150 inline void srcAddr32(const ValueRef
&, int pos
, int shr
);
152 inline bool isLIMM(const ValueRef
&, DataType ty
);
155 // for better visibility
156 #define HEX64(h, l) 0x##h##l##ULL
158 #define SDATA(a) ((a).rep()->reg.data)
159 #define DDATA(a) ((a).rep()->reg.data)
161 void CodeEmitterNVC0::srcId(const ValueRef
& src
, const int pos
)
163 code
[pos
/ 32] |= (src
.get() ? SDATA(src
).id
: 63) << (pos
% 32);
166 void CodeEmitterNVC0::srcId(const ValueRef
*src
, const int pos
)
168 code
[pos
/ 32] |= (src
? SDATA(*src
).id
: 63) << (pos
% 32);
171 void CodeEmitterNVC0::srcId(const Instruction
*insn
, int s
, int pos
)
173 int r
= insn
->srcExists(s
) ? SDATA(insn
->src(s
)).id
: 63;
174 code
[pos
/ 32] |= r
<< (pos
% 32);
178 CodeEmitterNVC0::srcAddr32(const ValueRef
& src
, int pos
, int shr
)
180 const uint32_t offset
= SDATA(src
).offset
>> shr
;
182 code
[pos
/ 32] |= offset
<< (pos
% 32);
183 if (pos
&& (pos
< 32))
184 code
[1] |= offset
>> (32 - pos
);
187 void CodeEmitterNVC0::defId(const ValueDef
& def
, const int pos
)
189 code
[pos
/ 32] |= (def
.get() ? DDATA(def
).id
: 63) << (pos
% 32);
192 void CodeEmitterNVC0::defId(const Instruction
*insn
, int d
, int pos
)
194 int r
= insn
->defExists(d
) ? DDATA(insn
->def(d
)).id
: 63;
195 code
[pos
/ 32] |= r
<< (pos
% 32);
198 bool CodeEmitterNVC0::isLIMM(const ValueRef
& ref
, DataType ty
)
200 const ImmediateValue
*imm
= ref
.get()->asImm();
202 return imm
&& (imm
->reg
.data
.u32
& ((ty
== TYPE_F32
) ? 0xfff : 0xfff00000));
206 CodeEmitterNVC0::roundMode_A(const Instruction
*insn
)
209 case ROUND_M
: code
[1] |= 1 << 23; break;
210 case ROUND_P
: code
[1] |= 2 << 23; break;
211 case ROUND_Z
: code
[1] |= 3 << 23; break;
213 assert(insn
->rnd
== ROUND_N
);
219 CodeEmitterNVC0::emitNegAbs12(const Instruction
*i
)
221 if (i
->src(1).mod
.abs()) code
[0] |= 1 << 6;
222 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 7;
223 if (i
->src(1).mod
.neg()) code
[0] |= 1 << 8;
224 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 9;
227 void CodeEmitterNVC0::emitCondCode(CondCode cc
, int pos
)
232 case CC_LT
: val
= 0x1; break;
233 case CC_LTU
: val
= 0x9; break;
234 case CC_EQ
: val
= 0x2; break;
235 case CC_EQU
: val
= 0xa; break;
236 case CC_LE
: val
= 0x3; break;
237 case CC_LEU
: val
= 0xb; break;
238 case CC_GT
: val
= 0x4; break;
239 case CC_GTU
: val
= 0xc; break;
240 case CC_NE
: val
= 0x5; break;
241 case CC_NEU
: val
= 0xd; break;
242 case CC_GE
: val
= 0x6; break;
243 case CC_GEU
: val
= 0xe; break;
244 case CC_TR
: val
= 0xf; break;
245 case CC_FL
: val
= 0x0; break;
247 case CC_A
: val
= 0x14; break;
248 case CC_NA
: val
= 0x13; break;
249 case CC_S
: val
= 0x15; break;
250 case CC_NS
: val
= 0x12; break;
251 case CC_C
: val
= 0x16; break;
252 case CC_NC
: val
= 0x11; break;
253 case CC_O
: val
= 0x17; break;
254 case CC_NO
: val
= 0x10; break;
258 assert(!"invalid condition code");
261 code
[pos
/ 32] |= val
<< (pos
% 32);
265 CodeEmitterNVC0::emitPredicate(const Instruction
*i
)
267 if (i
->predSrc
>= 0) {
268 assert(i
->getPredicate()->reg
.file
== FILE_PREDICATE
);
269 srcId(i
->src(i
->predSrc
), 10);
270 if (i
->cc
== CC_NOT_P
)
271 code
[0] |= 0x2000; // negate
278 CodeEmitterNVC0::setAddressByFile(const ValueRef
& src
)
280 switch (src
.getFile()) {
281 case FILE_MEMORY_GLOBAL
:
282 srcAddr32(src
, 26, 0);
284 case FILE_MEMORY_LOCAL
:
285 case FILE_MEMORY_SHARED
:
289 assert(src
.getFile() == FILE_MEMORY_CONST
);
296 CodeEmitterNVC0::setAddress16(const ValueRef
& src
)
298 Symbol
*sym
= src
.get()->asSym();
302 code
[0] |= (sym
->reg
.data
.offset
& 0x003f) << 26;
303 code
[1] |= (sym
->reg
.data
.offset
& 0xffc0) >> 6;
307 CodeEmitterNVC0::setAddress24(const ValueRef
& src
)
309 Symbol
*sym
= src
.get()->asSym();
313 code
[0] |= (sym
->reg
.data
.offset
& 0x00003f) << 26;
314 code
[1] |= (sym
->reg
.data
.offset
& 0xffffc0) >> 6;
318 CodeEmitterNVC0::setImmediate(const Instruction
*i
, const int s
)
320 const ImmediateValue
*imm
= i
->src(s
).get()->asImm();
324 u32
= imm
->reg
.data
.u32
;
326 if ((code
[0] & 0xf) == 0x2) {
328 code
[0] |= (u32
& 0x3f) << 26;
331 if ((code
[0] & 0xf) == 0x3 || (code
[0] & 0xf) == 4) {
333 assert((u32
& 0xfff00000) == 0 || (u32
& 0xfff00000) == 0xfff00000);
334 assert(!(code
[1] & 0xc000));
336 code
[0] |= (u32
& 0x3f) << 26;
337 code
[1] |= 0xc000 | (u32
>> 6);
340 assert(!(u32
& 0x00000fff));
341 assert(!(code
[1] & 0xc000));
342 code
[0] |= ((u32
>> 12) & 0x3f) << 26;
343 code
[1] |= 0xc000 | (u32
>> 18);
347 void CodeEmitterNVC0::setImmediateS8(const ValueRef
&ref
)
349 const ImmediateValue
*imm
= ref
.get()->asImm();
351 int8_t s8
= static_cast<int8_t>(imm
->reg
.data
.s32
);
353 assert(s8
== imm
->reg
.data
.s32
);
355 code
[0] |= (s8
& 0x3f) << 26;
356 code
[0] |= (s8
>> 6) << 8;
360 CodeEmitterNVC0::emitForm_A(const Instruction
*i
, uint64_t opc
)
367 defId(i
->def(0), 14);
370 if (i
->srcExists(2) && i
->getSrc(2)->reg
.file
== FILE_MEMORY_CONST
)
373 for (int s
= 0; s
< 3 && i
->srcExists(s
); ++s
) {
374 switch (i
->getSrc(s
)->reg
.file
) {
375 case FILE_MEMORY_CONST
:
376 assert(!(code
[1] & 0xc000));
377 code
[1] |= (s
== 2) ? 0x8000 : 0x4000;
378 code
[1] |= i
->getSrc(s
)->reg
.fileIndex
<< 10;
379 setAddress16(i
->src(s
));
383 i
->op
== OP_MOV
|| i
->op
== OP_PRESIN
|| i
->op
== OP_PREEX2
);
384 assert(!(code
[1] & 0xc000));
388 if ((s
== 2) && ((code
[0] & 0x7) == 2)) // LIMM: 3rd src == dst
390 srcId(i
->src(s
), s
? ((s
== 2) ? 49 : s1
) : 20);
393 // ignore here, can be predicate or flags, but must not be address
400 CodeEmitterNVC0::emitForm_B(const Instruction
*i
, uint64_t opc
)
407 defId(i
->def(0), 14);
409 switch (i
->src(0).getFile()) {
410 case FILE_MEMORY_CONST
:
411 assert(!(code
[1] & 0xc000));
412 code
[1] |= 0x4000 | (i
->src(0).get()->reg
.fileIndex
<< 10);
413 setAddress16(i
->src(0));
416 assert(!(code
[1] & 0xc000));
420 srcId(i
->src(0), 26);
423 // ignore here, can be predicate or flags, but must not be address
429 CodeEmitterNVC0::emitForm_S(const Instruction
*i
, uint32_t opc
, bool pred
)
434 if (opc
== 0x0d || opc
== 0x0e)
437 defId(i
->def(0), 14);
438 srcId(i
->src(0), 20);
440 assert(pred
|| (i
->predSrc
< 0));
444 for (int s
= 1; s
< 3 && i
->srcExists(s
); ++s
) {
445 if (i
->src(s
).get()->reg
.file
== FILE_MEMORY_CONST
) {
446 assert(!(code
[0] & (0x300 >> ss2a
)));
447 switch (i
->src(s
).get()->reg
.fileIndex
) {
448 case 0: code
[0] |= 0x100 >> ss2a
; break;
449 case 1: code
[0] |= 0x200 >> ss2a
; break;
450 case 16: code
[0] |= 0x300 >> ss2a
; break;
452 ERROR("invalid c[] space for short form\n");
456 code
[0] |= i
->getSrc(s
)->reg
.data
.offset
<< 24;
458 code
[0] |= i
->getSrc(s
)->reg
.data
.offset
<< 6;
460 if (i
->src(s
).getFile() == FILE_IMMEDIATE
) {
462 setImmediateS8(i
->src(s
));
464 if (i
->src(s
).getFile() == FILE_GPR
) {
465 srcId(i
->src(s
), (s
== 1) ? 26 : 8);
471 CodeEmitterNVC0::emitShortSrc2(const ValueRef
&src
)
473 if (src
.getFile() == FILE_MEMORY_CONST
) {
474 switch (src
.get()->reg
.fileIndex
) {
475 case 0: code
[0] |= 0x100; break;
476 case 1: code
[0] |= 0x200; break;
477 case 16: code
[0] |= 0x300; break;
479 assert(!"unsupported file index for short op");
482 srcAddr32(src
, 20, 2);
485 assert(src
.getFile() == FILE_GPR
);
490 CodeEmitterNVC0::emitNOP(const Instruction
*i
)
492 code
[0] = 0x000001e4;
493 code
[1] = 0x40000000;
498 CodeEmitterNVC0::emitFMAD(const Instruction
*i
)
500 bool neg1
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
502 if (i
->encSize
== 8) {
503 if (isLIMM(i
->src(1), TYPE_F32
)) {
504 emitForm_A(i
, HEX64(20000000, 00000002));
506 emitForm_A(i
, HEX64(30000000, 00000000));
508 if (i
->src(2).mod
.neg())
521 assert(!i
->saturate
&& !i
->src(2).mod
.neg());
522 emitForm_S(i
, (i
->src(2).getFile() == FILE_MEMORY_CONST
) ? 0x2e : 0x0e,
530 CodeEmitterNVC0::emitDMAD(const Instruction
*i
)
532 bool neg1
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
534 emitForm_A(i
, HEX64(20000000, 00000001));
536 if (i
->src(2).mod
.neg())
544 assert(!i
->saturate
);
549 CodeEmitterNVC0::emitFMUL(const Instruction
*i
)
551 bool neg
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
553 assert(i
->postFactor
>= -3 && i
->postFactor
<= 3);
555 if (i
->encSize
== 8) {
556 if (isLIMM(i
->src(1), TYPE_F32
)) {
557 assert(i
->postFactor
== 0); // constant folded, hopefully
558 emitForm_A(i
, HEX64(30000000, 00000002));
560 emitForm_A(i
, HEX64(58000000, 00000000));
562 code
[1] |= ((i
->postFactor
> 0) ?
563 (7 - i
->postFactor
) : (0 - i
->postFactor
)) << 17;
566 code
[1] ^= 1 << 25; // aliases with LIMM sign bit
577 assert(!neg
&& !i
->saturate
&& !i
->ftz
&& !i
->postFactor
);
578 emitForm_S(i
, 0xa8, true);
583 CodeEmitterNVC0::emitDMUL(const Instruction
*i
)
585 bool neg
= (i
->src(0).mod
^ i
->src(1).mod
).neg();
587 emitForm_A(i
, HEX64(50000000, 00000001));
593 assert(!i
->saturate
);
596 assert(!i
->postFactor
);
600 CodeEmitterNVC0::emitUMUL(const Instruction
*i
)
602 if (i
->encSize
== 8) {
603 if (i
->src(1).getFile() == FILE_IMMEDIATE
) {
604 emitForm_A(i
, HEX64(10000000, 00000002));
606 emitForm_A(i
, HEX64(50000000, 00000003));
608 if (i
->subOp
== NV50_IR_SUBOP_MUL_HIGH
)
610 if (i
->sType
== TYPE_S32
)
612 if (i
->dType
== TYPE_S32
)
615 emitForm_S(i
, i
->src(1).getFile() == FILE_IMMEDIATE
? 0xaa : 0x2a, true);
617 if (i
->sType
== TYPE_S32
)
623 CodeEmitterNVC0::emitFADD(const Instruction
*i
)
625 if (i
->encSize
== 8) {
626 if (isLIMM(i
->src(1), TYPE_F32
)) {
627 assert(!i
->saturate
);
628 emitForm_A(i
, HEX64(28000000, 00000002));
630 code
[0] |= i
->src(0).mod
.abs() << 7;
631 code
[0] |= i
->src(0).mod
.neg() << 9;
633 if (i
->src(1).mod
.abs())
634 code
[1] &= 0xfdffffff;
635 if ((i
->op
== OP_SUB
) != static_cast<bool>(i
->src(1).mod
.neg()))
636 code
[1] ^= 0x02000000;
638 emitForm_A(i
, HEX64(50000000, 00000000));
645 if (i
->op
== OP_SUB
) code
[0] ^= 1 << 8;
650 assert(!i
->saturate
&& i
->op
!= OP_SUB
&&
651 !i
->src(0).mod
.abs() &&
652 !i
->src(1).mod
.neg() && !i
->src(1).mod
.abs());
654 emitForm_S(i
, 0x49, true);
656 if (i
->src(0).mod
.neg())
662 CodeEmitterNVC0::emitDADD(const Instruction
*i
)
664 assert(i
->encSize
== 8);
665 emitForm_A(i
, HEX64(48000000, 00000001));
667 assert(!i
->saturate
);
675 CodeEmitterNVC0::emitUADD(const Instruction
*i
)
679 assert(!i
->src(0).mod
.abs() && !i
->src(1).mod
.abs());
680 assert(!i
->src(0).mod
.neg() || !i
->src(1).mod
.neg());
682 if (i
->src(0).mod
.neg())
684 if (i
->src(1).mod
.neg())
686 if (i
->op
== OP_SUB
) {
688 assert(addOp
!= 0x300); // would be add-plus-one
691 if (i
->encSize
== 8) {
692 if (isLIMM(i
->src(1), TYPE_U32
)) {
693 emitForm_A(i
, HEX64(08000000, 00000002));
695 code
[1] |= 1 << 26; // write carry
697 emitForm_A(i
, HEX64(48000000, 00000003));
699 code
[1] |= 1 << 16; // write carry
705 if (i
->flagsSrc
>= 0) // add carry
708 assert(!(addOp
& 0x100));
709 emitForm_S(i
, (addOp
>> 3) |
710 ((i
->src(1).getFile() == FILE_IMMEDIATE
) ? 0xac : 0x2c), true);
716 CodeEmitterNVC0::emitIMAD(const Instruction
*i
)
718 assert(i
->encSize
== 8);
719 emitForm_A(i
, HEX64(20000000, 00000003));
721 if (isSignedType(i
->dType
))
723 if (isSignedType(i
->sType
))
726 code
[1] |= i
->saturate
<< 24;
728 if (i
->flagsDef
>= 0) code
[1] |= 1 << 16;
729 if (i
->flagsSrc
>= 0) code
[1] |= 1 << 23;
731 if (i
->src(2).mod
.neg()) code
[0] |= 0x10;
732 if (i
->src(1).mod
.neg() ^
733 i
->src(0).mod
.neg()) code
[0] |= 0x20;
735 if (i
->subOp
== NV50_IR_SUBOP_MUL_HIGH
)
740 CodeEmitterNVC0::emitMADSP(const Instruction
*i
)
742 assert(targ
->getChipset() >= NVISA_GK104_CHIPSET
);
744 emitForm_A(i
, HEX64(00000000, 00000003));
746 if (i
->subOp
== NV50_IR_SUBOP_MADSP_SD
) {
747 code
[1] |= 0x01800000;
749 code
[0] |= (i
->subOp
& 0x00f) << 7;
750 code
[0] |= (i
->subOp
& 0x0f0) << 1;
751 code
[0] |= (i
->subOp
& 0x100) >> 3;
752 code
[0] |= (i
->subOp
& 0x200) >> 2;
753 code
[1] |= (i
->subOp
& 0xc00) << 13;
756 if (i
->flagsDef
>= 0)
761 CodeEmitterNVC0::emitISAD(const Instruction
*i
)
763 assert(i
->dType
== TYPE_S32
|| i
->dType
== TYPE_U32
);
764 assert(i
->encSize
== 8);
766 emitForm_A(i
, HEX64(38000000, 00000003));
768 if (i
->dType
== TYPE_S32
)
773 CodeEmitterNVC0::emitNOT(Instruction
*i
)
775 assert(i
->encSize
== 8);
776 i
->setSrc(1, i
->src(0));
777 emitForm_A(i
, HEX64(68000000, 000001c3
));
781 CodeEmitterNVC0::emitLogicOp(const Instruction
*i
, uint8_t subOp
)
783 if (i
->def(0).getFile() == FILE_PREDICATE
) {
784 code
[0] = 0x00000004 | (subOp
<< 30);
785 code
[1] = 0x0c000000;
789 defId(i
->def(0), 17);
790 srcId(i
->src(0), 20);
791 if (i
->src(0).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 23;
792 srcId(i
->src(1), 26);
793 if (i
->src(1).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 29;
795 if (i
->defExists(1)) {
796 defId(i
->def(1), 14);
801 if (i
->predSrc
!= 2 && i
->srcExists(2)) {
802 code
[1] |= subOp
<< 21;
803 srcId(i
->src(2), 17);
804 if (i
->src(2).mod
== Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 20;
806 code
[1] |= 0x000e0000;
809 if (i
->encSize
== 8) {
810 if (isLIMM(i
->src(1), TYPE_U32
)) {
811 emitForm_A(i
, HEX64(38000000, 00000002));
813 if (i
->flagsDef
>= 0)
816 emitForm_A(i
, HEX64(68000000, 00000003));
818 if (i
->flagsDef
>= 0)
821 code
[0] |= subOp
<< 6;
823 if (i
->flagsSrc
>= 0) // carry
826 if (i
->src(0).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 9;
827 if (i
->src(1).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 8;
829 emitForm_S(i
, (subOp
<< 5) |
830 ((i
->src(1).getFile() == FILE_IMMEDIATE
) ? 0x1d : 0x8d), true);
835 CodeEmitterNVC0::emitPOPC(const Instruction
*i
)
837 emitForm_A(i
, HEX64(54000000, 00000004));
839 if (i
->src(0).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 9;
840 if (i
->src(1).mod
& Modifier(NV50_IR_MOD_NOT
)) code
[0] |= 1 << 8;
844 CodeEmitterNVC0::emitINSBF(const Instruction
*i
)
846 emitForm_A(i
, HEX64(28000000, 00000003));
850 CodeEmitterNVC0::emitEXTBF(const Instruction
*i
)
852 emitForm_A(i
, HEX64(70000000, 00000003));
854 if (i
->dType
== TYPE_S32
)
856 if (i
->subOp
== NV50_IR_SUBOP_EXTBF_REV
)
861 CodeEmitterNVC0::emitBFIND(const Instruction
*i
)
863 emitForm_B(i
, HEX64(78000000, 00000003));
865 if (i
->dType
== TYPE_S32
)
867 if (i
->src(0).mod
== Modifier(NV50_IR_MOD_NOT
))
869 if (i
->subOp
== NV50_IR_SUBOP_BFIND_SAMT
)
874 CodeEmitterNVC0::emitPERMT(const Instruction
*i
)
876 emitForm_A(i
, HEX64(24000000, 00000004));
878 code
[0] |= i
->subOp
<< 5;
882 CodeEmitterNVC0::emitShift(const Instruction
*i
)
884 if (i
->op
== OP_SHR
) {
885 emitForm_A(i
, HEX64(58000000, 00000003)
886 | (isSignedType(i
->dType
) ? 0x20 : 0x00));
888 emitForm_A(i
, HEX64(60000000, 00000003));
891 if (i
->subOp
== NV50_IR_SUBOP_SHIFT_WRAP
)
896 CodeEmitterNVC0::emitPreOp(const Instruction
*i
)
898 if (i
->encSize
== 8) {
899 emitForm_B(i
, HEX64(60000000, 00000000));
901 if (i
->op
== OP_PREEX2
)
904 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 6;
905 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 8;
907 emitForm_S(i
, i
->op
== OP_PREEX2
? 0x74000008 : 0x70000008, true);
912 CodeEmitterNVC0::emitSFnOp(const Instruction
*i
, uint8_t subOp
)
914 if (i
->encSize
== 8) {
915 code
[0] = 0x00000000 | (subOp
<< 26);
916 code
[1] = 0xc8000000;
920 defId(i
->def(0), 14);
921 srcId(i
->src(0), 20);
923 assert(i
->src(0).getFile() == FILE_GPR
);
925 if (i
->saturate
) code
[0] |= 1 << 5;
927 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 7;
928 if (i
->src(0).mod
.neg()) code
[0] |= 1 << 9;
930 emitForm_S(i
, 0x80000008 | (subOp
<< 26), true);
932 assert(!i
->src(0).mod
.neg());
933 if (i
->src(0).mod
.abs()) code
[0] |= 1 << 30;
938 CodeEmitterNVC0::emitMINMAX(const Instruction
*i
)
942 assert(i
->encSize
== 8);
944 op
= (i
->op
== OP_MIN
) ? 0x080e000000000000ULL
: 0x081e000000000000ULL
;
949 if (!isFloatType(i
->dType
))
950 op
|= isSignedType(i
->dType
) ? 0x23 : 0x03;
951 if (i
->dType
== TYPE_F64
)
959 CodeEmitterNVC0::roundMode_C(const Instruction
*i
)
962 case ROUND_M
: code
[1] |= 1 << 17; break;
963 case ROUND_P
: code
[1] |= 2 << 17; break;
964 case ROUND_Z
: code
[1] |= 3 << 17; break;
965 case ROUND_NI
: code
[0] |= 1 << 7; break;
966 case ROUND_MI
: code
[0] |= 1 << 7; code
[1] |= 1 << 17; break;
967 case ROUND_PI
: code
[0] |= 1 << 7; code
[1] |= 2 << 17; break;
968 case ROUND_ZI
: code
[0] |= 1 << 7; code
[1] |= 3 << 17; break;
971 assert(!"invalid round mode");
977 CodeEmitterNVC0::roundMode_CS(const Instruction
*i
)
981 case ROUND_MI
: code
[0] |= 1 << 16; break;
983 case ROUND_PI
: code
[0] |= 2 << 16; break;
985 case ROUND_ZI
: code
[0] |= 3 << 16; break;
992 CodeEmitterNVC0::emitCVT(Instruction
*i
)
994 const bool f2f
= isFloatType(i
->dType
) && isFloatType(i
->sType
);
998 case OP_CEIL
: i
->rnd
= f2f
? ROUND_PI
: ROUND_P
; break;
999 case OP_FLOOR
: i
->rnd
= f2f
? ROUND_MI
: ROUND_M
; break;
1000 case OP_TRUNC
: i
->rnd
= f2f
? ROUND_ZI
: ROUND_Z
; break;
1005 const bool sat
= (i
->op
== OP_SAT
) || i
->saturate
;
1006 const bool abs
= (i
->op
== OP_ABS
) || i
->src(0).mod
.abs();
1007 const bool neg
= (i
->op
== OP_NEG
) || i
->src(0).mod
.neg();
1009 if (i
->op
== OP_NEG
&& i
->dType
== TYPE_U32
)
1014 if (i
->encSize
== 8) {
1015 emitForm_B(i
, HEX64(10000000, 00000004));
1019 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1020 code
[0] |= util_logbase2(typeSizeof(dType
)) << 20;
1021 code
[0] |= util_logbase2(typeSizeof(i
->sType
)) << 23;
1027 if (neg
&& i
->op
!= OP_ABS
)
1033 if (isSignedIntType(dType
))
1035 if (isSignedIntType(i
->sType
))
1038 if (isFloatType(dType
)) {
1039 if (!isFloatType(i
->sType
))
1040 code
[1] |= 0x08000000;
1042 if (isFloatType(i
->sType
))
1043 code
[1] |= 0x04000000;
1045 code
[1] |= 0x0c000000;
1048 if (i
->op
== OP_CEIL
|| i
->op
== OP_FLOOR
|| i
->op
== OP_TRUNC
) {
1051 if (isFloatType(dType
)) {
1052 if (isFloatType(i
->sType
))
1055 code
[0] = 0x088 | (isSignedType(i
->sType
) ? (1 << 8) : 0);
1057 assert(isFloatType(i
->sType
));
1059 code
[0] = 0x288 | (isSignedType(i
->sType
) ? (1 << 8) : 0);
1062 if (neg
) code
[0] |= 1 << 16;
1063 if (sat
) code
[0] |= 1 << 18;
1064 if (abs
) code
[0] |= 1 << 19;
1071 CodeEmitterNVC0::emitSET(const CmpInstruction
*i
)
1076 if (i
->sType
== TYPE_F64
)
1079 if (!isFloatType(i
->sType
))
1082 if (isSignedIntType(i
->sType
))
1084 if (isFloatType(i
->dType
)) {
1085 if (isFloatType(i
->sType
))
1092 case OP_SET_AND
: hi
= 0x10000000; break;
1093 case OP_SET_OR
: hi
= 0x10200000; break;
1094 case OP_SET_XOR
: hi
= 0x10400000; break;
1099 emitForm_A(i
, (static_cast<uint64_t>(hi
) << 32) | lo
);
1101 if (i
->op
!= OP_SET
)
1102 srcId(i
->src(2), 32 + 17);
1104 if (i
->def(0).getFile() == FILE_PREDICATE
) {
1105 if (i
->sType
== TYPE_F32
)
1106 code
[1] += 0x10000000;
1108 code
[1] += 0x08000000;
1110 code
[0] &= ~0xfc000;
1111 defId(i
->def(0), 17);
1112 if (i
->defExists(1))
1113 defId(i
->def(1), 14);
1121 emitCondCode(i
->setCond
, 32 + 23);
1126 CodeEmitterNVC0::emitSLCT(const CmpInstruction
*i
)
1132 op
= HEX64(30000000, 00000023);
1135 op
= HEX64(30000000, 00000003);
1138 op
= HEX64(38000000, 00000000);
1141 assert(!"invalid type for SLCT");
1147 CondCode cc
= i
->setCond
;
1149 if (i
->src(2).mod
.neg())
1150 cc
= reverseCondCode(cc
);
1152 emitCondCode(cc
, 32 + 23);
1158 void CodeEmitterNVC0::emitSELP(const Instruction
*i
)
1160 emitForm_A(i
, HEX64(20000000, 00000004));
1162 if (i
->cc
== CC_NOT_P
|| i
->src(2).mod
& Modifier(NV50_IR_MOD_NOT
))
1166 void CodeEmitterNVC0::emitTEXBAR(const Instruction
*i
)
1168 code
[0] = 0x00000006 | (i
->subOp
<< 26);
1169 code
[1] = 0xf0000000;
1171 emitCondCode(i
->flagsSrc
>= 0 ? i
->cc
: CC_ALWAYS
, 5);
1174 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction
*i
)
1176 code
[0] = 0x00000086;
1177 code
[1] = 0xd0000000;
1179 code
[1] |= i
->tex
.r
;
1180 code
[1] |= i
->tex
.s
<< 8;
1182 if (i
->tex
.liveOnly
)
1185 defId(i
->def(0), 14);
1186 srcId(i
->src(0), 20);
1190 isNextIndependentTex(const TexInstruction
*i
)
1192 if (!i
->next
|| !isTextureOp(i
->next
->op
))
1194 if (i
->getDef(0)->interfers(i
->next
->getSrc(0)))
1196 return !i
->next
->srcExists(1) || !i
->getDef(0)->interfers(i
->next
->getSrc(1));
1200 CodeEmitterNVC0::emitTEX(const TexInstruction
*i
)
1202 code
[0] = 0x00000006;
1204 if (isNextIndependentTex(i
))
1205 code
[0] |= 0x080; // t mode
1207 code
[0] |= 0x100; // p mode
1209 if (i
->tex
.liveOnly
)
1213 case OP_TEX
: code
[1] = 0x80000000; break;
1214 case OP_TXB
: code
[1] = 0x84000000; break;
1215 case OP_TXL
: code
[1] = 0x86000000; break;
1216 case OP_TXF
: code
[1] = 0x90000000; break;
1217 case OP_TXG
: code
[1] = 0xa0000000; break;
1218 case OP_TXLQ
: code
[1] = 0xb0000000; break;
1219 case OP_TXD
: code
[1] = 0xe0000000; break;
1221 assert(!"invalid texture op");
1224 if (i
->op
== OP_TXF
) {
1225 if (!i
->tex
.levelZero
)
1226 code
[1] |= 0x02000000;
1228 if (i
->tex
.levelZero
) {
1229 code
[1] |= 0x02000000;
1232 if (i
->op
!= OP_TXD
&& i
->tex
.derivAll
)
1235 defId(i
->def(0), 14);
1236 srcId(i
->src(0), 20);
1240 if (i
->op
== OP_TXG
) code
[0] |= i
->tex
.gatherComp
<< 5;
1242 code
[1] |= i
->tex
.mask
<< 14;
1244 code
[1] |= i
->tex
.r
;
1245 code
[1] |= i
->tex
.s
<< 8;
1246 if (i
->tex
.rIndirectSrc
>= 0 || i
->tex
.sIndirectSrc
>= 0)
1247 code
[1] |= 1 << 18; // in 1st source (with array index)
1250 code
[1] |= (i
->tex
.target
.getDim() - 1) << 20;
1251 if (i
->tex
.target
.isCube())
1253 if (i
->tex
.target
.isArray())
1255 if (i
->tex
.target
.isShadow())
1258 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1260 if (i
->srcExists(src1
) && i
->src(src1
).getFile() == FILE_IMMEDIATE
) {
1262 if (i
->op
== OP_TXL
)
1263 code
[1] &= ~(1 << 26);
1265 if (i
->op
== OP_TXF
)
1266 code
[1] &= ~(1 << 25);
1268 if (i
->tex
.target
== TEX_TARGET_2D_MS
||
1269 i
->tex
.target
== TEX_TARGET_2D_MS_ARRAY
)
1272 if (i
->tex
.useOffsets
== 1)
1274 if (i
->tex
.useOffsets
== 4)
1281 CodeEmitterNVC0::emitTXQ(const TexInstruction
*i
)
1283 code
[0] = 0x00000086;
1284 code
[1] = 0xc0000000;
1286 switch (i
->tex
.query
) {
1287 case TXQ_DIMS
: code
[1] |= 0 << 22; break;
1288 case TXQ_TYPE
: code
[1] |= 1 << 22; break;
1289 case TXQ_SAMPLE_POSITION
: code
[1] |= 2 << 22; break;
1290 case TXQ_FILTER
: code
[1] |= 3 << 22; break;
1291 case TXQ_LOD
: code
[1] |= 4 << 22; break;
1292 case TXQ_BORDER_COLOUR
: code
[1] |= 5 << 22; break;
1294 assert(!"invalid texture query");
1298 code
[1] |= i
->tex
.mask
<< 14;
1300 code
[1] |= i
->tex
.r
;
1301 code
[1] |= i
->tex
.s
<< 8;
1302 if (i
->tex
.sIndirectSrc
>= 0 || i
->tex
.rIndirectSrc
>= 0)
1305 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1307 defId(i
->def(0), 14);
1308 srcId(i
->src(0), 20);
1315 CodeEmitterNVC0::emitQUADOP(const Instruction
*i
, uint8_t qOp
, uint8_t laneMask
)
1317 code
[0] = 0x00000000 | (laneMask
<< 6);
1318 code
[1] = 0x48000000 | qOp
;
1320 defId(i
->def(0), 14);
1321 srcId(i
->src(0), 20);
1322 srcId(i
->srcExists(1) ? i
->src(1) : i
->src(0), 26);
1324 if (i
->op
== OP_QUADOP
&& progType
!= Program::TYPE_FRAGMENT
)
1325 code
[0] |= 1 << 9; // dall
1331 CodeEmitterNVC0::emitFlow(const Instruction
*i
)
1333 const FlowInstruction
*f
= i
->asFlow();
1335 unsigned mask
; // bit 0: predicate, bit 1: target
1337 code
[0] = 0x00000007;
1341 code
[1] = f
->absolute
? 0x00000000 : 0x40000000;
1342 if (i
->srcExists(0) && i
->src(0).getFile() == FILE_MEMORY_CONST
)
1347 code
[1] = f
->absolute
? 0x10000000 : 0x50000000;
1349 code
[0] |= 0x4000; // indirect calls always use c[] source
1353 case OP_EXIT
: code
[1] = 0x80000000; mask
= 1; break;
1354 case OP_RET
: code
[1] = 0x90000000; mask
= 1; break;
1355 case OP_DISCARD
: code
[1] = 0x98000000; mask
= 1; break;
1356 case OP_BREAK
: code
[1] = 0xa8000000; mask
= 1; break;
1357 case OP_CONT
: code
[1] = 0xb0000000; mask
= 1; break;
1359 case OP_JOINAT
: code
[1] = 0x60000000; mask
= 2; break;
1360 case OP_PREBREAK
: code
[1] = 0x68000000; mask
= 2; break;
1361 case OP_PRECONT
: code
[1] = 0x70000000; mask
= 2; break;
1362 case OP_PRERET
: code
[1] = 0x78000000; mask
= 2; break;
1364 case OP_QUADON
: code
[1] = 0xc0000000; mask
= 0; break;
1365 case OP_QUADPOP
: code
[1] = 0xc8000000; mask
= 0; break;
1366 case OP_BRKPT
: code
[1] = 0xd0000000; mask
= 0; break;
1368 assert(!"invalid flow operation");
1374 if (i
->flagsSrc
< 0)
1387 if (code
[0] & 0x4000) {
1388 assert(i
->srcExists(0) && i
->src(0).getFile() == FILE_MEMORY_CONST
);
1389 setAddress16(i
->src(0));
1390 code
[1] |= i
->getSrc(0)->reg
.fileIndex
<< 10;
1391 if (f
->op
== OP_BRA
)
1392 srcId(f
->src(0).getIndirect(0), 20);
1398 if (f
->op
== OP_CALL
) {
1403 assert(f
->absolute
);
1404 uint32_t pcAbs
= targNVC0
->getBuiltinOffset(f
->target
.builtin
);
1405 addReloc(RelocEntry::TYPE_BUILTIN
, 0, pcAbs
, 0xfc000000, 26);
1406 addReloc(RelocEntry::TYPE_BUILTIN
, 1, pcAbs
, 0x03ffffff, -6);
1408 assert(!f
->absolute
);
1409 int32_t pcRel
= f
->target
.fn
->binPos
- (codeSize
+ 8);
1410 code
[0] |= (pcRel
& 0x3f) << 26;
1411 code
[1] |= (pcRel
>> 6) & 0x3ffff;
1415 int32_t pcRel
= f
->target
.bb
->binPos
- (codeSize
+ 8);
1416 if (writeIssueDelays
&& !(f
->target
.bb
->binPos
& 0x3f))
1418 // currently we don't want absolute branches
1419 assert(!f
->absolute
);
1420 code
[0] |= (pcRel
& 0x3f) << 26;
1421 code
[1] |= (pcRel
>> 6) & 0x3ffff;
1426 CodeEmitterNVC0::emitBAR(const Instruction
*i
)
1428 Value
*rDef
= NULL
, *pDef
= NULL
;
1431 case NV50_IR_SUBOP_BAR_ARRIVE
: code
[0] = 0x84; break;
1432 case NV50_IR_SUBOP_BAR_RED_AND
: code
[0] = 0x24; break;
1433 case NV50_IR_SUBOP_BAR_RED_OR
: code
[0] = 0x44; break;
1434 case NV50_IR_SUBOP_BAR_RED_POPC
: code
[0] = 0x04; break;
1437 assert(i
->subOp
== NV50_IR_SUBOP_BAR_SYNC
);
1440 code
[1] = 0x50000000;
1442 code
[0] |= 63 << 14;
1448 if (i
->src(0).getFile() == FILE_GPR
) {
1449 srcId(i
->src(0), 20);
1451 ImmediateValue
*imm
= i
->getSrc(0)->asImm();
1453 code
[0] |= imm
->reg
.data
.u32
<< 20;
1458 if (i
->src(1).getFile() == FILE_GPR
) {
1459 srcId(i
->src(1), 26);
1461 ImmediateValue
*imm
= i
->getSrc(1)->asImm();
1463 code
[0] |= imm
->reg
.data
.u32
<< 26;
1464 code
[1] |= imm
->reg
.data
.u32
>> 6;
1468 if (i
->srcExists(2) && (i
->predSrc
!= 2)) {
1469 srcId(i
->src(2), 32 + 17);
1470 if (i
->src(2).mod
== Modifier(NV50_IR_MOD_NOT
))
1476 if (i
->defExists(0)) {
1477 if (i
->def(0).getFile() == FILE_GPR
)
1478 rDef
= i
->getDef(0);
1480 pDef
= i
->getDef(0);
1482 if (i
->defExists(1)) {
1483 if (i
->def(1).getFile() == FILE_GPR
)
1484 rDef
= i
->getDef(1);
1486 pDef
= i
->getDef(1);
1490 code
[0] &= ~(63 << 14);
1494 code
[1] &= ~(7 << 21);
1495 defId(pDef
, 32 + 21);
1500 CodeEmitterNVC0::emitAFETCH(const Instruction
*i
)
1502 code
[0] = 0x00000006;
1503 code
[1] = 0x0c000000 | (i
->src(0).get()->reg
.data
.offset
& 0x7ff);
1505 if (i
->getSrc(0)->reg
.file
== FILE_SHADER_OUTPUT
)
1510 defId(i
->def(0), 14);
1511 srcId(i
->src(0).getIndirect(0), 20);
1515 CodeEmitterNVC0::emitPFETCH(const Instruction
*i
)
1517 uint32_t prim
= i
->src(0).get()->reg
.data
.u32
;
1519 code
[0] = 0x00000006 | ((prim
& 0x3f) << 26);
1520 code
[1] = 0x00000000 | (prim
>> 6);
1524 const int src1
= (i
->predSrc
== 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1526 defId(i
->def(0), 14);
1531 CodeEmitterNVC0::emitVFETCH(const Instruction
*i
)
1533 code
[0] = 0x00000006;
1534 code
[1] = 0x06000000 | i
->src(0).get()->reg
.data
.offset
;
1538 if (i
->getSrc(0)->reg
.file
== FILE_SHADER_OUTPUT
)
1539 code
[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1543 code
[0] |= ((i
->getDef(0)->reg
.size
/ 4) - 1) << 5;
1545 defId(i
->def(0), 14);
1546 srcId(i
->src(0).getIndirect(0), 20);
1547 srcId(i
->src(0).getIndirect(1), 26); // vertex address
1551 CodeEmitterNVC0::emitEXPORT(const Instruction
*i
)
1553 unsigned int size
= typeSizeof(i
->dType
);
1555 code
[0] = 0x00000006 | ((size
/ 4 - 1) << 5);
1556 code
[1] = 0x0a000000 | i
->src(0).get()->reg
.data
.offset
;
1558 assert(!(code
[1] & ((size
== 12) ? 15 : (size
- 1))));
1565 assert(i
->src(1).getFile() == FILE_GPR
);
1567 srcId(i
->src(0).getIndirect(0), 20);
1568 srcId(i
->src(0).getIndirect(1), 32 + 17); // vertex base address
1569 srcId(i
->src(1), 26);
1573 CodeEmitterNVC0::emitOUT(const Instruction
*i
)
1575 code
[0] = 0x00000006;
1576 code
[1] = 0x1c000000;
1580 defId(i
->def(0), 14); // new secret address
1581 srcId(i
->src(0), 20); // old secret address, should be 0 initially
1583 assert(i
->src(0).getFile() == FILE_GPR
);
1585 if (i
->op
== OP_EMIT
)
1587 if (i
->op
== OP_RESTART
|| i
->subOp
== NV50_IR_SUBOP_EMIT_RESTART
)
1591 if (i
->src(1).getFile() == FILE_IMMEDIATE
) {
1592 unsigned int stream
= SDATA(i
->src(1)).u32
;
1596 code
[0] |= stream
<< 26;
1601 srcId(i
->src(1), 26);
1606 CodeEmitterNVC0::emitInterpMode(const Instruction
*i
)
1608 if (i
->encSize
== 8) {
1609 code
[0] |= i
->ipa
<< 6; // TODO: INTERP_SAMPLEID
1611 if (i
->getInterpMode() == NV50_IR_INTERP_SC
)
1613 assert(i
->op
== OP_PINTERP
&& i
->getSampleMode() == 0);
1618 CodeEmitterNVC0::emitINTERP(const Instruction
*i
)
1620 const uint32_t base
= i
->getSrc(0)->reg
.data
.offset
;
1622 if (i
->encSize
== 8) {
1623 code
[0] = 0x00000000;
1624 code
[1] = 0xc0000000 | (base
& 0xffff);
1629 if (i
->op
== OP_PINTERP
)
1630 srcId(i
->src(1), 26);
1632 code
[0] |= 0x3f << 26;
1634 srcId(i
->src(0).getIndirect(0), 20);
1636 assert(i
->op
== OP_PINTERP
);
1637 code
[0] = 0x00000009 | ((base
& 0xc) << 6) | ((base
>> 4) << 26);
1638 srcId(i
->src(1), 20);
1643 defId(i
->def(0), 14);
1645 if (i
->getSampleMode() == NV50_IR_INTERP_OFFSET
)
1646 srcId(i
->src(i
->op
== OP_PINTERP
? 2 : 1), 32 + 17);
1648 code
[1] |= 0x3f << 17;
1652 CodeEmitterNVC0::emitLoadStoreType(DataType ty
)
1685 assert(!"invalid type");
1692 CodeEmitterNVC0::emitCachingMode(CacheMode c
)
1713 assert(!"invalid caching mode");
1720 uses64bitAddress(const Instruction
*ldst
)
1722 return ldst
->src(0).getFile() == FILE_MEMORY_GLOBAL
&&
1723 ldst
->src(0).isIndirect(0) &&
1724 ldst
->getIndirect(0, 0)->reg
.size
== 8;
1728 CodeEmitterNVC0::emitSTORE(const Instruction
*i
)
1732 switch (i
->src(0).getFile()) {
1733 case FILE_MEMORY_GLOBAL
: opc
= 0x90000000; break;
1734 case FILE_MEMORY_LOCAL
: opc
= 0xc8000000; break;
1735 case FILE_MEMORY_SHARED
: opc
= 0xc9000000; break;
1737 assert(!"invalid memory file");
1741 code
[0] = 0x00000005;
1744 setAddressByFile(i
->src(0));
1745 srcId(i
->src(1), 14);
1746 srcId(i
->src(0).getIndirect(0), 20);
1747 if (uses64bitAddress(i
))
1752 emitLoadStoreType(i
->dType
);
1753 emitCachingMode(i
->cache
);
1757 CodeEmitterNVC0::emitLOAD(const Instruction
*i
)
1761 code
[0] = 0x00000005;
1763 switch (i
->src(0).getFile()) {
1764 case FILE_MEMORY_GLOBAL
: opc
= 0x80000000; break;
1765 case FILE_MEMORY_LOCAL
: opc
= 0xc0000000; break;
1766 case FILE_MEMORY_SHARED
: opc
= 0xc1000000; break;
1767 case FILE_MEMORY_CONST
:
1768 if (!i
->src(0).isIndirect(0) && typeSizeof(i
->dType
) == 4) {
1769 emitMOV(i
); // not sure if this is any better
1772 opc
= 0x14000000 | (i
->src(0).get()->reg
.fileIndex
<< 10);
1773 code
[0] = 0x00000006 | (i
->subOp
<< 8);
1776 assert(!"invalid memory file");
1782 defId(i
->def(0), 14);
1784 setAddressByFile(i
->src(0));
1785 srcId(i
->src(0).getIndirect(0), 20);
1786 if (uses64bitAddress(i
))
1791 emitLoadStoreType(i
->dType
);
1792 emitCachingMode(i
->cache
);
1796 CodeEmitterNVC0::getSRegEncoding(const ValueRef
& ref
)
1798 switch (SDATA(ref
).sv
.sv
) {
1799 case SV_LANEID
: return 0x00;
1800 case SV_PHYSID
: return 0x03;
1801 case SV_VERTEX_COUNT
: return 0x10;
1802 case SV_INVOCATION_ID
: return 0x11;
1803 case SV_YDIR
: return 0x12;
1804 case SV_TID
: return 0x21 + SDATA(ref
).sv
.index
;
1805 case SV_CTAID
: return 0x25 + SDATA(ref
).sv
.index
;
1806 case SV_NTID
: return 0x29 + SDATA(ref
).sv
.index
;
1807 case SV_GRIDID
: return 0x2c;
1808 case SV_NCTAID
: return 0x2d + SDATA(ref
).sv
.index
;
1809 case SV_LBASE
: return 0x34;
1810 case SV_SBASE
: return 0x30;
1811 case SV_CLOCK
: return 0x50 + SDATA(ref
).sv
.index
;
1813 assert(!"no sreg for system value");
1819 CodeEmitterNVC0::emitMOV(const Instruction
*i
)
1821 if (i
->def(0).getFile() == FILE_PREDICATE
) {
1822 if (i
->src(0).getFile() == FILE_GPR
) {
1823 code
[0] = 0xfc01c003;
1824 code
[1] = 0x1a8e0000;
1825 srcId(i
->src(0), 20);
1827 code
[0] = 0x0001c004;
1828 code
[1] = 0x0c0e0000;
1829 if (i
->src(0).getFile() == FILE_IMMEDIATE
) {
1831 if (!i
->getSrc(0)->reg
.data
.u32
)
1834 srcId(i
->src(0), 20);
1837 defId(i
->def(0), 17);
1840 if (i
->src(0).getFile() == FILE_SYSTEM_VALUE
) {
1841 uint8_t sr
= getSRegEncoding(i
->src(0));
1843 if (i
->encSize
== 8) {
1844 code
[0] = 0x00000004 | (sr
<< 26);
1845 code
[1] = 0x2c000000;
1847 code
[0] = 0x40000008 | (sr
<< 20);
1849 defId(i
->def(0), 14);
1853 if (i
->encSize
== 8) {
1856 if (i
->src(0).getFile() == FILE_IMMEDIATE
)
1857 opc
= HEX64(18000000, 000001e2
);
1859 if (i
->src(0).getFile() == FILE_PREDICATE
)
1860 opc
= HEX64(080e0000
, 1c000004
);
1862 opc
= HEX64(28000000, 00000004);
1864 opc
|= i
->lanes
<< 5;
1870 if (i
->src(0).getFile() == FILE_IMMEDIATE
) {
1871 imm
= SDATA(i
->src(0)).u32
;
1872 if (imm
& 0xfff00000) {
1873 assert(!(imm
& 0x000fffff));
1874 code
[0] = 0x00000318 | imm
;
1876 assert(imm
< 0x800 || ((int32_t)imm
>= -0x800));
1877 code
[0] = 0x00000118 | (imm
<< 20);
1881 emitShortSrc2(i
->src(0));
1883 defId(i
->def(0), 14);
1890 CodeEmitterNVC0::emitATOM(const Instruction
*i
)
1892 const bool hasDst
= i
->defExists(0);
1893 const bool casOrExch
=
1894 i
->subOp
== NV50_IR_SUBOP_ATOM_EXCH
||
1895 i
->subOp
== NV50_IR_SUBOP_ATOM_CAS
;
1897 if (i
->dType
== TYPE_U64
) {
1899 case NV50_IR_SUBOP_ATOM_ADD
:
1902 code
[1] = 0x507e0000;
1904 code
[1] = 0x10000000;
1906 case NV50_IR_SUBOP_ATOM_EXCH
:
1908 code
[1] = 0x507e0000;
1910 case NV50_IR_SUBOP_ATOM_CAS
:
1912 code
[1] = 0x50000000;
1915 assert(!"invalid u64 red op");
1919 if (i
->dType
== TYPE_U32
) {
1921 case NV50_IR_SUBOP_ATOM_EXCH
:
1923 code
[1] = 0x507e0000;
1925 case NV50_IR_SUBOP_ATOM_CAS
:
1927 code
[1] = 0x50000000;
1930 code
[0] = 0x5 | (i
->subOp
<< 5);
1932 code
[1] = 0x507e0000;
1934 code
[1] = 0x10000000;
1938 if (i
->dType
== TYPE_S32
) {
1939 assert(i
->subOp
<= 2);
1940 code
[0] = 0x205 | (i
->subOp
<< 5);
1942 code
[1] = 0x587e0000;
1944 code
[1] = 0x18000000;
1946 if (i
->dType
== TYPE_F32
) {
1947 assert(i
->subOp
== NV50_IR_SUBOP_ATOM_ADD
);
1950 code
[1] = 0x687e0000;
1952 code
[1] = 0x28000000;
1957 srcId(i
->src(1), 14);
1960 defId(i
->def(0), 32 + 11);
1963 code
[1] |= 63 << 11;
1965 if (hasDst
|| casOrExch
) {
1966 const int32_t offset
= SDATA(i
->src(0)).offset
;
1967 assert(offset
< 0x80000 && offset
>= -0x80000);
1968 code
[0] |= offset
<< 26;
1969 code
[1] |= (offset
& 0x1ffc0) >> 6;
1970 code
[1] |= (offset
& 0xe0000) << 6;
1972 srcAddr32(i
->src(0), 26, 0);
1974 if (i
->getIndirect(0, 0)) {
1975 srcId(i
->getIndirect(0, 0), 20);
1976 if (i
->getIndirect(0, 0)->reg
.size
== 8)
1979 code
[0] |= 63 << 20;
1982 if (i
->subOp
== NV50_IR_SUBOP_ATOM_CAS
)
1983 srcId(i
->src(2), 32 + 17);
1987 CodeEmitterNVC0::emitMEMBAR(const Instruction
*i
)
1989 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i
->subOp
)) {
1990 case NV50_IR_SUBOP_MEMBAR_CTA
: code
[0] = 0x05; break;
1991 case NV50_IR_SUBOP_MEMBAR_GL
: code
[0] = 0x25; break;
1994 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i
->subOp
) == NV50_IR_SUBOP_MEMBAR_SYS
);
1997 code
[1] = 0xe0000000;
2003 CodeEmitterNVC0::emitCCTL(const Instruction
*i
)
2005 code
[0] = 0x00000005 | (i
->subOp
<< 5);
2007 if (i
->src(0).getFile() == FILE_MEMORY_GLOBAL
) {
2008 code
[1] = 0x98000000;
2009 srcAddr32(i
->src(0), 28, 2);
2011 code
[1] = 0xd0000000;
2012 setAddress24(i
->src(0));
2014 if (uses64bitAddress(i
))
2016 srcId(i
->src(0).getIndirect(0), 20);
2024 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp
)
2027 switch (subOp
& ~NV50_IR_SUBOP_SUCLAMP_2D
) {
2028 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m
= 0; break;
2029 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m
= 1; break;
2030 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m
= 2; break;
2031 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m
= 3; break;
2032 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m
= 4; break;
2033 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m
= 5; break;
2034 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m
= 6; break;
2035 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m
= 7; break;
2036 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m
= 8; break;
2037 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m
= 9; break;
2038 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m
= 10; break;
2039 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m
= 11; break;
2040 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m
= 12; break;
2041 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m
= 13; break;
2042 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m
= 14; break;
2047 if (subOp
& NV50_IR_SUBOP_SUCLAMP_2D
)
2052 CodeEmitterNVC0::emitSUCalc(Instruction
*i
)
2054 ImmediateValue
*imm
= NULL
;
2057 if (i
->srcExists(2)) {
2058 imm
= i
->getSrc(2)->asImm();
2060 i
->setSrc(2, NULL
); // special case, make emitForm_A not assert
2064 case OP_SUCLAMP
: opc
= HEX64(58000000, 00000004); break;
2065 case OP_SUBFM
: opc
= HEX64(5c000000
, 00000004); break;
2066 case OP_SUEAU
: opc
= HEX64(60000000, 00000004); break;
2073 if (i
->op
== OP_SUCLAMP
) {
2074 if (i
->dType
== TYPE_S32
)
2076 emitSUCLAMPMode(i
->subOp
);
2079 if (i
->op
== OP_SUBFM
&& i
->subOp
== NV50_IR_SUBOP_SUBFM_3D
)
2082 if (i
->op
!= OP_SUEAU
) {
2083 if (i
->def(0).getFile() == FILE_PREDICATE
) { // p, #
2084 code
[0] |= 63 << 14;
2085 code
[1] |= i
->getDef(0)->reg
.data
.id
<< 23;
2087 if (i
->defExists(1)) { // r, p
2088 assert(i
->def(1).getFile() == FILE_PREDICATE
);
2089 code
[1] |= i
->getDef(1)->reg
.data
.id
<< 23;
2095 assert(i
->op
== OP_SUCLAMP
);
2097 code
[1] |= (imm
->reg
.data
.u32
& 0x3f) << 17; // sint6
2102 CodeEmitterNVC0::emitSUGType(DataType ty
)
2105 case TYPE_S32
: code
[1] |= 1 << 13; break;
2106 case TYPE_U8
: code
[1] |= 2 << 13; break;
2107 case TYPE_S8
: code
[1] |= 3 << 13; break;
2109 assert(ty
== TYPE_U32
);
2115 CodeEmitterNVC0::setSUConst16(const Instruction
*i
, const int s
)
2117 const uint32_t offset
= i
->getSrc(s
)->reg
.data
.offset
;
2119 assert(i
->src(s
).getFile() == FILE_MEMORY_CONST
);
2120 assert(offset
== (offset
& 0xfffc));
2123 code
[0] |= offset
<< 24;
2124 code
[1] |= offset
>> 8;
2125 code
[1] |= i
->getSrc(s
)->reg
.fileIndex
<< 8;
2129 CodeEmitterNVC0::setSUPred(const Instruction
*i
, const int s
)
2131 if (!i
->srcExists(s
) || (i
->predSrc
== s
)) {
2132 code
[1] |= 0x7 << 17;
2134 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_NOT
))
2136 srcId(i
->src(s
), 32 + 17);
2141 CodeEmitterNVC0::emitSULDGB(const TexInstruction
*i
)
2144 code
[1] = 0xd4000000 | (i
->subOp
<< 15);
2146 emitLoadStoreType(i
->dType
);
2147 emitSUGType(i
->sType
);
2148 emitCachingMode(i
->cache
);
2151 defId(i
->def(0), 14); // destination
2152 srcId(i
->src(0), 20); // address
2154 if (i
->src(1).getFile() == FILE_GPR
)
2155 srcId(i
->src(1), 26);
2162 CodeEmitterNVC0::emitSUSTGx(const TexInstruction
*i
)
2165 code
[1] = 0xdc000000 | (i
->subOp
<< 15);
2167 if (i
->op
== OP_SUSTP
)
2168 code
[1] |= i
->tex
.mask
<< 22;
2170 emitLoadStoreType(i
->dType
);
2171 emitSUGType(i
->sType
);
2172 emitCachingMode(i
->cache
);
2175 srcId(i
->src(0), 20); // address
2177 if (i
->src(1).getFile() == FILE_GPR
)
2178 srcId(i
->src(1), 26);
2181 srcId(i
->src(3), 14); // values
2186 CodeEmitterNVC0::emitVectorSubOp(const Instruction
*i
)
2188 switch (NV50_IR_SUBOP_Vn(i
->subOp
)) {
2190 code
[1] |= (i
->subOp
& 0x000f) << 12; // vsrc1
2191 code
[1] |= (i
->subOp
& 0x00e0) >> 5; // vsrc2
2192 code
[1] |= (i
->subOp
& 0x0100) << 7; // vsrc2
2193 code
[1] |= (i
->subOp
& 0x3c00) << 13; // vdst
2196 code
[1] |= (i
->subOp
& 0x000f) << 8; // v2src1
2197 code
[1] |= (i
->subOp
& 0x0010) << 11; // v2src1
2198 code
[1] |= (i
->subOp
& 0x01e0) >> 1; // v2src2
2199 code
[1] |= (i
->subOp
& 0x0200) << 6; // v2src2
2200 code
[1] |= (i
->subOp
& 0x3c00) << 2; // v4dst
2201 code
[1] |= (i
->mask
& 0x3) << 2;
2204 code
[1] |= (i
->subOp
& 0x000f) << 8; // v4src1
2205 code
[1] |= (i
->subOp
& 0x01e0) >> 1; // v4src2
2206 code
[1] |= (i
->subOp
& 0x3c00) << 2; // v4dst
2207 code
[1] |= (i
->mask
& 0x3) << 2;
2208 code
[1] |= (i
->mask
& 0xc) << 21;
2217 CodeEmitterNVC0::emitVSHL(const Instruction
*i
)
2221 switch (NV50_IR_SUBOP_Vn(i
->subOp
)) {
2222 case 0: opc
|= 0xe8ULL
<< 56; break;
2223 case 1: opc
|= 0xb4ULL
<< 56; break;
2224 case 2: opc
|= 0x94ULL
<< 56; break;
2229 if (NV50_IR_SUBOP_Vn(i
->subOp
) == 1) {
2230 if (isSignedType(i
->dType
)) opc
|= 1ULL << 0x2a;
2231 if (isSignedType(i
->sType
)) opc
|= (1 << 6) | (1 << 5);
2233 if (isSignedType(i
->dType
)) opc
|= 1ULL << 0x39;
2234 if (isSignedType(i
->sType
)) opc
|= 1 << 6;
2241 if (i
->flagsDef
>= 0)
2246 CodeEmitterNVC0::emitPIXLD(const Instruction
*i
)
2248 assert(i
->encSize
== 8);
2249 emitForm_A(i
, HEX64(10000000, 00000006));
2250 code
[0] |= i
->subOp
<< 5;
2251 code
[1] |= 0x00e00000;
2255 CodeEmitterNVC0::emitInstruction(Instruction
*insn
)
2257 unsigned int size
= insn
->encSize
;
2259 if (writeIssueDelays
&& !(codeSize
& 0x3f))
2262 if (!insn
->encSize
) {
2263 ERROR("skipping unencodable instruction: "); insn
->print();
2266 if (codeSize
+ size
> codeSizeLimit
) {
2267 ERROR("code emitter output buffer too small\n");
2271 if (writeIssueDelays
) {
2272 if (!(codeSize
& 0x3f)) {
2273 code
[0] = 0x00000007; // cf issue delay "instruction"
2274 code
[1] = 0x20000000;
2278 const unsigned int id
= (codeSize
& 0x3f) / 8 - 1;
2279 uint32_t *data
= code
- (id
* 2 + 2);
2281 data
[0] |= insn
->sched
<< (id
* 8 + 4);
2284 data
[0] |= insn
->sched
<< 28;
2285 data
[1] |= insn
->sched
>> 4;
2287 data
[1] |= insn
->sched
<< ((id
- 4) * 8 + 4);
2291 // assert that instructions with multiple defs don't corrupt registers
2292 for (int d
= 0; insn
->defExists(d
); ++d
)
2293 assert(insn
->asTex() || insn
->def(d
).rep()->reg
.data
.id
>= 0);
2327 if (insn
->dType
== TYPE_F64
)
2329 else if (isFloatType(insn
->dType
))
2335 if (insn
->dType
== TYPE_F64
)
2337 else if (isFloatType(insn
->dType
))
2344 if (insn
->dType
== TYPE_F64
)
2346 else if (isFloatType(insn
->dType
))
2358 emitLogicOp(insn
, 0);
2361 emitLogicOp(insn
, 1);
2364 emitLogicOp(insn
, 2);
2374 emitSET(insn
->asCmp());
2380 emitSLCT(insn
->asCmp());
2396 emitSFnOp(insn
, 5 + 2 * insn
->subOp
);
2399 emitSFnOp(insn
, 4 + 2 * insn
->subOp
);
2424 emitTEX(insn
->asTex());
2427 emitTXQ(insn
->asTex());
2441 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2442 emitSULDGB(insn
->asTex());
2444 ERROR("SULDB not yet supported on < nve4\n");
2448 if (targ
->getChipset() >= NVISA_GK104_CHIPSET
)
2449 emitSUSTGx(insn
->asTex());
2451 ERROR("SUSTx not yet supported on < nve4\n");
2473 emitQUADOP(insn
, insn
->subOp
, insn
->lanes
);
2476 emitQUADOP(insn
, insn
->src(0).mod
.neg() ? 0x66 : 0x99, 0x4);
2479 emitQUADOP(insn
, insn
->src(0).mod
.neg() ? 0x5a : 0xa5, 0x5);
2518 ERROR("operation should have been eliminated");
2524 ERROR("operation should have been lowered\n");
2527 ERROR("unknow op\n");
2533 assert(insn
->encSize
== 8);
2536 code
+= insn
->encSize
/ 4;
2537 codeSize
+= insn
->encSize
;
2542 CodeEmitterNVC0::getMinEncodingSize(const Instruction
*i
) const
2544 const Target::OpInfo
&info
= targ
->getOpInfo(i
);
2546 if (writeIssueDelays
|| info
.minEncSize
== 8 || 1)
2549 if (i
->ftz
|| i
->saturate
|| i
->join
)
2551 if (i
->rnd
!= ROUND_N
)
2553 if (i
->predSrc
>= 0 && i
->op
== OP_MAD
)
2556 if (i
->op
== OP_PINTERP
) {
2557 if (i
->getSampleMode() || 1) // XXX: grr, short op doesn't work
2560 if (i
->op
== OP_MOV
&& i
->lanes
!= 0xf) {
2564 for (int s
= 0; i
->srcExists(s
); ++s
) {
2565 if (i
->src(s
).isIndirect(0))
2568 if (i
->src(s
).getFile() == FILE_MEMORY_CONST
) {
2569 if (SDATA(i
->src(s
)).offset
>= 0x100)
2571 if (i
->getSrc(s
)->reg
.fileIndex
> 1 &&
2572 i
->getSrc(s
)->reg
.fileIndex
!= 16)
2575 if (i
->src(s
).getFile() == FILE_IMMEDIATE
) {
2576 if (i
->dType
== TYPE_F32
) {
2577 if (SDATA(i
->src(s
)).u32
>= 0x100)
2580 if (SDATA(i
->src(s
)).u32
> 0xff)
2585 if (i
->op
== OP_CVT
)
2587 if (i
->src(s
).mod
!= Modifier(0)) {
2588 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_ABS
))
2589 if (i
->op
!= OP_RSQ
)
2591 if (i
->src(s
).mod
== Modifier(NV50_IR_MOD_NEG
))
2592 if (i
->op
!= OP_ADD
|| s
!= 0)
2600 // Simplified, erring on safe side.
2601 class SchedDataCalculator
: public Pass
2604 SchedDataCalculator(const Target
*targ
) : targ(targ
) { }
2610 int st
[DATA_FILE_COUNT
]; // LD to LD delay 3
2611 int ld
[DATA_FILE_COUNT
]; // ST to ST delay 3
2612 int tex
; // TEX to non-TEX delay 17 (0x11)
2613 int sfu
; // SFU to SFU delay 3 (except PRE-ops)
2614 int imul
; // integer MUL to MUL delay 3
2623 void rebase(const int base
)
2625 const int delta
= this->base
- base
;
2630 for (int i
= 0; i
< 64; ++i
) {
2634 for (int i
= 0; i
< 8; ++i
) {
2641 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
2651 memset(&rd
, 0, sizeof(rd
));
2652 memset(&wr
, 0, sizeof(wr
));
2653 memset(&res
, 0, sizeof(res
));
2655 int getLatest(const ScoreData
& d
) const
2658 for (int i
= 0; i
< 64; ++i
)
2661 for (int i
= 0; i
< 8; ++i
)
2668 inline int getLatestRd() const
2670 return getLatest(rd
);
2672 inline int getLatestWr() const
2674 return getLatest(wr
);
2676 inline int getLatest() const
2678 const int a
= getLatestRd();
2679 const int b
= getLatestWr();
2681 int max
= MAX2(a
, b
);
2682 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
2683 max
= MAX2(res
.ld
[f
], max
);
2684 max
= MAX2(res
.st
[f
], max
);
2686 max
= MAX2(res
.sfu
, max
);
2687 max
= MAX2(res
.imul
, max
);
2688 max
= MAX2(res
.tex
, max
);
2691 void setMax(const RegScores
*that
)
2693 for (int i
= 0; i
< 64; ++i
) {
2694 rd
.r
[i
] = MAX2(rd
.r
[i
], that
->rd
.r
[i
]);
2695 wr
.r
[i
] = MAX2(wr
.r
[i
], that
->wr
.r
[i
]);
2697 for (int i
= 0; i
< 8; ++i
) {
2698 rd
.p
[i
] = MAX2(rd
.p
[i
], that
->rd
.p
[i
]);
2699 wr
.p
[i
] = MAX2(wr
.p
[i
], that
->wr
.p
[i
]);
2701 rd
.c
= MAX2(rd
.c
, that
->rd
.c
);
2702 wr
.c
= MAX2(wr
.c
, that
->wr
.c
);
2704 for (unsigned int f
= 0; f
< DATA_FILE_COUNT
; ++f
) {
2705 res
.ld
[f
] = MAX2(res
.ld
[f
], that
->res
.ld
[f
]);
2706 res
.st
[f
] = MAX2(res
.st
[f
], that
->res
.st
[f
]);
2708 res
.sfu
= MAX2(res
.sfu
, that
->res
.sfu
);
2709 res
.imul
= MAX2(res
.imul
, that
->res
.imul
);
2710 res
.tex
= MAX2(res
.tex
, that
->res
.tex
);
2712 void print(int cycle
)
2714 for (int i
= 0; i
< 64; ++i
) {
2715 if (rd
.r
[i
] > cycle
)
2716 INFO("rd $r%i @ %i\n", i
, rd
.r
[i
]);
2717 if (wr
.r
[i
] > cycle
)
2718 INFO("wr $r%i @ %i\n", i
, wr
.r
[i
]);
2720 for (int i
= 0; i
< 8; ++i
) {
2721 if (rd
.p
[i
] > cycle
)
2722 INFO("rd $p%i @ %i\n", i
, rd
.p
[i
]);
2723 if (wr
.p
[i
] > cycle
)
2724 INFO("wr $p%i @ %i\n", i
, wr
.p
[i
]);
2727 INFO("rd $c @ %i\n", rd
.c
);
2729 INFO("wr $c @ %i\n", wr
.c
);
2730 if (res
.sfu
> cycle
)
2731 INFO("sfu @ %i\n", res
.sfu
);
2732 if (res
.imul
> cycle
)
2733 INFO("imul @ %i\n", res
.imul
);
2734 if (res
.tex
> cycle
)
2735 INFO("tex @ %i\n", res
.tex
);
2739 RegScores
*score
; // for current BB
2740 std::vector
<RegScores
> scoreBoards
;
2746 bool visit(Function
*);
2747 bool visit(BasicBlock
*);
2749 void commitInsn(const Instruction
*, int cycle
);
2750 int calcDelay(const Instruction
*, int cycle
) const;
2751 void setDelay(Instruction
*, int delay
, Instruction
*next
);
2753 void recordRd(const Value
*, const int ready
);
2754 void recordWr(const Value
*, const int ready
);
2755 void checkRd(const Value
*, int cycle
, int& delay
) const;
2756 void checkWr(const Value
*, int cycle
, int& delay
) const;
2758 int getCycles(const Instruction
*, int origDelay
) const;
2762 SchedDataCalculator::setDelay(Instruction
*insn
, int delay
, Instruction
*next
)
2764 if (insn
->op
== OP_EXIT
|| insn
->op
== OP_RET
)
2765 delay
= MAX2(delay
, 14);
2767 if (insn
->op
== OP_TEXBAR
) {
2768 // TODO: except if results not used before EXIT
2771 if (insn
->op
== OP_JOIN
|| insn
->join
) {
2774 if (delay
>= 0 || prevData
== 0x04 ||
2775 !next
|| !targ
->canDualIssue(insn
, next
)) {
2776 insn
->sched
= static_cast<uint8_t>(MAX2(delay
, 0));
2777 if (prevOp
== OP_EXPORT
)
2778 insn
->sched
|= 0x40;
2780 insn
->sched
|= 0x20;
2782 insn
->sched
= 0x04; // dual-issue
2785 if (prevData
!= 0x04 || prevOp
!= OP_EXPORT
)
2786 if (insn
->sched
!= 0x04 || insn
->op
== OP_EXPORT
)
2789 prevData
= insn
->sched
;
2793 SchedDataCalculator::getCycles(const Instruction
*insn
, int origDelay
) const
2795 if (insn
->sched
& 0x80) {
2796 int c
= (insn
->sched
& 0x0f) * 2 + 1;
2797 if (insn
->op
== OP_TEXBAR
&& origDelay
> 0)
2801 if (insn
->sched
& 0x60)
2802 return (insn
->sched
& 0x1f) + 1;
2803 return (insn
->sched
== 0x04) ? 0 : 32;
2807 SchedDataCalculator::visit(Function
*func
)
2809 scoreBoards
.resize(func
->cfg
.getSize());
2810 for (size_t i
= 0; i
< scoreBoards
.size(); ++i
)
2811 scoreBoards
[i
].wipe();
2816 SchedDataCalculator::visit(BasicBlock
*bb
)
2819 Instruction
*next
= NULL
;
2825 score
= &scoreBoards
.at(bb
->getId());
2827 for (Graph::EdgeIterator ei
= bb
->cfg
.incident(); !ei
.end(); ei
.next()) {
2828 // back branches will wait until all target dependencies are satisfied
2829 if (ei
.getType() == Graph::Edge::BACK
) // sched would be uninitialized
2831 BasicBlock
*in
= BasicBlock::get(ei
.getNode());
2832 if (in
->getExit()) {
2833 if (prevData
!= 0x04)
2834 prevData
= in
->getExit()->sched
;
2835 prevOp
= in
->getExit()->op
;
2837 score
->setMax(&scoreBoards
.at(in
->getId()));
2839 if (bb
->cfg
.incidentCount() > 1)
2842 #ifdef NVC0_DEBUG_SCHED_DATA
2843 INFO("=== BB:%i initial scores\n", bb
->getId());
2844 score
->print(cycle
);
2847 for (insn
= bb
->getEntry(); insn
&& insn
->next
; insn
= insn
->next
) {
2850 commitInsn(insn
, cycle
);
2851 int delay
= calcDelay(next
, cycle
);
2852 setDelay(insn
, delay
, next
);
2853 cycle
+= getCycles(insn
, delay
);
2855 #ifdef NVC0_DEBUG_SCHED_DATA
2856 INFO("cycle %i, sched %02x\n", cycle
, insn
->sched
);
2863 commitInsn(insn
, cycle
);
2867 for (Graph::EdgeIterator ei
= bb
->cfg
.outgoing(); !ei
.end(); ei
.next()) {
2868 BasicBlock
*out
= BasicBlock::get(ei
.getNode());
2870 if (ei
.getType() != Graph::Edge::BACK
) {
2871 // only test the first instruction of the outgoing block
2872 next
= out
->getEntry();
2874 bbDelay
= MAX2(bbDelay
, calcDelay(next
, cycle
));
2876 // wait until all dependencies are satisfied
2877 const int regsFree
= score
->getLatest();
2878 next
= out
->getFirst();
2879 for (int c
= cycle
; next
&& c
< regsFree
; next
= next
->next
) {
2880 bbDelay
= MAX2(bbDelay
, calcDelay(next
, c
));
2881 c
+= getCycles(next
, bbDelay
);
2886 if (bb
->cfg
.outgoingCount() != 1)
2888 setDelay(insn
, bbDelay
, next
);
2889 cycle
+= getCycles(insn
, bbDelay
);
2891 score
->rebase(cycle
); // common base for initializing out blocks' scores
2895 #define NVE4_MAX_ISSUE_DELAY 0x1f
2897 SchedDataCalculator::calcDelay(const Instruction
*insn
, int cycle
) const
2899 int delay
= 0, ready
= cycle
;
2901 for (int s
= 0; insn
->srcExists(s
); ++s
)
2902 checkRd(insn
->getSrc(s
), cycle
, delay
);
2903 // WAR & WAW don't seem to matter
2904 // for (int s = 0; insn->srcExists(s); ++s)
2905 // recordRd(insn->getSrc(s), cycle);
2907 switch (Target::getOpClass(insn
->op
)) {
2909 ready
= score
->res
.sfu
;
2912 if (insn
->op
== OP_MUL
&& !isFloatType(insn
->dType
))
2913 ready
= score
->res
.imul
;
2915 case OPCLASS_TEXTURE
:
2916 ready
= score
->res
.tex
;
2919 ready
= score
->res
.ld
[insn
->src(0).getFile()];
2922 ready
= score
->res
.st
[insn
->src(0).getFile()];
2927 if (Target::getOpClass(insn
->op
) != OPCLASS_TEXTURE
)
2928 ready
= MAX2(ready
, score
->res
.tex
);
2930 delay
= MAX2(delay
, ready
- cycle
);
2932 // if can issue next cycle, delay is 0, not 1
2933 return MIN2(delay
- 1, NVE4_MAX_ISSUE_DELAY
);
2937 SchedDataCalculator::commitInsn(const Instruction
*insn
, int cycle
)
2939 const int ready
= cycle
+ targ
->getLatency(insn
);
2941 for (int d
= 0; insn
->defExists(d
); ++d
)
2942 recordWr(insn
->getDef(d
), ready
);
2943 // WAR & WAW don't seem to matter
2944 // for (int s = 0; insn->srcExists(s); ++s)
2945 // recordRd(insn->getSrc(s), cycle);
2947 switch (Target::getOpClass(insn
->op
)) {
2949 score
->res
.sfu
= cycle
+ 4;
2952 if (insn
->op
== OP_MUL
&& !isFloatType(insn
->dType
))
2953 score
->res
.imul
= cycle
+ 4;
2955 case OPCLASS_TEXTURE
:
2956 score
->res
.tex
= cycle
+ 18;
2959 if (insn
->src(0).getFile() == FILE_MEMORY_CONST
)
2961 score
->res
.ld
[insn
->src(0).getFile()] = cycle
+ 4;
2962 score
->res
.st
[insn
->src(0).getFile()] = ready
;
2965 score
->res
.st
[insn
->src(0).getFile()] = cycle
+ 4;
2966 score
->res
.ld
[insn
->src(0).getFile()] = ready
;
2969 if (insn
->op
== OP_TEXBAR
)
2970 score
->res
.tex
= cycle
;
2976 #ifdef NVC0_DEBUG_SCHED_DATA
2977 score
->print(cycle
);
2982 SchedDataCalculator::checkRd(const Value
*v
, int cycle
, int& delay
) const
2987 switch (v
->reg
.file
) {
2990 b
= a
+ v
->reg
.size
/ 4;
2991 for (int r
= a
; r
< b
; ++r
)
2992 ready
= MAX2(ready
, score
->rd
.r
[r
]);
2994 case FILE_PREDICATE
:
2995 ready
= MAX2(ready
, score
->rd
.p
[v
->reg
.data
.id
]);
2998 ready
= MAX2(ready
, score
->rd
.c
);
3000 case FILE_SHADER_INPUT
:
3001 case FILE_SHADER_OUTPUT
: // yes, TCPs can read outputs
3002 case FILE_MEMORY_LOCAL
:
3003 case FILE_MEMORY_CONST
:
3004 case FILE_MEMORY_SHARED
:
3005 case FILE_MEMORY_GLOBAL
:
3006 case FILE_SYSTEM_VALUE
:
3007 // TODO: any restrictions here ?
3009 case FILE_IMMEDIATE
:
3016 delay
= MAX2(delay
, ready
- cycle
);
3020 SchedDataCalculator::checkWr(const Value
*v
, int cycle
, int& delay
) const
3025 switch (v
->reg
.file
) {
3028 b
= a
+ v
->reg
.size
/ 4;
3029 for (int r
= a
; r
< b
; ++r
)
3030 ready
= MAX2(ready
, score
->wr
.r
[r
]);
3032 case FILE_PREDICATE
:
3033 ready
= MAX2(ready
, score
->wr
.p
[v
->reg
.data
.id
]);
3036 assert(v
->reg
.file
== FILE_FLAGS
);
3037 ready
= MAX2(ready
, score
->wr
.c
);
3041 delay
= MAX2(delay
, ready
- cycle
);
3045 SchedDataCalculator::recordWr(const Value
*v
, const int ready
)
3047 int a
= v
->reg
.data
.id
;
3049 if (v
->reg
.file
== FILE_GPR
) {
3050 int b
= a
+ v
->reg
.size
/ 4;
3051 for (int r
= a
; r
< b
; ++r
)
3052 score
->rd
.r
[r
] = ready
;
3054 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3055 if (v
->reg
.file
== FILE_PREDICATE
) {
3056 score
->rd
.p
[a
] = ready
+ 4;
3058 assert(v
->reg
.file
== FILE_FLAGS
);
3059 score
->rd
.c
= ready
+ 4;
3064 SchedDataCalculator::recordRd(const Value
*v
, const int ready
)
3066 int a
= v
->reg
.data
.id
;
3068 if (v
->reg
.file
== FILE_GPR
) {
3069 int b
= a
+ v
->reg
.size
/ 4;
3070 for (int r
= a
; r
< b
; ++r
)
3071 score
->wr
.r
[r
] = ready
;
3073 if (v
->reg
.file
== FILE_PREDICATE
) {
3074 score
->wr
.p
[a
] = ready
;
3076 if (v
->reg
.file
== FILE_FLAGS
) {
3077 score
->wr
.c
= ready
;
3082 calculateSchedDataNVC0(const Target
*targ
, Function
*func
)
3084 SchedDataCalculator
sched(targ
);
3085 return sched
.run(func
, true, true);
3089 CodeEmitterNVC0::prepareEmission(Function
*func
)
3091 CodeEmitter::prepareEmission(func
);
3093 if (targ
->hasSWSched
)
3094 calculateSchedDataNVC0(targ
, func
);
3097 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0
*target
)
3098 : CodeEmitter(target
),
3100 writeIssueDelays(target
->hasSWSched
)
3103 codeSize
= codeSizeLimit
= 0;
3108 TargetNVC0::createCodeEmitterNVC0(Program::Type type
)
3110 CodeEmitterNVC0
*emit
= new CodeEmitterNVC0(this);
3111 emit
->setProgramType(type
);
3116 TargetNVC0::getCodeEmitter(Program::Type type
)
3118 if (chipset
>= NVISA_GK20A_CHIPSET
)
3119 return createCodeEmitterGK110(type
);
3120 return createCodeEmitterNVC0(type
);
3123 } // namespace nv50_ir