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nv50/ir: restore OP_SELP to be a regular instruction
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitAFETCH(const Instruction *);
89 void emitPFETCH(const Instruction *);
90 void emitVFETCH(const Instruction *);
91 void emitEXPORT(const Instruction *);
92 void emitOUT(const Instruction *);
93
94 void emitUADD(const Instruction *);
95 void emitFADD(const Instruction *);
96 void emitDADD(const Instruction *);
97 void emitUMUL(const Instruction *);
98 void emitFMUL(const Instruction *);
99 void emitDMUL(const Instruction *);
100 void emitIMAD(const Instruction *);
101 void emitISAD(const Instruction *);
102 void emitFMAD(const Instruction *);
103 void emitDMAD(const Instruction *);
104 void emitMADSP(const Instruction *);
105
106 void emitNOT(Instruction *);
107 void emitLogicOp(const Instruction *, uint8_t subOp);
108 void emitPOPC(const Instruction *);
109 void emitINSBF(const Instruction *);
110 void emitEXTBF(const Instruction *);
111 void emitBFIND(const Instruction *);
112 void emitPERMT(const Instruction *);
113 void emitShift(const Instruction *);
114
115 void emitSFnOp(const Instruction *, uint8_t subOp);
116
117 void emitCVT(Instruction *);
118 void emitMINMAX(const Instruction *);
119 void emitPreOp(const Instruction *);
120
121 void emitSET(const CmpInstruction *);
122 void emitSLCT(const CmpInstruction *);
123 void emitSELP(const Instruction *);
124
125 void emitTEXBAR(const Instruction *);
126 void emitTEX(const TexInstruction *);
127 void emitTEXCSAA(const TexInstruction *);
128 void emitTXQ(const TexInstruction *);
129
130 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
131
132 void emitFlow(const Instruction *);
133 void emitBAR(const Instruction *);
134
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction *);
137 void emitSULDGB(const TexInstruction *);
138 void emitSUSTGx(const TexInstruction *);
139
140 void emitVSHL(const Instruction *);
141 void emitVectorSubOp(const Instruction *);
142
143 void emitPIXLD(const Instruction *);
144
145 inline void defId(const ValueDef&, const int pos);
146 inline void defId(const Instruction *, int d, const int pos);
147 inline void srcId(const ValueRef&, const int pos);
148 inline void srcId(const ValueRef *, const int pos);
149 inline void srcId(const Instruction *, int s, const int pos);
150 inline void srcAddr32(const ValueRef&, int pos, int shr);
151
152 inline bool isLIMM(const ValueRef&, DataType ty);
153 };
154
155 // for better visibility
156 #define HEX64(h, l) 0x##h##l##ULL
157
158 #define SDATA(a) ((a).rep()->reg.data)
159 #define DDATA(a) ((a).rep()->reg.data)
160
161 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
162 {
163 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
164 }
165
166 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
167 {
168 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
169 }
170
171 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
172 {
173 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
174 code[pos / 32] |= r << (pos % 32);
175 }
176
177 void
178 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
179 {
180 const uint32_t offset = SDATA(src).offset >> shr;
181
182 code[pos / 32] |= offset << (pos % 32);
183 if (pos && (pos < 32))
184 code[1] |= offset >> (32 - pos);
185 }
186
187 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
188 {
189 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
190 }
191
192 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
193 {
194 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
195 code[pos / 32] |= r << (pos % 32);
196 }
197
198 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
199 {
200 const ImmediateValue *imm = ref.get()->asImm();
201
202 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
203 }
204
205 void
206 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
207 {
208 switch (insn->rnd) {
209 case ROUND_M: code[1] |= 1 << 23; break;
210 case ROUND_P: code[1] |= 2 << 23; break;
211 case ROUND_Z: code[1] |= 3 << 23; break;
212 default:
213 assert(insn->rnd == ROUND_N);
214 break;
215 }
216 }
217
218 void
219 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
220 {
221 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
222 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
223 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
224 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
225 }
226
227 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
228 {
229 uint8_t val;
230
231 switch (cc) {
232 case CC_LT: val = 0x1; break;
233 case CC_LTU: val = 0x9; break;
234 case CC_EQ: val = 0x2; break;
235 case CC_EQU: val = 0xa; break;
236 case CC_LE: val = 0x3; break;
237 case CC_LEU: val = 0xb; break;
238 case CC_GT: val = 0x4; break;
239 case CC_GTU: val = 0xc; break;
240 case CC_NE: val = 0x5; break;
241 case CC_NEU: val = 0xd; break;
242 case CC_GE: val = 0x6; break;
243 case CC_GEU: val = 0xe; break;
244 case CC_TR: val = 0xf; break;
245 case CC_FL: val = 0x0; break;
246
247 case CC_A: val = 0x14; break;
248 case CC_NA: val = 0x13; break;
249 case CC_S: val = 0x15; break;
250 case CC_NS: val = 0x12; break;
251 case CC_C: val = 0x16; break;
252 case CC_NC: val = 0x11; break;
253 case CC_O: val = 0x17; break;
254 case CC_NO: val = 0x10; break;
255
256 default:
257 val = 0;
258 assert(!"invalid condition code");
259 break;
260 }
261 code[pos / 32] |= val << (pos % 32);
262 }
263
264 void
265 CodeEmitterNVC0::emitPredicate(const Instruction *i)
266 {
267 if (i->predSrc >= 0) {
268 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
269 srcId(i->src(i->predSrc), 10);
270 if (i->cc == CC_NOT_P)
271 code[0] |= 0x2000; // negate
272 } else {
273 code[0] |= 0x1c00;
274 }
275 }
276
277 void
278 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
279 {
280 switch (src.getFile()) {
281 case FILE_MEMORY_GLOBAL:
282 srcAddr32(src, 26, 0);
283 break;
284 case FILE_MEMORY_LOCAL:
285 case FILE_MEMORY_SHARED:
286 setAddress24(src);
287 break;
288 default:
289 assert(src.getFile() == FILE_MEMORY_CONST);
290 setAddress16(src);
291 break;
292 }
293 }
294
295 void
296 CodeEmitterNVC0::setAddress16(const ValueRef& src)
297 {
298 Symbol *sym = src.get()->asSym();
299
300 assert(sym);
301
302 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
303 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
304 }
305
306 void
307 CodeEmitterNVC0::setAddress24(const ValueRef& src)
308 {
309 Symbol *sym = src.get()->asSym();
310
311 assert(sym);
312
313 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
314 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
315 }
316
317 void
318 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
319 {
320 const ImmediateValue *imm = i->src(s).get()->asImm();
321 uint32_t u32;
322
323 assert(imm);
324 u32 = imm->reg.data.u32;
325
326 if ((code[0] & 0xf) == 0x1) {
327 // double immediate
328 uint64_t u64 = imm->reg.data.u64;
329 assert(!(u64 & 0x00000fffffffffffULL));
330 assert(!(code[1] & 0xc000));
331 code[0] |= ((u64 >> 44) & 0x3f) << 26;
332 code[1] |= 0xc000 | (u64 >> 50);
333 } else
334 if ((code[0] & 0xf) == 0x2) {
335 // LIMM
336 code[0] |= (u32 & 0x3f) << 26;
337 code[1] |= u32 >> 6;
338 } else
339 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
340 // integer immediate
341 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
342 assert(!(code[1] & 0xc000));
343 u32 &= 0xfffff;
344 code[0] |= (u32 & 0x3f) << 26;
345 code[1] |= 0xc000 | (u32 >> 6);
346 } else {
347 // float immediate
348 assert(!(u32 & 0x00000fff));
349 assert(!(code[1] & 0xc000));
350 code[0] |= ((u32 >> 12) & 0x3f) << 26;
351 code[1] |= 0xc000 | (u32 >> 18);
352 }
353 }
354
355 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
356 {
357 const ImmediateValue *imm = ref.get()->asImm();
358
359 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
360
361 assert(s8 == imm->reg.data.s32);
362
363 code[0] |= (s8 & 0x3f) << 26;
364 code[0] |= (s8 >> 6) << 8;
365 }
366
367 void
368 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
369 {
370 code[0] = opc;
371 code[1] = opc >> 32;
372
373 emitPredicate(i);
374
375 defId(i->def(0), 14);
376
377 int s1 = 26;
378 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
379 s1 = 49;
380
381 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
382 switch (i->getSrc(s)->reg.file) {
383 case FILE_MEMORY_CONST:
384 assert(!(code[1] & 0xc000));
385 code[1] |= (s == 2) ? 0x8000 : 0x4000;
386 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
387 setAddress16(i->src(s));
388 break;
389 case FILE_IMMEDIATE:
390 assert(s == 1 ||
391 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
392 assert(!(code[1] & 0xc000));
393 setImmediate(i, s);
394 break;
395 case FILE_GPR:
396 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
397 break;
398 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
399 break;
400 default:
401 if (i->op == OP_SELP) {
402 // OP_SELP is used to implement shared+atomics on Fermi.
403 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
404 srcId(i->src(s), 49);
405 }
406 // ignore here, can be predicate or flags, but must not be address
407 break;
408 }
409 }
410 }
411
412 void
413 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
414 {
415 code[0] = opc;
416 code[1] = opc >> 32;
417
418 emitPredicate(i);
419
420 defId(i->def(0), 14);
421
422 switch (i->src(0).getFile()) {
423 case FILE_MEMORY_CONST:
424 assert(!(code[1] & 0xc000));
425 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
426 setAddress16(i->src(0));
427 break;
428 case FILE_IMMEDIATE:
429 assert(!(code[1] & 0xc000));
430 setImmediate(i, 0);
431 break;
432 case FILE_GPR:
433 srcId(i->src(0), 26);
434 break;
435 default:
436 // ignore here, can be predicate or flags, but must not be address
437 break;
438 }
439 }
440
441 void
442 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
443 {
444 code[0] = opc;
445
446 int ss2a = 0;
447 if (opc == 0x0d || opc == 0x0e)
448 ss2a = 2;
449
450 defId(i->def(0), 14);
451 srcId(i->src(0), 20);
452
453 assert(pred || (i->predSrc < 0));
454 if (pred)
455 emitPredicate(i);
456
457 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
458 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
459 assert(!(code[0] & (0x300 >> ss2a)));
460 switch (i->src(s).get()->reg.fileIndex) {
461 case 0: code[0] |= 0x100 >> ss2a; break;
462 case 1: code[0] |= 0x200 >> ss2a; break;
463 case 16: code[0] |= 0x300 >> ss2a; break;
464 default:
465 ERROR("invalid c[] space for short form\n");
466 break;
467 }
468 if (s == 1)
469 code[0] |= i->getSrc(s)->reg.data.offset << 24;
470 else
471 code[0] |= i->getSrc(s)->reg.data.offset << 6;
472 } else
473 if (i->src(s).getFile() == FILE_IMMEDIATE) {
474 assert(s == 1);
475 setImmediateS8(i->src(s));
476 } else
477 if (i->src(s).getFile() == FILE_GPR) {
478 srcId(i->src(s), (s == 1) ? 26 : 8);
479 }
480 }
481 }
482
483 void
484 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
485 {
486 if (src.getFile() == FILE_MEMORY_CONST) {
487 switch (src.get()->reg.fileIndex) {
488 case 0: code[0] |= 0x100; break;
489 case 1: code[0] |= 0x200; break;
490 case 16: code[0] |= 0x300; break;
491 default:
492 assert(!"unsupported file index for short op");
493 break;
494 }
495 srcAddr32(src, 20, 2);
496 } else {
497 srcId(src, 20);
498 assert(src.getFile() == FILE_GPR);
499 }
500 }
501
502 void
503 CodeEmitterNVC0::emitNOP(const Instruction *i)
504 {
505 code[0] = 0x000001e4;
506 code[1] = 0x40000000;
507 emitPredicate(i);
508 }
509
510 void
511 CodeEmitterNVC0::emitFMAD(const Instruction *i)
512 {
513 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
514
515 if (i->encSize == 8) {
516 if (isLIMM(i->src(1), TYPE_F32)) {
517 emitForm_A(i, HEX64(20000000, 00000002));
518 } else {
519 emitForm_A(i, HEX64(30000000, 00000000));
520
521 if (i->src(2).mod.neg())
522 code[0] |= 1 << 8;
523 }
524 roundMode_A(i);
525
526 if (neg1)
527 code[0] |= 1 << 9;
528
529 if (i->saturate)
530 code[0] |= 1 << 5;
531 if (i->ftz)
532 code[0] |= 1 << 6;
533 } else {
534 assert(!i->saturate && !i->src(2).mod.neg());
535 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
536 false);
537 if (neg1)
538 code[0] |= 1 << 4;
539 }
540 }
541
542 void
543 CodeEmitterNVC0::emitDMAD(const Instruction *i)
544 {
545 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
546
547 emitForm_A(i, HEX64(20000000, 00000001));
548
549 if (i->src(2).mod.neg())
550 code[0] |= 1 << 8;
551
552 roundMode_A(i);
553
554 if (neg1)
555 code[0] |= 1 << 9;
556
557 assert(!i->saturate);
558 assert(!i->ftz);
559 }
560
561 void
562 CodeEmitterNVC0::emitFMUL(const Instruction *i)
563 {
564 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
565
566 assert(i->postFactor >= -3 && i->postFactor <= 3);
567
568 if (i->encSize == 8) {
569 if (isLIMM(i->src(1), TYPE_F32)) {
570 assert(i->postFactor == 0); // constant folded, hopefully
571 emitForm_A(i, HEX64(30000000, 00000002));
572 } else {
573 emitForm_A(i, HEX64(58000000, 00000000));
574 roundMode_A(i);
575 code[1] |= ((i->postFactor > 0) ?
576 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
577 }
578 if (neg)
579 code[1] ^= 1 << 25; // aliases with LIMM sign bit
580
581 if (i->saturate)
582 code[0] |= 1 << 5;
583
584 if (i->dnz)
585 code[0] |= 1 << 7;
586 else
587 if (i->ftz)
588 code[0] |= 1 << 6;
589 } else {
590 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
591 emitForm_S(i, 0xa8, true);
592 }
593 }
594
595 void
596 CodeEmitterNVC0::emitDMUL(const Instruction *i)
597 {
598 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
599
600 emitForm_A(i, HEX64(50000000, 00000001));
601 roundMode_A(i);
602
603 if (neg)
604 code[0] |= 1 << 9;
605
606 assert(!i->saturate);
607 assert(!i->ftz);
608 assert(!i->dnz);
609 assert(!i->postFactor);
610 }
611
612 void
613 CodeEmitterNVC0::emitUMUL(const Instruction *i)
614 {
615 if (i->encSize == 8) {
616 if (i->src(1).getFile() == FILE_IMMEDIATE) {
617 emitForm_A(i, HEX64(10000000, 00000002));
618 } else {
619 emitForm_A(i, HEX64(50000000, 00000003));
620 }
621 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
622 code[0] |= 1 << 6;
623 if (i->sType == TYPE_S32)
624 code[0] |= 1 << 5;
625 if (i->dType == TYPE_S32)
626 code[0] |= 1 << 7;
627 } else {
628 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
629
630 if (i->sType == TYPE_S32)
631 code[0] |= 1 << 6;
632 }
633 }
634
635 void
636 CodeEmitterNVC0::emitFADD(const Instruction *i)
637 {
638 if (i->encSize == 8) {
639 if (isLIMM(i->src(1), TYPE_F32)) {
640 assert(!i->saturate);
641 emitForm_A(i, HEX64(28000000, 00000002));
642
643 code[0] |= i->src(0).mod.abs() << 7;
644 code[0] |= i->src(0).mod.neg() << 9;
645
646 if (i->src(1).mod.abs())
647 code[1] &= 0xfdffffff;
648 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
649 code[1] ^= 0x02000000;
650 } else {
651 emitForm_A(i, HEX64(50000000, 00000000));
652
653 roundMode_A(i);
654 if (i->saturate)
655 code[1] |= 1 << 17;
656
657 emitNegAbs12(i);
658 if (i->op == OP_SUB) code[0] ^= 1 << 8;
659 }
660 if (i->ftz)
661 code[0] |= 1 << 5;
662 } else {
663 assert(!i->saturate && i->op != OP_SUB &&
664 !i->src(0).mod.abs() &&
665 !i->src(1).mod.neg() && !i->src(1).mod.abs());
666
667 emitForm_S(i, 0x49, true);
668
669 if (i->src(0).mod.neg())
670 code[0] |= 1 << 7;
671 }
672 }
673
674 void
675 CodeEmitterNVC0::emitDADD(const Instruction *i)
676 {
677 assert(i->encSize == 8);
678 emitForm_A(i, HEX64(48000000, 00000001));
679 roundMode_A(i);
680 assert(!i->saturate);
681 assert(!i->ftz);
682 emitNegAbs12(i);
683 if (i->op == OP_SUB)
684 code[0] ^= 1 << 8;
685 }
686
687 void
688 CodeEmitterNVC0::emitUADD(const Instruction *i)
689 {
690 uint32_t addOp = 0;
691
692 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
693 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
694
695 if (i->src(0).mod.neg())
696 addOp |= 0x200;
697 if (i->src(1).mod.neg())
698 addOp |= 0x100;
699 if (i->op == OP_SUB) {
700 addOp ^= 0x100;
701 assert(addOp != 0x300); // would be add-plus-one
702 }
703
704 if (i->encSize == 8) {
705 if (isLIMM(i->src(1), TYPE_U32)) {
706 emitForm_A(i, HEX64(08000000, 00000002));
707 if (i->defExists(1))
708 code[1] |= 1 << 26; // write carry
709 } else {
710 emitForm_A(i, HEX64(48000000, 00000003));
711 if (i->defExists(1))
712 code[1] |= 1 << 16; // write carry
713 }
714 code[0] |= addOp;
715
716 if (i->saturate)
717 code[0] |= 1 << 5;
718 if (i->flagsSrc >= 0) // add carry
719 code[0] |= 1 << 6;
720 } else {
721 assert(!(addOp & 0x100));
722 emitForm_S(i, (addOp >> 3) |
723 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
724 }
725 }
726
727 // TODO: shl-add
728 void
729 CodeEmitterNVC0::emitIMAD(const Instruction *i)
730 {
731 assert(i->encSize == 8);
732 emitForm_A(i, HEX64(20000000, 00000003));
733
734 if (isSignedType(i->dType))
735 code[0] |= 1 << 7;
736 if (isSignedType(i->sType))
737 code[0] |= 1 << 5;
738
739 code[1] |= i->saturate << 24;
740
741 if (i->flagsDef >= 0) code[1] |= 1 << 16;
742 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
743
744 if (i->src(2).mod.neg()) code[0] |= 0x10;
745 if (i->src(1).mod.neg() ^
746 i->src(0).mod.neg()) code[0] |= 0x20;
747
748 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
749 code[0] |= 1 << 6;
750 }
751
752 void
753 CodeEmitterNVC0::emitMADSP(const Instruction *i)
754 {
755 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
756
757 emitForm_A(i, HEX64(00000000, 00000003));
758
759 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
760 code[1] |= 0x01800000;
761 } else {
762 code[0] |= (i->subOp & 0x00f) << 7;
763 code[0] |= (i->subOp & 0x0f0) << 1;
764 code[0] |= (i->subOp & 0x100) >> 3;
765 code[0] |= (i->subOp & 0x200) >> 2;
766 code[1] |= (i->subOp & 0xc00) << 13;
767 }
768
769 if (i->flagsDef >= 0)
770 code[1] |= 1 << 16;
771 }
772
773 void
774 CodeEmitterNVC0::emitISAD(const Instruction *i)
775 {
776 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
777 assert(i->encSize == 8);
778
779 emitForm_A(i, HEX64(38000000, 00000003));
780
781 if (i->dType == TYPE_S32)
782 code[0] |= 1 << 5;
783 }
784
785 void
786 CodeEmitterNVC0::emitNOT(Instruction *i)
787 {
788 assert(i->encSize == 8);
789 i->setSrc(1, i->src(0));
790 emitForm_A(i, HEX64(68000000, 000001c3));
791 }
792
793 void
794 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
795 {
796 if (i->def(0).getFile() == FILE_PREDICATE) {
797 code[0] = 0x00000004 | (subOp << 30);
798 code[1] = 0x0c000000;
799
800 emitPredicate(i);
801
802 defId(i->def(0), 17);
803 srcId(i->src(0), 20);
804 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
805 srcId(i->src(1), 26);
806 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
807
808 if (i->defExists(1)) {
809 defId(i->def(1), 14);
810 } else {
811 code[0] |= 7 << 14;
812 }
813 // (a OP b) OP c
814 if (i->predSrc != 2 && i->srcExists(2)) {
815 code[1] |= subOp << 21;
816 srcId(i->src(2), 17);
817 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
818 } else {
819 code[1] |= 0x000e0000;
820 }
821 } else
822 if (i->encSize == 8) {
823 if (isLIMM(i->src(1), TYPE_U32)) {
824 emitForm_A(i, HEX64(38000000, 00000002));
825
826 if (i->flagsDef >= 0)
827 code[1] |= 1 << 26;
828 } else {
829 emitForm_A(i, HEX64(68000000, 00000003));
830
831 if (i->flagsDef >= 0)
832 code[1] |= 1 << 16;
833 }
834 code[0] |= subOp << 6;
835
836 if (i->flagsSrc >= 0) // carry
837 code[0] |= 1 << 5;
838
839 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
840 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
841 } else {
842 emitForm_S(i, (subOp << 5) |
843 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
844 }
845 }
846
847 void
848 CodeEmitterNVC0::emitPOPC(const Instruction *i)
849 {
850 emitForm_A(i, HEX64(54000000, 00000004));
851
852 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
853 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
854 }
855
856 void
857 CodeEmitterNVC0::emitINSBF(const Instruction *i)
858 {
859 emitForm_A(i, HEX64(28000000, 00000003));
860 }
861
862 void
863 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
864 {
865 emitForm_A(i, HEX64(70000000, 00000003));
866
867 if (i->dType == TYPE_S32)
868 code[0] |= 1 << 5;
869 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
870 code[0] |= 1 << 8;
871 }
872
873 void
874 CodeEmitterNVC0::emitBFIND(const Instruction *i)
875 {
876 emitForm_B(i, HEX64(78000000, 00000003));
877
878 if (i->dType == TYPE_S32)
879 code[0] |= 1 << 5;
880 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
881 code[0] |= 1 << 8;
882 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
883 code[0] |= 1 << 6;
884 }
885
886 void
887 CodeEmitterNVC0::emitPERMT(const Instruction *i)
888 {
889 emitForm_A(i, HEX64(24000000, 00000004));
890
891 code[0] |= i->subOp << 5;
892 }
893
894 void
895 CodeEmitterNVC0::emitShift(const Instruction *i)
896 {
897 if (i->op == OP_SHR) {
898 emitForm_A(i, HEX64(58000000, 00000003)
899 | (isSignedType(i->dType) ? 0x20 : 0x00));
900 } else {
901 emitForm_A(i, HEX64(60000000, 00000003));
902 }
903
904 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
905 code[0] |= 1 << 9;
906 }
907
908 void
909 CodeEmitterNVC0::emitPreOp(const Instruction *i)
910 {
911 if (i->encSize == 8) {
912 emitForm_B(i, HEX64(60000000, 00000000));
913
914 if (i->op == OP_PREEX2)
915 code[0] |= 0x20;
916
917 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
918 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
919 } else {
920 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
921 }
922 }
923
924 void
925 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
926 {
927 if (i->encSize == 8) {
928 code[0] = 0x00000000 | (subOp << 26);
929 code[1] = 0xc8000000;
930
931 emitPredicate(i);
932
933 defId(i->def(0), 14);
934 srcId(i->src(0), 20);
935
936 assert(i->src(0).getFile() == FILE_GPR);
937
938 if (i->saturate) code[0] |= 1 << 5;
939
940 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
941 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
942 } else {
943 emitForm_S(i, 0x80000008 | (subOp << 26), true);
944
945 assert(!i->src(0).mod.neg());
946 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
947 }
948 }
949
950 void
951 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
952 {
953 uint64_t op;
954
955 assert(i->encSize == 8);
956
957 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
958
959 if (i->ftz)
960 op |= 1 << 5;
961 else
962 if (!isFloatType(i->dType))
963 op |= isSignedType(i->dType) ? 0x23 : 0x03;
964 if (i->dType == TYPE_F64)
965 op |= 0x01;
966
967 emitForm_A(i, op);
968 emitNegAbs12(i);
969 }
970
971 void
972 CodeEmitterNVC0::roundMode_C(const Instruction *i)
973 {
974 switch (i->rnd) {
975 case ROUND_M: code[1] |= 1 << 17; break;
976 case ROUND_P: code[1] |= 2 << 17; break;
977 case ROUND_Z: code[1] |= 3 << 17; break;
978 case ROUND_NI: code[0] |= 1 << 7; break;
979 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
980 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
981 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
982 case ROUND_N: break;
983 default:
984 assert(!"invalid round mode");
985 break;
986 }
987 }
988
989 void
990 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
991 {
992 switch (i->rnd) {
993 case ROUND_M:
994 case ROUND_MI: code[0] |= 1 << 16; break;
995 case ROUND_P:
996 case ROUND_PI: code[0] |= 2 << 16; break;
997 case ROUND_Z:
998 case ROUND_ZI: code[0] |= 3 << 16; break;
999 default:
1000 break;
1001 }
1002 }
1003
1004 void
1005 CodeEmitterNVC0::emitCVT(Instruction *i)
1006 {
1007 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1008 DataType dType;
1009
1010 switch (i->op) {
1011 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1012 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1013 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1014 default:
1015 break;
1016 }
1017
1018 const bool sat = (i->op == OP_SAT) || i->saturate;
1019 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1020 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1021
1022 if (i->op == OP_NEG && i->dType == TYPE_U32)
1023 dType = TYPE_S32;
1024 else
1025 dType = i->dType;
1026
1027 if (i->encSize == 8) {
1028 emitForm_B(i, HEX64(10000000, 00000004));
1029
1030 roundMode_C(i);
1031
1032 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1033 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1034 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1035
1036 // for 8/16 source types, the byte/word is in subOp. word 1 is
1037 // represented as 2.
1038 if (!isFloatType(i->sType))
1039 code[1] |= i->subOp << 0x17;
1040 else
1041 code[1] |= i->subOp << 0x18;
1042
1043 if (sat)
1044 code[0] |= 0x20;
1045 if (abs)
1046 code[0] |= 1 << 6;
1047 if (neg && i->op != OP_ABS)
1048 code[0] |= 1 << 8;
1049
1050 if (i->ftz)
1051 code[1] |= 1 << 23;
1052
1053 if (isSignedIntType(dType))
1054 code[0] |= 0x080;
1055 if (isSignedIntType(i->sType))
1056 code[0] |= 0x200;
1057
1058 if (isFloatType(dType)) {
1059 if (!isFloatType(i->sType))
1060 code[1] |= 0x08000000;
1061 } else {
1062 if (isFloatType(i->sType))
1063 code[1] |= 0x04000000;
1064 else
1065 code[1] |= 0x0c000000;
1066 }
1067 } else {
1068 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1069 code[0] = 0x298;
1070 } else
1071 if (isFloatType(dType)) {
1072 if (isFloatType(i->sType))
1073 code[0] = 0x098;
1074 else
1075 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1076 } else {
1077 assert(isFloatType(i->sType));
1078
1079 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1080 }
1081
1082 if (neg) code[0] |= 1 << 16;
1083 if (sat) code[0] |= 1 << 18;
1084 if (abs) code[0] |= 1 << 19;
1085
1086 roundMode_CS(i);
1087 }
1088 }
1089
1090 void
1091 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1092 {
1093 uint32_t hi;
1094 uint32_t lo = 0;
1095
1096 if (i->sType == TYPE_F64)
1097 lo = 0x1;
1098 else
1099 if (!isFloatType(i->sType))
1100 lo = 0x3;
1101
1102 if (isSignedIntType(i->sType))
1103 lo |= 0x20;
1104 if (isFloatType(i->dType)) {
1105 if (isFloatType(i->sType))
1106 lo |= 0x20;
1107 else
1108 lo |= 0x80;
1109 }
1110
1111 switch (i->op) {
1112 case OP_SET_AND: hi = 0x10000000; break;
1113 case OP_SET_OR: hi = 0x10200000; break;
1114 case OP_SET_XOR: hi = 0x10400000; break;
1115 default:
1116 hi = 0x100e0000;
1117 break;
1118 }
1119 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1120
1121 if (i->op != OP_SET)
1122 srcId(i->src(2), 32 + 17);
1123
1124 if (i->def(0).getFile() == FILE_PREDICATE) {
1125 if (i->sType == TYPE_F32)
1126 code[1] += 0x10000000;
1127 else
1128 code[1] += 0x08000000;
1129
1130 code[0] &= ~0xfc000;
1131 defId(i->def(0), 17);
1132 if (i->defExists(1))
1133 defId(i->def(1), 14);
1134 else
1135 code[0] |= 0x1c000;
1136 }
1137
1138 if (i->ftz)
1139 code[1] |= 1 << 27;
1140
1141 emitCondCode(i->setCond, 32 + 23);
1142 emitNegAbs12(i);
1143 }
1144
1145 void
1146 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1147 {
1148 uint64_t op;
1149
1150 switch (i->dType) {
1151 case TYPE_S32:
1152 op = HEX64(30000000, 00000023);
1153 break;
1154 case TYPE_U32:
1155 op = HEX64(30000000, 00000003);
1156 break;
1157 case TYPE_F32:
1158 op = HEX64(38000000, 00000000);
1159 break;
1160 default:
1161 assert(!"invalid type for SLCT");
1162 op = 0;
1163 break;
1164 }
1165 emitForm_A(i, op);
1166
1167 CondCode cc = i->setCond;
1168
1169 if (i->src(2).mod.neg())
1170 cc = reverseCondCode(cc);
1171
1172 emitCondCode(cc, 32 + 23);
1173
1174 if (i->ftz)
1175 code[0] |= 1 << 5;
1176 }
1177
1178 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1179 {
1180 emitForm_A(i, HEX64(20000000, 00000004));
1181
1182 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1183 code[1] |= 1 << 20;
1184 }
1185
1186 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1187 {
1188 code[0] = 0x00000006 | (i->subOp << 26);
1189 code[1] = 0xf0000000;
1190 emitPredicate(i);
1191 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1192 }
1193
1194 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1195 {
1196 code[0] = 0x00000086;
1197 code[1] = 0xd0000000;
1198
1199 code[1] |= i->tex.r;
1200 code[1] |= i->tex.s << 8;
1201
1202 if (i->tex.liveOnly)
1203 code[0] |= 1 << 9;
1204
1205 defId(i->def(0), 14);
1206 srcId(i->src(0), 20);
1207 }
1208
1209 static inline bool
1210 isNextIndependentTex(const TexInstruction *i)
1211 {
1212 if (!i->next || !isTextureOp(i->next->op))
1213 return false;
1214 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1215 return false;
1216 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1217 }
1218
1219 void
1220 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1221 {
1222 code[0] = 0x00000006;
1223
1224 if (isNextIndependentTex(i))
1225 code[0] |= 0x080; // t mode
1226 else
1227 code[0] |= 0x100; // p mode
1228
1229 if (i->tex.liveOnly)
1230 code[0] |= 1 << 9;
1231
1232 switch (i->op) {
1233 case OP_TEX: code[1] = 0x80000000; break;
1234 case OP_TXB: code[1] = 0x84000000; break;
1235 case OP_TXL: code[1] = 0x86000000; break;
1236 case OP_TXF: code[1] = 0x90000000; break;
1237 case OP_TXG: code[1] = 0xa0000000; break;
1238 case OP_TXLQ: code[1] = 0xb0000000; break;
1239 case OP_TXD: code[1] = 0xe0000000; break;
1240 default:
1241 assert(!"invalid texture op");
1242 break;
1243 }
1244 if (i->op == OP_TXF) {
1245 if (!i->tex.levelZero)
1246 code[1] |= 0x02000000;
1247 } else
1248 if (i->tex.levelZero) {
1249 code[1] |= 0x02000000;
1250 }
1251
1252 if (i->op != OP_TXD && i->tex.derivAll)
1253 code[1] |= 1 << 13;
1254
1255 defId(i->def(0), 14);
1256 srcId(i->src(0), 20);
1257
1258 emitPredicate(i);
1259
1260 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1261
1262 code[1] |= i->tex.mask << 14;
1263
1264 code[1] |= i->tex.r;
1265 code[1] |= i->tex.s << 8;
1266 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1267 code[1] |= 1 << 18; // in 1st source (with array index)
1268
1269 // texture target:
1270 code[1] |= (i->tex.target.getDim() - 1) << 20;
1271 if (i->tex.target.isCube())
1272 code[1] += 2 << 20;
1273 if (i->tex.target.isArray())
1274 code[1] |= 1 << 19;
1275 if (i->tex.target.isShadow())
1276 code[1] |= 1 << 24;
1277
1278 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1279
1280 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1281 // lzero
1282 if (i->op == OP_TXL)
1283 code[1] &= ~(1 << 26);
1284 else
1285 if (i->op == OP_TXF)
1286 code[1] &= ~(1 << 25);
1287 }
1288 if (i->tex.target == TEX_TARGET_2D_MS ||
1289 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1290 code[1] |= 1 << 23;
1291
1292 if (i->tex.useOffsets == 1)
1293 code[1] |= 1 << 22;
1294 if (i->tex.useOffsets == 4)
1295 code[1] |= 1 << 23;
1296
1297 srcId(i, src1, 26);
1298 }
1299
1300 void
1301 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1302 {
1303 code[0] = 0x00000086;
1304 code[1] = 0xc0000000;
1305
1306 switch (i->tex.query) {
1307 case TXQ_DIMS: code[1] |= 0 << 22; break;
1308 case TXQ_TYPE: code[1] |= 1 << 22; break;
1309 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1310 case TXQ_FILTER: code[1] |= 3 << 22; break;
1311 case TXQ_LOD: code[1] |= 4 << 22; break;
1312 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1313 default:
1314 assert(!"invalid texture query");
1315 break;
1316 }
1317
1318 code[1] |= i->tex.mask << 14;
1319
1320 code[1] |= i->tex.r;
1321 code[1] |= i->tex.s << 8;
1322 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1323 code[1] |= 1 << 18;
1324
1325 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1326
1327 defId(i->def(0), 14);
1328 srcId(i->src(0), 20);
1329 srcId(i, src1, 26);
1330
1331 emitPredicate(i);
1332 }
1333
1334 void
1335 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1336 {
1337 code[0] = 0x00000000 | (laneMask << 6);
1338 code[1] = 0x48000000 | qOp;
1339
1340 defId(i->def(0), 14);
1341 srcId(i->src(0), 20);
1342 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1343
1344 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1345 code[0] |= 1 << 9; // dall
1346
1347 emitPredicate(i);
1348 }
1349
1350 void
1351 CodeEmitterNVC0::emitFlow(const Instruction *i)
1352 {
1353 const FlowInstruction *f = i->asFlow();
1354
1355 unsigned mask; // bit 0: predicate, bit 1: target
1356
1357 code[0] = 0x00000007;
1358
1359 switch (i->op) {
1360 case OP_BRA:
1361 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1362 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1363 code[0] |= 0x4000;
1364 mask = 3;
1365 break;
1366 case OP_CALL:
1367 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1368 if (f->indirect)
1369 code[0] |= 0x4000; // indirect calls always use c[] source
1370 mask = 2;
1371 break;
1372
1373 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1374 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1375 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1376 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1377 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1378
1379 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1380 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1381 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1382 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1383
1384 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1385 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1386 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1387 default:
1388 assert(!"invalid flow operation");
1389 return;
1390 }
1391
1392 if (mask & 1) {
1393 emitPredicate(i);
1394 if (i->flagsSrc < 0)
1395 code[0] |= 0x1e0;
1396 }
1397
1398 if (!f)
1399 return;
1400
1401 if (f->allWarp)
1402 code[0] |= 1 << 15;
1403 if (f->limit)
1404 code[0] |= 1 << 16;
1405
1406 if (f->indirect) {
1407 if (code[0] & 0x4000) {
1408 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1409 setAddress16(i->src(0));
1410 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1411 if (f->op == OP_BRA)
1412 srcId(f->src(0).getIndirect(0), 20);
1413 } else {
1414 srcId(f, 0, 20);
1415 }
1416 }
1417
1418 if (f->op == OP_CALL) {
1419 if (f->indirect) {
1420 // nothing
1421 } else
1422 if (f->builtin) {
1423 assert(f->absolute);
1424 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1425 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1426 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1427 } else {
1428 assert(!f->absolute);
1429 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1430 code[0] |= (pcRel & 0x3f) << 26;
1431 code[1] |= (pcRel >> 6) & 0x3ffff;
1432 }
1433 } else
1434 if (mask & 2) {
1435 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1436 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1437 pcRel += 8;
1438 // currently we don't want absolute branches
1439 assert(!f->absolute);
1440 code[0] |= (pcRel & 0x3f) << 26;
1441 code[1] |= (pcRel >> 6) & 0x3ffff;
1442 }
1443 }
1444
1445 void
1446 CodeEmitterNVC0::emitBAR(const Instruction *i)
1447 {
1448 Value *rDef = NULL, *pDef = NULL;
1449
1450 switch (i->subOp) {
1451 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1452 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1453 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1454 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1455 default:
1456 code[0] = 0x04;
1457 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1458 break;
1459 }
1460 code[1] = 0x50000000;
1461
1462 code[0] |= 63 << 14;
1463 code[1] |= 7 << 21;
1464
1465 emitPredicate(i);
1466
1467 // barrier id
1468 if (i->src(0).getFile() == FILE_GPR) {
1469 srcId(i->src(0), 20);
1470 } else {
1471 ImmediateValue *imm = i->getSrc(0)->asImm();
1472 assert(imm);
1473 code[0] |= imm->reg.data.u32 << 20;
1474 code[1] |= 0x8000;
1475 }
1476
1477 // thread count
1478 if (i->src(1).getFile() == FILE_GPR) {
1479 srcId(i->src(1), 26);
1480 } else {
1481 ImmediateValue *imm = i->getSrc(1)->asImm();
1482 assert(imm);
1483 code[0] |= imm->reg.data.u32 << 26;
1484 code[1] |= imm->reg.data.u32 >> 6;
1485 code[1] |= 0x4000;
1486 }
1487
1488 if (i->srcExists(2) && (i->predSrc != 2)) {
1489 srcId(i->src(2), 32 + 17);
1490 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1491 code[1] |= 1 << 20;
1492 } else {
1493 code[1] |= 7 << 17;
1494 }
1495
1496 if (i->defExists(0)) {
1497 if (i->def(0).getFile() == FILE_GPR)
1498 rDef = i->getDef(0);
1499 else
1500 pDef = i->getDef(0);
1501
1502 if (i->defExists(1)) {
1503 if (i->def(1).getFile() == FILE_GPR)
1504 rDef = i->getDef(1);
1505 else
1506 pDef = i->getDef(1);
1507 }
1508 }
1509 if (rDef) {
1510 code[0] &= ~(63 << 14);
1511 defId(rDef, 14);
1512 }
1513 if (pDef) {
1514 code[1] &= ~(7 << 21);
1515 defId(pDef, 32 + 21);
1516 }
1517 }
1518
1519 void
1520 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1521 {
1522 code[0] = 0x00000006;
1523 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1524
1525 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1526 code[0] |= 0x200;
1527
1528 emitPredicate(i);
1529
1530 defId(i->def(0), 14);
1531 srcId(i->src(0).getIndirect(0), 20);
1532 }
1533
1534 void
1535 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1536 {
1537 uint32_t prim = i->src(0).get()->reg.data.u32;
1538
1539 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1540 code[1] = 0x00000000 | (prim >> 6);
1541
1542 emitPredicate(i);
1543
1544 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1545
1546 defId(i->def(0), 14);
1547 srcId(i, src1, 20);
1548 }
1549
1550 void
1551 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1552 {
1553 code[0] = 0x00000006;
1554 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1555
1556 if (i->perPatch)
1557 code[0] |= 0x100;
1558 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1559 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1560
1561 emitPredicate(i);
1562
1563 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1564
1565 defId(i->def(0), 14);
1566 srcId(i->src(0).getIndirect(0), 20);
1567 srcId(i->src(0).getIndirect(1), 26); // vertex address
1568 }
1569
1570 void
1571 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1572 {
1573 unsigned int size = typeSizeof(i->dType);
1574
1575 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1576 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1577
1578 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1579
1580 if (i->perPatch)
1581 code[0] |= 0x100;
1582
1583 emitPredicate(i);
1584
1585 assert(i->src(1).getFile() == FILE_GPR);
1586
1587 srcId(i->src(0).getIndirect(0), 20);
1588 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1589 srcId(i->src(1), 26);
1590 }
1591
1592 void
1593 CodeEmitterNVC0::emitOUT(const Instruction *i)
1594 {
1595 code[0] = 0x00000006;
1596 code[1] = 0x1c000000;
1597
1598 emitPredicate(i);
1599
1600 defId(i->def(0), 14); // new secret address
1601 srcId(i->src(0), 20); // old secret address, should be 0 initially
1602
1603 assert(i->src(0).getFile() == FILE_GPR);
1604
1605 if (i->op == OP_EMIT)
1606 code[0] |= 1 << 5;
1607 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1608 code[0] |= 1 << 6;
1609
1610 // vertex stream
1611 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1612 unsigned int stream = SDATA(i->src(1)).u32;
1613 assert(stream < 4);
1614 if (stream) {
1615 code[1] |= 0xc000;
1616 code[0] |= stream << 26;
1617 } else {
1618 srcId(NULL, 26);
1619 }
1620 } else {
1621 srcId(i->src(1), 26);
1622 }
1623 }
1624
1625 void
1626 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1627 {
1628 if (i->encSize == 8) {
1629 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1630 } else {
1631 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1632 code[0] |= 0x80;
1633 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1634 }
1635 }
1636
1637 static void
1638 interpApply(const InterpEntry *entry, uint32_t *code,
1639 bool force_persample_interp, bool flatshade)
1640 {
1641 int ipa = entry->ipa;
1642 int reg = entry->reg;
1643 int loc = entry->loc;
1644
1645 if (flatshade &&
1646 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1647 ipa = NV50_IR_INTERP_FLAT;
1648 reg = 0x3f;
1649 } else if (force_persample_interp &&
1650 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1651 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1652 ipa |= NV50_IR_INTERP_CENTROID;
1653 }
1654 code[loc + 0] &= ~(0xf << 6);
1655 code[loc + 0] |= ipa << 6;
1656 code[loc + 0] &= ~(0x3f << 26);
1657 code[loc + 0] |= reg << 26;
1658 }
1659
1660 void
1661 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1662 {
1663 const uint32_t base = i->getSrc(0)->reg.data.offset;
1664
1665 if (i->encSize == 8) {
1666 code[0] = 0x00000000;
1667 code[1] = 0xc0000000 | (base & 0xffff);
1668
1669 if (i->saturate)
1670 code[0] |= 1 << 5;
1671
1672 if (i->op == OP_PINTERP) {
1673 srcId(i->src(1), 26);
1674 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1675 } else {
1676 code[0] |= 0x3f << 26;
1677 addInterp(i->ipa, 0x3f, interpApply);
1678 }
1679
1680 srcId(i->src(0).getIndirect(0), 20);
1681 } else {
1682 assert(i->op == OP_PINTERP);
1683 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1684 srcId(i->src(1), 20);
1685 }
1686 emitInterpMode(i);
1687
1688 emitPredicate(i);
1689 defId(i->def(0), 14);
1690
1691 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1692 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1693 else
1694 code[1] |= 0x3f << 17;
1695 }
1696
1697 void
1698 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1699 {
1700 uint8_t val;
1701
1702 switch (ty) {
1703 case TYPE_U8:
1704 val = 0x00;
1705 break;
1706 case TYPE_S8:
1707 val = 0x20;
1708 break;
1709 case TYPE_F16:
1710 case TYPE_U16:
1711 val = 0x40;
1712 break;
1713 case TYPE_S16:
1714 val = 0x60;
1715 break;
1716 case TYPE_F32:
1717 case TYPE_U32:
1718 case TYPE_S32:
1719 val = 0x80;
1720 break;
1721 case TYPE_F64:
1722 case TYPE_U64:
1723 case TYPE_S64:
1724 val = 0xa0;
1725 break;
1726 case TYPE_B128:
1727 val = 0xc0;
1728 break;
1729 default:
1730 val = 0x80;
1731 assert(!"invalid type");
1732 break;
1733 }
1734 code[0] |= val;
1735 }
1736
1737 void
1738 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1739 {
1740 uint32_t val;
1741
1742 switch (c) {
1743 case CACHE_CA:
1744 // case CACHE_WB:
1745 val = 0x000;
1746 break;
1747 case CACHE_CG:
1748 val = 0x100;
1749 break;
1750 case CACHE_CS:
1751 val = 0x200;
1752 break;
1753 case CACHE_CV:
1754 // case CACHE_WT:
1755 val = 0x300;
1756 break;
1757 default:
1758 val = 0;
1759 assert(!"invalid caching mode");
1760 break;
1761 }
1762 code[0] |= val;
1763 }
1764
1765 static inline bool
1766 uses64bitAddress(const Instruction *ldst)
1767 {
1768 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1769 ldst->src(0).isIndirect(0) &&
1770 ldst->getIndirect(0, 0)->reg.size == 8;
1771 }
1772
1773 void
1774 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1775 {
1776 uint32_t opc;
1777
1778 switch (i->src(0).getFile()) {
1779 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1780 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1781 case FILE_MEMORY_SHARED:
1782 opc = 0xc8000000;
1783 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED)
1784 opc |= (1 << 26);
1785 else
1786 opc |= (1 << 24);
1787 break;
1788 default:
1789 assert(!"invalid memory file");
1790 opc = 0;
1791 break;
1792 }
1793 code[0] = 0x00000005;
1794 code[1] = opc;
1795
1796 setAddressByFile(i->src(0));
1797 srcId(i->src(1), 14);
1798 srcId(i->src(0).getIndirect(0), 20);
1799 if (uses64bitAddress(i))
1800 code[1] |= 1 << 26;
1801
1802 emitPredicate(i);
1803
1804 emitLoadStoreType(i->dType);
1805 emitCachingMode(i->cache);
1806 }
1807
1808 void
1809 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1810 {
1811 uint32_t opc;
1812
1813 code[0] = 0x00000005;
1814
1815 switch (i->src(0).getFile()) {
1816 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1817 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1818 case FILE_MEMORY_SHARED:
1819 opc = 0xc0000000;
1820 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED)
1821 opc |= (1 << 26);
1822 else
1823 opc |= (1 << 24);
1824 break;
1825 case FILE_MEMORY_CONST:
1826 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1827 emitMOV(i); // not sure if this is any better
1828 return;
1829 }
1830 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1831 code[0] = 0x00000006 | (i->subOp << 8);
1832 break;
1833 default:
1834 assert(!"invalid memory file");
1835 opc = 0;
1836 break;
1837 }
1838 code[1] = opc;
1839
1840 defId(i->def(0), 14);
1841
1842 setAddressByFile(i->src(0));
1843 srcId(i->src(0).getIndirect(0), 20);
1844 if (uses64bitAddress(i))
1845 code[1] |= 1 << 26;
1846
1847 emitPredicate(i);
1848
1849 emitLoadStoreType(i->dType);
1850 emitCachingMode(i->cache);
1851 }
1852
1853 uint8_t
1854 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1855 {
1856 switch (SDATA(ref).sv.sv) {
1857 case SV_LANEID: return 0x00;
1858 case SV_PHYSID: return 0x03;
1859 case SV_VERTEX_COUNT: return 0x10;
1860 case SV_INVOCATION_ID: return 0x11;
1861 case SV_YDIR: return 0x12;
1862 case SV_THREAD_KILL: return 0x13;
1863 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1864 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1865 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1866 case SV_GRIDID: return 0x2c;
1867 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1868 case SV_LBASE: return 0x34;
1869 case SV_SBASE: return 0x30;
1870 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1871 default:
1872 assert(!"no sreg for system value");
1873 return 0;
1874 }
1875 }
1876
1877 void
1878 CodeEmitterNVC0::emitMOV(const Instruction *i)
1879 {
1880 if (i->def(0).getFile() == FILE_PREDICATE) {
1881 if (i->src(0).getFile() == FILE_GPR) {
1882 code[0] = 0xfc01c003;
1883 code[1] = 0x1a8e0000;
1884 srcId(i->src(0), 20);
1885 } else {
1886 code[0] = 0x0001c004;
1887 code[1] = 0x0c0e0000;
1888 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1889 code[0] |= 7 << 20;
1890 if (!i->getSrc(0)->reg.data.u32)
1891 code[0] |= 1 << 23;
1892 } else {
1893 srcId(i->src(0), 20);
1894 }
1895 }
1896 defId(i->def(0), 17);
1897 emitPredicate(i);
1898 } else
1899 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1900 uint8_t sr = getSRegEncoding(i->src(0));
1901
1902 if (i->encSize == 8) {
1903 code[0] = 0x00000004 | (sr << 26);
1904 code[1] = 0x2c000000;
1905 } else {
1906 code[0] = 0x40000008 | (sr << 20);
1907 }
1908 defId(i->def(0), 14);
1909
1910 emitPredicate(i);
1911 } else
1912 if (i->encSize == 8) {
1913 uint64_t opc;
1914
1915 if (i->src(0).getFile() == FILE_IMMEDIATE)
1916 opc = HEX64(18000000, 000001e2);
1917 else
1918 if (i->src(0).getFile() == FILE_PREDICATE)
1919 opc = HEX64(080e0000, 1c000004);
1920 else
1921 opc = HEX64(28000000, 00000004);
1922
1923 opc |= i->lanes << 5;
1924
1925 emitForm_B(i, opc);
1926 } else {
1927 uint32_t imm;
1928
1929 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1930 imm = SDATA(i->src(0)).u32;
1931 if (imm & 0xfff00000) {
1932 assert(!(imm & 0x000fffff));
1933 code[0] = 0x00000318 | imm;
1934 } else {
1935 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1936 code[0] = 0x00000118 | (imm << 20);
1937 }
1938 } else {
1939 code[0] = 0x0028;
1940 emitShortSrc2(i->src(0));
1941 }
1942 defId(i->def(0), 14);
1943
1944 emitPredicate(i);
1945 }
1946 }
1947
1948 void
1949 CodeEmitterNVC0::emitATOM(const Instruction *i)
1950 {
1951 const bool hasDst = i->defExists(0);
1952 const bool casOrExch =
1953 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1954 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1955
1956 if (i->dType == TYPE_U64) {
1957 switch (i->subOp) {
1958 case NV50_IR_SUBOP_ATOM_ADD:
1959 code[0] = 0x205;
1960 if (hasDst)
1961 code[1] = 0x507e0000;
1962 else
1963 code[1] = 0x10000000;
1964 break;
1965 case NV50_IR_SUBOP_ATOM_EXCH:
1966 code[0] = 0x305;
1967 code[1] = 0x507e0000;
1968 break;
1969 case NV50_IR_SUBOP_ATOM_CAS:
1970 code[0] = 0x325;
1971 code[1] = 0x50000000;
1972 break;
1973 default:
1974 assert(!"invalid u64 red op");
1975 break;
1976 }
1977 } else
1978 if (i->dType == TYPE_U32) {
1979 switch (i->subOp) {
1980 case NV50_IR_SUBOP_ATOM_EXCH:
1981 code[0] = 0x105;
1982 code[1] = 0x507e0000;
1983 break;
1984 case NV50_IR_SUBOP_ATOM_CAS:
1985 code[0] = 0x125;
1986 code[1] = 0x50000000;
1987 break;
1988 default:
1989 code[0] = 0x5 | (i->subOp << 5);
1990 if (hasDst)
1991 code[1] = 0x507e0000;
1992 else
1993 code[1] = 0x10000000;
1994 break;
1995 }
1996 } else
1997 if (i->dType == TYPE_S32) {
1998 assert(i->subOp <= 2);
1999 code[0] = 0x205 | (i->subOp << 5);
2000 if (hasDst)
2001 code[1] = 0x587e0000;
2002 else
2003 code[1] = 0x18000000;
2004 } else
2005 if (i->dType == TYPE_F32) {
2006 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2007 code[0] = 0x205;
2008 if (hasDst)
2009 code[1] = 0x687e0000;
2010 else
2011 code[1] = 0x28000000;
2012 }
2013
2014 emitPredicate(i);
2015
2016 srcId(i->src(1), 14);
2017
2018 if (hasDst)
2019 defId(i->def(0), 32 + 11);
2020 else
2021 if (casOrExch)
2022 code[1] |= 63 << 11;
2023
2024 if (hasDst || casOrExch) {
2025 const int32_t offset = SDATA(i->src(0)).offset;
2026 assert(offset < 0x80000 && offset >= -0x80000);
2027 code[0] |= offset << 26;
2028 code[1] |= (offset & 0x1ffc0) >> 6;
2029 code[1] |= (offset & 0xe0000) << 6;
2030 } else {
2031 srcAddr32(i->src(0), 26, 0);
2032 }
2033 if (i->getIndirect(0, 0)) {
2034 srcId(i->getIndirect(0, 0), 20);
2035 if (i->getIndirect(0, 0)->reg.size == 8)
2036 code[1] |= 1 << 26;
2037 } else {
2038 code[0] |= 63 << 20;
2039 }
2040
2041 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2042 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2043 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2044 }
2045 }
2046
2047 void
2048 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2049 {
2050 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2051 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2052 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2053 default:
2054 code[0] = 0x45;
2055 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2056 break;
2057 }
2058 code[1] = 0xe0000000;
2059
2060 emitPredicate(i);
2061 }
2062
2063 void
2064 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2065 {
2066 code[0] = 0x00000005 | (i->subOp << 5);
2067
2068 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2069 code[1] = 0x98000000;
2070 srcAddr32(i->src(0), 28, 2);
2071 } else {
2072 code[1] = 0xd0000000;
2073 setAddress24(i->src(0));
2074 }
2075 if (uses64bitAddress(i))
2076 code[1] |= 1 << 26;
2077 srcId(i->src(0).getIndirect(0), 20);
2078
2079 emitPredicate(i);
2080
2081 defId(i, 0, 14);
2082 }
2083
2084 void
2085 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2086 {
2087 uint8_t m;
2088 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2089 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2090 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2091 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2092 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2093 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2094 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2095 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2096 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2097 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2098 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2099 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2100 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2101 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2102 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2103 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2104 default:
2105 return;
2106 }
2107 code[0] |= m << 5;
2108 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2109 code[1] |= 1 << 16;
2110 }
2111
2112 void
2113 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2114 {
2115 ImmediateValue *imm = NULL;
2116 uint64_t opc;
2117
2118 if (i->srcExists(2)) {
2119 imm = i->getSrc(2)->asImm();
2120 if (imm)
2121 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2122 }
2123
2124 switch (i->op) {
2125 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2126 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2127 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2128 default:
2129 assert(0);
2130 return;
2131 }
2132 emitForm_A(i, opc);
2133
2134 if (i->op == OP_SUCLAMP) {
2135 if (i->dType == TYPE_S32)
2136 code[0] |= 1 << 9;
2137 emitSUCLAMPMode(i->subOp);
2138 }
2139
2140 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2141 code[1] |= 1 << 16;
2142
2143 if (i->op != OP_SUEAU) {
2144 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2145 code[0] |= 63 << 14;
2146 code[1] |= i->getDef(0)->reg.data.id << 23;
2147 } else
2148 if (i->defExists(1)) { // r, p
2149 assert(i->def(1).getFile() == FILE_PREDICATE);
2150 code[1] |= i->getDef(1)->reg.data.id << 23;
2151 } else { // r, #
2152 code[1] |= 7 << 23;
2153 }
2154 }
2155 if (imm) {
2156 assert(i->op == OP_SUCLAMP);
2157 i->setSrc(2, imm);
2158 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2159 }
2160 }
2161
2162 void
2163 CodeEmitterNVC0::emitSUGType(DataType ty)
2164 {
2165 switch (ty) {
2166 case TYPE_S32: code[1] |= 1 << 13; break;
2167 case TYPE_U8: code[1] |= 2 << 13; break;
2168 case TYPE_S8: code[1] |= 3 << 13; break;
2169 default:
2170 assert(ty == TYPE_U32);
2171 break;
2172 }
2173 }
2174
2175 void
2176 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2177 {
2178 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2179
2180 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2181 assert(offset == (offset & 0xfffc));
2182
2183 code[1] |= 1 << 21;
2184 code[0] |= offset << 24;
2185 code[1] |= offset >> 8;
2186 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2187 }
2188
2189 void
2190 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2191 {
2192 if (!i->srcExists(s) || (i->predSrc == s)) {
2193 code[1] |= 0x7 << 17;
2194 } else {
2195 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2196 code[1] |= 1 << 20;
2197 srcId(i->src(s), 32 + 17);
2198 }
2199 }
2200
2201 void
2202 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2203 {
2204 code[0] = 0x5;
2205 code[1] = 0xd4000000 | (i->subOp << 15);
2206
2207 emitLoadStoreType(i->dType);
2208 emitSUGType(i->sType);
2209 emitCachingMode(i->cache);
2210
2211 emitPredicate(i);
2212 defId(i->def(0), 14); // destination
2213 srcId(i->src(0), 20); // address
2214 // format
2215 if (i->src(1).getFile() == FILE_GPR)
2216 srcId(i->src(1), 26);
2217 else
2218 setSUConst16(i, 1);
2219 setSUPred(i, 2);
2220 }
2221
2222 void
2223 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2224 {
2225 code[0] = 0x5;
2226 code[1] = 0xdc000000 | (i->subOp << 15);
2227
2228 if (i->op == OP_SUSTP)
2229 code[1] |= i->tex.mask << 22;
2230 else
2231 emitLoadStoreType(i->dType);
2232 emitSUGType(i->sType);
2233 emitCachingMode(i->cache);
2234
2235 emitPredicate(i);
2236 srcId(i->src(0), 20); // address
2237 // format
2238 if (i->src(1).getFile() == FILE_GPR)
2239 srcId(i->src(1), 26);
2240 else
2241 setSUConst16(i, 1);
2242 srcId(i->src(3), 14); // values
2243 setSUPred(i, 2);
2244 }
2245
2246 void
2247 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2248 {
2249 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2250 case 0:
2251 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2252 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2253 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2254 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2255 break;
2256 case 1:
2257 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2258 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2259 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2260 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2261 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2262 code[1] |= (i->mask & 0x3) << 2;
2263 break;
2264 case 2:
2265 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2266 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2267 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2268 code[1] |= (i->mask & 0x3) << 2;
2269 code[1] |= (i->mask & 0xc) << 21;
2270 break;
2271 default:
2272 assert(0);
2273 break;
2274 }
2275 }
2276
2277 void
2278 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2279 {
2280 uint64_t opc = 0x4;
2281
2282 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2283 case 0: opc |= 0xe8ULL << 56; break;
2284 case 1: opc |= 0xb4ULL << 56; break;
2285 case 2: opc |= 0x94ULL << 56; break;
2286 default:
2287 assert(0);
2288 break;
2289 }
2290 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2291 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2292 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2293 } else {
2294 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2295 if (isSignedType(i->sType)) opc |= 1 << 6;
2296 }
2297 emitForm_A(i, opc);
2298 emitVectorSubOp(i);
2299
2300 if (i->saturate)
2301 code[0] |= 1 << 9;
2302 if (i->flagsDef >= 0)
2303 code[1] |= 1 << 16;
2304 }
2305
2306 void
2307 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2308 {
2309 assert(i->encSize == 8);
2310 emitForm_A(i, HEX64(10000000, 00000006));
2311 code[0] |= i->subOp << 5;
2312 code[1] |= 0x00e00000;
2313 }
2314
2315 bool
2316 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2317 {
2318 unsigned int size = insn->encSize;
2319
2320 if (writeIssueDelays && !(codeSize & 0x3f))
2321 size += 8;
2322
2323 if (!insn->encSize) {
2324 ERROR("skipping unencodable instruction: "); insn->print();
2325 return false;
2326 } else
2327 if (codeSize + size > codeSizeLimit) {
2328 ERROR("code emitter output buffer too small\n");
2329 return false;
2330 }
2331
2332 if (writeIssueDelays) {
2333 if (!(codeSize & 0x3f)) {
2334 code[0] = 0x00000007; // cf issue delay "instruction"
2335 code[1] = 0x20000000;
2336 code += 2;
2337 codeSize += 8;
2338 }
2339 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2340 uint32_t *data = code - (id * 2 + 2);
2341 if (id <= 2) {
2342 data[0] |= insn->sched << (id * 8 + 4);
2343 } else
2344 if (id == 3) {
2345 data[0] |= insn->sched << 28;
2346 data[1] |= insn->sched >> 4;
2347 } else {
2348 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2349 }
2350 }
2351
2352 // assert that instructions with multiple defs don't corrupt registers
2353 for (int d = 0; insn->defExists(d); ++d)
2354 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2355
2356 switch (insn->op) {
2357 case OP_MOV:
2358 case OP_RDSV:
2359 emitMOV(insn);
2360 break;
2361 case OP_NOP:
2362 break;
2363 case OP_LOAD:
2364 emitLOAD(insn);
2365 break;
2366 case OP_STORE:
2367 emitSTORE(insn);
2368 break;
2369 case OP_LINTERP:
2370 case OP_PINTERP:
2371 emitINTERP(insn);
2372 break;
2373 case OP_VFETCH:
2374 emitVFETCH(insn);
2375 break;
2376 case OP_EXPORT:
2377 emitEXPORT(insn);
2378 break;
2379 case OP_PFETCH:
2380 emitPFETCH(insn);
2381 break;
2382 case OP_AFETCH:
2383 emitAFETCH(insn);
2384 break;
2385 case OP_EMIT:
2386 case OP_RESTART:
2387 emitOUT(insn);
2388 break;
2389 case OP_ADD:
2390 case OP_SUB:
2391 if (insn->dType == TYPE_F64)
2392 emitDADD(insn);
2393 else if (isFloatType(insn->dType))
2394 emitFADD(insn);
2395 else
2396 emitUADD(insn);
2397 break;
2398 case OP_MUL:
2399 if (insn->dType == TYPE_F64)
2400 emitDMUL(insn);
2401 else if (isFloatType(insn->dType))
2402 emitFMUL(insn);
2403 else
2404 emitUMUL(insn);
2405 break;
2406 case OP_MAD:
2407 case OP_FMA:
2408 if (insn->dType == TYPE_F64)
2409 emitDMAD(insn);
2410 else if (isFloatType(insn->dType))
2411 emitFMAD(insn);
2412 else
2413 emitIMAD(insn);
2414 break;
2415 case OP_SAD:
2416 emitISAD(insn);
2417 break;
2418 case OP_NOT:
2419 emitNOT(insn);
2420 break;
2421 case OP_AND:
2422 emitLogicOp(insn, 0);
2423 break;
2424 case OP_OR:
2425 emitLogicOp(insn, 1);
2426 break;
2427 case OP_XOR:
2428 emitLogicOp(insn, 2);
2429 break;
2430 case OP_SHL:
2431 case OP_SHR:
2432 emitShift(insn);
2433 break;
2434 case OP_SET:
2435 case OP_SET_AND:
2436 case OP_SET_OR:
2437 case OP_SET_XOR:
2438 emitSET(insn->asCmp());
2439 break;
2440 case OP_SELP:
2441 emitSELP(insn);
2442 break;
2443 case OP_SLCT:
2444 emitSLCT(insn->asCmp());
2445 break;
2446 case OP_MIN:
2447 case OP_MAX:
2448 emitMINMAX(insn);
2449 break;
2450 case OP_ABS:
2451 case OP_NEG:
2452 case OP_CEIL:
2453 case OP_FLOOR:
2454 case OP_TRUNC:
2455 case OP_SAT:
2456 emitCVT(insn);
2457 break;
2458 case OP_CVT:
2459 if (insn->def(0).getFile() == FILE_PREDICATE ||
2460 insn->src(0).getFile() == FILE_PREDICATE)
2461 emitMOV(insn);
2462 else
2463 emitCVT(insn);
2464 break;
2465 case OP_RSQ:
2466 emitSFnOp(insn, 5 + 2 * insn->subOp);
2467 break;
2468 case OP_RCP:
2469 emitSFnOp(insn, 4 + 2 * insn->subOp);
2470 break;
2471 case OP_LG2:
2472 emitSFnOp(insn, 3);
2473 break;
2474 case OP_EX2:
2475 emitSFnOp(insn, 2);
2476 break;
2477 case OP_SIN:
2478 emitSFnOp(insn, 1);
2479 break;
2480 case OP_COS:
2481 emitSFnOp(insn, 0);
2482 break;
2483 case OP_PRESIN:
2484 case OP_PREEX2:
2485 emitPreOp(insn);
2486 break;
2487 case OP_TEX:
2488 case OP_TXB:
2489 case OP_TXL:
2490 case OP_TXD:
2491 case OP_TXF:
2492 case OP_TXG:
2493 case OP_TXLQ:
2494 emitTEX(insn->asTex());
2495 break;
2496 case OP_TXQ:
2497 emitTXQ(insn->asTex());
2498 break;
2499 case OP_TEXBAR:
2500 emitTEXBAR(insn);
2501 break;
2502 case OP_SUBFM:
2503 case OP_SUCLAMP:
2504 case OP_SUEAU:
2505 emitSUCalc(insn);
2506 break;
2507 case OP_MADSP:
2508 emitMADSP(insn);
2509 break;
2510 case OP_SULDB:
2511 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2512 emitSULDGB(insn->asTex());
2513 else
2514 ERROR("SULDB not yet supported on < nve4\n");
2515 break;
2516 case OP_SUSTB:
2517 case OP_SUSTP:
2518 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2519 emitSUSTGx(insn->asTex());
2520 else
2521 ERROR("SUSTx not yet supported on < nve4\n");
2522 break;
2523 case OP_ATOM:
2524 emitATOM(insn);
2525 break;
2526 case OP_BRA:
2527 case OP_CALL:
2528 case OP_PRERET:
2529 case OP_RET:
2530 case OP_DISCARD:
2531 case OP_EXIT:
2532 case OP_PRECONT:
2533 case OP_CONT:
2534 case OP_PREBREAK:
2535 case OP_BREAK:
2536 case OP_JOINAT:
2537 case OP_BRKPT:
2538 case OP_QUADON:
2539 case OP_QUADPOP:
2540 emitFlow(insn);
2541 break;
2542 case OP_QUADOP:
2543 emitQUADOP(insn, insn->subOp, insn->lanes);
2544 break;
2545 case OP_DFDX:
2546 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2547 break;
2548 case OP_DFDY:
2549 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2550 break;
2551 case OP_POPCNT:
2552 emitPOPC(insn);
2553 break;
2554 case OP_INSBF:
2555 emitINSBF(insn);
2556 break;
2557 case OP_EXTBF:
2558 emitEXTBF(insn);
2559 break;
2560 case OP_BFIND:
2561 emitBFIND(insn);
2562 break;
2563 case OP_PERMT:
2564 emitPERMT(insn);
2565 break;
2566 case OP_JOIN:
2567 emitNOP(insn);
2568 insn->join = 1;
2569 break;
2570 case OP_BAR:
2571 emitBAR(insn);
2572 break;
2573 case OP_MEMBAR:
2574 emitMEMBAR(insn);
2575 break;
2576 case OP_CCTL:
2577 emitCCTL(insn);
2578 break;
2579 case OP_VSHL:
2580 emitVSHL(insn);
2581 break;
2582 case OP_PIXLD:
2583 emitPIXLD(insn);
2584 break;
2585 case OP_PHI:
2586 case OP_UNION:
2587 case OP_CONSTRAINT:
2588 ERROR("operation should have been eliminated");
2589 return false;
2590 case OP_EXP:
2591 case OP_LOG:
2592 case OP_SQRT:
2593 case OP_POW:
2594 ERROR("operation should have been lowered\n");
2595 return false;
2596 default:
2597 ERROR("unknown op: %u\n", insn->op);
2598 return false;
2599 }
2600
2601 if (insn->join) {
2602 code[0] |= 0x10;
2603 assert(insn->encSize == 8);
2604 }
2605
2606 code += insn->encSize / 4;
2607 codeSize += insn->encSize;
2608 return true;
2609 }
2610
2611 uint32_t
2612 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2613 {
2614 const Target::OpInfo &info = targ->getOpInfo(i);
2615
2616 if (writeIssueDelays || info.minEncSize == 8 || 1)
2617 return 8;
2618
2619 if (i->ftz || i->saturate || i->join)
2620 return 8;
2621 if (i->rnd != ROUND_N)
2622 return 8;
2623 if (i->predSrc >= 0 && i->op == OP_MAD)
2624 return 8;
2625
2626 if (i->op == OP_PINTERP) {
2627 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2628 return 8;
2629 } else
2630 if (i->op == OP_MOV && i->lanes != 0xf) {
2631 return 8;
2632 }
2633
2634 for (int s = 0; i->srcExists(s); ++s) {
2635 if (i->src(s).isIndirect(0))
2636 return 8;
2637
2638 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2639 if (SDATA(i->src(s)).offset >= 0x100)
2640 return 8;
2641 if (i->getSrc(s)->reg.fileIndex > 1 &&
2642 i->getSrc(s)->reg.fileIndex != 16)
2643 return 8;
2644 } else
2645 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2646 if (i->dType == TYPE_F32) {
2647 if (SDATA(i->src(s)).u32 >= 0x100)
2648 return 8;
2649 } else {
2650 if (SDATA(i->src(s)).u32 > 0xff)
2651 return 8;
2652 }
2653 }
2654
2655 if (i->op == OP_CVT)
2656 continue;
2657 if (i->src(s).mod != Modifier(0)) {
2658 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2659 if (i->op != OP_RSQ)
2660 return 8;
2661 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2662 if (i->op != OP_ADD || s != 0)
2663 return 8;
2664 }
2665 }
2666
2667 return 4;
2668 }
2669
2670 // Simplified, erring on safe side.
2671 class SchedDataCalculator : public Pass
2672 {
2673 public:
2674 SchedDataCalculator(const Target *targ) : targ(targ) { }
2675
2676 private:
2677 struct RegScores
2678 {
2679 struct Resource {
2680 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2681 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2682 int tex; // TEX to non-TEX delay 17 (0x11)
2683 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2684 int imul; // integer MUL to MUL delay 3
2685 } res;
2686 struct ScoreData {
2687 int r[256];
2688 int p[8];
2689 int c;
2690 } rd, wr;
2691 int base;
2692 int regs;
2693
2694 void rebase(const int base)
2695 {
2696 const int delta = this->base - base;
2697 if (!delta)
2698 return;
2699 this->base = 0;
2700
2701 for (int i = 0; i < regs; ++i) {
2702 rd.r[i] += delta;
2703 wr.r[i] += delta;
2704 }
2705 for (int i = 0; i < 8; ++i) {
2706 rd.p[i] += delta;
2707 wr.p[i] += delta;
2708 }
2709 rd.c += delta;
2710 wr.c += delta;
2711
2712 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2713 res.ld[f] += delta;
2714 res.st[f] += delta;
2715 }
2716 res.sfu += delta;
2717 res.imul += delta;
2718 res.tex += delta;
2719 }
2720 void wipe(int regs)
2721 {
2722 memset(&rd, 0, sizeof(rd));
2723 memset(&wr, 0, sizeof(wr));
2724 memset(&res, 0, sizeof(res));
2725 this->regs = regs;
2726 }
2727 int getLatest(const ScoreData& d) const
2728 {
2729 int max = 0;
2730 for (int i = 0; i < regs; ++i)
2731 if (d.r[i] > max)
2732 max = d.r[i];
2733 for (int i = 0; i < 8; ++i)
2734 if (d.p[i] > max)
2735 max = d.p[i];
2736 if (d.c > max)
2737 max = d.c;
2738 return max;
2739 }
2740 inline int getLatestRd() const
2741 {
2742 return getLatest(rd);
2743 }
2744 inline int getLatestWr() const
2745 {
2746 return getLatest(wr);
2747 }
2748 inline int getLatest() const
2749 {
2750 const int a = getLatestRd();
2751 const int b = getLatestWr();
2752
2753 int max = MAX2(a, b);
2754 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2755 max = MAX2(res.ld[f], max);
2756 max = MAX2(res.st[f], max);
2757 }
2758 max = MAX2(res.sfu, max);
2759 max = MAX2(res.imul, max);
2760 max = MAX2(res.tex, max);
2761 return max;
2762 }
2763 void setMax(const RegScores *that)
2764 {
2765 for (int i = 0; i < regs; ++i) {
2766 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2767 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2768 }
2769 for (int i = 0; i < 8; ++i) {
2770 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2771 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2772 }
2773 rd.c = MAX2(rd.c, that->rd.c);
2774 wr.c = MAX2(wr.c, that->wr.c);
2775
2776 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2777 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2778 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2779 }
2780 res.sfu = MAX2(res.sfu, that->res.sfu);
2781 res.imul = MAX2(res.imul, that->res.imul);
2782 res.tex = MAX2(res.tex, that->res.tex);
2783 }
2784 void print(int cycle)
2785 {
2786 for (int i = 0; i < regs; ++i) {
2787 if (rd.r[i] > cycle)
2788 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2789 if (wr.r[i] > cycle)
2790 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2791 }
2792 for (int i = 0; i < 8; ++i) {
2793 if (rd.p[i] > cycle)
2794 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2795 if (wr.p[i] > cycle)
2796 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2797 }
2798 if (rd.c > cycle)
2799 INFO("rd $c @ %i\n", rd.c);
2800 if (wr.c > cycle)
2801 INFO("wr $c @ %i\n", wr.c);
2802 if (res.sfu > cycle)
2803 INFO("sfu @ %i\n", res.sfu);
2804 if (res.imul > cycle)
2805 INFO("imul @ %i\n", res.imul);
2806 if (res.tex > cycle)
2807 INFO("tex @ %i\n", res.tex);
2808 }
2809 };
2810
2811 RegScores *score; // for current BB
2812 std::vector<RegScores> scoreBoards;
2813 int prevData;
2814 operation prevOp;
2815
2816 const Target *targ;
2817
2818 bool visit(Function *);
2819 bool visit(BasicBlock *);
2820
2821 void commitInsn(const Instruction *, int cycle);
2822 int calcDelay(const Instruction *, int cycle) const;
2823 void setDelay(Instruction *, int delay, Instruction *next);
2824
2825 void recordRd(const Value *, const int ready);
2826 void recordWr(const Value *, const int ready);
2827 void checkRd(const Value *, int cycle, int& delay) const;
2828 void checkWr(const Value *, int cycle, int& delay) const;
2829
2830 int getCycles(const Instruction *, int origDelay) const;
2831 };
2832
2833 void
2834 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2835 {
2836 if (insn->op == OP_EXIT || insn->op == OP_RET)
2837 delay = MAX2(delay, 14);
2838
2839 if (insn->op == OP_TEXBAR) {
2840 // TODO: except if results not used before EXIT
2841 insn->sched = 0xc2;
2842 } else
2843 if (insn->op == OP_JOIN || insn->join) {
2844 insn->sched = 0x00;
2845 } else
2846 if (delay >= 0 || prevData == 0x04 ||
2847 !next || !targ->canDualIssue(insn, next)) {
2848 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2849 if (prevOp == OP_EXPORT)
2850 insn->sched |= 0x40;
2851 else
2852 insn->sched |= 0x20;
2853 } else {
2854 insn->sched = 0x04; // dual-issue
2855 }
2856
2857 if (prevData != 0x04 || prevOp != OP_EXPORT)
2858 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2859 prevOp = insn->op;
2860
2861 prevData = insn->sched;
2862 }
2863
2864 int
2865 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2866 {
2867 if (insn->sched & 0x80) {
2868 int c = (insn->sched & 0x0f) * 2 + 1;
2869 if (insn->op == OP_TEXBAR && origDelay > 0)
2870 c += origDelay;
2871 return c;
2872 }
2873 if (insn->sched & 0x60)
2874 return (insn->sched & 0x1f) + 1;
2875 return (insn->sched == 0x04) ? 0 : 32;
2876 }
2877
2878 bool
2879 SchedDataCalculator::visit(Function *func)
2880 {
2881 int regs = targ->getFileSize(FILE_GPR) + 1;
2882 scoreBoards.resize(func->cfg.getSize());
2883 for (size_t i = 0; i < scoreBoards.size(); ++i)
2884 scoreBoards[i].wipe(regs);
2885 return true;
2886 }
2887
2888 bool
2889 SchedDataCalculator::visit(BasicBlock *bb)
2890 {
2891 Instruction *insn;
2892 Instruction *next = NULL;
2893
2894 int cycle = 0;
2895
2896 prevData = 0x00;
2897 prevOp = OP_NOP;
2898 score = &scoreBoards.at(bb->getId());
2899
2900 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2901 // back branches will wait until all target dependencies are satisfied
2902 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2903 continue;
2904 BasicBlock *in = BasicBlock::get(ei.getNode());
2905 if (in->getExit()) {
2906 if (prevData != 0x04)
2907 prevData = in->getExit()->sched;
2908 prevOp = in->getExit()->op;
2909 }
2910 score->setMax(&scoreBoards.at(in->getId()));
2911 }
2912 if (bb->cfg.incidentCount() > 1)
2913 prevOp = OP_NOP;
2914
2915 #ifdef NVC0_DEBUG_SCHED_DATA
2916 INFO("=== BB:%i initial scores\n", bb->getId());
2917 score->print(cycle);
2918 #endif
2919
2920 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2921 next = insn->next;
2922
2923 commitInsn(insn, cycle);
2924 int delay = calcDelay(next, cycle);
2925 setDelay(insn, delay, next);
2926 cycle += getCycles(insn, delay);
2927
2928 #ifdef NVC0_DEBUG_SCHED_DATA
2929 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2930 insn->print();
2931 next->print();
2932 #endif
2933 }
2934 if (!insn)
2935 return true;
2936 commitInsn(insn, cycle);
2937
2938 int bbDelay = -1;
2939
2940 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2941 BasicBlock *out = BasicBlock::get(ei.getNode());
2942
2943 if (ei.getType() != Graph::Edge::BACK) {
2944 // only test the first instruction of the outgoing block
2945 next = out->getEntry();
2946 if (next)
2947 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2948 } else {
2949 // wait until all dependencies are satisfied
2950 const int regsFree = score->getLatest();
2951 next = out->getFirst();
2952 for (int c = cycle; next && c < regsFree; next = next->next) {
2953 bbDelay = MAX2(bbDelay, calcDelay(next, c));
2954 c += getCycles(next, bbDelay);
2955 }
2956 next = NULL;
2957 }
2958 }
2959 if (bb->cfg.outgoingCount() != 1)
2960 next = NULL;
2961 setDelay(insn, bbDelay, next);
2962 cycle += getCycles(insn, bbDelay);
2963
2964 score->rebase(cycle); // common base for initializing out blocks' scores
2965 return true;
2966 }
2967
2968 #define NVE4_MAX_ISSUE_DELAY 0x1f
2969 int
2970 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
2971 {
2972 int delay = 0, ready = cycle;
2973
2974 for (int s = 0; insn->srcExists(s); ++s)
2975 checkRd(insn->getSrc(s), cycle, delay);
2976 // WAR & WAW don't seem to matter
2977 // for (int s = 0; insn->srcExists(s); ++s)
2978 // recordRd(insn->getSrc(s), cycle);
2979
2980 switch (Target::getOpClass(insn->op)) {
2981 case OPCLASS_SFU:
2982 ready = score->res.sfu;
2983 break;
2984 case OPCLASS_ARITH:
2985 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2986 ready = score->res.imul;
2987 break;
2988 case OPCLASS_TEXTURE:
2989 ready = score->res.tex;
2990 break;
2991 case OPCLASS_LOAD:
2992 ready = score->res.ld[insn->src(0).getFile()];
2993 break;
2994 case OPCLASS_STORE:
2995 ready = score->res.st[insn->src(0).getFile()];
2996 break;
2997 default:
2998 break;
2999 }
3000 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3001 ready = MAX2(ready, score->res.tex);
3002
3003 delay = MAX2(delay, ready - cycle);
3004
3005 // if can issue next cycle, delay is 0, not 1
3006 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3007 }
3008
3009 void
3010 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3011 {
3012 const int ready = cycle + targ->getLatency(insn);
3013
3014 for (int d = 0; insn->defExists(d); ++d)
3015 recordWr(insn->getDef(d), ready);
3016 // WAR & WAW don't seem to matter
3017 // for (int s = 0; insn->srcExists(s); ++s)
3018 // recordRd(insn->getSrc(s), cycle);
3019
3020 switch (Target::getOpClass(insn->op)) {
3021 case OPCLASS_SFU:
3022 score->res.sfu = cycle + 4;
3023 break;
3024 case OPCLASS_ARITH:
3025 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3026 score->res.imul = cycle + 4;
3027 break;
3028 case OPCLASS_TEXTURE:
3029 score->res.tex = cycle + 18;
3030 break;
3031 case OPCLASS_LOAD:
3032 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3033 break;
3034 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3035 score->res.st[insn->src(0).getFile()] = ready;
3036 break;
3037 case OPCLASS_STORE:
3038 score->res.st[insn->src(0).getFile()] = cycle + 4;
3039 score->res.ld[insn->src(0).getFile()] = ready;
3040 break;
3041 case OPCLASS_OTHER:
3042 if (insn->op == OP_TEXBAR)
3043 score->res.tex = cycle;
3044 break;
3045 default:
3046 break;
3047 }
3048
3049 #ifdef NVC0_DEBUG_SCHED_DATA
3050 score->print(cycle);
3051 #endif
3052 }
3053
3054 void
3055 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3056 {
3057 int ready = cycle;
3058 int a, b;
3059
3060 switch (v->reg.file) {
3061 case FILE_GPR:
3062 a = v->reg.data.id;
3063 b = a + v->reg.size / 4;
3064 for (int r = a; r < b; ++r)
3065 ready = MAX2(ready, score->rd.r[r]);
3066 break;
3067 case FILE_PREDICATE:
3068 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3069 break;
3070 case FILE_FLAGS:
3071 ready = MAX2(ready, score->rd.c);
3072 break;
3073 case FILE_SHADER_INPUT:
3074 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3075 case FILE_MEMORY_LOCAL:
3076 case FILE_MEMORY_CONST:
3077 case FILE_MEMORY_SHARED:
3078 case FILE_MEMORY_GLOBAL:
3079 case FILE_SYSTEM_VALUE:
3080 // TODO: any restrictions here ?
3081 break;
3082 case FILE_IMMEDIATE:
3083 break;
3084 default:
3085 assert(0);
3086 break;
3087 }
3088 if (cycle < ready)
3089 delay = MAX2(delay, ready - cycle);
3090 }
3091
3092 void
3093 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3094 {
3095 int ready = cycle;
3096 int a, b;
3097
3098 switch (v->reg.file) {
3099 case FILE_GPR:
3100 a = v->reg.data.id;
3101 b = a + v->reg.size / 4;
3102 for (int r = a; r < b; ++r)
3103 ready = MAX2(ready, score->wr.r[r]);
3104 break;
3105 case FILE_PREDICATE:
3106 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3107 break;
3108 default:
3109 assert(v->reg.file == FILE_FLAGS);
3110 ready = MAX2(ready, score->wr.c);
3111 break;
3112 }
3113 if (cycle < ready)
3114 delay = MAX2(delay, ready - cycle);
3115 }
3116
3117 void
3118 SchedDataCalculator::recordWr(const Value *v, const int ready)
3119 {
3120 int a = v->reg.data.id;
3121
3122 if (v->reg.file == FILE_GPR) {
3123 int b = a + v->reg.size / 4;
3124 for (int r = a; r < b; ++r)
3125 score->rd.r[r] = ready;
3126 } else
3127 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3128 if (v->reg.file == FILE_PREDICATE) {
3129 score->rd.p[a] = ready + 4;
3130 } else {
3131 assert(v->reg.file == FILE_FLAGS);
3132 score->rd.c = ready + 4;
3133 }
3134 }
3135
3136 void
3137 SchedDataCalculator::recordRd(const Value *v, const int ready)
3138 {
3139 int a = v->reg.data.id;
3140
3141 if (v->reg.file == FILE_GPR) {
3142 int b = a + v->reg.size / 4;
3143 for (int r = a; r < b; ++r)
3144 score->wr.r[r] = ready;
3145 } else
3146 if (v->reg.file == FILE_PREDICATE) {
3147 score->wr.p[a] = ready;
3148 } else
3149 if (v->reg.file == FILE_FLAGS) {
3150 score->wr.c = ready;
3151 }
3152 }
3153
3154 bool
3155 calculateSchedDataNVC0(const Target *targ, Function *func)
3156 {
3157 SchedDataCalculator sched(targ);
3158 return sched.run(func, true, true);
3159 }
3160
3161 void
3162 CodeEmitterNVC0::prepareEmission(Function *func)
3163 {
3164 CodeEmitter::prepareEmission(func);
3165
3166 if (targ->hasSWSched)
3167 calculateSchedDataNVC0(targ, func);
3168 }
3169
3170 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3171 : CodeEmitter(target),
3172 targNVC0(target),
3173 writeIssueDelays(target->hasSWSched)
3174 {
3175 code = NULL;
3176 codeSize = codeSizeLimit = 0;
3177 relocInfo = NULL;
3178 }
3179
3180 CodeEmitter *
3181 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3182 {
3183 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3184 emit->setProgramType(type);
3185 return emit;
3186 }
3187
3188 CodeEmitter *
3189 TargetNVC0::getCodeEmitter(Program::Type type)
3190 {
3191 if (chipset >= NVISA_GK20A_CHIPSET)
3192 return createCodeEmitterGK110(type);
3193 return createCodeEmitterNVC0(type);
3194 }
3195
3196 } // namespace nv50_ir