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nvc0/ir: add missing emission of locked load predicate
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitAFETCH(const Instruction *);
89 void emitPFETCH(const Instruction *);
90 void emitVFETCH(const Instruction *);
91 void emitEXPORT(const Instruction *);
92 void emitOUT(const Instruction *);
93
94 void emitUADD(const Instruction *);
95 void emitFADD(const Instruction *);
96 void emitDADD(const Instruction *);
97 void emitUMUL(const Instruction *);
98 void emitFMUL(const Instruction *);
99 void emitDMUL(const Instruction *);
100 void emitIMAD(const Instruction *);
101 void emitISAD(const Instruction *);
102 void emitFMAD(const Instruction *);
103 void emitDMAD(const Instruction *);
104 void emitMADSP(const Instruction *);
105
106 void emitNOT(Instruction *);
107 void emitLogicOp(const Instruction *, uint8_t subOp);
108 void emitPOPC(const Instruction *);
109 void emitINSBF(const Instruction *);
110 void emitEXTBF(const Instruction *);
111 void emitBFIND(const Instruction *);
112 void emitPERMT(const Instruction *);
113 void emitShift(const Instruction *);
114
115 void emitSFnOp(const Instruction *, uint8_t subOp);
116
117 void emitCVT(Instruction *);
118 void emitMINMAX(const Instruction *);
119 void emitPreOp(const Instruction *);
120
121 void emitSET(const CmpInstruction *);
122 void emitSLCT(const CmpInstruction *);
123 void emitSELP(const Instruction *);
124
125 void emitTEXBAR(const Instruction *);
126 void emitTEX(const TexInstruction *);
127 void emitTEXCSAA(const TexInstruction *);
128 void emitTXQ(const TexInstruction *);
129
130 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
131
132 void emitFlow(const Instruction *);
133 void emitBAR(const Instruction *);
134
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction *);
137 void emitSULDGB(const TexInstruction *);
138 void emitSUSTGx(const TexInstruction *);
139
140 void emitVSHL(const Instruction *);
141 void emitVectorSubOp(const Instruction *);
142
143 void emitPIXLD(const Instruction *);
144
145 inline void defId(const ValueDef&, const int pos);
146 inline void defId(const Instruction *, int d, const int pos);
147 inline void srcId(const ValueRef&, const int pos);
148 inline void srcId(const ValueRef *, const int pos);
149 inline void srcId(const Instruction *, int s, const int pos);
150 inline void srcAddr32(const ValueRef&, int pos, int shr);
151
152 inline bool isLIMM(const ValueRef&, DataType ty);
153 };
154
155 // for better visibility
156 #define HEX64(h, l) 0x##h##l##ULL
157
158 #define SDATA(a) ((a).rep()->reg.data)
159 #define DDATA(a) ((a).rep()->reg.data)
160
161 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
162 {
163 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
164 }
165
166 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
167 {
168 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
169 }
170
171 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
172 {
173 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
174 code[pos / 32] |= r << (pos % 32);
175 }
176
177 void
178 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
179 {
180 const uint32_t offset = SDATA(src).offset >> shr;
181
182 code[pos / 32] |= offset << (pos % 32);
183 if (pos && (pos < 32))
184 code[1] |= offset >> (32 - pos);
185 }
186
187 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
188 {
189 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
190 }
191
192 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
193 {
194 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
195 code[pos / 32] |= r << (pos % 32);
196 }
197
198 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
199 {
200 const ImmediateValue *imm = ref.get()->asImm();
201
202 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
203 }
204
205 void
206 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
207 {
208 switch (insn->rnd) {
209 case ROUND_M: code[1] |= 1 << 23; break;
210 case ROUND_P: code[1] |= 2 << 23; break;
211 case ROUND_Z: code[1] |= 3 << 23; break;
212 default:
213 assert(insn->rnd == ROUND_N);
214 break;
215 }
216 }
217
218 void
219 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
220 {
221 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
222 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
223 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
224 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
225 }
226
227 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
228 {
229 uint8_t val;
230
231 switch (cc) {
232 case CC_LT: val = 0x1; break;
233 case CC_LTU: val = 0x9; break;
234 case CC_EQ: val = 0x2; break;
235 case CC_EQU: val = 0xa; break;
236 case CC_LE: val = 0x3; break;
237 case CC_LEU: val = 0xb; break;
238 case CC_GT: val = 0x4; break;
239 case CC_GTU: val = 0xc; break;
240 case CC_NE: val = 0x5; break;
241 case CC_NEU: val = 0xd; break;
242 case CC_GE: val = 0x6; break;
243 case CC_GEU: val = 0xe; break;
244 case CC_TR: val = 0xf; break;
245 case CC_FL: val = 0x0; break;
246
247 case CC_A: val = 0x14; break;
248 case CC_NA: val = 0x13; break;
249 case CC_S: val = 0x15; break;
250 case CC_NS: val = 0x12; break;
251 case CC_C: val = 0x16; break;
252 case CC_NC: val = 0x11; break;
253 case CC_O: val = 0x17; break;
254 case CC_NO: val = 0x10; break;
255
256 default:
257 val = 0;
258 assert(!"invalid condition code");
259 break;
260 }
261 code[pos / 32] |= val << (pos % 32);
262 }
263
264 void
265 CodeEmitterNVC0::emitPredicate(const Instruction *i)
266 {
267 if (i->predSrc >= 0) {
268 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
269 srcId(i->src(i->predSrc), 10);
270 if (i->cc == CC_NOT_P)
271 code[0] |= 0x2000; // negate
272 } else {
273 code[0] |= 0x1c00;
274 }
275 }
276
277 void
278 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
279 {
280 switch (src.getFile()) {
281 case FILE_MEMORY_GLOBAL:
282 srcAddr32(src, 26, 0);
283 break;
284 case FILE_MEMORY_LOCAL:
285 case FILE_MEMORY_SHARED:
286 setAddress24(src);
287 break;
288 default:
289 assert(src.getFile() == FILE_MEMORY_CONST);
290 setAddress16(src);
291 break;
292 }
293 }
294
295 void
296 CodeEmitterNVC0::setAddress16(const ValueRef& src)
297 {
298 Symbol *sym = src.get()->asSym();
299
300 assert(sym);
301
302 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
303 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
304 }
305
306 void
307 CodeEmitterNVC0::setAddress24(const ValueRef& src)
308 {
309 Symbol *sym = src.get()->asSym();
310
311 assert(sym);
312
313 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
314 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
315 }
316
317 void
318 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
319 {
320 const ImmediateValue *imm = i->src(s).get()->asImm();
321 uint32_t u32;
322
323 assert(imm);
324 u32 = imm->reg.data.u32;
325
326 if ((code[0] & 0xf) == 0x1) {
327 // double immediate
328 uint64_t u64 = imm->reg.data.u64;
329 assert(!(u64 & 0x00000fffffffffffULL));
330 assert(!(code[1] & 0xc000));
331 code[0] |= ((u64 >> 44) & 0x3f) << 26;
332 code[1] |= 0xc000 | (u64 >> 50);
333 } else
334 if ((code[0] & 0xf) == 0x2) {
335 // LIMM
336 code[0] |= (u32 & 0x3f) << 26;
337 code[1] |= u32 >> 6;
338 } else
339 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
340 // integer immediate
341 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
342 assert(!(code[1] & 0xc000));
343 u32 &= 0xfffff;
344 code[0] |= (u32 & 0x3f) << 26;
345 code[1] |= 0xc000 | (u32 >> 6);
346 } else {
347 // float immediate
348 assert(!(u32 & 0x00000fff));
349 assert(!(code[1] & 0xc000));
350 code[0] |= ((u32 >> 12) & 0x3f) << 26;
351 code[1] |= 0xc000 | (u32 >> 18);
352 }
353 }
354
355 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
356 {
357 const ImmediateValue *imm = ref.get()->asImm();
358
359 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
360
361 assert(s8 == imm->reg.data.s32);
362
363 code[0] |= (s8 & 0x3f) << 26;
364 code[0] |= (s8 >> 6) << 8;
365 }
366
367 void
368 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
369 {
370 code[0] = opc;
371 code[1] = opc >> 32;
372
373 emitPredicate(i);
374
375 defId(i->def(0), 14);
376
377 int s1 = 26;
378 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
379 s1 = 49;
380
381 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
382 switch (i->getSrc(s)->reg.file) {
383 case FILE_MEMORY_CONST:
384 assert(!(code[1] & 0xc000));
385 code[1] |= (s == 2) ? 0x8000 : 0x4000;
386 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
387 setAddress16(i->src(s));
388 break;
389 case FILE_IMMEDIATE:
390 assert(s == 1 ||
391 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
392 assert(!(code[1] & 0xc000));
393 setImmediate(i, s);
394 break;
395 case FILE_GPR:
396 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
397 break;
398 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
399 break;
400 default:
401 if (i->op == OP_SELP) {
402 // OP_SELP is used to implement shared+atomics on Fermi.
403 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
404 srcId(i->src(s), 49);
405 }
406 // ignore here, can be predicate or flags, but must not be address
407 break;
408 }
409 }
410 }
411
412 void
413 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
414 {
415 code[0] = opc;
416 code[1] = opc >> 32;
417
418 emitPredicate(i);
419
420 defId(i->def(0), 14);
421
422 switch (i->src(0).getFile()) {
423 case FILE_MEMORY_CONST:
424 assert(!(code[1] & 0xc000));
425 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
426 setAddress16(i->src(0));
427 break;
428 case FILE_IMMEDIATE:
429 assert(!(code[1] & 0xc000));
430 setImmediate(i, 0);
431 break;
432 case FILE_GPR:
433 srcId(i->src(0), 26);
434 break;
435 default:
436 // ignore here, can be predicate or flags, but must not be address
437 break;
438 }
439 }
440
441 void
442 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
443 {
444 code[0] = opc;
445
446 int ss2a = 0;
447 if (opc == 0x0d || opc == 0x0e)
448 ss2a = 2;
449
450 defId(i->def(0), 14);
451 srcId(i->src(0), 20);
452
453 assert(pred || (i->predSrc < 0));
454 if (pred)
455 emitPredicate(i);
456
457 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
458 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
459 assert(!(code[0] & (0x300 >> ss2a)));
460 switch (i->src(s).get()->reg.fileIndex) {
461 case 0: code[0] |= 0x100 >> ss2a; break;
462 case 1: code[0] |= 0x200 >> ss2a; break;
463 case 16: code[0] |= 0x300 >> ss2a; break;
464 default:
465 ERROR("invalid c[] space for short form\n");
466 break;
467 }
468 if (s == 1)
469 code[0] |= i->getSrc(s)->reg.data.offset << 24;
470 else
471 code[0] |= i->getSrc(s)->reg.data.offset << 6;
472 } else
473 if (i->src(s).getFile() == FILE_IMMEDIATE) {
474 assert(s == 1);
475 setImmediateS8(i->src(s));
476 } else
477 if (i->src(s).getFile() == FILE_GPR) {
478 srcId(i->src(s), (s == 1) ? 26 : 8);
479 }
480 }
481 }
482
483 void
484 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
485 {
486 if (src.getFile() == FILE_MEMORY_CONST) {
487 switch (src.get()->reg.fileIndex) {
488 case 0: code[0] |= 0x100; break;
489 case 1: code[0] |= 0x200; break;
490 case 16: code[0] |= 0x300; break;
491 default:
492 assert(!"unsupported file index for short op");
493 break;
494 }
495 srcAddr32(src, 20, 2);
496 } else {
497 srcId(src, 20);
498 assert(src.getFile() == FILE_GPR);
499 }
500 }
501
502 void
503 CodeEmitterNVC0::emitNOP(const Instruction *i)
504 {
505 code[0] = 0x000001e4;
506 code[1] = 0x40000000;
507 emitPredicate(i);
508 }
509
510 void
511 CodeEmitterNVC0::emitFMAD(const Instruction *i)
512 {
513 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
514
515 if (i->encSize == 8) {
516 if (isLIMM(i->src(1), TYPE_F32)) {
517 emitForm_A(i, HEX64(20000000, 00000002));
518 } else {
519 emitForm_A(i, HEX64(30000000, 00000000));
520
521 if (i->src(2).mod.neg())
522 code[0] |= 1 << 8;
523 }
524 roundMode_A(i);
525
526 if (neg1)
527 code[0] |= 1 << 9;
528
529 if (i->saturate)
530 code[0] |= 1 << 5;
531 if (i->ftz)
532 code[0] |= 1 << 6;
533 } else {
534 assert(!i->saturate && !i->src(2).mod.neg());
535 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
536 false);
537 if (neg1)
538 code[0] |= 1 << 4;
539 }
540 }
541
542 void
543 CodeEmitterNVC0::emitDMAD(const Instruction *i)
544 {
545 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
546
547 emitForm_A(i, HEX64(20000000, 00000001));
548
549 if (i->src(2).mod.neg())
550 code[0] |= 1 << 8;
551
552 roundMode_A(i);
553
554 if (neg1)
555 code[0] |= 1 << 9;
556
557 assert(!i->saturate);
558 assert(!i->ftz);
559 }
560
561 void
562 CodeEmitterNVC0::emitFMUL(const Instruction *i)
563 {
564 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
565
566 assert(i->postFactor >= -3 && i->postFactor <= 3);
567
568 if (i->encSize == 8) {
569 if (isLIMM(i->src(1), TYPE_F32)) {
570 assert(i->postFactor == 0); // constant folded, hopefully
571 emitForm_A(i, HEX64(30000000, 00000002));
572 } else {
573 emitForm_A(i, HEX64(58000000, 00000000));
574 roundMode_A(i);
575 code[1] |= ((i->postFactor > 0) ?
576 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
577 }
578 if (neg)
579 code[1] ^= 1 << 25; // aliases with LIMM sign bit
580
581 if (i->saturate)
582 code[0] |= 1 << 5;
583
584 if (i->dnz)
585 code[0] |= 1 << 7;
586 else
587 if (i->ftz)
588 code[0] |= 1 << 6;
589 } else {
590 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
591 emitForm_S(i, 0xa8, true);
592 }
593 }
594
595 void
596 CodeEmitterNVC0::emitDMUL(const Instruction *i)
597 {
598 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
599
600 emitForm_A(i, HEX64(50000000, 00000001));
601 roundMode_A(i);
602
603 if (neg)
604 code[0] |= 1 << 9;
605
606 assert(!i->saturate);
607 assert(!i->ftz);
608 assert(!i->dnz);
609 assert(!i->postFactor);
610 }
611
612 void
613 CodeEmitterNVC0::emitUMUL(const Instruction *i)
614 {
615 if (i->encSize == 8) {
616 if (i->src(1).getFile() == FILE_IMMEDIATE) {
617 emitForm_A(i, HEX64(10000000, 00000002));
618 } else {
619 emitForm_A(i, HEX64(50000000, 00000003));
620 }
621 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
622 code[0] |= 1 << 6;
623 if (i->sType == TYPE_S32)
624 code[0] |= 1 << 5;
625 if (i->dType == TYPE_S32)
626 code[0] |= 1 << 7;
627 } else {
628 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
629
630 if (i->sType == TYPE_S32)
631 code[0] |= 1 << 6;
632 }
633 }
634
635 void
636 CodeEmitterNVC0::emitFADD(const Instruction *i)
637 {
638 if (i->encSize == 8) {
639 if (isLIMM(i->src(1), TYPE_F32)) {
640 assert(!i->saturate);
641 emitForm_A(i, HEX64(28000000, 00000002));
642
643 code[0] |= i->src(0).mod.abs() << 7;
644 code[0] |= i->src(0).mod.neg() << 9;
645
646 if (i->src(1).mod.abs())
647 code[1] &= 0xfdffffff;
648 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
649 code[1] ^= 0x02000000;
650 } else {
651 emitForm_A(i, HEX64(50000000, 00000000));
652
653 roundMode_A(i);
654 if (i->saturate)
655 code[1] |= 1 << 17;
656
657 emitNegAbs12(i);
658 if (i->op == OP_SUB) code[0] ^= 1 << 8;
659 }
660 if (i->ftz)
661 code[0] |= 1 << 5;
662 } else {
663 assert(!i->saturate && i->op != OP_SUB &&
664 !i->src(0).mod.abs() &&
665 !i->src(1).mod.neg() && !i->src(1).mod.abs());
666
667 emitForm_S(i, 0x49, true);
668
669 if (i->src(0).mod.neg())
670 code[0] |= 1 << 7;
671 }
672 }
673
674 void
675 CodeEmitterNVC0::emitDADD(const Instruction *i)
676 {
677 assert(i->encSize == 8);
678 emitForm_A(i, HEX64(48000000, 00000001));
679 roundMode_A(i);
680 assert(!i->saturate);
681 assert(!i->ftz);
682 emitNegAbs12(i);
683 if (i->op == OP_SUB)
684 code[0] ^= 1 << 8;
685 }
686
687 void
688 CodeEmitterNVC0::emitUADD(const Instruction *i)
689 {
690 uint32_t addOp = 0;
691
692 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
693 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
694
695 if (i->src(0).mod.neg())
696 addOp |= 0x200;
697 if (i->src(1).mod.neg())
698 addOp |= 0x100;
699 if (i->op == OP_SUB) {
700 addOp ^= 0x100;
701 assert(addOp != 0x300); // would be add-plus-one
702 }
703
704 if (i->encSize == 8) {
705 if (isLIMM(i->src(1), TYPE_U32)) {
706 emitForm_A(i, HEX64(08000000, 00000002));
707 if (i->defExists(1))
708 code[1] |= 1 << 26; // write carry
709 } else {
710 emitForm_A(i, HEX64(48000000, 00000003));
711 if (i->defExists(1))
712 code[1] |= 1 << 16; // write carry
713 }
714 code[0] |= addOp;
715
716 if (i->saturate)
717 code[0] |= 1 << 5;
718 if (i->flagsSrc >= 0) // add carry
719 code[0] |= 1 << 6;
720 } else {
721 assert(!(addOp & 0x100));
722 emitForm_S(i, (addOp >> 3) |
723 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
724 }
725 }
726
727 // TODO: shl-add
728 void
729 CodeEmitterNVC0::emitIMAD(const Instruction *i)
730 {
731 assert(i->encSize == 8);
732 emitForm_A(i, HEX64(20000000, 00000003));
733
734 if (isSignedType(i->dType))
735 code[0] |= 1 << 7;
736 if (isSignedType(i->sType))
737 code[0] |= 1 << 5;
738
739 code[1] |= i->saturate << 24;
740
741 if (i->flagsDef >= 0) code[1] |= 1 << 16;
742 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
743
744 if (i->src(2).mod.neg()) code[0] |= 0x10;
745 if (i->src(1).mod.neg() ^
746 i->src(0).mod.neg()) code[0] |= 0x20;
747
748 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
749 code[0] |= 1 << 6;
750 }
751
752 void
753 CodeEmitterNVC0::emitMADSP(const Instruction *i)
754 {
755 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
756
757 emitForm_A(i, HEX64(00000000, 00000003));
758
759 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
760 code[1] |= 0x01800000;
761 } else {
762 code[0] |= (i->subOp & 0x00f) << 7;
763 code[0] |= (i->subOp & 0x0f0) << 1;
764 code[0] |= (i->subOp & 0x100) >> 3;
765 code[0] |= (i->subOp & 0x200) >> 2;
766 code[1] |= (i->subOp & 0xc00) << 13;
767 }
768
769 if (i->flagsDef >= 0)
770 code[1] |= 1 << 16;
771 }
772
773 void
774 CodeEmitterNVC0::emitISAD(const Instruction *i)
775 {
776 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
777 assert(i->encSize == 8);
778
779 emitForm_A(i, HEX64(38000000, 00000003));
780
781 if (i->dType == TYPE_S32)
782 code[0] |= 1 << 5;
783 }
784
785 void
786 CodeEmitterNVC0::emitNOT(Instruction *i)
787 {
788 assert(i->encSize == 8);
789 i->setSrc(1, i->src(0));
790 emitForm_A(i, HEX64(68000000, 000001c3));
791 }
792
793 void
794 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
795 {
796 if (i->def(0).getFile() == FILE_PREDICATE) {
797 code[0] = 0x00000004 | (subOp << 30);
798 code[1] = 0x0c000000;
799
800 emitPredicate(i);
801
802 defId(i->def(0), 17);
803 srcId(i->src(0), 20);
804 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
805 srcId(i->src(1), 26);
806 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
807
808 if (i->defExists(1)) {
809 defId(i->def(1), 14);
810 } else {
811 code[0] |= 7 << 14;
812 }
813 // (a OP b) OP c
814 if (i->predSrc != 2 && i->srcExists(2)) {
815 code[1] |= subOp << 21;
816 srcId(i->src(2), 17);
817 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
818 } else {
819 code[1] |= 0x000e0000;
820 }
821 } else
822 if (i->encSize == 8) {
823 if (isLIMM(i->src(1), TYPE_U32)) {
824 emitForm_A(i, HEX64(38000000, 00000002));
825
826 if (i->flagsDef >= 0)
827 code[1] |= 1 << 26;
828 } else {
829 emitForm_A(i, HEX64(68000000, 00000003));
830
831 if (i->flagsDef >= 0)
832 code[1] |= 1 << 16;
833 }
834 code[0] |= subOp << 6;
835
836 if (i->flagsSrc >= 0) // carry
837 code[0] |= 1 << 5;
838
839 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
840 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
841 } else {
842 emitForm_S(i, (subOp << 5) |
843 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
844 }
845 }
846
847 void
848 CodeEmitterNVC0::emitPOPC(const Instruction *i)
849 {
850 emitForm_A(i, HEX64(54000000, 00000004));
851
852 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
853 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
854 }
855
856 void
857 CodeEmitterNVC0::emitINSBF(const Instruction *i)
858 {
859 emitForm_A(i, HEX64(28000000, 00000003));
860 }
861
862 void
863 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
864 {
865 emitForm_A(i, HEX64(70000000, 00000003));
866
867 if (i->dType == TYPE_S32)
868 code[0] |= 1 << 5;
869 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
870 code[0] |= 1 << 8;
871 }
872
873 void
874 CodeEmitterNVC0::emitBFIND(const Instruction *i)
875 {
876 emitForm_B(i, HEX64(78000000, 00000003));
877
878 if (i->dType == TYPE_S32)
879 code[0] |= 1 << 5;
880 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
881 code[0] |= 1 << 8;
882 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
883 code[0] |= 1 << 6;
884 }
885
886 void
887 CodeEmitterNVC0::emitPERMT(const Instruction *i)
888 {
889 emitForm_A(i, HEX64(24000000, 00000004));
890
891 code[0] |= i->subOp << 5;
892 }
893
894 void
895 CodeEmitterNVC0::emitShift(const Instruction *i)
896 {
897 if (i->op == OP_SHR) {
898 emitForm_A(i, HEX64(58000000, 00000003)
899 | (isSignedType(i->dType) ? 0x20 : 0x00));
900 } else {
901 emitForm_A(i, HEX64(60000000, 00000003));
902 }
903
904 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
905 code[0] |= 1 << 9;
906 }
907
908 void
909 CodeEmitterNVC0::emitPreOp(const Instruction *i)
910 {
911 if (i->encSize == 8) {
912 emitForm_B(i, HEX64(60000000, 00000000));
913
914 if (i->op == OP_PREEX2)
915 code[0] |= 0x20;
916
917 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
918 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
919 } else {
920 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
921 }
922 }
923
924 void
925 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
926 {
927 if (i->encSize == 8) {
928 code[0] = 0x00000000 | (subOp << 26);
929 code[1] = 0xc8000000;
930
931 emitPredicate(i);
932
933 defId(i->def(0), 14);
934 srcId(i->src(0), 20);
935
936 assert(i->src(0).getFile() == FILE_GPR);
937
938 if (i->saturate) code[0] |= 1 << 5;
939
940 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
941 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
942 } else {
943 emitForm_S(i, 0x80000008 | (subOp << 26), true);
944
945 assert(!i->src(0).mod.neg());
946 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
947 }
948 }
949
950 void
951 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
952 {
953 uint64_t op;
954
955 assert(i->encSize == 8);
956
957 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
958
959 if (i->ftz)
960 op |= 1 << 5;
961 else
962 if (!isFloatType(i->dType))
963 op |= isSignedType(i->dType) ? 0x23 : 0x03;
964 if (i->dType == TYPE_F64)
965 op |= 0x01;
966
967 emitForm_A(i, op);
968 emitNegAbs12(i);
969 }
970
971 void
972 CodeEmitterNVC0::roundMode_C(const Instruction *i)
973 {
974 switch (i->rnd) {
975 case ROUND_M: code[1] |= 1 << 17; break;
976 case ROUND_P: code[1] |= 2 << 17; break;
977 case ROUND_Z: code[1] |= 3 << 17; break;
978 case ROUND_NI: code[0] |= 1 << 7; break;
979 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
980 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
981 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
982 case ROUND_N: break;
983 default:
984 assert(!"invalid round mode");
985 break;
986 }
987 }
988
989 void
990 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
991 {
992 switch (i->rnd) {
993 case ROUND_M:
994 case ROUND_MI: code[0] |= 1 << 16; break;
995 case ROUND_P:
996 case ROUND_PI: code[0] |= 2 << 16; break;
997 case ROUND_Z:
998 case ROUND_ZI: code[0] |= 3 << 16; break;
999 default:
1000 break;
1001 }
1002 }
1003
1004 void
1005 CodeEmitterNVC0::emitCVT(Instruction *i)
1006 {
1007 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1008 DataType dType;
1009
1010 switch (i->op) {
1011 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1012 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1013 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1014 default:
1015 break;
1016 }
1017
1018 const bool sat = (i->op == OP_SAT) || i->saturate;
1019 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1020 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1021
1022 if (i->op == OP_NEG && i->dType == TYPE_U32)
1023 dType = TYPE_S32;
1024 else
1025 dType = i->dType;
1026
1027 if (i->encSize == 8) {
1028 emitForm_B(i, HEX64(10000000, 00000004));
1029
1030 roundMode_C(i);
1031
1032 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1033 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1034 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1035
1036 // for 8/16 source types, the byte/word is in subOp. word 1 is
1037 // represented as 2.
1038 if (!isFloatType(i->sType))
1039 code[1] |= i->subOp << 0x17;
1040 else
1041 code[1] |= i->subOp << 0x18;
1042
1043 if (sat)
1044 code[0] |= 0x20;
1045 if (abs)
1046 code[0] |= 1 << 6;
1047 if (neg && i->op != OP_ABS)
1048 code[0] |= 1 << 8;
1049
1050 if (i->ftz)
1051 code[1] |= 1 << 23;
1052
1053 if (isSignedIntType(dType))
1054 code[0] |= 0x080;
1055 if (isSignedIntType(i->sType))
1056 code[0] |= 0x200;
1057
1058 if (isFloatType(dType)) {
1059 if (!isFloatType(i->sType))
1060 code[1] |= 0x08000000;
1061 } else {
1062 if (isFloatType(i->sType))
1063 code[1] |= 0x04000000;
1064 else
1065 code[1] |= 0x0c000000;
1066 }
1067 } else {
1068 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1069 code[0] = 0x298;
1070 } else
1071 if (isFloatType(dType)) {
1072 if (isFloatType(i->sType))
1073 code[0] = 0x098;
1074 else
1075 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1076 } else {
1077 assert(isFloatType(i->sType));
1078
1079 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1080 }
1081
1082 if (neg) code[0] |= 1 << 16;
1083 if (sat) code[0] |= 1 << 18;
1084 if (abs) code[0] |= 1 << 19;
1085
1086 roundMode_CS(i);
1087 }
1088 }
1089
1090 void
1091 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1092 {
1093 uint32_t hi;
1094 uint32_t lo = 0;
1095
1096 if (i->sType == TYPE_F64)
1097 lo = 0x1;
1098 else
1099 if (!isFloatType(i->sType))
1100 lo = 0x3;
1101
1102 if (isSignedIntType(i->sType))
1103 lo |= 0x20;
1104 if (isFloatType(i->dType)) {
1105 if (isFloatType(i->sType))
1106 lo |= 0x20;
1107 else
1108 lo |= 0x80;
1109 }
1110
1111 switch (i->op) {
1112 case OP_SET_AND: hi = 0x10000000; break;
1113 case OP_SET_OR: hi = 0x10200000; break;
1114 case OP_SET_XOR: hi = 0x10400000; break;
1115 default:
1116 hi = 0x100e0000;
1117 break;
1118 }
1119 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1120
1121 if (i->op != OP_SET)
1122 srcId(i->src(2), 32 + 17);
1123
1124 if (i->def(0).getFile() == FILE_PREDICATE) {
1125 if (i->sType == TYPE_F32)
1126 code[1] += 0x10000000;
1127 else
1128 code[1] += 0x08000000;
1129
1130 code[0] &= ~0xfc000;
1131 defId(i->def(0), 17);
1132 if (i->defExists(1))
1133 defId(i->def(1), 14);
1134 else
1135 code[0] |= 0x1c000;
1136 }
1137
1138 if (i->ftz)
1139 code[1] |= 1 << 27;
1140
1141 emitCondCode(i->setCond, 32 + 23);
1142 emitNegAbs12(i);
1143 }
1144
1145 void
1146 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1147 {
1148 uint64_t op;
1149
1150 switch (i->dType) {
1151 case TYPE_S32:
1152 op = HEX64(30000000, 00000023);
1153 break;
1154 case TYPE_U32:
1155 op = HEX64(30000000, 00000003);
1156 break;
1157 case TYPE_F32:
1158 op = HEX64(38000000, 00000000);
1159 break;
1160 default:
1161 assert(!"invalid type for SLCT");
1162 op = 0;
1163 break;
1164 }
1165 emitForm_A(i, op);
1166
1167 CondCode cc = i->setCond;
1168
1169 if (i->src(2).mod.neg())
1170 cc = reverseCondCode(cc);
1171
1172 emitCondCode(cc, 32 + 23);
1173
1174 if (i->ftz)
1175 code[0] |= 1 << 5;
1176 }
1177
1178 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1179 {
1180 emitForm_A(i, HEX64(20000000, 00000004));
1181
1182 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1183 code[1] |= 1 << 20;
1184 }
1185
1186 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1187 {
1188 code[0] = 0x00000006 | (i->subOp << 26);
1189 code[1] = 0xf0000000;
1190 emitPredicate(i);
1191 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1192 }
1193
1194 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1195 {
1196 code[0] = 0x00000086;
1197 code[1] = 0xd0000000;
1198
1199 code[1] |= i->tex.r;
1200 code[1] |= i->tex.s << 8;
1201
1202 if (i->tex.liveOnly)
1203 code[0] |= 1 << 9;
1204
1205 defId(i->def(0), 14);
1206 srcId(i->src(0), 20);
1207 }
1208
1209 static inline bool
1210 isNextIndependentTex(const TexInstruction *i)
1211 {
1212 if (!i->next || !isTextureOp(i->next->op))
1213 return false;
1214 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1215 return false;
1216 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1217 }
1218
1219 void
1220 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1221 {
1222 code[0] = 0x00000006;
1223
1224 if (isNextIndependentTex(i))
1225 code[0] |= 0x080; // t mode
1226 else
1227 code[0] |= 0x100; // p mode
1228
1229 if (i->tex.liveOnly)
1230 code[0] |= 1 << 9;
1231
1232 switch (i->op) {
1233 case OP_TEX: code[1] = 0x80000000; break;
1234 case OP_TXB: code[1] = 0x84000000; break;
1235 case OP_TXL: code[1] = 0x86000000; break;
1236 case OP_TXF: code[1] = 0x90000000; break;
1237 case OP_TXG: code[1] = 0xa0000000; break;
1238 case OP_TXLQ: code[1] = 0xb0000000; break;
1239 case OP_TXD: code[1] = 0xe0000000; break;
1240 default:
1241 assert(!"invalid texture op");
1242 break;
1243 }
1244 if (i->op == OP_TXF) {
1245 if (!i->tex.levelZero)
1246 code[1] |= 0x02000000;
1247 } else
1248 if (i->tex.levelZero) {
1249 code[1] |= 0x02000000;
1250 }
1251
1252 if (i->op != OP_TXD && i->tex.derivAll)
1253 code[1] |= 1 << 13;
1254
1255 defId(i->def(0), 14);
1256 srcId(i->src(0), 20);
1257
1258 emitPredicate(i);
1259
1260 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1261
1262 code[1] |= i->tex.mask << 14;
1263
1264 code[1] |= i->tex.r;
1265 code[1] |= i->tex.s << 8;
1266 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1267 code[1] |= 1 << 18; // in 1st source (with array index)
1268
1269 // texture target:
1270 code[1] |= (i->tex.target.getDim() - 1) << 20;
1271 if (i->tex.target.isCube())
1272 code[1] += 2 << 20;
1273 if (i->tex.target.isArray())
1274 code[1] |= 1 << 19;
1275 if (i->tex.target.isShadow())
1276 code[1] |= 1 << 24;
1277
1278 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1279
1280 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1281 // lzero
1282 if (i->op == OP_TXL)
1283 code[1] &= ~(1 << 26);
1284 else
1285 if (i->op == OP_TXF)
1286 code[1] &= ~(1 << 25);
1287 }
1288 if (i->tex.target == TEX_TARGET_2D_MS ||
1289 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1290 code[1] |= 1 << 23;
1291
1292 if (i->tex.useOffsets == 1)
1293 code[1] |= 1 << 22;
1294 if (i->tex.useOffsets == 4)
1295 code[1] |= 1 << 23;
1296
1297 srcId(i, src1, 26);
1298 }
1299
1300 void
1301 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1302 {
1303 code[0] = 0x00000086;
1304 code[1] = 0xc0000000;
1305
1306 switch (i->tex.query) {
1307 case TXQ_DIMS: code[1] |= 0 << 22; break;
1308 case TXQ_TYPE: code[1] |= 1 << 22; break;
1309 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1310 case TXQ_FILTER: code[1] |= 3 << 22; break;
1311 case TXQ_LOD: code[1] |= 4 << 22; break;
1312 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1313 default:
1314 assert(!"invalid texture query");
1315 break;
1316 }
1317
1318 code[1] |= i->tex.mask << 14;
1319
1320 code[1] |= i->tex.r;
1321 code[1] |= i->tex.s << 8;
1322 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1323 code[1] |= 1 << 18;
1324
1325 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1326
1327 defId(i->def(0), 14);
1328 srcId(i->src(0), 20);
1329 srcId(i, src1, 26);
1330
1331 emitPredicate(i);
1332 }
1333
1334 void
1335 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1336 {
1337 code[0] = 0x00000000 | (laneMask << 6);
1338 code[1] = 0x48000000 | qOp;
1339
1340 defId(i->def(0), 14);
1341 srcId(i->src(0), 20);
1342 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1343
1344 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1345 code[0] |= 1 << 9; // dall
1346
1347 emitPredicate(i);
1348 }
1349
1350 void
1351 CodeEmitterNVC0::emitFlow(const Instruction *i)
1352 {
1353 const FlowInstruction *f = i->asFlow();
1354
1355 unsigned mask; // bit 0: predicate, bit 1: target
1356
1357 code[0] = 0x00000007;
1358
1359 switch (i->op) {
1360 case OP_BRA:
1361 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1362 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1363 code[0] |= 0x4000;
1364 mask = 3;
1365 break;
1366 case OP_CALL:
1367 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1368 if (f->indirect)
1369 code[0] |= 0x4000; // indirect calls always use c[] source
1370 mask = 2;
1371 break;
1372
1373 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1374 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1375 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1376 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1377 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1378
1379 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1380 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1381 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1382 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1383
1384 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1385 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1386 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1387 default:
1388 assert(!"invalid flow operation");
1389 return;
1390 }
1391
1392 if (mask & 1) {
1393 emitPredicate(i);
1394 if (i->flagsSrc < 0)
1395 code[0] |= 0x1e0;
1396 }
1397
1398 if (!f)
1399 return;
1400
1401 if (f->allWarp)
1402 code[0] |= 1 << 15;
1403 if (f->limit)
1404 code[0] |= 1 << 16;
1405
1406 if (f->indirect) {
1407 if (code[0] & 0x4000) {
1408 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1409 setAddress16(i->src(0));
1410 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1411 if (f->op == OP_BRA)
1412 srcId(f->src(0).getIndirect(0), 20);
1413 } else {
1414 srcId(f, 0, 20);
1415 }
1416 }
1417
1418 if (f->op == OP_CALL) {
1419 if (f->indirect) {
1420 // nothing
1421 } else
1422 if (f->builtin) {
1423 assert(f->absolute);
1424 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1425 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1426 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1427 } else {
1428 assert(!f->absolute);
1429 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1430 code[0] |= (pcRel & 0x3f) << 26;
1431 code[1] |= (pcRel >> 6) & 0x3ffff;
1432 }
1433 } else
1434 if (mask & 2) {
1435 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1436 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1437 pcRel += 8;
1438 // currently we don't want absolute branches
1439 assert(!f->absolute);
1440 code[0] |= (pcRel & 0x3f) << 26;
1441 code[1] |= (pcRel >> 6) & 0x3ffff;
1442 }
1443 }
1444
1445 void
1446 CodeEmitterNVC0::emitBAR(const Instruction *i)
1447 {
1448 Value *rDef = NULL, *pDef = NULL;
1449
1450 switch (i->subOp) {
1451 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1452 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1453 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1454 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1455 default:
1456 code[0] = 0x04;
1457 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1458 break;
1459 }
1460 code[1] = 0x50000000;
1461
1462 code[0] |= 63 << 14;
1463 code[1] |= 7 << 21;
1464
1465 emitPredicate(i);
1466
1467 // barrier id
1468 if (i->src(0).getFile() == FILE_GPR) {
1469 srcId(i->src(0), 20);
1470 } else {
1471 ImmediateValue *imm = i->getSrc(0)->asImm();
1472 assert(imm);
1473 code[0] |= imm->reg.data.u32 << 20;
1474 code[1] |= 0x8000;
1475 }
1476
1477 // thread count
1478 if (i->src(1).getFile() == FILE_GPR) {
1479 srcId(i->src(1), 26);
1480 } else {
1481 ImmediateValue *imm = i->getSrc(1)->asImm();
1482 assert(imm);
1483 code[0] |= imm->reg.data.u32 << 26;
1484 code[1] |= imm->reg.data.u32 >> 6;
1485 code[1] |= 0x4000;
1486 }
1487
1488 if (i->srcExists(2) && (i->predSrc != 2)) {
1489 srcId(i->src(2), 32 + 17);
1490 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1491 code[1] |= 1 << 20;
1492 } else {
1493 code[1] |= 7 << 17;
1494 }
1495
1496 if (i->defExists(0)) {
1497 if (i->def(0).getFile() == FILE_GPR)
1498 rDef = i->getDef(0);
1499 else
1500 pDef = i->getDef(0);
1501
1502 if (i->defExists(1)) {
1503 if (i->def(1).getFile() == FILE_GPR)
1504 rDef = i->getDef(1);
1505 else
1506 pDef = i->getDef(1);
1507 }
1508 }
1509 if (rDef) {
1510 code[0] &= ~(63 << 14);
1511 defId(rDef, 14);
1512 }
1513 if (pDef) {
1514 code[1] &= ~(7 << 21);
1515 defId(pDef, 32 + 21);
1516 }
1517 }
1518
1519 void
1520 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1521 {
1522 code[0] = 0x00000006;
1523 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1524
1525 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1526 code[0] |= 0x200;
1527
1528 emitPredicate(i);
1529
1530 defId(i->def(0), 14);
1531 srcId(i->src(0).getIndirect(0), 20);
1532 }
1533
1534 void
1535 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1536 {
1537 uint32_t prim = i->src(0).get()->reg.data.u32;
1538
1539 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1540 code[1] = 0x00000000 | (prim >> 6);
1541
1542 emitPredicate(i);
1543
1544 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1545
1546 defId(i->def(0), 14);
1547 srcId(i, src1, 20);
1548 }
1549
1550 void
1551 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1552 {
1553 code[0] = 0x00000006;
1554 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1555
1556 if (i->perPatch)
1557 code[0] |= 0x100;
1558 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1559 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1560
1561 emitPredicate(i);
1562
1563 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1564
1565 defId(i->def(0), 14);
1566 srcId(i->src(0).getIndirect(0), 20);
1567 srcId(i->src(0).getIndirect(1), 26); // vertex address
1568 }
1569
1570 void
1571 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1572 {
1573 unsigned int size = typeSizeof(i->dType);
1574
1575 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1576 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1577
1578 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1579
1580 if (i->perPatch)
1581 code[0] |= 0x100;
1582
1583 emitPredicate(i);
1584
1585 assert(i->src(1).getFile() == FILE_GPR);
1586
1587 srcId(i->src(0).getIndirect(0), 20);
1588 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1589 srcId(i->src(1), 26);
1590 }
1591
1592 void
1593 CodeEmitterNVC0::emitOUT(const Instruction *i)
1594 {
1595 code[0] = 0x00000006;
1596 code[1] = 0x1c000000;
1597
1598 emitPredicate(i);
1599
1600 defId(i->def(0), 14); // new secret address
1601 srcId(i->src(0), 20); // old secret address, should be 0 initially
1602
1603 assert(i->src(0).getFile() == FILE_GPR);
1604
1605 if (i->op == OP_EMIT)
1606 code[0] |= 1 << 5;
1607 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1608 code[0] |= 1 << 6;
1609
1610 // vertex stream
1611 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1612 unsigned int stream = SDATA(i->src(1)).u32;
1613 assert(stream < 4);
1614 if (stream) {
1615 code[1] |= 0xc000;
1616 code[0] |= stream << 26;
1617 } else {
1618 srcId(NULL, 26);
1619 }
1620 } else {
1621 srcId(i->src(1), 26);
1622 }
1623 }
1624
1625 void
1626 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1627 {
1628 if (i->encSize == 8) {
1629 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1630 } else {
1631 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1632 code[0] |= 0x80;
1633 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1634 }
1635 }
1636
1637 static void
1638 interpApply(const InterpEntry *entry, uint32_t *code,
1639 bool force_persample_interp, bool flatshade)
1640 {
1641 int ipa = entry->ipa;
1642 int reg = entry->reg;
1643 int loc = entry->loc;
1644
1645 if (flatshade &&
1646 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1647 ipa = NV50_IR_INTERP_FLAT;
1648 reg = 0x3f;
1649 } else if (force_persample_interp &&
1650 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1651 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1652 ipa |= NV50_IR_INTERP_CENTROID;
1653 }
1654 code[loc + 0] &= ~(0xf << 6);
1655 code[loc + 0] |= ipa << 6;
1656 code[loc + 0] &= ~(0x3f << 26);
1657 code[loc + 0] |= reg << 26;
1658 }
1659
1660 void
1661 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1662 {
1663 const uint32_t base = i->getSrc(0)->reg.data.offset;
1664
1665 if (i->encSize == 8) {
1666 code[0] = 0x00000000;
1667 code[1] = 0xc0000000 | (base & 0xffff);
1668
1669 if (i->saturate)
1670 code[0] |= 1 << 5;
1671
1672 if (i->op == OP_PINTERP) {
1673 srcId(i->src(1), 26);
1674 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1675 } else {
1676 code[0] |= 0x3f << 26;
1677 addInterp(i->ipa, 0x3f, interpApply);
1678 }
1679
1680 srcId(i->src(0).getIndirect(0), 20);
1681 } else {
1682 assert(i->op == OP_PINTERP);
1683 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1684 srcId(i->src(1), 20);
1685 }
1686 emitInterpMode(i);
1687
1688 emitPredicate(i);
1689 defId(i->def(0), 14);
1690
1691 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1692 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1693 else
1694 code[1] |= 0x3f << 17;
1695 }
1696
1697 void
1698 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1699 {
1700 uint8_t val;
1701
1702 switch (ty) {
1703 case TYPE_U8:
1704 val = 0x00;
1705 break;
1706 case TYPE_S8:
1707 val = 0x20;
1708 break;
1709 case TYPE_F16:
1710 case TYPE_U16:
1711 val = 0x40;
1712 break;
1713 case TYPE_S16:
1714 val = 0x60;
1715 break;
1716 case TYPE_F32:
1717 case TYPE_U32:
1718 case TYPE_S32:
1719 val = 0x80;
1720 break;
1721 case TYPE_F64:
1722 case TYPE_U64:
1723 case TYPE_S64:
1724 val = 0xa0;
1725 break;
1726 case TYPE_B128:
1727 val = 0xc0;
1728 break;
1729 default:
1730 val = 0x80;
1731 assert(!"invalid type");
1732 break;
1733 }
1734 code[0] |= val;
1735 }
1736
1737 void
1738 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1739 {
1740 uint32_t val;
1741
1742 switch (c) {
1743 case CACHE_CA:
1744 // case CACHE_WB:
1745 val = 0x000;
1746 break;
1747 case CACHE_CG:
1748 val = 0x100;
1749 break;
1750 case CACHE_CS:
1751 val = 0x200;
1752 break;
1753 case CACHE_CV:
1754 // case CACHE_WT:
1755 val = 0x300;
1756 break;
1757 default:
1758 val = 0;
1759 assert(!"invalid caching mode");
1760 break;
1761 }
1762 code[0] |= val;
1763 }
1764
1765 static inline bool
1766 uses64bitAddress(const Instruction *ldst)
1767 {
1768 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1769 ldst->src(0).isIndirect(0) &&
1770 ldst->getIndirect(0, 0)->reg.size == 8;
1771 }
1772
1773 void
1774 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1775 {
1776 uint32_t opc;
1777
1778 switch (i->src(0).getFile()) {
1779 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1780 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1781 case FILE_MEMORY_SHARED:
1782 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1783 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1784 opc = 0xb8000000;
1785 else
1786 opc = 0xcc000000;
1787 } else {
1788 opc = 0xc9000000;
1789 }
1790 break;
1791 default:
1792 assert(!"invalid memory file");
1793 opc = 0;
1794 break;
1795 }
1796 code[0] = 0x00000005;
1797 code[1] = opc;
1798
1799 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1800 // Unlocked store on shared memory can fail.
1801 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1802 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1803 assert(i->defExists(0));
1804 defId(i->def(0), 8);
1805 }
1806 }
1807
1808 setAddressByFile(i->src(0));
1809 srcId(i->src(1), 14);
1810 srcId(i->src(0).getIndirect(0), 20);
1811 if (uses64bitAddress(i))
1812 code[1] |= 1 << 26;
1813
1814 emitPredicate(i);
1815
1816 emitLoadStoreType(i->dType);
1817 emitCachingMode(i->cache);
1818 }
1819
1820 void
1821 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1822 {
1823 uint32_t opc;
1824
1825 code[0] = 0x00000005;
1826
1827 switch (i->src(0).getFile()) {
1828 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1829 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1830 case FILE_MEMORY_SHARED:
1831 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1832 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1833 opc = 0xa8000000;
1834 else
1835 opc = 0xc4000000;
1836 } else {
1837 opc = 0xc1000000;
1838 }
1839 break;
1840 case FILE_MEMORY_CONST:
1841 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1842 emitMOV(i); // not sure if this is any better
1843 return;
1844 }
1845 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1846 code[0] = 0x00000006 | (i->subOp << 8);
1847 break;
1848 default:
1849 assert(!"invalid memory file");
1850 opc = 0;
1851 break;
1852 }
1853 code[1] = opc;
1854
1855 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1856 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1857 assert(i->defExists(1));
1858 defId(i->def(1), 32 + 18);
1859 }
1860 }
1861
1862 defId(i->def(0), 14);
1863
1864 setAddressByFile(i->src(0));
1865 srcId(i->src(0).getIndirect(0), 20);
1866 if (uses64bitAddress(i))
1867 code[1] |= 1 << 26;
1868
1869 emitPredicate(i);
1870
1871 emitLoadStoreType(i->dType);
1872 emitCachingMode(i->cache);
1873 }
1874
1875 uint8_t
1876 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1877 {
1878 switch (SDATA(ref).sv.sv) {
1879 case SV_LANEID: return 0x00;
1880 case SV_PHYSID: return 0x03;
1881 case SV_VERTEX_COUNT: return 0x10;
1882 case SV_INVOCATION_ID: return 0x11;
1883 case SV_YDIR: return 0x12;
1884 case SV_THREAD_KILL: return 0x13;
1885 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1886 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1887 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1888 case SV_GRIDID: return 0x2c;
1889 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1890 case SV_LBASE: return 0x34;
1891 case SV_SBASE: return 0x30;
1892 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1893 default:
1894 assert(!"no sreg for system value");
1895 return 0;
1896 }
1897 }
1898
1899 void
1900 CodeEmitterNVC0::emitMOV(const Instruction *i)
1901 {
1902 if (i->def(0).getFile() == FILE_PREDICATE) {
1903 if (i->src(0).getFile() == FILE_GPR) {
1904 code[0] = 0xfc01c003;
1905 code[1] = 0x1a8e0000;
1906 srcId(i->src(0), 20);
1907 } else {
1908 code[0] = 0x0001c004;
1909 code[1] = 0x0c0e0000;
1910 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1911 code[0] |= 7 << 20;
1912 if (!i->getSrc(0)->reg.data.u32)
1913 code[0] |= 1 << 23;
1914 } else {
1915 srcId(i->src(0), 20);
1916 }
1917 }
1918 defId(i->def(0), 17);
1919 emitPredicate(i);
1920 } else
1921 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1922 uint8_t sr = getSRegEncoding(i->src(0));
1923
1924 if (i->encSize == 8) {
1925 code[0] = 0x00000004 | (sr << 26);
1926 code[1] = 0x2c000000;
1927 } else {
1928 code[0] = 0x40000008 | (sr << 20);
1929 }
1930 defId(i->def(0), 14);
1931
1932 emitPredicate(i);
1933 } else
1934 if (i->encSize == 8) {
1935 uint64_t opc;
1936
1937 if (i->src(0).getFile() == FILE_IMMEDIATE)
1938 opc = HEX64(18000000, 000001e2);
1939 else
1940 if (i->src(0).getFile() == FILE_PREDICATE)
1941 opc = HEX64(080e0000, 1c000004);
1942 else
1943 opc = HEX64(28000000, 00000004);
1944
1945 opc |= i->lanes << 5;
1946
1947 emitForm_B(i, opc);
1948 } else {
1949 uint32_t imm;
1950
1951 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1952 imm = SDATA(i->src(0)).u32;
1953 if (imm & 0xfff00000) {
1954 assert(!(imm & 0x000fffff));
1955 code[0] = 0x00000318 | imm;
1956 } else {
1957 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1958 code[0] = 0x00000118 | (imm << 20);
1959 }
1960 } else {
1961 code[0] = 0x0028;
1962 emitShortSrc2(i->src(0));
1963 }
1964 defId(i->def(0), 14);
1965
1966 emitPredicate(i);
1967 }
1968 }
1969
1970 void
1971 CodeEmitterNVC0::emitATOM(const Instruction *i)
1972 {
1973 const bool hasDst = i->defExists(0);
1974 const bool casOrExch =
1975 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1976 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1977
1978 if (i->dType == TYPE_U64) {
1979 switch (i->subOp) {
1980 case NV50_IR_SUBOP_ATOM_ADD:
1981 code[0] = 0x205;
1982 if (hasDst)
1983 code[1] = 0x507e0000;
1984 else
1985 code[1] = 0x10000000;
1986 break;
1987 case NV50_IR_SUBOP_ATOM_EXCH:
1988 code[0] = 0x305;
1989 code[1] = 0x507e0000;
1990 break;
1991 case NV50_IR_SUBOP_ATOM_CAS:
1992 code[0] = 0x325;
1993 code[1] = 0x50000000;
1994 break;
1995 default:
1996 assert(!"invalid u64 red op");
1997 break;
1998 }
1999 } else
2000 if (i->dType == TYPE_U32) {
2001 switch (i->subOp) {
2002 case NV50_IR_SUBOP_ATOM_EXCH:
2003 code[0] = 0x105;
2004 code[1] = 0x507e0000;
2005 break;
2006 case NV50_IR_SUBOP_ATOM_CAS:
2007 code[0] = 0x125;
2008 code[1] = 0x50000000;
2009 break;
2010 default:
2011 code[0] = 0x5 | (i->subOp << 5);
2012 if (hasDst)
2013 code[1] = 0x507e0000;
2014 else
2015 code[1] = 0x10000000;
2016 break;
2017 }
2018 } else
2019 if (i->dType == TYPE_S32) {
2020 assert(i->subOp <= 2);
2021 code[0] = 0x205 | (i->subOp << 5);
2022 if (hasDst)
2023 code[1] = 0x587e0000;
2024 else
2025 code[1] = 0x18000000;
2026 } else
2027 if (i->dType == TYPE_F32) {
2028 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2029 code[0] = 0x205;
2030 if (hasDst)
2031 code[1] = 0x687e0000;
2032 else
2033 code[1] = 0x28000000;
2034 }
2035
2036 emitPredicate(i);
2037
2038 srcId(i->src(1), 14);
2039
2040 if (hasDst)
2041 defId(i->def(0), 32 + 11);
2042 else
2043 if (casOrExch)
2044 code[1] |= 63 << 11;
2045
2046 if (hasDst || casOrExch) {
2047 const int32_t offset = SDATA(i->src(0)).offset;
2048 assert(offset < 0x80000 && offset >= -0x80000);
2049 code[0] |= offset << 26;
2050 code[1] |= (offset & 0x1ffc0) >> 6;
2051 code[1] |= (offset & 0xe0000) << 6;
2052 } else {
2053 srcAddr32(i->src(0), 26, 0);
2054 }
2055 if (i->getIndirect(0, 0)) {
2056 srcId(i->getIndirect(0, 0), 20);
2057 if (i->getIndirect(0, 0)->reg.size == 8)
2058 code[1] |= 1 << 26;
2059 } else {
2060 code[0] |= 63 << 20;
2061 }
2062
2063 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2064 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2065 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2066 }
2067 }
2068
2069 void
2070 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2071 {
2072 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2073 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2074 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2075 default:
2076 code[0] = 0x45;
2077 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2078 break;
2079 }
2080 code[1] = 0xe0000000;
2081
2082 emitPredicate(i);
2083 }
2084
2085 void
2086 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2087 {
2088 code[0] = 0x00000005 | (i->subOp << 5);
2089
2090 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2091 code[1] = 0x98000000;
2092 srcAddr32(i->src(0), 28, 2);
2093 } else {
2094 code[1] = 0xd0000000;
2095 setAddress24(i->src(0));
2096 }
2097 if (uses64bitAddress(i))
2098 code[1] |= 1 << 26;
2099 srcId(i->src(0).getIndirect(0), 20);
2100
2101 emitPredicate(i);
2102
2103 defId(i, 0, 14);
2104 }
2105
2106 void
2107 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2108 {
2109 uint8_t m;
2110 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2111 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2112 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2113 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2114 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2115 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2116 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2117 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2118 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2119 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2120 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2121 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2122 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2123 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2124 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2125 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2126 default:
2127 return;
2128 }
2129 code[0] |= m << 5;
2130 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2131 code[1] |= 1 << 16;
2132 }
2133
2134 void
2135 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2136 {
2137 ImmediateValue *imm = NULL;
2138 uint64_t opc;
2139
2140 if (i->srcExists(2)) {
2141 imm = i->getSrc(2)->asImm();
2142 if (imm)
2143 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2144 }
2145
2146 switch (i->op) {
2147 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2148 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2149 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2150 default:
2151 assert(0);
2152 return;
2153 }
2154 emitForm_A(i, opc);
2155
2156 if (i->op == OP_SUCLAMP) {
2157 if (i->dType == TYPE_S32)
2158 code[0] |= 1 << 9;
2159 emitSUCLAMPMode(i->subOp);
2160 }
2161
2162 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2163 code[1] |= 1 << 16;
2164
2165 if (i->op != OP_SUEAU) {
2166 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2167 code[0] |= 63 << 14;
2168 code[1] |= i->getDef(0)->reg.data.id << 23;
2169 } else
2170 if (i->defExists(1)) { // r, p
2171 assert(i->def(1).getFile() == FILE_PREDICATE);
2172 code[1] |= i->getDef(1)->reg.data.id << 23;
2173 } else { // r, #
2174 code[1] |= 7 << 23;
2175 }
2176 }
2177 if (imm) {
2178 assert(i->op == OP_SUCLAMP);
2179 i->setSrc(2, imm);
2180 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2181 }
2182 }
2183
2184 void
2185 CodeEmitterNVC0::emitSUGType(DataType ty)
2186 {
2187 switch (ty) {
2188 case TYPE_S32: code[1] |= 1 << 13; break;
2189 case TYPE_U8: code[1] |= 2 << 13; break;
2190 case TYPE_S8: code[1] |= 3 << 13; break;
2191 default:
2192 assert(ty == TYPE_U32);
2193 break;
2194 }
2195 }
2196
2197 void
2198 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2199 {
2200 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2201
2202 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2203 assert(offset == (offset & 0xfffc));
2204
2205 code[1] |= 1 << 21;
2206 code[0] |= offset << 24;
2207 code[1] |= offset >> 8;
2208 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2209 }
2210
2211 void
2212 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2213 {
2214 if (!i->srcExists(s) || (i->predSrc == s)) {
2215 code[1] |= 0x7 << 17;
2216 } else {
2217 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2218 code[1] |= 1 << 20;
2219 srcId(i->src(s), 32 + 17);
2220 }
2221 }
2222
2223 void
2224 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2225 {
2226 code[0] = 0x5;
2227 code[1] = 0xd4000000 | (i->subOp << 15);
2228
2229 emitLoadStoreType(i->dType);
2230 emitSUGType(i->sType);
2231 emitCachingMode(i->cache);
2232
2233 emitPredicate(i);
2234 defId(i->def(0), 14); // destination
2235 srcId(i->src(0), 20); // address
2236 // format
2237 if (i->src(1).getFile() == FILE_GPR)
2238 srcId(i->src(1), 26);
2239 else
2240 setSUConst16(i, 1);
2241 setSUPred(i, 2);
2242 }
2243
2244 void
2245 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2246 {
2247 code[0] = 0x5;
2248 code[1] = 0xdc000000 | (i->subOp << 15);
2249
2250 if (i->op == OP_SUSTP)
2251 code[1] |= i->tex.mask << 22;
2252 else
2253 emitLoadStoreType(i->dType);
2254 emitSUGType(i->sType);
2255 emitCachingMode(i->cache);
2256
2257 emitPredicate(i);
2258 srcId(i->src(0), 20); // address
2259 // format
2260 if (i->src(1).getFile() == FILE_GPR)
2261 srcId(i->src(1), 26);
2262 else
2263 setSUConst16(i, 1);
2264 srcId(i->src(3), 14); // values
2265 setSUPred(i, 2);
2266 }
2267
2268 void
2269 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2270 {
2271 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2272 case 0:
2273 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2274 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2275 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2276 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2277 break;
2278 case 1:
2279 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2280 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2281 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2282 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2283 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2284 code[1] |= (i->mask & 0x3) << 2;
2285 break;
2286 case 2:
2287 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2288 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2289 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2290 code[1] |= (i->mask & 0x3) << 2;
2291 code[1] |= (i->mask & 0xc) << 21;
2292 break;
2293 default:
2294 assert(0);
2295 break;
2296 }
2297 }
2298
2299 void
2300 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2301 {
2302 uint64_t opc = 0x4;
2303
2304 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2305 case 0: opc |= 0xe8ULL << 56; break;
2306 case 1: opc |= 0xb4ULL << 56; break;
2307 case 2: opc |= 0x94ULL << 56; break;
2308 default:
2309 assert(0);
2310 break;
2311 }
2312 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2313 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2314 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2315 } else {
2316 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2317 if (isSignedType(i->sType)) opc |= 1 << 6;
2318 }
2319 emitForm_A(i, opc);
2320 emitVectorSubOp(i);
2321
2322 if (i->saturate)
2323 code[0] |= 1 << 9;
2324 if (i->flagsDef >= 0)
2325 code[1] |= 1 << 16;
2326 }
2327
2328 void
2329 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2330 {
2331 assert(i->encSize == 8);
2332 emitForm_A(i, HEX64(10000000, 00000006));
2333 code[0] |= i->subOp << 5;
2334 code[1] |= 0x00e00000;
2335 }
2336
2337 bool
2338 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2339 {
2340 unsigned int size = insn->encSize;
2341
2342 if (writeIssueDelays && !(codeSize & 0x3f))
2343 size += 8;
2344
2345 if (!insn->encSize) {
2346 ERROR("skipping unencodable instruction: "); insn->print();
2347 return false;
2348 } else
2349 if (codeSize + size > codeSizeLimit) {
2350 ERROR("code emitter output buffer too small\n");
2351 return false;
2352 }
2353
2354 if (writeIssueDelays) {
2355 if (!(codeSize & 0x3f)) {
2356 code[0] = 0x00000007; // cf issue delay "instruction"
2357 code[1] = 0x20000000;
2358 code += 2;
2359 codeSize += 8;
2360 }
2361 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2362 uint32_t *data = code - (id * 2 + 2);
2363 if (id <= 2) {
2364 data[0] |= insn->sched << (id * 8 + 4);
2365 } else
2366 if (id == 3) {
2367 data[0] |= insn->sched << 28;
2368 data[1] |= insn->sched >> 4;
2369 } else {
2370 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2371 }
2372 }
2373
2374 // assert that instructions with multiple defs don't corrupt registers
2375 for (int d = 0; insn->defExists(d); ++d)
2376 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2377
2378 switch (insn->op) {
2379 case OP_MOV:
2380 case OP_RDSV:
2381 emitMOV(insn);
2382 break;
2383 case OP_NOP:
2384 break;
2385 case OP_LOAD:
2386 emitLOAD(insn);
2387 break;
2388 case OP_STORE:
2389 emitSTORE(insn);
2390 break;
2391 case OP_LINTERP:
2392 case OP_PINTERP:
2393 emitINTERP(insn);
2394 break;
2395 case OP_VFETCH:
2396 emitVFETCH(insn);
2397 break;
2398 case OP_EXPORT:
2399 emitEXPORT(insn);
2400 break;
2401 case OP_PFETCH:
2402 emitPFETCH(insn);
2403 break;
2404 case OP_AFETCH:
2405 emitAFETCH(insn);
2406 break;
2407 case OP_EMIT:
2408 case OP_RESTART:
2409 emitOUT(insn);
2410 break;
2411 case OP_ADD:
2412 case OP_SUB:
2413 if (insn->dType == TYPE_F64)
2414 emitDADD(insn);
2415 else if (isFloatType(insn->dType))
2416 emitFADD(insn);
2417 else
2418 emitUADD(insn);
2419 break;
2420 case OP_MUL:
2421 if (insn->dType == TYPE_F64)
2422 emitDMUL(insn);
2423 else if (isFloatType(insn->dType))
2424 emitFMUL(insn);
2425 else
2426 emitUMUL(insn);
2427 break;
2428 case OP_MAD:
2429 case OP_FMA:
2430 if (insn->dType == TYPE_F64)
2431 emitDMAD(insn);
2432 else if (isFloatType(insn->dType))
2433 emitFMAD(insn);
2434 else
2435 emitIMAD(insn);
2436 break;
2437 case OP_SAD:
2438 emitISAD(insn);
2439 break;
2440 case OP_NOT:
2441 emitNOT(insn);
2442 break;
2443 case OP_AND:
2444 emitLogicOp(insn, 0);
2445 break;
2446 case OP_OR:
2447 emitLogicOp(insn, 1);
2448 break;
2449 case OP_XOR:
2450 emitLogicOp(insn, 2);
2451 break;
2452 case OP_SHL:
2453 case OP_SHR:
2454 emitShift(insn);
2455 break;
2456 case OP_SET:
2457 case OP_SET_AND:
2458 case OP_SET_OR:
2459 case OP_SET_XOR:
2460 emitSET(insn->asCmp());
2461 break;
2462 case OP_SELP:
2463 emitSELP(insn);
2464 break;
2465 case OP_SLCT:
2466 emitSLCT(insn->asCmp());
2467 break;
2468 case OP_MIN:
2469 case OP_MAX:
2470 emitMINMAX(insn);
2471 break;
2472 case OP_ABS:
2473 case OP_NEG:
2474 case OP_CEIL:
2475 case OP_FLOOR:
2476 case OP_TRUNC:
2477 case OP_SAT:
2478 emitCVT(insn);
2479 break;
2480 case OP_CVT:
2481 if (insn->def(0).getFile() == FILE_PREDICATE ||
2482 insn->src(0).getFile() == FILE_PREDICATE)
2483 emitMOV(insn);
2484 else
2485 emitCVT(insn);
2486 break;
2487 case OP_RSQ:
2488 emitSFnOp(insn, 5 + 2 * insn->subOp);
2489 break;
2490 case OP_RCP:
2491 emitSFnOp(insn, 4 + 2 * insn->subOp);
2492 break;
2493 case OP_LG2:
2494 emitSFnOp(insn, 3);
2495 break;
2496 case OP_EX2:
2497 emitSFnOp(insn, 2);
2498 break;
2499 case OP_SIN:
2500 emitSFnOp(insn, 1);
2501 break;
2502 case OP_COS:
2503 emitSFnOp(insn, 0);
2504 break;
2505 case OP_PRESIN:
2506 case OP_PREEX2:
2507 emitPreOp(insn);
2508 break;
2509 case OP_TEX:
2510 case OP_TXB:
2511 case OP_TXL:
2512 case OP_TXD:
2513 case OP_TXF:
2514 case OP_TXG:
2515 case OP_TXLQ:
2516 emitTEX(insn->asTex());
2517 break;
2518 case OP_TXQ:
2519 emitTXQ(insn->asTex());
2520 break;
2521 case OP_TEXBAR:
2522 emitTEXBAR(insn);
2523 break;
2524 case OP_SUBFM:
2525 case OP_SUCLAMP:
2526 case OP_SUEAU:
2527 emitSUCalc(insn);
2528 break;
2529 case OP_MADSP:
2530 emitMADSP(insn);
2531 break;
2532 case OP_SULDB:
2533 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2534 emitSULDGB(insn->asTex());
2535 else
2536 ERROR("SULDB not yet supported on < nve4\n");
2537 break;
2538 case OP_SUSTB:
2539 case OP_SUSTP:
2540 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2541 emitSUSTGx(insn->asTex());
2542 else
2543 ERROR("SUSTx not yet supported on < nve4\n");
2544 break;
2545 case OP_ATOM:
2546 emitATOM(insn);
2547 break;
2548 case OP_BRA:
2549 case OP_CALL:
2550 case OP_PRERET:
2551 case OP_RET:
2552 case OP_DISCARD:
2553 case OP_EXIT:
2554 case OP_PRECONT:
2555 case OP_CONT:
2556 case OP_PREBREAK:
2557 case OP_BREAK:
2558 case OP_JOINAT:
2559 case OP_BRKPT:
2560 case OP_QUADON:
2561 case OP_QUADPOP:
2562 emitFlow(insn);
2563 break;
2564 case OP_QUADOP:
2565 emitQUADOP(insn, insn->subOp, insn->lanes);
2566 break;
2567 case OP_DFDX:
2568 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2569 break;
2570 case OP_DFDY:
2571 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2572 break;
2573 case OP_POPCNT:
2574 emitPOPC(insn);
2575 break;
2576 case OP_INSBF:
2577 emitINSBF(insn);
2578 break;
2579 case OP_EXTBF:
2580 emitEXTBF(insn);
2581 break;
2582 case OP_BFIND:
2583 emitBFIND(insn);
2584 break;
2585 case OP_PERMT:
2586 emitPERMT(insn);
2587 break;
2588 case OP_JOIN:
2589 emitNOP(insn);
2590 insn->join = 1;
2591 break;
2592 case OP_BAR:
2593 emitBAR(insn);
2594 break;
2595 case OP_MEMBAR:
2596 emitMEMBAR(insn);
2597 break;
2598 case OP_CCTL:
2599 emitCCTL(insn);
2600 break;
2601 case OP_VSHL:
2602 emitVSHL(insn);
2603 break;
2604 case OP_PIXLD:
2605 emitPIXLD(insn);
2606 break;
2607 case OP_PHI:
2608 case OP_UNION:
2609 case OP_CONSTRAINT:
2610 ERROR("operation should have been eliminated");
2611 return false;
2612 case OP_EXP:
2613 case OP_LOG:
2614 case OP_SQRT:
2615 case OP_POW:
2616 ERROR("operation should have been lowered\n");
2617 return false;
2618 default:
2619 ERROR("unknown op: %u\n", insn->op);
2620 return false;
2621 }
2622
2623 if (insn->join) {
2624 code[0] |= 0x10;
2625 assert(insn->encSize == 8);
2626 }
2627
2628 code += insn->encSize / 4;
2629 codeSize += insn->encSize;
2630 return true;
2631 }
2632
2633 uint32_t
2634 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2635 {
2636 const Target::OpInfo &info = targ->getOpInfo(i);
2637
2638 if (writeIssueDelays || info.minEncSize == 8 || 1)
2639 return 8;
2640
2641 if (i->ftz || i->saturate || i->join)
2642 return 8;
2643 if (i->rnd != ROUND_N)
2644 return 8;
2645 if (i->predSrc >= 0 && i->op == OP_MAD)
2646 return 8;
2647
2648 if (i->op == OP_PINTERP) {
2649 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2650 return 8;
2651 } else
2652 if (i->op == OP_MOV && i->lanes != 0xf) {
2653 return 8;
2654 }
2655
2656 for (int s = 0; i->srcExists(s); ++s) {
2657 if (i->src(s).isIndirect(0))
2658 return 8;
2659
2660 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2661 if (SDATA(i->src(s)).offset >= 0x100)
2662 return 8;
2663 if (i->getSrc(s)->reg.fileIndex > 1 &&
2664 i->getSrc(s)->reg.fileIndex != 16)
2665 return 8;
2666 } else
2667 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2668 if (i->dType == TYPE_F32) {
2669 if (SDATA(i->src(s)).u32 >= 0x100)
2670 return 8;
2671 } else {
2672 if (SDATA(i->src(s)).u32 > 0xff)
2673 return 8;
2674 }
2675 }
2676
2677 if (i->op == OP_CVT)
2678 continue;
2679 if (i->src(s).mod != Modifier(0)) {
2680 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2681 if (i->op != OP_RSQ)
2682 return 8;
2683 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2684 if (i->op != OP_ADD || s != 0)
2685 return 8;
2686 }
2687 }
2688
2689 return 4;
2690 }
2691
2692 // Simplified, erring on safe side.
2693 class SchedDataCalculator : public Pass
2694 {
2695 public:
2696 SchedDataCalculator(const Target *targ) : targ(targ) { }
2697
2698 private:
2699 struct RegScores
2700 {
2701 struct Resource {
2702 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2703 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2704 int tex; // TEX to non-TEX delay 17 (0x11)
2705 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2706 int imul; // integer MUL to MUL delay 3
2707 } res;
2708 struct ScoreData {
2709 int r[256];
2710 int p[8];
2711 int c;
2712 } rd, wr;
2713 int base;
2714 int regs;
2715
2716 void rebase(const int base)
2717 {
2718 const int delta = this->base - base;
2719 if (!delta)
2720 return;
2721 this->base = 0;
2722
2723 for (int i = 0; i < regs; ++i) {
2724 rd.r[i] += delta;
2725 wr.r[i] += delta;
2726 }
2727 for (int i = 0; i < 8; ++i) {
2728 rd.p[i] += delta;
2729 wr.p[i] += delta;
2730 }
2731 rd.c += delta;
2732 wr.c += delta;
2733
2734 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2735 res.ld[f] += delta;
2736 res.st[f] += delta;
2737 }
2738 res.sfu += delta;
2739 res.imul += delta;
2740 res.tex += delta;
2741 }
2742 void wipe(int regs)
2743 {
2744 memset(&rd, 0, sizeof(rd));
2745 memset(&wr, 0, sizeof(wr));
2746 memset(&res, 0, sizeof(res));
2747 this->regs = regs;
2748 }
2749 int getLatest(const ScoreData& d) const
2750 {
2751 int max = 0;
2752 for (int i = 0; i < regs; ++i)
2753 if (d.r[i] > max)
2754 max = d.r[i];
2755 for (int i = 0; i < 8; ++i)
2756 if (d.p[i] > max)
2757 max = d.p[i];
2758 if (d.c > max)
2759 max = d.c;
2760 return max;
2761 }
2762 inline int getLatestRd() const
2763 {
2764 return getLatest(rd);
2765 }
2766 inline int getLatestWr() const
2767 {
2768 return getLatest(wr);
2769 }
2770 inline int getLatest() const
2771 {
2772 const int a = getLatestRd();
2773 const int b = getLatestWr();
2774
2775 int max = MAX2(a, b);
2776 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2777 max = MAX2(res.ld[f], max);
2778 max = MAX2(res.st[f], max);
2779 }
2780 max = MAX2(res.sfu, max);
2781 max = MAX2(res.imul, max);
2782 max = MAX2(res.tex, max);
2783 return max;
2784 }
2785 void setMax(const RegScores *that)
2786 {
2787 for (int i = 0; i < regs; ++i) {
2788 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2789 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2790 }
2791 for (int i = 0; i < 8; ++i) {
2792 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2793 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2794 }
2795 rd.c = MAX2(rd.c, that->rd.c);
2796 wr.c = MAX2(wr.c, that->wr.c);
2797
2798 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2799 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2800 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2801 }
2802 res.sfu = MAX2(res.sfu, that->res.sfu);
2803 res.imul = MAX2(res.imul, that->res.imul);
2804 res.tex = MAX2(res.tex, that->res.tex);
2805 }
2806 void print(int cycle)
2807 {
2808 for (int i = 0; i < regs; ++i) {
2809 if (rd.r[i] > cycle)
2810 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2811 if (wr.r[i] > cycle)
2812 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2813 }
2814 for (int i = 0; i < 8; ++i) {
2815 if (rd.p[i] > cycle)
2816 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2817 if (wr.p[i] > cycle)
2818 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2819 }
2820 if (rd.c > cycle)
2821 INFO("rd $c @ %i\n", rd.c);
2822 if (wr.c > cycle)
2823 INFO("wr $c @ %i\n", wr.c);
2824 if (res.sfu > cycle)
2825 INFO("sfu @ %i\n", res.sfu);
2826 if (res.imul > cycle)
2827 INFO("imul @ %i\n", res.imul);
2828 if (res.tex > cycle)
2829 INFO("tex @ %i\n", res.tex);
2830 }
2831 };
2832
2833 RegScores *score; // for current BB
2834 std::vector<RegScores> scoreBoards;
2835 int prevData;
2836 operation prevOp;
2837
2838 const Target *targ;
2839
2840 bool visit(Function *);
2841 bool visit(BasicBlock *);
2842
2843 void commitInsn(const Instruction *, int cycle);
2844 int calcDelay(const Instruction *, int cycle) const;
2845 void setDelay(Instruction *, int delay, Instruction *next);
2846
2847 void recordRd(const Value *, const int ready);
2848 void recordWr(const Value *, const int ready);
2849 void checkRd(const Value *, int cycle, int& delay) const;
2850 void checkWr(const Value *, int cycle, int& delay) const;
2851
2852 int getCycles(const Instruction *, int origDelay) const;
2853 };
2854
2855 void
2856 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2857 {
2858 if (insn->op == OP_EXIT || insn->op == OP_RET)
2859 delay = MAX2(delay, 14);
2860
2861 if (insn->op == OP_TEXBAR) {
2862 // TODO: except if results not used before EXIT
2863 insn->sched = 0xc2;
2864 } else
2865 if (insn->op == OP_JOIN || insn->join) {
2866 insn->sched = 0x00;
2867 } else
2868 if (delay >= 0 || prevData == 0x04 ||
2869 !next || !targ->canDualIssue(insn, next)) {
2870 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2871 if (prevOp == OP_EXPORT)
2872 insn->sched |= 0x40;
2873 else
2874 insn->sched |= 0x20;
2875 } else {
2876 insn->sched = 0x04; // dual-issue
2877 }
2878
2879 if (prevData != 0x04 || prevOp != OP_EXPORT)
2880 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2881 prevOp = insn->op;
2882
2883 prevData = insn->sched;
2884 }
2885
2886 int
2887 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2888 {
2889 if (insn->sched & 0x80) {
2890 int c = (insn->sched & 0x0f) * 2 + 1;
2891 if (insn->op == OP_TEXBAR && origDelay > 0)
2892 c += origDelay;
2893 return c;
2894 }
2895 if (insn->sched & 0x60)
2896 return (insn->sched & 0x1f) + 1;
2897 return (insn->sched == 0x04) ? 0 : 32;
2898 }
2899
2900 bool
2901 SchedDataCalculator::visit(Function *func)
2902 {
2903 int regs = targ->getFileSize(FILE_GPR) + 1;
2904 scoreBoards.resize(func->cfg.getSize());
2905 for (size_t i = 0; i < scoreBoards.size(); ++i)
2906 scoreBoards[i].wipe(regs);
2907 return true;
2908 }
2909
2910 bool
2911 SchedDataCalculator::visit(BasicBlock *bb)
2912 {
2913 Instruction *insn;
2914 Instruction *next = NULL;
2915
2916 int cycle = 0;
2917
2918 prevData = 0x00;
2919 prevOp = OP_NOP;
2920 score = &scoreBoards.at(bb->getId());
2921
2922 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2923 // back branches will wait until all target dependencies are satisfied
2924 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2925 continue;
2926 BasicBlock *in = BasicBlock::get(ei.getNode());
2927 if (in->getExit()) {
2928 if (prevData != 0x04)
2929 prevData = in->getExit()->sched;
2930 prevOp = in->getExit()->op;
2931 }
2932 score->setMax(&scoreBoards.at(in->getId()));
2933 }
2934 if (bb->cfg.incidentCount() > 1)
2935 prevOp = OP_NOP;
2936
2937 #ifdef NVC0_DEBUG_SCHED_DATA
2938 INFO("=== BB:%i initial scores\n", bb->getId());
2939 score->print(cycle);
2940 #endif
2941
2942 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2943 next = insn->next;
2944
2945 commitInsn(insn, cycle);
2946 int delay = calcDelay(next, cycle);
2947 setDelay(insn, delay, next);
2948 cycle += getCycles(insn, delay);
2949
2950 #ifdef NVC0_DEBUG_SCHED_DATA
2951 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2952 insn->print();
2953 next->print();
2954 #endif
2955 }
2956 if (!insn)
2957 return true;
2958 commitInsn(insn, cycle);
2959
2960 int bbDelay = -1;
2961
2962 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2963 BasicBlock *out = BasicBlock::get(ei.getNode());
2964
2965 if (ei.getType() != Graph::Edge::BACK) {
2966 // only test the first instruction of the outgoing block
2967 next = out->getEntry();
2968 if (next)
2969 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2970 } else {
2971 // wait until all dependencies are satisfied
2972 const int regsFree = score->getLatest();
2973 next = out->getFirst();
2974 for (int c = cycle; next && c < regsFree; next = next->next) {
2975 bbDelay = MAX2(bbDelay, calcDelay(next, c));
2976 c += getCycles(next, bbDelay);
2977 }
2978 next = NULL;
2979 }
2980 }
2981 if (bb->cfg.outgoingCount() != 1)
2982 next = NULL;
2983 setDelay(insn, bbDelay, next);
2984 cycle += getCycles(insn, bbDelay);
2985
2986 score->rebase(cycle); // common base for initializing out blocks' scores
2987 return true;
2988 }
2989
2990 #define NVE4_MAX_ISSUE_DELAY 0x1f
2991 int
2992 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
2993 {
2994 int delay = 0, ready = cycle;
2995
2996 for (int s = 0; insn->srcExists(s); ++s)
2997 checkRd(insn->getSrc(s), cycle, delay);
2998 // WAR & WAW don't seem to matter
2999 // for (int s = 0; insn->srcExists(s); ++s)
3000 // recordRd(insn->getSrc(s), cycle);
3001
3002 switch (Target::getOpClass(insn->op)) {
3003 case OPCLASS_SFU:
3004 ready = score->res.sfu;
3005 break;
3006 case OPCLASS_ARITH:
3007 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3008 ready = score->res.imul;
3009 break;
3010 case OPCLASS_TEXTURE:
3011 ready = score->res.tex;
3012 break;
3013 case OPCLASS_LOAD:
3014 ready = score->res.ld[insn->src(0).getFile()];
3015 break;
3016 case OPCLASS_STORE:
3017 ready = score->res.st[insn->src(0).getFile()];
3018 break;
3019 default:
3020 break;
3021 }
3022 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3023 ready = MAX2(ready, score->res.tex);
3024
3025 delay = MAX2(delay, ready - cycle);
3026
3027 // if can issue next cycle, delay is 0, not 1
3028 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3029 }
3030
3031 void
3032 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3033 {
3034 const int ready = cycle + targ->getLatency(insn);
3035
3036 for (int d = 0; insn->defExists(d); ++d)
3037 recordWr(insn->getDef(d), ready);
3038 // WAR & WAW don't seem to matter
3039 // for (int s = 0; insn->srcExists(s); ++s)
3040 // recordRd(insn->getSrc(s), cycle);
3041
3042 switch (Target::getOpClass(insn->op)) {
3043 case OPCLASS_SFU:
3044 score->res.sfu = cycle + 4;
3045 break;
3046 case OPCLASS_ARITH:
3047 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3048 score->res.imul = cycle + 4;
3049 break;
3050 case OPCLASS_TEXTURE:
3051 score->res.tex = cycle + 18;
3052 break;
3053 case OPCLASS_LOAD:
3054 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3055 break;
3056 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3057 score->res.st[insn->src(0).getFile()] = ready;
3058 break;
3059 case OPCLASS_STORE:
3060 score->res.st[insn->src(0).getFile()] = cycle + 4;
3061 score->res.ld[insn->src(0).getFile()] = ready;
3062 break;
3063 case OPCLASS_OTHER:
3064 if (insn->op == OP_TEXBAR)
3065 score->res.tex = cycle;
3066 break;
3067 default:
3068 break;
3069 }
3070
3071 #ifdef NVC0_DEBUG_SCHED_DATA
3072 score->print(cycle);
3073 #endif
3074 }
3075
3076 void
3077 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3078 {
3079 int ready = cycle;
3080 int a, b;
3081
3082 switch (v->reg.file) {
3083 case FILE_GPR:
3084 a = v->reg.data.id;
3085 b = a + v->reg.size / 4;
3086 for (int r = a; r < b; ++r)
3087 ready = MAX2(ready, score->rd.r[r]);
3088 break;
3089 case FILE_PREDICATE:
3090 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3091 break;
3092 case FILE_FLAGS:
3093 ready = MAX2(ready, score->rd.c);
3094 break;
3095 case FILE_SHADER_INPUT:
3096 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3097 case FILE_MEMORY_LOCAL:
3098 case FILE_MEMORY_CONST:
3099 case FILE_MEMORY_SHARED:
3100 case FILE_MEMORY_GLOBAL:
3101 case FILE_SYSTEM_VALUE:
3102 // TODO: any restrictions here ?
3103 break;
3104 case FILE_IMMEDIATE:
3105 break;
3106 default:
3107 assert(0);
3108 break;
3109 }
3110 if (cycle < ready)
3111 delay = MAX2(delay, ready - cycle);
3112 }
3113
3114 void
3115 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3116 {
3117 int ready = cycle;
3118 int a, b;
3119
3120 switch (v->reg.file) {
3121 case FILE_GPR:
3122 a = v->reg.data.id;
3123 b = a + v->reg.size / 4;
3124 for (int r = a; r < b; ++r)
3125 ready = MAX2(ready, score->wr.r[r]);
3126 break;
3127 case FILE_PREDICATE:
3128 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3129 break;
3130 default:
3131 assert(v->reg.file == FILE_FLAGS);
3132 ready = MAX2(ready, score->wr.c);
3133 break;
3134 }
3135 if (cycle < ready)
3136 delay = MAX2(delay, ready - cycle);
3137 }
3138
3139 void
3140 SchedDataCalculator::recordWr(const Value *v, const int ready)
3141 {
3142 int a = v->reg.data.id;
3143
3144 if (v->reg.file == FILE_GPR) {
3145 int b = a + v->reg.size / 4;
3146 for (int r = a; r < b; ++r)
3147 score->rd.r[r] = ready;
3148 } else
3149 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3150 if (v->reg.file == FILE_PREDICATE) {
3151 score->rd.p[a] = ready + 4;
3152 } else {
3153 assert(v->reg.file == FILE_FLAGS);
3154 score->rd.c = ready + 4;
3155 }
3156 }
3157
3158 void
3159 SchedDataCalculator::recordRd(const Value *v, const int ready)
3160 {
3161 int a = v->reg.data.id;
3162
3163 if (v->reg.file == FILE_GPR) {
3164 int b = a + v->reg.size / 4;
3165 for (int r = a; r < b; ++r)
3166 score->wr.r[r] = ready;
3167 } else
3168 if (v->reg.file == FILE_PREDICATE) {
3169 score->wr.p[a] = ready;
3170 } else
3171 if (v->reg.file == FILE_FLAGS) {
3172 score->wr.c = ready;
3173 }
3174 }
3175
3176 bool
3177 calculateSchedDataNVC0(const Target *targ, Function *func)
3178 {
3179 SchedDataCalculator sched(targ);
3180 return sched.run(func, true, true);
3181 }
3182
3183 void
3184 CodeEmitterNVC0::prepareEmission(Function *func)
3185 {
3186 CodeEmitter::prepareEmission(func);
3187
3188 if (targ->hasSWSched)
3189 calculateSchedDataNVC0(targ, func);
3190 }
3191
3192 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3193 : CodeEmitter(target),
3194 targNVC0(target),
3195 writeIssueDelays(target->hasSWSched)
3196 {
3197 code = NULL;
3198 codeSize = codeSizeLimit = 0;
3199 relocInfo = NULL;
3200 }
3201
3202 CodeEmitter *
3203 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3204 {
3205 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3206 emit->setProgramType(type);
3207 return emit;
3208 }
3209
3210 CodeEmitter *
3211 TargetNVC0::getCodeEmitter(Program::Type type)
3212 {
3213 if (chipset >= NVISA_GK20A_CHIPSET)
3214 return createCodeEmitterGK110(type);
3215 return createCodeEmitterNVC0(type);
3216 }
3217
3218 } // namespace nv50_ir