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nvc0/ir: actually emit AFETCH on kepler
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61
62 void emitCondCode(CondCode cc, int pos);
63 void emitInterpMode(const Instruction *);
64 void emitLoadStoreType(DataType ty);
65 void emitSUGType(DataType);
66 void emitCachingMode(CacheMode c);
67
68 void emitShortSrc2(const ValueRef&);
69
70 inline uint8_t getSRegEncoding(const ValueRef&);
71
72 void roundMode_A(const Instruction *);
73 void roundMode_C(const Instruction *);
74 void roundMode_CS(const Instruction *);
75
76 void emitNegAbs12(const Instruction *);
77
78 void emitNOP(const Instruction *);
79
80 void emitLOAD(const Instruction *);
81 void emitSTORE(const Instruction *);
82 void emitMOV(const Instruction *);
83 void emitATOM(const Instruction *);
84 void emitMEMBAR(const Instruction *);
85 void emitCCTL(const Instruction *);
86
87 void emitINTERP(const Instruction *);
88 void emitAFETCH(const Instruction *);
89 void emitPFETCH(const Instruction *);
90 void emitVFETCH(const Instruction *);
91 void emitEXPORT(const Instruction *);
92 void emitOUT(const Instruction *);
93
94 void emitUADD(const Instruction *);
95 void emitFADD(const Instruction *);
96 void emitDADD(const Instruction *);
97 void emitUMUL(const Instruction *);
98 void emitFMUL(const Instruction *);
99 void emitDMUL(const Instruction *);
100 void emitIMAD(const Instruction *);
101 void emitISAD(const Instruction *);
102 void emitFMAD(const Instruction *);
103 void emitDMAD(const Instruction *);
104 void emitMADSP(const Instruction *);
105
106 void emitNOT(Instruction *);
107 void emitLogicOp(const Instruction *, uint8_t subOp);
108 void emitPOPC(const Instruction *);
109 void emitINSBF(const Instruction *);
110 void emitEXTBF(const Instruction *);
111 void emitBFIND(const Instruction *);
112 void emitPERMT(const Instruction *);
113 void emitShift(const Instruction *);
114
115 void emitSFnOp(const Instruction *, uint8_t subOp);
116
117 void emitCVT(Instruction *);
118 void emitMINMAX(const Instruction *);
119 void emitPreOp(const Instruction *);
120
121 void emitSET(const CmpInstruction *);
122 void emitSLCT(const CmpInstruction *);
123 void emitSELP(const Instruction *);
124
125 void emitTEXBAR(const Instruction *);
126 void emitTEX(const TexInstruction *);
127 void emitTEXCSAA(const TexInstruction *);
128 void emitTXQ(const TexInstruction *);
129
130 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
131
132 void emitFlow(const Instruction *);
133 void emitBAR(const Instruction *);
134
135 void emitSUCLAMPMode(uint16_t);
136 void emitSUCalc(Instruction *);
137 void emitSULDGB(const TexInstruction *);
138 void emitSUSTGx(const TexInstruction *);
139
140 void emitVSHL(const Instruction *);
141 void emitVectorSubOp(const Instruction *);
142
143 void emitPIXLD(const Instruction *);
144
145 inline void defId(const ValueDef&, const int pos);
146 inline void defId(const Instruction *, int d, const int pos);
147 inline void srcId(const ValueRef&, const int pos);
148 inline void srcId(const ValueRef *, const int pos);
149 inline void srcId(const Instruction *, int s, const int pos);
150 inline void srcAddr32(const ValueRef&, int pos, int shr);
151
152 inline bool isLIMM(const ValueRef&, DataType ty);
153 };
154
155 // for better visibility
156 #define HEX64(h, l) 0x##h##l##ULL
157
158 #define SDATA(a) ((a).rep()->reg.data)
159 #define DDATA(a) ((a).rep()->reg.data)
160
161 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
162 {
163 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
164 }
165
166 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
167 {
168 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
169 }
170
171 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
172 {
173 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
174 code[pos / 32] |= r << (pos % 32);
175 }
176
177 void
178 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
179 {
180 const uint32_t offset = SDATA(src).offset >> shr;
181
182 code[pos / 32] |= offset << (pos % 32);
183 if (pos && (pos < 32))
184 code[1] |= offset >> (32 - pos);
185 }
186
187 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
188 {
189 code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
190 }
191
192 void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
193 {
194 int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
195 code[pos / 32] |= r << (pos % 32);
196 }
197
198 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
199 {
200 const ImmediateValue *imm = ref.get()->asImm();
201
202 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
203 }
204
205 void
206 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
207 {
208 switch (insn->rnd) {
209 case ROUND_M: code[1] |= 1 << 23; break;
210 case ROUND_P: code[1] |= 2 << 23; break;
211 case ROUND_Z: code[1] |= 3 << 23; break;
212 default:
213 assert(insn->rnd == ROUND_N);
214 break;
215 }
216 }
217
218 void
219 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
220 {
221 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
222 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
223 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
224 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
225 }
226
227 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
228 {
229 uint8_t val;
230
231 switch (cc) {
232 case CC_LT: val = 0x1; break;
233 case CC_LTU: val = 0x9; break;
234 case CC_EQ: val = 0x2; break;
235 case CC_EQU: val = 0xa; break;
236 case CC_LE: val = 0x3; break;
237 case CC_LEU: val = 0xb; break;
238 case CC_GT: val = 0x4; break;
239 case CC_GTU: val = 0xc; break;
240 case CC_NE: val = 0x5; break;
241 case CC_NEU: val = 0xd; break;
242 case CC_GE: val = 0x6; break;
243 case CC_GEU: val = 0xe; break;
244 case CC_TR: val = 0xf; break;
245 case CC_FL: val = 0x0; break;
246
247 case CC_A: val = 0x14; break;
248 case CC_NA: val = 0x13; break;
249 case CC_S: val = 0x15; break;
250 case CC_NS: val = 0x12; break;
251 case CC_C: val = 0x16; break;
252 case CC_NC: val = 0x11; break;
253 case CC_O: val = 0x17; break;
254 case CC_NO: val = 0x10; break;
255
256 default:
257 val = 0;
258 assert(!"invalid condition code");
259 break;
260 }
261 code[pos / 32] |= val << (pos % 32);
262 }
263
264 void
265 CodeEmitterNVC0::emitPredicate(const Instruction *i)
266 {
267 if (i->predSrc >= 0) {
268 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
269 srcId(i->src(i->predSrc), 10);
270 if (i->cc == CC_NOT_P)
271 code[0] |= 0x2000; // negate
272 } else {
273 code[0] |= 0x1c00;
274 }
275 }
276
277 void
278 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
279 {
280 switch (src.getFile()) {
281 case FILE_MEMORY_GLOBAL:
282 srcAddr32(src, 26, 0);
283 break;
284 case FILE_MEMORY_LOCAL:
285 case FILE_MEMORY_SHARED:
286 setAddress24(src);
287 break;
288 default:
289 assert(src.getFile() == FILE_MEMORY_CONST);
290 setAddress16(src);
291 break;
292 }
293 }
294
295 void
296 CodeEmitterNVC0::setAddress16(const ValueRef& src)
297 {
298 Symbol *sym = src.get()->asSym();
299
300 assert(sym);
301
302 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
303 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
304 }
305
306 void
307 CodeEmitterNVC0::setAddress24(const ValueRef& src)
308 {
309 Symbol *sym = src.get()->asSym();
310
311 assert(sym);
312
313 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
314 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
315 }
316
317 void
318 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
319 {
320 const ImmediateValue *imm = i->src(s).get()->asImm();
321 uint32_t u32;
322
323 assert(imm);
324 u32 = imm->reg.data.u32;
325
326 if ((code[0] & 0xf) == 0x1) {
327 // double immediate
328 uint64_t u64 = imm->reg.data.u64;
329 assert(!(u64 & 0x00000fffffffffffULL));
330 assert(!(code[1] & 0xc000));
331 code[0] |= ((u64 >> 44) & 0x3f) << 26;
332 code[1] |= 0xc000 | (u64 >> 50);
333 } else
334 if ((code[0] & 0xf) == 0x2) {
335 // LIMM
336 code[0] |= (u32 & 0x3f) << 26;
337 code[1] |= u32 >> 6;
338 } else
339 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
340 // integer immediate
341 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
342 assert(!(code[1] & 0xc000));
343 u32 &= 0xfffff;
344 code[0] |= (u32 & 0x3f) << 26;
345 code[1] |= 0xc000 | (u32 >> 6);
346 } else {
347 // float immediate
348 assert(!(u32 & 0x00000fff));
349 assert(!(code[1] & 0xc000));
350 code[0] |= ((u32 >> 12) & 0x3f) << 26;
351 code[1] |= 0xc000 | (u32 >> 18);
352 }
353 }
354
355 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
356 {
357 const ImmediateValue *imm = ref.get()->asImm();
358
359 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
360
361 assert(s8 == imm->reg.data.s32);
362
363 code[0] |= (s8 & 0x3f) << 26;
364 code[0] |= (s8 >> 6) << 8;
365 }
366
367 void
368 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
369 {
370 code[0] = opc;
371 code[1] = opc >> 32;
372
373 emitPredicate(i);
374
375 defId(i->def(0), 14);
376
377 int s1 = 26;
378 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
379 s1 = 49;
380
381 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
382 switch (i->getSrc(s)->reg.file) {
383 case FILE_MEMORY_CONST:
384 assert(!(code[1] & 0xc000));
385 code[1] |= (s == 2) ? 0x8000 : 0x4000;
386 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
387 setAddress16(i->src(s));
388 break;
389 case FILE_IMMEDIATE:
390 assert(s == 1 ||
391 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
392 assert(!(code[1] & 0xc000));
393 setImmediate(i, s);
394 break;
395 case FILE_GPR:
396 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
397 break;
398 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
399 break;
400 default:
401 // ignore here, can be predicate or flags, but must not be address
402 break;
403 }
404 }
405 }
406
407 void
408 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
409 {
410 code[0] = opc;
411 code[1] = opc >> 32;
412
413 emitPredicate(i);
414
415 defId(i->def(0), 14);
416
417 switch (i->src(0).getFile()) {
418 case FILE_MEMORY_CONST:
419 assert(!(code[1] & 0xc000));
420 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
421 setAddress16(i->src(0));
422 break;
423 case FILE_IMMEDIATE:
424 assert(!(code[1] & 0xc000));
425 setImmediate(i, 0);
426 break;
427 case FILE_GPR:
428 srcId(i->src(0), 26);
429 break;
430 default:
431 // ignore here, can be predicate or flags, but must not be address
432 break;
433 }
434 }
435
436 void
437 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
438 {
439 code[0] = opc;
440
441 int ss2a = 0;
442 if (opc == 0x0d || opc == 0x0e)
443 ss2a = 2;
444
445 defId(i->def(0), 14);
446 srcId(i->src(0), 20);
447
448 assert(pred || (i->predSrc < 0));
449 if (pred)
450 emitPredicate(i);
451
452 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
453 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
454 assert(!(code[0] & (0x300 >> ss2a)));
455 switch (i->src(s).get()->reg.fileIndex) {
456 case 0: code[0] |= 0x100 >> ss2a; break;
457 case 1: code[0] |= 0x200 >> ss2a; break;
458 case 16: code[0] |= 0x300 >> ss2a; break;
459 default:
460 ERROR("invalid c[] space for short form\n");
461 break;
462 }
463 if (s == 1)
464 code[0] |= i->getSrc(s)->reg.data.offset << 24;
465 else
466 code[0] |= i->getSrc(s)->reg.data.offset << 6;
467 } else
468 if (i->src(s).getFile() == FILE_IMMEDIATE) {
469 assert(s == 1);
470 setImmediateS8(i->src(s));
471 } else
472 if (i->src(s).getFile() == FILE_GPR) {
473 srcId(i->src(s), (s == 1) ? 26 : 8);
474 }
475 }
476 }
477
478 void
479 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
480 {
481 if (src.getFile() == FILE_MEMORY_CONST) {
482 switch (src.get()->reg.fileIndex) {
483 case 0: code[0] |= 0x100; break;
484 case 1: code[0] |= 0x200; break;
485 case 16: code[0] |= 0x300; break;
486 default:
487 assert(!"unsupported file index for short op");
488 break;
489 }
490 srcAddr32(src, 20, 2);
491 } else {
492 srcId(src, 20);
493 assert(src.getFile() == FILE_GPR);
494 }
495 }
496
497 void
498 CodeEmitterNVC0::emitNOP(const Instruction *i)
499 {
500 code[0] = 0x000001e4;
501 code[1] = 0x40000000;
502 emitPredicate(i);
503 }
504
505 void
506 CodeEmitterNVC0::emitFMAD(const Instruction *i)
507 {
508 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
509
510 if (i->encSize == 8) {
511 if (isLIMM(i->src(1), TYPE_F32)) {
512 emitForm_A(i, HEX64(20000000, 00000002));
513 } else {
514 emitForm_A(i, HEX64(30000000, 00000000));
515
516 if (i->src(2).mod.neg())
517 code[0] |= 1 << 8;
518 }
519 roundMode_A(i);
520
521 if (neg1)
522 code[0] |= 1 << 9;
523
524 if (i->saturate)
525 code[0] |= 1 << 5;
526 if (i->ftz)
527 code[0] |= 1 << 6;
528 } else {
529 assert(!i->saturate && !i->src(2).mod.neg());
530 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
531 false);
532 if (neg1)
533 code[0] |= 1 << 4;
534 }
535 }
536
537 void
538 CodeEmitterNVC0::emitDMAD(const Instruction *i)
539 {
540 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
541
542 emitForm_A(i, HEX64(20000000, 00000001));
543
544 if (i->src(2).mod.neg())
545 code[0] |= 1 << 8;
546
547 roundMode_A(i);
548
549 if (neg1)
550 code[0] |= 1 << 9;
551
552 assert(!i->saturate);
553 assert(!i->ftz);
554 }
555
556 void
557 CodeEmitterNVC0::emitFMUL(const Instruction *i)
558 {
559 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
560
561 assert(i->postFactor >= -3 && i->postFactor <= 3);
562
563 if (i->encSize == 8) {
564 if (isLIMM(i->src(1), TYPE_F32)) {
565 assert(i->postFactor == 0); // constant folded, hopefully
566 emitForm_A(i, HEX64(30000000, 00000002));
567 } else {
568 emitForm_A(i, HEX64(58000000, 00000000));
569 roundMode_A(i);
570 code[1] |= ((i->postFactor > 0) ?
571 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
572 }
573 if (neg)
574 code[1] ^= 1 << 25; // aliases with LIMM sign bit
575
576 if (i->saturate)
577 code[0] |= 1 << 5;
578
579 if (i->dnz)
580 code[0] |= 1 << 7;
581 else
582 if (i->ftz)
583 code[0] |= 1 << 6;
584 } else {
585 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
586 emitForm_S(i, 0xa8, true);
587 }
588 }
589
590 void
591 CodeEmitterNVC0::emitDMUL(const Instruction *i)
592 {
593 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
594
595 emitForm_A(i, HEX64(50000000, 00000001));
596 roundMode_A(i);
597
598 if (neg)
599 code[0] |= 1 << 9;
600
601 assert(!i->saturate);
602 assert(!i->ftz);
603 assert(!i->dnz);
604 assert(!i->postFactor);
605 }
606
607 void
608 CodeEmitterNVC0::emitUMUL(const Instruction *i)
609 {
610 if (i->encSize == 8) {
611 if (i->src(1).getFile() == FILE_IMMEDIATE) {
612 emitForm_A(i, HEX64(10000000, 00000002));
613 } else {
614 emitForm_A(i, HEX64(50000000, 00000003));
615 }
616 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
617 code[0] |= 1 << 6;
618 if (i->sType == TYPE_S32)
619 code[0] |= 1 << 5;
620 if (i->dType == TYPE_S32)
621 code[0] |= 1 << 7;
622 } else {
623 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
624
625 if (i->sType == TYPE_S32)
626 code[0] |= 1 << 6;
627 }
628 }
629
630 void
631 CodeEmitterNVC0::emitFADD(const Instruction *i)
632 {
633 if (i->encSize == 8) {
634 if (isLIMM(i->src(1), TYPE_F32)) {
635 assert(!i->saturate);
636 emitForm_A(i, HEX64(28000000, 00000002));
637
638 code[0] |= i->src(0).mod.abs() << 7;
639 code[0] |= i->src(0).mod.neg() << 9;
640
641 if (i->src(1).mod.abs())
642 code[1] &= 0xfdffffff;
643 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
644 code[1] ^= 0x02000000;
645 } else {
646 emitForm_A(i, HEX64(50000000, 00000000));
647
648 roundMode_A(i);
649 if (i->saturate)
650 code[1] |= 1 << 17;
651
652 emitNegAbs12(i);
653 if (i->op == OP_SUB) code[0] ^= 1 << 8;
654 }
655 if (i->ftz)
656 code[0] |= 1 << 5;
657 } else {
658 assert(!i->saturate && i->op != OP_SUB &&
659 !i->src(0).mod.abs() &&
660 !i->src(1).mod.neg() && !i->src(1).mod.abs());
661
662 emitForm_S(i, 0x49, true);
663
664 if (i->src(0).mod.neg())
665 code[0] |= 1 << 7;
666 }
667 }
668
669 void
670 CodeEmitterNVC0::emitDADD(const Instruction *i)
671 {
672 assert(i->encSize == 8);
673 emitForm_A(i, HEX64(48000000, 00000001));
674 roundMode_A(i);
675 assert(!i->saturate);
676 assert(!i->ftz);
677 emitNegAbs12(i);
678 if (i->op == OP_SUB)
679 code[0] ^= 1 << 8;
680 }
681
682 void
683 CodeEmitterNVC0::emitUADD(const Instruction *i)
684 {
685 uint32_t addOp = 0;
686
687 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
688 assert(!i->src(0).mod.neg() || !i->src(1).mod.neg());
689
690 if (i->src(0).mod.neg())
691 addOp |= 0x200;
692 if (i->src(1).mod.neg())
693 addOp |= 0x100;
694 if (i->op == OP_SUB) {
695 addOp ^= 0x100;
696 assert(addOp != 0x300); // would be add-plus-one
697 }
698
699 if (i->encSize == 8) {
700 if (isLIMM(i->src(1), TYPE_U32)) {
701 emitForm_A(i, HEX64(08000000, 00000002));
702 if (i->defExists(1))
703 code[1] |= 1 << 26; // write carry
704 } else {
705 emitForm_A(i, HEX64(48000000, 00000003));
706 if (i->defExists(1))
707 code[1] |= 1 << 16; // write carry
708 }
709 code[0] |= addOp;
710
711 if (i->saturate)
712 code[0] |= 1 << 5;
713 if (i->flagsSrc >= 0) // add carry
714 code[0] |= 1 << 6;
715 } else {
716 assert(!(addOp & 0x100));
717 emitForm_S(i, (addOp >> 3) |
718 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
719 }
720 }
721
722 // TODO: shl-add
723 void
724 CodeEmitterNVC0::emitIMAD(const Instruction *i)
725 {
726 assert(i->encSize == 8);
727 emitForm_A(i, HEX64(20000000, 00000003));
728
729 if (isSignedType(i->dType))
730 code[0] |= 1 << 7;
731 if (isSignedType(i->sType))
732 code[0] |= 1 << 5;
733
734 code[1] |= i->saturate << 24;
735
736 if (i->flagsDef >= 0) code[1] |= 1 << 16;
737 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
738
739 if (i->src(2).mod.neg()) code[0] |= 0x10;
740 if (i->src(1).mod.neg() ^
741 i->src(0).mod.neg()) code[0] |= 0x20;
742
743 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
744 code[0] |= 1 << 6;
745 }
746
747 void
748 CodeEmitterNVC0::emitMADSP(const Instruction *i)
749 {
750 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
751
752 emitForm_A(i, HEX64(00000000, 00000003));
753
754 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
755 code[1] |= 0x01800000;
756 } else {
757 code[0] |= (i->subOp & 0x00f) << 7;
758 code[0] |= (i->subOp & 0x0f0) << 1;
759 code[0] |= (i->subOp & 0x100) >> 3;
760 code[0] |= (i->subOp & 0x200) >> 2;
761 code[1] |= (i->subOp & 0xc00) << 13;
762 }
763
764 if (i->flagsDef >= 0)
765 code[1] |= 1 << 16;
766 }
767
768 void
769 CodeEmitterNVC0::emitISAD(const Instruction *i)
770 {
771 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
772 assert(i->encSize == 8);
773
774 emitForm_A(i, HEX64(38000000, 00000003));
775
776 if (i->dType == TYPE_S32)
777 code[0] |= 1 << 5;
778 }
779
780 void
781 CodeEmitterNVC0::emitNOT(Instruction *i)
782 {
783 assert(i->encSize == 8);
784 i->setSrc(1, i->src(0));
785 emitForm_A(i, HEX64(68000000, 000001c3));
786 }
787
788 void
789 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
790 {
791 if (i->def(0).getFile() == FILE_PREDICATE) {
792 code[0] = 0x00000004 | (subOp << 30);
793 code[1] = 0x0c000000;
794
795 emitPredicate(i);
796
797 defId(i->def(0), 17);
798 srcId(i->src(0), 20);
799 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
800 srcId(i->src(1), 26);
801 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
802
803 if (i->defExists(1)) {
804 defId(i->def(1), 14);
805 } else {
806 code[0] |= 7 << 14;
807 }
808 // (a OP b) OP c
809 if (i->predSrc != 2 && i->srcExists(2)) {
810 code[1] |= subOp << 21;
811 srcId(i->src(2), 17);
812 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 20;
813 } else {
814 code[1] |= 0x000e0000;
815 }
816 } else
817 if (i->encSize == 8) {
818 if (isLIMM(i->src(1), TYPE_U32)) {
819 emitForm_A(i, HEX64(38000000, 00000002));
820
821 if (i->flagsDef >= 0)
822 code[1] |= 1 << 26;
823 } else {
824 emitForm_A(i, HEX64(68000000, 00000003));
825
826 if (i->flagsDef >= 0)
827 code[1] |= 1 << 16;
828 }
829 code[0] |= subOp << 6;
830
831 if (i->flagsSrc >= 0) // carry
832 code[0] |= 1 << 5;
833
834 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
835 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
836 } else {
837 emitForm_S(i, (subOp << 5) |
838 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
839 }
840 }
841
842 void
843 CodeEmitterNVC0::emitPOPC(const Instruction *i)
844 {
845 emitForm_A(i, HEX64(54000000, 00000004));
846
847 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
848 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
849 }
850
851 void
852 CodeEmitterNVC0::emitINSBF(const Instruction *i)
853 {
854 emitForm_A(i, HEX64(28000000, 00000003));
855 }
856
857 void
858 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
859 {
860 emitForm_A(i, HEX64(70000000, 00000003));
861
862 if (i->dType == TYPE_S32)
863 code[0] |= 1 << 5;
864 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
865 code[0] |= 1 << 8;
866 }
867
868 void
869 CodeEmitterNVC0::emitBFIND(const Instruction *i)
870 {
871 emitForm_B(i, HEX64(78000000, 00000003));
872
873 if (i->dType == TYPE_S32)
874 code[0] |= 1 << 5;
875 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
876 code[0] |= 1 << 8;
877 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
878 code[0] |= 1 << 6;
879 }
880
881 void
882 CodeEmitterNVC0::emitPERMT(const Instruction *i)
883 {
884 emitForm_A(i, HEX64(24000000, 00000004));
885
886 code[0] |= i->subOp << 5;
887 }
888
889 void
890 CodeEmitterNVC0::emitShift(const Instruction *i)
891 {
892 if (i->op == OP_SHR) {
893 emitForm_A(i, HEX64(58000000, 00000003)
894 | (isSignedType(i->dType) ? 0x20 : 0x00));
895 } else {
896 emitForm_A(i, HEX64(60000000, 00000003));
897 }
898
899 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
900 code[0] |= 1 << 9;
901 }
902
903 void
904 CodeEmitterNVC0::emitPreOp(const Instruction *i)
905 {
906 if (i->encSize == 8) {
907 emitForm_B(i, HEX64(60000000, 00000000));
908
909 if (i->op == OP_PREEX2)
910 code[0] |= 0x20;
911
912 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
913 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
914 } else {
915 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
916 }
917 }
918
919 void
920 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
921 {
922 if (i->encSize == 8) {
923 code[0] = 0x00000000 | (subOp << 26);
924 code[1] = 0xc8000000;
925
926 emitPredicate(i);
927
928 defId(i->def(0), 14);
929 srcId(i->src(0), 20);
930
931 assert(i->src(0).getFile() == FILE_GPR);
932
933 if (i->saturate) code[0] |= 1 << 5;
934
935 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
936 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
937 } else {
938 emitForm_S(i, 0x80000008 | (subOp << 26), true);
939
940 assert(!i->src(0).mod.neg());
941 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
942 }
943 }
944
945 void
946 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
947 {
948 uint64_t op;
949
950 assert(i->encSize == 8);
951
952 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
953
954 if (i->ftz)
955 op |= 1 << 5;
956 else
957 if (!isFloatType(i->dType))
958 op |= isSignedType(i->dType) ? 0x23 : 0x03;
959 if (i->dType == TYPE_F64)
960 op |= 0x01;
961
962 emitForm_A(i, op);
963 emitNegAbs12(i);
964 }
965
966 void
967 CodeEmitterNVC0::roundMode_C(const Instruction *i)
968 {
969 switch (i->rnd) {
970 case ROUND_M: code[1] |= 1 << 17; break;
971 case ROUND_P: code[1] |= 2 << 17; break;
972 case ROUND_Z: code[1] |= 3 << 17; break;
973 case ROUND_NI: code[0] |= 1 << 7; break;
974 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
975 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
976 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
977 case ROUND_N: break;
978 default:
979 assert(!"invalid round mode");
980 break;
981 }
982 }
983
984 void
985 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
986 {
987 switch (i->rnd) {
988 case ROUND_M:
989 case ROUND_MI: code[0] |= 1 << 16; break;
990 case ROUND_P:
991 case ROUND_PI: code[0] |= 2 << 16; break;
992 case ROUND_Z:
993 case ROUND_ZI: code[0] |= 3 << 16; break;
994 default:
995 break;
996 }
997 }
998
999 void
1000 CodeEmitterNVC0::emitCVT(Instruction *i)
1001 {
1002 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1003 DataType dType;
1004
1005 switch (i->op) {
1006 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1007 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1008 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1009 default:
1010 break;
1011 }
1012
1013 const bool sat = (i->op == OP_SAT) || i->saturate;
1014 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1015 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1016
1017 if (i->op == OP_NEG && i->dType == TYPE_U32)
1018 dType = TYPE_S32;
1019 else
1020 dType = i->dType;
1021
1022 if (i->encSize == 8) {
1023 emitForm_B(i, HEX64(10000000, 00000004));
1024
1025 roundMode_C(i);
1026
1027 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1028 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1029 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1030
1031 // for 8/16 source types, the byte/word is in subOp. word 1 is
1032 // represented as 2.
1033 code[1] |= i->subOp << 0x17;
1034
1035 if (sat)
1036 code[0] |= 0x20;
1037 if (abs)
1038 code[0] |= 1 << 6;
1039 if (neg && i->op != OP_ABS)
1040 code[0] |= 1 << 8;
1041
1042 if (i->ftz)
1043 code[1] |= 1 << 23;
1044
1045 if (isSignedIntType(dType))
1046 code[0] |= 0x080;
1047 if (isSignedIntType(i->sType))
1048 code[0] |= 0x200;
1049
1050 if (isFloatType(dType)) {
1051 if (!isFloatType(i->sType))
1052 code[1] |= 0x08000000;
1053 } else {
1054 if (isFloatType(i->sType))
1055 code[1] |= 0x04000000;
1056 else
1057 code[1] |= 0x0c000000;
1058 }
1059 } else {
1060 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1061 code[0] = 0x298;
1062 } else
1063 if (isFloatType(dType)) {
1064 if (isFloatType(i->sType))
1065 code[0] = 0x098;
1066 else
1067 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1068 } else {
1069 assert(isFloatType(i->sType));
1070
1071 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1072 }
1073
1074 if (neg) code[0] |= 1 << 16;
1075 if (sat) code[0] |= 1 << 18;
1076 if (abs) code[0] |= 1 << 19;
1077
1078 roundMode_CS(i);
1079 }
1080 }
1081
1082 void
1083 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1084 {
1085 uint32_t hi;
1086 uint32_t lo = 0;
1087
1088 if (i->sType == TYPE_F64)
1089 lo = 0x1;
1090 else
1091 if (!isFloatType(i->sType))
1092 lo = 0x3;
1093
1094 if (isSignedIntType(i->sType))
1095 lo |= 0x20;
1096 if (isFloatType(i->dType)) {
1097 if (isFloatType(i->sType))
1098 lo |= 0x20;
1099 else
1100 lo |= 0x80;
1101 }
1102
1103 switch (i->op) {
1104 case OP_SET_AND: hi = 0x10000000; break;
1105 case OP_SET_OR: hi = 0x10200000; break;
1106 case OP_SET_XOR: hi = 0x10400000; break;
1107 default:
1108 hi = 0x100e0000;
1109 break;
1110 }
1111 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1112
1113 if (i->op != OP_SET)
1114 srcId(i->src(2), 32 + 17);
1115
1116 if (i->def(0).getFile() == FILE_PREDICATE) {
1117 if (i->sType == TYPE_F32)
1118 code[1] += 0x10000000;
1119 else
1120 code[1] += 0x08000000;
1121
1122 code[0] &= ~0xfc000;
1123 defId(i->def(0), 17);
1124 if (i->defExists(1))
1125 defId(i->def(1), 14);
1126 else
1127 code[0] |= 0x1c000;
1128 }
1129
1130 if (i->ftz)
1131 code[1] |= 1 << 27;
1132
1133 emitCondCode(i->setCond, 32 + 23);
1134 emitNegAbs12(i);
1135 }
1136
1137 void
1138 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1139 {
1140 uint64_t op;
1141
1142 switch (i->dType) {
1143 case TYPE_S32:
1144 op = HEX64(30000000, 00000023);
1145 break;
1146 case TYPE_U32:
1147 op = HEX64(30000000, 00000003);
1148 break;
1149 case TYPE_F32:
1150 op = HEX64(38000000, 00000000);
1151 break;
1152 default:
1153 assert(!"invalid type for SLCT");
1154 op = 0;
1155 break;
1156 }
1157 emitForm_A(i, op);
1158
1159 CondCode cc = i->setCond;
1160
1161 if (i->src(2).mod.neg())
1162 cc = reverseCondCode(cc);
1163
1164 emitCondCode(cc, 32 + 23);
1165
1166 if (i->ftz)
1167 code[0] |= 1 << 5;
1168 }
1169
1170 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1171 {
1172 emitForm_A(i, HEX64(20000000, 00000004));
1173
1174 if (i->cc == CC_NOT_P || i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1175 code[1] |= 1 << 20;
1176 }
1177
1178 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1179 {
1180 code[0] = 0x00000006 | (i->subOp << 26);
1181 code[1] = 0xf0000000;
1182 emitPredicate(i);
1183 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1184 }
1185
1186 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1187 {
1188 code[0] = 0x00000086;
1189 code[1] = 0xd0000000;
1190
1191 code[1] |= i->tex.r;
1192 code[1] |= i->tex.s << 8;
1193
1194 if (i->tex.liveOnly)
1195 code[0] |= 1 << 9;
1196
1197 defId(i->def(0), 14);
1198 srcId(i->src(0), 20);
1199 }
1200
1201 static inline bool
1202 isNextIndependentTex(const TexInstruction *i)
1203 {
1204 if (!i->next || !isTextureOp(i->next->op))
1205 return false;
1206 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1207 return false;
1208 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1209 }
1210
1211 void
1212 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1213 {
1214 code[0] = 0x00000006;
1215
1216 if (isNextIndependentTex(i))
1217 code[0] |= 0x080; // t mode
1218 else
1219 code[0] |= 0x100; // p mode
1220
1221 if (i->tex.liveOnly)
1222 code[0] |= 1 << 9;
1223
1224 switch (i->op) {
1225 case OP_TEX: code[1] = 0x80000000; break;
1226 case OP_TXB: code[1] = 0x84000000; break;
1227 case OP_TXL: code[1] = 0x86000000; break;
1228 case OP_TXF: code[1] = 0x90000000; break;
1229 case OP_TXG: code[1] = 0xa0000000; break;
1230 case OP_TXLQ: code[1] = 0xb0000000; break;
1231 case OP_TXD: code[1] = 0xe0000000; break;
1232 default:
1233 assert(!"invalid texture op");
1234 break;
1235 }
1236 if (i->op == OP_TXF) {
1237 if (!i->tex.levelZero)
1238 code[1] |= 0x02000000;
1239 } else
1240 if (i->tex.levelZero) {
1241 code[1] |= 0x02000000;
1242 }
1243
1244 if (i->op != OP_TXD && i->tex.derivAll)
1245 code[1] |= 1 << 13;
1246
1247 defId(i->def(0), 14);
1248 srcId(i->src(0), 20);
1249
1250 emitPredicate(i);
1251
1252 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1253
1254 code[1] |= i->tex.mask << 14;
1255
1256 code[1] |= i->tex.r;
1257 code[1] |= i->tex.s << 8;
1258 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1259 code[1] |= 1 << 18; // in 1st source (with array index)
1260
1261 // texture target:
1262 code[1] |= (i->tex.target.getDim() - 1) << 20;
1263 if (i->tex.target.isCube())
1264 code[1] += 2 << 20;
1265 if (i->tex.target.isArray())
1266 code[1] |= 1 << 19;
1267 if (i->tex.target.isShadow())
1268 code[1] |= 1 << 24;
1269
1270 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1271
1272 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1273 // lzero
1274 if (i->op == OP_TXL)
1275 code[1] &= ~(1 << 26);
1276 else
1277 if (i->op == OP_TXF)
1278 code[1] &= ~(1 << 25);
1279 }
1280 if (i->tex.target == TEX_TARGET_2D_MS ||
1281 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1282 code[1] |= 1 << 23;
1283
1284 if (i->tex.useOffsets == 1)
1285 code[1] |= 1 << 22;
1286 if (i->tex.useOffsets == 4)
1287 code[1] |= 1 << 23;
1288
1289 srcId(i, src1, 26);
1290 }
1291
1292 void
1293 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1294 {
1295 code[0] = 0x00000086;
1296 code[1] = 0xc0000000;
1297
1298 switch (i->tex.query) {
1299 case TXQ_DIMS: code[1] |= 0 << 22; break;
1300 case TXQ_TYPE: code[1] |= 1 << 22; break;
1301 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1302 case TXQ_FILTER: code[1] |= 3 << 22; break;
1303 case TXQ_LOD: code[1] |= 4 << 22; break;
1304 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1305 default:
1306 assert(!"invalid texture query");
1307 break;
1308 }
1309
1310 code[1] |= i->tex.mask << 14;
1311
1312 code[1] |= i->tex.r;
1313 code[1] |= i->tex.s << 8;
1314 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1315 code[1] |= 1 << 18;
1316
1317 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1318
1319 defId(i->def(0), 14);
1320 srcId(i->src(0), 20);
1321 srcId(i, src1, 26);
1322
1323 emitPredicate(i);
1324 }
1325
1326 void
1327 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1328 {
1329 code[0] = 0x00000000 | (laneMask << 6);
1330 code[1] = 0x48000000 | qOp;
1331
1332 defId(i->def(0), 14);
1333 srcId(i->src(0), 20);
1334 srcId(i->srcExists(1) ? i->src(1) : i->src(0), 26);
1335
1336 if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
1337 code[0] |= 1 << 9; // dall
1338
1339 emitPredicate(i);
1340 }
1341
1342 void
1343 CodeEmitterNVC0::emitFlow(const Instruction *i)
1344 {
1345 const FlowInstruction *f = i->asFlow();
1346
1347 unsigned mask; // bit 0: predicate, bit 1: target
1348
1349 code[0] = 0x00000007;
1350
1351 switch (i->op) {
1352 case OP_BRA:
1353 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1354 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1355 code[0] |= 0x4000;
1356 mask = 3;
1357 break;
1358 case OP_CALL:
1359 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1360 if (f->indirect)
1361 code[0] |= 0x4000; // indirect calls always use c[] source
1362 mask = 2;
1363 break;
1364
1365 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1366 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1367 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1368 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1369 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1370
1371 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1372 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1373 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1374 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1375
1376 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1377 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1378 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1379 default:
1380 assert(!"invalid flow operation");
1381 return;
1382 }
1383
1384 if (mask & 1) {
1385 emitPredicate(i);
1386 if (i->flagsSrc < 0)
1387 code[0] |= 0x1e0;
1388 }
1389
1390 if (!f)
1391 return;
1392
1393 if (f->allWarp)
1394 code[0] |= 1 << 15;
1395 if (f->limit)
1396 code[0] |= 1 << 16;
1397
1398 if (f->indirect) {
1399 if (code[0] & 0x4000) {
1400 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1401 setAddress16(i->src(0));
1402 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1403 if (f->op == OP_BRA)
1404 srcId(f->src(0).getIndirect(0), 20);
1405 } else {
1406 srcId(f, 0, 20);
1407 }
1408 }
1409
1410 if (f->op == OP_CALL) {
1411 if (f->indirect) {
1412 // nothing
1413 } else
1414 if (f->builtin) {
1415 assert(f->absolute);
1416 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1417 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1418 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1419 } else {
1420 assert(!f->absolute);
1421 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1422 code[0] |= (pcRel & 0x3f) << 26;
1423 code[1] |= (pcRel >> 6) & 0x3ffff;
1424 }
1425 } else
1426 if (mask & 2) {
1427 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1428 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1429 pcRel += 8;
1430 // currently we don't want absolute branches
1431 assert(!f->absolute);
1432 code[0] |= (pcRel & 0x3f) << 26;
1433 code[1] |= (pcRel >> 6) & 0x3ffff;
1434 }
1435 }
1436
1437 void
1438 CodeEmitterNVC0::emitBAR(const Instruction *i)
1439 {
1440 Value *rDef = NULL, *pDef = NULL;
1441
1442 switch (i->subOp) {
1443 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1444 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1445 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1446 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1447 default:
1448 code[0] = 0x04;
1449 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1450 break;
1451 }
1452 code[1] = 0x50000000;
1453
1454 code[0] |= 63 << 14;
1455 code[1] |= 7 << 21;
1456
1457 emitPredicate(i);
1458
1459 // barrier id
1460 if (i->src(0).getFile() == FILE_GPR) {
1461 srcId(i->src(0), 20);
1462 } else {
1463 ImmediateValue *imm = i->getSrc(0)->asImm();
1464 assert(imm);
1465 code[0] |= imm->reg.data.u32 << 20;
1466 code[1] |= 0x8000;
1467 }
1468
1469 // thread count
1470 if (i->src(1).getFile() == FILE_GPR) {
1471 srcId(i->src(1), 26);
1472 } else {
1473 ImmediateValue *imm = i->getSrc(1)->asImm();
1474 assert(imm);
1475 code[0] |= imm->reg.data.u32 << 26;
1476 code[1] |= imm->reg.data.u32 >> 6;
1477 code[1] |= 0x4000;
1478 }
1479
1480 if (i->srcExists(2) && (i->predSrc != 2)) {
1481 srcId(i->src(2), 32 + 17);
1482 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1483 code[1] |= 1 << 20;
1484 } else {
1485 code[1] |= 7 << 17;
1486 }
1487
1488 if (i->defExists(0)) {
1489 if (i->def(0).getFile() == FILE_GPR)
1490 rDef = i->getDef(0);
1491 else
1492 pDef = i->getDef(0);
1493
1494 if (i->defExists(1)) {
1495 if (i->def(1).getFile() == FILE_GPR)
1496 rDef = i->getDef(1);
1497 else
1498 pDef = i->getDef(1);
1499 }
1500 }
1501 if (rDef) {
1502 code[0] &= ~(63 << 14);
1503 defId(rDef, 14);
1504 }
1505 if (pDef) {
1506 code[1] &= ~(7 << 21);
1507 defId(pDef, 32 + 21);
1508 }
1509 }
1510
1511 void
1512 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1513 {
1514 code[0] = 0x00000006;
1515 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1516
1517 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1518 code[0] |= 0x200;
1519
1520 emitPredicate(i);
1521
1522 defId(i->def(0), 14);
1523 srcId(i->src(0).getIndirect(0), 20);
1524 }
1525
1526 void
1527 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1528 {
1529 uint32_t prim = i->src(0).get()->reg.data.u32;
1530
1531 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1532 code[1] = 0x00000000 | (prim >> 6);
1533
1534 emitPredicate(i);
1535
1536 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1537
1538 defId(i->def(0), 14);
1539 srcId(i, src1, 20);
1540 }
1541
1542 void
1543 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1544 {
1545 code[0] = 0x00000006;
1546 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1547
1548 if (i->perPatch)
1549 code[0] |= 0x100;
1550 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1551 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1552
1553 emitPredicate(i);
1554
1555 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1556
1557 defId(i->def(0), 14);
1558 srcId(i->src(0).getIndirect(0), 20);
1559 srcId(i->src(0).getIndirect(1), 26); // vertex address
1560 }
1561
1562 void
1563 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1564 {
1565 unsigned int size = typeSizeof(i->dType);
1566
1567 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1568 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1569
1570 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1571
1572 if (i->perPatch)
1573 code[0] |= 0x100;
1574
1575 emitPredicate(i);
1576
1577 assert(i->src(1).getFile() == FILE_GPR);
1578
1579 srcId(i->src(0).getIndirect(0), 20);
1580 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1581 srcId(i->src(1), 26);
1582 }
1583
1584 void
1585 CodeEmitterNVC0::emitOUT(const Instruction *i)
1586 {
1587 code[0] = 0x00000006;
1588 code[1] = 0x1c000000;
1589
1590 emitPredicate(i);
1591
1592 defId(i->def(0), 14); // new secret address
1593 srcId(i->src(0), 20); // old secret address, should be 0 initially
1594
1595 assert(i->src(0).getFile() == FILE_GPR);
1596
1597 if (i->op == OP_EMIT)
1598 code[0] |= 1 << 5;
1599 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1600 code[0] |= 1 << 6;
1601
1602 // vertex stream
1603 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1604 unsigned int stream = SDATA(i->src(1)).u32;
1605 assert(stream < 4);
1606 if (stream) {
1607 code[1] |= 0xc000;
1608 code[0] |= stream << 26;
1609 } else {
1610 srcId(NULL, 26);
1611 }
1612 } else {
1613 srcId(i->src(1), 26);
1614 }
1615 }
1616
1617 void
1618 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1619 {
1620 if (i->encSize == 8) {
1621 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1622 } else {
1623 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1624 code[0] |= 0x80;
1625 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1626 }
1627 }
1628
1629 static void
1630 interpApply(const InterpEntry *entry, uint32_t *code,
1631 bool force_persample_interp, bool flatshade)
1632 {
1633 int ipa = entry->ipa;
1634 int reg = entry->reg;
1635 int loc = entry->loc;
1636
1637 if (flatshade &&
1638 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1639 ipa = NV50_IR_INTERP_FLAT;
1640 reg = 0x3f;
1641 } else if (force_persample_interp &&
1642 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1643 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1644 ipa |= NV50_IR_INTERP_CENTROID;
1645 }
1646 code[loc + 0] &= ~(0xf << 6);
1647 code[loc + 0] |= ipa << 6;
1648 code[loc + 0] &= ~(0x3f << 26);
1649 code[loc + 0] |= reg << 26;
1650 }
1651
1652 void
1653 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1654 {
1655 const uint32_t base = i->getSrc(0)->reg.data.offset;
1656
1657 if (i->encSize == 8) {
1658 code[0] = 0x00000000;
1659 code[1] = 0xc0000000 | (base & 0xffff);
1660
1661 if (i->saturate)
1662 code[0] |= 1 << 5;
1663
1664 if (i->op == OP_PINTERP) {
1665 srcId(i->src(1), 26);
1666 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1667 } else {
1668 code[0] |= 0x3f << 26;
1669 addInterp(i->ipa, 0x3f, interpApply);
1670 }
1671
1672 srcId(i->src(0).getIndirect(0), 20);
1673 } else {
1674 assert(i->op == OP_PINTERP);
1675 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1676 srcId(i->src(1), 20);
1677 }
1678 emitInterpMode(i);
1679
1680 emitPredicate(i);
1681 defId(i->def(0), 14);
1682
1683 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1684 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1685 else
1686 code[1] |= 0x3f << 17;
1687 }
1688
1689 void
1690 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1691 {
1692 uint8_t val;
1693
1694 switch (ty) {
1695 case TYPE_U8:
1696 val = 0x00;
1697 break;
1698 case TYPE_S8:
1699 val = 0x20;
1700 break;
1701 case TYPE_F16:
1702 case TYPE_U16:
1703 val = 0x40;
1704 break;
1705 case TYPE_S16:
1706 val = 0x60;
1707 break;
1708 case TYPE_F32:
1709 case TYPE_U32:
1710 case TYPE_S32:
1711 val = 0x80;
1712 break;
1713 case TYPE_F64:
1714 case TYPE_U64:
1715 case TYPE_S64:
1716 val = 0xa0;
1717 break;
1718 case TYPE_B128:
1719 val = 0xc0;
1720 break;
1721 default:
1722 val = 0x80;
1723 assert(!"invalid type");
1724 break;
1725 }
1726 code[0] |= val;
1727 }
1728
1729 void
1730 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1731 {
1732 uint32_t val;
1733
1734 switch (c) {
1735 case CACHE_CA:
1736 // case CACHE_WB:
1737 val = 0x000;
1738 break;
1739 case CACHE_CG:
1740 val = 0x100;
1741 break;
1742 case CACHE_CS:
1743 val = 0x200;
1744 break;
1745 case CACHE_CV:
1746 // case CACHE_WT:
1747 val = 0x300;
1748 break;
1749 default:
1750 val = 0;
1751 assert(!"invalid caching mode");
1752 break;
1753 }
1754 code[0] |= val;
1755 }
1756
1757 static inline bool
1758 uses64bitAddress(const Instruction *ldst)
1759 {
1760 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1761 ldst->src(0).isIndirect(0) &&
1762 ldst->getIndirect(0, 0)->reg.size == 8;
1763 }
1764
1765 void
1766 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1767 {
1768 uint32_t opc;
1769
1770 switch (i->src(0).getFile()) {
1771 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1772 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1773 case FILE_MEMORY_SHARED: opc = 0xc9000000; break;
1774 default:
1775 assert(!"invalid memory file");
1776 opc = 0;
1777 break;
1778 }
1779 code[0] = 0x00000005;
1780 code[1] = opc;
1781
1782 setAddressByFile(i->src(0));
1783 srcId(i->src(1), 14);
1784 srcId(i->src(0).getIndirect(0), 20);
1785 if (uses64bitAddress(i))
1786 code[1] |= 1 << 26;
1787
1788 emitPredicate(i);
1789
1790 emitLoadStoreType(i->dType);
1791 emitCachingMode(i->cache);
1792 }
1793
1794 void
1795 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1796 {
1797 uint32_t opc;
1798
1799 code[0] = 0x00000005;
1800
1801 switch (i->src(0).getFile()) {
1802 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1803 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1804 case FILE_MEMORY_SHARED: opc = 0xc1000000; break;
1805 case FILE_MEMORY_CONST:
1806 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1807 emitMOV(i); // not sure if this is any better
1808 return;
1809 }
1810 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1811 code[0] = 0x00000006 | (i->subOp << 8);
1812 break;
1813 default:
1814 assert(!"invalid memory file");
1815 opc = 0;
1816 break;
1817 }
1818 code[1] = opc;
1819
1820 defId(i->def(0), 14);
1821
1822 setAddressByFile(i->src(0));
1823 srcId(i->src(0).getIndirect(0), 20);
1824 if (uses64bitAddress(i))
1825 code[1] |= 1 << 26;
1826
1827 emitPredicate(i);
1828
1829 emitLoadStoreType(i->dType);
1830 emitCachingMode(i->cache);
1831 }
1832
1833 uint8_t
1834 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1835 {
1836 switch (SDATA(ref).sv.sv) {
1837 case SV_LANEID: return 0x00;
1838 case SV_PHYSID: return 0x03;
1839 case SV_VERTEX_COUNT: return 0x10;
1840 case SV_INVOCATION_ID: return 0x11;
1841 case SV_YDIR: return 0x12;
1842 case SV_THREAD_KILL: return 0x13;
1843 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1844 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1845 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1846 case SV_GRIDID: return 0x2c;
1847 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1848 case SV_LBASE: return 0x34;
1849 case SV_SBASE: return 0x30;
1850 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1851 default:
1852 assert(!"no sreg for system value");
1853 return 0;
1854 }
1855 }
1856
1857 void
1858 CodeEmitterNVC0::emitMOV(const Instruction *i)
1859 {
1860 if (i->def(0).getFile() == FILE_PREDICATE) {
1861 if (i->src(0).getFile() == FILE_GPR) {
1862 code[0] = 0xfc01c003;
1863 code[1] = 0x1a8e0000;
1864 srcId(i->src(0), 20);
1865 } else {
1866 code[0] = 0x0001c004;
1867 code[1] = 0x0c0e0000;
1868 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1869 code[0] |= 7 << 20;
1870 if (!i->getSrc(0)->reg.data.u32)
1871 code[0] |= 1 << 23;
1872 } else {
1873 srcId(i->src(0), 20);
1874 }
1875 }
1876 defId(i->def(0), 17);
1877 emitPredicate(i);
1878 } else
1879 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
1880 uint8_t sr = getSRegEncoding(i->src(0));
1881
1882 if (i->encSize == 8) {
1883 code[0] = 0x00000004 | (sr << 26);
1884 code[1] = 0x2c000000;
1885 } else {
1886 code[0] = 0x40000008 | (sr << 20);
1887 }
1888 defId(i->def(0), 14);
1889
1890 emitPredicate(i);
1891 } else
1892 if (i->encSize == 8) {
1893 uint64_t opc;
1894
1895 if (i->src(0).getFile() == FILE_IMMEDIATE)
1896 opc = HEX64(18000000, 000001e2);
1897 else
1898 if (i->src(0).getFile() == FILE_PREDICATE)
1899 opc = HEX64(080e0000, 1c000004);
1900 else
1901 opc = HEX64(28000000, 00000004);
1902
1903 opc |= i->lanes << 5;
1904
1905 emitForm_B(i, opc);
1906 } else {
1907 uint32_t imm;
1908
1909 if (i->src(0).getFile() == FILE_IMMEDIATE) {
1910 imm = SDATA(i->src(0)).u32;
1911 if (imm & 0xfff00000) {
1912 assert(!(imm & 0x000fffff));
1913 code[0] = 0x00000318 | imm;
1914 } else {
1915 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
1916 code[0] = 0x00000118 | (imm << 20);
1917 }
1918 } else {
1919 code[0] = 0x0028;
1920 emitShortSrc2(i->src(0));
1921 }
1922 defId(i->def(0), 14);
1923
1924 emitPredicate(i);
1925 }
1926 }
1927
1928 void
1929 CodeEmitterNVC0::emitATOM(const Instruction *i)
1930 {
1931 const bool hasDst = i->defExists(0);
1932 const bool casOrExch =
1933 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
1934 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
1935
1936 if (i->dType == TYPE_U64) {
1937 switch (i->subOp) {
1938 case NV50_IR_SUBOP_ATOM_ADD:
1939 code[0] = 0x205;
1940 if (hasDst)
1941 code[1] = 0x507e0000;
1942 else
1943 code[1] = 0x10000000;
1944 break;
1945 case NV50_IR_SUBOP_ATOM_EXCH:
1946 code[0] = 0x305;
1947 code[1] = 0x507e0000;
1948 break;
1949 case NV50_IR_SUBOP_ATOM_CAS:
1950 code[0] = 0x325;
1951 code[1] = 0x50000000;
1952 break;
1953 default:
1954 assert(!"invalid u64 red op");
1955 break;
1956 }
1957 } else
1958 if (i->dType == TYPE_U32) {
1959 switch (i->subOp) {
1960 case NV50_IR_SUBOP_ATOM_EXCH:
1961 code[0] = 0x105;
1962 code[1] = 0x507e0000;
1963 break;
1964 case NV50_IR_SUBOP_ATOM_CAS:
1965 code[0] = 0x125;
1966 code[1] = 0x50000000;
1967 break;
1968 default:
1969 code[0] = 0x5 | (i->subOp << 5);
1970 if (hasDst)
1971 code[1] = 0x507e0000;
1972 else
1973 code[1] = 0x10000000;
1974 break;
1975 }
1976 } else
1977 if (i->dType == TYPE_S32) {
1978 assert(i->subOp <= 2);
1979 code[0] = 0x205 | (i->subOp << 5);
1980 if (hasDst)
1981 code[1] = 0x587e0000;
1982 else
1983 code[1] = 0x18000000;
1984 } else
1985 if (i->dType == TYPE_F32) {
1986 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
1987 code[0] = 0x205;
1988 if (hasDst)
1989 code[1] = 0x687e0000;
1990 else
1991 code[1] = 0x28000000;
1992 }
1993
1994 emitPredicate(i);
1995
1996 srcId(i->src(1), 14);
1997
1998 if (hasDst)
1999 defId(i->def(0), 32 + 11);
2000 else
2001 if (casOrExch)
2002 code[1] |= 63 << 11;
2003
2004 if (hasDst || casOrExch) {
2005 const int32_t offset = SDATA(i->src(0)).offset;
2006 assert(offset < 0x80000 && offset >= -0x80000);
2007 code[0] |= offset << 26;
2008 code[1] |= (offset & 0x1ffc0) >> 6;
2009 code[1] |= (offset & 0xe0000) << 6;
2010 } else {
2011 srcAddr32(i->src(0), 26, 0);
2012 }
2013 if (i->getIndirect(0, 0)) {
2014 srcId(i->getIndirect(0, 0), 20);
2015 if (i->getIndirect(0, 0)->reg.size == 8)
2016 code[1] |= 1 << 26;
2017 } else {
2018 code[0] |= 63 << 20;
2019 }
2020
2021 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS)
2022 srcId(i->src(2), 32 + 17);
2023 }
2024
2025 void
2026 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2027 {
2028 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2029 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2030 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2031 default:
2032 code[0] = 0x45;
2033 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2034 break;
2035 }
2036 code[1] = 0xe0000000;
2037
2038 emitPredicate(i);
2039 }
2040
2041 void
2042 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2043 {
2044 code[0] = 0x00000005 | (i->subOp << 5);
2045
2046 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2047 code[1] = 0x98000000;
2048 srcAddr32(i->src(0), 28, 2);
2049 } else {
2050 code[1] = 0xd0000000;
2051 setAddress24(i->src(0));
2052 }
2053 if (uses64bitAddress(i))
2054 code[1] |= 1 << 26;
2055 srcId(i->src(0).getIndirect(0), 20);
2056
2057 emitPredicate(i);
2058
2059 defId(i, 0, 14);
2060 }
2061
2062 void
2063 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2064 {
2065 uint8_t m;
2066 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2067 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2068 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2069 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2070 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2071 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2072 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2073 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2074 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2075 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2076 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2077 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2078 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2079 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2080 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2081 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2082 default:
2083 return;
2084 }
2085 code[0] |= m << 5;
2086 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2087 code[1] |= 1 << 16;
2088 }
2089
2090 void
2091 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2092 {
2093 ImmediateValue *imm = NULL;
2094 uint64_t opc;
2095
2096 if (i->srcExists(2)) {
2097 imm = i->getSrc(2)->asImm();
2098 if (imm)
2099 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2100 }
2101
2102 switch (i->op) {
2103 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2104 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2105 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2106 default:
2107 assert(0);
2108 return;
2109 }
2110 emitForm_A(i, opc);
2111
2112 if (i->op == OP_SUCLAMP) {
2113 if (i->dType == TYPE_S32)
2114 code[0] |= 1 << 9;
2115 emitSUCLAMPMode(i->subOp);
2116 }
2117
2118 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2119 code[1] |= 1 << 16;
2120
2121 if (i->op != OP_SUEAU) {
2122 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2123 code[0] |= 63 << 14;
2124 code[1] |= i->getDef(0)->reg.data.id << 23;
2125 } else
2126 if (i->defExists(1)) { // r, p
2127 assert(i->def(1).getFile() == FILE_PREDICATE);
2128 code[1] |= i->getDef(1)->reg.data.id << 23;
2129 } else { // r, #
2130 code[1] |= 7 << 23;
2131 }
2132 }
2133 if (imm) {
2134 assert(i->op == OP_SUCLAMP);
2135 i->setSrc(2, imm);
2136 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2137 }
2138 }
2139
2140 void
2141 CodeEmitterNVC0::emitSUGType(DataType ty)
2142 {
2143 switch (ty) {
2144 case TYPE_S32: code[1] |= 1 << 13; break;
2145 case TYPE_U8: code[1] |= 2 << 13; break;
2146 case TYPE_S8: code[1] |= 3 << 13; break;
2147 default:
2148 assert(ty == TYPE_U32);
2149 break;
2150 }
2151 }
2152
2153 void
2154 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2155 {
2156 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2157
2158 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2159 assert(offset == (offset & 0xfffc));
2160
2161 code[1] |= 1 << 21;
2162 code[0] |= offset << 24;
2163 code[1] |= offset >> 8;
2164 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2165 }
2166
2167 void
2168 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2169 {
2170 if (!i->srcExists(s) || (i->predSrc == s)) {
2171 code[1] |= 0x7 << 17;
2172 } else {
2173 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2174 code[1] |= 1 << 20;
2175 srcId(i->src(s), 32 + 17);
2176 }
2177 }
2178
2179 void
2180 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2181 {
2182 code[0] = 0x5;
2183 code[1] = 0xd4000000 | (i->subOp << 15);
2184
2185 emitLoadStoreType(i->dType);
2186 emitSUGType(i->sType);
2187 emitCachingMode(i->cache);
2188
2189 emitPredicate(i);
2190 defId(i->def(0), 14); // destination
2191 srcId(i->src(0), 20); // address
2192 // format
2193 if (i->src(1).getFile() == FILE_GPR)
2194 srcId(i->src(1), 26);
2195 else
2196 setSUConst16(i, 1);
2197 setSUPred(i, 2);
2198 }
2199
2200 void
2201 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2202 {
2203 code[0] = 0x5;
2204 code[1] = 0xdc000000 | (i->subOp << 15);
2205
2206 if (i->op == OP_SUSTP)
2207 code[1] |= i->tex.mask << 22;
2208 else
2209 emitLoadStoreType(i->dType);
2210 emitSUGType(i->sType);
2211 emitCachingMode(i->cache);
2212
2213 emitPredicate(i);
2214 srcId(i->src(0), 20); // address
2215 // format
2216 if (i->src(1).getFile() == FILE_GPR)
2217 srcId(i->src(1), 26);
2218 else
2219 setSUConst16(i, 1);
2220 srcId(i->src(3), 14); // values
2221 setSUPred(i, 2);
2222 }
2223
2224 void
2225 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2226 {
2227 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2228 case 0:
2229 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2230 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2231 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2232 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2233 break;
2234 case 1:
2235 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2236 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2237 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2238 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2239 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2240 code[1] |= (i->mask & 0x3) << 2;
2241 break;
2242 case 2:
2243 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2244 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2245 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2246 code[1] |= (i->mask & 0x3) << 2;
2247 code[1] |= (i->mask & 0xc) << 21;
2248 break;
2249 default:
2250 assert(0);
2251 break;
2252 }
2253 }
2254
2255 void
2256 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2257 {
2258 uint64_t opc = 0x4;
2259
2260 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2261 case 0: opc |= 0xe8ULL << 56; break;
2262 case 1: opc |= 0xb4ULL << 56; break;
2263 case 2: opc |= 0x94ULL << 56; break;
2264 default:
2265 assert(0);
2266 break;
2267 }
2268 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2269 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2270 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2271 } else {
2272 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2273 if (isSignedType(i->sType)) opc |= 1 << 6;
2274 }
2275 emitForm_A(i, opc);
2276 emitVectorSubOp(i);
2277
2278 if (i->saturate)
2279 code[0] |= 1 << 9;
2280 if (i->flagsDef >= 0)
2281 code[1] |= 1 << 16;
2282 }
2283
2284 void
2285 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2286 {
2287 assert(i->encSize == 8);
2288 emitForm_A(i, HEX64(10000000, 00000006));
2289 code[0] |= i->subOp << 5;
2290 code[1] |= 0x00e00000;
2291 }
2292
2293 bool
2294 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2295 {
2296 unsigned int size = insn->encSize;
2297
2298 if (writeIssueDelays && !(codeSize & 0x3f))
2299 size += 8;
2300
2301 if (!insn->encSize) {
2302 ERROR("skipping unencodable instruction: "); insn->print();
2303 return false;
2304 } else
2305 if (codeSize + size > codeSizeLimit) {
2306 ERROR("code emitter output buffer too small\n");
2307 return false;
2308 }
2309
2310 if (writeIssueDelays) {
2311 if (!(codeSize & 0x3f)) {
2312 code[0] = 0x00000007; // cf issue delay "instruction"
2313 code[1] = 0x20000000;
2314 code += 2;
2315 codeSize += 8;
2316 }
2317 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2318 uint32_t *data = code - (id * 2 + 2);
2319 if (id <= 2) {
2320 data[0] |= insn->sched << (id * 8 + 4);
2321 } else
2322 if (id == 3) {
2323 data[0] |= insn->sched << 28;
2324 data[1] |= insn->sched >> 4;
2325 } else {
2326 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2327 }
2328 }
2329
2330 // assert that instructions with multiple defs don't corrupt registers
2331 for (int d = 0; insn->defExists(d); ++d)
2332 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2333
2334 switch (insn->op) {
2335 case OP_MOV:
2336 case OP_RDSV:
2337 emitMOV(insn);
2338 break;
2339 case OP_NOP:
2340 break;
2341 case OP_LOAD:
2342 emitLOAD(insn);
2343 break;
2344 case OP_STORE:
2345 emitSTORE(insn);
2346 break;
2347 case OP_LINTERP:
2348 case OP_PINTERP:
2349 emitINTERP(insn);
2350 break;
2351 case OP_VFETCH:
2352 emitVFETCH(insn);
2353 break;
2354 case OP_EXPORT:
2355 emitEXPORT(insn);
2356 break;
2357 case OP_PFETCH:
2358 emitPFETCH(insn);
2359 break;
2360 case OP_AFETCH:
2361 emitAFETCH(insn);
2362 break;
2363 case OP_EMIT:
2364 case OP_RESTART:
2365 emitOUT(insn);
2366 break;
2367 case OP_ADD:
2368 case OP_SUB:
2369 if (insn->dType == TYPE_F64)
2370 emitDADD(insn);
2371 else if (isFloatType(insn->dType))
2372 emitFADD(insn);
2373 else
2374 emitUADD(insn);
2375 break;
2376 case OP_MUL:
2377 if (insn->dType == TYPE_F64)
2378 emitDMUL(insn);
2379 else if (isFloatType(insn->dType))
2380 emitFMUL(insn);
2381 else
2382 emitUMUL(insn);
2383 break;
2384 case OP_MAD:
2385 case OP_FMA:
2386 if (insn->dType == TYPE_F64)
2387 emitDMAD(insn);
2388 else if (isFloatType(insn->dType))
2389 emitFMAD(insn);
2390 else
2391 emitIMAD(insn);
2392 break;
2393 case OP_SAD:
2394 emitISAD(insn);
2395 break;
2396 case OP_NOT:
2397 emitNOT(insn);
2398 break;
2399 case OP_AND:
2400 emitLogicOp(insn, 0);
2401 break;
2402 case OP_OR:
2403 emitLogicOp(insn, 1);
2404 break;
2405 case OP_XOR:
2406 emitLogicOp(insn, 2);
2407 break;
2408 case OP_SHL:
2409 case OP_SHR:
2410 emitShift(insn);
2411 break;
2412 case OP_SET:
2413 case OP_SET_AND:
2414 case OP_SET_OR:
2415 case OP_SET_XOR:
2416 emitSET(insn->asCmp());
2417 break;
2418 case OP_SELP:
2419 emitSELP(insn);
2420 break;
2421 case OP_SLCT:
2422 emitSLCT(insn->asCmp());
2423 break;
2424 case OP_MIN:
2425 case OP_MAX:
2426 emitMINMAX(insn);
2427 break;
2428 case OP_ABS:
2429 case OP_NEG:
2430 case OP_CEIL:
2431 case OP_FLOOR:
2432 case OP_TRUNC:
2433 case OP_CVT:
2434 case OP_SAT:
2435 emitCVT(insn);
2436 break;
2437 case OP_RSQ:
2438 emitSFnOp(insn, 5 + 2 * insn->subOp);
2439 break;
2440 case OP_RCP:
2441 emitSFnOp(insn, 4 + 2 * insn->subOp);
2442 break;
2443 case OP_LG2:
2444 emitSFnOp(insn, 3);
2445 break;
2446 case OP_EX2:
2447 emitSFnOp(insn, 2);
2448 break;
2449 case OP_SIN:
2450 emitSFnOp(insn, 1);
2451 break;
2452 case OP_COS:
2453 emitSFnOp(insn, 0);
2454 break;
2455 case OP_PRESIN:
2456 case OP_PREEX2:
2457 emitPreOp(insn);
2458 break;
2459 case OP_TEX:
2460 case OP_TXB:
2461 case OP_TXL:
2462 case OP_TXD:
2463 case OP_TXF:
2464 case OP_TXG:
2465 case OP_TXLQ:
2466 emitTEX(insn->asTex());
2467 break;
2468 case OP_TXQ:
2469 emitTXQ(insn->asTex());
2470 break;
2471 case OP_TEXBAR:
2472 emitTEXBAR(insn);
2473 break;
2474 case OP_SUBFM:
2475 case OP_SUCLAMP:
2476 case OP_SUEAU:
2477 emitSUCalc(insn);
2478 break;
2479 case OP_MADSP:
2480 emitMADSP(insn);
2481 break;
2482 case OP_SULDB:
2483 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2484 emitSULDGB(insn->asTex());
2485 else
2486 ERROR("SULDB not yet supported on < nve4\n");
2487 break;
2488 case OP_SUSTB:
2489 case OP_SUSTP:
2490 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2491 emitSUSTGx(insn->asTex());
2492 else
2493 ERROR("SUSTx not yet supported on < nve4\n");
2494 break;
2495 case OP_ATOM:
2496 emitATOM(insn);
2497 break;
2498 case OP_BRA:
2499 case OP_CALL:
2500 case OP_PRERET:
2501 case OP_RET:
2502 case OP_DISCARD:
2503 case OP_EXIT:
2504 case OP_PRECONT:
2505 case OP_CONT:
2506 case OP_PREBREAK:
2507 case OP_BREAK:
2508 case OP_JOINAT:
2509 case OP_BRKPT:
2510 case OP_QUADON:
2511 case OP_QUADPOP:
2512 emitFlow(insn);
2513 break;
2514 case OP_QUADOP:
2515 emitQUADOP(insn, insn->subOp, insn->lanes);
2516 break;
2517 case OP_DFDX:
2518 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2519 break;
2520 case OP_DFDY:
2521 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2522 break;
2523 case OP_POPCNT:
2524 emitPOPC(insn);
2525 break;
2526 case OP_INSBF:
2527 emitINSBF(insn);
2528 break;
2529 case OP_EXTBF:
2530 emitEXTBF(insn);
2531 break;
2532 case OP_BFIND:
2533 emitBFIND(insn);
2534 break;
2535 case OP_PERMT:
2536 emitPERMT(insn);
2537 break;
2538 case OP_JOIN:
2539 emitNOP(insn);
2540 insn->join = 1;
2541 break;
2542 case OP_BAR:
2543 emitBAR(insn);
2544 break;
2545 case OP_MEMBAR:
2546 emitMEMBAR(insn);
2547 break;
2548 case OP_CCTL:
2549 emitCCTL(insn);
2550 break;
2551 case OP_VSHL:
2552 emitVSHL(insn);
2553 break;
2554 case OP_PIXLD:
2555 emitPIXLD(insn);
2556 break;
2557 case OP_PHI:
2558 case OP_UNION:
2559 case OP_CONSTRAINT:
2560 ERROR("operation should have been eliminated");
2561 return false;
2562 case OP_EXP:
2563 case OP_LOG:
2564 case OP_SQRT:
2565 case OP_POW:
2566 ERROR("operation should have been lowered\n");
2567 return false;
2568 default:
2569 ERROR("unknow op\n");
2570 return false;
2571 }
2572
2573 if (insn->join) {
2574 code[0] |= 0x10;
2575 assert(insn->encSize == 8);
2576 }
2577
2578 code += insn->encSize / 4;
2579 codeSize += insn->encSize;
2580 return true;
2581 }
2582
2583 uint32_t
2584 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2585 {
2586 const Target::OpInfo &info = targ->getOpInfo(i);
2587
2588 if (writeIssueDelays || info.minEncSize == 8 || 1)
2589 return 8;
2590
2591 if (i->ftz || i->saturate || i->join)
2592 return 8;
2593 if (i->rnd != ROUND_N)
2594 return 8;
2595 if (i->predSrc >= 0 && i->op == OP_MAD)
2596 return 8;
2597
2598 if (i->op == OP_PINTERP) {
2599 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2600 return 8;
2601 } else
2602 if (i->op == OP_MOV && i->lanes != 0xf) {
2603 return 8;
2604 }
2605
2606 for (int s = 0; i->srcExists(s); ++s) {
2607 if (i->src(s).isIndirect(0))
2608 return 8;
2609
2610 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2611 if (SDATA(i->src(s)).offset >= 0x100)
2612 return 8;
2613 if (i->getSrc(s)->reg.fileIndex > 1 &&
2614 i->getSrc(s)->reg.fileIndex != 16)
2615 return 8;
2616 } else
2617 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2618 if (i->dType == TYPE_F32) {
2619 if (SDATA(i->src(s)).u32 >= 0x100)
2620 return 8;
2621 } else {
2622 if (SDATA(i->src(s)).u32 > 0xff)
2623 return 8;
2624 }
2625 }
2626
2627 if (i->op == OP_CVT)
2628 continue;
2629 if (i->src(s).mod != Modifier(0)) {
2630 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2631 if (i->op != OP_RSQ)
2632 return 8;
2633 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2634 if (i->op != OP_ADD || s != 0)
2635 return 8;
2636 }
2637 }
2638
2639 return 4;
2640 }
2641
2642 // Simplified, erring on safe side.
2643 class SchedDataCalculator : public Pass
2644 {
2645 public:
2646 SchedDataCalculator(const Target *targ) : targ(targ) { }
2647
2648 private:
2649 struct RegScores
2650 {
2651 struct Resource {
2652 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2653 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2654 int tex; // TEX to non-TEX delay 17 (0x11)
2655 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2656 int imul; // integer MUL to MUL delay 3
2657 } res;
2658 struct ScoreData {
2659 int r[256];
2660 int p[8];
2661 int c;
2662 } rd, wr;
2663 int base;
2664 int regs;
2665
2666 void rebase(const int base)
2667 {
2668 const int delta = this->base - base;
2669 if (!delta)
2670 return;
2671 this->base = 0;
2672
2673 for (int i = 0; i < regs; ++i) {
2674 rd.r[i] += delta;
2675 wr.r[i] += delta;
2676 }
2677 for (int i = 0; i < 8; ++i) {
2678 rd.p[i] += delta;
2679 wr.p[i] += delta;
2680 }
2681 rd.c += delta;
2682 wr.c += delta;
2683
2684 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2685 res.ld[f] += delta;
2686 res.st[f] += delta;
2687 }
2688 res.sfu += delta;
2689 res.imul += delta;
2690 res.tex += delta;
2691 }
2692 void wipe(int regs)
2693 {
2694 memset(&rd, 0, sizeof(rd));
2695 memset(&wr, 0, sizeof(wr));
2696 memset(&res, 0, sizeof(res));
2697 this->regs = regs;
2698 }
2699 int getLatest(const ScoreData& d) const
2700 {
2701 int max = 0;
2702 for (int i = 0; i < regs; ++i)
2703 if (d.r[i] > max)
2704 max = d.r[i];
2705 for (int i = 0; i < 8; ++i)
2706 if (d.p[i] > max)
2707 max = d.p[i];
2708 if (d.c > max)
2709 max = d.c;
2710 return max;
2711 }
2712 inline int getLatestRd() const
2713 {
2714 return getLatest(rd);
2715 }
2716 inline int getLatestWr() const
2717 {
2718 return getLatest(wr);
2719 }
2720 inline int getLatest() const
2721 {
2722 const int a = getLatestRd();
2723 const int b = getLatestWr();
2724
2725 int max = MAX2(a, b);
2726 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2727 max = MAX2(res.ld[f], max);
2728 max = MAX2(res.st[f], max);
2729 }
2730 max = MAX2(res.sfu, max);
2731 max = MAX2(res.imul, max);
2732 max = MAX2(res.tex, max);
2733 return max;
2734 }
2735 void setMax(const RegScores *that)
2736 {
2737 for (int i = 0; i < regs; ++i) {
2738 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
2739 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
2740 }
2741 for (int i = 0; i < 8; ++i) {
2742 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
2743 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
2744 }
2745 rd.c = MAX2(rd.c, that->rd.c);
2746 wr.c = MAX2(wr.c, that->wr.c);
2747
2748 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
2749 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
2750 res.st[f] = MAX2(res.st[f], that->res.st[f]);
2751 }
2752 res.sfu = MAX2(res.sfu, that->res.sfu);
2753 res.imul = MAX2(res.imul, that->res.imul);
2754 res.tex = MAX2(res.tex, that->res.tex);
2755 }
2756 void print(int cycle)
2757 {
2758 for (int i = 0; i < regs; ++i) {
2759 if (rd.r[i] > cycle)
2760 INFO("rd $r%i @ %i\n", i, rd.r[i]);
2761 if (wr.r[i] > cycle)
2762 INFO("wr $r%i @ %i\n", i, wr.r[i]);
2763 }
2764 for (int i = 0; i < 8; ++i) {
2765 if (rd.p[i] > cycle)
2766 INFO("rd $p%i @ %i\n", i, rd.p[i]);
2767 if (wr.p[i] > cycle)
2768 INFO("wr $p%i @ %i\n", i, wr.p[i]);
2769 }
2770 if (rd.c > cycle)
2771 INFO("rd $c @ %i\n", rd.c);
2772 if (wr.c > cycle)
2773 INFO("wr $c @ %i\n", wr.c);
2774 if (res.sfu > cycle)
2775 INFO("sfu @ %i\n", res.sfu);
2776 if (res.imul > cycle)
2777 INFO("imul @ %i\n", res.imul);
2778 if (res.tex > cycle)
2779 INFO("tex @ %i\n", res.tex);
2780 }
2781 };
2782
2783 RegScores *score; // for current BB
2784 std::vector<RegScores> scoreBoards;
2785 int prevData;
2786 operation prevOp;
2787
2788 const Target *targ;
2789
2790 bool visit(Function *);
2791 bool visit(BasicBlock *);
2792
2793 void commitInsn(const Instruction *, int cycle);
2794 int calcDelay(const Instruction *, int cycle) const;
2795 void setDelay(Instruction *, int delay, Instruction *next);
2796
2797 void recordRd(const Value *, const int ready);
2798 void recordWr(const Value *, const int ready);
2799 void checkRd(const Value *, int cycle, int& delay) const;
2800 void checkWr(const Value *, int cycle, int& delay) const;
2801
2802 int getCycles(const Instruction *, int origDelay) const;
2803 };
2804
2805 void
2806 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
2807 {
2808 if (insn->op == OP_EXIT || insn->op == OP_RET)
2809 delay = MAX2(delay, 14);
2810
2811 if (insn->op == OP_TEXBAR) {
2812 // TODO: except if results not used before EXIT
2813 insn->sched = 0xc2;
2814 } else
2815 if (insn->op == OP_JOIN || insn->join) {
2816 insn->sched = 0x00;
2817 } else
2818 if (delay >= 0 || prevData == 0x04 ||
2819 !next || !targ->canDualIssue(insn, next)) {
2820 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
2821 if (prevOp == OP_EXPORT)
2822 insn->sched |= 0x40;
2823 else
2824 insn->sched |= 0x20;
2825 } else {
2826 insn->sched = 0x04; // dual-issue
2827 }
2828
2829 if (prevData != 0x04 || prevOp != OP_EXPORT)
2830 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
2831 prevOp = insn->op;
2832
2833 prevData = insn->sched;
2834 }
2835
2836 int
2837 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
2838 {
2839 if (insn->sched & 0x80) {
2840 int c = (insn->sched & 0x0f) * 2 + 1;
2841 if (insn->op == OP_TEXBAR && origDelay > 0)
2842 c += origDelay;
2843 return c;
2844 }
2845 if (insn->sched & 0x60)
2846 return (insn->sched & 0x1f) + 1;
2847 return (insn->sched == 0x04) ? 0 : 32;
2848 }
2849
2850 bool
2851 SchedDataCalculator::visit(Function *func)
2852 {
2853 int regs = targ->getFileSize(FILE_GPR) + 1;
2854 scoreBoards.resize(func->cfg.getSize());
2855 for (size_t i = 0; i < scoreBoards.size(); ++i)
2856 scoreBoards[i].wipe(regs);
2857 return true;
2858 }
2859
2860 bool
2861 SchedDataCalculator::visit(BasicBlock *bb)
2862 {
2863 Instruction *insn;
2864 Instruction *next = NULL;
2865
2866 int cycle = 0;
2867
2868 prevData = 0x00;
2869 prevOp = OP_NOP;
2870 score = &scoreBoards.at(bb->getId());
2871
2872 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
2873 // back branches will wait until all target dependencies are satisfied
2874 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
2875 continue;
2876 BasicBlock *in = BasicBlock::get(ei.getNode());
2877 if (in->getExit()) {
2878 if (prevData != 0x04)
2879 prevData = in->getExit()->sched;
2880 prevOp = in->getExit()->op;
2881 }
2882 score->setMax(&scoreBoards.at(in->getId()));
2883 }
2884 if (bb->cfg.incidentCount() > 1)
2885 prevOp = OP_NOP;
2886
2887 #ifdef NVC0_DEBUG_SCHED_DATA
2888 INFO("=== BB:%i initial scores\n", bb->getId());
2889 score->print(cycle);
2890 #endif
2891
2892 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
2893 next = insn->next;
2894
2895 commitInsn(insn, cycle);
2896 int delay = calcDelay(next, cycle);
2897 setDelay(insn, delay, next);
2898 cycle += getCycles(insn, delay);
2899
2900 #ifdef NVC0_DEBUG_SCHED_DATA
2901 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
2902 insn->print();
2903 next->print();
2904 #endif
2905 }
2906 if (!insn)
2907 return true;
2908 commitInsn(insn, cycle);
2909
2910 int bbDelay = -1;
2911
2912 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
2913 BasicBlock *out = BasicBlock::get(ei.getNode());
2914
2915 if (ei.getType() != Graph::Edge::BACK) {
2916 // only test the first instruction of the outgoing block
2917 next = out->getEntry();
2918 if (next)
2919 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
2920 } else {
2921 // wait until all dependencies are satisfied
2922 const int regsFree = score->getLatest();
2923 next = out->getFirst();
2924 for (int c = cycle; next && c < regsFree; next = next->next) {
2925 bbDelay = MAX2(bbDelay, calcDelay(next, c));
2926 c += getCycles(next, bbDelay);
2927 }
2928 next = NULL;
2929 }
2930 }
2931 if (bb->cfg.outgoingCount() != 1)
2932 next = NULL;
2933 setDelay(insn, bbDelay, next);
2934 cycle += getCycles(insn, bbDelay);
2935
2936 score->rebase(cycle); // common base for initializing out blocks' scores
2937 return true;
2938 }
2939
2940 #define NVE4_MAX_ISSUE_DELAY 0x1f
2941 int
2942 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
2943 {
2944 int delay = 0, ready = cycle;
2945
2946 for (int s = 0; insn->srcExists(s); ++s)
2947 checkRd(insn->getSrc(s), cycle, delay);
2948 // WAR & WAW don't seem to matter
2949 // for (int s = 0; insn->srcExists(s); ++s)
2950 // recordRd(insn->getSrc(s), cycle);
2951
2952 switch (Target::getOpClass(insn->op)) {
2953 case OPCLASS_SFU:
2954 ready = score->res.sfu;
2955 break;
2956 case OPCLASS_ARITH:
2957 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2958 ready = score->res.imul;
2959 break;
2960 case OPCLASS_TEXTURE:
2961 ready = score->res.tex;
2962 break;
2963 case OPCLASS_LOAD:
2964 ready = score->res.ld[insn->src(0).getFile()];
2965 break;
2966 case OPCLASS_STORE:
2967 ready = score->res.st[insn->src(0).getFile()];
2968 break;
2969 default:
2970 break;
2971 }
2972 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
2973 ready = MAX2(ready, score->res.tex);
2974
2975 delay = MAX2(delay, ready - cycle);
2976
2977 // if can issue next cycle, delay is 0, not 1
2978 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
2979 }
2980
2981 void
2982 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
2983 {
2984 const int ready = cycle + targ->getLatency(insn);
2985
2986 for (int d = 0; insn->defExists(d); ++d)
2987 recordWr(insn->getDef(d), ready);
2988 // WAR & WAW don't seem to matter
2989 // for (int s = 0; insn->srcExists(s); ++s)
2990 // recordRd(insn->getSrc(s), cycle);
2991
2992 switch (Target::getOpClass(insn->op)) {
2993 case OPCLASS_SFU:
2994 score->res.sfu = cycle + 4;
2995 break;
2996 case OPCLASS_ARITH:
2997 if (insn->op == OP_MUL && !isFloatType(insn->dType))
2998 score->res.imul = cycle + 4;
2999 break;
3000 case OPCLASS_TEXTURE:
3001 score->res.tex = cycle + 18;
3002 break;
3003 case OPCLASS_LOAD:
3004 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3005 break;
3006 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3007 score->res.st[insn->src(0).getFile()] = ready;
3008 break;
3009 case OPCLASS_STORE:
3010 score->res.st[insn->src(0).getFile()] = cycle + 4;
3011 score->res.ld[insn->src(0).getFile()] = ready;
3012 break;
3013 case OPCLASS_OTHER:
3014 if (insn->op == OP_TEXBAR)
3015 score->res.tex = cycle;
3016 break;
3017 default:
3018 break;
3019 }
3020
3021 #ifdef NVC0_DEBUG_SCHED_DATA
3022 score->print(cycle);
3023 #endif
3024 }
3025
3026 void
3027 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3028 {
3029 int ready = cycle;
3030 int a, b;
3031
3032 switch (v->reg.file) {
3033 case FILE_GPR:
3034 a = v->reg.data.id;
3035 b = a + v->reg.size / 4;
3036 for (int r = a; r < b; ++r)
3037 ready = MAX2(ready, score->rd.r[r]);
3038 break;
3039 case FILE_PREDICATE:
3040 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3041 break;
3042 case FILE_FLAGS:
3043 ready = MAX2(ready, score->rd.c);
3044 break;
3045 case FILE_SHADER_INPUT:
3046 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3047 case FILE_MEMORY_LOCAL:
3048 case FILE_MEMORY_CONST:
3049 case FILE_MEMORY_SHARED:
3050 case FILE_MEMORY_GLOBAL:
3051 case FILE_SYSTEM_VALUE:
3052 // TODO: any restrictions here ?
3053 break;
3054 case FILE_IMMEDIATE:
3055 break;
3056 default:
3057 assert(0);
3058 break;
3059 }
3060 if (cycle < ready)
3061 delay = MAX2(delay, ready - cycle);
3062 }
3063
3064 void
3065 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3066 {
3067 int ready = cycle;
3068 int a, b;
3069
3070 switch (v->reg.file) {
3071 case FILE_GPR:
3072 a = v->reg.data.id;
3073 b = a + v->reg.size / 4;
3074 for (int r = a; r < b; ++r)
3075 ready = MAX2(ready, score->wr.r[r]);
3076 break;
3077 case FILE_PREDICATE:
3078 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3079 break;
3080 default:
3081 assert(v->reg.file == FILE_FLAGS);
3082 ready = MAX2(ready, score->wr.c);
3083 break;
3084 }
3085 if (cycle < ready)
3086 delay = MAX2(delay, ready - cycle);
3087 }
3088
3089 void
3090 SchedDataCalculator::recordWr(const Value *v, const int ready)
3091 {
3092 int a = v->reg.data.id;
3093
3094 if (v->reg.file == FILE_GPR) {
3095 int b = a + v->reg.size / 4;
3096 for (int r = a; r < b; ++r)
3097 score->rd.r[r] = ready;
3098 } else
3099 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3100 if (v->reg.file == FILE_PREDICATE) {
3101 score->rd.p[a] = ready + 4;
3102 } else {
3103 assert(v->reg.file == FILE_FLAGS);
3104 score->rd.c = ready + 4;
3105 }
3106 }
3107
3108 void
3109 SchedDataCalculator::recordRd(const Value *v, const int ready)
3110 {
3111 int a = v->reg.data.id;
3112
3113 if (v->reg.file == FILE_GPR) {
3114 int b = a + v->reg.size / 4;
3115 for (int r = a; r < b; ++r)
3116 score->wr.r[r] = ready;
3117 } else
3118 if (v->reg.file == FILE_PREDICATE) {
3119 score->wr.p[a] = ready;
3120 } else
3121 if (v->reg.file == FILE_FLAGS) {
3122 score->wr.c = ready;
3123 }
3124 }
3125
3126 bool
3127 calculateSchedDataNVC0(const Target *targ, Function *func)
3128 {
3129 SchedDataCalculator sched(targ);
3130 return sched.run(func, true, true);
3131 }
3132
3133 void
3134 CodeEmitterNVC0::prepareEmission(Function *func)
3135 {
3136 CodeEmitter::prepareEmission(func);
3137
3138 if (targ->hasSWSched)
3139 calculateSchedDataNVC0(targ, func);
3140 }
3141
3142 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3143 : CodeEmitter(target),
3144 targNVC0(target),
3145 writeIssueDelays(target->hasSWSched)
3146 {
3147 code = NULL;
3148 codeSize = codeSizeLimit = 0;
3149 relocInfo = NULL;
3150 }
3151
3152 CodeEmitter *
3153 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3154 {
3155 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3156 emit->setProgramType(type);
3157 return emit;
3158 }
3159
3160 CodeEmitter *
3161 TargetNVC0::getCodeEmitter(Program::Type type)
3162 {
3163 if (chipset >= NVISA_GK20A_CHIPSET)
3164 return createCodeEmitterGK110(type);
3165 return createCodeEmitterNVC0(type);
3166 }
3167
3168 } // namespace nv50_ir