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nvc0/ir: Emit OP_SHFL
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_emit_nvc0.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
27 // Argh, all these assertions ...
28
29 class CodeEmitterNVC0 : public CodeEmitter
30 {
31 public:
32 CodeEmitterNVC0(const TargetNVC0 *);
33
34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
36 virtual void prepareEmission(Function *);
37
38 inline void setProgramType(Program::Type pType) { progType = pType; }
39
40 private:
41 const TargetNVC0 *targNVC0;
42
43 Program::Type progType;
44
45 const bool writeIssueDelays;
46
47 private:
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
51
52 void emitPredicate(const Instruction *);
53
54 void setAddress16(const ValueRef&);
55 void setAddress24(const ValueRef&);
56 void setAddressByFile(const ValueRef&);
57 void setImmediate(const Instruction *, const int s); // needs op already set
58 void setImmediateS8(const ValueRef&);
59 void setSUConst16(const Instruction *, const int s);
60 void setSUPred(const Instruction *, const int s);
61 void setPDSTL(const Instruction *, const int d);
62
63 void emitCondCode(CondCode cc, int pos);
64 void emitInterpMode(const Instruction *);
65 void emitLoadStoreType(DataType ty);
66 void emitSUGType(DataType);
67 void emitSUAddr(const TexInstruction *);
68 void emitSUDim(const TexInstruction *);
69 void emitCachingMode(CacheMode c);
70
71 void emitShortSrc2(const ValueRef&);
72
73 inline uint8_t getSRegEncoding(const ValueRef&);
74
75 void roundMode_A(const Instruction *);
76 void roundMode_C(const Instruction *);
77 void roundMode_CS(const Instruction *);
78
79 void emitNegAbs12(const Instruction *);
80
81 void emitNOP(const Instruction *);
82
83 void emitLOAD(const Instruction *);
84 void emitSTORE(const Instruction *);
85 void emitMOV(const Instruction *);
86 void emitATOM(const Instruction *);
87 void emitMEMBAR(const Instruction *);
88 void emitCCTL(const Instruction *);
89
90 void emitINTERP(const Instruction *);
91 void emitAFETCH(const Instruction *);
92 void emitPFETCH(const Instruction *);
93 void emitVFETCH(const Instruction *);
94 void emitEXPORT(const Instruction *);
95 void emitOUT(const Instruction *);
96
97 void emitUADD(const Instruction *);
98 void emitFADD(const Instruction *);
99 void emitDADD(const Instruction *);
100 void emitUMUL(const Instruction *);
101 void emitFMUL(const Instruction *);
102 void emitDMUL(const Instruction *);
103 void emitIMAD(const Instruction *);
104 void emitISAD(const Instruction *);
105 void emitSHLADD(const Instruction *a);
106 void emitFMAD(const Instruction *);
107 void emitDMAD(const Instruction *);
108 void emitMADSP(const Instruction *);
109
110 void emitNOT(Instruction *);
111 void emitLogicOp(const Instruction *, uint8_t subOp);
112 void emitPOPC(const Instruction *);
113 void emitINSBF(const Instruction *);
114 void emitEXTBF(const Instruction *);
115 void emitBFIND(const Instruction *);
116 void emitPERMT(const Instruction *);
117 void emitShift(const Instruction *);
118
119 void emitSFnOp(const Instruction *, uint8_t subOp);
120
121 void emitCVT(Instruction *);
122 void emitMINMAX(const Instruction *);
123 void emitPreOp(const Instruction *);
124
125 void emitSET(const CmpInstruction *);
126 void emitSLCT(const CmpInstruction *);
127 void emitSELP(const Instruction *);
128
129 void emitTEXBAR(const Instruction *);
130 void emitTEX(const TexInstruction *);
131 void emitTEXCSAA(const TexInstruction *);
132 void emitTXQ(const TexInstruction *);
133
134 void emitQUADOP(const Instruction *, uint8_t qOp, uint8_t laneMask);
135
136 void emitFlow(const Instruction *);
137 void emitBAR(const Instruction *);
138
139 void emitSUCLAMPMode(uint16_t);
140 void emitSUCalc(Instruction *);
141 void emitSULDGB(const TexInstruction *);
142 void emitSUSTGx(const TexInstruction *);
143
144 void emitSULDB(const TexInstruction *);
145 void emitSUSTx(const TexInstruction *);
146 void emitSULEA(const TexInstruction *);
147
148 void emitVSHL(const Instruction *);
149 void emitVectorSubOp(const Instruction *);
150
151 void emitPIXLD(const Instruction *);
152
153 void emitSHFL(const Instruction *);
154
155 void emitVOTE(const Instruction *);
156
157 inline void defId(const ValueDef&, const int pos);
158 inline void defId(const Instruction *, int d, const int pos);
159 inline void srcId(const ValueRef&, const int pos);
160 inline void srcId(const ValueRef *, const int pos);
161 inline void srcId(const Instruction *, int s, const int pos);
162 inline void srcAddr32(const ValueRef&, int pos, int shr);
163
164 inline bool isLIMM(const ValueRef&, DataType ty);
165 };
166
167 // for better visibility
168 #define HEX64(h, l) 0x##h##l##ULL
169
170 #define SDATA(a) ((a).rep()->reg.data)
171 #define DDATA(a) ((a).rep()->reg.data)
172
173 void CodeEmitterNVC0::srcId(const ValueRef& src, const int pos)
174 {
175 code[pos / 32] |= (src.get() ? SDATA(src).id : 63) << (pos % 32);
176 }
177
178 void CodeEmitterNVC0::srcId(const ValueRef *src, const int pos)
179 {
180 code[pos / 32] |= (src ? SDATA(*src).id : 63) << (pos % 32);
181 }
182
183 void CodeEmitterNVC0::srcId(const Instruction *insn, int s, int pos)
184 {
185 int r = insn->srcExists(s) ? SDATA(insn->src(s)).id : 63;
186 code[pos / 32] |= r << (pos % 32);
187 }
188
189 void
190 CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
191 {
192 const uint32_t offset = SDATA(src).offset >> shr;
193
194 code[pos / 32] |= offset << (pos % 32);
195 if (pos && (pos < 32))
196 code[1] |= offset >> (32 - pos);
197 }
198
199 void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
200 {
201 code[pos / 32] |= (def.get() && def.getFile() != FILE_FLAGS ? DDATA(def).id : 63) << (pos % 32);
202 }
203
204 void CodeEmitterNVC0::defId(const Instruction *insn, int d, const int pos)
205 {
206 if (insn->defExists(d))
207 defId(insn->def(d), pos);
208 else
209 code[pos / 32] |= 63 << (pos % 32);
210 }
211
212 bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
213 {
214 const ImmediateValue *imm = ref.get()->asImm();
215
216 return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
217 }
218
219 void
220 CodeEmitterNVC0::roundMode_A(const Instruction *insn)
221 {
222 switch (insn->rnd) {
223 case ROUND_M: code[1] |= 1 << 23; break;
224 case ROUND_P: code[1] |= 2 << 23; break;
225 case ROUND_Z: code[1] |= 3 << 23; break;
226 default:
227 assert(insn->rnd == ROUND_N);
228 break;
229 }
230 }
231
232 void
233 CodeEmitterNVC0::emitNegAbs12(const Instruction *i)
234 {
235 if (i->src(1).mod.abs()) code[0] |= 1 << 6;
236 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
237 if (i->src(1).mod.neg()) code[0] |= 1 << 8;
238 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
239 }
240
241 void CodeEmitterNVC0::emitCondCode(CondCode cc, int pos)
242 {
243 uint8_t val;
244
245 switch (cc) {
246 case CC_LT: val = 0x1; break;
247 case CC_LTU: val = 0x9; break;
248 case CC_EQ: val = 0x2; break;
249 case CC_EQU: val = 0xa; break;
250 case CC_LE: val = 0x3; break;
251 case CC_LEU: val = 0xb; break;
252 case CC_GT: val = 0x4; break;
253 case CC_GTU: val = 0xc; break;
254 case CC_NE: val = 0x5; break;
255 case CC_NEU: val = 0xd; break;
256 case CC_GE: val = 0x6; break;
257 case CC_GEU: val = 0xe; break;
258 case CC_TR: val = 0xf; break;
259 case CC_FL: val = 0x0; break;
260
261 case CC_A: val = 0x14; break;
262 case CC_NA: val = 0x13; break;
263 case CC_S: val = 0x15; break;
264 case CC_NS: val = 0x12; break;
265 case CC_C: val = 0x16; break;
266 case CC_NC: val = 0x11; break;
267 case CC_O: val = 0x17; break;
268 case CC_NO: val = 0x10; break;
269
270 default:
271 val = 0;
272 assert(!"invalid condition code");
273 break;
274 }
275 code[pos / 32] |= val << (pos % 32);
276 }
277
278 void
279 CodeEmitterNVC0::emitPredicate(const Instruction *i)
280 {
281 if (i->predSrc >= 0) {
282 assert(i->getPredicate()->reg.file == FILE_PREDICATE);
283 srcId(i->src(i->predSrc), 10);
284 if (i->cc == CC_NOT_P)
285 code[0] |= 0x2000; // negate
286 } else {
287 code[0] |= 0x1c00;
288 }
289 }
290
291 void
292 CodeEmitterNVC0::setAddressByFile(const ValueRef& src)
293 {
294 switch (src.getFile()) {
295 case FILE_MEMORY_GLOBAL:
296 srcAddr32(src, 26, 0);
297 break;
298 case FILE_MEMORY_LOCAL:
299 case FILE_MEMORY_SHARED:
300 setAddress24(src);
301 break;
302 default:
303 assert(src.getFile() == FILE_MEMORY_CONST);
304 setAddress16(src);
305 break;
306 }
307 }
308
309 void
310 CodeEmitterNVC0::setAddress16(const ValueRef& src)
311 {
312 Symbol *sym = src.get()->asSym();
313
314 assert(sym);
315
316 code[0] |= (sym->reg.data.offset & 0x003f) << 26;
317 code[1] |= (sym->reg.data.offset & 0xffc0) >> 6;
318 }
319
320 void
321 CodeEmitterNVC0::setAddress24(const ValueRef& src)
322 {
323 Symbol *sym = src.get()->asSym();
324
325 assert(sym);
326
327 code[0] |= (sym->reg.data.offset & 0x00003f) << 26;
328 code[1] |= (sym->reg.data.offset & 0xffffc0) >> 6;
329 }
330
331 void
332 CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
333 {
334 const ImmediateValue *imm = i->src(s).get()->asImm();
335 uint32_t u32;
336
337 assert(imm);
338 u32 = imm->reg.data.u32;
339
340 if ((code[0] & 0xf) == 0x1) {
341 // double immediate
342 uint64_t u64 = imm->reg.data.u64;
343 assert(!(u64 & 0x00000fffffffffffULL));
344 assert(!(code[1] & 0xc000));
345 code[0] |= ((u64 >> 44) & 0x3f) << 26;
346 code[1] |= 0xc000 | (u64 >> 50);
347 } else
348 if ((code[0] & 0xf) == 0x2) {
349 // LIMM
350 code[0] |= (u32 & 0x3f) << 26;
351 code[1] |= u32 >> 6;
352 } else
353 if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
354 // integer immediate
355 assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
356 assert(!(code[1] & 0xc000));
357 u32 &= 0xfffff;
358 code[0] |= (u32 & 0x3f) << 26;
359 code[1] |= 0xc000 | (u32 >> 6);
360 } else {
361 // float immediate
362 assert(!(u32 & 0x00000fff));
363 assert(!(code[1] & 0xc000));
364 code[0] |= ((u32 >> 12) & 0x3f) << 26;
365 code[1] |= 0xc000 | (u32 >> 18);
366 }
367 }
368
369 void CodeEmitterNVC0::setImmediateS8(const ValueRef &ref)
370 {
371 const ImmediateValue *imm = ref.get()->asImm();
372
373 int8_t s8 = static_cast<int8_t>(imm->reg.data.s32);
374
375 assert(s8 == imm->reg.data.s32);
376
377 code[0] |= (s8 & 0x3f) << 26;
378 code[0] |= (s8 >> 6) << 8;
379 }
380
381 void CodeEmitterNVC0::setPDSTL(const Instruction *i, const int d)
382 {
383 assert(d < 0 || (i->defExists(d) && i->def(d).getFile() == FILE_PREDICATE));
384
385 uint32_t pred = d >= 0 ? DDATA(i->def(d)).id : 7;
386
387 code[0] |= (pred & 3) << 8;
388 code[1] |= (pred & 4) << (26 - 2);
389 }
390
391 void
392 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc)
393 {
394 code[0] = opc;
395 code[1] = opc >> 32;
396
397 emitPredicate(i);
398
399 defId(i->def(0), 14);
400
401 int s1 = 26;
402 if (i->srcExists(2) && i->getSrc(2)->reg.file == FILE_MEMORY_CONST)
403 s1 = 49;
404
405 for (int s = 0; s < 3 && i->srcExists(s); ++s) {
406 switch (i->getSrc(s)->reg.file) {
407 case FILE_MEMORY_CONST:
408 assert(!(code[1] & 0xc000));
409 code[1] |= (s == 2) ? 0x8000 : 0x4000;
410 code[1] |= i->getSrc(s)->reg.fileIndex << 10;
411 setAddress16(i->src(s));
412 break;
413 case FILE_IMMEDIATE:
414 assert(s == 1 ||
415 i->op == OP_MOV || i->op == OP_PRESIN || i->op == OP_PREEX2);
416 assert(!(code[1] & 0xc000));
417 setImmediate(i, s);
418 break;
419 case FILE_GPR:
420 if ((s == 2) && ((code[0] & 0x7) == 2)) // LIMM: 3rd src == dst
421 break;
422 srcId(i->src(s), s ? ((s == 2) ? 49 : s1) : 20);
423 break;
424 default:
425 if (i->op == OP_SELP) {
426 // OP_SELP is used to implement shared+atomics on Fermi.
427 assert(s == 2 && i->src(s).getFile() == FILE_PREDICATE);
428 srcId(i->src(s), 49);
429 }
430 // ignore here, can be predicate or flags, but must not be address
431 break;
432 }
433 }
434 }
435
436 void
437 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc)
438 {
439 code[0] = opc;
440 code[1] = opc >> 32;
441
442 emitPredicate(i);
443
444 defId(i->def(0), 14);
445
446 switch (i->src(0).getFile()) {
447 case FILE_MEMORY_CONST:
448 assert(!(code[1] & 0xc000));
449 code[1] |= 0x4000 | (i->src(0).get()->reg.fileIndex << 10);
450 setAddress16(i->src(0));
451 break;
452 case FILE_IMMEDIATE:
453 assert(!(code[1] & 0xc000));
454 setImmediate(i, 0);
455 break;
456 case FILE_GPR:
457 srcId(i->src(0), 26);
458 break;
459 default:
460 // ignore here, can be predicate or flags, but must not be address
461 break;
462 }
463 }
464
465 void
466 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred)
467 {
468 code[0] = opc;
469
470 int ss2a = 0;
471 if (opc == 0x0d || opc == 0x0e)
472 ss2a = 2;
473
474 defId(i->def(0), 14);
475 srcId(i->src(0), 20);
476
477 assert(pred || (i->predSrc < 0));
478 if (pred)
479 emitPredicate(i);
480
481 for (int s = 1; s < 3 && i->srcExists(s); ++s) {
482 if (i->src(s).get()->reg.file == FILE_MEMORY_CONST) {
483 assert(!(code[0] & (0x300 >> ss2a)));
484 switch (i->src(s).get()->reg.fileIndex) {
485 case 0: code[0] |= 0x100 >> ss2a; break;
486 case 1: code[0] |= 0x200 >> ss2a; break;
487 case 16: code[0] |= 0x300 >> ss2a; break;
488 default:
489 ERROR("invalid c[] space for short form\n");
490 break;
491 }
492 if (s == 1)
493 code[0] |= i->getSrc(s)->reg.data.offset << 24;
494 else
495 code[0] |= i->getSrc(s)->reg.data.offset << 6;
496 } else
497 if (i->src(s).getFile() == FILE_IMMEDIATE) {
498 assert(s == 1);
499 setImmediateS8(i->src(s));
500 } else
501 if (i->src(s).getFile() == FILE_GPR) {
502 srcId(i->src(s), (s == 1) ? 26 : 8);
503 }
504 }
505 }
506
507 void
508 CodeEmitterNVC0::emitShortSrc2(const ValueRef &src)
509 {
510 if (src.getFile() == FILE_MEMORY_CONST) {
511 switch (src.get()->reg.fileIndex) {
512 case 0: code[0] |= 0x100; break;
513 case 1: code[0] |= 0x200; break;
514 case 16: code[0] |= 0x300; break;
515 default:
516 assert(!"unsupported file index for short op");
517 break;
518 }
519 srcAddr32(src, 20, 2);
520 } else {
521 srcId(src, 20);
522 assert(src.getFile() == FILE_GPR);
523 }
524 }
525
526 void
527 CodeEmitterNVC0::emitNOP(const Instruction *i)
528 {
529 code[0] = 0x000001e4;
530 code[1] = 0x40000000;
531 emitPredicate(i);
532 }
533
534 void
535 CodeEmitterNVC0::emitFMAD(const Instruction *i)
536 {
537 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
538
539 if (i->encSize == 8) {
540 if (isLIMM(i->src(1), TYPE_F32)) {
541 emitForm_A(i, HEX64(20000000, 00000002));
542 } else {
543 emitForm_A(i, HEX64(30000000, 00000000));
544
545 if (i->src(2).mod.neg())
546 code[0] |= 1 << 8;
547 }
548 roundMode_A(i);
549
550 if (neg1)
551 code[0] |= 1 << 9;
552
553 if (i->saturate)
554 code[0] |= 1 << 5;
555
556 if (i->dnz)
557 code[0] |= 1 << 7;
558 else
559 if (i->ftz)
560 code[0] |= 1 << 6;
561 } else {
562 assert(!i->saturate && !i->src(2).mod.neg());
563 emitForm_S(i, (i->src(2).getFile() == FILE_MEMORY_CONST) ? 0x2e : 0x0e,
564 false);
565 if (neg1)
566 code[0] |= 1 << 4;
567 }
568 }
569
570 void
571 CodeEmitterNVC0::emitDMAD(const Instruction *i)
572 {
573 bool neg1 = (i->src(0).mod ^ i->src(1).mod).neg();
574
575 emitForm_A(i, HEX64(20000000, 00000001));
576
577 if (i->src(2).mod.neg())
578 code[0] |= 1 << 8;
579
580 roundMode_A(i);
581
582 if (neg1)
583 code[0] |= 1 << 9;
584
585 assert(!i->saturate);
586 assert(!i->ftz);
587 }
588
589 void
590 CodeEmitterNVC0::emitFMUL(const Instruction *i)
591 {
592 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
593
594 assert(i->postFactor >= -3 && i->postFactor <= 3);
595
596 if (i->encSize == 8) {
597 if (isLIMM(i->src(1), TYPE_F32)) {
598 assert(i->postFactor == 0); // constant folded, hopefully
599 emitForm_A(i, HEX64(30000000, 00000002));
600 } else {
601 emitForm_A(i, HEX64(58000000, 00000000));
602 roundMode_A(i);
603 code[1] |= ((i->postFactor > 0) ?
604 (7 - i->postFactor) : (0 - i->postFactor)) << 17;
605 }
606 if (neg)
607 code[1] ^= 1 << 25; // aliases with LIMM sign bit
608
609 if (i->saturate)
610 code[0] |= 1 << 5;
611
612 if (i->dnz)
613 code[0] |= 1 << 7;
614 else
615 if (i->ftz)
616 code[0] |= 1 << 6;
617 } else {
618 assert(!neg && !i->saturate && !i->ftz && !i->postFactor);
619 emitForm_S(i, 0xa8, true);
620 }
621 }
622
623 void
624 CodeEmitterNVC0::emitDMUL(const Instruction *i)
625 {
626 bool neg = (i->src(0).mod ^ i->src(1).mod).neg();
627
628 emitForm_A(i, HEX64(50000000, 00000001));
629 roundMode_A(i);
630
631 if (neg)
632 code[0] |= 1 << 9;
633
634 assert(!i->saturate);
635 assert(!i->ftz);
636 assert(!i->dnz);
637 assert(!i->postFactor);
638 }
639
640 void
641 CodeEmitterNVC0::emitUMUL(const Instruction *i)
642 {
643 if (i->encSize == 8) {
644 if (i->src(1).getFile() == FILE_IMMEDIATE) {
645 emitForm_A(i, HEX64(10000000, 00000002));
646 } else {
647 emitForm_A(i, HEX64(50000000, 00000003));
648 }
649 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
650 code[0] |= 1 << 6;
651 if (i->sType == TYPE_S32)
652 code[0] |= 1 << 5;
653 if (i->dType == TYPE_S32)
654 code[0] |= 1 << 7;
655 } else {
656 emitForm_S(i, i->src(1).getFile() == FILE_IMMEDIATE ? 0xaa : 0x2a, true);
657
658 if (i->sType == TYPE_S32)
659 code[0] |= 1 << 6;
660 }
661 }
662
663 void
664 CodeEmitterNVC0::emitFADD(const Instruction *i)
665 {
666 if (i->encSize == 8) {
667 if (isLIMM(i->src(1), TYPE_F32)) {
668 assert(!i->saturate);
669 emitForm_A(i, HEX64(28000000, 00000002));
670
671 code[0] |= i->src(0).mod.abs() << 7;
672 code[0] |= i->src(0).mod.neg() << 9;
673
674 if (i->src(1).mod.abs())
675 code[1] &= 0xfdffffff;
676 if ((i->op == OP_SUB) != static_cast<bool>(i->src(1).mod.neg()))
677 code[1] ^= 0x02000000;
678 } else {
679 emitForm_A(i, HEX64(50000000, 00000000));
680
681 roundMode_A(i);
682 if (i->saturate)
683 code[1] |= 1 << 17;
684
685 emitNegAbs12(i);
686 if (i->op == OP_SUB) code[0] ^= 1 << 8;
687 }
688 if (i->ftz)
689 code[0] |= 1 << 5;
690 } else {
691 assert(!i->saturate && i->op != OP_SUB &&
692 !i->src(0).mod.abs() &&
693 !i->src(1).mod.neg() && !i->src(1).mod.abs());
694
695 emitForm_S(i, 0x49, true);
696
697 if (i->src(0).mod.neg())
698 code[0] |= 1 << 7;
699 }
700 }
701
702 void
703 CodeEmitterNVC0::emitDADD(const Instruction *i)
704 {
705 assert(i->encSize == 8);
706 emitForm_A(i, HEX64(48000000, 00000001));
707 roundMode_A(i);
708 assert(!i->saturate);
709 assert(!i->ftz);
710 emitNegAbs12(i);
711 if (i->op == OP_SUB)
712 code[0] ^= 1 << 8;
713 }
714
715 void
716 CodeEmitterNVC0::emitUADD(const Instruction *i)
717 {
718 uint32_t addOp = 0;
719
720 assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
721
722 if (i->src(0).mod.neg())
723 addOp |= 0x200;
724 if (i->src(1).mod.neg())
725 addOp |= 0x100;
726 if (i->op == OP_SUB)
727 addOp ^= 0x100;
728
729 assert(addOp != 0x300); // would be add-plus-one
730
731 if (i->encSize == 8) {
732 if (isLIMM(i->src(1), TYPE_U32)) {
733 emitForm_A(i, HEX64(08000000, 00000002));
734 if (i->flagsDef >= 0)
735 code[1] |= 1 << 26; // write carry
736 } else {
737 emitForm_A(i, HEX64(48000000, 00000003));
738 if (i->flagsDef >= 0)
739 code[1] |= 1 << 16; // write carry
740 }
741 code[0] |= addOp;
742
743 if (i->saturate)
744 code[0] |= 1 << 5;
745 if (i->flagsSrc >= 0) // add carry
746 code[0] |= 1 << 6;
747 } else {
748 assert(!(addOp & 0x100));
749 emitForm_S(i, (addOp >> 3) |
750 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0xac : 0x2c), true);
751 }
752 }
753
754 void
755 CodeEmitterNVC0::emitIMAD(const Instruction *i)
756 {
757 uint8_t addOp =
758 i->src(2).mod.neg() | ((i->src(0).mod.neg() ^ i->src(1).mod.neg()) << 1);
759
760 assert(i->encSize == 8);
761 emitForm_A(i, HEX64(20000000, 00000003));
762
763 assert(addOp != 3);
764 code[0] |= addOp << 8;
765
766 if (isSignedType(i->dType))
767 code[0] |= 1 << 7;
768 if (isSignedType(i->sType))
769 code[0] |= 1 << 5;
770
771 code[1] |= i->saturate << 24;
772
773 if (i->flagsDef >= 0) code[1] |= 1 << 16;
774 if (i->flagsSrc >= 0) code[1] |= 1 << 23;
775
776 if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
777 code[0] |= 1 << 6;
778 }
779
780 void
781 CodeEmitterNVC0::emitSHLADD(const Instruction *i)
782 {
783 uint8_t addOp = (i->src(0).mod.neg() << 1) | i->src(2).mod.neg();
784 const ImmediateValue *imm = i->src(1).get()->asImm();
785 assert(imm);
786
787 code[0] = 0x00000003;
788 code[1] = 0x40000000 | addOp << 23;
789
790 emitPredicate(i);
791
792 defId(i->def(0), 14);
793 srcId(i->src(0), 20);
794
795 if (i->flagsDef >= 0)
796 code[1] |= 1 << 16;
797
798 assert(!(imm->reg.data.u32 & 0xffffffe0));
799 code[0] |= imm->reg.data.u32 << 5;
800
801 switch (i->src(2).getFile()) {
802 case FILE_GPR:
803 srcId(i->src(2), 26);
804 break;
805 case FILE_MEMORY_CONST:
806 code[1] |= 0x4000;
807 code[1] |= i->getSrc(2)->reg.fileIndex << 10;
808 setAddress16(i->src(2));
809 break;
810 case FILE_IMMEDIATE:
811 setImmediate(i, 2);
812 break;
813 default:
814 assert(!"bad src2 file");
815 break;
816 }
817 }
818
819 void
820 CodeEmitterNVC0::emitMADSP(const Instruction *i)
821 {
822 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
823
824 emitForm_A(i, HEX64(00000000, 00000003));
825
826 if (i->subOp == NV50_IR_SUBOP_MADSP_SD) {
827 code[1] |= 0x01800000;
828 } else {
829 code[0] |= (i->subOp & 0x00f) << 7;
830 code[0] |= (i->subOp & 0x0f0) << 1;
831 code[0] |= (i->subOp & 0x100) >> 3;
832 code[0] |= (i->subOp & 0x200) >> 2;
833 code[1] |= (i->subOp & 0xc00) << 13;
834 }
835
836 if (i->flagsDef >= 0)
837 code[1] |= 1 << 16;
838 }
839
840 void
841 CodeEmitterNVC0::emitISAD(const Instruction *i)
842 {
843 assert(i->dType == TYPE_S32 || i->dType == TYPE_U32);
844 assert(i->encSize == 8);
845
846 emitForm_A(i, HEX64(38000000, 00000003));
847
848 if (i->dType == TYPE_S32)
849 code[0] |= 1 << 5;
850 }
851
852 void
853 CodeEmitterNVC0::emitNOT(Instruction *i)
854 {
855 assert(i->encSize == 8);
856 i->setSrc(1, i->src(0));
857 emitForm_A(i, HEX64(68000000, 000001c3));
858 }
859
860 void
861 CodeEmitterNVC0::emitLogicOp(const Instruction *i, uint8_t subOp)
862 {
863 if (i->def(0).getFile() == FILE_PREDICATE) {
864 code[0] = 0x00000004 | (subOp << 30);
865 code[1] = 0x0c000000;
866
867 emitPredicate(i);
868
869 defId(i->def(0), 17);
870 srcId(i->src(0), 20);
871 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 23;
872 srcId(i->src(1), 26);
873 if (i->src(1).mod == Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 29;
874
875 if (i->defExists(1)) {
876 defId(i->def(1), 14);
877 } else {
878 code[0] |= 7 << 14;
879 }
880 // (a OP b) OP c
881 if (i->predSrc != 2 && i->srcExists(2)) {
882 code[1] |= subOp << 21;
883 srcId(i->src(2), 49);
884 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT)) code[1] |= 1 << 20;
885 } else {
886 code[1] |= 0x000e0000;
887 }
888 } else
889 if (i->encSize == 8) {
890 if (isLIMM(i->src(1), TYPE_U32)) {
891 emitForm_A(i, HEX64(38000000, 00000002));
892
893 if (i->flagsDef >= 0)
894 code[1] |= 1 << 26;
895 } else {
896 emitForm_A(i, HEX64(68000000, 00000003));
897
898 if (i->flagsDef >= 0)
899 code[1] |= 1 << 16;
900 }
901 code[0] |= subOp << 6;
902
903 if (i->flagsSrc >= 0) // carry
904 code[0] |= 1 << 5;
905
906 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
907 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
908 } else {
909 emitForm_S(i, (subOp << 5) |
910 ((i->src(1).getFile() == FILE_IMMEDIATE) ? 0x1d : 0x8d), true);
911 }
912 }
913
914 void
915 CodeEmitterNVC0::emitPOPC(const Instruction *i)
916 {
917 emitForm_A(i, HEX64(54000000, 00000004));
918
919 if (i->src(0).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 9;
920 if (i->src(1).mod & Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 << 8;
921 }
922
923 void
924 CodeEmitterNVC0::emitINSBF(const Instruction *i)
925 {
926 emitForm_A(i, HEX64(28000000, 00000003));
927 }
928
929 void
930 CodeEmitterNVC0::emitEXTBF(const Instruction *i)
931 {
932 emitForm_A(i, HEX64(70000000, 00000003));
933
934 if (i->dType == TYPE_S32)
935 code[0] |= 1 << 5;
936 if (i->subOp == NV50_IR_SUBOP_EXTBF_REV)
937 code[0] |= 1 << 8;
938 }
939
940 void
941 CodeEmitterNVC0::emitBFIND(const Instruction *i)
942 {
943 emitForm_B(i, HEX64(78000000, 00000003));
944
945 if (i->dType == TYPE_S32)
946 code[0] |= 1 << 5;
947 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
948 code[0] |= 1 << 8;
949 if (i->subOp == NV50_IR_SUBOP_BFIND_SAMT)
950 code[0] |= 1 << 6;
951 }
952
953 void
954 CodeEmitterNVC0::emitPERMT(const Instruction *i)
955 {
956 emitForm_A(i, HEX64(24000000, 00000004));
957
958 code[0] |= i->subOp << 5;
959 }
960
961 void
962 CodeEmitterNVC0::emitShift(const Instruction *i)
963 {
964 if (i->op == OP_SHR) {
965 emitForm_A(i, HEX64(58000000, 00000003)
966 | (isSignedType(i->dType) ? 0x20 : 0x00));
967 } else {
968 emitForm_A(i, HEX64(60000000, 00000003));
969 }
970
971 if (i->subOp == NV50_IR_SUBOP_SHIFT_WRAP)
972 code[0] |= 1 << 9;
973 }
974
975 void
976 CodeEmitterNVC0::emitPreOp(const Instruction *i)
977 {
978 if (i->encSize == 8) {
979 emitForm_B(i, HEX64(60000000, 00000000));
980
981 if (i->op == OP_PREEX2)
982 code[0] |= 0x20;
983
984 if (i->src(0).mod.abs()) code[0] |= 1 << 6;
985 if (i->src(0).mod.neg()) code[0] |= 1 << 8;
986 } else {
987 emitForm_S(i, i->op == OP_PREEX2 ? 0x74000008 : 0x70000008, true);
988 }
989 }
990
991 void
992 CodeEmitterNVC0::emitSFnOp(const Instruction *i, uint8_t subOp)
993 {
994 if (i->encSize == 8) {
995 code[0] = 0x00000000 | (subOp << 26);
996 code[1] = 0xc8000000;
997
998 emitPredicate(i);
999
1000 defId(i->def(0), 14);
1001 srcId(i->src(0), 20);
1002
1003 assert(i->src(0).getFile() == FILE_GPR);
1004
1005 if (i->saturate) code[0] |= 1 << 5;
1006
1007 if (i->src(0).mod.abs()) code[0] |= 1 << 7;
1008 if (i->src(0).mod.neg()) code[0] |= 1 << 9;
1009 } else {
1010 emitForm_S(i, 0x80000008 | (subOp << 26), true);
1011
1012 assert(!i->src(0).mod.neg());
1013 if (i->src(0).mod.abs()) code[0] |= 1 << 30;
1014 }
1015 }
1016
1017 void
1018 CodeEmitterNVC0::emitMINMAX(const Instruction *i)
1019 {
1020 uint64_t op;
1021
1022 assert(i->encSize == 8);
1023
1024 op = (i->op == OP_MIN) ? 0x080e000000000000ULL : 0x081e000000000000ULL;
1025
1026 if (i->ftz)
1027 op |= 1 << 5;
1028 else
1029 if (!isFloatType(i->dType)) {
1030 op |= isSignedType(i->dType) ? 0x23 : 0x03;
1031 op |= i->subOp << 6;
1032 }
1033 if (i->dType == TYPE_F64)
1034 op |= 0x01;
1035
1036 emitForm_A(i, op);
1037 emitNegAbs12(i);
1038
1039 if (i->flagsDef >= 0)
1040 code[1] |= 1 << 16;
1041 }
1042
1043 void
1044 CodeEmitterNVC0::roundMode_C(const Instruction *i)
1045 {
1046 switch (i->rnd) {
1047 case ROUND_M: code[1] |= 1 << 17; break;
1048 case ROUND_P: code[1] |= 2 << 17; break;
1049 case ROUND_Z: code[1] |= 3 << 17; break;
1050 case ROUND_NI: code[0] |= 1 << 7; break;
1051 case ROUND_MI: code[0] |= 1 << 7; code[1] |= 1 << 17; break;
1052 case ROUND_PI: code[0] |= 1 << 7; code[1] |= 2 << 17; break;
1053 case ROUND_ZI: code[0] |= 1 << 7; code[1] |= 3 << 17; break;
1054 case ROUND_N: break;
1055 default:
1056 assert(!"invalid round mode");
1057 break;
1058 }
1059 }
1060
1061 void
1062 CodeEmitterNVC0::roundMode_CS(const Instruction *i)
1063 {
1064 switch (i->rnd) {
1065 case ROUND_M:
1066 case ROUND_MI: code[0] |= 1 << 16; break;
1067 case ROUND_P:
1068 case ROUND_PI: code[0] |= 2 << 16; break;
1069 case ROUND_Z:
1070 case ROUND_ZI: code[0] |= 3 << 16; break;
1071 default:
1072 break;
1073 }
1074 }
1075
1076 void
1077 CodeEmitterNVC0::emitCVT(Instruction *i)
1078 {
1079 const bool f2f = isFloatType(i->dType) && isFloatType(i->sType);
1080 DataType dType;
1081
1082 switch (i->op) {
1083 case OP_CEIL: i->rnd = f2f ? ROUND_PI : ROUND_P; break;
1084 case OP_FLOOR: i->rnd = f2f ? ROUND_MI : ROUND_M; break;
1085 case OP_TRUNC: i->rnd = f2f ? ROUND_ZI : ROUND_Z; break;
1086 default:
1087 break;
1088 }
1089
1090 const bool sat = (i->op == OP_SAT) || i->saturate;
1091 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1092 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg();
1093
1094 if (i->op == OP_NEG && i->dType == TYPE_U32)
1095 dType = TYPE_S32;
1096 else
1097 dType = i->dType;
1098
1099 if (i->encSize == 8) {
1100 emitForm_B(i, HEX64(10000000, 00000004));
1101
1102 roundMode_C(i);
1103
1104 // cvt u16 f32 sets high bits to 0, so we don't have to use Value::Size()
1105 code[0] |= util_logbase2(typeSizeof(dType)) << 20;
1106 code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
1107
1108 // for 8/16 source types, the byte/word is in subOp. word 1 is
1109 // represented as 2.
1110 if (!isFloatType(i->sType))
1111 code[1] |= i->subOp << 0x17;
1112 else
1113 code[1] |= i->subOp << 0x18;
1114
1115 if (sat)
1116 code[0] |= 0x20;
1117 if (abs)
1118 code[0] |= 1 << 6;
1119 if (neg && i->op != OP_ABS)
1120 code[0] |= 1 << 8;
1121
1122 if (i->ftz)
1123 code[1] |= 1 << 23;
1124
1125 if (isSignedIntType(dType))
1126 code[0] |= 0x080;
1127 if (isSignedIntType(i->sType))
1128 code[0] |= 0x200;
1129
1130 if (isFloatType(dType)) {
1131 if (!isFloatType(i->sType))
1132 code[1] |= 0x08000000;
1133 } else {
1134 if (isFloatType(i->sType))
1135 code[1] |= 0x04000000;
1136 else
1137 code[1] |= 0x0c000000;
1138 }
1139 } else {
1140 if (i->op == OP_CEIL || i->op == OP_FLOOR || i->op == OP_TRUNC) {
1141 code[0] = 0x298;
1142 } else
1143 if (isFloatType(dType)) {
1144 if (isFloatType(i->sType))
1145 code[0] = 0x098;
1146 else
1147 code[0] = 0x088 | (isSignedType(i->sType) ? (1 << 8) : 0);
1148 } else {
1149 assert(isFloatType(i->sType));
1150
1151 code[0] = 0x288 | (isSignedType(i->sType) ? (1 << 8) : 0);
1152 }
1153
1154 if (neg) code[0] |= 1 << 16;
1155 if (sat) code[0] |= 1 << 18;
1156 if (abs) code[0] |= 1 << 19;
1157
1158 roundMode_CS(i);
1159 }
1160 }
1161
1162 void
1163 CodeEmitterNVC0::emitSET(const CmpInstruction *i)
1164 {
1165 uint32_t hi;
1166 uint32_t lo = 0;
1167
1168 if (i->sType == TYPE_F64)
1169 lo = 0x1;
1170 else
1171 if (!isFloatType(i->sType))
1172 lo = 0x3;
1173
1174 if (isSignedIntType(i->sType))
1175 lo |= 0x20;
1176 if (isFloatType(i->dType)) {
1177 if (isFloatType(i->sType))
1178 lo |= 0x20;
1179 else
1180 lo |= 0x80;
1181 }
1182
1183 switch (i->op) {
1184 case OP_SET_AND: hi = 0x10000000; break;
1185 case OP_SET_OR: hi = 0x10200000; break;
1186 case OP_SET_XOR: hi = 0x10400000; break;
1187 default:
1188 hi = 0x100e0000;
1189 break;
1190 }
1191 emitForm_A(i, (static_cast<uint64_t>(hi) << 32) | lo);
1192
1193 if (i->op != OP_SET)
1194 srcId(i->src(2), 32 + 17);
1195
1196 if (i->def(0).getFile() == FILE_PREDICATE) {
1197 if (i->sType == TYPE_F32)
1198 code[1] += 0x10000000;
1199 else
1200 code[1] += 0x08000000;
1201
1202 code[0] &= ~0xfc000;
1203 defId(i->def(0), 17);
1204 if (i->defExists(1))
1205 defId(i->def(1), 14);
1206 else
1207 code[0] |= 0x1c000;
1208 }
1209
1210 if (i->ftz)
1211 code[1] |= 1 << 27;
1212 if (i->flagsSrc >= 0)
1213 code[0] |= 1 << 6;
1214
1215 emitCondCode(i->setCond, 32 + 23);
1216 emitNegAbs12(i);
1217 }
1218
1219 void
1220 CodeEmitterNVC0::emitSLCT(const CmpInstruction *i)
1221 {
1222 uint64_t op;
1223
1224 switch (i->dType) {
1225 case TYPE_S32:
1226 op = HEX64(30000000, 00000023);
1227 break;
1228 case TYPE_U32:
1229 op = HEX64(30000000, 00000003);
1230 break;
1231 case TYPE_F32:
1232 op = HEX64(38000000, 00000000);
1233 break;
1234 default:
1235 assert(!"invalid type for SLCT");
1236 op = 0;
1237 break;
1238 }
1239 emitForm_A(i, op);
1240
1241 CondCode cc = i->setCond;
1242
1243 if (i->src(2).mod.neg())
1244 cc = reverseCondCode(cc);
1245
1246 emitCondCode(cc, 32 + 23);
1247
1248 if (i->ftz)
1249 code[0] |= 1 << 5;
1250 }
1251
1252 static void
1253 selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1254 {
1255 int loc = entry->loc;
1256 if (data.force_persample_interp)
1257 code[loc + 1] |= 1 << 20;
1258 else
1259 code[loc + 1] &= ~(1 << 20);
1260 }
1261
1262 void CodeEmitterNVC0::emitSELP(const Instruction *i)
1263 {
1264 emitForm_A(i, HEX64(20000000, 00000004));
1265
1266 if (i->src(2).mod & Modifier(NV50_IR_MOD_NOT))
1267 code[1] |= 1 << 20;
1268
1269 if (i->subOp == 1) {
1270 addInterp(0, 0, selpFlip);
1271 }
1272 }
1273
1274 void CodeEmitterNVC0::emitTEXBAR(const Instruction *i)
1275 {
1276 code[0] = 0x00000006 | (i->subOp << 26);
1277 code[1] = 0xf0000000;
1278 emitPredicate(i);
1279 emitCondCode(i->flagsSrc >= 0 ? i->cc : CC_ALWAYS, 5);
1280 }
1281
1282 void CodeEmitterNVC0::emitTEXCSAA(const TexInstruction *i)
1283 {
1284 code[0] = 0x00000086;
1285 code[1] = 0xd0000000;
1286
1287 code[1] |= i->tex.r;
1288 code[1] |= i->tex.s << 8;
1289
1290 if (i->tex.liveOnly)
1291 code[0] |= 1 << 9;
1292
1293 defId(i->def(0), 14);
1294 srcId(i->src(0), 20);
1295 }
1296
1297 static inline bool
1298 isNextIndependentTex(const TexInstruction *i)
1299 {
1300 if (!i->next || !isTextureOp(i->next->op))
1301 return false;
1302 if (i->getDef(0)->interfers(i->next->getSrc(0)))
1303 return false;
1304 return !i->next->srcExists(1) || !i->getDef(0)->interfers(i->next->getSrc(1));
1305 }
1306
1307 void
1308 CodeEmitterNVC0::emitTEX(const TexInstruction *i)
1309 {
1310 code[0] = 0x00000006;
1311
1312 if (isNextIndependentTex(i))
1313 code[0] |= 0x080; // t mode
1314 else
1315 code[0] |= 0x100; // p mode
1316
1317 if (i->tex.liveOnly)
1318 code[0] |= 1 << 9;
1319
1320 switch (i->op) {
1321 case OP_TEX: code[1] = 0x80000000; break;
1322 case OP_TXB: code[1] = 0x84000000; break;
1323 case OP_TXL: code[1] = 0x86000000; break;
1324 case OP_TXF: code[1] = 0x90000000; break;
1325 case OP_TXG: code[1] = 0xa0000000; break;
1326 case OP_TXLQ: code[1] = 0xb0000000; break;
1327 case OP_TXD: code[1] = 0xe0000000; break;
1328 default:
1329 assert(!"invalid texture op");
1330 break;
1331 }
1332 if (i->op == OP_TXF) {
1333 if (!i->tex.levelZero)
1334 code[1] |= 0x02000000;
1335 } else
1336 if (i->tex.levelZero) {
1337 code[1] |= 0x02000000;
1338 }
1339
1340 if (i->op != OP_TXD && i->tex.derivAll)
1341 code[1] |= 1 << 13;
1342
1343 defId(i->def(0), 14);
1344 srcId(i->src(0), 20);
1345
1346 emitPredicate(i);
1347
1348 if (i->op == OP_TXG) code[0] |= i->tex.gatherComp << 5;
1349
1350 code[1] |= i->tex.mask << 14;
1351
1352 code[1] |= i->tex.r;
1353 code[1] |= i->tex.s << 8;
1354 if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0)
1355 code[1] |= 1 << 18; // in 1st source (with array index)
1356
1357 // texture target:
1358 code[1] |= (i->tex.target.getDim() - 1) << 20;
1359 if (i->tex.target.isCube())
1360 code[1] += 2 << 20;
1361 if (i->tex.target.isArray())
1362 code[1] |= 1 << 19;
1363 if (i->tex.target.isShadow())
1364 code[1] |= 1 << 24;
1365
1366 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1367
1368 if (i->srcExists(src1) && i->src(src1).getFile() == FILE_IMMEDIATE) {
1369 // lzero
1370 if (i->op == OP_TXL)
1371 code[1] &= ~(1 << 26);
1372 else
1373 if (i->op == OP_TXF)
1374 code[1] &= ~(1 << 25);
1375 }
1376 if (i->tex.target == TEX_TARGET_2D_MS ||
1377 i->tex.target == TEX_TARGET_2D_MS_ARRAY)
1378 code[1] |= 1 << 23;
1379
1380 if (i->tex.useOffsets == 1)
1381 code[1] |= 1 << 22;
1382 if (i->tex.useOffsets == 4)
1383 code[1] |= 1 << 23;
1384
1385 srcId(i, src1, 26);
1386 }
1387
1388 void
1389 CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
1390 {
1391 code[0] = 0x00000086;
1392 code[1] = 0xc0000000;
1393
1394 switch (i->tex.query) {
1395 case TXQ_DIMS: code[1] |= 0 << 22; break;
1396 case TXQ_TYPE: code[1] |= 1 << 22; break;
1397 case TXQ_SAMPLE_POSITION: code[1] |= 2 << 22; break;
1398 case TXQ_FILTER: code[1] |= 3 << 22; break;
1399 case TXQ_LOD: code[1] |= 4 << 22; break;
1400 case TXQ_BORDER_COLOUR: code[1] |= 5 << 22; break;
1401 default:
1402 assert(!"invalid texture query");
1403 break;
1404 }
1405
1406 code[1] |= i->tex.mask << 14;
1407
1408 code[1] |= i->tex.r;
1409 code[1] |= i->tex.s << 8;
1410 if (i->tex.sIndirectSrc >= 0 || i->tex.rIndirectSrc >= 0)
1411 code[1] |= 1 << 18;
1412
1413 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1414
1415 defId(i->def(0), 14);
1416 srcId(i->src(0), 20);
1417 srcId(i, src1, 26);
1418
1419 emitPredicate(i);
1420 }
1421
1422 void
1423 CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
1424 {
1425 code[0] = 0x00000200 | (laneMask << 6); // dall
1426 code[1] = 0x48000000 | qOp;
1427
1428 defId(i->def(0), 14);
1429 srcId(i->src(0), 20);
1430 srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
1431
1432 emitPredicate(i);
1433 }
1434
1435 void
1436 CodeEmitterNVC0::emitFlow(const Instruction *i)
1437 {
1438 const FlowInstruction *f = i->asFlow();
1439
1440 unsigned mask; // bit 0: predicate, bit 1: target
1441
1442 code[0] = 0x00000007;
1443
1444 switch (i->op) {
1445 case OP_BRA:
1446 code[1] = f->absolute ? 0x00000000 : 0x40000000;
1447 if (i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST)
1448 code[0] |= 0x4000;
1449 mask = 3;
1450 break;
1451 case OP_CALL:
1452 code[1] = f->absolute ? 0x10000000 : 0x50000000;
1453 if (f->indirect)
1454 code[0] |= 0x4000; // indirect calls always use c[] source
1455 mask = 2;
1456 break;
1457
1458 case OP_EXIT: code[1] = 0x80000000; mask = 1; break;
1459 case OP_RET: code[1] = 0x90000000; mask = 1; break;
1460 case OP_DISCARD: code[1] = 0x98000000; mask = 1; break;
1461 case OP_BREAK: code[1] = 0xa8000000; mask = 1; break;
1462 case OP_CONT: code[1] = 0xb0000000; mask = 1; break;
1463
1464 case OP_JOINAT: code[1] = 0x60000000; mask = 2; break;
1465 case OP_PREBREAK: code[1] = 0x68000000; mask = 2; break;
1466 case OP_PRECONT: code[1] = 0x70000000; mask = 2; break;
1467 case OP_PRERET: code[1] = 0x78000000; mask = 2; break;
1468
1469 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
1470 case OP_QUADPOP: code[1] = 0xc8000000; mask = 0; break;
1471 case OP_BRKPT: code[1] = 0xd0000000; mask = 0; break;
1472 default:
1473 assert(!"invalid flow operation");
1474 return;
1475 }
1476
1477 if (mask & 1) {
1478 emitPredicate(i);
1479 if (i->flagsSrc < 0)
1480 code[0] |= 0x1e0;
1481 }
1482
1483 if (!f)
1484 return;
1485
1486 if (f->allWarp)
1487 code[0] |= 1 << 15;
1488 if (f->limit)
1489 code[0] |= 1 << 16;
1490
1491 if (f->indirect) {
1492 if (code[0] & 0x4000) {
1493 assert(i->srcExists(0) && i->src(0).getFile() == FILE_MEMORY_CONST);
1494 setAddress16(i->src(0));
1495 code[1] |= i->getSrc(0)->reg.fileIndex << 10;
1496 if (f->op == OP_BRA)
1497 srcId(f->src(0).getIndirect(0), 20);
1498 } else {
1499 srcId(f, 0, 20);
1500 }
1501 }
1502
1503 if (f->op == OP_CALL) {
1504 if (f->indirect) {
1505 // nothing
1506 } else
1507 if (f->builtin) {
1508 assert(f->absolute);
1509 uint32_t pcAbs = targNVC0->getBuiltinOffset(f->target.builtin);
1510 addReloc(RelocEntry::TYPE_BUILTIN, 0, pcAbs, 0xfc000000, 26);
1511 addReloc(RelocEntry::TYPE_BUILTIN, 1, pcAbs, 0x03ffffff, -6);
1512 } else {
1513 assert(!f->absolute);
1514 int32_t pcRel = f->target.fn->binPos - (codeSize + 8);
1515 code[0] |= (pcRel & 0x3f) << 26;
1516 code[1] |= (pcRel >> 6) & 0x3ffff;
1517 }
1518 } else
1519 if (mask & 2) {
1520 int32_t pcRel = f->target.bb->binPos - (codeSize + 8);
1521 if (writeIssueDelays && !(f->target.bb->binPos & 0x3f))
1522 pcRel += 8;
1523 // currently we don't want absolute branches
1524 assert(!f->absolute);
1525 code[0] |= (pcRel & 0x3f) << 26;
1526 code[1] |= (pcRel >> 6) & 0x3ffff;
1527 }
1528 }
1529
1530 void
1531 CodeEmitterNVC0::emitBAR(const Instruction *i)
1532 {
1533 Value *rDef = NULL, *pDef = NULL;
1534
1535 switch (i->subOp) {
1536 case NV50_IR_SUBOP_BAR_ARRIVE: code[0] = 0x84; break;
1537 case NV50_IR_SUBOP_BAR_RED_AND: code[0] = 0x24; break;
1538 case NV50_IR_SUBOP_BAR_RED_OR: code[0] = 0x44; break;
1539 case NV50_IR_SUBOP_BAR_RED_POPC: code[0] = 0x04; break;
1540 default:
1541 code[0] = 0x04;
1542 assert(i->subOp == NV50_IR_SUBOP_BAR_SYNC);
1543 break;
1544 }
1545 code[1] = 0x50000000;
1546
1547 code[0] |= 63 << 14;
1548 code[1] |= 7 << 21;
1549
1550 emitPredicate(i);
1551
1552 // barrier id
1553 if (i->src(0).getFile() == FILE_GPR) {
1554 srcId(i->src(0), 20);
1555 } else {
1556 ImmediateValue *imm = i->getSrc(0)->asImm();
1557 assert(imm);
1558 code[0] |= imm->reg.data.u32 << 20;
1559 code[1] |= 0x8000;
1560 }
1561
1562 // thread count
1563 if (i->src(1).getFile() == FILE_GPR) {
1564 srcId(i->src(1), 26);
1565 } else {
1566 ImmediateValue *imm = i->getSrc(1)->asImm();
1567 assert(imm);
1568 assert(imm->reg.data.u32 <= 0xfff);
1569 code[0] |= imm->reg.data.u32 << 26;
1570 code[1] |= imm->reg.data.u32 >> 6;
1571 code[1] |= 0x4000;
1572 }
1573
1574 if (i->srcExists(2) && (i->predSrc != 2)) {
1575 srcId(i->src(2), 32 + 17);
1576 if (i->src(2).mod == Modifier(NV50_IR_MOD_NOT))
1577 code[1] |= 1 << 20;
1578 } else {
1579 code[1] |= 7 << 17;
1580 }
1581
1582 if (i->defExists(0)) {
1583 if (i->def(0).getFile() == FILE_GPR)
1584 rDef = i->getDef(0);
1585 else
1586 pDef = i->getDef(0);
1587
1588 if (i->defExists(1)) {
1589 if (i->def(1).getFile() == FILE_GPR)
1590 rDef = i->getDef(1);
1591 else
1592 pDef = i->getDef(1);
1593 }
1594 }
1595 if (rDef) {
1596 code[0] &= ~(63 << 14);
1597 defId(rDef, 14);
1598 }
1599 if (pDef) {
1600 code[1] &= ~(7 << 21);
1601 defId(pDef, 32 + 21);
1602 }
1603 }
1604
1605 void
1606 CodeEmitterNVC0::emitAFETCH(const Instruction *i)
1607 {
1608 code[0] = 0x00000006;
1609 code[1] = 0x0c000000 | (i->src(0).get()->reg.data.offset & 0x7ff);
1610
1611 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1612 code[0] |= 0x200;
1613
1614 emitPredicate(i);
1615
1616 defId(i->def(0), 14);
1617 srcId(i->src(0).getIndirect(0), 20);
1618 }
1619
1620 void
1621 CodeEmitterNVC0::emitPFETCH(const Instruction *i)
1622 {
1623 uint32_t prim = i->src(0).get()->reg.data.u32;
1624
1625 code[0] = 0x00000006 | ((prim & 0x3f) << 26);
1626 code[1] = 0x00000000 | (prim >> 6);
1627
1628 emitPredicate(i);
1629
1630 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2)
1631
1632 defId(i->def(0), 14);
1633 srcId(i, src1, 20);
1634 }
1635
1636 void
1637 CodeEmitterNVC0::emitVFETCH(const Instruction *i)
1638 {
1639 code[0] = 0x00000006;
1640 code[1] = 0x06000000 | i->src(0).get()->reg.data.offset;
1641
1642 if (i->perPatch)
1643 code[0] |= 0x100;
1644 if (i->getSrc(0)->reg.file == FILE_SHADER_OUTPUT)
1645 code[0] |= 0x200; // yes, TCPs can read from *outputs* of other threads
1646
1647 emitPredicate(i);
1648
1649 code[0] |= ((i->getDef(0)->reg.size / 4) - 1) << 5;
1650
1651 defId(i->def(0), 14);
1652 srcId(i->src(0).getIndirect(0), 20);
1653 srcId(i->src(0).getIndirect(1), 26); // vertex address
1654 }
1655
1656 void
1657 CodeEmitterNVC0::emitEXPORT(const Instruction *i)
1658 {
1659 unsigned int size = typeSizeof(i->dType);
1660
1661 code[0] = 0x00000006 | ((size / 4 - 1) << 5);
1662 code[1] = 0x0a000000 | i->src(0).get()->reg.data.offset;
1663
1664 assert(!(code[1] & ((size == 12) ? 15 : (size - 1))));
1665
1666 if (i->perPatch)
1667 code[0] |= 0x100;
1668
1669 emitPredicate(i);
1670
1671 assert(i->src(1).getFile() == FILE_GPR);
1672
1673 srcId(i->src(0).getIndirect(0), 20);
1674 srcId(i->src(0).getIndirect(1), 32 + 17); // vertex base address
1675 srcId(i->src(1), 26);
1676 }
1677
1678 void
1679 CodeEmitterNVC0::emitOUT(const Instruction *i)
1680 {
1681 code[0] = 0x00000006;
1682 code[1] = 0x1c000000;
1683
1684 emitPredicate(i);
1685
1686 defId(i->def(0), 14); // new secret address
1687 srcId(i->src(0), 20); // old secret address, should be 0 initially
1688
1689 assert(i->src(0).getFile() == FILE_GPR);
1690
1691 if (i->op == OP_EMIT)
1692 code[0] |= 1 << 5;
1693 if (i->op == OP_RESTART || i->subOp == NV50_IR_SUBOP_EMIT_RESTART)
1694 code[0] |= 1 << 6;
1695
1696 // vertex stream
1697 if (i->src(1).getFile() == FILE_IMMEDIATE) {
1698 unsigned int stream = SDATA(i->src(1)).u32;
1699 assert(stream < 4);
1700 if (stream) {
1701 code[1] |= 0xc000;
1702 code[0] |= stream << 26;
1703 } else {
1704 srcId(NULL, 26);
1705 }
1706 } else {
1707 srcId(i->src(1), 26);
1708 }
1709 }
1710
1711 void
1712 CodeEmitterNVC0::emitInterpMode(const Instruction *i)
1713 {
1714 if (i->encSize == 8) {
1715 code[0] |= i->ipa << 6; // TODO: INTERP_SAMPLEID
1716 } else {
1717 if (i->getInterpMode() == NV50_IR_INTERP_SC)
1718 code[0] |= 0x80;
1719 assert(i->op == OP_PINTERP && i->getSampleMode() == 0);
1720 }
1721 }
1722
1723 static void
1724 interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
1725 {
1726 int ipa = entry->ipa;
1727 int reg = entry->reg;
1728 int loc = entry->loc;
1729
1730 if (data.flatshade &&
1731 (ipa & NV50_IR_INTERP_MODE_MASK) == NV50_IR_INTERP_SC) {
1732 ipa = NV50_IR_INTERP_FLAT;
1733 reg = 0x3f;
1734 } else if (data.force_persample_interp &&
1735 (ipa & NV50_IR_INTERP_SAMPLE_MASK) == NV50_IR_INTERP_DEFAULT &&
1736 (ipa & NV50_IR_INTERP_MODE_MASK) != NV50_IR_INTERP_FLAT) {
1737 ipa |= NV50_IR_INTERP_CENTROID;
1738 }
1739 code[loc + 0] &= ~(0xf << 6);
1740 code[loc + 0] |= ipa << 6;
1741 code[loc + 0] &= ~(0x3f << 26);
1742 code[loc + 0] |= reg << 26;
1743 }
1744
1745 void
1746 CodeEmitterNVC0::emitINTERP(const Instruction *i)
1747 {
1748 const uint32_t base = i->getSrc(0)->reg.data.offset;
1749
1750 if (i->encSize == 8) {
1751 code[0] = 0x00000000;
1752 code[1] = 0xc0000000 | (base & 0xffff);
1753
1754 if (i->saturate)
1755 code[0] |= 1 << 5;
1756
1757 if (i->op == OP_PINTERP) {
1758 srcId(i->src(1), 26);
1759 addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
1760 } else {
1761 code[0] |= 0x3f << 26;
1762 addInterp(i->ipa, 0x3f, interpApply);
1763 }
1764
1765 srcId(i->src(0).getIndirect(0), 20);
1766 } else {
1767 assert(i->op == OP_PINTERP);
1768 code[0] = 0x00000009 | ((base & 0xc) << 6) | ((base >> 4) << 26);
1769 srcId(i->src(1), 20);
1770 }
1771 emitInterpMode(i);
1772
1773 emitPredicate(i);
1774 defId(i->def(0), 14);
1775
1776 if (i->getSampleMode() == NV50_IR_INTERP_OFFSET)
1777 srcId(i->src(i->op == OP_PINTERP ? 2 : 1), 32 + 17);
1778 else
1779 code[1] |= 0x3f << 17;
1780 }
1781
1782 void
1783 CodeEmitterNVC0::emitLoadStoreType(DataType ty)
1784 {
1785 uint8_t val;
1786
1787 switch (ty) {
1788 case TYPE_U8:
1789 val = 0x00;
1790 break;
1791 case TYPE_S8:
1792 val = 0x20;
1793 break;
1794 case TYPE_F16:
1795 case TYPE_U16:
1796 val = 0x40;
1797 break;
1798 case TYPE_S16:
1799 val = 0x60;
1800 break;
1801 case TYPE_F32:
1802 case TYPE_U32:
1803 case TYPE_S32:
1804 val = 0x80;
1805 break;
1806 case TYPE_F64:
1807 case TYPE_U64:
1808 case TYPE_S64:
1809 val = 0xa0;
1810 break;
1811 case TYPE_B128:
1812 val = 0xc0;
1813 break;
1814 default:
1815 val = 0x80;
1816 assert(!"invalid type");
1817 break;
1818 }
1819 code[0] |= val;
1820 }
1821
1822 void
1823 CodeEmitterNVC0::emitCachingMode(CacheMode c)
1824 {
1825 uint32_t val;
1826
1827 switch (c) {
1828 case CACHE_CA:
1829 // case CACHE_WB:
1830 val = 0x000;
1831 break;
1832 case CACHE_CG:
1833 val = 0x100;
1834 break;
1835 case CACHE_CS:
1836 val = 0x200;
1837 break;
1838 case CACHE_CV:
1839 // case CACHE_WT:
1840 val = 0x300;
1841 break;
1842 default:
1843 val = 0;
1844 assert(!"invalid caching mode");
1845 break;
1846 }
1847 code[0] |= val;
1848 }
1849
1850 static inline bool
1851 uses64bitAddress(const Instruction *ldst)
1852 {
1853 return ldst->src(0).getFile() == FILE_MEMORY_GLOBAL &&
1854 ldst->src(0).isIndirect(0) &&
1855 ldst->getIndirect(0, 0)->reg.size == 8;
1856 }
1857
1858 void
1859 CodeEmitterNVC0::emitSTORE(const Instruction *i)
1860 {
1861 uint32_t opc;
1862
1863 switch (i->src(0).getFile()) {
1864 case FILE_MEMORY_GLOBAL: opc = 0x90000000; break;
1865 case FILE_MEMORY_LOCAL: opc = 0xc8000000; break;
1866 case FILE_MEMORY_SHARED:
1867 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1868 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1869 opc = 0xb8000000;
1870 else
1871 opc = 0xcc000000;
1872 } else {
1873 opc = 0xc9000000;
1874 }
1875 break;
1876 default:
1877 assert(!"invalid memory file");
1878 opc = 0;
1879 break;
1880 }
1881 code[0] = 0x00000005;
1882 code[1] = opc;
1883
1884 if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
1885 // Unlocked store on shared memory can fail.
1886 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
1887 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
1888 assert(i->defExists(0));
1889 setPDSTL(i, 0);
1890 }
1891 }
1892
1893 setAddressByFile(i->src(0));
1894 srcId(i->src(1), 14);
1895 srcId(i->src(0).getIndirect(0), 20);
1896 if (uses64bitAddress(i))
1897 code[1] |= 1 << 26;
1898
1899 emitPredicate(i);
1900
1901 emitLoadStoreType(i->dType);
1902 emitCachingMode(i->cache);
1903 }
1904
1905 void
1906 CodeEmitterNVC0::emitLOAD(const Instruction *i)
1907 {
1908 uint32_t opc;
1909
1910 code[0] = 0x00000005;
1911
1912 switch (i->src(0).getFile()) {
1913 case FILE_MEMORY_GLOBAL: opc = 0x80000000; break;
1914 case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
1915 case FILE_MEMORY_SHARED:
1916 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1917 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1918 opc = 0xa8000000;
1919 else
1920 opc = 0xc4000000;
1921 } else {
1922 opc = 0xc1000000;
1923 }
1924 break;
1925 case FILE_MEMORY_CONST:
1926 if (!i->src(0).isIndirect(0) && typeSizeof(i->dType) == 4) {
1927 emitMOV(i); // not sure if this is any better
1928 return;
1929 }
1930 opc = 0x14000000 | (i->src(0).get()->reg.fileIndex << 10);
1931 code[0] = 0x00000006 | (i->subOp << 8);
1932 break;
1933 default:
1934 assert(!"invalid memory file");
1935 opc = 0;
1936 break;
1937 }
1938 code[1] = opc;
1939
1940 int r = 0, p = -1;
1941 if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
1942 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
1943 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
1944 r = -1;
1945 p = 0;
1946 } else if (i->defExists(1)) { // r, p
1947 p = 1;
1948 } else {
1949 assert(!"Expected predicate dest for load locked");
1950 }
1951 }
1952 }
1953
1954 if (r >= 0)
1955 defId(i->def(r), 14);
1956 else
1957 code[0] |= 63 << 14;
1958
1959 if (p >= 0) {
1960 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
1961 setPDSTL(i, p);
1962 else
1963 defId(i->def(p), 32 + 18);
1964 }
1965
1966 setAddressByFile(i->src(0));
1967 srcId(i->src(0).getIndirect(0), 20);
1968 if (uses64bitAddress(i))
1969 code[1] |= 1 << 26;
1970
1971 emitPredicate(i);
1972
1973 emitLoadStoreType(i->dType);
1974 emitCachingMode(i->cache);
1975 }
1976
1977 uint8_t
1978 CodeEmitterNVC0::getSRegEncoding(const ValueRef& ref)
1979 {
1980 switch (SDATA(ref).sv.sv) {
1981 case SV_LANEID: return 0x00;
1982 case SV_PHYSID: return 0x03;
1983 case SV_VERTEX_COUNT: return 0x10;
1984 case SV_INVOCATION_ID: return 0x11;
1985 case SV_YDIR: return 0x12;
1986 case SV_THREAD_KILL: return 0x13;
1987 case SV_TID: return 0x21 + SDATA(ref).sv.index;
1988 case SV_CTAID: return 0x25 + SDATA(ref).sv.index;
1989 case SV_NTID: return 0x29 + SDATA(ref).sv.index;
1990 case SV_GRIDID: return 0x2c;
1991 case SV_NCTAID: return 0x2d + SDATA(ref).sv.index;
1992 case SV_LBASE: return 0x34;
1993 case SV_SBASE: return 0x30;
1994 case SV_CLOCK: return 0x50 + SDATA(ref).sv.index;
1995 default:
1996 assert(!"no sreg for system value");
1997 return 0;
1998 }
1999 }
2000
2001 void
2002 CodeEmitterNVC0::emitMOV(const Instruction *i)
2003 {
2004 if (i->def(0).getFile() == FILE_PREDICATE) {
2005 if (i->src(0).getFile() == FILE_GPR) {
2006 code[0] = 0xfc01c003;
2007 code[1] = 0x1a8e0000;
2008 srcId(i->src(0), 20);
2009 } else {
2010 code[0] = 0x0001c004;
2011 code[1] = 0x0c0e0000;
2012 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2013 code[0] |= 7 << 20;
2014 if (!i->getSrc(0)->reg.data.u32)
2015 code[0] |= 1 << 23;
2016 } else {
2017 srcId(i->src(0), 20);
2018 }
2019 }
2020 defId(i->def(0), 17);
2021 emitPredicate(i);
2022 } else
2023 if (i->src(0).getFile() == FILE_SYSTEM_VALUE) {
2024 uint8_t sr = getSRegEncoding(i->src(0));
2025
2026 if (i->encSize == 8) {
2027 code[0] = 0x00000004 | (sr << 26);
2028 code[1] = 0x2c000000;
2029 } else {
2030 code[0] = 0x40000008 | (sr << 20);
2031 }
2032 defId(i->def(0), 14);
2033
2034 emitPredicate(i);
2035 } else
2036 if (i->encSize == 8) {
2037 uint64_t opc;
2038
2039 if (i->src(0).getFile() == FILE_IMMEDIATE)
2040 opc = HEX64(18000000, 000001e2);
2041 else
2042 if (i->src(0).getFile() == FILE_PREDICATE)
2043 opc = HEX64(080e0000, 1c000004);
2044 else
2045 opc = HEX64(28000000, 00000004);
2046
2047 if (i->src(0).getFile() != FILE_PREDICATE)
2048 opc |= i->lanes << 5;
2049
2050 emitForm_B(i, opc);
2051
2052 // Explicitly emit the predicate source as emitForm_B skips it.
2053 if (i->src(0).getFile() == FILE_PREDICATE)
2054 srcId(i->src(0), 20);
2055 } else {
2056 uint32_t imm;
2057
2058 if (i->src(0).getFile() == FILE_IMMEDIATE) {
2059 imm = SDATA(i->src(0)).u32;
2060 if (imm & 0xfff00000) {
2061 assert(!(imm & 0x000fffff));
2062 code[0] = 0x00000318 | imm;
2063 } else {
2064 assert(imm < 0x800 || ((int32_t)imm >= -0x800));
2065 code[0] = 0x00000118 | (imm << 20);
2066 }
2067 } else {
2068 code[0] = 0x0028;
2069 emitShortSrc2(i->src(0));
2070 }
2071 defId(i->def(0), 14);
2072
2073 emitPredicate(i);
2074 }
2075 }
2076
2077 void
2078 CodeEmitterNVC0::emitATOM(const Instruction *i)
2079 {
2080 const bool hasDst = i->defExists(0);
2081 const bool casOrExch =
2082 i->subOp == NV50_IR_SUBOP_ATOM_EXCH ||
2083 i->subOp == NV50_IR_SUBOP_ATOM_CAS;
2084
2085 if (i->dType == TYPE_U64) {
2086 switch (i->subOp) {
2087 case NV50_IR_SUBOP_ATOM_ADD:
2088 code[0] = 0x205;
2089 if (hasDst)
2090 code[1] = 0x507e0000;
2091 else
2092 code[1] = 0x10000000;
2093 break;
2094 case NV50_IR_SUBOP_ATOM_EXCH:
2095 code[0] = 0x305;
2096 code[1] = 0x507e0000;
2097 break;
2098 case NV50_IR_SUBOP_ATOM_CAS:
2099 code[0] = 0x325;
2100 code[1] = 0x50000000;
2101 break;
2102 default:
2103 assert(!"invalid u64 red op");
2104 break;
2105 }
2106 } else
2107 if (i->dType == TYPE_U32) {
2108 switch (i->subOp) {
2109 case NV50_IR_SUBOP_ATOM_EXCH:
2110 code[0] = 0x105;
2111 code[1] = 0x507e0000;
2112 break;
2113 case NV50_IR_SUBOP_ATOM_CAS:
2114 code[0] = 0x125;
2115 code[1] = 0x50000000;
2116 break;
2117 default:
2118 code[0] = 0x5 | (i->subOp << 5);
2119 if (hasDst)
2120 code[1] = 0x507e0000;
2121 else
2122 code[1] = 0x10000000;
2123 break;
2124 }
2125 } else
2126 if (i->dType == TYPE_S32) {
2127 assert(i->subOp <= 2);
2128 code[0] = 0x205 | (i->subOp << 5);
2129 if (hasDst)
2130 code[1] = 0x587e0000;
2131 else
2132 code[1] = 0x18000000;
2133 } else
2134 if (i->dType == TYPE_F32) {
2135 assert(i->subOp == NV50_IR_SUBOP_ATOM_ADD);
2136 code[0] = 0x205;
2137 if (hasDst)
2138 code[1] = 0x687e0000;
2139 else
2140 code[1] = 0x28000000;
2141 }
2142
2143 emitPredicate(i);
2144
2145 srcId(i->src(1), 14);
2146
2147 if (hasDst)
2148 defId(i->def(0), 32 + 11);
2149 else
2150 if (casOrExch)
2151 code[1] |= 63 << 11;
2152
2153 if (hasDst || casOrExch) {
2154 const int32_t offset = SDATA(i->src(0)).offset;
2155 assert(offset < 0x80000 && offset >= -0x80000);
2156 code[0] |= offset << 26;
2157 code[1] |= (offset & 0x1ffc0) >> 6;
2158 code[1] |= (offset & 0xe0000) << 6;
2159 } else {
2160 srcAddr32(i->src(0), 26, 0);
2161 }
2162 if (i->getIndirect(0, 0)) {
2163 srcId(i->getIndirect(0, 0), 20);
2164 if (i->getIndirect(0, 0)->reg.size == 8)
2165 code[1] |= 1 << 26;
2166 } else {
2167 code[0] |= 63 << 20;
2168 }
2169
2170 if (i->subOp == NV50_IR_SUBOP_ATOM_CAS) {
2171 assert(i->src(1).getSize() == 2 * typeSizeof(i->sType));
2172 code[1] |= (SDATA(i->src(1)).id + 1) << 17;
2173 }
2174 }
2175
2176 void
2177 CodeEmitterNVC0::emitMEMBAR(const Instruction *i)
2178 {
2179 switch (NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp)) {
2180 case NV50_IR_SUBOP_MEMBAR_CTA: code[0] = 0x05; break;
2181 case NV50_IR_SUBOP_MEMBAR_GL: code[0] = 0x25; break;
2182 default:
2183 code[0] = 0x45;
2184 assert(NV50_IR_SUBOP_MEMBAR_SCOPE(i->subOp) == NV50_IR_SUBOP_MEMBAR_SYS);
2185 break;
2186 }
2187 code[1] = 0xe0000000;
2188
2189 emitPredicate(i);
2190 }
2191
2192 void
2193 CodeEmitterNVC0::emitCCTL(const Instruction *i)
2194 {
2195 code[0] = 0x00000005 | (i->subOp << 5);
2196
2197 if (i->src(0).getFile() == FILE_MEMORY_GLOBAL) {
2198 code[1] = 0x98000000;
2199 srcAddr32(i->src(0), 28, 2);
2200 } else {
2201 code[1] = 0xd0000000;
2202 setAddress24(i->src(0));
2203 }
2204 if (uses64bitAddress(i))
2205 code[1] |= 1 << 26;
2206 srcId(i->src(0).getIndirect(0), 20);
2207
2208 emitPredicate(i);
2209
2210 defId(i, 0, 14);
2211 }
2212
2213 void
2214 CodeEmitterNVC0::emitSUCLAMPMode(uint16_t subOp)
2215 {
2216 uint8_t m;
2217 switch (subOp & ~NV50_IR_SUBOP_SUCLAMP_2D) {
2218 case NV50_IR_SUBOP_SUCLAMP_SD(0, 1): m = 0; break;
2219 case NV50_IR_SUBOP_SUCLAMP_SD(1, 1): m = 1; break;
2220 case NV50_IR_SUBOP_SUCLAMP_SD(2, 1): m = 2; break;
2221 case NV50_IR_SUBOP_SUCLAMP_SD(3, 1): m = 3; break;
2222 case NV50_IR_SUBOP_SUCLAMP_SD(4, 1): m = 4; break;
2223 case NV50_IR_SUBOP_SUCLAMP_PL(0, 1): m = 5; break;
2224 case NV50_IR_SUBOP_SUCLAMP_PL(1, 1): m = 6; break;
2225 case NV50_IR_SUBOP_SUCLAMP_PL(2, 1): m = 7; break;
2226 case NV50_IR_SUBOP_SUCLAMP_PL(3, 1): m = 8; break;
2227 case NV50_IR_SUBOP_SUCLAMP_PL(4, 1): m = 9; break;
2228 case NV50_IR_SUBOP_SUCLAMP_BL(0, 1): m = 10; break;
2229 case NV50_IR_SUBOP_SUCLAMP_BL(1, 1): m = 11; break;
2230 case NV50_IR_SUBOP_SUCLAMP_BL(2, 1): m = 12; break;
2231 case NV50_IR_SUBOP_SUCLAMP_BL(3, 1): m = 13; break;
2232 case NV50_IR_SUBOP_SUCLAMP_BL(4, 1): m = 14; break;
2233 default:
2234 return;
2235 }
2236 code[0] |= m << 5;
2237 if (subOp & NV50_IR_SUBOP_SUCLAMP_2D)
2238 code[1] |= 1 << 16;
2239 }
2240
2241 void
2242 CodeEmitterNVC0::emitSUCalc(Instruction *i)
2243 {
2244 ImmediateValue *imm = NULL;
2245 uint64_t opc;
2246
2247 if (i->srcExists(2)) {
2248 imm = i->getSrc(2)->asImm();
2249 if (imm)
2250 i->setSrc(2, NULL); // special case, make emitForm_A not assert
2251 }
2252
2253 switch (i->op) {
2254 case OP_SUCLAMP: opc = HEX64(58000000, 00000004); break;
2255 case OP_SUBFM: opc = HEX64(5c000000, 00000004); break;
2256 case OP_SUEAU: opc = HEX64(60000000, 00000004); break;
2257 default:
2258 assert(0);
2259 return;
2260 }
2261 emitForm_A(i, opc);
2262
2263 if (i->op == OP_SUCLAMP) {
2264 if (i->dType == TYPE_S32)
2265 code[0] |= 1 << 9;
2266 emitSUCLAMPMode(i->subOp);
2267 }
2268
2269 if (i->op == OP_SUBFM && i->subOp == NV50_IR_SUBOP_SUBFM_3D)
2270 code[1] |= 1 << 16;
2271
2272 if (i->op != OP_SUEAU) {
2273 if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
2274 code[0] |= 63 << 14;
2275 code[1] |= i->getDef(0)->reg.data.id << 23;
2276 } else
2277 if (i->defExists(1)) { // r, p
2278 assert(i->def(1).getFile() == FILE_PREDICATE);
2279 code[1] |= i->getDef(1)->reg.data.id << 23;
2280 } else { // r, #
2281 code[1] |= 7 << 23;
2282 }
2283 }
2284 if (imm) {
2285 assert(i->op == OP_SUCLAMP);
2286 i->setSrc(2, imm);
2287 code[1] |= (imm->reg.data.u32 & 0x3f) << 17; // sint6
2288 }
2289 }
2290
2291 void
2292 CodeEmitterNVC0::emitSUGType(DataType ty)
2293 {
2294 switch (ty) {
2295 case TYPE_S32: code[1] |= 1 << 13; break;
2296 case TYPE_U8: code[1] |= 2 << 13; break;
2297 case TYPE_S8: code[1] |= 3 << 13; break;
2298 default:
2299 assert(ty == TYPE_U32);
2300 break;
2301 }
2302 }
2303
2304 void
2305 CodeEmitterNVC0::setSUConst16(const Instruction *i, const int s)
2306 {
2307 const uint32_t offset = i->getSrc(s)->reg.data.offset;
2308
2309 assert(i->src(s).getFile() == FILE_MEMORY_CONST);
2310 assert(offset == (offset & 0xfffc));
2311
2312 code[1] |= 1 << 21;
2313 code[0] |= offset << 24;
2314 code[1] |= offset >> 8;
2315 code[1] |= i->getSrc(s)->reg.fileIndex << 8;
2316 }
2317
2318 void
2319 CodeEmitterNVC0::setSUPred(const Instruction *i, const int s)
2320 {
2321 if (!i->srcExists(s) || (i->predSrc == s)) {
2322 code[1] |= 0x7 << 17;
2323 } else {
2324 if (i->src(s).mod == Modifier(NV50_IR_MOD_NOT))
2325 code[1] |= 1 << 20;
2326 srcId(i->src(s), 32 + 17);
2327 }
2328 }
2329
2330 void
2331 CodeEmitterNVC0::emitSULDGB(const TexInstruction *i)
2332 {
2333 code[0] = 0x5;
2334 code[1] = 0xd4000000 | (i->subOp << 15);
2335
2336 emitLoadStoreType(i->dType);
2337 emitSUGType(i->sType);
2338 emitCachingMode(i->cache);
2339
2340 emitPredicate(i);
2341 defId(i->def(0), 14); // destination
2342 srcId(i->src(0), 20); // address
2343 // format
2344 if (i->src(1).getFile() == FILE_GPR)
2345 srcId(i->src(1), 26);
2346 else
2347 setSUConst16(i, 1);
2348 setSUPred(i, 2);
2349 }
2350
2351 void
2352 CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
2353 {
2354 code[0] = 0x5;
2355 code[1] = 0xdc000000 | (i->subOp << 15);
2356
2357 if (i->op == OP_SUSTP)
2358 code[1] |= i->tex.mask << 22;
2359 else
2360 emitLoadStoreType(i->dType);
2361 emitSUGType(i->sType);
2362 emitCachingMode(i->cache);
2363
2364 emitPredicate(i);
2365 srcId(i->src(0), 20); // address
2366 // format
2367 if (i->src(1).getFile() == FILE_GPR)
2368 srcId(i->src(1), 26);
2369 else
2370 setSUConst16(i, 1);
2371 srcId(i->src(3), 14); // values
2372 setSUPred(i, 2);
2373 }
2374
2375 void
2376 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
2377 {
2378 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2379
2380 if (i->tex.rIndirectSrc < 0) {
2381 code[1] |= 0x00004000;
2382 code[0] |= i->tex.r << 26;
2383 } else {
2384 srcId(i, i->tex.rIndirectSrc, 26);
2385 }
2386 }
2387
2388 void
2389 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
2390 {
2391 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2392
2393 code[1] |= (i->tex.target.getDim() - 1) << 12;
2394 if (i->tex.target.isArray() || i->tex.target.isCube() ||
2395 i->tex.target.getDim() == 3) {
2396 // use e2d mode for 3-dim images, arrays and cubes.
2397 code[1] |= 3 << 12;
2398 }
2399
2400 srcId(i->src(0), 20);
2401 }
2402
2403 void
2404 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
2405 {
2406 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2407
2408 code[0] = 0x5;
2409 code[1] = 0xf0000000;
2410
2411 emitPredicate(i);
2412 emitLoadStoreType(i->sType);
2413
2414 defId(i->def(0), 14);
2415
2416 if (i->defExists(1)) {
2417 defId(i->def(1), 32 + 22);
2418 } else {
2419 code[1] |= 7 << 22;
2420 }
2421
2422 emitSUAddr(i);
2423 emitSUDim(i);
2424 }
2425
2426 void
2427 CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
2428 {
2429 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2430
2431 code[0] = 0x5;
2432 code[1] = 0xd4000000 | (i->subOp << 15);
2433
2434 emitPredicate(i);
2435 emitLoadStoreType(i->dType);
2436
2437 defId(i->def(0), 14);
2438
2439 emitCachingMode(i->cache);
2440 emitSUAddr(i);
2441 emitSUDim(i);
2442 }
2443
2444 void
2445 CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
2446 {
2447 assert(targ->getChipset() < NVISA_GK104_CHIPSET);
2448
2449 code[0] = 0x5;
2450 code[1] = 0xdc000000 | (i->subOp << 15);
2451
2452 if (i->op == OP_SUSTP)
2453 code[1] |= i->tex.mask << 17;
2454 else
2455 emitLoadStoreType(i->dType);
2456
2457 emitPredicate(i);
2458
2459 srcId(i->src(1), 14);
2460
2461 emitCachingMode(i->cache);
2462 emitSUAddr(i);
2463 emitSUDim(i);
2464 }
2465
2466 void
2467 CodeEmitterNVC0::emitVectorSubOp(const Instruction *i)
2468 {
2469 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2470 case 0:
2471 code[1] |= (i->subOp & 0x000f) << 12; // vsrc1
2472 code[1] |= (i->subOp & 0x00e0) >> 5; // vsrc2
2473 code[1] |= (i->subOp & 0x0100) << 7; // vsrc2
2474 code[1] |= (i->subOp & 0x3c00) << 13; // vdst
2475 break;
2476 case 1:
2477 code[1] |= (i->subOp & 0x000f) << 8; // v2src1
2478 code[1] |= (i->subOp & 0x0010) << 11; // v2src1
2479 code[1] |= (i->subOp & 0x01e0) >> 1; // v2src2
2480 code[1] |= (i->subOp & 0x0200) << 6; // v2src2
2481 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2482 code[1] |= (i->mask & 0x3) << 2;
2483 break;
2484 case 2:
2485 code[1] |= (i->subOp & 0x000f) << 8; // v4src1
2486 code[1] |= (i->subOp & 0x01e0) >> 1; // v4src2
2487 code[1] |= (i->subOp & 0x3c00) << 2; // v4dst
2488 code[1] |= (i->mask & 0x3) << 2;
2489 code[1] |= (i->mask & 0xc) << 21;
2490 break;
2491 default:
2492 assert(0);
2493 break;
2494 }
2495 }
2496
2497 void
2498 CodeEmitterNVC0::emitVSHL(const Instruction *i)
2499 {
2500 uint64_t opc = 0x4;
2501
2502 switch (NV50_IR_SUBOP_Vn(i->subOp)) {
2503 case 0: opc |= 0xe8ULL << 56; break;
2504 case 1: opc |= 0xb4ULL << 56; break;
2505 case 2: opc |= 0x94ULL << 56; break;
2506 default:
2507 assert(0);
2508 break;
2509 }
2510 if (NV50_IR_SUBOP_Vn(i->subOp) == 1) {
2511 if (isSignedType(i->dType)) opc |= 1ULL << 0x2a;
2512 if (isSignedType(i->sType)) opc |= (1 << 6) | (1 << 5);
2513 } else {
2514 if (isSignedType(i->dType)) opc |= 1ULL << 0x39;
2515 if (isSignedType(i->sType)) opc |= 1 << 6;
2516 }
2517 emitForm_A(i, opc);
2518 emitVectorSubOp(i);
2519
2520 if (i->saturate)
2521 code[0] |= 1 << 9;
2522 if (i->flagsDef >= 0)
2523 code[1] |= 1 << 16;
2524 }
2525
2526 void
2527 CodeEmitterNVC0::emitPIXLD(const Instruction *i)
2528 {
2529 assert(i->encSize == 8);
2530 emitForm_A(i, HEX64(10000000, 00000006));
2531 code[0] |= i->subOp << 5;
2532 code[1] |= 0x00e00000;
2533 }
2534
2535 void
2536 CodeEmitterNVC0::emitSHFL(const Instruction *i)
2537 {
2538 const ImmediateValue *imm;
2539
2540 assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
2541
2542 code[0] = 0x00000005;
2543 code[1] = 0x88000000 | (i->subOp << 23);
2544
2545 emitPredicate(i);
2546
2547 defId(i->def(0), 14);
2548 srcId(i->src(0), 20);
2549
2550 switch (i->src(1).getFile()) {
2551 case FILE_GPR:
2552 srcId(i->src(1), 26);
2553 break;
2554 case FILE_IMMEDIATE:
2555 imm = i->getSrc(1)->asImm();
2556 assert(imm && imm->reg.data.u32 < 0x20);
2557 code[0] |= imm->reg.data.u32 << 26;
2558 code[0] |= 1 << 5;
2559 break;
2560 default:
2561 assert(!"invalid src1 file");
2562 break;
2563 }
2564
2565 switch (i->src(2).getFile()) {
2566 case FILE_GPR:
2567 srcId(i->src(2), 49);
2568 break;
2569 case FILE_IMMEDIATE:
2570 imm = i->getSrc(2)->asImm();
2571 assert(imm && imm->reg.data.u32 < 0x2000);
2572 code[1] |= imm->reg.data.u32 << 10;
2573 code[0] |= 1 << 6;
2574 break;
2575 default:
2576 assert(!"invalid src2 file");
2577 break;
2578 }
2579
2580 setPDSTL(i, i->defExists(1) ? 1 : -1);
2581 }
2582
2583 void
2584 CodeEmitterNVC0::emitVOTE(const Instruction *i)
2585 {
2586 assert(i->src(0).getFile() == FILE_PREDICATE);
2587
2588 code[0] = 0x00000004 | (i->subOp << 5);
2589 code[1] = 0x48000000;
2590
2591 emitPredicate(i);
2592
2593 unsigned rp = 0;
2594 for (int d = 0; i->defExists(d); d++) {
2595 if (i->def(d).getFile() == FILE_PREDICATE) {
2596 assert(!(rp & 2));
2597 rp |= 2;
2598 defId(i->def(d), 32 + 22);
2599 } else if (i->def(d).getFile() == FILE_GPR) {
2600 assert(!(rp & 1));
2601 rp |= 1;
2602 defId(i->def(d), 14);
2603 } else {
2604 assert(!"Unhandled def");
2605 }
2606 }
2607 if (!(rp & 1))
2608 code[0] |= 63 << 14;
2609 if (!(rp & 2))
2610 code[1] |= 7 << 22;
2611 if (i->src(0).mod == Modifier(NV50_IR_MOD_NOT))
2612 code[0] |= 1 << 23;
2613 srcId(i->src(0), 20);
2614 }
2615
2616 bool
2617 CodeEmitterNVC0::emitInstruction(Instruction *insn)
2618 {
2619 unsigned int size = insn->encSize;
2620
2621 if (writeIssueDelays && !(codeSize & 0x3f))
2622 size += 8;
2623
2624 if (!insn->encSize) {
2625 ERROR("skipping unencodable instruction: "); insn->print();
2626 return false;
2627 } else
2628 if (codeSize + size > codeSizeLimit) {
2629 ERROR("code emitter output buffer too small\n");
2630 return false;
2631 }
2632
2633 if (writeIssueDelays) {
2634 if (!(codeSize & 0x3f)) {
2635 code[0] = 0x00000007; // cf issue delay "instruction"
2636 code[1] = 0x20000000;
2637 code += 2;
2638 codeSize += 8;
2639 }
2640 const unsigned int id = (codeSize & 0x3f) / 8 - 1;
2641 uint32_t *data = code - (id * 2 + 2);
2642 if (id <= 2) {
2643 data[0] |= insn->sched << (id * 8 + 4);
2644 } else
2645 if (id == 3) {
2646 data[0] |= insn->sched << 28;
2647 data[1] |= insn->sched >> 4;
2648 } else {
2649 data[1] |= insn->sched << ((id - 4) * 8 + 4);
2650 }
2651 }
2652
2653 // assert that instructions with multiple defs don't corrupt registers
2654 for (int d = 0; insn->defExists(d); ++d)
2655 assert(insn->asTex() || insn->def(d).rep()->reg.data.id >= 0);
2656
2657 switch (insn->op) {
2658 case OP_MOV:
2659 case OP_RDSV:
2660 emitMOV(insn);
2661 break;
2662 case OP_NOP:
2663 break;
2664 case OP_LOAD:
2665 emitLOAD(insn);
2666 break;
2667 case OP_STORE:
2668 emitSTORE(insn);
2669 break;
2670 case OP_LINTERP:
2671 case OP_PINTERP:
2672 emitINTERP(insn);
2673 break;
2674 case OP_VFETCH:
2675 emitVFETCH(insn);
2676 break;
2677 case OP_EXPORT:
2678 emitEXPORT(insn);
2679 break;
2680 case OP_PFETCH:
2681 emitPFETCH(insn);
2682 break;
2683 case OP_AFETCH:
2684 emitAFETCH(insn);
2685 break;
2686 case OP_EMIT:
2687 case OP_RESTART:
2688 emitOUT(insn);
2689 break;
2690 case OP_ADD:
2691 case OP_SUB:
2692 if (insn->dType == TYPE_F64)
2693 emitDADD(insn);
2694 else if (isFloatType(insn->dType))
2695 emitFADD(insn);
2696 else
2697 emitUADD(insn);
2698 break;
2699 case OP_MUL:
2700 if (insn->dType == TYPE_F64)
2701 emitDMUL(insn);
2702 else if (isFloatType(insn->dType))
2703 emitFMUL(insn);
2704 else
2705 emitUMUL(insn);
2706 break;
2707 case OP_MAD:
2708 case OP_FMA:
2709 if (insn->dType == TYPE_F64)
2710 emitDMAD(insn);
2711 else if (isFloatType(insn->dType))
2712 emitFMAD(insn);
2713 else
2714 emitIMAD(insn);
2715 break;
2716 case OP_SAD:
2717 emitISAD(insn);
2718 break;
2719 case OP_SHLADD:
2720 emitSHLADD(insn);
2721 break;
2722 case OP_NOT:
2723 emitNOT(insn);
2724 break;
2725 case OP_AND:
2726 emitLogicOp(insn, 0);
2727 break;
2728 case OP_OR:
2729 emitLogicOp(insn, 1);
2730 break;
2731 case OP_XOR:
2732 emitLogicOp(insn, 2);
2733 break;
2734 case OP_SHL:
2735 case OP_SHR:
2736 emitShift(insn);
2737 break;
2738 case OP_SET:
2739 case OP_SET_AND:
2740 case OP_SET_OR:
2741 case OP_SET_XOR:
2742 emitSET(insn->asCmp());
2743 break;
2744 case OP_SELP:
2745 emitSELP(insn);
2746 break;
2747 case OP_SLCT:
2748 emitSLCT(insn->asCmp());
2749 break;
2750 case OP_MIN:
2751 case OP_MAX:
2752 emitMINMAX(insn);
2753 break;
2754 case OP_ABS:
2755 case OP_NEG:
2756 case OP_CEIL:
2757 case OP_FLOOR:
2758 case OP_TRUNC:
2759 case OP_SAT:
2760 emitCVT(insn);
2761 break;
2762 case OP_CVT:
2763 if (insn->def(0).getFile() == FILE_PREDICATE ||
2764 insn->src(0).getFile() == FILE_PREDICATE)
2765 emitMOV(insn);
2766 else
2767 emitCVT(insn);
2768 break;
2769 case OP_RSQ:
2770 emitSFnOp(insn, 5 + 2 * insn->subOp);
2771 break;
2772 case OP_RCP:
2773 emitSFnOp(insn, 4 + 2 * insn->subOp);
2774 break;
2775 case OP_LG2:
2776 emitSFnOp(insn, 3);
2777 break;
2778 case OP_EX2:
2779 emitSFnOp(insn, 2);
2780 break;
2781 case OP_SIN:
2782 emitSFnOp(insn, 1);
2783 break;
2784 case OP_COS:
2785 emitSFnOp(insn, 0);
2786 break;
2787 case OP_PRESIN:
2788 case OP_PREEX2:
2789 emitPreOp(insn);
2790 break;
2791 case OP_TEX:
2792 case OP_TXB:
2793 case OP_TXL:
2794 case OP_TXD:
2795 case OP_TXF:
2796 case OP_TXG:
2797 case OP_TXLQ:
2798 emitTEX(insn->asTex());
2799 break;
2800 case OP_TXQ:
2801 emitTXQ(insn->asTex());
2802 break;
2803 case OP_TEXBAR:
2804 emitTEXBAR(insn);
2805 break;
2806 case OP_SUBFM:
2807 case OP_SUCLAMP:
2808 case OP_SUEAU:
2809 emitSUCalc(insn);
2810 break;
2811 case OP_MADSP:
2812 emitMADSP(insn);
2813 break;
2814 case OP_SULDB:
2815 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2816 emitSULDGB(insn->asTex());
2817 else
2818 emitSULDB(insn->asTex());
2819 break;
2820 case OP_SUSTB:
2821 case OP_SUSTP:
2822 if (targ->getChipset() >= NVISA_GK104_CHIPSET)
2823 emitSUSTGx(insn->asTex());
2824 else
2825 emitSUSTx(insn->asTex());
2826 break;
2827 case OP_SULEA:
2828 emitSULEA(insn->asTex());
2829 break;
2830 case OP_ATOM:
2831 emitATOM(insn);
2832 break;
2833 case OP_BRA:
2834 case OP_CALL:
2835 case OP_PRERET:
2836 case OP_RET:
2837 case OP_DISCARD:
2838 case OP_EXIT:
2839 case OP_PRECONT:
2840 case OP_CONT:
2841 case OP_PREBREAK:
2842 case OP_BREAK:
2843 case OP_JOINAT:
2844 case OP_BRKPT:
2845 case OP_QUADON:
2846 case OP_QUADPOP:
2847 emitFlow(insn);
2848 break;
2849 case OP_QUADOP:
2850 emitQUADOP(insn, insn->subOp, insn->lanes);
2851 break;
2852 case OP_DFDX:
2853 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x66 : 0x99, 0x4);
2854 break;
2855 case OP_DFDY:
2856 emitQUADOP(insn, insn->src(0).mod.neg() ? 0x5a : 0xa5, 0x5);
2857 break;
2858 case OP_POPCNT:
2859 emitPOPC(insn);
2860 break;
2861 case OP_INSBF:
2862 emitINSBF(insn);
2863 break;
2864 case OP_EXTBF:
2865 emitEXTBF(insn);
2866 break;
2867 case OP_BFIND:
2868 emitBFIND(insn);
2869 break;
2870 case OP_PERMT:
2871 emitPERMT(insn);
2872 break;
2873 case OP_JOIN:
2874 emitNOP(insn);
2875 insn->join = 1;
2876 break;
2877 case OP_BAR:
2878 emitBAR(insn);
2879 break;
2880 case OP_MEMBAR:
2881 emitMEMBAR(insn);
2882 break;
2883 case OP_CCTL:
2884 emitCCTL(insn);
2885 break;
2886 case OP_VSHL:
2887 emitVSHL(insn);
2888 break;
2889 case OP_PIXLD:
2890 emitPIXLD(insn);
2891 break;
2892 case OP_SHFL:
2893 emitSHFL(insn);
2894 break;
2895 case OP_VOTE:
2896 emitVOTE(insn);
2897 break;
2898 case OP_PHI:
2899 case OP_UNION:
2900 case OP_CONSTRAINT:
2901 ERROR("operation should have been eliminated");
2902 return false;
2903 case OP_EXP:
2904 case OP_LOG:
2905 case OP_SQRT:
2906 case OP_POW:
2907 ERROR("operation should have been lowered\n");
2908 return false;
2909 default:
2910 ERROR("unknown op: %u\n", insn->op);
2911 return false;
2912 }
2913
2914 if (insn->join) {
2915 code[0] |= 0x10;
2916 assert(insn->encSize == 8);
2917 }
2918
2919 code += insn->encSize / 4;
2920 codeSize += insn->encSize;
2921 return true;
2922 }
2923
2924 uint32_t
2925 CodeEmitterNVC0::getMinEncodingSize(const Instruction *i) const
2926 {
2927 const Target::OpInfo &info = targ->getOpInfo(i);
2928
2929 if (writeIssueDelays || info.minEncSize == 8 || 1)
2930 return 8;
2931
2932 if (i->ftz || i->saturate || i->join)
2933 return 8;
2934 if (i->rnd != ROUND_N)
2935 return 8;
2936 if (i->predSrc >= 0 && i->op == OP_MAD)
2937 return 8;
2938
2939 if (i->op == OP_PINTERP) {
2940 if (i->getSampleMode() || 1) // XXX: grr, short op doesn't work
2941 return 8;
2942 } else
2943 if (i->op == OP_MOV && i->lanes != 0xf) {
2944 return 8;
2945 }
2946
2947 for (int s = 0; i->srcExists(s); ++s) {
2948 if (i->src(s).isIndirect(0))
2949 return 8;
2950
2951 if (i->src(s).getFile() == FILE_MEMORY_CONST) {
2952 if (SDATA(i->src(s)).offset >= 0x100)
2953 return 8;
2954 if (i->getSrc(s)->reg.fileIndex > 1 &&
2955 i->getSrc(s)->reg.fileIndex != 16)
2956 return 8;
2957 } else
2958 if (i->src(s).getFile() == FILE_IMMEDIATE) {
2959 if (i->dType == TYPE_F32) {
2960 if (SDATA(i->src(s)).u32 >= 0x100)
2961 return 8;
2962 } else {
2963 if (SDATA(i->src(s)).u32 > 0xff)
2964 return 8;
2965 }
2966 }
2967
2968 if (i->op == OP_CVT)
2969 continue;
2970 if (i->src(s).mod != Modifier(0)) {
2971 if (i->src(s).mod == Modifier(NV50_IR_MOD_ABS))
2972 if (i->op != OP_RSQ)
2973 return 8;
2974 if (i->src(s).mod == Modifier(NV50_IR_MOD_NEG))
2975 if (i->op != OP_ADD || s != 0)
2976 return 8;
2977 }
2978 }
2979
2980 return 4;
2981 }
2982
2983 // Simplified, erring on safe side.
2984 class SchedDataCalculator : public Pass
2985 {
2986 public:
2987 SchedDataCalculator(const Target *targ) : targ(targ) { }
2988
2989 private:
2990 struct RegScores
2991 {
2992 struct Resource {
2993 int st[DATA_FILE_COUNT]; // LD to LD delay 3
2994 int ld[DATA_FILE_COUNT]; // ST to ST delay 3
2995 int tex; // TEX to non-TEX delay 17 (0x11)
2996 int sfu; // SFU to SFU delay 3 (except PRE-ops)
2997 int imul; // integer MUL to MUL delay 3
2998 } res;
2999 struct ScoreData {
3000 int r[256];
3001 int p[8];
3002 int c;
3003 } rd, wr;
3004 int base;
3005 int regs;
3006
3007 void rebase(const int base)
3008 {
3009 const int delta = this->base - base;
3010 if (!delta)
3011 return;
3012 this->base = 0;
3013
3014 for (int i = 0; i < regs; ++i) {
3015 rd.r[i] += delta;
3016 wr.r[i] += delta;
3017 }
3018 for (int i = 0; i < 8; ++i) {
3019 rd.p[i] += delta;
3020 wr.p[i] += delta;
3021 }
3022 rd.c += delta;
3023 wr.c += delta;
3024
3025 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3026 res.ld[f] += delta;
3027 res.st[f] += delta;
3028 }
3029 res.sfu += delta;
3030 res.imul += delta;
3031 res.tex += delta;
3032 }
3033 void wipe(int regs)
3034 {
3035 memset(&rd, 0, sizeof(rd));
3036 memset(&wr, 0, sizeof(wr));
3037 memset(&res, 0, sizeof(res));
3038 this->regs = regs;
3039 }
3040 int getLatest(const ScoreData& d) const
3041 {
3042 int max = 0;
3043 for (int i = 0; i < regs; ++i)
3044 if (d.r[i] > max)
3045 max = d.r[i];
3046 for (int i = 0; i < 8; ++i)
3047 if (d.p[i] > max)
3048 max = d.p[i];
3049 if (d.c > max)
3050 max = d.c;
3051 return max;
3052 }
3053 inline int getLatestRd() const
3054 {
3055 return getLatest(rd);
3056 }
3057 inline int getLatestWr() const
3058 {
3059 return getLatest(wr);
3060 }
3061 inline int getLatest() const
3062 {
3063 const int a = getLatestRd();
3064 const int b = getLatestWr();
3065
3066 int max = MAX2(a, b);
3067 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3068 max = MAX2(res.ld[f], max);
3069 max = MAX2(res.st[f], max);
3070 }
3071 max = MAX2(res.sfu, max);
3072 max = MAX2(res.imul, max);
3073 max = MAX2(res.tex, max);
3074 return max;
3075 }
3076 void setMax(const RegScores *that)
3077 {
3078 for (int i = 0; i < regs; ++i) {
3079 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
3080 wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
3081 }
3082 for (int i = 0; i < 8; ++i) {
3083 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]);
3084 wr.p[i] = MAX2(wr.p[i], that->wr.p[i]);
3085 }
3086 rd.c = MAX2(rd.c, that->rd.c);
3087 wr.c = MAX2(wr.c, that->wr.c);
3088
3089 for (unsigned int f = 0; f < DATA_FILE_COUNT; ++f) {
3090 res.ld[f] = MAX2(res.ld[f], that->res.ld[f]);
3091 res.st[f] = MAX2(res.st[f], that->res.st[f]);
3092 }
3093 res.sfu = MAX2(res.sfu, that->res.sfu);
3094 res.imul = MAX2(res.imul, that->res.imul);
3095 res.tex = MAX2(res.tex, that->res.tex);
3096 }
3097 void print(int cycle)
3098 {
3099 for (int i = 0; i < regs; ++i) {
3100 if (rd.r[i] > cycle)
3101 INFO("rd $r%i @ %i\n", i, rd.r[i]);
3102 if (wr.r[i] > cycle)
3103 INFO("wr $r%i @ %i\n", i, wr.r[i]);
3104 }
3105 for (int i = 0; i < 8; ++i) {
3106 if (rd.p[i] > cycle)
3107 INFO("rd $p%i @ %i\n", i, rd.p[i]);
3108 if (wr.p[i] > cycle)
3109 INFO("wr $p%i @ %i\n", i, wr.p[i]);
3110 }
3111 if (rd.c > cycle)
3112 INFO("rd $c @ %i\n", rd.c);
3113 if (wr.c > cycle)
3114 INFO("wr $c @ %i\n", wr.c);
3115 if (res.sfu > cycle)
3116 INFO("sfu @ %i\n", res.sfu);
3117 if (res.imul > cycle)
3118 INFO("imul @ %i\n", res.imul);
3119 if (res.tex > cycle)
3120 INFO("tex @ %i\n", res.tex);
3121 }
3122 };
3123
3124 RegScores *score; // for current BB
3125 std::vector<RegScores> scoreBoards;
3126 int prevData;
3127 operation prevOp;
3128
3129 const Target *targ;
3130
3131 bool visit(Function *);
3132 bool visit(BasicBlock *);
3133
3134 void commitInsn(const Instruction *, int cycle);
3135 int calcDelay(const Instruction *, int cycle) const;
3136 void setDelay(Instruction *, int delay, Instruction *next);
3137
3138 void recordRd(const Value *, const int ready);
3139 void recordWr(const Value *, const int ready);
3140 void checkRd(const Value *, int cycle, int& delay) const;
3141 void checkWr(const Value *, int cycle, int& delay) const;
3142
3143 int getCycles(const Instruction *, int origDelay) const;
3144 };
3145
3146 void
3147 SchedDataCalculator::setDelay(Instruction *insn, int delay, Instruction *next)
3148 {
3149 if (insn->op == OP_EXIT || insn->op == OP_RET)
3150 delay = MAX2(delay, 14);
3151
3152 if (insn->op == OP_TEXBAR) {
3153 // TODO: except if results not used before EXIT
3154 insn->sched = 0xc2;
3155 } else
3156 if (insn->op == OP_JOIN || insn->join) {
3157 insn->sched = 0x00;
3158 } else
3159 if (delay >= 0 || prevData == 0x04 ||
3160 !next || !targ->canDualIssue(insn, next)) {
3161 insn->sched = static_cast<uint8_t>(MAX2(delay, 0));
3162 if (prevOp == OP_EXPORT)
3163 insn->sched |= 0x40;
3164 else
3165 insn->sched |= 0x20;
3166 } else {
3167 insn->sched = 0x04; // dual-issue
3168 }
3169
3170 if (prevData != 0x04 || prevOp != OP_EXPORT)
3171 if (insn->sched != 0x04 || insn->op == OP_EXPORT)
3172 prevOp = insn->op;
3173
3174 prevData = insn->sched;
3175 }
3176
3177 int
3178 SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
3179 {
3180 if (insn->sched & 0x80) {
3181 int c = (insn->sched & 0x0f) * 2 + 1;
3182 if (insn->op == OP_TEXBAR && origDelay > 0)
3183 c += origDelay;
3184 return c;
3185 }
3186 if (insn->sched & 0x60)
3187 return (insn->sched & 0x1f) + 1;
3188 return (insn->sched == 0x04) ? 0 : 32;
3189 }
3190
3191 bool
3192 SchedDataCalculator::visit(Function *func)
3193 {
3194 int regs = targ->getFileSize(FILE_GPR) + 1;
3195 scoreBoards.resize(func->cfg.getSize());
3196 for (size_t i = 0; i < scoreBoards.size(); ++i)
3197 scoreBoards[i].wipe(regs);
3198 return true;
3199 }
3200
3201 bool
3202 SchedDataCalculator::visit(BasicBlock *bb)
3203 {
3204 Instruction *insn;
3205 Instruction *next = NULL;
3206
3207 int cycle = 0;
3208
3209 prevData = 0x00;
3210 prevOp = OP_NOP;
3211 score = &scoreBoards.at(bb->getId());
3212
3213 for (Graph::EdgeIterator ei = bb->cfg.incident(); !ei.end(); ei.next()) {
3214 // back branches will wait until all target dependencies are satisfied
3215 if (ei.getType() == Graph::Edge::BACK) // sched would be uninitialized
3216 continue;
3217 BasicBlock *in = BasicBlock::get(ei.getNode());
3218 if (in->getExit()) {
3219 if (prevData != 0x04)
3220 prevData = in->getExit()->sched;
3221 prevOp = in->getExit()->op;
3222 }
3223 score->setMax(&scoreBoards.at(in->getId()));
3224 }
3225 if (bb->cfg.incidentCount() > 1)
3226 prevOp = OP_NOP;
3227
3228 #ifdef NVC0_DEBUG_SCHED_DATA
3229 INFO("=== BB:%i initial scores\n", bb->getId());
3230 score->print(cycle);
3231 #endif
3232
3233 for (insn = bb->getEntry(); insn && insn->next; insn = insn->next) {
3234 next = insn->next;
3235
3236 commitInsn(insn, cycle);
3237 int delay = calcDelay(next, cycle);
3238 setDelay(insn, delay, next);
3239 cycle += getCycles(insn, delay);
3240
3241 #ifdef NVC0_DEBUG_SCHED_DATA
3242 INFO("cycle %i, sched %02x\n", cycle, insn->sched);
3243 insn->print();
3244 next->print();
3245 #endif
3246 }
3247 if (!insn)
3248 return true;
3249 commitInsn(insn, cycle);
3250
3251 int bbDelay = -1;
3252
3253 for (Graph::EdgeIterator ei = bb->cfg.outgoing(); !ei.end(); ei.next()) {
3254 BasicBlock *out = BasicBlock::get(ei.getNode());
3255
3256 if (ei.getType() != Graph::Edge::BACK) {
3257 // only test the first instruction of the outgoing block
3258 next = out->getEntry();
3259 if (next)
3260 bbDelay = MAX2(bbDelay, calcDelay(next, cycle));
3261 } else {
3262 // wait until all dependencies are satisfied
3263 const int regsFree = score->getLatest();
3264 next = out->getFirst();
3265 for (int c = cycle; next && c < regsFree; next = next->next) {
3266 bbDelay = MAX2(bbDelay, calcDelay(next, c));
3267 c += getCycles(next, bbDelay);
3268 }
3269 next = NULL;
3270 }
3271 }
3272 if (bb->cfg.outgoingCount() != 1)
3273 next = NULL;
3274 setDelay(insn, bbDelay, next);
3275 cycle += getCycles(insn, bbDelay);
3276
3277 score->rebase(cycle); // common base for initializing out blocks' scores
3278 return true;
3279 }
3280
3281 #define NVE4_MAX_ISSUE_DELAY 0x1f
3282 int
3283 SchedDataCalculator::calcDelay(const Instruction *insn, int cycle) const
3284 {
3285 int delay = 0, ready = cycle;
3286
3287 for (int s = 0; insn->srcExists(s); ++s)
3288 checkRd(insn->getSrc(s), cycle, delay);
3289 // WAR & WAW don't seem to matter
3290 // for (int s = 0; insn->srcExists(s); ++s)
3291 // recordRd(insn->getSrc(s), cycle);
3292
3293 switch (Target::getOpClass(insn->op)) {
3294 case OPCLASS_SFU:
3295 ready = score->res.sfu;
3296 break;
3297 case OPCLASS_ARITH:
3298 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3299 ready = score->res.imul;
3300 break;
3301 case OPCLASS_TEXTURE:
3302 ready = score->res.tex;
3303 break;
3304 case OPCLASS_LOAD:
3305 ready = score->res.ld[insn->src(0).getFile()];
3306 break;
3307 case OPCLASS_STORE:
3308 ready = score->res.st[insn->src(0).getFile()];
3309 break;
3310 default:
3311 break;
3312 }
3313 if (Target::getOpClass(insn->op) != OPCLASS_TEXTURE)
3314 ready = MAX2(ready, score->res.tex);
3315
3316 delay = MAX2(delay, ready - cycle);
3317
3318 // if can issue next cycle, delay is 0, not 1
3319 return MIN2(delay - 1, NVE4_MAX_ISSUE_DELAY);
3320 }
3321
3322 void
3323 SchedDataCalculator::commitInsn(const Instruction *insn, int cycle)
3324 {
3325 const int ready = cycle + targ->getLatency(insn);
3326
3327 for (int d = 0; insn->defExists(d); ++d)
3328 recordWr(insn->getDef(d), ready);
3329 // WAR & WAW don't seem to matter
3330 // for (int s = 0; insn->srcExists(s); ++s)
3331 // recordRd(insn->getSrc(s), cycle);
3332
3333 switch (Target::getOpClass(insn->op)) {
3334 case OPCLASS_SFU:
3335 score->res.sfu = cycle + 4;
3336 break;
3337 case OPCLASS_ARITH:
3338 if (insn->op == OP_MUL && !isFloatType(insn->dType))
3339 score->res.imul = cycle + 4;
3340 break;
3341 case OPCLASS_TEXTURE:
3342 score->res.tex = cycle + 18;
3343 break;
3344 case OPCLASS_LOAD:
3345 if (insn->src(0).getFile() == FILE_MEMORY_CONST)
3346 break;
3347 score->res.ld[insn->src(0).getFile()] = cycle + 4;
3348 score->res.st[insn->src(0).getFile()] = ready;
3349 break;
3350 case OPCLASS_STORE:
3351 score->res.st[insn->src(0).getFile()] = cycle + 4;
3352 score->res.ld[insn->src(0).getFile()] = ready;
3353 break;
3354 case OPCLASS_OTHER:
3355 if (insn->op == OP_TEXBAR)
3356 score->res.tex = cycle;
3357 break;
3358 default:
3359 break;
3360 }
3361
3362 #ifdef NVC0_DEBUG_SCHED_DATA
3363 score->print(cycle);
3364 #endif
3365 }
3366
3367 void
3368 SchedDataCalculator::checkRd(const Value *v, int cycle, int& delay) const
3369 {
3370 int ready = cycle;
3371 int a, b;
3372
3373 switch (v->reg.file) {
3374 case FILE_GPR:
3375 a = v->reg.data.id;
3376 b = a + v->reg.size / 4;
3377 for (int r = a; r < b; ++r)
3378 ready = MAX2(ready, score->rd.r[r]);
3379 break;
3380 case FILE_PREDICATE:
3381 ready = MAX2(ready, score->rd.p[v->reg.data.id]);
3382 break;
3383 case FILE_FLAGS:
3384 ready = MAX2(ready, score->rd.c);
3385 break;
3386 case FILE_SHADER_INPUT:
3387 case FILE_SHADER_OUTPUT: // yes, TCPs can read outputs
3388 case FILE_MEMORY_LOCAL:
3389 case FILE_MEMORY_CONST:
3390 case FILE_MEMORY_SHARED:
3391 case FILE_MEMORY_GLOBAL:
3392 case FILE_SYSTEM_VALUE:
3393 // TODO: any restrictions here ?
3394 break;
3395 case FILE_IMMEDIATE:
3396 break;
3397 default:
3398 assert(0);
3399 break;
3400 }
3401 if (cycle < ready)
3402 delay = MAX2(delay, ready - cycle);
3403 }
3404
3405 void
3406 SchedDataCalculator::checkWr(const Value *v, int cycle, int& delay) const
3407 {
3408 int ready = cycle;
3409 int a, b;
3410
3411 switch (v->reg.file) {
3412 case FILE_GPR:
3413 a = v->reg.data.id;
3414 b = a + v->reg.size / 4;
3415 for (int r = a; r < b; ++r)
3416 ready = MAX2(ready, score->wr.r[r]);
3417 break;
3418 case FILE_PREDICATE:
3419 ready = MAX2(ready, score->wr.p[v->reg.data.id]);
3420 break;
3421 default:
3422 assert(v->reg.file == FILE_FLAGS);
3423 ready = MAX2(ready, score->wr.c);
3424 break;
3425 }
3426 if (cycle < ready)
3427 delay = MAX2(delay, ready - cycle);
3428 }
3429
3430 void
3431 SchedDataCalculator::recordWr(const Value *v, const int ready)
3432 {
3433 int a = v->reg.data.id;
3434
3435 if (v->reg.file == FILE_GPR) {
3436 int b = a + v->reg.size / 4;
3437 for (int r = a; r < b; ++r)
3438 score->rd.r[r] = ready;
3439 } else
3440 // $c, $pX: shorter issue-to-read delay (at least as exec pred and carry)
3441 if (v->reg.file == FILE_PREDICATE) {
3442 score->rd.p[a] = ready + 4;
3443 } else {
3444 assert(v->reg.file == FILE_FLAGS);
3445 score->rd.c = ready + 4;
3446 }
3447 }
3448
3449 void
3450 SchedDataCalculator::recordRd(const Value *v, const int ready)
3451 {
3452 int a = v->reg.data.id;
3453
3454 if (v->reg.file == FILE_GPR) {
3455 int b = a + v->reg.size / 4;
3456 for (int r = a; r < b; ++r)
3457 score->wr.r[r] = ready;
3458 } else
3459 if (v->reg.file == FILE_PREDICATE) {
3460 score->wr.p[a] = ready;
3461 } else
3462 if (v->reg.file == FILE_FLAGS) {
3463 score->wr.c = ready;
3464 }
3465 }
3466
3467 bool
3468 calculateSchedDataNVC0(const Target *targ, Function *func)
3469 {
3470 SchedDataCalculator sched(targ);
3471 return sched.run(func, true, true);
3472 }
3473
3474 void
3475 CodeEmitterNVC0::prepareEmission(Function *func)
3476 {
3477 CodeEmitter::prepareEmission(func);
3478
3479 if (targ->hasSWSched)
3480 calculateSchedDataNVC0(targ, func);
3481 }
3482
3483 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
3484 : CodeEmitter(target),
3485 targNVC0(target),
3486 writeIssueDelays(target->hasSWSched)
3487 {
3488 code = NULL;
3489 codeSize = codeSizeLimit = 0;
3490 relocInfo = NULL;
3491 }
3492
3493 CodeEmitter *
3494 TargetNVC0::createCodeEmitterNVC0(Program::Type type)
3495 {
3496 CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
3497 emit->setProgramType(type);
3498 return emit;
3499 }
3500
3501 CodeEmitter *
3502 TargetNVC0::getCodeEmitter(Program::Type type)
3503 {
3504 if (chipset >= NVISA_GK20A_CHIPSET)
3505 return createCodeEmitterGK110(type);
3506 return createCodeEmitterNVC0(type);
3507 }
3508
3509 } // namespace nv50_ir