projects / mesa.git / blob
? search:


3fa590a46555b1c52bc7aa437d3a647234ea8e5e
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_nir.cpp
1 /*
2 * Copyright 2017 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Karol Herbst <kherbst@redhat.com>
23 */
24
25 #include "compiler/nir/nir.h"
26
27 #include "util/u_debug.h"
28
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_from_common.h"
31 #include "codegen/nv50_ir_lowering_helper.h"
32 #include "codegen/nv50_ir_util.h"
33
34 #if __cplusplus >= 201103L
35 #include <unordered_map>
36 #else
37 #include <tr1/unordered_map>
38 #endif
39 #include <vector>
40
41 namespace {
42
43 #if __cplusplus >= 201103L
44 using std::hash;
45 using std::unordered_map;
46 #else
47 using std::tr1::hash;
48 using std::tr1::unordered_map;
49 #endif
50
51 using namespace nv50_ir;
52
53 int
54 type_size(const struct glsl_type *type)
55 {
56 return glsl_count_attribute_slots(type, false);
57 }
58
59 class Converter : public ConverterCommon
60 {
61 public:
62 Converter(Program *, nir_shader *, nv50_ir_prog_info *);
63
64 bool run();
65 private:
66 typedef std::vector<LValue*> LValues;
67 typedef unordered_map<unsigned, LValues> NirDefMap;
68 typedef unordered_map<unsigned, BasicBlock*> NirBlockMap;
69
70 LValues& convert(nir_alu_dest *);
71 BasicBlock* convert(nir_block *);
72 LValues& convert(nir_dest *);
73 LValues& convert(nir_register *);
74 LValues& convert(nir_ssa_def *);
75
76 Value* getSrc(nir_alu_src *, uint8_t component = 0);
77 Value* getSrc(nir_register *, uint8_t);
78 Value* getSrc(nir_src *, uint8_t, bool indirect = false);
79 Value* getSrc(nir_ssa_def *, uint8_t);
80
81 // returned value is the constant part of the given source (either the
82 // nir_src or the selected source component of an intrinsic). Even though
83 // this is mostly an optimization to be able to skip indirects in a few
84 // cases, sometimes we require immediate values or set some fileds on
85 // instructions (e.g. tex) in order for codegen to consume those.
86 // If the found value has not a constant part, the Value gets returned
87 // through the Value parameter.
88 uint32_t getIndirect(nir_src *, uint8_t, Value *&);
89 uint32_t getIndirect(nir_intrinsic_instr *, uint8_t s, uint8_t c, Value *&);
90
91 uint32_t getSlotAddress(nir_intrinsic_instr *, uint8_t idx, uint8_t slot);
92
93 void setInterpolate(nv50_ir_varying *,
94 uint8_t,
95 bool centroid,
96 unsigned semantics);
97
98 Instruction *loadFrom(DataFile, uint8_t, DataType, Value *def, uint32_t base,
99 uint8_t c, Value *indirect0 = NULL,
100 Value *indirect1 = NULL, bool patch = false);
101 void storeTo(nir_intrinsic_instr *, DataFile, operation, DataType,
102 Value *src, uint8_t idx, uint8_t c, Value *indirect0 = NULL,
103 Value *indirect1 = NULL);
104
105 bool isFloatType(nir_alu_type);
106 bool isSignedType(nir_alu_type);
107 bool isResultFloat(nir_op);
108 bool isResultSigned(nir_op);
109
110 DataType getDType(nir_alu_instr *);
111 DataType getDType(nir_intrinsic_instr *);
112 DataType getDType(nir_op, uint8_t);
113
114 std::vector<DataType> getSTypes(nir_alu_instr *);
115 DataType getSType(nir_src &, bool isFloat, bool isSigned);
116
117 bool assignSlots();
118 bool parseNIR();
119
120 bool visit(nir_block *);
121 bool visit(nir_cf_node *);
122 bool visit(nir_function *);
123 bool visit(nir_if *);
124 bool visit(nir_instr *);
125 bool visit(nir_jump_instr *);
126 bool visit(nir_load_const_instr*);
127 bool visit(nir_loop *);
128
129 nir_shader *nir;
130
131 NirDefMap ssaDefs;
132 NirDefMap regDefs;
133 NirBlockMap blocks;
134 unsigned int curLoopDepth;
135
136 BasicBlock *exit;
137
138 union {
139 struct {
140 Value *position;
141 } fp;
142 };
143 };
144
145 Converter::Converter(Program *prog, nir_shader *nir, nv50_ir_prog_info *info)
146 : ConverterCommon(prog, info),
147 nir(nir),
148 curLoopDepth(0) {}
149
150 BasicBlock *
151 Converter::convert(nir_block *block)
152 {
153 NirBlockMap::iterator it = blocks.find(block->index);
154 if (it != blocks.end())
155 return it->second;
156
157 BasicBlock *bb = new BasicBlock(func);
158 blocks[block->index] = bb;
159 return bb;
160 }
161
162 bool
163 Converter::isFloatType(nir_alu_type type)
164 {
165 return nir_alu_type_get_base_type(type) == nir_type_float;
166 }
167
168 bool
169 Converter::isSignedType(nir_alu_type type)
170 {
171 return nir_alu_type_get_base_type(type) == nir_type_int;
172 }
173
174 bool
175 Converter::isResultFloat(nir_op op)
176 {
177 const nir_op_info &info = nir_op_infos[op];
178 if (info.output_type != nir_type_invalid)
179 return isFloatType(info.output_type);
180
181 ERROR("isResultFloat not implemented for %s\n", nir_op_infos[op].name);
182 assert(false);
183 return true;
184 }
185
186 bool
187 Converter::isResultSigned(nir_op op)
188 {
189 switch (op) {
190 // there is no umul and we get wrong results if we treat all muls as signed
191 case nir_op_imul:
192 case nir_op_inot:
193 return false;
194 default:
195 const nir_op_info &info = nir_op_infos[op];
196 if (info.output_type != nir_type_invalid)
197 return isSignedType(info.output_type);
198 ERROR("isResultSigned not implemented for %s\n", nir_op_infos[op].name);
199 assert(false);
200 return true;
201 }
202 }
203
204 DataType
205 Converter::getDType(nir_alu_instr *insn)
206 {
207 if (insn->dest.dest.is_ssa)
208 return getDType(insn->op, insn->dest.dest.ssa.bit_size);
209 else
210 return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
211 }
212
213 DataType
214 Converter::getDType(nir_intrinsic_instr *insn)
215 {
216 if (insn->dest.is_ssa)
217 return typeOfSize(insn->dest.ssa.bit_size / 8, false, false);
218 else
219 return typeOfSize(insn->dest.reg.reg->bit_size / 8, false, false);
220 }
221
222 DataType
223 Converter::getDType(nir_op op, uint8_t bitSize)
224 {
225 DataType ty = typeOfSize(bitSize / 8, isResultFloat(op), isResultSigned(op));
226 if (ty == TYPE_NONE) {
227 ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos[op].name, bitSize);
228 assert(false);
229 }
230 return ty;
231 }
232
233 std::vector<DataType>
234 Converter::getSTypes(nir_alu_instr *insn)
235 {
236 const nir_op_info &info = nir_op_infos[insn->op];
237 std::vector<DataType> res(info.num_inputs);
238
239 for (uint8_t i = 0; i < info.num_inputs; ++i) {
240 if (info.input_types[i] != nir_type_invalid) {
241 res[i] = getSType(insn->src[i].src, isFloatType(info.input_types[i]), isSignedType(info.input_types[i]));
242 } else {
243 ERROR("getSType not implemented for %s idx %u\n", info.name, i);
244 assert(false);
245 res[i] = TYPE_NONE;
246 break;
247 }
248 }
249
250 return res;
251 }
252
253 DataType
254 Converter::getSType(nir_src &src, bool isFloat, bool isSigned)
255 {
256 uint8_t bitSize;
257 if (src.is_ssa)
258 bitSize = src.ssa->bit_size;
259 else
260 bitSize = src.reg.reg->bit_size;
261
262 DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned);
263 if (ty == TYPE_NONE) {
264 const char *str;
265 if (isFloat)
266 str = "float";
267 else if (isSigned)
268 str = "int";
269 else
270 str = "uint";
271 ERROR("couldn't get Type for %s with bitSize %u\n", str, bitSize);
272 assert(false);
273 }
274 return ty;
275 }
276
277 Converter::LValues&
278 Converter::convert(nir_dest *dest)
279 {
280 if (dest->is_ssa)
281 return convert(&dest->ssa);
282 if (dest->reg.indirect) {
283 ERROR("no support for indirects.");
284 assert(false);
285 }
286 return convert(dest->reg.reg);
287 }
288
289 Converter::LValues&
290 Converter::convert(nir_register *reg)
291 {
292 NirDefMap::iterator it = regDefs.find(reg->index);
293 if (it != regDefs.end())
294 return it->second;
295
296 LValues newDef(reg->num_components);
297 for (uint8_t i = 0; i < reg->num_components; i++)
298 newDef[i] = getScratch(std::max(4, reg->bit_size / 8));
299 return regDefs[reg->index] = newDef;
300 }
301
302 Converter::LValues&
303 Converter::convert(nir_ssa_def *def)
304 {
305 NirDefMap::iterator it = ssaDefs.find(def->index);
306 if (it != ssaDefs.end())
307 return it->second;
308
309 LValues newDef(def->num_components);
310 for (uint8_t i = 0; i < def->num_components; i++)
311 newDef[i] = getSSA(std::max(4, def->bit_size / 8));
312 return ssaDefs[def->index] = newDef;
313 }
314
315 Value*
316 Converter::getSrc(nir_alu_src *src, uint8_t component)
317 {
318 if (src->abs || src->negate) {
319 ERROR("modifiers currently not supported on nir_alu_src\n");
320 assert(false);
321 }
322 return getSrc(&src->src, src->swizzle[component]);
323 }
324
325 Value*
326 Converter::getSrc(nir_register *reg, uint8_t idx)
327 {
328 NirDefMap::iterator it = regDefs.find(reg->index);
329 if (it == regDefs.end())
330 return convert(reg)[idx];
331 return it->second[idx];
332 }
333
334 Value*
335 Converter::getSrc(nir_src *src, uint8_t idx, bool indirect)
336 {
337 if (src->is_ssa)
338 return getSrc(src->ssa, idx);
339
340 if (src->reg.indirect) {
341 if (indirect)
342 return getSrc(src->reg.indirect, idx);
343 ERROR("no support for indirects.");
344 assert(false);
345 return NULL;
346 }
347
348 return getSrc(src->reg.reg, idx);
349 }
350
351 Value*
352 Converter::getSrc(nir_ssa_def *src, uint8_t idx)
353 {
354 NirDefMap::iterator it = ssaDefs.find(src->index);
355 if (it == ssaDefs.end()) {
356 ERROR("SSA value %u not found\n", src->index);
357 assert(false);
358 return NULL;
359 }
360 return it->second[idx];
361 }
362
363 uint32_t
364 Converter::getIndirect(nir_src *src, uint8_t idx, Value *&indirect)
365 {
366 nir_const_value *offset = nir_src_as_const_value(*src);
367
368 if (offset) {
369 indirect = NULL;
370 return offset->u32[0];
371 }
372
373 indirect = getSrc(src, idx, true);
374 return 0;
375 }
376
377 uint32_t
378 Converter::getIndirect(nir_intrinsic_instr *insn, uint8_t s, uint8_t c, Value *&indirect)
379 {
380 int32_t idx = nir_intrinsic_base(insn) + getIndirect(&insn->src[s], c, indirect);
381 if (indirect)
382 indirect = mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), indirect, loadImm(NULL, 4));
383 return idx;
384 }
385
386 static void
387 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot, unsigned *name, unsigned *index)
388 {
389 assert(name && index);
390
391 if (slot >= VERT_ATTRIB_MAX) {
392 ERROR("invalid varying slot %u\n", slot);
393 assert(false);
394 return;
395 }
396
397 if (slot >= VERT_ATTRIB_GENERIC0 &&
398 slot < VERT_ATTRIB_GENERIC0 + VERT_ATTRIB_GENERIC_MAX) {
399 *name = TGSI_SEMANTIC_GENERIC;
400 *index = slot - VERT_ATTRIB_GENERIC0;
401 return;
402 }
403
404 if (slot >= VERT_ATTRIB_TEX0 &&
405 slot < VERT_ATTRIB_TEX0 + VERT_ATTRIB_TEX_MAX) {
406 *name = TGSI_SEMANTIC_TEXCOORD;
407 *index = slot - VERT_ATTRIB_TEX0;
408 return;
409 }
410
411 switch (slot) {
412 case VERT_ATTRIB_COLOR0:
413 *name = TGSI_SEMANTIC_COLOR;
414 *index = 0;
415 break;
416 case VERT_ATTRIB_COLOR1:
417 *name = TGSI_SEMANTIC_COLOR;
418 *index = 1;
419 break;
420 case VERT_ATTRIB_EDGEFLAG:
421 *name = TGSI_SEMANTIC_EDGEFLAG;
422 *index = 0;
423 break;
424 case VERT_ATTRIB_FOG:
425 *name = TGSI_SEMANTIC_FOG;
426 *index = 0;
427 break;
428 case VERT_ATTRIB_NORMAL:
429 *name = TGSI_SEMANTIC_NORMAL;
430 *index = 0;
431 break;
432 case VERT_ATTRIB_POS:
433 *name = TGSI_SEMANTIC_POSITION;
434 *index = 0;
435 break;
436 case VERT_ATTRIB_POINT_SIZE:
437 *name = TGSI_SEMANTIC_PSIZE;
438 *index = 0;
439 break;
440 default:
441 ERROR("unknown vert attrib slot %u\n", slot);
442 assert(false);
443 break;
444 }
445 }
446
447 static void
448 varying_slot_to_tgsi_semantic(gl_varying_slot slot, unsigned *name, unsigned *index)
449 {
450 assert(name && index);
451
452 if (slot >= VARYING_SLOT_TESS_MAX) {
453 ERROR("invalid varying slot %u\n", slot);
454 assert(false);
455 return;
456 }
457
458 if (slot >= VARYING_SLOT_PATCH0) {
459 *name = TGSI_SEMANTIC_PATCH;
460 *index = slot - VARYING_SLOT_PATCH0;
461 return;
462 }
463
464 if (slot >= VARYING_SLOT_VAR0) {
465 *name = TGSI_SEMANTIC_GENERIC;
466 *index = slot - VARYING_SLOT_VAR0;
467 return;
468 }
469
470 if (slot >= VARYING_SLOT_TEX0 && slot <= VARYING_SLOT_TEX7) {
471 *name = TGSI_SEMANTIC_TEXCOORD;
472 *index = slot - VARYING_SLOT_TEX0;
473 return;
474 }
475
476 switch (slot) {
477 case VARYING_SLOT_BFC0:
478 *name = TGSI_SEMANTIC_BCOLOR;
479 *index = 0;
480 break;
481 case VARYING_SLOT_BFC1:
482 *name = TGSI_SEMANTIC_BCOLOR;
483 *index = 1;
484 break;
485 case VARYING_SLOT_CLIP_DIST0:
486 *name = TGSI_SEMANTIC_CLIPDIST;
487 *index = 0;
488 break;
489 case VARYING_SLOT_CLIP_DIST1:
490 *name = TGSI_SEMANTIC_CLIPDIST;
491 *index = 1;
492 break;
493 case VARYING_SLOT_CLIP_VERTEX:
494 *name = TGSI_SEMANTIC_CLIPVERTEX;
495 *index = 0;
496 break;
497 case VARYING_SLOT_COL0:
498 *name = TGSI_SEMANTIC_COLOR;
499 *index = 0;
500 break;
501 case VARYING_SLOT_COL1:
502 *name = TGSI_SEMANTIC_COLOR;
503 *index = 1;
504 break;
505 case VARYING_SLOT_EDGE:
506 *name = TGSI_SEMANTIC_EDGEFLAG;
507 *index = 0;
508 break;
509 case VARYING_SLOT_FACE:
510 *name = TGSI_SEMANTIC_FACE;
511 *index = 0;
512 break;
513 case VARYING_SLOT_FOGC:
514 *name = TGSI_SEMANTIC_FOG;
515 *index = 0;
516 break;
517 case VARYING_SLOT_LAYER:
518 *name = TGSI_SEMANTIC_LAYER;
519 *index = 0;
520 break;
521 case VARYING_SLOT_PNTC:
522 *name = TGSI_SEMANTIC_PCOORD;
523 *index = 0;
524 break;
525 case VARYING_SLOT_POS:
526 *name = TGSI_SEMANTIC_POSITION;
527 *index = 0;
528 break;
529 case VARYING_SLOT_PRIMITIVE_ID:
530 *name = TGSI_SEMANTIC_PRIMID;
531 *index = 0;
532 break;
533 case VARYING_SLOT_PSIZ:
534 *name = TGSI_SEMANTIC_PSIZE;
535 *index = 0;
536 break;
537 case VARYING_SLOT_TESS_LEVEL_INNER:
538 *name = TGSI_SEMANTIC_TESSINNER;
539 *index = 0;
540 break;
541 case VARYING_SLOT_TESS_LEVEL_OUTER:
542 *name = TGSI_SEMANTIC_TESSOUTER;
543 *index = 0;
544 break;
545 case VARYING_SLOT_VIEWPORT:
546 *name = TGSI_SEMANTIC_VIEWPORT_INDEX;
547 *index = 0;
548 break;
549 default:
550 ERROR("unknown varying slot %u\n", slot);
551 assert(false);
552 break;
553 }
554 }
555
556 static void
557 frag_result_to_tgsi_semantic(unsigned slot, unsigned *name, unsigned *index)
558 {
559 if (slot >= FRAG_RESULT_DATA0) {
560 *name = TGSI_SEMANTIC_COLOR;
561 *index = slot - FRAG_RESULT_COLOR - 2; // intentional
562 return;
563 }
564
565 switch (slot) {
566 case FRAG_RESULT_COLOR:
567 *name = TGSI_SEMANTIC_COLOR;
568 *index = 0;
569 break;
570 case FRAG_RESULT_DEPTH:
571 *name = TGSI_SEMANTIC_POSITION;
572 *index = 0;
573 break;
574 case FRAG_RESULT_SAMPLE_MASK:
575 *name = TGSI_SEMANTIC_SAMPLEMASK;
576 *index = 0;
577 break;
578 default:
579 ERROR("unknown frag result slot %u\n", slot);
580 assert(false);
581 break;
582 }
583 }
584
585 // copy of _mesa_sysval_to_semantic
586 static void
587 system_val_to_tgsi_semantic(unsigned val, unsigned *name, unsigned *index)
588 {
589 *index = 0;
590 switch (val) {
591 // Vertex shader
592 case SYSTEM_VALUE_VERTEX_ID:
593 *name = TGSI_SEMANTIC_VERTEXID;
594 break;
595 case SYSTEM_VALUE_INSTANCE_ID:
596 *name = TGSI_SEMANTIC_INSTANCEID;
597 break;
598 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
599 *name = TGSI_SEMANTIC_VERTEXID_NOBASE;
600 break;
601 case SYSTEM_VALUE_BASE_VERTEX:
602 *name = TGSI_SEMANTIC_BASEVERTEX;
603 break;
604 case SYSTEM_VALUE_BASE_INSTANCE:
605 *name = TGSI_SEMANTIC_BASEINSTANCE;
606 break;
607 case SYSTEM_VALUE_DRAW_ID:
608 *name = TGSI_SEMANTIC_DRAWID;
609 break;
610
611 // Geometry shader
612 case SYSTEM_VALUE_INVOCATION_ID:
613 *name = TGSI_SEMANTIC_INVOCATIONID;
614 break;
615
616 // Fragment shader
617 case SYSTEM_VALUE_FRAG_COORD:
618 *name = TGSI_SEMANTIC_POSITION;
619 break;
620 case SYSTEM_VALUE_FRONT_FACE:
621 *name = TGSI_SEMANTIC_FACE;
622 break;
623 case SYSTEM_VALUE_SAMPLE_ID:
624 *name = TGSI_SEMANTIC_SAMPLEID;
625 break;
626 case SYSTEM_VALUE_SAMPLE_POS:
627 *name = TGSI_SEMANTIC_SAMPLEPOS;
628 break;
629 case SYSTEM_VALUE_SAMPLE_MASK_IN:
630 *name = TGSI_SEMANTIC_SAMPLEMASK;
631 break;
632 case SYSTEM_VALUE_HELPER_INVOCATION:
633 *name = TGSI_SEMANTIC_HELPER_INVOCATION;
634 break;
635
636 // Tessellation shader
637 case SYSTEM_VALUE_TESS_COORD:
638 *name = TGSI_SEMANTIC_TESSCOORD;
639 break;
640 case SYSTEM_VALUE_VERTICES_IN:
641 *name = TGSI_SEMANTIC_VERTICESIN;
642 break;
643 case SYSTEM_VALUE_PRIMITIVE_ID:
644 *name = TGSI_SEMANTIC_PRIMID;
645 break;
646 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
647 *name = TGSI_SEMANTIC_TESSOUTER;
648 break;
649 case SYSTEM_VALUE_TESS_LEVEL_INNER:
650 *name = TGSI_SEMANTIC_TESSINNER;
651 break;
652
653 // Compute shader
654 case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
655 *name = TGSI_SEMANTIC_THREAD_ID;
656 break;
657 case SYSTEM_VALUE_WORK_GROUP_ID:
658 *name = TGSI_SEMANTIC_BLOCK_ID;
659 break;
660 case SYSTEM_VALUE_NUM_WORK_GROUPS:
661 *name = TGSI_SEMANTIC_GRID_SIZE;
662 break;
663 case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
664 *name = TGSI_SEMANTIC_BLOCK_SIZE;
665 break;
666
667 // ARB_shader_ballot
668 case SYSTEM_VALUE_SUBGROUP_SIZE:
669 *name = TGSI_SEMANTIC_SUBGROUP_SIZE;
670 break;
671 case SYSTEM_VALUE_SUBGROUP_INVOCATION:
672 *name = TGSI_SEMANTIC_SUBGROUP_INVOCATION;
673 break;
674 case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
675 *name = TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
676 break;
677 case SYSTEM_VALUE_SUBGROUP_GE_MASK:
678 *name = TGSI_SEMANTIC_SUBGROUP_GE_MASK;
679 break;
680 case SYSTEM_VALUE_SUBGROUP_GT_MASK:
681 *name = TGSI_SEMANTIC_SUBGROUP_GT_MASK;
682 break;
683 case SYSTEM_VALUE_SUBGROUP_LE_MASK:
684 *name = TGSI_SEMANTIC_SUBGROUP_LE_MASK;
685 break;
686 case SYSTEM_VALUE_SUBGROUP_LT_MASK:
687 *name = TGSI_SEMANTIC_SUBGROUP_LT_MASK;
688 break;
689
690 default:
691 ERROR("unknown system value %u\n", val);
692 assert(false);
693 break;
694 }
695 }
696
697 void
698 Converter::setInterpolate(nv50_ir_varying *var,
699 uint8_t mode,
700 bool centroid,
701 unsigned semantic)
702 {
703 switch (mode) {
704 case INTERP_MODE_FLAT:
705 var->flat = 1;
706 break;
707 case INTERP_MODE_NONE:
708 if (semantic == TGSI_SEMANTIC_COLOR)
709 var->sc = 1;
710 else if (semantic == TGSI_SEMANTIC_POSITION)
711 var->linear = 1;
712 break;
713 case INTERP_MODE_NOPERSPECTIVE:
714 var->linear = 1;
715 break;
716 case INTERP_MODE_SMOOTH:
717 break;
718 }
719 var->centroid = centroid;
720 }
721
722 static uint16_t
723 calcSlots(const glsl_type *type, Program::Type stage, const shader_info &info,
724 bool input, const nir_variable *var)
725 {
726 if (!type->is_array())
727 return type->count_attribute_slots(false);
728
729 uint16_t slots;
730 switch (stage) {
731 case Program::TYPE_GEOMETRY:
732 slots = type->uniform_locations();
733 if (input)
734 slots /= info.gs.vertices_in;
735 break;
736 case Program::TYPE_TESSELLATION_CONTROL:
737 case Program::TYPE_TESSELLATION_EVAL:
738 // remove first dimension
739 if (var->data.patch || (!input && stage == Program::TYPE_TESSELLATION_EVAL))
740 slots = type->uniform_locations();
741 else
742 slots = type->fields.array->uniform_locations();
743 break;
744 default:
745 slots = type->count_attribute_slots(false);
746 break;
747 }
748
749 return slots;
750 }
751
752 bool Converter::assignSlots() {
753 unsigned name;
754 unsigned index;
755
756 info->io.viewportId = -1;
757 info->numInputs = 0;
758
759 // we have to fixup the uniform locations for arrays
760 unsigned numImages = 0;
761 nir_foreach_variable(var, &nir->uniforms) {
762 const glsl_type *type = var->type;
763 if (!type->without_array()->is_image())
764 continue;
765 var->data.driver_location = numImages;
766 numImages += type->is_array() ? type->arrays_of_arrays_size() : 1;
767 }
768
769 nir_foreach_variable(var, &nir->inputs) {
770 const glsl_type *type = var->type;
771 int slot = var->data.location;
772 uint16_t slots = calcSlots(type, prog->getType(), nir->info, true, var);
773 uint32_t comp = type->is_array() ? type->without_array()->component_slots()
774 : type->component_slots();
775 uint32_t frac = var->data.location_frac;
776 uint32_t vary = var->data.driver_location;
777
778 if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
779 if (comp > 2)
780 slots *= 2;
781 }
782
783 assert(vary + slots <= PIPE_MAX_SHADER_INPUTS);
784
785 switch(prog->getType()) {
786 case Program::TYPE_FRAGMENT:
787 varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
788 for (uint16_t i = 0; i < slots; ++i) {
789 setInterpolate(&info->in[vary + i], var->data.interpolation,
790 var->data.centroid | var->data.sample, name);
791 }
792 break;
793 case Program::TYPE_GEOMETRY:
794 varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
795 break;
796 case Program::TYPE_TESSELLATION_CONTROL:
797 case Program::TYPE_TESSELLATION_EVAL:
798 varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
799 if (var->data.patch && name == TGSI_SEMANTIC_PATCH)
800 info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
801 break;
802 case Program::TYPE_VERTEX:
803 vert_attrib_to_tgsi_semantic((gl_vert_attrib)slot, &name, &index);
804 switch (name) {
805 case TGSI_SEMANTIC_EDGEFLAG:
806 info->io.edgeFlagIn = vary;
807 break;
808 default:
809 break;
810 }
811 break;
812 default:
813 ERROR("unknown shader type %u in assignSlots\n", prog->getType());
814 return false;
815 }
816
817 for (uint16_t i = 0u; i < slots; ++i, ++vary) {
818 info->in[vary].id = vary;
819 info->in[vary].patch = var->data.patch;
820 info->in[vary].sn = name;
821 info->in[vary].si = index + i;
822 if (glsl_base_type_is_64bit(type->without_array()->base_type))
823 if (i & 0x1)
824 info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
825 else
826 info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
827 else
828 info->in[vary].mask |= ((1 << comp) - 1) << frac;
829 }
830 info->numInputs = std::max<uint8_t>(info->numInputs, vary);
831 }
832
833 info->numOutputs = 0;
834 nir_foreach_variable(var, &nir->outputs) {
835 const glsl_type *type = var->type;
836 int slot = var->data.location;
837 uint16_t slots = calcSlots(type, prog->getType(), nir->info, false, var);
838 uint32_t comp = type->is_array() ? type->without_array()->component_slots()
839 : type->component_slots();
840 uint32_t frac = var->data.location_frac;
841 uint32_t vary = var->data.driver_location;
842
843 if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
844 if (comp > 2)
845 slots *= 2;
846 }
847
848 assert(vary < PIPE_MAX_SHADER_OUTPUTS);
849
850 switch(prog->getType()) {
851 case Program::TYPE_FRAGMENT:
852 frag_result_to_tgsi_semantic((gl_frag_result)slot, &name, &index);
853 switch (name) {
854 case TGSI_SEMANTIC_COLOR:
855 if (!var->data.fb_fetch_output)
856 info->prop.fp.numColourResults++;
857 info->prop.fp.separateFragData = true;
858 // sometimes we get FRAG_RESULT_DATAX with data.index 0
859 // sometimes we get FRAG_RESULT_DATA0 with data.index X
860 index = index == 0 ? var->data.index : index;
861 break;
862 case TGSI_SEMANTIC_POSITION:
863 info->io.fragDepth = vary;
864 info->prop.fp.writesDepth = true;
865 break;
866 case TGSI_SEMANTIC_SAMPLEMASK:
867 info->io.sampleMask = vary;
868 break;
869 default:
870 break;
871 }
872 break;
873 case Program::TYPE_GEOMETRY:
874 case Program::TYPE_TESSELLATION_CONTROL:
875 case Program::TYPE_TESSELLATION_EVAL:
876 case Program::TYPE_VERTEX:
877 varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
878
879 if (var->data.patch && name != TGSI_SEMANTIC_TESSINNER &&
880 name != TGSI_SEMANTIC_TESSOUTER)
881 info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
882
883 switch (name) {
884 case TGSI_SEMANTIC_CLIPDIST:
885 info->io.genUserClip = -1;
886 break;
887 case TGSI_SEMANTIC_EDGEFLAG:
888 info->io.edgeFlagOut = vary;
889 break;
890 default:
891 break;
892 }
893 break;
894 default:
895 ERROR("unknown shader type %u in assignSlots\n", prog->getType());
896 return false;
897 }
898
899 for (uint16_t i = 0u; i < slots; ++i, ++vary) {
900 info->out[vary].id = vary;
901 info->out[vary].patch = var->data.patch;
902 info->out[vary].sn = name;
903 info->out[vary].si = index + i;
904 if (glsl_base_type_is_64bit(type->without_array()->base_type))
905 if (i & 0x1)
906 info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
907 else
908 info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
909 else
910 info->out[vary].mask |= ((1 << comp) - 1) << frac;
911
912 if (nir->info.outputs_read & 1ll << slot)
913 info->out[vary].oread = 1;
914 }
915 info->numOutputs = std::max<uint8_t>(info->numOutputs, vary);
916 }
917
918 info->numSysVals = 0;
919 for (uint8_t i = 0; i < 64; ++i) {
920 if (!(nir->info.system_values_read & 1ll << i))
921 continue;
922
923 system_val_to_tgsi_semantic(i, &name, &index);
924 info->sv[info->numSysVals].sn = name;
925 info->sv[info->numSysVals].si = index;
926 info->sv[info->numSysVals].input = 0; // TODO inferSysValDirection(sn);
927
928 switch (i) {
929 case SYSTEM_VALUE_INSTANCE_ID:
930 info->io.instanceId = info->numSysVals;
931 break;
932 case SYSTEM_VALUE_TESS_LEVEL_INNER:
933 case SYSTEM_VALUE_TESS_LEVEL_OUTER:
934 info->sv[info->numSysVals].patch = 1;
935 break;
936 case SYSTEM_VALUE_VERTEX_ID:
937 info->io.vertexId = info->numSysVals;
938 break;
939 default:
940 break;
941 }
942
943 info->numSysVals += 1;
944 }
945
946 if (info->io.genUserClip > 0) {
947 info->io.clipDistances = info->io.genUserClip;
948
949 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
950
951 for (unsigned int n = 0; n < nOut; ++n) {
952 unsigned int i = info->numOutputs++;
953 info->out[i].id = i;
954 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
955 info->out[i].si = n;
956 info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
957 }
958 }
959
960 return info->assignSlots(info) == 0;
961 }
962
963 uint32_t
964 Converter::getSlotAddress(nir_intrinsic_instr *insn, uint8_t idx, uint8_t slot)
965 {
966 DataType ty;
967 int offset = nir_intrinsic_component(insn);
968 bool input;
969
970 if (nir_intrinsic_infos[insn->intrinsic].has_dest)
971 ty = getDType(insn);
972 else
973 ty = getSType(insn->src[0], false, false);
974
975 switch (insn->intrinsic) {
976 case nir_intrinsic_load_input:
977 case nir_intrinsic_load_interpolated_input:
978 case nir_intrinsic_load_per_vertex_input:
979 input = true;
980 break;
981 case nir_intrinsic_load_output:
982 case nir_intrinsic_load_per_vertex_output:
983 case nir_intrinsic_store_output:
984 case nir_intrinsic_store_per_vertex_output:
985 input = false;
986 break;
987 default:
988 ERROR("unknown intrinsic in getSlotAddress %s",
989 nir_intrinsic_infos[insn->intrinsic].name);
990 input = false;
991 assert(false);
992 break;
993 }
994
995 if (typeSizeof(ty) == 8) {
996 slot *= 2;
997 slot += offset;
998 if (slot >= 4) {
999 idx += 1;
1000 slot -= 4;
1001 }
1002 } else {
1003 slot += offset;
1004 }
1005
1006 assert(slot < 4);
1007 assert(!input || idx < PIPE_MAX_SHADER_INPUTS);
1008 assert(input || idx < PIPE_MAX_SHADER_OUTPUTS);
1009
1010 const nv50_ir_varying *vary = input ? info->in : info->out;
1011 return vary[idx].slot[slot] * 4;
1012 }
1013
1014 Instruction *
1015 Converter::loadFrom(DataFile file, uint8_t i, DataType ty, Value *def,
1016 uint32_t base, uint8_t c, Value *indirect0,
1017 Value *indirect1, bool patch)
1018 {
1019 unsigned int tySize = typeSizeof(ty);
1020
1021 if (tySize == 8 &&
1022 (file == FILE_MEMORY_CONST || file == FILE_MEMORY_BUFFER || indirect0)) {
1023 Value *lo = getSSA();
1024 Value *hi = getSSA();
1025
1026 Instruction *loi =
1027 mkLoad(TYPE_U32, lo,
1028 mkSymbol(file, i, TYPE_U32, base + c * tySize),
1029 indirect0);
1030 loi->setIndirect(0, 1, indirect1);
1031 loi->perPatch = patch;
1032
1033 Instruction *hii =
1034 mkLoad(TYPE_U32, hi,
1035 mkSymbol(file, i, TYPE_U32, base + c * tySize + 4),
1036 indirect0);
1037 hii->setIndirect(0, 1, indirect1);
1038 hii->perPatch = patch;
1039
1040 return mkOp2(OP_MERGE, ty, def, lo, hi);
1041 } else {
1042 Instruction *ld =
1043 mkLoad(ty, def, mkSymbol(file, i, ty, base + c * tySize), indirect0);
1044 ld->setIndirect(0, 1, indirect1);
1045 ld->perPatch = patch;
1046 return ld;
1047 }
1048 }
1049
1050 void
1051 Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
1052 DataType ty, Value *src, uint8_t idx, uint8_t c,
1053 Value *indirect0, Value *indirect1)
1054 {
1055 uint8_t size = typeSizeof(ty);
1056 uint32_t address = getSlotAddress(insn, idx, c);
1057
1058 if (size == 8 && indirect0) {
1059 Value *split[2];
1060 mkSplit(split, 4, src);
1061
1062 if (op == OP_EXPORT) {
1063 split[0] = mkMov(getSSA(), split[0], ty)->getDef(0);
1064 split[1] = mkMov(getSSA(), split[1], ty)->getDef(0);
1065 }
1066
1067 mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address), indirect0,
1068 split[0])->perPatch = info->out[idx].patch;
1069 mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address + 4), indirect0,
1070 split[1])->perPatch = info->out[idx].patch;
1071 } else {
1072 if (op == OP_EXPORT)
1073 src = mkMov(getSSA(size), src, ty)->getDef(0);
1074 mkStore(op, ty, mkSymbol(file, 0, ty, address), indirect0,
1075 src)->perPatch = info->out[idx].patch;
1076 }
1077 }
1078
1079 bool
1080 Converter::parseNIR()
1081 {
1082 info->io.clipDistances = nir->info.clip_distance_array_size;
1083 info->io.cullDistances = nir->info.cull_distance_array_size;
1084
1085 switch(prog->getType()) {
1086 case Program::TYPE_COMPUTE:
1087 info->prop.cp.numThreads[0] = nir->info.cs.local_size[0];
1088 info->prop.cp.numThreads[1] = nir->info.cs.local_size[1];
1089 info->prop.cp.numThreads[2] = nir->info.cs.local_size[2];
1090 info->bin.smemSize = nir->info.cs.shared_size;
1091 break;
1092 case Program::TYPE_FRAGMENT:
1093 info->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
1094 info->prop.fp.persampleInvocation =
1095 (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
1096 (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1097 info->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
1098 info->prop.fp.readsSampleLocations =
1099 (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1100 info->prop.fp.usesDiscard = nir->info.fs.uses_discard;
1101 info->prop.fp.usesSampleMaskIn =
1102 !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
1103 break;
1104 case Program::TYPE_GEOMETRY:
1105 info->prop.gp.inputPrim = nir->info.gs.input_primitive;
1106 info->prop.gp.instanceCount = nir->info.gs.invocations;
1107 info->prop.gp.maxVertices = nir->info.gs.vertices_out;
1108 info->prop.gp.outputPrim = nir->info.gs.output_primitive;
1109 break;
1110 case Program::TYPE_TESSELLATION_CONTROL:
1111 case Program::TYPE_TESSELLATION_EVAL:
1112 if (nir->info.tess.primitive_mode == GL_ISOLINES)
1113 info->prop.tp.domain = GL_LINES;
1114 else
1115 info->prop.tp.domain = nir->info.tess.primitive_mode;
1116 info->prop.tp.outputPatchSize = nir->info.tess.tcs_vertices_out;
1117 info->prop.tp.outputPrim =
1118 nir->info.tess.point_mode ? PIPE_PRIM_POINTS : PIPE_PRIM_TRIANGLES;
1119 info->prop.tp.partitioning = (nir->info.tess.spacing + 1) % 3;
1120 info->prop.tp.winding = !nir->info.tess.ccw;
1121 break;
1122 case Program::TYPE_VERTEX:
1123 info->prop.vp.usesDrawParameters =
1124 (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
1125 (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
1126 (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
1127 break;
1128 default:
1129 break;
1130 }
1131
1132 return true;
1133 }
1134
1135 bool
1136 Converter::visit(nir_function *function)
1137 {
1138 // we only support emiting the main function for now
1139 assert(!strcmp(function->name, "main"));
1140 assert(function->impl);
1141
1142 // usually the blocks will set everything up, but main is special
1143 BasicBlock *entry = new BasicBlock(prog->main);
1144 exit = new BasicBlock(prog->main);
1145 blocks[nir_start_block(function->impl)->index] = entry;
1146 prog->main->setEntry(entry);
1147 prog->main->setExit(exit);
1148
1149 setPosition(entry, true);
1150
1151 switch (prog->getType()) {
1152 case Program::TYPE_TESSELLATION_CONTROL:
1153 outBase = mkOp2v(
1154 OP_SUB, TYPE_U32, getSSA(),
1155 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
1156 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
1157 break;
1158 case Program::TYPE_FRAGMENT: {
1159 Symbol *sv = mkSysVal(SV_POSITION, 3);
1160 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
1161 fp.position = mkOp1v(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
1162 break;
1163 }
1164 default:
1165 break;
1166 }
1167
1168 nir_index_ssa_defs(function->impl);
1169 foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
1170 if (!visit(node))
1171 return false;
1172 }
1173
1174 bb->cfg.attach(&exit->cfg, Graph::Edge::TREE);
1175 setPosition(exit, true);
1176
1177 // TODO: for non main function this needs to be a OP_RETURN
1178 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
1179 return true;
1180 }
1181
1182 bool
1183 Converter::visit(nir_cf_node *node)
1184 {
1185 switch (node->type) {
1186 case nir_cf_node_block:
1187 return visit(nir_cf_node_as_block(node));
1188 case nir_cf_node_if:
1189 return visit(nir_cf_node_as_if(node));
1190 case nir_cf_node_loop:
1191 return visit(nir_cf_node_as_loop(node));
1192 default:
1193 ERROR("unknown nir_cf_node type %u\n", node->type);
1194 return false;
1195 }
1196 }
1197
1198 bool
1199 Converter::visit(nir_block *block)
1200 {
1201 if (!block->predecessors->entries && block->instr_list.is_empty())
1202 return true;
1203
1204 BasicBlock *bb = convert(block);
1205
1206 setPosition(bb, true);
1207 nir_foreach_instr(insn, block) {
1208 if (!visit(insn))
1209 return false;
1210 }
1211 return true;
1212 }
1213
1214 bool
1215 Converter::visit(nir_if *nif)
1216 {
1217 DataType sType = getSType(nif->condition, false, false);
1218 Value *src = getSrc(&nif->condition, 0);
1219
1220 nir_block *lastThen = nir_if_last_then_block(nif);
1221 nir_block *lastElse = nir_if_last_else_block(nif);
1222
1223 assert(!lastThen->successors[1]);
1224 assert(!lastElse->successors[1]);
1225
1226 BasicBlock *ifBB = convert(nir_if_first_then_block(nif));
1227 BasicBlock *elseBB = convert(nir_if_first_else_block(nif));
1228
1229 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1230 bb->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
1231
1232 // we only insert joinats, if both nodes end up at the end of the if again.
1233 // the reason for this to not happens are breaks/continues/ret/... which
1234 // have their own handling
1235 if (lastThen->successors[0] == lastElse->successors[0])
1236 bb->joinAt = mkFlow(OP_JOINAT, convert(lastThen->successors[0]),
1237 CC_ALWAYS, NULL);
1238
1239 mkFlow(OP_BRA, elseBB, CC_EQ, src)->setType(sType);
1240
1241 foreach_list_typed(nir_cf_node, node, node, &nif->then_list) {
1242 if (!visit(node))
1243 return false;
1244 }
1245 setPosition(convert(lastThen), true);
1246 if (!bb->getExit() ||
1247 !bb->getExit()->asFlow() ||
1248 bb->getExit()->asFlow()->op == OP_JOIN) {
1249 BasicBlock *tailBB = convert(lastThen->successors[0]);
1250 mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1251 bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1252 }
1253
1254 foreach_list_typed(nir_cf_node, node, node, &nif->else_list) {
1255 if (!visit(node))
1256 return false;
1257 }
1258 setPosition(convert(lastElse), true);
1259 if (!bb->getExit() ||
1260 !bb->getExit()->asFlow() ||
1261 bb->getExit()->asFlow()->op == OP_JOIN) {
1262 BasicBlock *tailBB = convert(lastElse->successors[0]);
1263 mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1264 bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1265 }
1266
1267 if (lastThen->successors[0] == lastElse->successors[0]) {
1268 setPosition(convert(lastThen->successors[0]), true);
1269 mkFlow(OP_JOIN, NULL, CC_ALWAYS, NULL)->fixed = 1;
1270 }
1271
1272 return true;
1273 }
1274
1275 bool
1276 Converter::visit(nir_loop *loop)
1277 {
1278 curLoopDepth += 1;
1279 func->loopNestingBound = std::max(func->loopNestingBound, curLoopDepth);
1280
1281 BasicBlock *loopBB = convert(nir_loop_first_block(loop));
1282 BasicBlock *tailBB =
1283 convert(nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)));
1284 bb->cfg.attach(&loopBB->cfg, Graph::Edge::TREE);
1285
1286 mkFlow(OP_PREBREAK, tailBB, CC_ALWAYS, NULL);
1287 setPosition(loopBB, false);
1288 mkFlow(OP_PRECONT, loopBB, CC_ALWAYS, NULL);
1289
1290 foreach_list_typed(nir_cf_node, node, node, &loop->body) {
1291 if (!visit(node))
1292 return false;
1293 }
1294 Instruction *insn = bb->getExit();
1295 if (bb->cfg.incidentCount() != 0) {
1296 if (!insn || !insn->asFlow()) {
1297 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
1298 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
1299 } else if (insn && insn->op == OP_BRA && !insn->getPredicate() &&
1300 tailBB->cfg.incidentCount() == 0) {
1301 // RA doesn't like having blocks around with no incident edge,
1302 // so we create a fake one to make it happy
1303 bb->cfg.attach(&tailBB->cfg, Graph::Edge::TREE);
1304 }
1305 }
1306
1307 curLoopDepth -= 1;
1308
1309 return true;
1310 }
1311
1312 bool
1313 Converter::visit(nir_instr *insn)
1314 {
1315 switch (insn->type) {
1316 case nir_instr_type_jump:
1317 return visit(nir_instr_as_jump(insn));
1318 case nir_instr_type_load_const:
1319 return visit(nir_instr_as_load_const(insn));
1320 default:
1321 ERROR("unknown nir_instr type %u\n", insn->type);
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 bool
1328 Converter::visit(nir_jump_instr *insn)
1329 {
1330 switch (insn->type) {
1331 case nir_jump_return:
1332 // TODO: this only works in the main function
1333 mkFlow(OP_BRA, exit, CC_ALWAYS, NULL);
1334 bb->cfg.attach(&exit->cfg, Graph::Edge::CROSS);
1335 break;
1336 case nir_jump_break:
1337 case nir_jump_continue: {
1338 bool isBreak = insn->type == nir_jump_break;
1339 nir_block *block = insn->instr.block;
1340 assert(!block->successors[1]);
1341 BasicBlock *target = convert(block->successors[0]);
1342 mkFlow(isBreak ? OP_BREAK : OP_CONT, target, CC_ALWAYS, NULL);
1343 bb->cfg.attach(&target->cfg, isBreak ? Graph::Edge::CROSS : Graph::Edge::BACK);
1344 break;
1345 }
1346 default:
1347 ERROR("unknown nir_jump_type %u\n", insn->type);
1348 return false;
1349 }
1350
1351 return true;
1352 }
1353
1354 bool
1355 Converter::visit(nir_load_const_instr *insn)
1356 {
1357 assert(insn->def.bit_size <= 64);
1358
1359 LValues &newDefs = convert(&insn->def);
1360 for (int i = 0; i < insn->def.num_components; i++) {
1361 switch (insn->def.bit_size) {
1362 case 64:
1363 loadImm(newDefs[i], insn->value.u64[i]);
1364 break;
1365 case 32:
1366 loadImm(newDefs[i], insn->value.u32[i]);
1367 break;
1368 case 16:
1369 loadImm(newDefs[i], insn->value.u16[i]);
1370 break;
1371 case 8:
1372 loadImm(newDefs[i], insn->value.u8[i]);
1373 break;
1374 }
1375 }
1376 return true;
1377 }
1378
1379 bool
1380 Converter::run()
1381 {
1382 bool progress;
1383
1384 if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
1385 nir_print_shader(nir, stderr);
1386
1387 NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, (nir_lower_io_options)0);
1388 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
1389 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
1390 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1391 NIR_PASS_V(nir, nir_lower_alu_to_scalar);
1392 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
1393
1394 do {
1395 progress = false;
1396 NIR_PASS(progress, nir, nir_copy_prop);
1397 NIR_PASS(progress, nir, nir_opt_remove_phis);
1398 NIR_PASS(progress, nir, nir_opt_trivial_continues);
1399 NIR_PASS(progress, nir, nir_opt_cse);
1400 NIR_PASS(progress, nir, nir_opt_algebraic);
1401 NIR_PASS(progress, nir, nir_opt_constant_folding);
1402 NIR_PASS(progress, nir, nir_copy_prop);
1403 NIR_PASS(progress, nir, nir_opt_dce);
1404 NIR_PASS(progress, nir, nir_opt_dead_cf);
1405 } while (progress);
1406
1407 NIR_PASS_V(nir, nir_lower_bool_to_int32);
1408 NIR_PASS_V(nir, nir_lower_locals_to_regs);
1409 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
1410 NIR_PASS_V(nir, nir_convert_from_ssa, true);
1411
1412 // Garbage collect dead instructions
1413 nir_sweep(nir);
1414
1415 if (!parseNIR()) {
1416 ERROR("Couldn't prase NIR!\n");
1417 return false;
1418 }
1419
1420 if (!assignSlots()) {
1421 ERROR("Couldn't assign slots!\n");
1422 return false;
1423 }
1424
1425 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
1426 nir_print_shader(nir, stderr);
1427
1428 nir_foreach_function(function, nir) {
1429 if (!visit(function))
1430 return false;
1431 }
1432
1433 return true;
1434 }
1435
1436 } // unnamed namespace
1437
1438 namespace nv50_ir {
1439
1440 bool
1441 Program::makeFromNIR(struct nv50_ir_prog_info *info)
1442 {
1443 nir_shader *nir = (nir_shader*)info->bin.source;
1444 Converter converter(this, nir, info);
1445 bool result = converter.run();
1446 if (!result)
1447 return result;
1448 LoweringHelper lowering;
1449 lowering.run(this);
1450 tlsSize = info->bin.tlsSpace;
1451 return result;
1452 }
1453
1454 } // namespace nv50_ir