src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

   1 /*
   2  * Copyright 2017 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Karol Herbst <kherbst@redhat.com>
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26
  27 #include "util/u_debug.h"
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_from_common.h"
  31 #include "codegen/nv50_ir_lowering_helper.h"
  32 #include "codegen/nv50_ir_util.h"
  33 #include "tgsi/tgsi_from_mesa.h"
  34
  35 #if __cplusplus >= 201103L
  36 #include <unordered_map>
  37 #else
  38 #include <tr1/unordered_map>
  39 #endif
  40 #include <cstring>
  41 #include <list>
  42 #include <vector>
  43
  44 namespace {
  45
  46 #if __cplusplus >= 201103L
  47 using std::hash;
  48 using std::unordered_map;
  49 #else
  50 using std::tr1::hash;
  51 using std::tr1::unordered_map;
  52 #endif
  53
  54 using namespace nv50_ir;
  55
  56 int
  57 type_size(const struct glsl_type *type, bool bindless)
  58 {
  59    return glsl_count_attribute_slots(type, false);
  60 }
  61
  62 class Converter : public ConverterCommon
  63 {
  64 public:
  65    Converter(Program *, nir_shader *, nv50_ir_prog_info *);
  66
  67    bool run();
  68 private:
  69    typedef std::vector<LValue*> LValues;
  70    typedef unordered_map<unsigned, LValues> NirDefMap;
  71    typedef unordered_map<unsigned, nir_load_const_instr*> ImmediateMap;
  72    typedef unordered_map<unsigned, uint32_t> NirArrayLMemOffsets;
  73    typedef unordered_map<unsigned, BasicBlock*> NirBlockMap;
  74
  75    CacheMode convert(enum gl_access_qualifier);
  76    TexTarget convert(glsl_sampler_dim, bool isArray, bool isShadow);
  77    LValues& convert(nir_alu_dest *);
  78    BasicBlock* convert(nir_block *);
  79    LValues& convert(nir_dest *);
  80    SVSemantic convert(nir_intrinsic_op);
  81    Value* convert(nir_load_const_instr*, uint8_t);
  82    LValues& convert(nir_register *);
  83    LValues& convert(nir_ssa_def *);
  84
  85    Value* getSrc(nir_alu_src *, uint8_t component = 0);
  86    Value* getSrc(nir_register *, uint8_t);
  87    Value* getSrc(nir_src *, uint8_t, bool indirect = false);
  88    Value* getSrc(nir_ssa_def *, uint8_t);
  89
  90    // returned value is the constant part of the given source (either the
  91    // nir_src or the selected source component of an intrinsic). Even though
  92    // this is mostly an optimization to be able to skip indirects in a few
  93    // cases, sometimes we require immediate values or set some fileds on
  94    // instructions (e.g. tex) in order for codegen to consume those.
  95    // If the found value has not a constant part, the Value gets returned
  96    // through the Value parameter.
  97    uint32_t getIndirect(nir_src *, uint8_t, Value *&);
  98    // isScalar indicates that the addressing is scalar, vec4 addressing is
  99    // assumed otherwise
 100    uint32_t getIndirect(nir_intrinsic_instr *, uint8_t s, uint8_t c, Value *&,
 101                         bool isScalar = false);
 102
 103    uint32_t getSlotAddress(nir_intrinsic_instr *, uint8_t idx, uint8_t slot);
 104
 105    void setInterpolate(nv50_ir_varying *,
 106                        uint8_t,
 107                        bool centroid,
 108                        unsigned semantics);
 109
 110    Instruction *loadFrom(DataFile, uint8_t, DataType, Value *def, uint32_t base,
 111                          uint8_t c, Value *indirect0 = NULL,
 112                          Value *indirect1 = NULL, bool patch = false);
 113    void storeTo(nir_intrinsic_instr *, DataFile, operation, DataType,
 114                 Value *src, uint8_t idx, uint8_t c, Value *indirect0 = NULL,
 115                 Value *indirect1 = NULL);
 116
 117    bool isFloatType(nir_alu_type);
 118    bool isSignedType(nir_alu_type);
 119    bool isResultFloat(nir_op);
 120    bool isResultSigned(nir_op);
 121
 122    DataType getDType(nir_alu_instr *);
 123    DataType getDType(nir_intrinsic_instr *);
 124    DataType getDType(nir_intrinsic_instr *, bool isSigned);
 125    DataType getDType(nir_op, uint8_t);
 126
 127    std::vector<DataType> getSTypes(nir_alu_instr *);
 128    DataType getSType(nir_src &, bool isFloat, bool isSigned);
 129
 130    operation getOperation(nir_intrinsic_op);
 131    operation getOperation(nir_op);
 132    operation getOperation(nir_texop);
 133    operation preOperationNeeded(nir_op);
 134
 135    int getSubOp(nir_intrinsic_op);
 136    int getSubOp(nir_op);
 137
 138    CondCode getCondCode(nir_op);
 139
 140    bool assignSlots();
 141    bool parseNIR();
 142
 143    bool visit(nir_alu_instr *);
 144    bool visit(nir_block *);
 145    bool visit(nir_cf_node *);
 146    bool visit(nir_function *);
 147    bool visit(nir_if *);
 148    bool visit(nir_instr *);
 149    bool visit(nir_intrinsic_instr *);
 150    bool visit(nir_jump_instr *);
 151    bool visit(nir_load_const_instr*);
 152    bool visit(nir_loop *);
 153    bool visit(nir_ssa_undef_instr *);
 154    bool visit(nir_tex_instr *);
 155
 156    // tex stuff
 157    Value* applyProjection(Value *src, Value *proj);
 158    unsigned int getNIRArgCount(TexInstruction::Target&);
 159
 160    nir_shader *nir;
 161
 162    NirDefMap ssaDefs;
 163    NirDefMap regDefs;
 164    ImmediateMap immediates;
 165    NirArrayLMemOffsets regToLmemOffset;
 166    NirBlockMap blocks;
 167    unsigned int curLoopDepth;
 168    unsigned int curIfDepth;
 169
 170    BasicBlock *exit;
 171    Value *zero;
 172    Instruction *immInsertPos;
 173
 174    int clipVertexOutput;
 175
 176    union {
 177       struct {
 178          Value *position;
 179       } fp;
 180    };
 181 };
 182
 183 Converter::Converter(Program *prog, nir_shader *nir, nv50_ir_prog_info *info)
 184    : ConverterCommon(prog, info),
 185      nir(nir),
 186      curLoopDepth(0),
 187      curIfDepth(0),
 188      clipVertexOutput(-1)
 189 {
 190    zero = mkImm((uint32_t)0);
 191 }
 192
 193 BasicBlock *
 194 Converter::convert(nir_block *block)
 195 {
 196    NirBlockMap::iterator it = blocks.find(block->index);
 197    if (it != blocks.end())
 198       return it->second;
 199
 200    BasicBlock *bb = new BasicBlock(func);
 201    blocks[block->index] = bb;
 202    return bb;
 203 }
 204
 205 bool
 206 Converter::isFloatType(nir_alu_type type)
 207 {
 208    return nir_alu_type_get_base_type(type) == nir_type_float;
 209 }
 210
 211 bool
 212 Converter::isSignedType(nir_alu_type type)
 213 {
 214    return nir_alu_type_get_base_type(type) == nir_type_int;
 215 }
 216
 217 bool
 218 Converter::isResultFloat(nir_op op)
 219 {
 220    const nir_op_info &info = nir_op_infos[op];
 221    if (info.output_type != nir_type_invalid)
 222       return isFloatType(info.output_type);
 223
 224    ERROR("isResultFloat not implemented for %s\n", nir_op_infos[op].name);
 225    assert(false);
 226    return true;
 227 }
 228
 229 bool
 230 Converter::isResultSigned(nir_op op)
 231 {
 232    switch (op) {
 233    // there is no umul and we get wrong results if we treat all muls as signed
 234    case nir_op_imul:
 235    case nir_op_inot:
 236       return false;
 237    default:
 238       const nir_op_info &info = nir_op_infos[op];
 239       if (info.output_type != nir_type_invalid)
 240          return isSignedType(info.output_type);
 241       ERROR("isResultSigned not implemented for %s\n", nir_op_infos[op].name);
 242       assert(false);
 243       return true;
 244    }
 245 }
 246
 247 DataType
 248 Converter::getDType(nir_alu_instr *insn)
 249 {
 250    if (insn->dest.dest.is_ssa)
 251       return getDType(insn->op, insn->dest.dest.ssa.bit_size);
 252    else
 253       return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
 254 }
 255
 256 DataType
 257 Converter::getDType(nir_intrinsic_instr *insn)
 258 {
 259    bool isSigned;
 260    switch (insn->intrinsic) {
 261    case nir_intrinsic_shared_atomic_imax:
 262    case nir_intrinsic_shared_atomic_imin:
 263    case nir_intrinsic_ssbo_atomic_imax:
 264    case nir_intrinsic_ssbo_atomic_imin:
 265       isSigned = true;
 266       break;
 267    default:
 268       isSigned = false;
 269       break;
 270    }
 271
 272    return getDType(insn, isSigned);
 273 }
 274
 275 DataType
 276 Converter::getDType(nir_intrinsic_instr *insn, bool isSigned)
 277 {
 278    if (insn->dest.is_ssa)
 279       return typeOfSize(insn->dest.ssa.bit_size / 8, false, isSigned);
 280    else
 281       return typeOfSize(insn->dest.reg.reg->bit_size / 8, false, isSigned);
 282 }
 283
 284 DataType
 285 Converter::getDType(nir_op op, uint8_t bitSize)
 286 {
 287    DataType ty = typeOfSize(bitSize / 8, isResultFloat(op), isResultSigned(op));
 288    if (ty == TYPE_NONE) {
 289       ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos[op].name, bitSize);
 290       assert(false);
 291    }
 292    return ty;
 293 }
 294
 295 std::vector<DataType>
 296 Converter::getSTypes(nir_alu_instr *insn)
 297 {
 298    const nir_op_info &info = nir_op_infos[insn->op];
 299    std::vector<DataType> res(info.num_inputs);
 300
 301    for (uint8_t i = 0; i < info.num_inputs; ++i) {
 302       if (info.input_types[i] != nir_type_invalid) {
 303          res[i] = getSType(insn->src[i].src, isFloatType(info.input_types[i]), isSignedType(info.input_types[i]));
 304       } else {
 305          ERROR("getSType not implemented for %s idx %u\n", info.name, i);
 306          assert(false);
 307          res[i] = TYPE_NONE;
 308          break;
 309       }
 310    }
 311
 312    return res;
 313 }
 314
 315 DataType
 316 Converter::getSType(nir_src &src, bool isFloat, bool isSigned)
 317 {
 318    uint8_t bitSize;
 319    if (src.is_ssa)
 320       bitSize = src.ssa->bit_size;
 321    else
 322       bitSize = src.reg.reg->bit_size;
 323
 324    DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned);
 325    if (ty == TYPE_NONE) {
 326       const char *str;
 327       if (isFloat)
 328          str = "float";
 329       else if (isSigned)
 330          str = "int";
 331       else
 332          str = "uint";
 333       ERROR("couldn't get Type for %s with bitSize %u\n", str, bitSize);
 334       assert(false);
 335    }
 336    return ty;
 337 }
 338
 339 operation
 340 Converter::getOperation(nir_op op)
 341 {
 342    switch (op) {
 343    // basic ops with float and int variants
 344    case nir_op_fabs:
 345    case nir_op_iabs:
 346       return OP_ABS;
 347    case nir_op_fadd:
 348    case nir_op_iadd:
 349       return OP_ADD;
 350    case nir_op_iand:
 351       return OP_AND;
 352    case nir_op_ifind_msb:
 353    case nir_op_ufind_msb:
 354       return OP_BFIND;
 355    case nir_op_fceil:
 356       return OP_CEIL;
 357    case nir_op_fcos:
 358       return OP_COS;
 359    case nir_op_f2f32:
 360    case nir_op_f2f64:
 361    case nir_op_f2i32:
 362    case nir_op_f2i64:
 363    case nir_op_f2u32:
 364    case nir_op_f2u64:
 365    case nir_op_i2f32:
 366    case nir_op_i2f64:
 367    case nir_op_i2i32:
 368    case nir_op_i2i64:
 369    case nir_op_u2f32:
 370    case nir_op_u2f64:
 371    case nir_op_u2u32:
 372    case nir_op_u2u64:
 373       return OP_CVT;
 374    case nir_op_fddx:
 375    case nir_op_fddx_coarse:
 376    case nir_op_fddx_fine:
 377       return OP_DFDX;
 378    case nir_op_fddy:
 379    case nir_op_fddy_coarse:
 380    case nir_op_fddy_fine:
 381       return OP_DFDY;
 382    case nir_op_fdiv:
 383    case nir_op_idiv:
 384    case nir_op_udiv:
 385       return OP_DIV;
 386    case nir_op_fexp2:
 387       return OP_EX2;
 388    case nir_op_ffloor:
 389       return OP_FLOOR;
 390    case nir_op_ffma:
 391       return OP_FMA;
 392    case nir_op_flog2:
 393       return OP_LG2;
 394    case nir_op_fmax:
 395    case nir_op_imax:
 396    case nir_op_umax:
 397       return OP_MAX;
 398    case nir_op_pack_64_2x32_split:
 399       return OP_MERGE;
 400    case nir_op_fmin:
 401    case nir_op_imin:
 402    case nir_op_umin:
 403       return OP_MIN;
 404    case nir_op_fmod:
 405    case nir_op_imod:
 406    case nir_op_umod:
 407    case nir_op_frem:
 408    case nir_op_irem:
 409       return OP_MOD;
 410    case nir_op_fmul:
 411    case nir_op_imul:
 412    case nir_op_imul_high:
 413    case nir_op_umul_high:
 414       return OP_MUL;
 415    case nir_op_fneg:
 416    case nir_op_ineg:
 417       return OP_NEG;
 418    case nir_op_inot:
 419       return OP_NOT;
 420    case nir_op_ior:
 421       return OP_OR;
 422    case nir_op_fpow:
 423       return OP_POW;
 424    case nir_op_frcp:
 425       return OP_RCP;
 426    case nir_op_frsq:
 427       return OP_RSQ;
 428    case nir_op_fsat:
 429       return OP_SAT;
 430    case nir_op_feq32:
 431    case nir_op_ieq32:
 432    case nir_op_fge32:
 433    case nir_op_ige32:
 434    case nir_op_uge32:
 435    case nir_op_flt32:
 436    case nir_op_ilt32:
 437    case nir_op_ult32:
 438    case nir_op_fne32:
 439    case nir_op_ine32:
 440       return OP_SET;
 441    case nir_op_ishl:
 442       return OP_SHL;
 443    case nir_op_ishr:
 444    case nir_op_ushr:
 445       return OP_SHR;
 446    case nir_op_fsin:
 447       return OP_SIN;
 448    case nir_op_fsqrt:
 449       return OP_SQRT;
 450    case nir_op_ftrunc:
 451       return OP_TRUNC;
 452    case nir_op_ixor:
 453       return OP_XOR;
 454    default:
 455       ERROR("couldn't get operation for op %s\n", nir_op_infos[op].name);
 456       assert(false);
 457       return OP_NOP;
 458    }
 459 }
 460
 461 operation
 462 Converter::getOperation(nir_texop op)
 463 {
 464    switch (op) {
 465    case nir_texop_tex:
 466       return OP_TEX;
 467    case nir_texop_lod:
 468       return OP_TXLQ;
 469    case nir_texop_txb:
 470       return OP_TXB;
 471    case nir_texop_txd:
 472       return OP_TXD;
 473    case nir_texop_txf:
 474    case nir_texop_txf_ms:
 475       return OP_TXF;
 476    case nir_texop_tg4:
 477       return OP_TXG;
 478    case nir_texop_txl:
 479       return OP_TXL;
 480    case nir_texop_query_levels:
 481    case nir_texop_texture_samples:
 482    case nir_texop_txs:
 483       return OP_TXQ;
 484    default:
 485       ERROR("couldn't get operation for nir_texop %u\n", op);
 486       assert(false);
 487       return OP_NOP;
 488    }
 489 }
 490
 491 operation
 492 Converter::getOperation(nir_intrinsic_op op)
 493 {
 494    switch (op) {
 495    case nir_intrinsic_emit_vertex:
 496       return OP_EMIT;
 497    case nir_intrinsic_end_primitive:
 498       return OP_RESTART;
 499    case nir_intrinsic_bindless_image_atomic_add:
 500    case nir_intrinsic_image_atomic_add:
 501    case nir_intrinsic_bindless_image_atomic_and:
 502    case nir_intrinsic_image_atomic_and:
 503    case nir_intrinsic_bindless_image_atomic_comp_swap:
 504    case nir_intrinsic_image_atomic_comp_swap:
 505    case nir_intrinsic_bindless_image_atomic_exchange:
 506    case nir_intrinsic_image_atomic_exchange:
 507    case nir_intrinsic_bindless_image_atomic_imax:
 508    case nir_intrinsic_image_atomic_imax:
 509    case nir_intrinsic_bindless_image_atomic_umax:
 510    case nir_intrinsic_image_atomic_umax:
 511    case nir_intrinsic_bindless_image_atomic_imin:
 512    case nir_intrinsic_image_atomic_imin:
 513    case nir_intrinsic_bindless_image_atomic_umin:
 514    case nir_intrinsic_image_atomic_umin:
 515    case nir_intrinsic_bindless_image_atomic_or:
 516    case nir_intrinsic_image_atomic_or:
 517    case nir_intrinsic_bindless_image_atomic_xor:
 518    case nir_intrinsic_image_atomic_xor:
 519    case nir_intrinsic_bindless_image_atomic_inc_wrap:
 520    case nir_intrinsic_image_atomic_inc_wrap:
 521    case nir_intrinsic_bindless_image_atomic_dec_wrap:
 522    case nir_intrinsic_image_atomic_dec_wrap:
 523       return OP_SUREDP;
 524    case nir_intrinsic_bindless_image_load:
 525    case nir_intrinsic_image_load:
 526       return OP_SULDP;
 527    case nir_intrinsic_bindless_image_samples:
 528    case nir_intrinsic_image_samples:
 529    case nir_intrinsic_bindless_image_size:
 530    case nir_intrinsic_image_size:
 531       return OP_SUQ;
 532    case nir_intrinsic_bindless_image_store:
 533    case nir_intrinsic_image_store:
 534       return OP_SUSTP;
 535    default:
 536       ERROR("couldn't get operation for nir_intrinsic_op %u\n", op);
 537       assert(false);
 538       return OP_NOP;
 539    }
 540 }
 541
 542 operation
 543 Converter::preOperationNeeded(nir_op op)
 544 {
 545    switch (op) {
 546    case nir_op_fcos:
 547    case nir_op_fsin:
 548       return OP_PRESIN;
 549    default:
 550       return OP_NOP;
 551    }
 552 }
 553
 554 int
 555 Converter::getSubOp(nir_op op)
 556 {
 557    switch (op) {
 558    case nir_op_imul_high:
 559    case nir_op_umul_high:
 560       return NV50_IR_SUBOP_MUL_HIGH;
 561    case nir_op_ishl:
 562    case nir_op_ishr:
 563    case nir_op_ushr:
 564       return NV50_IR_SUBOP_SHIFT_WRAP;
 565    default:
 566       return 0;
 567    }
 568 }
 569
 570 int
 571 Converter::getSubOp(nir_intrinsic_op op)
 572 {
 573    switch (op) {
 574    case nir_intrinsic_bindless_image_atomic_add:
 575    case nir_intrinsic_global_atomic_add:
 576    case nir_intrinsic_image_atomic_add:
 577    case nir_intrinsic_shared_atomic_add:
 578    case nir_intrinsic_ssbo_atomic_add:
 579       return  NV50_IR_SUBOP_ATOM_ADD;
 580    case nir_intrinsic_bindless_image_atomic_and:
 581    case nir_intrinsic_global_atomic_and:
 582    case nir_intrinsic_image_atomic_and:
 583    case nir_intrinsic_shared_atomic_and:
 584    case nir_intrinsic_ssbo_atomic_and:
 585       return  NV50_IR_SUBOP_ATOM_AND;
 586    case nir_intrinsic_bindless_image_atomic_comp_swap:
 587    case nir_intrinsic_global_atomic_comp_swap:
 588    case nir_intrinsic_image_atomic_comp_swap:
 589    case nir_intrinsic_shared_atomic_comp_swap:
 590    case nir_intrinsic_ssbo_atomic_comp_swap:
 591       return  NV50_IR_SUBOP_ATOM_CAS;
 592    case nir_intrinsic_bindless_image_atomic_exchange:
 593    case nir_intrinsic_global_atomic_exchange:
 594    case nir_intrinsic_image_atomic_exchange:
 595    case nir_intrinsic_shared_atomic_exchange:
 596    case nir_intrinsic_ssbo_atomic_exchange:
 597       return  NV50_IR_SUBOP_ATOM_EXCH;
 598    case nir_intrinsic_bindless_image_atomic_or:
 599    case nir_intrinsic_global_atomic_or:
 600    case nir_intrinsic_image_atomic_or:
 601    case nir_intrinsic_shared_atomic_or:
 602    case nir_intrinsic_ssbo_atomic_or:
 603       return  NV50_IR_SUBOP_ATOM_OR;
 604    case nir_intrinsic_bindless_image_atomic_imax:
 605    case nir_intrinsic_bindless_image_atomic_umax:
 606    case nir_intrinsic_global_atomic_imax:
 607    case nir_intrinsic_global_atomic_umax:
 608    case nir_intrinsic_image_atomic_imax:
 609    case nir_intrinsic_image_atomic_umax:
 610    case nir_intrinsic_shared_atomic_imax:
 611    case nir_intrinsic_shared_atomic_umax:
 612    case nir_intrinsic_ssbo_atomic_imax:
 613    case nir_intrinsic_ssbo_atomic_umax:
 614       return  NV50_IR_SUBOP_ATOM_MAX;
 615    case nir_intrinsic_bindless_image_atomic_imin:
 616    case nir_intrinsic_bindless_image_atomic_umin:
 617    case nir_intrinsic_global_atomic_imin:
 618    case nir_intrinsic_global_atomic_umin:
 619    case nir_intrinsic_image_atomic_imin:
 620    case nir_intrinsic_image_atomic_umin:
 621    case nir_intrinsic_shared_atomic_imin:
 622    case nir_intrinsic_shared_atomic_umin:
 623    case nir_intrinsic_ssbo_atomic_imin:
 624    case nir_intrinsic_ssbo_atomic_umin:
 625       return  NV50_IR_SUBOP_ATOM_MIN;
 626    case nir_intrinsic_bindless_image_atomic_xor:
 627    case nir_intrinsic_global_atomic_xor:
 628    case nir_intrinsic_image_atomic_xor:
 629    case nir_intrinsic_shared_atomic_xor:
 630    case nir_intrinsic_ssbo_atomic_xor:
 631       return  NV50_IR_SUBOP_ATOM_XOR;
 632    case nir_intrinsic_bindless_image_atomic_inc_wrap:
 633    case nir_intrinsic_image_atomic_inc_wrap:
 634       return NV50_IR_SUBOP_ATOM_INC;
 635    case nir_intrinsic_bindless_image_atomic_dec_wrap:
 636    case nir_intrinsic_image_atomic_dec_wrap:
 637       return NV50_IR_SUBOP_ATOM_DEC;
 638
 639    case nir_intrinsic_group_memory_barrier:
 640    case nir_intrinsic_memory_barrier:
 641    case nir_intrinsic_memory_barrier_buffer:
 642    case nir_intrinsic_memory_barrier_image:
 643       return NV50_IR_SUBOP_MEMBAR(M, GL);
 644    case nir_intrinsic_memory_barrier_shared:
 645       return NV50_IR_SUBOP_MEMBAR(M, CTA);
 646
 647    case nir_intrinsic_vote_all:
 648       return NV50_IR_SUBOP_VOTE_ALL;
 649    case nir_intrinsic_vote_any:
 650       return NV50_IR_SUBOP_VOTE_ANY;
 651    case nir_intrinsic_vote_ieq:
 652       return NV50_IR_SUBOP_VOTE_UNI;
 653    default:
 654       return 0;
 655    }
 656 }
 657
 658 CondCode
 659 Converter::getCondCode(nir_op op)
 660 {
 661    switch (op) {
 662    case nir_op_feq32:
 663    case nir_op_ieq32:
 664       return CC_EQ;
 665    case nir_op_fge32:
 666    case nir_op_ige32:
 667    case nir_op_uge32:
 668       return CC_GE;
 669    case nir_op_flt32:
 670    case nir_op_ilt32:
 671    case nir_op_ult32:
 672       return CC_LT;
 673    case nir_op_fne32:
 674       return CC_NEU;
 675    case nir_op_ine32:
 676       return CC_NE;
 677    default:
 678       ERROR("couldn't get CondCode for op %s\n", nir_op_infos[op].name);
 679       assert(false);
 680       return CC_FL;
 681    }
 682 }
 683
 684 Converter::LValues&
 685 Converter::convert(nir_alu_dest *dest)
 686 {
 687    return convert(&dest->dest);
 688 }
 689
 690 Converter::LValues&
 691 Converter::convert(nir_dest *dest)
 692 {
 693    if (dest->is_ssa)
 694       return convert(&dest->ssa);
 695    if (dest->reg.indirect) {
 696       ERROR("no support for indirects.");
 697       assert(false);
 698    }
 699    return convert(dest->reg.reg);
 700 }
 701
 702 Converter::LValues&
 703 Converter::convert(nir_register *reg)
 704 {
 705    NirDefMap::iterator it = regDefs.find(reg->index);
 706    if (it != regDefs.end())
 707       return it->second;
 708
 709    LValues newDef(reg->num_components);
 710    for (uint8_t i = 0; i < reg->num_components; i++)
 711       newDef[i] = getScratch(std::max(4, reg->bit_size / 8));
 712    return regDefs[reg->index] = newDef;
 713 }
 714
 715 Converter::LValues&
 716 Converter::convert(nir_ssa_def *def)
 717 {
 718    NirDefMap::iterator it = ssaDefs.find(def->index);
 719    if (it != ssaDefs.end())
 720       return it->second;
 721
 722    LValues newDef(def->num_components);
 723    for (uint8_t i = 0; i < def->num_components; i++)
 724       newDef[i] = getSSA(std::max(4, def->bit_size / 8));
 725    return ssaDefs[def->index] = newDef;
 726 }
 727
 728 Value*
 729 Converter::getSrc(nir_alu_src *src, uint8_t component)
 730 {
 731    if (src->abs || src->negate) {
 732       ERROR("modifiers currently not supported on nir_alu_src\n");
 733       assert(false);
 734    }
 735    return getSrc(&src->src, src->swizzle[component]);
 736 }
 737
 738 Value*
 739 Converter::getSrc(nir_register *reg, uint8_t idx)
 740 {
 741    NirDefMap::iterator it = regDefs.find(reg->index);
 742    if (it == regDefs.end())
 743       return convert(reg)[idx];
 744    return it->second[idx];
 745 }
 746
 747 Value*
 748 Converter::getSrc(nir_src *src, uint8_t idx, bool indirect)
 749 {
 750    if (src->is_ssa)
 751       return getSrc(src->ssa, idx);
 752
 753    if (src->reg.indirect) {
 754       if (indirect)
 755          return getSrc(src->reg.indirect, idx);
 756       ERROR("no support for indirects.");
 757       assert(false);
 758       return NULL;
 759    }
 760
 761    return getSrc(src->reg.reg, idx);
 762 }
 763
 764 Value*
 765 Converter::getSrc(nir_ssa_def *src, uint8_t idx)
 766 {
 767    ImmediateMap::iterator iit = immediates.find(src->index);
 768    if (iit != immediates.end())
 769       return convert((*iit).second, idx);
 770
 771    NirDefMap::iterator it = ssaDefs.find(src->index);
 772    if (it == ssaDefs.end()) {
 773       ERROR("SSA value %u not found\n", src->index);
 774       assert(false);
 775       return NULL;
 776    }
 777    return it->second[idx];
 778 }
 779
 780 uint32_t
 781 Converter::getIndirect(nir_src *src, uint8_t idx, Value *&indirect)
 782 {
 783    nir_const_value *offset = nir_src_as_const_value(*src);
 784
 785    if (offset) {
 786       indirect = NULL;
 787       return offset[0].u32;
 788    }
 789
 790    indirect = getSrc(src, idx, true);
 791    return 0;
 792 }
 793
 794 uint32_t
 795 Converter::getIndirect(nir_intrinsic_instr *insn, uint8_t s, uint8_t c, Value *&indirect, bool isScalar)
 796 {
 797    int32_t idx = nir_intrinsic_base(insn) + getIndirect(&insn->src[s], c, indirect);
 798    if (indirect && !isScalar)
 799       indirect = mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), indirect, loadImm(NULL, 4));
 800    return idx;
 801 }
 802
 803 static void
 804 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot, unsigned *name, unsigned *index)
 805 {
 806    assert(name && index);
 807
 808    if (slot >= VERT_ATTRIB_MAX) {
 809       ERROR("invalid varying slot %u\n", slot);
 810       assert(false);
 811       return;
 812    }
 813
 814    if (slot >= VERT_ATTRIB_GENERIC0 &&
 815        slot < VERT_ATTRIB_GENERIC0 + VERT_ATTRIB_GENERIC_MAX) {
 816       *name = TGSI_SEMANTIC_GENERIC;
 817       *index = slot - VERT_ATTRIB_GENERIC0;
 818       return;
 819    }
 820
 821    if (slot >= VERT_ATTRIB_TEX0 &&
 822        slot < VERT_ATTRIB_TEX0 + VERT_ATTRIB_TEX_MAX) {
 823       *name = TGSI_SEMANTIC_TEXCOORD;
 824       *index = slot - VERT_ATTRIB_TEX0;
 825       return;
 826    }
 827
 828    switch (slot) {
 829    case VERT_ATTRIB_COLOR0:
 830       *name = TGSI_SEMANTIC_COLOR;
 831       *index = 0;
 832       break;
 833    case VERT_ATTRIB_COLOR1:
 834       *name = TGSI_SEMANTIC_COLOR;
 835       *index = 1;
 836       break;
 837    case VERT_ATTRIB_EDGEFLAG:
 838       *name = TGSI_SEMANTIC_EDGEFLAG;
 839       *index = 0;
 840       break;
 841    case VERT_ATTRIB_FOG:
 842       *name = TGSI_SEMANTIC_FOG;
 843       *index = 0;
 844       break;
 845    case VERT_ATTRIB_NORMAL:
 846       *name = TGSI_SEMANTIC_NORMAL;
 847       *index = 0;
 848       break;
 849    case VERT_ATTRIB_POS:
 850       *name = TGSI_SEMANTIC_POSITION;
 851       *index = 0;
 852       break;
 853    case VERT_ATTRIB_POINT_SIZE:
 854       *name = TGSI_SEMANTIC_PSIZE;
 855       *index = 0;
 856       break;
 857    default:
 858       ERROR("unknown vert attrib slot %u\n", slot);
 859       assert(false);
 860       break;
 861    }
 862 }
 863
 864 void
 865 Converter::setInterpolate(nv50_ir_varying *var,
 866                           uint8_t mode,
 867                           bool centroid,
 868                           unsigned semantic)
 869 {
 870    switch (mode) {
 871    case INTERP_MODE_FLAT:
 872       var->flat = 1;
 873       break;
 874    case INTERP_MODE_NONE:
 875       if (semantic == TGSI_SEMANTIC_COLOR)
 876          var->sc = 1;
 877       else if (semantic == TGSI_SEMANTIC_POSITION)
 878          var->linear = 1;
 879       break;
 880    case INTERP_MODE_NOPERSPECTIVE:
 881       var->linear = 1;
 882       break;
 883    case INTERP_MODE_SMOOTH:
 884       break;
 885    }
 886    var->centroid = centroid;
 887 }
 888
 889 static uint16_t
 890 calcSlots(const glsl_type *type, Program::Type stage, const shader_info &info,
 891           bool input, const nir_variable *var)
 892 {
 893    if (!type->is_array())
 894       return type->count_attribute_slots(false);
 895
 896    uint16_t slots;
 897    switch (stage) {
 898    case Program::TYPE_GEOMETRY:
 899       slots = type->count_attribute_slots(false);
 900       if (input)
 901          slots /= info.gs.vertices_in;
 902       break;
 903    case Program::TYPE_TESSELLATION_CONTROL:
 904    case Program::TYPE_TESSELLATION_EVAL:
 905       // remove first dimension
 906       if (var->data.patch || (!input && stage == Program::TYPE_TESSELLATION_EVAL))
 907          slots = type->count_attribute_slots(false);
 908       else
 909          slots = type->fields.array->count_attribute_slots(false);
 910       break;
 911    default:
 912       slots = type->count_attribute_slots(false);
 913       break;
 914    }
 915
 916    return slots;
 917 }
 918
 919 static uint8_t
 920 getMaskForType(const glsl_type *type, uint8_t slot) {
 921    uint16_t comp = type->without_array()->components();
 922    comp = comp ? comp : 4;
 923
 924    if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
 925       comp *= 2;
 926       if (comp > 4) {
 927          if (slot % 2)
 928             comp -= 4;
 929          else
 930             comp = 4;
 931       }
 932    }
 933
 934    return (1 << comp) - 1;
 935 }
 936
 937 bool Converter::assignSlots() {
 938    unsigned name;
 939    unsigned index;
 940
 941    info->io.viewportId = -1;
 942    info->numInputs = 0;
 943    info->numOutputs = 0;
 944    info->numSysVals = 0;
 945
 946    for (uint8_t i = 0; i < SYSTEM_VALUE_MAX; ++i) {
 947       if (!(nir->info.system_values_read & 1ull << i))
 948          continue;
 949
 950       info->sv[info->numSysVals].sn = tgsi_get_sysval_semantic(i);
 951       info->sv[info->numSysVals].si = 0;
 952       info->sv[info->numSysVals].input = 0; // TODO inferSysValDirection(sn);
 953
 954       switch (i) {
 955       case SYSTEM_VALUE_INSTANCE_ID:
 956          info->io.instanceId = info->numSysVals;
 957          break;
 958       case SYSTEM_VALUE_TESS_LEVEL_INNER:
 959       case SYSTEM_VALUE_TESS_LEVEL_OUTER:
 960          info->sv[info->numSysVals].patch = 1;
 961          break;
 962       case SYSTEM_VALUE_VERTEX_ID:
 963          info->io.vertexId = info->numSysVals;
 964          break;
 965       default:
 966          break;
 967       }
 968
 969       info->numSysVals += 1;
 970    }
 971
 972    if (prog->getType() == Program::TYPE_COMPUTE)
 973       return true;
 974
 975    nir_foreach_variable(var, &nir->inputs) {
 976       const glsl_type *type = var->type;
 977       int slot = var->data.location;
 978       uint16_t slots = calcSlots(type, prog->getType(), nir->info, true, var);
 979       uint32_t vary = var->data.driver_location;
 980
 981       assert(vary + slots <= PIPE_MAX_SHADER_INPUTS);
 982
 983       switch(prog->getType()) {
 984       case Program::TYPE_FRAGMENT:
 985          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
 986                                       &name, &index);
 987          for (uint16_t i = 0; i < slots; ++i) {
 988             setInterpolate(&info->in[vary + i], var->data.interpolation,
 989                            var->data.centroid | var->data.sample, name);
 990          }
 991          break;
 992       case Program::TYPE_GEOMETRY:
 993          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
 994                                       &name, &index);
 995          break;
 996       case Program::TYPE_TESSELLATION_CONTROL:
 997       case Program::TYPE_TESSELLATION_EVAL:
 998          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
 999                                       &name, &index);
1000          if (var->data.patch && name == TGSI_SEMANTIC_PATCH)
1001             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1002          break;
1003       case Program::TYPE_VERTEX:
1004          if (slot >= VERT_ATTRIB_GENERIC0)
1005             slot = VERT_ATTRIB_GENERIC0 + vary;
1006          vert_attrib_to_tgsi_semantic((gl_vert_attrib)slot, &name, &index);
1007          switch (name) {
1008          case TGSI_SEMANTIC_EDGEFLAG:
1009             info->io.edgeFlagIn = vary;
1010             break;
1011          default:
1012             break;
1013          }
1014          break;
1015       default:
1016          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1017          return false;
1018       }
1019
1020       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1021          nv50_ir_varying *v = &info->in[vary];
1022
1023          v->patch = var->data.patch;
1024          v->sn = name;
1025          v->si = index + i;
1026          v->mask |= getMaskForType(type, i) << var->data.location_frac;
1027       }
1028       info->numInputs = std::max<uint8_t>(info->numInputs, vary);
1029    }
1030
1031    nir_foreach_variable(var, &nir->outputs) {
1032       const glsl_type *type = var->type;
1033       int slot = var->data.location;
1034       uint16_t slots = calcSlots(type, prog->getType(), nir->info, false, var);
1035       uint32_t vary = var->data.driver_location;
1036
1037       assert(vary < PIPE_MAX_SHADER_OUTPUTS);
1038
1039       switch(prog->getType()) {
1040       case Program::TYPE_FRAGMENT:
1041          tgsi_get_gl_frag_result_semantic((gl_frag_result)slot, &name, &index);
1042          switch (name) {
1043          case TGSI_SEMANTIC_COLOR:
1044             if (!var->data.fb_fetch_output)
1045                info->prop.fp.numColourResults++;
1046
1047             if (var->data.location == FRAG_RESULT_COLOR &&
1048                 nir->info.outputs_written & BITFIELD64_BIT(var->data.location))
1049                info->prop.fp.separateFragData = true;
1050
1051             // sometimes we get FRAG_RESULT_DATAX with data.index 0
1052             // sometimes we get FRAG_RESULT_DATA0 with data.index X
1053             index = index == 0 ? var->data.index : index;
1054             break;
1055          case TGSI_SEMANTIC_POSITION:
1056             info->io.fragDepth = vary;
1057             info->prop.fp.writesDepth = true;
1058             break;
1059          case TGSI_SEMANTIC_SAMPLEMASK:
1060             info->io.sampleMask = vary;
1061             break;
1062          default:
1063             break;
1064          }
1065          break;
1066       case Program::TYPE_GEOMETRY:
1067       case Program::TYPE_TESSELLATION_CONTROL:
1068       case Program::TYPE_TESSELLATION_EVAL:
1069       case Program::TYPE_VERTEX:
1070          tgsi_get_gl_varying_semantic((gl_varying_slot)slot, true,
1071                                       &name, &index);
1072
1073          if (var->data.patch && name != TGSI_SEMANTIC_TESSINNER &&
1074              name != TGSI_SEMANTIC_TESSOUTER)
1075             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
1076
1077          switch (name) {
1078          case TGSI_SEMANTIC_CLIPDIST:
1079             info->io.genUserClip = -1;
1080             break;
1081          case TGSI_SEMANTIC_CLIPVERTEX:
1082             clipVertexOutput = vary;
1083             break;
1084          case TGSI_SEMANTIC_EDGEFLAG:
1085             info->io.edgeFlagOut = vary;
1086             break;
1087          case TGSI_SEMANTIC_POSITION:
1088             if (clipVertexOutput < 0)
1089                clipVertexOutput = vary;
1090             break;
1091          default:
1092             break;
1093          }
1094          break;
1095       default:
1096          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
1097          return false;
1098       }
1099
1100       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
1101          nv50_ir_varying *v = &info->out[vary];
1102          v->patch = var->data.patch;
1103          v->sn = name;
1104          v->si = index + i;
1105          v->mask |= getMaskForType(type, i) << var->data.location_frac;
1106
1107          if (nir->info.outputs_read & 1ull << slot)
1108             v->oread = 1;
1109       }
1110       info->numOutputs = std::max<uint8_t>(info->numOutputs, vary);
1111    }
1112
1113    if (info->io.genUserClip > 0) {
1114       info->io.clipDistances = info->io.genUserClip;
1115
1116       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1117
1118       for (unsigned int n = 0; n < nOut; ++n) {
1119          unsigned int i = info->numOutputs++;
1120          info->out[i].id = i;
1121          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1122          info->out[i].si = n;
1123          info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1124       }
1125    }
1126
1127    return info->assignSlots(info) == 0;
1128 }
1129
1130 uint32_t
1131 Converter::getSlotAddress(nir_intrinsic_instr *insn, uint8_t idx, uint8_t slot)
1132 {
1133    DataType ty;
1134    int offset = nir_intrinsic_component(insn);
1135    bool input;
1136
1137    if (nir_intrinsic_infos[insn->intrinsic].has_dest)
1138       ty = getDType(insn);
1139    else
1140       ty = getSType(insn->src[0], false, false);
1141
1142    switch (insn->intrinsic) {
1143    case nir_intrinsic_load_input:
1144    case nir_intrinsic_load_interpolated_input:
1145    case nir_intrinsic_load_per_vertex_input:
1146       input = true;
1147       break;
1148    case nir_intrinsic_load_output:
1149    case nir_intrinsic_load_per_vertex_output:
1150    case nir_intrinsic_store_output:
1151    case nir_intrinsic_store_per_vertex_output:
1152       input = false;
1153       break;
1154    default:
1155       ERROR("unknown intrinsic in getSlotAddress %s",
1156             nir_intrinsic_infos[insn->intrinsic].name);
1157       input = false;
1158       assert(false);
1159       break;
1160    }
1161
1162    if (typeSizeof(ty) == 8) {
1163       slot *= 2;
1164       slot += offset;
1165       if (slot >= 4) {
1166          idx += 1;
1167          slot -= 4;
1168       }
1169    } else {
1170       slot += offset;
1171    }
1172
1173    assert(slot < 4);
1174    assert(!input || idx < PIPE_MAX_SHADER_INPUTS);
1175    assert(input || idx < PIPE_MAX_SHADER_OUTPUTS);
1176
1177    const nv50_ir_varying *vary = input ? info->in : info->out;
1178    return vary[idx].slot[slot] * 4;
1179 }
1180
1181 Instruction *
1182 Converter::loadFrom(DataFile file, uint8_t i, DataType ty, Value *def,
1183                     uint32_t base, uint8_t c, Value *indirect0,
1184                     Value *indirect1, bool patch)
1185 {
1186    unsigned int tySize = typeSizeof(ty);
1187
1188    if (tySize == 8 &&
1189        (file == FILE_MEMORY_CONST || file == FILE_MEMORY_BUFFER || indirect0)) {
1190       Value *lo = getSSA();
1191       Value *hi = getSSA();
1192
1193       Instruction *loi =
1194          mkLoad(TYPE_U32, lo,
1195                 mkSymbol(file, i, TYPE_U32, base + c * tySize),
1196                 indirect0);
1197       loi->setIndirect(0, 1, indirect1);
1198       loi->perPatch = patch;
1199
1200       Instruction *hii =
1201          mkLoad(TYPE_U32, hi,
1202                 mkSymbol(file, i, TYPE_U32, base + c * tySize + 4),
1203                 indirect0);
1204       hii->setIndirect(0, 1, indirect1);
1205       hii->perPatch = patch;
1206
1207       return mkOp2(OP_MERGE, ty, def, lo, hi);
1208    } else {
1209       Instruction *ld =
1210          mkLoad(ty, def, mkSymbol(file, i, ty, base + c * tySize), indirect0);
1211       ld->setIndirect(0, 1, indirect1);
1212       ld->perPatch = patch;
1213       return ld;
1214    }
1215 }
1216
1217 void
1218 Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
1219                    DataType ty, Value *src, uint8_t idx, uint8_t c,
1220                    Value *indirect0, Value *indirect1)
1221 {
1222    uint8_t size = typeSizeof(ty);
1223    uint32_t address = getSlotAddress(insn, idx, c);
1224
1225    if (size == 8 && indirect0) {
1226       Value *split[2];
1227       mkSplit(split, 4, src);
1228
1229       if (op == OP_EXPORT) {
1230          split[0] = mkMov(getSSA(), split[0], ty)->getDef(0);
1231          split[1] = mkMov(getSSA(), split[1], ty)->getDef(0);
1232       }
1233
1234       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address), indirect0,
1235               split[0])->perPatch = info->out[idx].patch;
1236       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address + 4), indirect0,
1237               split[1])->perPatch = info->out[idx].patch;
1238    } else {
1239       if (op == OP_EXPORT)
1240          src = mkMov(getSSA(size), src, ty)->getDef(0);
1241       mkStore(op, ty, mkSymbol(file, 0, ty, address), indirect0,
1242               src)->perPatch = info->out[idx].patch;
1243    }
1244 }
1245
1246 bool
1247 Converter::parseNIR()
1248 {
1249    info->bin.tlsSpace = 0;
1250    info->io.clipDistances = nir->info.clip_distance_array_size;
1251    info->io.cullDistances = nir->info.cull_distance_array_size;
1252    info->io.layer_viewport_relative = nir->info.layer_viewport_relative;
1253
1254    switch(prog->getType()) {
1255    case Program::TYPE_COMPUTE:
1256       info->prop.cp.numThreads[0] = nir->info.cs.local_size[0];
1257       info->prop.cp.numThreads[1] = nir->info.cs.local_size[1];
1258       info->prop.cp.numThreads[2] = nir->info.cs.local_size[2];
1259       info->bin.smemSize = nir->info.cs.shared_size;
1260       break;
1261    case Program::TYPE_FRAGMENT:
1262       info->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
1263       info->prop.fp.persampleInvocation =
1264          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
1265          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1266       info->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
1267       info->prop.fp.readsSampleLocations =
1268          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1269       info->prop.fp.usesDiscard = nir->info.fs.uses_discard || nir->info.fs.uses_demote;
1270       info->prop.fp.usesSampleMaskIn =
1271          !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
1272       break;
1273    case Program::TYPE_GEOMETRY:
1274       info->prop.gp.inputPrim = nir->info.gs.input_primitive;
1275       info->prop.gp.instanceCount = nir->info.gs.invocations;
1276       info->prop.gp.maxVertices = nir->info.gs.vertices_out;
1277       info->prop.gp.outputPrim = nir->info.gs.output_primitive;
1278       break;
1279    case Program::TYPE_TESSELLATION_CONTROL:
1280    case Program::TYPE_TESSELLATION_EVAL:
1281       if (nir->info.tess.primitive_mode == GL_ISOLINES)
1282          info->prop.tp.domain = GL_LINES;
1283       else
1284          info->prop.tp.domain = nir->info.tess.primitive_mode;
1285       info->prop.tp.outputPatchSize = nir->info.tess.tcs_vertices_out;
1286       info->prop.tp.outputPrim =
1287          nir->info.tess.point_mode ? PIPE_PRIM_POINTS : PIPE_PRIM_TRIANGLES;
1288       info->prop.tp.partitioning = (nir->info.tess.spacing + 1) % 3;
1289       info->prop.tp.winding = !nir->info.tess.ccw;
1290       break;
1291    case Program::TYPE_VERTEX:
1292       info->prop.vp.usesDrawParameters =
1293          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
1294          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
1295          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
1296       break;
1297    default:
1298       break;
1299    }
1300
1301    return true;
1302 }
1303
1304 bool
1305 Converter::visit(nir_function *function)
1306 {
1307    assert(function->impl);
1308
1309    // usually the blocks will set everything up, but main is special
1310    BasicBlock *entry = new BasicBlock(prog->main);
1311    exit = new BasicBlock(prog->main);
1312    blocks[nir_start_block(function->impl)->index] = entry;
1313    prog->main->setEntry(entry);
1314    prog->main->setExit(exit);
1315
1316    setPosition(entry, true);
1317
1318    if (info->io.genUserClip > 0) {
1319       for (int c = 0; c < 4; ++c)
1320          clipVtx[c] = getScratch();
1321    }
1322
1323    switch (prog->getType()) {
1324    case Program::TYPE_TESSELLATION_CONTROL:
1325       outBase = mkOp2v(
1326          OP_SUB, TYPE_U32, getSSA(),
1327          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
1328          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
1329       break;
1330    case Program::TYPE_FRAGMENT: {
1331       Symbol *sv = mkSysVal(SV_POSITION, 3);
1332       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
1333       fp.position = mkOp1v(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
1334       break;
1335    }
1336    default:
1337       break;
1338    }
1339
1340    nir_foreach_register(reg, &function->impl->registers) {
1341       if (reg->num_array_elems) {
1342          // TODO: packed variables would be nice, but MemoryOpt fails
1343          // replace 4 with reg->num_components
1344          uint32_t size = 4 * reg->num_array_elems * (reg->bit_size / 8);
1345          regToLmemOffset[reg->index] = info->bin.tlsSpace;
1346          info->bin.tlsSpace += size;
1347       }
1348    }
1349
1350    nir_index_ssa_defs(function->impl);
1351    foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
1352       if (!visit(node))
1353          return false;
1354    }
1355
1356    bb->cfg.attach(&exit->cfg, Graph::Edge::TREE);
1357    setPosition(exit, true);
1358
1359    if ((prog->getType() == Program::TYPE_VERTEX ||
1360         prog->getType() == Program::TYPE_TESSELLATION_EVAL)
1361        && info->io.genUserClip > 0)
1362       handleUserClipPlanes();
1363
1364    // TODO: for non main function this needs to be a OP_RETURN
1365    mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
1366    return true;
1367 }
1368
1369 bool
1370 Converter::visit(nir_cf_node *node)
1371 {
1372    switch (node->type) {
1373    case nir_cf_node_block:
1374       return visit(nir_cf_node_as_block(node));
1375    case nir_cf_node_if:
1376       return visit(nir_cf_node_as_if(node));
1377    case nir_cf_node_loop:
1378       return visit(nir_cf_node_as_loop(node));
1379    default:
1380       ERROR("unknown nir_cf_node type %u\n", node->type);
1381       return false;
1382    }
1383 }
1384
1385 bool
1386 Converter::visit(nir_block *block)
1387 {
1388    if (!block->predecessors->entries && block->instr_list.is_empty())
1389       return true;
1390
1391    BasicBlock *bb = convert(block);
1392
1393    setPosition(bb, true);
1394    nir_foreach_instr(insn, block) {
1395       if (!visit(insn))
1396          return false;
1397    }
1398    return true;
1399 }
1400
1401 bool
1402 Converter::visit(nir_if *nif)
1403 {
1404    curIfDepth++;
1405
1406    DataType sType = getSType(nif->condition, false, false);
1407    Value *src = getSrc(&nif->condition, 0);
1408
1409    nir_block *lastThen = nir_if_last_then_block(nif);
1410    nir_block *lastElse = nir_if_last_else_block(nif);
1411
1412    BasicBlock *headBB = bb;
1413    BasicBlock *ifBB = convert(nir_if_first_then_block(nif));
1414    BasicBlock *elseBB = convert(nir_if_first_else_block(nif));
1415
1416    bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1417    bb->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
1418
1419    bool insertJoins = lastThen->successors[0] == lastElse->successors[0];
1420    mkFlow(OP_BRA, elseBB, CC_EQ, src)->setType(sType);
1421
1422    foreach_list_typed(nir_cf_node, node, node, &nif->then_list) {
1423       if (!visit(node))
1424          return false;
1425    }
1426
1427    setPosition(convert(lastThen), true);
1428    if (!bb->isTerminated()) {
1429       BasicBlock *tailBB = convert(lastThen->successors[0]);
1430       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1431       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1432    } else {
1433       insertJoins = insertJoins && bb->getExit()->op == OP_BRA;
1434    }
1435
1436    foreach_list_typed(nir_cf_node, node, node, &nif->else_list) {
1437       if (!visit(node))
1438          return false;
1439    }
1440
1441    setPosition(convert(lastElse), true);
1442    if (!bb->isTerminated()) {
1443       BasicBlock *tailBB = convert(lastElse->successors[0]);
1444       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1445       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1446    } else {
1447       insertJoins = insertJoins && bb->getExit()->op == OP_BRA;
1448    }
1449
1450    /* only insert joins for the most outer if */
1451    if (--curIfDepth)
1452       insertJoins = false;
1453
1454    /* we made sure that all threads would converge at the same block */
1455    if (insertJoins) {
1456       BasicBlock *conv = convert(lastThen->successors[0]);
1457       setPosition(headBB->getExit(), false);
1458       headBB->joinAt = mkFlow(OP_JOINAT, conv, CC_ALWAYS, NULL);
1459       setPosition(conv, false);
1460       mkFlow(OP_JOIN, NULL, CC_ALWAYS, NULL)->fixed = 1;
1461    }
1462
1463    return true;
1464 }
1465
1466 // TODO: add convergency
1467 bool
1468 Converter::visit(nir_loop *loop)
1469 {
1470    curLoopDepth += 1;
1471    func->loopNestingBound = std::max(func->loopNestingBound, curLoopDepth);
1472
1473    BasicBlock *loopBB = convert(nir_loop_first_block(loop));
1474    BasicBlock *tailBB = convert(nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)));
1475
1476    bb->cfg.attach(&loopBB->cfg, Graph::Edge::TREE);
1477
1478    mkFlow(OP_PREBREAK, tailBB, CC_ALWAYS, NULL);
1479    setPosition(loopBB, false);
1480    mkFlow(OP_PRECONT, loopBB, CC_ALWAYS, NULL);
1481
1482    foreach_list_typed(nir_cf_node, node, node, &loop->body) {
1483       if (!visit(node))
1484          return false;
1485    }
1486
1487    if (!bb->isTerminated()) {
1488       mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
1489       bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
1490    }
1491
1492    if (tailBB->cfg.incidentCount() == 0)
1493       loopBB->cfg.attach(&tailBB->cfg, Graph::Edge::TREE);
1494
1495    curLoopDepth -= 1;
1496
1497    return true;
1498 }
1499
1500 bool
1501 Converter::visit(nir_instr *insn)
1502 {
1503    // we need an insertion point for on the fly generated immediate loads
1504    immInsertPos = bb->getExit();
1505    switch (insn->type) {
1506    case nir_instr_type_alu:
1507       return visit(nir_instr_as_alu(insn));
1508    case nir_instr_type_intrinsic:
1509       return visit(nir_instr_as_intrinsic(insn));
1510    case nir_instr_type_jump:
1511       return visit(nir_instr_as_jump(insn));
1512    case nir_instr_type_load_const:
1513       return visit(nir_instr_as_load_const(insn));
1514    case nir_instr_type_ssa_undef:
1515       return visit(nir_instr_as_ssa_undef(insn));
1516    case nir_instr_type_tex:
1517       return visit(nir_instr_as_tex(insn));
1518    default:
1519       ERROR("unknown nir_instr type %u\n", insn->type);
1520       return false;
1521    }
1522    return true;
1523 }
1524
1525 SVSemantic
1526 Converter::convert(nir_intrinsic_op intr)
1527 {
1528    switch (intr) {
1529    case nir_intrinsic_load_base_vertex:
1530       return SV_BASEVERTEX;
1531    case nir_intrinsic_load_base_instance:
1532       return SV_BASEINSTANCE;
1533    case nir_intrinsic_load_draw_id:
1534       return SV_DRAWID;
1535    case nir_intrinsic_load_front_face:
1536       return SV_FACE;
1537    case nir_intrinsic_is_helper_invocation:
1538    case nir_intrinsic_load_helper_invocation:
1539       return SV_THREAD_KILL;
1540    case nir_intrinsic_load_instance_id:
1541       return SV_INSTANCE_ID;
1542    case nir_intrinsic_load_invocation_id:
1543       return SV_INVOCATION_ID;
1544    case nir_intrinsic_load_local_group_size:
1545       return SV_NTID;
1546    case nir_intrinsic_load_local_invocation_id:
1547       return SV_TID;
1548    case nir_intrinsic_load_num_work_groups:
1549       return SV_NCTAID;
1550    case nir_intrinsic_load_patch_vertices_in:
1551       return SV_VERTEX_COUNT;
1552    case nir_intrinsic_load_primitive_id:
1553       return SV_PRIMITIVE_ID;
1554    case nir_intrinsic_load_sample_id:
1555       return SV_SAMPLE_INDEX;
1556    case nir_intrinsic_load_sample_mask_in:
1557       return SV_SAMPLE_MASK;
1558    case nir_intrinsic_load_sample_pos:
1559       return SV_SAMPLE_POS;
1560    case nir_intrinsic_load_subgroup_eq_mask:
1561       return SV_LANEMASK_EQ;
1562    case nir_intrinsic_load_subgroup_ge_mask:
1563       return SV_LANEMASK_GE;
1564    case nir_intrinsic_load_subgroup_gt_mask:
1565       return SV_LANEMASK_GT;
1566    case nir_intrinsic_load_subgroup_le_mask:
1567       return SV_LANEMASK_LE;
1568    case nir_intrinsic_load_subgroup_lt_mask:
1569       return SV_LANEMASK_LT;
1570    case nir_intrinsic_load_subgroup_invocation:
1571       return SV_LANEID;
1572    case nir_intrinsic_load_tess_coord:
1573       return SV_TESS_COORD;
1574    case nir_intrinsic_load_tess_level_inner:
1575       return SV_TESS_INNER;
1576    case nir_intrinsic_load_tess_level_outer:
1577       return SV_TESS_OUTER;
1578    case nir_intrinsic_load_vertex_id:
1579       return SV_VERTEX_ID;
1580    case nir_intrinsic_load_work_group_id:
1581       return SV_CTAID;
1582    default:
1583       ERROR("unknown SVSemantic for nir_intrinsic_op %s\n",
1584             nir_intrinsic_infos[intr].name);
1585       assert(false);
1586       return SV_LAST;
1587    }
1588 }
1589
1590 bool
1591 Converter::visit(nir_intrinsic_instr *insn)
1592 {
1593    nir_intrinsic_op op = insn->intrinsic;
1594    const nir_intrinsic_info &opInfo = nir_intrinsic_infos[op];
1595    unsigned dest_components = nir_intrinsic_dest_components(insn);
1596
1597    switch (op) {
1598    case nir_intrinsic_load_uniform: {
1599       LValues &newDefs = convert(&insn->dest);
1600       const DataType dType = getDType(insn);
1601       Value *indirect;
1602       uint32_t coffset = getIndirect(insn, 0, 0, indirect);
1603       for (uint8_t i = 0; i < dest_components; ++i) {
1604          loadFrom(FILE_MEMORY_CONST, 0, dType, newDefs[i], 16 * coffset, i, indirect);
1605       }
1606       break;
1607    }
1608    case nir_intrinsic_store_output:
1609    case nir_intrinsic_store_per_vertex_output: {
1610       Value *indirect;
1611       DataType dType = getSType(insn->src[0], false, false);
1612       uint32_t idx = getIndirect(insn, op == nir_intrinsic_store_output ? 1 : 2, 0, indirect);
1613
1614       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
1615          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
1616             continue;
1617
1618          uint8_t offset = 0;
1619          Value *src = getSrc(&insn->src[0], i);
1620          switch (prog->getType()) {
1621          case Program::TYPE_FRAGMENT: {
1622             if (info->out[idx].sn == TGSI_SEMANTIC_POSITION) {
1623                // TGSI uses a different interface than NIR, TGSI stores that
1624                // value in the z component, NIR in X
1625                offset += 2;
1626                src = mkOp1v(OP_SAT, TYPE_F32, getScratch(), src);
1627             }
1628             break;
1629          }
1630          case Program::TYPE_GEOMETRY:
1631          case Program::TYPE_TESSELLATION_EVAL:
1632          case Program::TYPE_VERTEX: {
1633             if (info->io.genUserClip > 0 && idx == (uint32_t)clipVertexOutput) {
1634                mkMov(clipVtx[i], src);
1635                src = clipVtx[i];
1636             }
1637             break;
1638          }
1639          default:
1640             break;
1641          }
1642
1643          storeTo(insn, FILE_SHADER_OUTPUT, OP_EXPORT, dType, src, idx, i + offset, indirect);
1644       }
1645       break;
1646    }
1647    case nir_intrinsic_load_input:
1648    case nir_intrinsic_load_interpolated_input:
1649    case nir_intrinsic_load_output: {
1650       LValues &newDefs = convert(&insn->dest);
1651
1652       // FBFetch
1653       if (prog->getType() == Program::TYPE_FRAGMENT &&
1654           op == nir_intrinsic_load_output) {
1655          std::vector<Value*> defs, srcs;
1656          uint8_t mask = 0;
1657
1658          srcs.push_back(getSSA());
1659          srcs.push_back(getSSA());
1660          Value *x = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 0));
1661          Value *y = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 1));
1662          mkCvt(OP_CVT, TYPE_U32, srcs[0], TYPE_F32, x)->rnd = ROUND_Z;
1663          mkCvt(OP_CVT, TYPE_U32, srcs[1], TYPE_F32, y)->rnd = ROUND_Z;
1664
1665          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LAYER, 0)));
1666          srcs.push_back(mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_SAMPLE_INDEX, 0)));
1667
1668          for (uint8_t i = 0u; i < dest_components; ++i) {
1669             defs.push_back(newDefs[i]);
1670             mask |= 1 << i;
1671          }
1672
1673          TexInstruction *texi = mkTex(OP_TXF, TEX_TARGET_2D_MS_ARRAY, 0, 0, defs, srcs);
1674          texi->tex.levelZero = 1;
1675          texi->tex.mask = mask;
1676          texi->tex.useOffsets = 0;
1677          texi->tex.r = 0xffff;
1678          texi->tex.s = 0xffff;
1679
1680          info->prop.fp.readsFramebuffer = true;
1681          break;
1682       }
1683
1684       const DataType dType = getDType(insn);
1685       Value *indirect;
1686       bool input = op != nir_intrinsic_load_output;
1687       operation nvirOp;
1688       uint32_t mode = 0;
1689
1690       uint32_t idx = getIndirect(insn, op == nir_intrinsic_load_interpolated_input ? 1 : 0, 0, indirect);
1691       nv50_ir_varying& vary = input ? info->in[idx] : info->out[idx];
1692
1693       // see load_barycentric_* handling
1694       if (prog->getType() == Program::TYPE_FRAGMENT) {
1695          mode = translateInterpMode(&vary, nvirOp);
1696          if (op == nir_intrinsic_load_interpolated_input) {
1697             ImmediateValue immMode;
1698             if (getSrc(&insn->src[0], 1)->getUniqueInsn()->src(0).getImmediate(immMode))
1699                mode |= immMode.reg.data.u32;
1700          }
1701       }
1702
1703       for (uint8_t i = 0u; i < dest_components; ++i) {
1704          uint32_t address = getSlotAddress(insn, idx, i);
1705          Symbol *sym = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address);
1706          if (prog->getType() == Program::TYPE_FRAGMENT) {
1707             int s = 1;
1708             if (typeSizeof(dType) == 8) {
1709                Value *lo = getSSA();
1710                Value *hi = getSSA();
1711                Instruction *interp;
1712
1713                interp = mkOp1(nvirOp, TYPE_U32, lo, sym);
1714                if (nvirOp == OP_PINTERP)
1715                   interp->setSrc(s++, fp.position);
1716                if (mode & NV50_IR_INTERP_OFFSET)
1717                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1718                interp->setInterpolate(mode);
1719                interp->setIndirect(0, 0, indirect);
1720
1721                Symbol *sym1 = mkSymbol(input ? FILE_SHADER_INPUT : FILE_SHADER_OUTPUT, 0, dType, address + 4);
1722                interp = mkOp1(nvirOp, TYPE_U32, hi, sym1);
1723                if (nvirOp == OP_PINTERP)
1724                   interp->setSrc(s++, fp.position);
1725                if (mode & NV50_IR_INTERP_OFFSET)
1726                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1727                interp->setInterpolate(mode);
1728                interp->setIndirect(0, 0, indirect);
1729
1730                mkOp2(OP_MERGE, dType, newDefs[i], lo, hi);
1731             } else {
1732                Instruction *interp = mkOp1(nvirOp, dType, newDefs[i], sym);
1733                if (nvirOp == OP_PINTERP)
1734                   interp->setSrc(s++, fp.position);
1735                if (mode & NV50_IR_INTERP_OFFSET)
1736                   interp->setSrc(s++, getSrc(&insn->src[0], 0));
1737                interp->setInterpolate(mode);
1738                interp->setIndirect(0, 0, indirect);
1739             }
1740          } else {
1741             mkLoad(dType, newDefs[i], sym, indirect)->perPatch = vary.patch;
1742          }
1743       }
1744       break;
1745    }
1746    case nir_intrinsic_load_kernel_input: {
1747       assert(prog->getType() == Program::TYPE_COMPUTE);
1748       assert(insn->num_components == 1);
1749
1750       LValues &newDefs = convert(&insn->dest);
1751       const DataType dType = getDType(insn);
1752       Value *indirect;
1753       uint32_t idx = getIndirect(insn, 0, 0, indirect, true);
1754
1755       mkLoad(dType, newDefs[0], mkSymbol(FILE_SHADER_INPUT, 0, dType, idx), indirect);
1756       break;
1757    }
1758    case nir_intrinsic_load_barycentric_at_offset:
1759    case nir_intrinsic_load_barycentric_at_sample:
1760    case nir_intrinsic_load_barycentric_centroid:
1761    case nir_intrinsic_load_barycentric_pixel:
1762    case nir_intrinsic_load_barycentric_sample: {
1763       LValues &newDefs = convert(&insn->dest);
1764       uint32_t mode;
1765
1766       if (op == nir_intrinsic_load_barycentric_centroid ||
1767           op == nir_intrinsic_load_barycentric_sample) {
1768          mode = NV50_IR_INTERP_CENTROID;
1769       } else if (op == nir_intrinsic_load_barycentric_at_offset) {
1770          Value *offs[2];
1771          for (uint8_t c = 0; c < 2; c++) {
1772             offs[c] = getScratch();
1773             mkOp2(OP_MIN, TYPE_F32, offs[c], getSrc(&insn->src[0], c), loadImm(NULL, 0.4375f));
1774             mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
1775             mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
1776             mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
1777          }
1778          mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[1], mkImm(0x1010), offs[0]);
1779
1780          mode = NV50_IR_INTERP_OFFSET;
1781       } else if (op == nir_intrinsic_load_barycentric_pixel) {
1782          mode = NV50_IR_INTERP_DEFAULT;
1783       } else if (op == nir_intrinsic_load_barycentric_at_sample) {
1784          info->prop.fp.readsSampleLocations = true;
1785          mkOp1(OP_PIXLD, TYPE_U32, newDefs[0], getSrc(&insn->src[0], 0))->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
1786          mode = NV50_IR_INTERP_OFFSET;
1787       } else {
1788          unreachable("all intrinsics already handled above");
1789       }
1790
1791       loadImm(newDefs[1], mode);
1792       break;
1793    }
1794    case nir_intrinsic_demote:
1795    case nir_intrinsic_discard:
1796       mkOp(OP_DISCARD, TYPE_NONE, NULL);
1797       break;
1798    case nir_intrinsic_demote_if:
1799    case nir_intrinsic_discard_if: {
1800       Value *pred = getSSA(1, FILE_PREDICATE);
1801       if (insn->num_components > 1) {
1802          ERROR("nir_intrinsic_discard_if only with 1 component supported!\n");
1803          assert(false);
1804          return false;
1805       }
1806       mkCmp(OP_SET, CC_NE, TYPE_U8, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1807       mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, pred);
1808       break;
1809    }
1810    case nir_intrinsic_load_base_vertex:
1811    case nir_intrinsic_load_base_instance:
1812    case nir_intrinsic_load_draw_id:
1813    case nir_intrinsic_load_front_face:
1814    case nir_intrinsic_is_helper_invocation:
1815    case nir_intrinsic_load_helper_invocation:
1816    case nir_intrinsic_load_instance_id:
1817    case nir_intrinsic_load_invocation_id:
1818    case nir_intrinsic_load_local_group_size:
1819    case nir_intrinsic_load_local_invocation_id:
1820    case nir_intrinsic_load_num_work_groups:
1821    case nir_intrinsic_load_patch_vertices_in:
1822    case nir_intrinsic_load_primitive_id:
1823    case nir_intrinsic_load_sample_id:
1824    case nir_intrinsic_load_sample_mask_in:
1825    case nir_intrinsic_load_sample_pos:
1826    case nir_intrinsic_load_subgroup_eq_mask:
1827    case nir_intrinsic_load_subgroup_ge_mask:
1828    case nir_intrinsic_load_subgroup_gt_mask:
1829    case nir_intrinsic_load_subgroup_le_mask:
1830    case nir_intrinsic_load_subgroup_lt_mask:
1831    case nir_intrinsic_load_subgroup_invocation:
1832    case nir_intrinsic_load_tess_coord:
1833    case nir_intrinsic_load_tess_level_inner:
1834    case nir_intrinsic_load_tess_level_outer:
1835    case nir_intrinsic_load_vertex_id:
1836    case nir_intrinsic_load_work_group_id: {
1837       const DataType dType = getDType(insn);
1838       SVSemantic sv = convert(op);
1839       LValues &newDefs = convert(&insn->dest);
1840
1841       for (uint8_t i = 0u; i < nir_intrinsic_dest_components(insn); ++i) {
1842          Value *def;
1843          if (typeSizeof(dType) == 8)
1844             def = getSSA();
1845          else
1846             def = newDefs[i];
1847
1848          if (sv == SV_TID && info->prop.cp.numThreads[i] == 1) {
1849             loadImm(def, 0u);
1850          } else {
1851             Symbol *sym = mkSysVal(sv, i);
1852             Instruction *rdsv = mkOp1(OP_RDSV, TYPE_U32, def, sym);
1853             if (sv == SV_TESS_OUTER || sv == SV_TESS_INNER)
1854                rdsv->perPatch = 1;
1855          }
1856
1857          if (typeSizeof(dType) == 8)
1858             mkOp2(OP_MERGE, dType, newDefs[i], def, loadImm(getSSA(), 0u));
1859       }
1860       break;
1861    }
1862    // constants
1863    case nir_intrinsic_load_subgroup_size: {
1864       LValues &newDefs = convert(&insn->dest);
1865       loadImm(newDefs[0], 32u);
1866       break;
1867    }
1868    case nir_intrinsic_vote_all:
1869    case nir_intrinsic_vote_any:
1870    case nir_intrinsic_vote_ieq: {
1871       LValues &newDefs = convert(&insn->dest);
1872       Value *pred = getScratch(1, FILE_PREDICATE);
1873       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1874       mkOp1(OP_VOTE, TYPE_U32, pred, pred)->subOp = getSubOp(op);
1875       mkCvt(OP_CVT, TYPE_U32, newDefs[0], TYPE_U8, pred);
1876       break;
1877    }
1878    case nir_intrinsic_ballot: {
1879       LValues &newDefs = convert(&insn->dest);
1880       Value *pred = getSSA(1, FILE_PREDICATE);
1881       mkCmp(OP_SET, CC_NE, TYPE_U32, pred, TYPE_U32, getSrc(&insn->src[0], 0), zero);
1882       mkOp1(OP_VOTE, TYPE_U32, newDefs[0], pred)->subOp = NV50_IR_SUBOP_VOTE_ANY;
1883       break;
1884    }
1885    case nir_intrinsic_read_first_invocation:
1886    case nir_intrinsic_read_invocation: {
1887       LValues &newDefs = convert(&insn->dest);
1888       const DataType dType = getDType(insn);
1889       Value *tmp = getScratch();
1890
1891       if (op == nir_intrinsic_read_first_invocation) {
1892          mkOp1(OP_VOTE, TYPE_U32, tmp, mkImm(1))->subOp = NV50_IR_SUBOP_VOTE_ANY;
1893          mkOp1(OP_BREV, TYPE_U32, tmp, tmp);
1894          mkOp1(OP_BFIND, TYPE_U32, tmp, tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
1895       } else
1896          tmp = getSrc(&insn->src[1], 0);
1897
1898       for (uint8_t i = 0; i < dest_components; ++i) {
1899          mkOp3(OP_SHFL, dType, newDefs[i], getSrc(&insn->src[0], i), tmp, mkImm(0x1f))
1900             ->subOp = NV50_IR_SUBOP_SHFL_IDX;
1901       }
1902       break;
1903    }
1904    case nir_intrinsic_load_per_vertex_input: {
1905       const DataType dType = getDType(insn);
1906       LValues &newDefs = convert(&insn->dest);
1907       Value *indirectVertex;
1908       Value *indirectOffset;
1909       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
1910       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
1911
1912       Value *vtxBase = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1913                               mkImm(baseVertex), indirectVertex);
1914       for (uint8_t i = 0u; i < dest_components; ++i) {
1915          uint32_t address = getSlotAddress(insn, idx, i);
1916          loadFrom(FILE_SHADER_INPUT, 0, dType, newDefs[i], address, 0,
1917                   indirectOffset, vtxBase, info->in[idx].patch);
1918       }
1919       break;
1920    }
1921    case nir_intrinsic_load_per_vertex_output: {
1922       const DataType dType = getDType(insn);
1923       LValues &newDefs = convert(&insn->dest);
1924       Value *indirectVertex;
1925       Value *indirectOffset;
1926       uint32_t baseVertex = getIndirect(&insn->src[0], 0, indirectVertex);
1927       uint32_t idx = getIndirect(insn, 1, 0, indirectOffset);
1928       Value *vtxBase = NULL;
1929
1930       if (indirectVertex)
1931          vtxBase = indirectVertex;
1932       else
1933          vtxBase = loadImm(NULL, baseVertex);
1934
1935       vtxBase = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, FILE_ADDRESS), outBase, vtxBase);
1936
1937       for (uint8_t i = 0u; i < dest_components; ++i) {
1938          uint32_t address = getSlotAddress(insn, idx, i);
1939          loadFrom(FILE_SHADER_OUTPUT, 0, dType, newDefs[i], address, 0,
1940                   indirectOffset, vtxBase, info->in[idx].patch);
1941       }
1942       break;
1943    }
1944    case nir_intrinsic_emit_vertex: {
1945       if (info->io.genUserClip > 0)
1946          handleUserClipPlanes();
1947       uint32_t idx = nir_intrinsic_stream_id(insn);
1948       mkOp1(getOperation(op), TYPE_U32, NULL, mkImm(idx))->fixed = 1;
1949       break;
1950    }
1951    case nir_intrinsic_end_primitive: {
1952       uint32_t idx = nir_intrinsic_stream_id(insn);
1953       if (idx)
1954          break;
1955       mkOp1(getOperation(op), TYPE_U32, NULL, mkImm(idx))->fixed = 1;
1956       break;
1957    }
1958    case nir_intrinsic_load_ubo: {
1959       const DataType dType = getDType(insn);
1960       LValues &newDefs = convert(&insn->dest);
1961       Value *indirectIndex;
1962       Value *indirectOffset;
1963       uint32_t index = getIndirect(&insn->src[0], 0, indirectIndex) + 1;
1964       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
1965
1966       for (uint8_t i = 0u; i < dest_components; ++i) {
1967          loadFrom(FILE_MEMORY_CONST, index, dType, newDefs[i], offset, i,
1968                   indirectOffset, indirectIndex);
1969       }
1970       break;
1971    }
1972    case nir_intrinsic_get_buffer_size: {
1973       LValues &newDefs = convert(&insn->dest);
1974       const DataType dType = getDType(insn);
1975       Value *indirectBuffer;
1976       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
1977
1978       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, 0);
1979       mkOp1(OP_BUFQ, dType, newDefs[0], sym)->setIndirect(0, 0, indirectBuffer);
1980       break;
1981    }
1982    case nir_intrinsic_store_ssbo: {
1983       DataType sType = getSType(insn->src[0], false, false);
1984       Value *indirectBuffer;
1985       Value *indirectOffset;
1986       uint32_t buffer = getIndirect(&insn->src[1], 0, indirectBuffer);
1987       uint32_t offset = getIndirect(&insn->src[2], 0, indirectOffset);
1988
1989       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
1990          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
1991             continue;
1992          Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, sType,
1993                                 offset + i * typeSizeof(sType));
1994          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i))
1995             ->setIndirect(0, 1, indirectBuffer);
1996       }
1997       info->io.globalAccess |= 0x2;
1998       break;
1999    }
2000    case nir_intrinsic_load_ssbo: {
2001       const DataType dType = getDType(insn);
2002       LValues &newDefs = convert(&insn->dest);
2003       Value *indirectBuffer;
2004       Value *indirectOffset;
2005       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2006       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2007
2008       for (uint8_t i = 0u; i < dest_components; ++i)
2009          loadFrom(FILE_MEMORY_BUFFER, buffer, dType, newDefs[i], offset, i,
2010                   indirectOffset, indirectBuffer);
2011
2012       info->io.globalAccess |= 0x1;
2013       break;
2014    }
2015    case nir_intrinsic_shared_atomic_add:
2016    case nir_intrinsic_shared_atomic_and:
2017    case nir_intrinsic_shared_atomic_comp_swap:
2018    case nir_intrinsic_shared_atomic_exchange:
2019    case nir_intrinsic_shared_atomic_or:
2020    case nir_intrinsic_shared_atomic_imax:
2021    case nir_intrinsic_shared_atomic_imin:
2022    case nir_intrinsic_shared_atomic_umax:
2023    case nir_intrinsic_shared_atomic_umin:
2024    case nir_intrinsic_shared_atomic_xor: {
2025       const DataType dType = getDType(insn);
2026       LValues &newDefs = convert(&insn->dest);
2027       Value *indirectOffset;
2028       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2029       Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, dType, offset);
2030       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym, getSrc(&insn->src[1], 0));
2031       if (op == nir_intrinsic_shared_atomic_comp_swap)
2032          atom->setSrc(2, getSrc(&insn->src[2], 0));
2033       atom->setIndirect(0, 0, indirectOffset);
2034       atom->subOp = getSubOp(op);
2035       break;
2036    }
2037    case nir_intrinsic_ssbo_atomic_add:
2038    case nir_intrinsic_ssbo_atomic_and:
2039    case nir_intrinsic_ssbo_atomic_comp_swap:
2040    case nir_intrinsic_ssbo_atomic_exchange:
2041    case nir_intrinsic_ssbo_atomic_or:
2042    case nir_intrinsic_ssbo_atomic_imax:
2043    case nir_intrinsic_ssbo_atomic_imin:
2044    case nir_intrinsic_ssbo_atomic_umax:
2045    case nir_intrinsic_ssbo_atomic_umin:
2046    case nir_intrinsic_ssbo_atomic_xor: {
2047       const DataType dType = getDType(insn);
2048       LValues &newDefs = convert(&insn->dest);
2049       Value *indirectBuffer;
2050       Value *indirectOffset;
2051       uint32_t buffer = getIndirect(&insn->src[0], 0, indirectBuffer);
2052       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2053
2054       Symbol *sym = mkSymbol(FILE_MEMORY_BUFFER, buffer, dType, offset);
2055       Instruction *atom = mkOp2(OP_ATOM, dType, newDefs[0], sym,
2056                                 getSrc(&insn->src[2], 0));
2057       if (op == nir_intrinsic_ssbo_atomic_comp_swap)
2058          atom->setSrc(2, getSrc(&insn->src[3], 0));
2059       atom->setIndirect(0, 0, indirectOffset);
2060       atom->setIndirect(0, 1, indirectBuffer);
2061       atom->subOp = getSubOp(op);
2062
2063       info->io.globalAccess |= 0x2;
2064       break;
2065    }
2066    case nir_intrinsic_global_atomic_add:
2067    case nir_intrinsic_global_atomic_and:
2068    case nir_intrinsic_global_atomic_comp_swap:
2069    case nir_intrinsic_global_atomic_exchange:
2070    case nir_intrinsic_global_atomic_or:
2071    case nir_intrinsic_global_atomic_imax:
2072    case nir_intrinsic_global_atomic_imin:
2073    case nir_intrinsic_global_atomic_umax:
2074    case nir_intrinsic_global_atomic_umin:
2075    case nir_intrinsic_global_atomic_xor: {
2076       const DataType dType = getDType(insn);
2077       LValues &newDefs = convert(&insn->dest);
2078       Value *address;
2079       uint32_t offset = getIndirect(&insn->src[0], 0, address);
2080
2081       Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, dType, offset);
2082       Instruction *atom =
2083          mkOp2(OP_ATOM, dType, newDefs[0], sym, getSrc(&insn->src[1], 0));
2084       atom->setIndirect(0, 0, address);
2085       atom->subOp = getSubOp(op);
2086
2087       info->io.globalAccess |= 0x2;
2088       break;
2089    }
2090    case nir_intrinsic_bindless_image_atomic_add:
2091    case nir_intrinsic_bindless_image_atomic_and:
2092    case nir_intrinsic_bindless_image_atomic_comp_swap:
2093    case nir_intrinsic_bindless_image_atomic_exchange:
2094    case nir_intrinsic_bindless_image_atomic_imax:
2095    case nir_intrinsic_bindless_image_atomic_umax:
2096    case nir_intrinsic_bindless_image_atomic_imin:
2097    case nir_intrinsic_bindless_image_atomic_umin:
2098    case nir_intrinsic_bindless_image_atomic_or:
2099    case nir_intrinsic_bindless_image_atomic_xor:
2100    case nir_intrinsic_bindless_image_atomic_inc_wrap:
2101    case nir_intrinsic_bindless_image_atomic_dec_wrap:
2102    case nir_intrinsic_bindless_image_load:
2103    case nir_intrinsic_bindless_image_samples:
2104    case nir_intrinsic_bindless_image_size:
2105    case nir_intrinsic_bindless_image_store:
2106    case nir_intrinsic_image_atomic_add:
2107    case nir_intrinsic_image_atomic_and:
2108    case nir_intrinsic_image_atomic_comp_swap:
2109    case nir_intrinsic_image_atomic_exchange:
2110    case nir_intrinsic_image_atomic_imax:
2111    case nir_intrinsic_image_atomic_umax:
2112    case nir_intrinsic_image_atomic_imin:
2113    case nir_intrinsic_image_atomic_umin:
2114    case nir_intrinsic_image_atomic_or:
2115    case nir_intrinsic_image_atomic_xor:
2116    case nir_intrinsic_image_atomic_inc_wrap:
2117    case nir_intrinsic_image_atomic_dec_wrap:
2118    case nir_intrinsic_image_load:
2119    case nir_intrinsic_image_samples:
2120    case nir_intrinsic_image_size:
2121    case nir_intrinsic_image_store: {
2122       std::vector<Value*> srcs, defs;
2123       Value *indirect;
2124       DataType ty;
2125
2126       uint32_t mask = 0;
2127       TexInstruction::Target target =
2128          convert(nir_intrinsic_image_dim(insn), !!nir_intrinsic_image_array(insn), false);
2129       unsigned int argCount = getNIRArgCount(target);
2130       uint16_t location = 0;
2131
2132       if (opInfo.has_dest) {
2133          LValues &newDefs = convert(&insn->dest);
2134          for (uint8_t i = 0u; i < newDefs.size(); ++i) {
2135             defs.push_back(newDefs[i]);
2136             mask |= 1 << i;
2137          }
2138       }
2139
2140       int lod_src = -1;
2141       bool bindless = false;
2142       switch (op) {
2143       case nir_intrinsic_bindless_image_atomic_add:
2144       case nir_intrinsic_bindless_image_atomic_and:
2145       case nir_intrinsic_bindless_image_atomic_comp_swap:
2146       case nir_intrinsic_bindless_image_atomic_exchange:
2147       case nir_intrinsic_bindless_image_atomic_imax:
2148       case nir_intrinsic_bindless_image_atomic_umax:
2149       case nir_intrinsic_bindless_image_atomic_imin:
2150       case nir_intrinsic_bindless_image_atomic_umin:
2151       case nir_intrinsic_bindless_image_atomic_or:
2152       case nir_intrinsic_bindless_image_atomic_xor:
2153       case nir_intrinsic_bindless_image_atomic_inc_wrap:
2154       case nir_intrinsic_bindless_image_atomic_dec_wrap:
2155          ty = getDType(insn);
2156          bindless = true;
2157          info->io.globalAccess |= 0x2;
2158          mask = 0x1;
2159          break;
2160       case nir_intrinsic_image_atomic_add:
2161       case nir_intrinsic_image_atomic_and:
2162       case nir_intrinsic_image_atomic_comp_swap:
2163       case nir_intrinsic_image_atomic_exchange:
2164       case nir_intrinsic_image_atomic_imax:
2165       case nir_intrinsic_image_atomic_umax:
2166       case nir_intrinsic_image_atomic_imin:
2167       case nir_intrinsic_image_atomic_umin:
2168       case nir_intrinsic_image_atomic_or:
2169       case nir_intrinsic_image_atomic_xor:
2170       case nir_intrinsic_image_atomic_inc_wrap:
2171       case nir_intrinsic_image_atomic_dec_wrap:
2172          ty = getDType(insn);
2173          bindless = false;
2174          info->io.globalAccess |= 0x2;
2175          mask = 0x1;
2176          break;
2177       case nir_intrinsic_bindless_image_load:
2178       case nir_intrinsic_image_load:
2179          ty = TYPE_U32;
2180          bindless = op == nir_intrinsic_bindless_image_load;
2181          info->io.globalAccess |= 0x1;
2182          lod_src = 4;
2183          break;
2184       case nir_intrinsic_bindless_image_store:
2185       case nir_intrinsic_image_store:
2186          ty = TYPE_U32;
2187          bindless = op == nir_intrinsic_bindless_image_store;
2188          info->io.globalAccess |= 0x2;
2189          lod_src = 5;
2190          mask = 0xf;
2191          break;
2192       case nir_intrinsic_bindless_image_samples:
2193       case nir_intrinsic_image_samples:
2194          ty = TYPE_U32;
2195          bindless = op == nir_intrinsic_bindless_image_samples;
2196          mask = 0x8;
2197          break;
2198       case nir_intrinsic_bindless_image_size:
2199       case nir_intrinsic_image_size:
2200          ty = TYPE_U32;
2201          bindless = op == nir_intrinsic_bindless_image_size;
2202          break;
2203       default:
2204          unreachable("unhandled image opcode");
2205          break;
2206       }
2207
2208       if (bindless)
2209          indirect = getSrc(&insn->src[0], 0);
2210       else
2211          location = getIndirect(&insn->src[0], 0, indirect);
2212
2213       // coords
2214       if (opInfo.num_srcs >= 2)
2215          for (unsigned int i = 0u; i < argCount; ++i)
2216             srcs.push_back(getSrc(&insn->src[1], i));
2217
2218       // the sampler is just another src added after coords
2219       if (opInfo.num_srcs >= 3 && target.isMS())
2220          srcs.push_back(getSrc(&insn->src[2], 0));
2221
2222       if (opInfo.num_srcs >= 4 && lod_src != 4) {
2223          unsigned components = opInfo.src_components[3] ? opInfo.src_components[3] : insn->num_components;
2224          for (uint8_t i = 0u; i < components; ++i)
2225             srcs.push_back(getSrc(&insn->src[3], i));
2226       }
2227
2228       if (opInfo.num_srcs >= 5 && lod_src != 5)
2229          // 1 for aotmic swap
2230          for (uint8_t i = 0u; i < opInfo.src_components[4]; ++i)
2231             srcs.push_back(getSrc(&insn->src[4], i));
2232
2233       TexInstruction *texi = mkTex(getOperation(op), target.getEnum(), location, 0, defs, srcs);
2234       texi->tex.bindless = bindless;
2235       texi->tex.format = nv50_ir::TexInstruction::translateImgFormat(nir_intrinsic_format(insn));
2236       texi->tex.mask = mask;
2237       texi->cache = convert(nir_intrinsic_access(insn));
2238       texi->setType(ty);
2239       texi->subOp = getSubOp(op);
2240
2241       if (indirect)
2242          texi->setIndirectR(indirect);
2243
2244       break;
2245    }
2246    case nir_intrinsic_store_shared: {
2247       DataType sType = getSType(insn->src[0], false, false);
2248       Value *indirectOffset;
2249       uint32_t offset = getIndirect(&insn->src[1], 0, indirectOffset);
2250
2251       for (uint8_t i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
2252          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2253             continue;
2254          Symbol *sym = mkSymbol(FILE_MEMORY_SHARED, 0, sType, offset + i * typeSizeof(sType));
2255          mkStore(OP_STORE, sType, sym, indirectOffset, getSrc(&insn->src[0], i));
2256       }
2257       break;
2258    }
2259    case nir_intrinsic_load_shared: {
2260       const DataType dType = getDType(insn);
2261       LValues &newDefs = convert(&insn->dest);
2262       Value *indirectOffset;
2263       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2264
2265       for (uint8_t i = 0u; i < dest_components; ++i)
2266          loadFrom(FILE_MEMORY_SHARED, 0, dType, newDefs[i], offset, i, indirectOffset);
2267
2268       break;
2269    }
2270    case nir_intrinsic_control_barrier: {
2271       // TODO: add flag to shader_info
2272       info->numBarriers = 1;
2273       Instruction *bar = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2274       bar->fixed = 1;
2275       bar->subOp = NV50_IR_SUBOP_BAR_SYNC;
2276       break;
2277    }
2278    case nir_intrinsic_group_memory_barrier:
2279    case nir_intrinsic_memory_barrier:
2280    case nir_intrinsic_memory_barrier_buffer:
2281    case nir_intrinsic_memory_barrier_image:
2282    case nir_intrinsic_memory_barrier_shared: {
2283       Instruction *bar = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2284       bar->fixed = 1;
2285       bar->subOp = getSubOp(op);
2286       break;
2287    }
2288    case nir_intrinsic_memory_barrier_tcs_patch:
2289       break;
2290    case nir_intrinsic_shader_clock: {
2291       const DataType dType = getDType(insn);
2292       LValues &newDefs = convert(&insn->dest);
2293
2294       loadImm(newDefs[0], 0u);
2295       mkOp1(OP_RDSV, dType, newDefs[1], mkSysVal(SV_CLOCK, 0))->fixed = 1;
2296       break;
2297    }
2298    case nir_intrinsic_load_global: {
2299       const DataType dType = getDType(insn);
2300       LValues &newDefs = convert(&insn->dest);
2301       Value *indirectOffset;
2302       uint32_t offset = getIndirect(&insn->src[0], 0, indirectOffset);
2303
2304       for (auto i = 0u; i < dest_components; ++i)
2305          loadFrom(FILE_MEMORY_GLOBAL, 0, dType, newDefs[i], offset, i, indirectOffset);
2306
2307       info->io.globalAccess |= 0x1;
2308       break;
2309    }
2310    case nir_intrinsic_store_global: {
2311       DataType sType = getSType(insn->src[0], false, false);
2312
2313       for (auto i = 0u; i < nir_intrinsic_src_components(insn, 0); ++i) {
2314          if (!((1u << i) & nir_intrinsic_write_mask(insn)))
2315             continue;
2316          if (typeSizeof(sType) == 8) {
2317             Value *split[2];
2318             mkSplit(split, 4, getSrc(&insn->src[0], i));
2319
2320             Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, i * typeSizeof(sType));
2321             mkStore(OP_STORE, TYPE_U32, sym, getSrc(&insn->src[1], 0), split[0]);
2322
2323             sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, TYPE_U32, i * typeSizeof(sType) + 4);
2324             mkStore(OP_STORE, TYPE_U32, sym, getSrc(&insn->src[1], 0), split[1]);
2325          } else {
2326             Symbol *sym = mkSymbol(FILE_MEMORY_GLOBAL, 0, sType, i * typeSizeof(sType));
2327             mkStore(OP_STORE, sType, sym, getSrc(&insn->src[1], 0), getSrc(&insn->src[0], i));
2328          }
2329       }
2330
2331       info->io.globalAccess |= 0x2;
2332       break;
2333    }
2334    default:
2335       ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
2336       return false;
2337    }
2338
2339    return true;
2340 }
2341
2342 bool
2343 Converter::visit(nir_jump_instr *insn)
2344 {
2345    switch (insn->type) {
2346    case nir_jump_return:
2347       // TODO: this only works in the main function
2348       mkFlow(OP_BRA, exit, CC_ALWAYS, NULL);
2349       bb->cfg.attach(&exit->cfg, Graph::Edge::CROSS);
2350       break;
2351    case nir_jump_break:
2352    case nir_jump_continue: {
2353       bool isBreak = insn->type == nir_jump_break;
2354       nir_block *block = insn->instr.block;
2355       BasicBlock *target = convert(block->successors[0]);
2356       mkFlow(isBreak ? OP_BREAK : OP_CONT, target, CC_ALWAYS, NULL);
2357       bb->cfg.attach(&target->cfg, isBreak ? Graph::Edge::CROSS : Graph::Edge::BACK);
2358       break;
2359    }
2360    default:
2361       ERROR("unknown nir_jump_type %u\n", insn->type);
2362       return false;
2363    }
2364
2365    return true;
2366 }
2367
2368 Value*
2369 Converter::convert(nir_load_const_instr *insn, uint8_t idx)
2370 {
2371    Value *val;
2372
2373    if (immInsertPos)
2374       setPosition(immInsertPos, true);
2375    else
2376       setPosition(bb, false);
2377
2378    switch (insn->def.bit_size) {
2379    case 64:
2380       val = loadImm(getSSA(8), insn->value[idx].u64);
2381       break;
2382    case 32:
2383       val = loadImm(getSSA(4), insn->value[idx].u32);
2384       break;
2385    case 16:
2386       val = loadImm(getSSA(2), insn->value[idx].u16);
2387       break;
2388    case 8:
2389       val = loadImm(getSSA(1), insn->value[idx].u8);
2390       break;
2391    default:
2392       unreachable("unhandled bit size!\n");
2393    }
2394    setPosition(bb, true);
2395    return val;
2396 }
2397
2398 bool
2399 Converter::visit(nir_load_const_instr *insn)
2400 {
2401    assert(insn->def.bit_size <= 64);
2402    immediates[insn->def.index] = insn;
2403    return true;
2404 }
2405
2406 #define DEFAULT_CHECKS \
2407       if (insn->dest.dest.ssa.num_components > 1) { \
2408          ERROR("nir_alu_instr only supported with 1 component!\n"); \
2409          return false; \
2410       } \
2411       if (insn->dest.write_mask != 1) { \
2412          ERROR("nir_alu_instr only with write_mask of 1 supported!\n"); \
2413          return false; \
2414       }
2415 bool
2416 Converter::visit(nir_alu_instr *insn)
2417 {
2418    const nir_op op = insn->op;
2419    const nir_op_info &info = nir_op_infos[op];
2420    DataType dType = getDType(insn);
2421    const std::vector<DataType> sTypes = getSTypes(insn);
2422
2423    Instruction *oldPos = this->bb->getExit();
2424
2425    switch (op) {
2426    case nir_op_fabs:
2427    case nir_op_iabs:
2428    case nir_op_fadd:
2429    case nir_op_iadd:
2430    case nir_op_iand:
2431    case nir_op_fceil:
2432    case nir_op_fcos:
2433    case nir_op_fddx:
2434    case nir_op_fddx_coarse:
2435    case nir_op_fddx_fine:
2436    case nir_op_fddy:
2437    case nir_op_fddy_coarse:
2438    case nir_op_fddy_fine:
2439    case nir_op_fdiv:
2440    case nir_op_idiv:
2441    case nir_op_udiv:
2442    case nir_op_fexp2:
2443    case nir_op_ffloor:
2444    case nir_op_ffma:
2445    case nir_op_flog2:
2446    case nir_op_fmax:
2447    case nir_op_imax:
2448    case nir_op_umax:
2449    case nir_op_fmin:
2450    case nir_op_imin:
2451    case nir_op_umin:
2452    case nir_op_fmod:
2453    case nir_op_imod:
2454    case nir_op_umod:
2455    case nir_op_fmul:
2456    case nir_op_imul:
2457    case nir_op_imul_high:
2458    case nir_op_umul_high:
2459    case nir_op_fneg:
2460    case nir_op_ineg:
2461    case nir_op_inot:
2462    case nir_op_ior:
2463    case nir_op_pack_64_2x32_split:
2464    case nir_op_fpow:
2465    case nir_op_frcp:
2466    case nir_op_frem:
2467    case nir_op_irem:
2468    case nir_op_frsq:
2469    case nir_op_fsat:
2470    case nir_op_ishr:
2471    case nir_op_ushr:
2472    case nir_op_fsin:
2473    case nir_op_fsqrt:
2474    case nir_op_ftrunc:
2475    case nir_op_ishl:
2476    case nir_op_ixor: {
2477       DEFAULT_CHECKS;
2478       LValues &newDefs = convert(&insn->dest);
2479       operation preOp = preOperationNeeded(op);
2480       if (preOp != OP_NOP) {
2481          assert(info.num_inputs < 2);
2482          Value *tmp = getSSA(typeSizeof(dType));
2483          Instruction *i0 = mkOp(preOp, dType, tmp);
2484          Instruction *i1 = mkOp(getOperation(op), dType, newDefs[0]);
2485          if (info.num_inputs) {
2486             i0->setSrc(0, getSrc(&insn->src[0]));
2487             i1->setSrc(0, tmp);
2488          }
2489          i1->subOp = getSubOp(op);
2490       } else {
2491          Instruction *i = mkOp(getOperation(op), dType, newDefs[0]);
2492          for (unsigned s = 0u; s < info.num_inputs; ++s) {
2493             i->setSrc(s, getSrc(&insn->src[s]));
2494          }
2495          i->subOp = getSubOp(op);
2496       }
2497       break;
2498    }
2499    case nir_op_ifind_msb:
2500    case nir_op_ufind_msb: {
2501       DEFAULT_CHECKS;
2502       LValues &newDefs = convert(&insn->dest);
2503       dType = sTypes[0];
2504       mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2505       break;
2506    }
2507    case nir_op_fround_even: {
2508       DEFAULT_CHECKS;
2509       LValues &newDefs = convert(&insn->dest);
2510       mkCvt(OP_CVT, dType, newDefs[0], dType, getSrc(&insn->src[0]))->rnd = ROUND_NI;
2511       break;
2512    }
2513    // convert instructions
2514    case nir_op_f2f32:
2515    case nir_op_f2i32:
2516    case nir_op_f2u32:
2517    case nir_op_i2f32:
2518    case nir_op_i2i32:
2519    case nir_op_u2f32:
2520    case nir_op_u2u32:
2521    case nir_op_f2f64:
2522    case nir_op_f2i64:
2523    case nir_op_f2u64:
2524    case nir_op_i2f64:
2525    case nir_op_i2i64:
2526    case nir_op_u2f64:
2527    case nir_op_u2u64: {
2528       DEFAULT_CHECKS;
2529       LValues &newDefs = convert(&insn->dest);
2530       Instruction *i = mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
2531       if (op == nir_op_f2i32 || op == nir_op_f2i64 || op == nir_op_f2u32 || op == nir_op_f2u64)
2532          i->rnd = ROUND_Z;
2533       i->sType = sTypes[0];
2534       break;
2535    }
2536    // compare instructions
2537    case nir_op_feq32:
2538    case nir_op_ieq32:
2539    case nir_op_fge32:
2540    case nir_op_ige32:
2541    case nir_op_uge32:
2542    case nir_op_flt32:
2543    case nir_op_ilt32:
2544    case nir_op_ult32:
2545    case nir_op_fne32:
2546    case nir_op_ine32: {
2547       DEFAULT_CHECKS;
2548       LValues &newDefs = convert(&insn->dest);
2549       Instruction *i = mkCmp(getOperation(op),
2550                              getCondCode(op),
2551                              dType,
2552                              newDefs[0],
2553                              dType,
2554                              getSrc(&insn->src[0]),
2555                              getSrc(&insn->src[1]));
2556       if (info.num_inputs == 3)
2557          i->setSrc(2, getSrc(&insn->src[2]));
2558       i->sType = sTypes[0];
2559       break;
2560    }
2561    // those are weird ALU ops and need special handling, because
2562    //   1. they are always componend based
2563    //   2. they basically just merge multiple values into one data type
2564    case nir_op_mov:
2565       if (!insn->dest.dest.is_ssa && insn->dest.dest.reg.reg->num_array_elems) {
2566          nir_reg_dest& reg = insn->dest.dest.reg;
2567          uint32_t goffset = regToLmemOffset[reg.reg->index];
2568          uint8_t comps = reg.reg->num_components;
2569          uint8_t size = reg.reg->bit_size / 8;
2570          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2571          uint32_t aoffset = csize * reg.base_offset;
2572          Value *indirect = NULL;
2573
2574          if (reg.indirect)
2575             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS),
2576                               getSrc(reg.indirect, 0), mkImm(csize));
2577
2578          for (uint8_t i = 0u; i < comps; ++i) {
2579             if (!((1u << i) & insn->dest.write_mask))
2580                continue;
2581
2582             Symbol *sym = mkSymbol(FILE_MEMORY_LOCAL, 0, dType, goffset + aoffset + i * size);
2583             mkStore(OP_STORE, dType, sym, indirect, getSrc(&insn->src[0], i));
2584          }
2585          break;
2586       } else if (!insn->src[0].src.is_ssa && insn->src[0].src.reg.reg->num_array_elems) {
2587          LValues &newDefs = convert(&insn->dest);
2588          nir_reg_src& reg = insn->src[0].src.reg;
2589          uint32_t goffset = regToLmemOffset[reg.reg->index];
2590          // uint8_t comps = reg.reg->num_components;
2591          uint8_t size = reg.reg->bit_size / 8;
2592          uint8_t csize = 4 * size; // TODO after fixing MemoryOpts: comps * size;
2593          uint32_t aoffset = csize * reg.base_offset;
2594          Value *indirect = NULL;
2595
2596          if (reg.indirect)
2597             indirect = mkOp2v(OP_MUL, TYPE_U32, getSSA(4, FILE_ADDRESS), getSrc(reg.indirect, 0), mkImm(csize));
2598
2599          for (uint8_t i = 0u; i < newDefs.size(); ++i)
2600             loadFrom(FILE_MEMORY_LOCAL, 0, dType, newDefs[i], goffset + aoffset, i, indirect);
2601
2602          break;
2603       } else {
2604          LValues &newDefs = convert(&insn->dest);
2605          for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2606             mkMov(newDefs[c], getSrc(&insn->src[0], c), dType);
2607          }
2608       }
2609       break;
2610    case nir_op_vec2:
2611    case nir_op_vec3:
2612    case nir_op_vec4:
2613    case nir_op_vec8:
2614    case nir_op_vec16: {
2615       LValues &newDefs = convert(&insn->dest);
2616       for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
2617          mkMov(newDefs[c], getSrc(&insn->src[c]), dType);
2618       }
2619       break;
2620    }
2621    // (un)pack
2622    case nir_op_pack_64_2x32: {
2623       LValues &newDefs = convert(&insn->dest);
2624       Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
2625       merge->setSrc(0, getSrc(&insn->src[0], 0));
2626       merge->setSrc(1, getSrc(&insn->src[0], 1));
2627       break;
2628    }
2629    case nir_op_pack_half_2x16_split: {
2630       LValues &newDefs = convert(&insn->dest);
2631       Value *tmpH = getSSA();
2632       Value *tmpL = getSSA();
2633
2634       mkCvt(OP_CVT, TYPE_F16, tmpL, TYPE_F32, getSrc(&insn->src[0]));
2635       mkCvt(OP_CVT, TYPE_F16, tmpH, TYPE_F32, getSrc(&insn->src[1]));
2636       mkOp3(OP_INSBF, TYPE_U32, newDefs[0], tmpH, mkImm(0x1010), tmpL);
2637       break;
2638    }
2639    case nir_op_unpack_half_2x16_split_x:
2640    case nir_op_unpack_half_2x16_split_y: {
2641       LValues &newDefs = convert(&insn->dest);
2642       Instruction *cvt = mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, getSrc(&insn->src[0]));
2643       if (op == nir_op_unpack_half_2x16_split_y)
2644          cvt->subOp = 1;
2645       break;
2646    }
2647    case nir_op_unpack_64_2x32: {
2648       LValues &newDefs = convert(&insn->dest);
2649       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, newDefs[1]);
2650       break;
2651    }
2652    case nir_op_unpack_64_2x32_split_x: {
2653       LValues &newDefs = convert(&insn->dest);
2654       mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, getSSA());
2655       break;
2656    }
2657    case nir_op_unpack_64_2x32_split_y: {
2658       LValues &newDefs = convert(&insn->dest);
2659       mkOp1(OP_SPLIT, dType, getSSA(), getSrc(&insn->src[0]))->setDef(1, newDefs[0]);
2660       break;
2661    }
2662    // special instructions
2663    case nir_op_fsign:
2664    case nir_op_isign: {
2665       DEFAULT_CHECKS;
2666       DataType iType;
2667       if (::isFloatType(dType))
2668          iType = TYPE_F32;
2669       else
2670          iType = TYPE_S32;
2671
2672       LValues &newDefs = convert(&insn->dest);
2673       LValue *val0 = getScratch();
2674       LValue *val1 = getScratch();
2675       mkCmp(OP_SET, CC_GT, iType, val0, dType, getSrc(&insn->src[0]), zero);
2676       mkCmp(OP_SET, CC_LT, iType, val1, dType, getSrc(&insn->src[0]), zero);
2677
2678       if (dType == TYPE_F64) {
2679          mkOp2(OP_SUB, iType, val0, val0, val1);
2680          mkCvt(OP_CVT, TYPE_F64, newDefs[0], iType, val0);
2681       } else if (dType == TYPE_S64 || dType == TYPE_U64) {
2682          mkOp2(OP_SUB, iType, val0, val1, val0);
2683          mkOp2(OP_SHR, iType, val1, val0, loadImm(NULL, 31));
2684          mkOp2(OP_MERGE, dType, newDefs[0], val0, val1);
2685       } else if (::isFloatType(dType))
2686          mkOp2(OP_SUB, iType, newDefs[0], val0, val1);
2687       else
2688          mkOp2(OP_SUB, iType, newDefs[0], val1, val0);
2689       break;
2690    }
2691    case nir_op_fcsel:
2692    case nir_op_b32csel: {
2693       DEFAULT_CHECKS;
2694       LValues &newDefs = convert(&insn->dest);
2695       mkCmp(OP_SLCT, CC_NE, dType, newDefs[0], sTypes[0], getSrc(&insn->src[1]), getSrc(&insn->src[2]), getSrc(&insn->src[0]));
2696       break;
2697    }
2698    case nir_op_ibitfield_extract:
2699    case nir_op_ubitfield_extract: {
2700       DEFAULT_CHECKS;
2701       Value *tmp = getSSA();
2702       LValues &newDefs = convert(&insn->dest);
2703       mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2704       mkOp2(OP_EXTBF, dType, newDefs[0], getSrc(&insn->src[0]), tmp);
2705       break;
2706    }
2707    case nir_op_bfm: {
2708       DEFAULT_CHECKS;
2709       LValues &newDefs = convert(&insn->dest);
2710       mkOp2(OP_BMSK, dType, newDefs[0], getSrc(&insn->src[1]), getSrc(&insn->src[0]))->subOp = NV50_IR_SUBOP_BMSK_W;
2711       break;
2712    }
2713    case nir_op_bitfield_insert: {
2714       DEFAULT_CHECKS;
2715       LValues &newDefs = convert(&insn->dest);
2716       LValue *temp = getSSA();
2717       mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
2718       mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
2719       break;
2720    }
2721    case nir_op_bit_count: {
2722       DEFAULT_CHECKS;
2723       LValues &newDefs = convert(&insn->dest);
2724       mkOp2(OP_POPCNT, dType, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[0]));
2725       break;
2726    }
2727    case nir_op_bitfield_reverse: {
2728       DEFAULT_CHECKS;
2729       LValues &newDefs = convert(&insn->dest);
2730       mkOp1(OP_BREV, TYPE_U32, newDefs[0], getSrc(&insn->src[0]));
2731       break;
2732    }
2733    case nir_op_find_lsb: {
2734       DEFAULT_CHECKS;
2735       LValues &newDefs = convert(&insn->dest);
2736       Value *tmp = getSSA();
2737       mkOp1(OP_BREV, TYPE_U32, tmp, getSrc(&insn->src[0]));
2738       mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2739       break;
2740    }
2741    case nir_op_extract_u8: {
2742       DEFAULT_CHECKS;
2743       LValues &newDefs = convert(&insn->dest);
2744       Value *prmt = getSSA();
2745       mkOp2(OP_OR, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x4440));
2746       mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
2747       break;
2748    }
2749    case nir_op_extract_i8: {
2750       DEFAULT_CHECKS;
2751       LValues &newDefs = convert(&insn->dest);
2752       Value *prmt = getSSA();
2753       mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x1111), loadImm(NULL, 0x8880));
2754       mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
2755       break;
2756    }
2757    case nir_op_extract_u16: {
2758       DEFAULT_CHECKS;
2759       LValues &newDefs = convert(&insn->dest);
2760       Value *prmt = getSSA();
2761       mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x22), loadImm(NULL, 0x4410));
2762       mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
2763       break;
2764    }
2765    case nir_op_extract_i16: {
2766       DEFAULT_CHECKS;
2767       LValues &newDefs = convert(&insn->dest);
2768       Value *prmt = getSSA();
2769       mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x2222), loadImm(NULL, 0x9910));
2770       mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
2771       break;
2772    }
2773    case nir_op_urol: {
2774       DEFAULT_CHECKS;
2775       LValues &newDefs = convert(&insn->dest);
2776       mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]),
2777             getSrc(&insn->src[1]), getSrc(&insn->src[0]))
2778          ->subOp = NV50_IR_SUBOP_SHF_L |
2779                    NV50_IR_SUBOP_SHF_W |
2780                    NV50_IR_SUBOP_SHF_HI;
2781       break;
2782    }
2783    case nir_op_uror: {
2784       DEFAULT_CHECKS;
2785       LValues &newDefs = convert(&insn->dest);
2786       mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]),
2787             getSrc(&insn->src[1]), getSrc(&insn->src[0]))
2788          ->subOp = NV50_IR_SUBOP_SHF_R |
2789                    NV50_IR_SUBOP_SHF_W |
2790                    NV50_IR_SUBOP_SHF_LO;
2791       break;
2792    }
2793    // boolean conversions
2794    case nir_op_b2f32: {
2795       DEFAULT_CHECKS;
2796       LValues &newDefs = convert(&insn->dest);
2797       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1.0f));
2798       break;
2799    }
2800    case nir_op_b2f64: {
2801       DEFAULT_CHECKS;
2802       LValues &newDefs = convert(&insn->dest);
2803       Value *tmp = getSSA(4);
2804       mkOp2(OP_AND, TYPE_U32, tmp, getSrc(&insn->src[0]), loadImm(NULL, 0x3ff00000));
2805       mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
2806       break;
2807    }
2808    case nir_op_f2b32:
2809    case nir_op_i2b32: {
2810       DEFAULT_CHECKS;
2811       LValues &newDefs = convert(&insn->dest);
2812       Value *src1;
2813       if (typeSizeof(sTypes[0]) == 8) {
2814          src1 = loadImm(getSSA(8), 0.0);
2815       } else {
2816          src1 = zero;
2817       }
2818       CondCode cc = op == nir_op_f2b32 ? CC_NEU : CC_NE;
2819       mkCmp(OP_SET, cc, TYPE_U32, newDefs[0], sTypes[0], getSrc(&insn->src[0]), src1);
2820       break;
2821    }
2822    case nir_op_b2i32: {
2823       DEFAULT_CHECKS;
2824       LValues &newDefs = convert(&insn->dest);
2825       mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1));
2826       break;
2827    }
2828    case nir_op_b2i64: {
2829       DEFAULT_CHECKS;
2830       LValues &newDefs = convert(&insn->dest);
2831       LValue *def = getScratch();
2832       mkOp2(OP_AND, TYPE_U32, def, getSrc(&insn->src[0]), loadImm(NULL, 1));
2833       mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
2834       break;
2835    }
2836    default:
2837       ERROR("unknown nir_op %s\n", info.name);
2838       return false;
2839    }
2840
2841    if (!oldPos) {
2842       oldPos = this->bb->getEntry();
2843       oldPos->precise = insn->exact;
2844    }
2845
2846    if (unlikely(!oldPos))
2847       return true;
2848
2849    while (oldPos->next) {
2850       oldPos = oldPos->next;
2851       oldPos->precise = insn->exact;
2852    }
2853    oldPos->saturate = insn->dest.saturate;
2854
2855    return true;
2856 }
2857 #undef DEFAULT_CHECKS
2858
2859 bool
2860 Converter::visit(nir_ssa_undef_instr *insn)
2861 {
2862    LValues &newDefs = convert(&insn->def);
2863    for (uint8_t i = 0u; i < insn->def.num_components; ++i) {
2864       mkOp(OP_NOP, TYPE_NONE, newDefs[i]);
2865    }
2866    return true;
2867 }
2868
2869 #define CASE_SAMPLER(ty) \
2870    case GLSL_SAMPLER_DIM_ ## ty : \
2871       if (isArray && !isShadow) \
2872          return TEX_TARGET_ ## ty ## _ARRAY; \
2873       else if (!isArray && isShadow) \
2874          return TEX_TARGET_## ty ## _SHADOW; \
2875       else if (isArray && isShadow) \
2876          return TEX_TARGET_## ty ## _ARRAY_SHADOW; \
2877       else \
2878          return TEX_TARGET_ ## ty
2879
2880 TexTarget
2881 Converter::convert(glsl_sampler_dim dim, bool isArray, bool isShadow)
2882 {
2883    switch (dim) {
2884    CASE_SAMPLER(1D);
2885    CASE_SAMPLER(2D);
2886    CASE_SAMPLER(CUBE);
2887    case GLSL_SAMPLER_DIM_3D:
2888       return TEX_TARGET_3D;
2889    case GLSL_SAMPLER_DIM_MS:
2890       if (isArray)
2891          return TEX_TARGET_2D_MS_ARRAY;
2892       return TEX_TARGET_2D_MS;
2893    case GLSL_SAMPLER_DIM_RECT:
2894       if (isShadow)
2895          return TEX_TARGET_RECT_SHADOW;
2896       return TEX_TARGET_RECT;
2897    case GLSL_SAMPLER_DIM_BUF:
2898       return TEX_TARGET_BUFFER;
2899    case GLSL_SAMPLER_DIM_EXTERNAL:
2900       return TEX_TARGET_2D;
2901    default:
2902       ERROR("unknown glsl_sampler_dim %u\n", dim);
2903       assert(false);
2904       return TEX_TARGET_COUNT;
2905    }
2906 }
2907 #undef CASE_SAMPLER
2908
2909 Value*
2910 Converter::applyProjection(Value *src, Value *proj)
2911 {
2912    if (!proj)
2913       return src;
2914    return mkOp2v(OP_MUL, TYPE_F32, getScratch(), src, proj);
2915 }
2916
2917 unsigned int
2918 Converter::getNIRArgCount(TexInstruction::Target& target)
2919 {
2920    unsigned int result = target.getArgCount();
2921    if (target.isCube() && target.isArray())
2922       result--;
2923    if (target.isMS())
2924       result--;
2925    return result;
2926 }
2927
2928 CacheMode
2929 Converter::convert(enum gl_access_qualifier access)
2930 {
2931    switch (access) {
2932    case ACCESS_VOLATILE:
2933       return CACHE_CV;
2934    case ACCESS_COHERENT:
2935       return CACHE_CG;
2936    default:
2937       return CACHE_CA;
2938    }
2939 }
2940
2941 bool
2942 Converter::visit(nir_tex_instr *insn)
2943 {
2944    switch (insn->op) {
2945    case nir_texop_lod:
2946    case nir_texop_query_levels:
2947    case nir_texop_tex:
2948    case nir_texop_texture_samples:
2949    case nir_texop_tg4:
2950    case nir_texop_txb:
2951    case nir_texop_txd:
2952    case nir_texop_txf:
2953    case nir_texop_txf_ms:
2954    case nir_texop_txl:
2955    case nir_texop_txs: {
2956       LValues &newDefs = convert(&insn->dest);
2957       std::vector<Value*> srcs;
2958       std::vector<Value*> defs;
2959       std::vector<nir_src*> offsets;
2960       uint8_t mask = 0;
2961       bool lz = false;
2962       Value *proj = NULL;
2963       TexInstruction::Target target = convert(insn->sampler_dim, insn->is_array, insn->is_shadow);
2964       operation op = getOperation(insn->op);
2965
2966       int r, s;
2967       int biasIdx = nir_tex_instr_src_index(insn, nir_tex_src_bias);
2968       int compIdx = nir_tex_instr_src_index(insn, nir_tex_src_comparator);
2969       int coordsIdx = nir_tex_instr_src_index(insn, nir_tex_src_coord);
2970       int ddxIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddx);
2971       int ddyIdx = nir_tex_instr_src_index(insn, nir_tex_src_ddy);
2972       int msIdx = nir_tex_instr_src_index(insn, nir_tex_src_ms_index);
2973       int lodIdx = nir_tex_instr_src_index(insn, nir_tex_src_lod);
2974       int offsetIdx = nir_tex_instr_src_index(insn, nir_tex_src_offset);
2975       int projIdx = nir_tex_instr_src_index(insn, nir_tex_src_projector);
2976       int sampOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_offset);
2977       int texOffIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_offset);
2978       int sampHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_sampler_handle);
2979       int texHandleIdx = nir_tex_instr_src_index(insn, nir_tex_src_texture_handle);
2980
2981       bool bindless = sampHandleIdx != -1 || texHandleIdx != -1;
2982       assert((sampHandleIdx != -1) == (texHandleIdx != -1));
2983
2984       if (projIdx != -1)
2985          proj = mkOp1v(OP_RCP, TYPE_F32, getScratch(), getSrc(&insn->src[projIdx].src, 0));
2986
2987       srcs.resize(insn->coord_components);
2988       for (uint8_t i = 0u; i < insn->coord_components; ++i)
2989          srcs[i] = applyProjection(getSrc(&insn->src[coordsIdx].src, i), proj);
2990
2991       // sometimes we get less args than target.getArgCount, but codegen expects the latter
2992       if (insn->coord_components) {
2993          uint32_t argCount = target.getArgCount();
2994
2995          if (target.isMS())
2996             argCount -= 1;
2997
2998          for (uint32_t i = 0u; i < (argCount - insn->coord_components); ++i)
2999             srcs.push_back(getSSA());
3000       }
3001
3002       if (insn->op == nir_texop_texture_samples)
3003          srcs.push_back(zero);
3004       else if (!insn->num_srcs)
3005          srcs.push_back(loadImm(NULL, 0));
3006       if (biasIdx != -1)
3007          srcs.push_back(getSrc(&insn->src[biasIdx].src, 0));
3008       if (lodIdx != -1)
3009          srcs.push_back(getSrc(&insn->src[lodIdx].src, 0));
3010       else if (op == OP_TXF)
3011          lz = true;
3012       if (msIdx != -1)
3013          srcs.push_back(getSrc(&insn->src[msIdx].src, 0));
3014       if (offsetIdx != -1)
3015          offsets.push_back(&insn->src[offsetIdx].src);
3016       if (compIdx != -1)
3017          srcs.push_back(applyProjection(getSrc(&insn->src[compIdx].src, 0), proj));
3018       if (texOffIdx != -1) {
3019          srcs.push_back(getSrc(&insn->src[texOffIdx].src, 0));
3020          texOffIdx = srcs.size() - 1;
3021       }
3022       if (sampOffIdx != -1) {
3023          srcs.push_back(getSrc(&insn->src[sampOffIdx].src, 0));
3024          sampOffIdx = srcs.size() - 1;
3025       }
3026       if (bindless) {
3027          // currently we use the lower bits
3028          Value *split[2];
3029          Value *handle = getSrc(&insn->src[sampHandleIdx].src, 0);
3030
3031          mkSplit(split, 4, handle);
3032
3033          srcs.push_back(split[0]);
3034          texOffIdx = srcs.size() - 1;
3035       }
3036
3037       r = bindless ? 0xff : insn->texture_index;
3038       s = bindless ? 0x1f : insn->sampler_index;
3039
3040       defs.resize(newDefs.size());
3041       for (uint8_t d = 0u; d < newDefs.size(); ++d) {
3042          defs[d] = newDefs[d];
3043          mask |= 1 << d;
3044       }
3045       if (target.isMS() || (op == OP_TEX && prog->getType() != Program::TYPE_FRAGMENT))
3046          lz = true;
3047
3048       TexInstruction *texi = mkTex(op, target.getEnum(), r, s, defs, srcs);
3049       texi->tex.levelZero = lz;
3050       texi->tex.mask = mask;
3051       texi->tex.bindless = bindless;
3052
3053       if (texOffIdx != -1)
3054          texi->tex.rIndirectSrc = texOffIdx;
3055       if (sampOffIdx != -1)
3056          texi->tex.sIndirectSrc = sampOffIdx;
3057
3058       switch (insn->op) {
3059       case nir_texop_tg4:
3060          if (!target.isShadow())
3061             texi->tex.gatherComp = insn->component;
3062          break;
3063       case nir_texop_txs:
3064          texi->tex.query = TXQ_DIMS;
3065          break;
3066       case nir_texop_texture_samples:
3067          texi->tex.mask = 0x4;
3068          texi->tex.query = TXQ_TYPE;
3069          break;
3070       case nir_texop_query_levels:
3071          texi->tex.mask = 0x8;
3072          texi->tex.query = TXQ_DIMS;
3073          break;
3074       default:
3075          break;
3076       }
3077
3078       texi->tex.useOffsets = offsets.size();
3079       if (texi->tex.useOffsets) {
3080          for (uint8_t s = 0; s < texi->tex.useOffsets; ++s) {
3081             for (uint32_t c = 0u; c < 3; ++c) {
3082                uint8_t s2 = std::min(c, target.getDim() - 1);
3083                texi->offset[s][c].set(getSrc(offsets[s], s2));
3084                texi->offset[s][c].setInsn(texi);
3085             }
3086          }
3087       }
3088
3089       if (op == OP_TXG && offsetIdx == -1) {
3090          if (nir_tex_instr_has_explicit_tg4_offsets(insn)) {
3091             texi->tex.useOffsets = 4;
3092             setPosition(texi, false);
3093             for (uint8_t i = 0; i < 4; ++i) {
3094                for (uint8_t j = 0; j < 2; ++j) {
3095                   texi->offset[i][j].set(loadImm(NULL, insn->tg4_offsets[i][j]));
3096                   texi->offset[i][j].setInsn(texi);
3097                }
3098             }
3099             setPosition(texi, true);
3100          }
3101       }
3102
3103       if (ddxIdx != -1 && ddyIdx != -1) {
3104          for (uint8_t c = 0u; c < target.getDim() + target.isCube(); ++c) {
3105             texi->dPdx[c].set(getSrc(&insn->src[ddxIdx].src, c));
3106             texi->dPdy[c].set(getSrc(&insn->src[ddyIdx].src, c));
3107          }
3108       }
3109
3110       break;
3111    }
3112    default:
3113       ERROR("unknown nir_texop %u\n", insn->op);
3114       return false;
3115    }
3116    return true;
3117 }
3118
3119 bool
3120 Converter::run()
3121 {
3122    bool progress;
3123
3124    if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
3125       nir_print_shader(nir, stderr);
3126
3127    struct nir_lower_subgroups_options subgroup_options = {
3128       .subgroup_size = 32,
3129       .ballot_bit_size = 32,
3130    };
3131
3132    NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, (nir_lower_io_options)0);
3133    NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
3134    NIR_PASS_V(nir, nir_lower_regs_to_ssa);
3135    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
3136    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3137    NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
3138    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
3139
3140    /*TODO: improve this lowering/optimisation loop so that we can use
3141     *      nir_opt_idiv_const effectively before this.
3142     */
3143    NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_precise);
3144
3145    do {
3146       progress = false;
3147       NIR_PASS(progress, nir, nir_copy_prop);
3148       NIR_PASS(progress, nir, nir_opt_remove_phis);
3149       NIR_PASS(progress, nir, nir_opt_trivial_continues);
3150       NIR_PASS(progress, nir, nir_opt_cse);
3151       NIR_PASS(progress, nir, nir_opt_algebraic);
3152       NIR_PASS(progress, nir, nir_opt_constant_folding);
3153       NIR_PASS(progress, nir, nir_copy_prop);
3154       NIR_PASS(progress, nir, nir_opt_dce);
3155       NIR_PASS(progress, nir, nir_opt_dead_cf);
3156    } while (progress);
3157
3158    NIR_PASS_V(nir, nir_lower_bool_to_int32);
3159    NIR_PASS_V(nir, nir_lower_locals_to_regs);
3160    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
3161    NIR_PASS_V(nir, nir_convert_from_ssa, true);
3162
3163    // Garbage collect dead instructions
3164    nir_sweep(nir);
3165
3166    if (!parseNIR()) {
3167       ERROR("Couldn't prase NIR!\n");
3168       return false;
3169    }
3170
3171    if (!assignSlots()) {
3172       ERROR("Couldn't assign slots!\n");
3173       return false;
3174    }
3175
3176    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
3177       nir_print_shader(nir, stderr);
3178
3179    nir_foreach_function(function, nir) {
3180       if (!visit(function))
3181          return false;
3182    }
3183
3184    return true;
3185 }
3186
3187 } // unnamed namespace
3188
3189 namespace nv50_ir {
3190
3191 bool
3192 Program::makeFromNIR(struct nv50_ir_prog_info *info)
3193 {
3194    nir_shader *nir = (nir_shader*)info->bin.source;
3195    Converter converter(this, nir, info);
3196    bool result = converter.run();
3197    if (!result)
3198       return result;
3199    LoweringHelper lowering;
3200    lowering.run(this);
3201    tlsSize = info->bin.tlsSpace;
3202    return result;
3203 }
3204
3205 } // namespace nv50_ir
3206
3207 static nir_shader_compiler_options
3208 nvir_nir_shader_compiler_options(int chipset)
3209 {
3210    nir_shader_compiler_options op = {};
3211    op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET);
3212    op.lower_ffma = false;
3213    op.fuse_ffma = false; /* nir doesn't track mad vs fma */
3214    op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET);
3215    op.lower_flrp32 = true;
3216    op.lower_flrp64 = true;
3217    op.lower_fpow = false; // TODO: nir's lowering is broken, or we could use it
3218    op.lower_fsat = false;
3219    op.lower_fsqrt = false; // TODO: only before gm200
3220    op.lower_sincos = false;
3221    op.lower_fmod = true;
3222    op.lower_bitfield_extract = false;
3223    op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
3224    op.lower_bitfield_insert = false;
3225    op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
3226    op.lower_bitfield_insert_to_bitfield_select = false;
3227    op.lower_bitfield_reverse = false;
3228    op.lower_bit_count = false;
3229    op.lower_ifind_msb = false;
3230    op.lower_find_lsb = false;
3231    op.lower_uadd_carry = true; // TODO
3232    op.lower_usub_borrow = true; // TODO
3233    op.lower_mul_high = false;
3234    op.lower_negate = false;
3235    op.lower_sub = true;
3236    op.lower_scmp = true; // TODO: not implemented yet
3237    op.lower_vector_cmp = false;
3238    op.lower_idiv = true;
3239    op.lower_bitops = false;
3240    op.lower_isign = (chipset >= NVISA_GV100_CHIPSET);
3241    op.lower_fsign = (chipset >= NVISA_GV100_CHIPSET);
3242    op.lower_fdph = false;
3243    op.lower_fdot = false;
3244    op.fdot_replicates = false; // TODO
3245    op.lower_ffloor = false; // TODO
3246    op.lower_ffract = true;
3247    op.lower_fceil = false; // TODO
3248    op.lower_ftrunc = false;
3249    op.lower_ldexp = true;
3250    op.lower_pack_half_2x16 = true;
3251    op.lower_pack_unorm_2x16 = true;
3252    op.lower_pack_snorm_2x16 = true;
3253    op.lower_pack_unorm_4x8 = true;
3254    op.lower_pack_snorm_4x8 = true;
3255    op.lower_unpack_half_2x16 = true;
3256    op.lower_unpack_unorm_2x16 = true;
3257    op.lower_unpack_snorm_2x16 = true;
3258    op.lower_unpack_unorm_4x8 = true;
3259    op.lower_unpack_snorm_4x8 = true;
3260    op.lower_pack_split = false;
3261    op.lower_extract_byte = (chipset < NVISA_GM107_CHIPSET);
3262    op.lower_extract_word = (chipset < NVISA_GM107_CHIPSET);
3263    op.lower_all_io_to_temps = false;
3264    op.lower_all_io_to_elements = false;
3265    op.vertex_id_zero_based = false;
3266    op.lower_base_vertex = false;
3267    op.lower_helper_invocation = false;
3268    op.optimize_sample_mask_in = false;
3269    op.lower_cs_local_index_from_id = true;
3270    op.lower_cs_local_id_from_index = false;
3271    op.lower_device_index_to_zero = false; // TODO
3272    op.lower_wpos_pntc = false; // TODO
3273    op.lower_hadd = true; // TODO
3274    op.lower_add_sat = true; // TODO
3275    op.vectorize_io = false;
3276    op.lower_to_scalar = false;
3277    op.unify_interfaces = false;
3278    op.use_interpolated_input_intrinsics = true;
3279    op.lower_mul_2x32_64 = true; // TODO
3280    op.lower_rotate = (chipset < NVISA_GV100_CHIPSET);
3281    op.has_imul24 = false;
3282    op.intel_vec4 = false;
3283    op.max_unroll_iterations = 32;
3284    op.lower_int64_options = (nir_lower_int64_options) (
3285       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) |
3286       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) |
3287       nir_lower_divmod64 |
3288       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) |
3289       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_mov64 : 0) |
3290       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_icmp64 : 0) |
3291       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_iabs64 : 0) |
3292       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ineg64 : 0) |
3293       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_logic64 : 0) |
3294       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_minmax64 : 0) |
3295       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) |
3296       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_2x32_64 : 0) |
3297       ((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) |
3298       nir_lower_ufind_msb64
3299    );
3300    op.lower_doubles_options = (nir_lower_doubles_options) (
3301       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drcp : 0) |
3302       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsqrt : 0) |
3303       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drsq : 0) |
3304       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dfract : 0) |
3305       nir_lower_dmod |
3306       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_dsub : 0) |
3307       ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ddiv : 0)
3308    );
3309    return op;
3310 }
3311
3312 static const nir_shader_compiler_options gf100_nir_shader_compiler_options =
3313 nvir_nir_shader_compiler_options(NVISA_GF100_CHIPSET);
3314 static const nir_shader_compiler_options gm107_nir_shader_compiler_options =
3315 nvir_nir_shader_compiler_options(NVISA_GM107_CHIPSET);
3316 static const nir_shader_compiler_options gv100_nir_shader_compiler_options =
3317 nvir_nir_shader_compiler_options(NVISA_GV100_CHIPSET);
3318
3319 const nir_shader_compiler_options *
3320 nv50_ir_nir_shader_compiler_options(int chipset)
3321 {
3322    if (chipset >= NVISA_GV100_CHIPSET)
3323       return &gv100_nir_shader_compiler_options;
3324    if (chipset >= NVISA_GM107_CHIPSET)
3325       return &gm107_nir_shader_compiler_options;
3326    return &gf100_nir_shader_compiler_options;
3327 }