src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

   1 /*
   2  * Copyright 2017 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Karol Herbst <kherbst@redhat.com>
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26
  27 #include "util/u_debug.h"
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_from_common.h"
  31 #include "codegen/nv50_ir_lowering_helper.h"
  32 #include "codegen/nv50_ir_util.h"
  33
  34 #if __cplusplus >= 201103L
  35 #include <unordered_map>
  36 #else
  37 #include <tr1/unordered_map>
  38 #endif
  39 #include <vector>
  40
  41 namespace {
  42
  43 #if __cplusplus >= 201103L
  44 using std::hash;
  45 using std::unordered_map;
  46 #else
  47 using std::tr1::hash;
  48 using std::tr1::unordered_map;
  49 #endif
  50
  51 using namespace nv50_ir;
  52
  53 int
  54 type_size(const struct glsl_type *type)
  55 {
  56    return glsl_count_attribute_slots(type, false);
  57 }
  58
  59 class Converter : public ConverterCommon
  60 {
  61 public:
  62    Converter(Program *, nir_shader *, nv50_ir_prog_info *);
  63
  64    bool run();
  65 private:
  66    typedef std::vector<LValue*> LValues;
  67    typedef unordered_map<unsigned, LValues> NirDefMap;
  68    typedef unordered_map<unsigned, BasicBlock*> NirBlockMap;
  69
  70    LValues& convert(nir_alu_dest *);
  71    BasicBlock* convert(nir_block *);
  72    LValues& convert(nir_dest *);
  73    LValues& convert(nir_register *);
  74    LValues& convert(nir_ssa_def *);
  75
  76    Value* getSrc(nir_alu_src *, uint8_t component = 0);
  77    Value* getSrc(nir_register *, uint8_t);
  78    Value* getSrc(nir_src *, uint8_t, bool indirect = false);
  79    Value* getSrc(nir_ssa_def *, uint8_t);
  80
  81    // returned value is the constant part of the given source (either the
  82    // nir_src or the selected source component of an intrinsic). Even though
  83    // this is mostly an optimization to be able to skip indirects in a few
  84    // cases, sometimes we require immediate values or set some fileds on
  85    // instructions (e.g. tex) in order for codegen to consume those.
  86    // If the found value has not a constant part, the Value gets returned
  87    // through the Value parameter.
  88    uint32_t getIndirect(nir_src *, uint8_t, Value *&);
  89    uint32_t getIndirect(nir_intrinsic_instr *, uint8_t s, uint8_t c, Value *&);
  90
  91    uint32_t getSlotAddress(nir_intrinsic_instr *, uint8_t idx, uint8_t slot);
  92
  93    void setInterpolate(nv50_ir_varying *,
  94                        uint8_t,
  95                        bool centroid,
  96                        unsigned semantics);
  97
  98    Instruction *loadFrom(DataFile, uint8_t, DataType, Value *def, uint32_t base,
  99                          uint8_t c, Value *indirect0 = NULL,
 100                          Value *indirect1 = NULL, bool patch = false);
 101    void storeTo(nir_intrinsic_instr *, DataFile, operation, DataType,
 102                 Value *src, uint8_t idx, uint8_t c, Value *indirect0 = NULL,
 103                 Value *indirect1 = NULL);
 104
 105    bool isFloatType(nir_alu_type);
 106    bool isSignedType(nir_alu_type);
 107    bool isResultFloat(nir_op);
 108    bool isResultSigned(nir_op);
 109
 110    DataType getDType(nir_alu_instr *);
 111    DataType getDType(nir_intrinsic_instr *);
 112    DataType getDType(nir_op, uint8_t);
 113
 114    std::vector<DataType> getSTypes(nir_alu_instr *);
 115    DataType getSType(nir_src &, bool isFloat, bool isSigned);
 116
 117    bool assignSlots();
 118    bool parseNIR();
 119
 120    bool visit(nir_block *);
 121    bool visit(nir_cf_node *);
 122    bool visit(nir_function *);
 123    bool visit(nir_if *);
 124    bool visit(nir_instr *);
 125    bool visit(nir_intrinsic_instr *);
 126    bool visit(nir_jump_instr *);
 127    bool visit(nir_load_const_instr*);
 128    bool visit(nir_loop *);
 129
 130    nir_shader *nir;
 131
 132    NirDefMap ssaDefs;
 133    NirDefMap regDefs;
 134    NirBlockMap blocks;
 135    unsigned int curLoopDepth;
 136
 137    BasicBlock *exit;
 138
 139    union {
 140       struct {
 141          Value *position;
 142       } fp;
 143    };
 144 };
 145
 146 Converter::Converter(Program *prog, nir_shader *nir, nv50_ir_prog_info *info)
 147    : ConverterCommon(prog, info),
 148      nir(nir),
 149      curLoopDepth(0) {}
 150
 151 BasicBlock *
 152 Converter::convert(nir_block *block)
 153 {
 154    NirBlockMap::iterator it = blocks.find(block->index);
 155    if (it != blocks.end())
 156       return it->second;
 157
 158    BasicBlock *bb = new BasicBlock(func);
 159    blocks[block->index] = bb;
 160    return bb;
 161 }
 162
 163 bool
 164 Converter::isFloatType(nir_alu_type type)
 165 {
 166    return nir_alu_type_get_base_type(type) == nir_type_float;
 167 }
 168
 169 bool
 170 Converter::isSignedType(nir_alu_type type)
 171 {
 172    return nir_alu_type_get_base_type(type) == nir_type_int;
 173 }
 174
 175 bool
 176 Converter::isResultFloat(nir_op op)
 177 {
 178    const nir_op_info &info = nir_op_infos[op];
 179    if (info.output_type != nir_type_invalid)
 180       return isFloatType(info.output_type);
 181
 182    ERROR("isResultFloat not implemented for %s\n", nir_op_infos[op].name);
 183    assert(false);
 184    return true;
 185 }
 186
 187 bool
 188 Converter::isResultSigned(nir_op op)
 189 {
 190    switch (op) {
 191    // there is no umul and we get wrong results if we treat all muls as signed
 192    case nir_op_imul:
 193    case nir_op_inot:
 194       return false;
 195    default:
 196       const nir_op_info &info = nir_op_infos[op];
 197       if (info.output_type != nir_type_invalid)
 198          return isSignedType(info.output_type);
 199       ERROR("isResultSigned not implemented for %s\n", nir_op_infos[op].name);
 200       assert(false);
 201       return true;
 202    }
 203 }
 204
 205 DataType
 206 Converter::getDType(nir_alu_instr *insn)
 207 {
 208    if (insn->dest.dest.is_ssa)
 209       return getDType(insn->op, insn->dest.dest.ssa.bit_size);
 210    else
 211       return getDType(insn->op, insn->dest.dest.reg.reg->bit_size);
 212 }
 213
 214 DataType
 215 Converter::getDType(nir_intrinsic_instr *insn)
 216 {
 217    if (insn->dest.is_ssa)
 218       return typeOfSize(insn->dest.ssa.bit_size / 8, false, false);
 219    else
 220       return typeOfSize(insn->dest.reg.reg->bit_size / 8, false, false);
 221 }
 222
 223 DataType
 224 Converter::getDType(nir_op op, uint8_t bitSize)
 225 {
 226    DataType ty = typeOfSize(bitSize / 8, isResultFloat(op), isResultSigned(op));
 227    if (ty == TYPE_NONE) {
 228       ERROR("couldn't get Type for op %s with bitSize %u\n", nir_op_infos[op].name, bitSize);
 229       assert(false);
 230    }
 231    return ty;
 232 }
 233
 234 std::vector<DataType>
 235 Converter::getSTypes(nir_alu_instr *insn)
 236 {
 237    const nir_op_info &info = nir_op_infos[insn->op];
 238    std::vector<DataType> res(info.num_inputs);
 239
 240    for (uint8_t i = 0; i < info.num_inputs; ++i) {
 241       if (info.input_types[i] != nir_type_invalid) {
 242          res[i] = getSType(insn->src[i].src, isFloatType(info.input_types[i]), isSignedType(info.input_types[i]));
 243       } else {
 244          ERROR("getSType not implemented for %s idx %u\n", info.name, i);
 245          assert(false);
 246          res[i] = TYPE_NONE;
 247          break;
 248       }
 249    }
 250
 251    return res;
 252 }
 253
 254 DataType
 255 Converter::getSType(nir_src &src, bool isFloat, bool isSigned)
 256 {
 257    uint8_t bitSize;
 258    if (src.is_ssa)
 259       bitSize = src.ssa->bit_size;
 260    else
 261       bitSize = src.reg.reg->bit_size;
 262
 263    DataType ty = typeOfSize(bitSize / 8, isFloat, isSigned);
 264    if (ty == TYPE_NONE) {
 265       const char *str;
 266       if (isFloat)
 267          str = "float";
 268       else if (isSigned)
 269          str = "int";
 270       else
 271          str = "uint";
 272       ERROR("couldn't get Type for %s with bitSize %u\n", str, bitSize);
 273       assert(false);
 274    }
 275    return ty;
 276 }
 277
 278 Converter::LValues&
 279 Converter::convert(nir_dest *dest)
 280 {
 281    if (dest->is_ssa)
 282       return convert(&dest->ssa);
 283    if (dest->reg.indirect) {
 284       ERROR("no support for indirects.");
 285       assert(false);
 286    }
 287    return convert(dest->reg.reg);
 288 }
 289
 290 Converter::LValues&
 291 Converter::convert(nir_register *reg)
 292 {
 293    NirDefMap::iterator it = regDefs.find(reg->index);
 294    if (it != regDefs.end())
 295       return it->second;
 296
 297    LValues newDef(reg->num_components);
 298    for (uint8_t i = 0; i < reg->num_components; i++)
 299       newDef[i] = getScratch(std::max(4, reg->bit_size / 8));
 300    return regDefs[reg->index] = newDef;
 301 }
 302
 303 Converter::LValues&
 304 Converter::convert(nir_ssa_def *def)
 305 {
 306    NirDefMap::iterator it = ssaDefs.find(def->index);
 307    if (it != ssaDefs.end())
 308       return it->second;
 309
 310    LValues newDef(def->num_components);
 311    for (uint8_t i = 0; i < def->num_components; i++)
 312       newDef[i] = getSSA(std::max(4, def->bit_size / 8));
 313    return ssaDefs[def->index] = newDef;
 314 }
 315
 316 Value*
 317 Converter::getSrc(nir_alu_src *src, uint8_t component)
 318 {
 319    if (src->abs || src->negate) {
 320       ERROR("modifiers currently not supported on nir_alu_src\n");
 321       assert(false);
 322    }
 323    return getSrc(&src->src, src->swizzle[component]);
 324 }
 325
 326 Value*
 327 Converter::getSrc(nir_register *reg, uint8_t idx)
 328 {
 329    NirDefMap::iterator it = regDefs.find(reg->index);
 330    if (it == regDefs.end())
 331       return convert(reg)[idx];
 332    return it->second[idx];
 333 }
 334
 335 Value*
 336 Converter::getSrc(nir_src *src, uint8_t idx, bool indirect)
 337 {
 338    if (src->is_ssa)
 339       return getSrc(src->ssa, idx);
 340
 341    if (src->reg.indirect) {
 342       if (indirect)
 343          return getSrc(src->reg.indirect, idx);
 344       ERROR("no support for indirects.");
 345       assert(false);
 346       return NULL;
 347    }
 348
 349    return getSrc(src->reg.reg, idx);
 350 }
 351
 352 Value*
 353 Converter::getSrc(nir_ssa_def *src, uint8_t idx)
 354 {
 355    NirDefMap::iterator it = ssaDefs.find(src->index);
 356    if (it == ssaDefs.end()) {
 357       ERROR("SSA value %u not found\n", src->index);
 358       assert(false);
 359       return NULL;
 360    }
 361    return it->second[idx];
 362 }
 363
 364 uint32_t
 365 Converter::getIndirect(nir_src *src, uint8_t idx, Value *&indirect)
 366 {
 367    nir_const_value *offset = nir_src_as_const_value(*src);
 368
 369    if (offset) {
 370       indirect = NULL;
 371       return offset->u32[0];
 372    }
 373
 374    indirect = getSrc(src, idx, true);
 375    return 0;
 376 }
 377
 378 uint32_t
 379 Converter::getIndirect(nir_intrinsic_instr *insn, uint8_t s, uint8_t c, Value *&indirect)
 380 {
 381    int32_t idx = nir_intrinsic_base(insn) + getIndirect(&insn->src[s], c, indirect);
 382    if (indirect)
 383       indirect = mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), indirect, loadImm(NULL, 4));
 384    return idx;
 385 }
 386
 387 static void
 388 vert_attrib_to_tgsi_semantic(gl_vert_attrib slot, unsigned *name, unsigned *index)
 389 {
 390    assert(name && index);
 391
 392    if (slot >= VERT_ATTRIB_MAX) {
 393       ERROR("invalid varying slot %u\n", slot);
 394       assert(false);
 395       return;
 396    }
 397
 398    if (slot >= VERT_ATTRIB_GENERIC0 &&
 399        slot < VERT_ATTRIB_GENERIC0 + VERT_ATTRIB_GENERIC_MAX) {
 400       *name = TGSI_SEMANTIC_GENERIC;
 401       *index = slot - VERT_ATTRIB_GENERIC0;
 402       return;
 403    }
 404
 405    if (slot >= VERT_ATTRIB_TEX0 &&
 406        slot < VERT_ATTRIB_TEX0 + VERT_ATTRIB_TEX_MAX) {
 407       *name = TGSI_SEMANTIC_TEXCOORD;
 408       *index = slot - VERT_ATTRIB_TEX0;
 409       return;
 410    }
 411
 412    switch (slot) {
 413    case VERT_ATTRIB_COLOR0:
 414       *name = TGSI_SEMANTIC_COLOR;
 415       *index = 0;
 416       break;
 417    case VERT_ATTRIB_COLOR1:
 418       *name = TGSI_SEMANTIC_COLOR;
 419       *index = 1;
 420       break;
 421    case VERT_ATTRIB_EDGEFLAG:
 422       *name = TGSI_SEMANTIC_EDGEFLAG;
 423       *index = 0;
 424       break;
 425    case VERT_ATTRIB_FOG:
 426       *name = TGSI_SEMANTIC_FOG;
 427       *index = 0;
 428       break;
 429    case VERT_ATTRIB_NORMAL:
 430       *name = TGSI_SEMANTIC_NORMAL;
 431       *index = 0;
 432       break;
 433    case VERT_ATTRIB_POS:
 434       *name = TGSI_SEMANTIC_POSITION;
 435       *index = 0;
 436       break;
 437    case VERT_ATTRIB_POINT_SIZE:
 438       *name = TGSI_SEMANTIC_PSIZE;
 439       *index = 0;
 440       break;
 441    default:
 442       ERROR("unknown vert attrib slot %u\n", slot);
 443       assert(false);
 444       break;
 445    }
 446 }
 447
 448 static void
 449 varying_slot_to_tgsi_semantic(gl_varying_slot slot, unsigned *name, unsigned *index)
 450 {
 451    assert(name && index);
 452
 453    if (slot >= VARYING_SLOT_TESS_MAX) {
 454       ERROR("invalid varying slot %u\n", slot);
 455       assert(false);
 456       return;
 457    }
 458
 459    if (slot >= VARYING_SLOT_PATCH0) {
 460       *name = TGSI_SEMANTIC_PATCH;
 461       *index = slot - VARYING_SLOT_PATCH0;
 462       return;
 463    }
 464
 465    if (slot >= VARYING_SLOT_VAR0) {
 466       *name = TGSI_SEMANTIC_GENERIC;
 467       *index = slot - VARYING_SLOT_VAR0;
 468       return;
 469    }
 470
 471    if (slot >= VARYING_SLOT_TEX0 && slot <= VARYING_SLOT_TEX7) {
 472       *name = TGSI_SEMANTIC_TEXCOORD;
 473       *index = slot - VARYING_SLOT_TEX0;
 474       return;
 475    }
 476
 477    switch (slot) {
 478    case VARYING_SLOT_BFC0:
 479       *name = TGSI_SEMANTIC_BCOLOR;
 480       *index = 0;
 481       break;
 482    case VARYING_SLOT_BFC1:
 483       *name = TGSI_SEMANTIC_BCOLOR;
 484       *index = 1;
 485       break;
 486    case VARYING_SLOT_CLIP_DIST0:
 487       *name = TGSI_SEMANTIC_CLIPDIST;
 488       *index = 0;
 489       break;
 490    case VARYING_SLOT_CLIP_DIST1:
 491       *name = TGSI_SEMANTIC_CLIPDIST;
 492       *index = 1;
 493       break;
 494    case VARYING_SLOT_CLIP_VERTEX:
 495       *name = TGSI_SEMANTIC_CLIPVERTEX;
 496       *index = 0;
 497       break;
 498    case VARYING_SLOT_COL0:
 499       *name = TGSI_SEMANTIC_COLOR;
 500       *index = 0;
 501       break;
 502    case VARYING_SLOT_COL1:
 503       *name = TGSI_SEMANTIC_COLOR;
 504       *index = 1;
 505       break;
 506    case VARYING_SLOT_EDGE:
 507       *name = TGSI_SEMANTIC_EDGEFLAG;
 508       *index = 0;
 509       break;
 510    case VARYING_SLOT_FACE:
 511       *name = TGSI_SEMANTIC_FACE;
 512       *index = 0;
 513       break;
 514    case VARYING_SLOT_FOGC:
 515       *name = TGSI_SEMANTIC_FOG;
 516       *index = 0;
 517       break;
 518    case VARYING_SLOT_LAYER:
 519       *name = TGSI_SEMANTIC_LAYER;
 520       *index = 0;
 521       break;
 522    case VARYING_SLOT_PNTC:
 523       *name = TGSI_SEMANTIC_PCOORD;
 524       *index = 0;
 525       break;
 526    case VARYING_SLOT_POS:
 527       *name = TGSI_SEMANTIC_POSITION;
 528       *index = 0;
 529       break;
 530    case VARYING_SLOT_PRIMITIVE_ID:
 531       *name = TGSI_SEMANTIC_PRIMID;
 532       *index = 0;
 533       break;
 534    case VARYING_SLOT_PSIZ:
 535       *name = TGSI_SEMANTIC_PSIZE;
 536       *index = 0;
 537       break;
 538    case VARYING_SLOT_TESS_LEVEL_INNER:
 539       *name = TGSI_SEMANTIC_TESSINNER;
 540       *index = 0;
 541       break;
 542    case VARYING_SLOT_TESS_LEVEL_OUTER:
 543       *name = TGSI_SEMANTIC_TESSOUTER;
 544       *index = 0;
 545       break;
 546    case VARYING_SLOT_VIEWPORT:
 547       *name = TGSI_SEMANTIC_VIEWPORT_INDEX;
 548       *index = 0;
 549       break;
 550    default:
 551       ERROR("unknown varying slot %u\n", slot);
 552       assert(false);
 553       break;
 554    }
 555 }
 556
 557 static void
 558 frag_result_to_tgsi_semantic(unsigned slot, unsigned *name, unsigned *index)
 559 {
 560    if (slot >= FRAG_RESULT_DATA0) {
 561       *name = TGSI_SEMANTIC_COLOR;
 562       *index = slot - FRAG_RESULT_COLOR - 2; // intentional
 563       return;
 564    }
 565
 566    switch (slot) {
 567    case FRAG_RESULT_COLOR:
 568       *name = TGSI_SEMANTIC_COLOR;
 569       *index = 0;
 570       break;
 571    case FRAG_RESULT_DEPTH:
 572       *name = TGSI_SEMANTIC_POSITION;
 573       *index = 0;
 574       break;
 575    case FRAG_RESULT_SAMPLE_MASK:
 576       *name = TGSI_SEMANTIC_SAMPLEMASK;
 577       *index = 0;
 578       break;
 579    default:
 580       ERROR("unknown frag result slot %u\n", slot);
 581       assert(false);
 582       break;
 583    }
 584 }
 585
 586 // copy of _mesa_sysval_to_semantic
 587 static void
 588 system_val_to_tgsi_semantic(unsigned val, unsigned *name, unsigned *index)
 589 {
 590    *index = 0;
 591    switch (val) {
 592    // Vertex shader
 593    case SYSTEM_VALUE_VERTEX_ID:
 594       *name = TGSI_SEMANTIC_VERTEXID;
 595       break;
 596    case SYSTEM_VALUE_INSTANCE_ID:
 597       *name = TGSI_SEMANTIC_INSTANCEID;
 598       break;
 599    case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
 600       *name = TGSI_SEMANTIC_VERTEXID_NOBASE;
 601       break;
 602    case SYSTEM_VALUE_BASE_VERTEX:
 603       *name = TGSI_SEMANTIC_BASEVERTEX;
 604       break;
 605    case SYSTEM_VALUE_BASE_INSTANCE:
 606       *name = TGSI_SEMANTIC_BASEINSTANCE;
 607       break;
 608    case SYSTEM_VALUE_DRAW_ID:
 609       *name = TGSI_SEMANTIC_DRAWID;
 610       break;
 611
 612    // Geometry shader
 613    case SYSTEM_VALUE_INVOCATION_ID:
 614       *name = TGSI_SEMANTIC_INVOCATIONID;
 615       break;
 616
 617    // Fragment shader
 618    case SYSTEM_VALUE_FRAG_COORD:
 619       *name = TGSI_SEMANTIC_POSITION;
 620       break;
 621    case SYSTEM_VALUE_FRONT_FACE:
 622       *name = TGSI_SEMANTIC_FACE;
 623       break;
 624    case SYSTEM_VALUE_SAMPLE_ID:
 625       *name = TGSI_SEMANTIC_SAMPLEID;
 626       break;
 627    case SYSTEM_VALUE_SAMPLE_POS:
 628       *name = TGSI_SEMANTIC_SAMPLEPOS;
 629       break;
 630    case SYSTEM_VALUE_SAMPLE_MASK_IN:
 631       *name = TGSI_SEMANTIC_SAMPLEMASK;
 632       break;
 633    case SYSTEM_VALUE_HELPER_INVOCATION:
 634       *name = TGSI_SEMANTIC_HELPER_INVOCATION;
 635       break;
 636
 637    // Tessellation shader
 638    case SYSTEM_VALUE_TESS_COORD:
 639       *name = TGSI_SEMANTIC_TESSCOORD;
 640       break;
 641    case SYSTEM_VALUE_VERTICES_IN:
 642       *name = TGSI_SEMANTIC_VERTICESIN;
 643       break;
 644    case SYSTEM_VALUE_PRIMITIVE_ID:
 645       *name = TGSI_SEMANTIC_PRIMID;
 646       break;
 647    case SYSTEM_VALUE_TESS_LEVEL_OUTER:
 648       *name = TGSI_SEMANTIC_TESSOUTER;
 649       break;
 650    case SYSTEM_VALUE_TESS_LEVEL_INNER:
 651       *name = TGSI_SEMANTIC_TESSINNER;
 652       break;
 653
 654    // Compute shader
 655    case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
 656       *name = TGSI_SEMANTIC_THREAD_ID;
 657       break;
 658    case SYSTEM_VALUE_WORK_GROUP_ID:
 659       *name = TGSI_SEMANTIC_BLOCK_ID;
 660       break;
 661    case SYSTEM_VALUE_NUM_WORK_GROUPS:
 662       *name = TGSI_SEMANTIC_GRID_SIZE;
 663       break;
 664    case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
 665       *name = TGSI_SEMANTIC_BLOCK_SIZE;
 666       break;
 667
 668    // ARB_shader_ballot
 669    case SYSTEM_VALUE_SUBGROUP_SIZE:
 670       *name = TGSI_SEMANTIC_SUBGROUP_SIZE;
 671       break;
 672    case SYSTEM_VALUE_SUBGROUP_INVOCATION:
 673       *name = TGSI_SEMANTIC_SUBGROUP_INVOCATION;
 674       break;
 675    case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
 676       *name = TGSI_SEMANTIC_SUBGROUP_EQ_MASK;
 677       break;
 678    case SYSTEM_VALUE_SUBGROUP_GE_MASK:
 679       *name = TGSI_SEMANTIC_SUBGROUP_GE_MASK;
 680       break;
 681    case SYSTEM_VALUE_SUBGROUP_GT_MASK:
 682       *name = TGSI_SEMANTIC_SUBGROUP_GT_MASK;
 683       break;
 684    case SYSTEM_VALUE_SUBGROUP_LE_MASK:
 685       *name = TGSI_SEMANTIC_SUBGROUP_LE_MASK;
 686       break;
 687    case SYSTEM_VALUE_SUBGROUP_LT_MASK:
 688       *name = TGSI_SEMANTIC_SUBGROUP_LT_MASK;
 689       break;
 690
 691    default:
 692       ERROR("unknown system value %u\n", val);
 693       assert(false);
 694       break;
 695    }
 696 }
 697
 698 void
 699 Converter::setInterpolate(nv50_ir_varying *var,
 700                           uint8_t mode,
 701                           bool centroid,
 702                           unsigned semantic)
 703 {
 704    switch (mode) {
 705    case INTERP_MODE_FLAT:
 706       var->flat = 1;
 707       break;
 708    case INTERP_MODE_NONE:
 709       if (semantic == TGSI_SEMANTIC_COLOR)
 710          var->sc = 1;
 711       else if (semantic == TGSI_SEMANTIC_POSITION)
 712          var->linear = 1;
 713       break;
 714    case INTERP_MODE_NOPERSPECTIVE:
 715       var->linear = 1;
 716       break;
 717    case INTERP_MODE_SMOOTH:
 718       break;
 719    }
 720    var->centroid = centroid;
 721 }
 722
 723 static uint16_t
 724 calcSlots(const glsl_type *type, Program::Type stage, const shader_info &info,
 725           bool input, const nir_variable *var)
 726 {
 727    if (!type->is_array())
 728       return type->count_attribute_slots(false);
 729
 730    uint16_t slots;
 731    switch (stage) {
 732    case Program::TYPE_GEOMETRY:
 733       slots = type->uniform_locations();
 734       if (input)
 735          slots /= info.gs.vertices_in;
 736       break;
 737    case Program::TYPE_TESSELLATION_CONTROL:
 738    case Program::TYPE_TESSELLATION_EVAL:
 739       // remove first dimension
 740       if (var->data.patch || (!input && stage == Program::TYPE_TESSELLATION_EVAL))
 741          slots = type->uniform_locations();
 742       else
 743          slots = type->fields.array->uniform_locations();
 744       break;
 745    default:
 746       slots = type->count_attribute_slots(false);
 747       break;
 748    }
 749
 750    return slots;
 751 }
 752
 753 bool Converter::assignSlots() {
 754    unsigned name;
 755    unsigned index;
 756
 757    info->io.viewportId = -1;
 758    info->numInputs = 0;
 759
 760    // we have to fixup the uniform locations for arrays
 761    unsigned numImages = 0;
 762    nir_foreach_variable(var, &nir->uniforms) {
 763       const glsl_type *type = var->type;
 764       if (!type->without_array()->is_image())
 765          continue;
 766       var->data.driver_location = numImages;
 767       numImages += type->is_array() ? type->arrays_of_arrays_size() : 1;
 768    }
 769
 770    nir_foreach_variable(var, &nir->inputs) {
 771       const glsl_type *type = var->type;
 772       int slot = var->data.location;
 773       uint16_t slots = calcSlots(type, prog->getType(), nir->info, true, var);
 774       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
 775                                        : type->component_slots();
 776       uint32_t frac = var->data.location_frac;
 777       uint32_t vary = var->data.driver_location;
 778
 779       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
 780          if (comp > 2)
 781             slots *= 2;
 782       }
 783
 784       assert(vary + slots <= PIPE_MAX_SHADER_INPUTS);
 785
 786       switch(prog->getType()) {
 787       case Program::TYPE_FRAGMENT:
 788          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
 789          for (uint16_t i = 0; i < slots; ++i) {
 790             setInterpolate(&info->in[vary + i], var->data.interpolation,
 791                            var->data.centroid | var->data.sample, name);
 792          }
 793          break;
 794       case Program::TYPE_GEOMETRY:
 795          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
 796          break;
 797       case Program::TYPE_TESSELLATION_CONTROL:
 798       case Program::TYPE_TESSELLATION_EVAL:
 799          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
 800          if (var->data.patch && name == TGSI_SEMANTIC_PATCH)
 801             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
 802          break;
 803       case Program::TYPE_VERTEX:
 804          vert_attrib_to_tgsi_semantic((gl_vert_attrib)slot, &name, &index);
 805          switch (name) {
 806          case TGSI_SEMANTIC_EDGEFLAG:
 807             info->io.edgeFlagIn = vary;
 808             break;
 809          default:
 810             break;
 811          }
 812          break;
 813       default:
 814          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
 815          return false;
 816       }
 817
 818       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
 819          info->in[vary].id = vary;
 820          info->in[vary].patch = var->data.patch;
 821          info->in[vary].sn = name;
 822          info->in[vary].si = index + i;
 823          if (glsl_base_type_is_64bit(type->without_array()->base_type))
 824             if (i & 0x1)
 825                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
 826             else
 827                info->in[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
 828          else
 829             info->in[vary].mask |= ((1 << comp) - 1) << frac;
 830       }
 831       info->numInputs = std::max<uint8_t>(info->numInputs, vary);
 832    }
 833
 834    info->numOutputs = 0;
 835    nir_foreach_variable(var, &nir->outputs) {
 836       const glsl_type *type = var->type;
 837       int slot = var->data.location;
 838       uint16_t slots = calcSlots(type, prog->getType(), nir->info, false, var);
 839       uint32_t comp = type->is_array() ? type->without_array()->component_slots()
 840                                        : type->component_slots();
 841       uint32_t frac = var->data.location_frac;
 842       uint32_t vary = var->data.driver_location;
 843
 844       if (glsl_base_type_is_64bit(type->without_array()->base_type)) {
 845          if (comp > 2)
 846             slots *= 2;
 847       }
 848
 849       assert(vary < PIPE_MAX_SHADER_OUTPUTS);
 850
 851       switch(prog->getType()) {
 852       case Program::TYPE_FRAGMENT:
 853          frag_result_to_tgsi_semantic((gl_frag_result)slot, &name, &index);
 854          switch (name) {
 855          case TGSI_SEMANTIC_COLOR:
 856             if (!var->data.fb_fetch_output)
 857                info->prop.fp.numColourResults++;
 858             info->prop.fp.separateFragData = true;
 859             // sometimes we get FRAG_RESULT_DATAX with data.index 0
 860             // sometimes we get FRAG_RESULT_DATA0 with data.index X
 861             index = index == 0 ? var->data.index : index;
 862             break;
 863          case TGSI_SEMANTIC_POSITION:
 864             info->io.fragDepth = vary;
 865             info->prop.fp.writesDepth = true;
 866             break;
 867          case TGSI_SEMANTIC_SAMPLEMASK:
 868             info->io.sampleMask = vary;
 869             break;
 870          default:
 871             break;
 872          }
 873          break;
 874       case Program::TYPE_GEOMETRY:
 875       case Program::TYPE_TESSELLATION_CONTROL:
 876       case Program::TYPE_TESSELLATION_EVAL:
 877       case Program::TYPE_VERTEX:
 878          varying_slot_to_tgsi_semantic((gl_varying_slot)slot, &name, &index);
 879
 880          if (var->data.patch && name != TGSI_SEMANTIC_TESSINNER &&
 881              name != TGSI_SEMANTIC_TESSOUTER)
 882             info->numPatchConstants = MAX2(info->numPatchConstants, index + slots);
 883
 884          switch (name) {
 885          case TGSI_SEMANTIC_CLIPDIST:
 886             info->io.genUserClip = -1;
 887             break;
 888          case TGSI_SEMANTIC_EDGEFLAG:
 889             info->io.edgeFlagOut = vary;
 890             break;
 891          default:
 892             break;
 893          }
 894          break;
 895       default:
 896          ERROR("unknown shader type %u in assignSlots\n", prog->getType());
 897          return false;
 898       }
 899
 900       for (uint16_t i = 0u; i < slots; ++i, ++vary) {
 901          info->out[vary].id = vary;
 902          info->out[vary].patch = var->data.patch;
 903          info->out[vary].sn = name;
 904          info->out[vary].si = index + i;
 905          if (glsl_base_type_is_64bit(type->without_array()->base_type))
 906             if (i & 0x1)
 907                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) >> 0x4);
 908             else
 909                info->out[vary].mask |= (((1 << (comp * 2)) - 1) << (frac * 2) & 0xf);
 910          else
 911             info->out[vary].mask |= ((1 << comp) - 1) << frac;
 912
 913          if (nir->info.outputs_read & 1ll << slot)
 914             info->out[vary].oread = 1;
 915       }
 916       info->numOutputs = std::max<uint8_t>(info->numOutputs, vary);
 917    }
 918
 919    info->numSysVals = 0;
 920    for (uint8_t i = 0; i < 64; ++i) {
 921       if (!(nir->info.system_values_read & 1ll << i))
 922          continue;
 923
 924       system_val_to_tgsi_semantic(i, &name, &index);
 925       info->sv[info->numSysVals].sn = name;
 926       info->sv[info->numSysVals].si = index;
 927       info->sv[info->numSysVals].input = 0; // TODO inferSysValDirection(sn);
 928
 929       switch (i) {
 930       case SYSTEM_VALUE_INSTANCE_ID:
 931          info->io.instanceId = info->numSysVals;
 932          break;
 933       case SYSTEM_VALUE_TESS_LEVEL_INNER:
 934       case SYSTEM_VALUE_TESS_LEVEL_OUTER:
 935          info->sv[info->numSysVals].patch = 1;
 936          break;
 937       case SYSTEM_VALUE_VERTEX_ID:
 938          info->io.vertexId = info->numSysVals;
 939          break;
 940       default:
 941          break;
 942       }
 943
 944       info->numSysVals += 1;
 945    }
 946
 947    if (info->io.genUserClip > 0) {
 948       info->io.clipDistances = info->io.genUserClip;
 949
 950       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 951
 952       for (unsigned int n = 0; n < nOut; ++n) {
 953          unsigned int i = info->numOutputs++;
 954          info->out[i].id = i;
 955          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 956          info->out[i].si = n;
 957          info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
 958       }
 959    }
 960
 961    return info->assignSlots(info) == 0;
 962 }
 963
 964 uint32_t
 965 Converter::getSlotAddress(nir_intrinsic_instr *insn, uint8_t idx, uint8_t slot)
 966 {
 967    DataType ty;
 968    int offset = nir_intrinsic_component(insn);
 969    bool input;
 970
 971    if (nir_intrinsic_infos[insn->intrinsic].has_dest)
 972       ty = getDType(insn);
 973    else
 974       ty = getSType(insn->src[0], false, false);
 975
 976    switch (insn->intrinsic) {
 977    case nir_intrinsic_load_input:
 978    case nir_intrinsic_load_interpolated_input:
 979    case nir_intrinsic_load_per_vertex_input:
 980       input = true;
 981       break;
 982    case nir_intrinsic_load_output:
 983    case nir_intrinsic_load_per_vertex_output:
 984    case nir_intrinsic_store_output:
 985    case nir_intrinsic_store_per_vertex_output:
 986       input = false;
 987       break;
 988    default:
 989       ERROR("unknown intrinsic in getSlotAddress %s",
 990             nir_intrinsic_infos[insn->intrinsic].name);
 991       input = false;
 992       assert(false);
 993       break;
 994    }
 995
 996    if (typeSizeof(ty) == 8) {
 997       slot *= 2;
 998       slot += offset;
 999       if (slot >= 4) {
1000          idx += 1;
1001          slot -= 4;
1002       }
1003    } else {
1004       slot += offset;
1005    }
1006
1007    assert(slot < 4);
1008    assert(!input || idx < PIPE_MAX_SHADER_INPUTS);
1009    assert(input || idx < PIPE_MAX_SHADER_OUTPUTS);
1010
1011    const nv50_ir_varying *vary = input ? info->in : info->out;
1012    return vary[idx].slot[slot] * 4;
1013 }
1014
1015 Instruction *
1016 Converter::loadFrom(DataFile file, uint8_t i, DataType ty, Value *def,
1017                     uint32_t base, uint8_t c, Value *indirect0,
1018                     Value *indirect1, bool patch)
1019 {
1020    unsigned int tySize = typeSizeof(ty);
1021
1022    if (tySize == 8 &&
1023        (file == FILE_MEMORY_CONST || file == FILE_MEMORY_BUFFER || indirect0)) {
1024       Value *lo = getSSA();
1025       Value *hi = getSSA();
1026
1027       Instruction *loi =
1028          mkLoad(TYPE_U32, lo,
1029                 mkSymbol(file, i, TYPE_U32, base + c * tySize),
1030                 indirect0);
1031       loi->setIndirect(0, 1, indirect1);
1032       loi->perPatch = patch;
1033
1034       Instruction *hii =
1035          mkLoad(TYPE_U32, hi,
1036                 mkSymbol(file, i, TYPE_U32, base + c * tySize + 4),
1037                 indirect0);
1038       hii->setIndirect(0, 1, indirect1);
1039       hii->perPatch = patch;
1040
1041       return mkOp2(OP_MERGE, ty, def, lo, hi);
1042    } else {
1043       Instruction *ld =
1044          mkLoad(ty, def, mkSymbol(file, i, ty, base + c * tySize), indirect0);
1045       ld->setIndirect(0, 1, indirect1);
1046       ld->perPatch = patch;
1047       return ld;
1048    }
1049 }
1050
1051 void
1052 Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op,
1053                    DataType ty, Value *src, uint8_t idx, uint8_t c,
1054                    Value *indirect0, Value *indirect1)
1055 {
1056    uint8_t size = typeSizeof(ty);
1057    uint32_t address = getSlotAddress(insn, idx, c);
1058
1059    if (size == 8 && indirect0) {
1060       Value *split[2];
1061       mkSplit(split, 4, src);
1062
1063       if (op == OP_EXPORT) {
1064          split[0] = mkMov(getSSA(), split[0], ty)->getDef(0);
1065          split[1] = mkMov(getSSA(), split[1], ty)->getDef(0);
1066       }
1067
1068       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address), indirect0,
1069               split[0])->perPatch = info->out[idx].patch;
1070       mkStore(op, TYPE_U32, mkSymbol(file, 0, TYPE_U32, address + 4), indirect0,
1071               split[1])->perPatch = info->out[idx].patch;
1072    } else {
1073       if (op == OP_EXPORT)
1074          src = mkMov(getSSA(size), src, ty)->getDef(0);
1075       mkStore(op, ty, mkSymbol(file, 0, ty, address), indirect0,
1076               src)->perPatch = info->out[idx].patch;
1077    }
1078 }
1079
1080 bool
1081 Converter::parseNIR()
1082 {
1083    info->io.clipDistances = nir->info.clip_distance_array_size;
1084    info->io.cullDistances = nir->info.cull_distance_array_size;
1085
1086    switch(prog->getType()) {
1087    case Program::TYPE_COMPUTE:
1088       info->prop.cp.numThreads[0] = nir->info.cs.local_size[0];
1089       info->prop.cp.numThreads[1] = nir->info.cs.local_size[1];
1090       info->prop.cp.numThreads[2] = nir->info.cs.local_size[2];
1091       info->bin.smemSize = nir->info.cs.shared_size;
1092       break;
1093    case Program::TYPE_FRAGMENT:
1094       info->prop.fp.earlyFragTests = nir->info.fs.early_fragment_tests;
1095       info->prop.fp.persampleInvocation =
1096          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_ID) ||
1097          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1098       info->prop.fp.postDepthCoverage = nir->info.fs.post_depth_coverage;
1099       info->prop.fp.readsSampleLocations =
1100          (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_POS);
1101       info->prop.fp.usesDiscard = nir->info.fs.uses_discard;
1102       info->prop.fp.usesSampleMaskIn =
1103          !!(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN);
1104       break;
1105    case Program::TYPE_GEOMETRY:
1106       info->prop.gp.inputPrim = nir->info.gs.input_primitive;
1107       info->prop.gp.instanceCount = nir->info.gs.invocations;
1108       info->prop.gp.maxVertices = nir->info.gs.vertices_out;
1109       info->prop.gp.outputPrim = nir->info.gs.output_primitive;
1110       break;
1111    case Program::TYPE_TESSELLATION_CONTROL:
1112    case Program::TYPE_TESSELLATION_EVAL:
1113       if (nir->info.tess.primitive_mode == GL_ISOLINES)
1114          info->prop.tp.domain = GL_LINES;
1115       else
1116          info->prop.tp.domain = nir->info.tess.primitive_mode;
1117       info->prop.tp.outputPatchSize = nir->info.tess.tcs_vertices_out;
1118       info->prop.tp.outputPrim =
1119          nir->info.tess.point_mode ? PIPE_PRIM_POINTS : PIPE_PRIM_TRIANGLES;
1120       info->prop.tp.partitioning = (nir->info.tess.spacing + 1) % 3;
1121       info->prop.tp.winding = !nir->info.tess.ccw;
1122       break;
1123    case Program::TYPE_VERTEX:
1124       info->prop.vp.usesDrawParameters =
1125          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) ||
1126          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) ||
1127          (nir->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID));
1128       break;
1129    default:
1130       break;
1131    }
1132
1133    return true;
1134 }
1135
1136 bool
1137 Converter::visit(nir_function *function)
1138 {
1139    // we only support emiting the main function for now
1140    assert(!strcmp(function->name, "main"));
1141    assert(function->impl);
1142
1143    // usually the blocks will set everything up, but main is special
1144    BasicBlock *entry = new BasicBlock(prog->main);
1145    exit = new BasicBlock(prog->main);
1146    blocks[nir_start_block(function->impl)->index] = entry;
1147    prog->main->setEntry(entry);
1148    prog->main->setExit(exit);
1149
1150    setPosition(entry, true);
1151
1152    switch (prog->getType()) {
1153    case Program::TYPE_TESSELLATION_CONTROL:
1154       outBase = mkOp2v(
1155          OP_SUB, TYPE_U32, getSSA(),
1156          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
1157          mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
1158       break;
1159    case Program::TYPE_FRAGMENT: {
1160       Symbol *sv = mkSysVal(SV_POSITION, 3);
1161       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
1162       fp.position = mkOp1v(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
1163       break;
1164    }
1165    default:
1166       break;
1167    }
1168
1169    nir_index_ssa_defs(function->impl);
1170    foreach_list_typed(nir_cf_node, node, node, &function->impl->body) {
1171       if (!visit(node))
1172          return false;
1173    }
1174
1175    bb->cfg.attach(&exit->cfg, Graph::Edge::TREE);
1176    setPosition(exit, true);
1177
1178    // TODO: for non main function this needs to be a OP_RETURN
1179    mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
1180    return true;
1181 }
1182
1183 bool
1184 Converter::visit(nir_cf_node *node)
1185 {
1186    switch (node->type) {
1187    case nir_cf_node_block:
1188       return visit(nir_cf_node_as_block(node));
1189    case nir_cf_node_if:
1190       return visit(nir_cf_node_as_if(node));
1191    case nir_cf_node_loop:
1192       return visit(nir_cf_node_as_loop(node));
1193    default:
1194       ERROR("unknown nir_cf_node type %u\n", node->type);
1195       return false;
1196    }
1197 }
1198
1199 bool
1200 Converter::visit(nir_block *block)
1201 {
1202    if (!block->predecessors->entries && block->instr_list.is_empty())
1203       return true;
1204
1205    BasicBlock *bb = convert(block);
1206
1207    setPosition(bb, true);
1208    nir_foreach_instr(insn, block) {
1209       if (!visit(insn))
1210          return false;
1211    }
1212    return true;
1213 }
1214
1215 bool
1216 Converter::visit(nir_if *nif)
1217 {
1218    DataType sType = getSType(nif->condition, false, false);
1219    Value *src = getSrc(&nif->condition, 0);
1220
1221    nir_block *lastThen = nir_if_last_then_block(nif);
1222    nir_block *lastElse = nir_if_last_else_block(nif);
1223
1224    assert(!lastThen->successors[1]);
1225    assert(!lastElse->successors[1]);
1226
1227    BasicBlock *ifBB = convert(nir_if_first_then_block(nif));
1228    BasicBlock *elseBB = convert(nir_if_first_else_block(nif));
1229
1230    bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
1231    bb->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
1232
1233    // we only insert joinats, if both nodes end up at the end of the if again.
1234    // the reason for this to not happens are breaks/continues/ret/... which
1235    // have their own handling
1236    if (lastThen->successors[0] == lastElse->successors[0])
1237       bb->joinAt = mkFlow(OP_JOINAT, convert(lastThen->successors[0]),
1238                           CC_ALWAYS, NULL);
1239
1240    mkFlow(OP_BRA, elseBB, CC_EQ, src)->setType(sType);
1241
1242    foreach_list_typed(nir_cf_node, node, node, &nif->then_list) {
1243       if (!visit(node))
1244          return false;
1245    }
1246    setPosition(convert(lastThen), true);
1247    if (!bb->getExit() ||
1248        !bb->getExit()->asFlow() ||
1249         bb->getExit()->asFlow()->op == OP_JOIN) {
1250       BasicBlock *tailBB = convert(lastThen->successors[0]);
1251       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1252       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1253    }
1254
1255    foreach_list_typed(nir_cf_node, node, node, &nif->else_list) {
1256       if (!visit(node))
1257          return false;
1258    }
1259    setPosition(convert(lastElse), true);
1260    if (!bb->getExit() ||
1261        !bb->getExit()->asFlow() ||
1262         bb->getExit()->asFlow()->op == OP_JOIN) {
1263       BasicBlock *tailBB = convert(lastElse->successors[0]);
1264       mkFlow(OP_BRA, tailBB, CC_ALWAYS, NULL);
1265       bb->cfg.attach(&tailBB->cfg, Graph::Edge::FORWARD);
1266    }
1267
1268    if (lastThen->successors[0] == lastElse->successors[0]) {
1269       setPosition(convert(lastThen->successors[0]), true);
1270       mkFlow(OP_JOIN, NULL, CC_ALWAYS, NULL)->fixed = 1;
1271    }
1272
1273    return true;
1274 }
1275
1276 bool
1277 Converter::visit(nir_loop *loop)
1278 {
1279    curLoopDepth += 1;
1280    func->loopNestingBound = std::max(func->loopNestingBound, curLoopDepth);
1281
1282    BasicBlock *loopBB = convert(nir_loop_first_block(loop));
1283    BasicBlock *tailBB =
1284       convert(nir_cf_node_as_block(nir_cf_node_next(&loop->cf_node)));
1285    bb->cfg.attach(&loopBB->cfg, Graph::Edge::TREE);
1286
1287    mkFlow(OP_PREBREAK, tailBB, CC_ALWAYS, NULL);
1288    setPosition(loopBB, false);
1289    mkFlow(OP_PRECONT, loopBB, CC_ALWAYS, NULL);
1290
1291    foreach_list_typed(nir_cf_node, node, node, &loop->body) {
1292       if (!visit(node))
1293          return false;
1294    }
1295    Instruction *insn = bb->getExit();
1296    if (bb->cfg.incidentCount() != 0) {
1297       if (!insn || !insn->asFlow()) {
1298          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
1299          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
1300       } else if (insn && insn->op == OP_BRA && !insn->getPredicate() &&
1301                  tailBB->cfg.incidentCount() == 0) {
1302          // RA doesn't like having blocks around with no incident edge,
1303          // so we create a fake one to make it happy
1304          bb->cfg.attach(&tailBB->cfg, Graph::Edge::TREE);
1305       }
1306    }
1307
1308    curLoopDepth -= 1;
1309
1310    return true;
1311 }
1312
1313 bool
1314 Converter::visit(nir_instr *insn)
1315 {
1316    switch (insn->type) {
1317    case nir_instr_type_intrinsic:
1318       return visit(nir_instr_as_intrinsic(insn));
1319    case nir_instr_type_jump:
1320       return visit(nir_instr_as_jump(insn));
1321    case nir_instr_type_load_const:
1322       return visit(nir_instr_as_load_const(insn));
1323    default:
1324       ERROR("unknown nir_instr type %u\n", insn->type);
1325       return false;
1326    }
1327    return true;
1328 }
1329
1330 bool
1331 Converter::visit(nir_intrinsic_instr *insn)
1332 {
1333    nir_intrinsic_op op = insn->intrinsic;
1334
1335    switch (op) {
1336    default:
1337       ERROR("unknown nir_intrinsic_op %s\n", nir_intrinsic_infos[op].name);
1338       return false;
1339    }
1340
1341    return true;
1342 }
1343
1344 bool
1345 Converter::visit(nir_jump_instr *insn)
1346 {
1347    switch (insn->type) {
1348    case nir_jump_return:
1349       // TODO: this only works in the main function
1350       mkFlow(OP_BRA, exit, CC_ALWAYS, NULL);
1351       bb->cfg.attach(&exit->cfg, Graph::Edge::CROSS);
1352       break;
1353    case nir_jump_break:
1354    case nir_jump_continue: {
1355       bool isBreak = insn->type == nir_jump_break;
1356       nir_block *block = insn->instr.block;
1357       assert(!block->successors[1]);
1358       BasicBlock *target = convert(block->successors[0]);
1359       mkFlow(isBreak ? OP_BREAK : OP_CONT, target, CC_ALWAYS, NULL);
1360       bb->cfg.attach(&target->cfg, isBreak ? Graph::Edge::CROSS : Graph::Edge::BACK);
1361       break;
1362    }
1363    default:
1364       ERROR("unknown nir_jump_type %u\n", insn->type);
1365       return false;
1366    }
1367
1368    return true;
1369 }
1370
1371 bool
1372 Converter::visit(nir_load_const_instr *insn)
1373 {
1374    assert(insn->def.bit_size <= 64);
1375
1376    LValues &newDefs = convert(&insn->def);
1377    for (int i = 0; i < insn->def.num_components; i++) {
1378       switch (insn->def.bit_size) {
1379       case 64:
1380          loadImm(newDefs[i], insn->value.u64[i]);
1381          break;
1382       case 32:
1383          loadImm(newDefs[i], insn->value.u32[i]);
1384          break;
1385       case 16:
1386          loadImm(newDefs[i], insn->value.u16[i]);
1387          break;
1388       case 8:
1389          loadImm(newDefs[i], insn->value.u8[i]);
1390          break;
1391       }
1392    }
1393    return true;
1394 }
1395
1396 bool
1397 Converter::run()
1398 {
1399    bool progress;
1400
1401    if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
1402       nir_print_shader(nir, stderr);
1403
1404    NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, (nir_lower_io_options)0);
1405    NIR_PASS_V(nir, nir_lower_regs_to_ssa);
1406    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
1407    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1408    NIR_PASS_V(nir, nir_lower_alu_to_scalar);
1409    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
1410
1411    do {
1412       progress = false;
1413       NIR_PASS(progress, nir, nir_copy_prop);
1414       NIR_PASS(progress, nir, nir_opt_remove_phis);
1415       NIR_PASS(progress, nir, nir_opt_trivial_continues);
1416       NIR_PASS(progress, nir, nir_opt_cse);
1417       NIR_PASS(progress, nir, nir_opt_algebraic);
1418       NIR_PASS(progress, nir, nir_opt_constant_folding);
1419       NIR_PASS(progress, nir, nir_copy_prop);
1420       NIR_PASS(progress, nir, nir_opt_dce);
1421       NIR_PASS(progress, nir, nir_opt_dead_cf);
1422    } while (progress);
1423
1424    NIR_PASS_V(nir, nir_lower_bool_to_int32);
1425    NIR_PASS_V(nir, nir_lower_locals_to_regs);
1426    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp);
1427    NIR_PASS_V(nir, nir_convert_from_ssa, true);
1428
1429    // Garbage collect dead instructions
1430    nir_sweep(nir);
1431
1432    if (!parseNIR()) {
1433       ERROR("Couldn't prase NIR!\n");
1434       return false;
1435    }
1436
1437    if (!assignSlots()) {
1438       ERROR("Couldn't assign slots!\n");
1439       return false;
1440    }
1441
1442    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
1443       nir_print_shader(nir, stderr);
1444
1445    nir_foreach_function(function, nir) {
1446       if (!visit(function))
1447          return false;
1448    }
1449
1450    return true;
1451 }
1452
1453 } // unnamed namespace
1454
1455 namespace nv50_ir {
1456
1457 bool
1458 Program::makeFromNIR(struct nv50_ir_prog_info *info)
1459 {
1460    nir_shader *nir = (nir_shader*)info->bin.source;
1461    Converter converter(this, nir, info);
1462    bool result = converter.run();
1463    if (!result)
1464       return result;
1465    LoweringHelper lowering;
1466    lowering.run(this);
1467    tlsSize = info->bin.tlsSpace;
1468    return result;
1469 }
1470
1471 } // namespace nv50_ir