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nv50/ir: silent TGSI_PROPERTY_FS_DEPTH_LAYOUT
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "tgsi/tgsi_dump.h"
24 #include "tgsi/tgsi_scan.h"
25 #include "tgsi/tgsi_util.h"
26
27 #include <set>
28
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_util.h"
31 #include "codegen/nv50_ir_build_util.h"
32
33 namespace tgsi {
34
35 class Source;
36
37 static nv50_ir::operation translateOpcode(uint opcode);
38 static nv50_ir::DataFile translateFile(uint file);
39 static nv50_ir::TexTarget translateTexture(uint texTarg);
40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
41 static nv50_ir::CacheMode translateCacheMode(uint qualifier);
42 static nv50_ir::ImgFormat translateImgFormat(uint format);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 int getArrayId() const
101 {
102 if (isIndirect(0))
103 return fsr->Indirect.ArrayID;
104 return 0;
105 }
106
107 nv50_ir::Modifier getMod(int chan) const;
108
109 SrcRegister getIndirect(int dim) const
110 {
111 assert(fsr && isIndirect(dim));
112 if (dim)
113 return SrcRegister(fsr->DimIndirect);
114 return SrcRegister(fsr->Indirect);
115 }
116
117 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
118 {
119 assert(reg.File == TGSI_FILE_IMMEDIATE);
120 assert(!reg.Absolute);
121 assert(!reg.Negate);
122 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
123 }
124
125 private:
126 const struct tgsi_src_register reg;
127 const struct tgsi_full_src_register *fsr;
128 };
129
130 class DstRegister
131 {
132 public:
133 DstRegister(const struct tgsi_full_dst_register *dst)
134 : reg(dst->Register),
135 fdr(dst)
136 { }
137
138 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
139
140 uint getFile() const { return reg.File; }
141
142 bool is2D() const { return reg.Dimension; }
143
144 bool isIndirect(int dim) const
145 {
146 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
147 }
148
149 int getIndex(int dim) const
150 {
151 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
152 }
153
154 unsigned int getMask() const { return reg.WriteMask; }
155
156 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
157
158 SrcRegister getIndirect(int dim) const
159 {
160 assert(fdr && isIndirect(dim));
161 if (dim)
162 return SrcRegister(fdr->DimIndirect);
163 return SrcRegister(fdr->Indirect);
164 }
165
166 int getArrayId() const
167 {
168 if (isIndirect(0))
169 return fdr->Indirect.ArrayID;
170 return 0;
171 }
172
173 private:
174 const struct tgsi_dst_register reg;
175 const struct tgsi_full_dst_register *fdr;
176 };
177
178 inline uint getOpcode() const { return insn->Instruction.Opcode; }
179
180 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
181 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
182
183 // mask of used components of source s
184 unsigned int srcMask(unsigned int s) const;
185
186 SrcRegister getSrc(unsigned int s) const
187 {
188 assert(s < srcCount());
189 return SrcRegister(&insn->Src[s]);
190 }
191
192 DstRegister getDst(unsigned int d) const
193 {
194 assert(d < dstCount());
195 return DstRegister(&insn->Dst[d]);
196 }
197
198 SrcRegister getTexOffset(unsigned int i) const
199 {
200 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
201 return SrcRegister(insn->TexOffsets[i]);
202 }
203
204 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
205
206 bool checkDstSrcAliasing() const;
207
208 inline nv50_ir::operation getOP() const {
209 return translateOpcode(getOpcode()); }
210
211 nv50_ir::DataType inferSrcType() const;
212 nv50_ir::DataType inferDstType() const;
213
214 nv50_ir::CondCode getSetCond() const;
215
216 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
217
218 nv50_ir::CacheMode getCacheMode() const {
219 if (!insn->Instruction.Memory)
220 return nv50_ir::CACHE_CA;
221 return translateCacheMode(insn->Memory.Qualifier);
222 }
223
224 inline uint getLabel() { return insn->Label.Label; }
225
226 unsigned getSaturate() const { return insn->Instruction.Saturate; }
227
228 void print() const
229 {
230 tgsi_dump_instruction(insn, 1);
231 }
232
233 private:
234 const struct tgsi_full_instruction *insn;
235 };
236
237 unsigned int Instruction::srcMask(unsigned int s) const
238 {
239 unsigned int mask = insn->Dst[0].Register.WriteMask;
240
241 switch (insn->Instruction.Opcode) {
242 case TGSI_OPCODE_COS:
243 case TGSI_OPCODE_SIN:
244 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
245 case TGSI_OPCODE_DP2:
246 return 0x3;
247 case TGSI_OPCODE_DP3:
248 return 0x7;
249 case TGSI_OPCODE_DP4:
250 case TGSI_OPCODE_DPH:
251 case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
252 return 0xf;
253 case TGSI_OPCODE_DST:
254 return mask & (s ? 0xa : 0x6);
255 case TGSI_OPCODE_EX2:
256 case TGSI_OPCODE_EXP:
257 case TGSI_OPCODE_LG2:
258 case TGSI_OPCODE_LOG:
259 case TGSI_OPCODE_POW:
260 case TGSI_OPCODE_RCP:
261 case TGSI_OPCODE_RSQ:
262 case TGSI_OPCODE_SCS:
263 return 0x1;
264 case TGSI_OPCODE_IF:
265 case TGSI_OPCODE_UIF:
266 return 0x1;
267 case TGSI_OPCODE_LIT:
268 return 0xb;
269 case TGSI_OPCODE_TEX2:
270 case TGSI_OPCODE_TXB2:
271 case TGSI_OPCODE_TXL2:
272 return (s == 0) ? 0xf : 0x3;
273 case TGSI_OPCODE_TEX:
274 case TGSI_OPCODE_TXB:
275 case TGSI_OPCODE_TXD:
276 case TGSI_OPCODE_TXL:
277 case TGSI_OPCODE_TXP:
278 case TGSI_OPCODE_LODQ:
279 {
280 const struct tgsi_instruction_texture *tex = &insn->Texture;
281
282 assert(insn->Instruction.Texture);
283
284 mask = 0x7;
285 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
286 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
287 mask |= 0x8; /* bias, lod or proj */
288
289 switch (tex->Texture) {
290 case TGSI_TEXTURE_1D:
291 mask &= 0x9;
292 break;
293 case TGSI_TEXTURE_SHADOW1D:
294 mask &= 0xd;
295 break;
296 case TGSI_TEXTURE_1D_ARRAY:
297 case TGSI_TEXTURE_2D:
298 case TGSI_TEXTURE_RECT:
299 mask &= 0xb;
300 break;
301 case TGSI_TEXTURE_CUBE_ARRAY:
302 case TGSI_TEXTURE_SHADOW2D_ARRAY:
303 case TGSI_TEXTURE_SHADOWCUBE:
304 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
305 mask |= 0x8;
306 break;
307 default:
308 break;
309 }
310 }
311 return mask;
312 case TGSI_OPCODE_XPD:
313 {
314 unsigned int x = 0;
315 if (mask & 1) x |= 0x6;
316 if (mask & 2) x |= 0x5;
317 if (mask & 4) x |= 0x3;
318 return x;
319 }
320 case TGSI_OPCODE_D2I:
321 case TGSI_OPCODE_D2U:
322 case TGSI_OPCODE_D2F:
323 case TGSI_OPCODE_DSLT:
324 case TGSI_OPCODE_DSGE:
325 case TGSI_OPCODE_DSEQ:
326 case TGSI_OPCODE_DSNE:
327 switch (util_bitcount(mask)) {
328 case 1: return 0x3;
329 case 2: return 0xf;
330 default:
331 assert(!"unexpected mask");
332 return 0xf;
333 }
334 case TGSI_OPCODE_I2D:
335 case TGSI_OPCODE_U2D:
336 case TGSI_OPCODE_F2D: {
337 unsigned int x = 0;
338 if ((mask & 0x3) == 0x3)
339 x |= 1;
340 if ((mask & 0xc) == 0xc)
341 x |= 2;
342 return x;
343 }
344 case TGSI_OPCODE_PK2H:
345 return 0x3;
346 case TGSI_OPCODE_UP2H:
347 return 0x1;
348 default:
349 break;
350 }
351
352 return mask;
353 }
354
355 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
356 {
357 nv50_ir::Modifier m(0);
358
359 if (reg.Absolute)
360 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
361 if (reg.Negate)
362 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
363 return m;
364 }
365
366 static nv50_ir::DataFile translateFile(uint file)
367 {
368 switch (file) {
369 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
370 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
371 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
372 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
373 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
374 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
375 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
376 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
377 case TGSI_FILE_BUFFER: return nv50_ir::FILE_MEMORY_BUFFER;
378 case TGSI_FILE_IMAGE: return nv50_ir::FILE_MEMORY_GLOBAL;
379 case TGSI_FILE_MEMORY: return nv50_ir::FILE_MEMORY_GLOBAL;
380 case TGSI_FILE_SAMPLER:
381 case TGSI_FILE_NULL:
382 default:
383 return nv50_ir::FILE_NULL;
384 }
385 }
386
387 static nv50_ir::SVSemantic translateSysVal(uint sysval)
388 {
389 switch (sysval) {
390 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
391 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
392 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
393 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
394 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
395 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
396 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
397 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
398 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
399 case TGSI_SEMANTIC_SAMPLEID: return nv50_ir::SV_SAMPLE_INDEX;
400 case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
401 case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
402 case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
403 case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD;
404 case TGSI_SEMANTIC_TESSOUTER: return nv50_ir::SV_TESS_OUTER;
405 case TGSI_SEMANTIC_TESSINNER: return nv50_ir::SV_TESS_INNER;
406 case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
407 case TGSI_SEMANTIC_HELPER_INVOCATION: return nv50_ir::SV_THREAD_KILL;
408 case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
409 case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
410 case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
411 case TGSI_SEMANTIC_WORK_DIM: return nv50_ir::SV_WORK_DIM;
412 default:
413 assert(0);
414 return nv50_ir::SV_CLOCK;
415 }
416 }
417
418 #define NV50_IR_TEX_TARG_CASE(a, b) \
419 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
420
421 static nv50_ir::TexTarget translateTexture(uint tex)
422 {
423 switch (tex) {
424 NV50_IR_TEX_TARG_CASE(1D, 1D);
425 NV50_IR_TEX_TARG_CASE(2D, 2D);
426 NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
427 NV50_IR_TEX_TARG_CASE(3D, 3D);
428 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
429 NV50_IR_TEX_TARG_CASE(RECT, RECT);
430 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
431 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
432 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
433 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
434 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
435 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
436 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
437 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
438 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
439 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
440 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
441 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
442
443 case TGSI_TEXTURE_UNKNOWN:
444 default:
445 assert(!"invalid texture target");
446 return nv50_ir::TEX_TARGET_2D;
447 }
448 }
449
450 static nv50_ir::CacheMode translateCacheMode(uint qualifier)
451 {
452 if (qualifier & TGSI_MEMORY_VOLATILE)
453 return nv50_ir::CACHE_CV;
454 if (qualifier & TGSI_MEMORY_COHERENT)
455 return nv50_ir::CACHE_CG;
456 return nv50_ir::CACHE_CA;
457 }
458
459 static nv50_ir::ImgFormat translateImgFormat(uint format)
460 {
461
462 #define FMT_CASE(a, b) \
463 case PIPE_FORMAT_ ## a: return nv50_ir::FMT_ ## b
464
465 switch (format) {
466 FMT_CASE(NONE, NONE);
467
468 FMT_CASE(R32G32B32A32_FLOAT, RGBA32F);
469 FMT_CASE(R16G16B16A16_FLOAT, RGBA16F);
470 FMT_CASE(R32G32_FLOAT, RG32F);
471 FMT_CASE(R16G16_FLOAT, RG16F);
472 FMT_CASE(R11G11B10_FLOAT, R11G11B10F);
473 FMT_CASE(R32_FLOAT, R32F);
474 FMT_CASE(R16_FLOAT, R16F);
475
476 FMT_CASE(R32G32B32A32_UINT, RGBA32UI);
477 FMT_CASE(R16G16B16A16_UINT, RGBA16UI);
478 FMT_CASE(R10G10B10A2_UINT, RGB10A2UI);
479 FMT_CASE(R8G8B8A8_UINT, RGBA8UI);
480 FMT_CASE(R32G32_UINT, RG32UI);
481 FMT_CASE(R16G16_UINT, RG16UI);
482 FMT_CASE(R8G8_UINT, RG8UI);
483 FMT_CASE(R32_UINT, R32UI);
484 FMT_CASE(R16_UINT, R16UI);
485 FMT_CASE(R8_UINT, R8UI);
486
487 FMT_CASE(R32G32B32A32_SINT, RGBA32I);
488 FMT_CASE(R16G16B16A16_SINT, RGBA16I);
489 FMT_CASE(R8G8B8A8_SINT, RGBA8I);
490 FMT_CASE(R32G32_SINT, RG32I);
491 FMT_CASE(R16G16_SINT, RG16I);
492 FMT_CASE(R8G8_SINT, RG8I);
493 FMT_CASE(R32_SINT, R32I);
494 FMT_CASE(R16_SINT, R16I);
495 FMT_CASE(R8_SINT, R8I);
496
497 FMT_CASE(R16G16B16A16_UNORM, RGBA16);
498 FMT_CASE(R10G10B10A2_UNORM, RGB10A2);
499 FMT_CASE(R8G8B8A8_UNORM, RGBA8);
500 FMT_CASE(R16G16_UNORM, RG16);
501 FMT_CASE(R8G8_UNORM, RG8);
502 FMT_CASE(R16_UNORM, R16);
503 FMT_CASE(R8_UNORM, R8);
504
505 FMT_CASE(R16G16B16A16_SNORM, RGBA16_SNORM);
506 FMT_CASE(R8G8B8A8_SNORM, RGBA8_SNORM);
507 FMT_CASE(R16G16_SNORM, RG16_SNORM);
508 FMT_CASE(R8G8_SNORM, RG8_SNORM);
509 FMT_CASE(R16_SNORM, R16_SNORM);
510 FMT_CASE(R8_SNORM, R8_SNORM);
511
512 FMT_CASE(B8G8R8A8_UNORM, BGRA8);
513 }
514
515 assert(!"Unexpected format");
516 return nv50_ir::FMT_NONE;
517 }
518
519 nv50_ir::DataType Instruction::inferSrcType() const
520 {
521 switch (getOpcode()) {
522 case TGSI_OPCODE_UIF:
523 case TGSI_OPCODE_AND:
524 case TGSI_OPCODE_OR:
525 case TGSI_OPCODE_XOR:
526 case TGSI_OPCODE_NOT:
527 case TGSI_OPCODE_SHL:
528 case TGSI_OPCODE_U2F:
529 case TGSI_OPCODE_U2D:
530 case TGSI_OPCODE_UADD:
531 case TGSI_OPCODE_UDIV:
532 case TGSI_OPCODE_UMOD:
533 case TGSI_OPCODE_UMAD:
534 case TGSI_OPCODE_UMUL:
535 case TGSI_OPCODE_UMUL_HI:
536 case TGSI_OPCODE_UMAX:
537 case TGSI_OPCODE_UMIN:
538 case TGSI_OPCODE_USEQ:
539 case TGSI_OPCODE_USGE:
540 case TGSI_OPCODE_USLT:
541 case TGSI_OPCODE_USNE:
542 case TGSI_OPCODE_USHR:
543 case TGSI_OPCODE_ATOMUADD:
544 case TGSI_OPCODE_ATOMXCHG:
545 case TGSI_OPCODE_ATOMCAS:
546 case TGSI_OPCODE_ATOMAND:
547 case TGSI_OPCODE_ATOMOR:
548 case TGSI_OPCODE_ATOMXOR:
549 case TGSI_OPCODE_ATOMUMIN:
550 case TGSI_OPCODE_ATOMUMAX:
551 case TGSI_OPCODE_UBFE:
552 case TGSI_OPCODE_UMSB:
553 case TGSI_OPCODE_UP2H:
554 case TGSI_OPCODE_VOTE_ALL:
555 case TGSI_OPCODE_VOTE_ANY:
556 case TGSI_OPCODE_VOTE_EQ:
557 return nv50_ir::TYPE_U32;
558 case TGSI_OPCODE_I2F:
559 case TGSI_OPCODE_I2D:
560 case TGSI_OPCODE_IDIV:
561 case TGSI_OPCODE_IMUL_HI:
562 case TGSI_OPCODE_IMAX:
563 case TGSI_OPCODE_IMIN:
564 case TGSI_OPCODE_IABS:
565 case TGSI_OPCODE_INEG:
566 case TGSI_OPCODE_ISGE:
567 case TGSI_OPCODE_ISHR:
568 case TGSI_OPCODE_ISLT:
569 case TGSI_OPCODE_ISSG:
570 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
571 case TGSI_OPCODE_MOD:
572 case TGSI_OPCODE_UARL:
573 case TGSI_OPCODE_ATOMIMIN:
574 case TGSI_OPCODE_ATOMIMAX:
575 case TGSI_OPCODE_IBFE:
576 case TGSI_OPCODE_IMSB:
577 return nv50_ir::TYPE_S32;
578 case TGSI_OPCODE_D2F:
579 case TGSI_OPCODE_D2I:
580 case TGSI_OPCODE_D2U:
581 case TGSI_OPCODE_DABS:
582 case TGSI_OPCODE_DNEG:
583 case TGSI_OPCODE_DADD:
584 case TGSI_OPCODE_DMUL:
585 case TGSI_OPCODE_DMAX:
586 case TGSI_OPCODE_DMIN:
587 case TGSI_OPCODE_DSLT:
588 case TGSI_OPCODE_DSGE:
589 case TGSI_OPCODE_DSEQ:
590 case TGSI_OPCODE_DSNE:
591 case TGSI_OPCODE_DRCP:
592 case TGSI_OPCODE_DSQRT:
593 case TGSI_OPCODE_DMAD:
594 case TGSI_OPCODE_DFMA:
595 case TGSI_OPCODE_DFRAC:
596 case TGSI_OPCODE_DRSQ:
597 case TGSI_OPCODE_DTRUNC:
598 case TGSI_OPCODE_DCEIL:
599 case TGSI_OPCODE_DFLR:
600 case TGSI_OPCODE_DROUND:
601 return nv50_ir::TYPE_F64;
602 default:
603 return nv50_ir::TYPE_F32;
604 }
605 }
606
607 nv50_ir::DataType Instruction::inferDstType() const
608 {
609 switch (getOpcode()) {
610 case TGSI_OPCODE_D2U:
611 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
612 case TGSI_OPCODE_D2I:
613 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
614 case TGSI_OPCODE_FSEQ:
615 case TGSI_OPCODE_FSGE:
616 case TGSI_OPCODE_FSLT:
617 case TGSI_OPCODE_FSNE:
618 case TGSI_OPCODE_DSEQ:
619 case TGSI_OPCODE_DSGE:
620 case TGSI_OPCODE_DSLT:
621 case TGSI_OPCODE_DSNE:
622 case TGSI_OPCODE_PK2H:
623 return nv50_ir::TYPE_U32;
624 case TGSI_OPCODE_I2F:
625 case TGSI_OPCODE_U2F:
626 case TGSI_OPCODE_D2F:
627 case TGSI_OPCODE_UP2H:
628 return nv50_ir::TYPE_F32;
629 case TGSI_OPCODE_I2D:
630 case TGSI_OPCODE_U2D:
631 case TGSI_OPCODE_F2D:
632 return nv50_ir::TYPE_F64;
633 default:
634 return inferSrcType();
635 }
636 }
637
638 nv50_ir::CondCode Instruction::getSetCond() const
639 {
640 using namespace nv50_ir;
641
642 switch (getOpcode()) {
643 case TGSI_OPCODE_SLT:
644 case TGSI_OPCODE_ISLT:
645 case TGSI_OPCODE_USLT:
646 case TGSI_OPCODE_FSLT:
647 case TGSI_OPCODE_DSLT:
648 return CC_LT;
649 case TGSI_OPCODE_SLE:
650 return CC_LE;
651 case TGSI_OPCODE_SGE:
652 case TGSI_OPCODE_ISGE:
653 case TGSI_OPCODE_USGE:
654 case TGSI_OPCODE_FSGE:
655 case TGSI_OPCODE_DSGE:
656 return CC_GE;
657 case TGSI_OPCODE_SGT:
658 return CC_GT;
659 case TGSI_OPCODE_SEQ:
660 case TGSI_OPCODE_USEQ:
661 case TGSI_OPCODE_FSEQ:
662 case TGSI_OPCODE_DSEQ:
663 return CC_EQ;
664 case TGSI_OPCODE_SNE:
665 case TGSI_OPCODE_FSNE:
666 case TGSI_OPCODE_DSNE:
667 return CC_NEU;
668 case TGSI_OPCODE_USNE:
669 return CC_NE;
670 default:
671 return CC_ALWAYS;
672 }
673 }
674
675 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
676
677 static nv50_ir::operation translateOpcode(uint opcode)
678 {
679 switch (opcode) {
680 NV50_IR_OPCODE_CASE(ARL, SHL);
681 NV50_IR_OPCODE_CASE(MOV, MOV);
682
683 NV50_IR_OPCODE_CASE(RCP, RCP);
684 NV50_IR_OPCODE_CASE(RSQ, RSQ);
685 NV50_IR_OPCODE_CASE(SQRT, SQRT);
686
687 NV50_IR_OPCODE_CASE(MUL, MUL);
688 NV50_IR_OPCODE_CASE(ADD, ADD);
689
690 NV50_IR_OPCODE_CASE(MIN, MIN);
691 NV50_IR_OPCODE_CASE(MAX, MAX);
692 NV50_IR_OPCODE_CASE(SLT, SET);
693 NV50_IR_OPCODE_CASE(SGE, SET);
694 NV50_IR_OPCODE_CASE(MAD, MAD);
695 NV50_IR_OPCODE_CASE(FMA, FMA);
696 NV50_IR_OPCODE_CASE(SUB, SUB);
697
698 NV50_IR_OPCODE_CASE(FLR, FLOOR);
699 NV50_IR_OPCODE_CASE(ROUND, CVT);
700 NV50_IR_OPCODE_CASE(EX2, EX2);
701 NV50_IR_OPCODE_CASE(LG2, LG2);
702 NV50_IR_OPCODE_CASE(POW, POW);
703
704 NV50_IR_OPCODE_CASE(ABS, ABS);
705
706 NV50_IR_OPCODE_CASE(COS, COS);
707 NV50_IR_OPCODE_CASE(DDX, DFDX);
708 NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
709 NV50_IR_OPCODE_CASE(DDY, DFDY);
710 NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
711 NV50_IR_OPCODE_CASE(KILL, DISCARD);
712
713 NV50_IR_OPCODE_CASE(SEQ, SET);
714 NV50_IR_OPCODE_CASE(SGT, SET);
715 NV50_IR_OPCODE_CASE(SIN, SIN);
716 NV50_IR_OPCODE_CASE(SLE, SET);
717 NV50_IR_OPCODE_CASE(SNE, SET);
718 NV50_IR_OPCODE_CASE(TEX, TEX);
719 NV50_IR_OPCODE_CASE(TXD, TXD);
720 NV50_IR_OPCODE_CASE(TXP, TEX);
721
722 NV50_IR_OPCODE_CASE(CAL, CALL);
723 NV50_IR_OPCODE_CASE(RET, RET);
724 NV50_IR_OPCODE_CASE(CMP, SLCT);
725
726 NV50_IR_OPCODE_CASE(TXB, TXB);
727
728 NV50_IR_OPCODE_CASE(DIV, DIV);
729
730 NV50_IR_OPCODE_CASE(TXL, TXL);
731
732 NV50_IR_OPCODE_CASE(CEIL, CEIL);
733 NV50_IR_OPCODE_CASE(I2F, CVT);
734 NV50_IR_OPCODE_CASE(NOT, NOT);
735 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
736 NV50_IR_OPCODE_CASE(SHL, SHL);
737
738 NV50_IR_OPCODE_CASE(AND, AND);
739 NV50_IR_OPCODE_CASE(OR, OR);
740 NV50_IR_OPCODE_CASE(MOD, MOD);
741 NV50_IR_OPCODE_CASE(XOR, XOR);
742 NV50_IR_OPCODE_CASE(SAD, SAD);
743 NV50_IR_OPCODE_CASE(TXF, TXF);
744 NV50_IR_OPCODE_CASE(TXQ, TXQ);
745 NV50_IR_OPCODE_CASE(TXQS, TXQ);
746 NV50_IR_OPCODE_CASE(TG4, TXG);
747 NV50_IR_OPCODE_CASE(LODQ, TXLQ);
748
749 NV50_IR_OPCODE_CASE(EMIT, EMIT);
750 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
751
752 NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
753
754 NV50_IR_OPCODE_CASE(F2I, CVT);
755 NV50_IR_OPCODE_CASE(FSEQ, SET);
756 NV50_IR_OPCODE_CASE(FSGE, SET);
757 NV50_IR_OPCODE_CASE(FSLT, SET);
758 NV50_IR_OPCODE_CASE(FSNE, SET);
759 NV50_IR_OPCODE_CASE(IDIV, DIV);
760 NV50_IR_OPCODE_CASE(IMAX, MAX);
761 NV50_IR_OPCODE_CASE(IMIN, MIN);
762 NV50_IR_OPCODE_CASE(IABS, ABS);
763 NV50_IR_OPCODE_CASE(INEG, NEG);
764 NV50_IR_OPCODE_CASE(ISGE, SET);
765 NV50_IR_OPCODE_CASE(ISHR, SHR);
766 NV50_IR_OPCODE_CASE(ISLT, SET);
767 NV50_IR_OPCODE_CASE(F2U, CVT);
768 NV50_IR_OPCODE_CASE(U2F, CVT);
769 NV50_IR_OPCODE_CASE(UADD, ADD);
770 NV50_IR_OPCODE_CASE(UDIV, DIV);
771 NV50_IR_OPCODE_CASE(UMAD, MAD);
772 NV50_IR_OPCODE_CASE(UMAX, MAX);
773 NV50_IR_OPCODE_CASE(UMIN, MIN);
774 NV50_IR_OPCODE_CASE(UMOD, MOD);
775 NV50_IR_OPCODE_CASE(UMUL, MUL);
776 NV50_IR_OPCODE_CASE(USEQ, SET);
777 NV50_IR_OPCODE_CASE(USGE, SET);
778 NV50_IR_OPCODE_CASE(USHR, SHR);
779 NV50_IR_OPCODE_CASE(USLT, SET);
780 NV50_IR_OPCODE_CASE(USNE, SET);
781
782 NV50_IR_OPCODE_CASE(DABS, ABS);
783 NV50_IR_OPCODE_CASE(DNEG, NEG);
784 NV50_IR_OPCODE_CASE(DADD, ADD);
785 NV50_IR_OPCODE_CASE(DMUL, MUL);
786 NV50_IR_OPCODE_CASE(DMAX, MAX);
787 NV50_IR_OPCODE_CASE(DMIN, MIN);
788 NV50_IR_OPCODE_CASE(DSLT, SET);
789 NV50_IR_OPCODE_CASE(DSGE, SET);
790 NV50_IR_OPCODE_CASE(DSEQ, SET);
791 NV50_IR_OPCODE_CASE(DSNE, SET);
792 NV50_IR_OPCODE_CASE(DRCP, RCP);
793 NV50_IR_OPCODE_CASE(DSQRT, SQRT);
794 NV50_IR_OPCODE_CASE(DMAD, MAD);
795 NV50_IR_OPCODE_CASE(DFMA, FMA);
796 NV50_IR_OPCODE_CASE(D2I, CVT);
797 NV50_IR_OPCODE_CASE(D2U, CVT);
798 NV50_IR_OPCODE_CASE(I2D, CVT);
799 NV50_IR_OPCODE_CASE(U2D, CVT);
800 NV50_IR_OPCODE_CASE(DRSQ, RSQ);
801 NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
802 NV50_IR_OPCODE_CASE(DCEIL, CEIL);
803 NV50_IR_OPCODE_CASE(DFLR, FLOOR);
804 NV50_IR_OPCODE_CASE(DROUND, CVT);
805
806 NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
807 NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
808
809 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
810 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
811 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
812 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
813 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
814 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
815 NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
816 NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
817 NV50_IR_OPCODE_CASE(GATHER4, TXG);
818 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
819
820 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
821 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
822 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
823 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
824 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
825 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
826 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
827 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
828 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
829 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
830
831 NV50_IR_OPCODE_CASE(TEX2, TEX);
832 NV50_IR_OPCODE_CASE(TXB2, TXB);
833 NV50_IR_OPCODE_CASE(TXL2, TXL);
834
835 NV50_IR_OPCODE_CASE(IBFE, EXTBF);
836 NV50_IR_OPCODE_CASE(UBFE, EXTBF);
837 NV50_IR_OPCODE_CASE(BFI, INSBF);
838 NV50_IR_OPCODE_CASE(BREV, EXTBF);
839 NV50_IR_OPCODE_CASE(POPC, POPCNT);
840 NV50_IR_OPCODE_CASE(LSB, BFIND);
841 NV50_IR_OPCODE_CASE(IMSB, BFIND);
842 NV50_IR_OPCODE_CASE(UMSB, BFIND);
843
844 NV50_IR_OPCODE_CASE(VOTE_ALL, VOTE);
845 NV50_IR_OPCODE_CASE(VOTE_ANY, VOTE);
846 NV50_IR_OPCODE_CASE(VOTE_EQ, VOTE);
847
848 NV50_IR_OPCODE_CASE(END, EXIT);
849
850 default:
851 return nv50_ir::OP_NOP;
852 }
853 }
854
855 static uint16_t opcodeToSubOp(uint opcode)
856 {
857 switch (opcode) {
858 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
859 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
860 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
861 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
862 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
863 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
864 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
865 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
866 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
867 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
868 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
869 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
870 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
871 case TGSI_OPCODE_IMUL_HI:
872 case TGSI_OPCODE_UMUL_HI:
873 return NV50_IR_SUBOP_MUL_HIGH;
874 case TGSI_OPCODE_VOTE_ALL: return NV50_IR_SUBOP_VOTE_ALL;
875 case TGSI_OPCODE_VOTE_ANY: return NV50_IR_SUBOP_VOTE_ANY;
876 case TGSI_OPCODE_VOTE_EQ: return NV50_IR_SUBOP_VOTE_UNI;
877 default:
878 return 0;
879 }
880 }
881
882 bool Instruction::checkDstSrcAliasing() const
883 {
884 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
885 return false;
886
887 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
888 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
889 break;
890 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
891 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
892 return true;
893 }
894 return false;
895 }
896
897 class Source
898 {
899 public:
900 Source(struct nv50_ir_prog_info *);
901 ~Source();
902
903 public:
904 bool scanSource();
905 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
906
907 public:
908 struct tgsi_shader_info scan;
909 struct tgsi_full_instruction *insns;
910 const struct tgsi_token *tokens;
911 struct nv50_ir_prog_info *info;
912
913 nv50_ir::DynArray tempArrays;
914 nv50_ir::DynArray immdArrays;
915
916 typedef nv50_ir::BuildUtil::Location Location;
917 // these registers are per-subroutine, cannot be used for parameter passing
918 std::set<Location> locals;
919
920 std::set<int> indirectTempArrays;
921 std::map<int, int> indirectTempOffsets;
922 std::map<int, std::pair<int, int> > tempArrayInfo;
923 std::vector<int> tempArrayId;
924
925 int clipVertexOutput;
926
927 struct TextureView {
928 uint8_t target; // TGSI_TEXTURE_*
929 };
930 std::vector<TextureView> textureViews;
931
932 /*
933 struct Resource {
934 uint8_t target; // TGSI_TEXTURE_*
935 bool raw;
936 uint8_t slot; // $surface index
937 };
938 std::vector<Resource> resources;
939 */
940
941 struct Image {
942 uint8_t target; // TGSI_TEXTURE_*
943 bool raw;
944 uint8_t slot;
945 uint16_t format; // PIPE_FORMAT_*
946 };
947 std::vector<Image> images;
948
949 struct MemoryFile {
950 uint8_t mem_type; // TGSI_MEMORY_TYPE_*
951 };
952 std::vector<MemoryFile> memoryFiles;
953
954 private:
955 int inferSysValDirection(unsigned sn) const;
956 bool scanDeclaration(const struct tgsi_full_declaration *);
957 bool scanInstruction(const struct tgsi_full_instruction *);
958 void scanProperty(const struct tgsi_full_property *);
959 void scanImmediate(const struct tgsi_full_immediate *);
960
961 inline bool isEdgeFlagPassthrough(const Instruction&) const;
962 };
963
964 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
965 {
966 tokens = (const struct tgsi_token *)info->bin.source;
967
968 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
969 tgsi_dump(tokens, 0);
970 }
971
972 Source::~Source()
973 {
974 if (insns)
975 FREE(insns);
976
977 if (info->immd.data)
978 FREE(info->immd.data);
979 if (info->immd.type)
980 FREE(info->immd.type);
981 }
982
983 bool Source::scanSource()
984 {
985 unsigned insnCount = 0;
986 struct tgsi_parse_context parse;
987
988 tgsi_scan_shader(tokens, &scan);
989
990 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
991 sizeof(insns[0]));
992 if (!insns)
993 return false;
994
995 clipVertexOutput = -1;
996
997 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
998 //resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
999 images.resize(scan.file_max[TGSI_FILE_IMAGE] + 1);
1000 tempArrayId.resize(scan.file_max[TGSI_FILE_TEMPORARY] + 1);
1001 memoryFiles.resize(scan.file_max[TGSI_FILE_MEMORY] + 1);
1002
1003 info->immd.bufSize = 0;
1004
1005 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
1006 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
1007 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
1008
1009 if (info->type == PIPE_SHADER_FRAGMENT) {
1010 info->prop.fp.writesDepth = scan.writes_z;
1011 info->prop.fp.usesDiscard = scan.uses_kill || info->io.alphaRefBase;
1012 } else
1013 if (info->type == PIPE_SHADER_GEOMETRY) {
1014 info->prop.gp.instanceCount = 1; // default value
1015 }
1016
1017 info->io.viewportId = -1;
1018 info->prop.cp.numThreads = 1;
1019
1020 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
1021 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
1022
1023 tgsi_parse_init(&parse, tokens);
1024 while (!tgsi_parse_end_of_tokens(&parse)) {
1025 tgsi_parse_token(&parse);
1026
1027 switch (parse.FullToken.Token.Type) {
1028 case TGSI_TOKEN_TYPE_IMMEDIATE:
1029 scanImmediate(&parse.FullToken.FullImmediate);
1030 break;
1031 case TGSI_TOKEN_TYPE_DECLARATION:
1032 scanDeclaration(&parse.FullToken.FullDeclaration);
1033 break;
1034 case TGSI_TOKEN_TYPE_INSTRUCTION:
1035 insns[insnCount++] = parse.FullToken.FullInstruction;
1036 scanInstruction(&parse.FullToken.FullInstruction);
1037 break;
1038 case TGSI_TOKEN_TYPE_PROPERTY:
1039 scanProperty(&parse.FullToken.FullProperty);
1040 break;
1041 default:
1042 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
1043 break;
1044 }
1045 }
1046 tgsi_parse_free(&parse);
1047
1048 if (indirectTempArrays.size()) {
1049 int tempBase = 0;
1050 for (std::set<int>::const_iterator it = indirectTempArrays.begin();
1051 it != indirectTempArrays.end(); ++it) {
1052 std::pair<int, int>& info = tempArrayInfo[*it];
1053 indirectTempOffsets.insert(std::make_pair(*it, tempBase - info.first));
1054 tempBase += info.second;
1055 }
1056 info->bin.tlsSpace += tempBase * 16;
1057 }
1058
1059 if (info->io.genUserClip > 0) {
1060 info->io.clipDistances = info->io.genUserClip;
1061
1062 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1063
1064 for (unsigned int n = 0; n < nOut; ++n) {
1065 unsigned int i = info->numOutputs++;
1066 info->out[i].id = i;
1067 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1068 info->out[i].si = n;
1069 info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1070 }
1071 }
1072
1073 return info->assignSlots(info) == 0;
1074 }
1075
1076 void Source::scanProperty(const struct tgsi_full_property *prop)
1077 {
1078 switch (prop->Property.PropertyName) {
1079 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1080 info->prop.gp.outputPrim = prop->u[0].Data;
1081 break;
1082 case TGSI_PROPERTY_GS_INPUT_PRIM:
1083 info->prop.gp.inputPrim = prop->u[0].Data;
1084 break;
1085 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1086 info->prop.gp.maxVertices = prop->u[0].Data;
1087 break;
1088 case TGSI_PROPERTY_GS_INVOCATIONS:
1089 info->prop.gp.instanceCount = prop->u[0].Data;
1090 break;
1091 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1092 info->prop.fp.separateFragData = true;
1093 break;
1094 case TGSI_PROPERTY_FS_COORD_ORIGIN:
1095 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
1096 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
1097 // we don't care
1098 break;
1099 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1100 info->io.genUserClip = -1;
1101 break;
1102 case TGSI_PROPERTY_TCS_VERTICES_OUT:
1103 info->prop.tp.outputPatchSize = prop->u[0].Data;
1104 break;
1105 case TGSI_PROPERTY_TES_PRIM_MODE:
1106 info->prop.tp.domain = prop->u[0].Data;
1107 break;
1108 case TGSI_PROPERTY_TES_SPACING:
1109 info->prop.tp.partitioning = prop->u[0].Data;
1110 break;
1111 case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
1112 info->prop.tp.winding = prop->u[0].Data;
1113 break;
1114 case TGSI_PROPERTY_TES_POINT_MODE:
1115 if (prop->u[0].Data)
1116 info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
1117 else
1118 info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
1119 break;
1120 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
1121 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
1122 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
1123 info->prop.cp.numThreads *= prop->u[0].Data;
1124 break;
1125 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
1126 info->io.clipDistances = prop->u[0].Data;
1127 break;
1128 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
1129 info->io.cullDistances = prop->u[0].Data;
1130 break;
1131 case TGSI_PROPERTY_NEXT_SHADER:
1132 /* Do not need to know the next shader stage. */
1133 break;
1134 case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
1135 info->prop.fp.earlyFragTests = prop->u[0].Data;
1136 break;
1137 default:
1138 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
1139 break;
1140 }
1141 }
1142
1143 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
1144 {
1145 const unsigned n = info->immd.count++;
1146
1147 assert(n < scan.immediate_count);
1148
1149 for (int c = 0; c < 4; ++c)
1150 info->immd.data[n * 4 + c] = imm->u[c].Uint;
1151
1152 info->immd.type[n] = imm->Immediate.DataType;
1153 }
1154
1155 int Source::inferSysValDirection(unsigned sn) const
1156 {
1157 switch (sn) {
1158 case TGSI_SEMANTIC_INSTANCEID:
1159 case TGSI_SEMANTIC_VERTEXID:
1160 return 1;
1161 case TGSI_SEMANTIC_LAYER:
1162 #if 0
1163 case TGSI_SEMANTIC_VIEWPORTINDEX:
1164 return 0;
1165 #endif
1166 case TGSI_SEMANTIC_PRIMID:
1167 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
1168 default:
1169 return 0;
1170 }
1171 }
1172
1173 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
1174 {
1175 unsigned i, c;
1176 unsigned sn = TGSI_SEMANTIC_GENERIC;
1177 unsigned si = 0;
1178 const unsigned first = decl->Range.First, last = decl->Range.Last;
1179 const int arrayId = decl->Array.ArrayID;
1180
1181 if (decl->Declaration.Semantic) {
1182 sn = decl->Semantic.Name;
1183 si = decl->Semantic.Index;
1184 }
1185
1186 if (decl->Declaration.Local || decl->Declaration.File == TGSI_FILE_ADDRESS) {
1187 for (i = first; i <= last; ++i) {
1188 for (c = 0; c < 4; ++c) {
1189 locals.insert(
1190 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1191 }
1192 }
1193 }
1194
1195 switch (decl->Declaration.File) {
1196 case TGSI_FILE_INPUT:
1197 if (info->type == PIPE_SHADER_VERTEX) {
1198 // all vertex attributes are equal
1199 for (i = first; i <= last; ++i) {
1200 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1201 info->in[i].si = i;
1202 }
1203 } else {
1204 for (i = first; i <= last; ++i, ++si) {
1205 info->in[i].id = i;
1206 info->in[i].sn = sn;
1207 info->in[i].si = si;
1208 if (info->type == PIPE_SHADER_FRAGMENT) {
1209 // translate interpolation mode
1210 switch (decl->Interp.Interpolate) {
1211 case TGSI_INTERPOLATE_CONSTANT:
1212 info->in[i].flat = 1;
1213 break;
1214 case TGSI_INTERPOLATE_COLOR:
1215 info->in[i].sc = 1;
1216 break;
1217 case TGSI_INTERPOLATE_LINEAR:
1218 info->in[i].linear = 1;
1219 break;
1220 default:
1221 break;
1222 }
1223 if (decl->Interp.Location)
1224 info->in[i].centroid = 1;
1225 }
1226
1227 if (sn == TGSI_SEMANTIC_PATCH)
1228 info->in[i].patch = 1;
1229 if (sn == TGSI_SEMANTIC_PATCH)
1230 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1231 }
1232 }
1233 break;
1234 case TGSI_FILE_OUTPUT:
1235 for (i = first; i <= last; ++i, ++si) {
1236 switch (sn) {
1237 case TGSI_SEMANTIC_POSITION:
1238 if (info->type == PIPE_SHADER_FRAGMENT)
1239 info->io.fragDepth = i;
1240 else
1241 if (clipVertexOutput < 0)
1242 clipVertexOutput = i;
1243 break;
1244 case TGSI_SEMANTIC_COLOR:
1245 if (info->type == PIPE_SHADER_FRAGMENT)
1246 info->prop.fp.numColourResults++;
1247 break;
1248 case TGSI_SEMANTIC_EDGEFLAG:
1249 info->io.edgeFlagOut = i;
1250 break;
1251 case TGSI_SEMANTIC_CLIPVERTEX:
1252 clipVertexOutput = i;
1253 break;
1254 case TGSI_SEMANTIC_CLIPDIST:
1255 info->io.genUserClip = -1;
1256 break;
1257 case TGSI_SEMANTIC_SAMPLEMASK:
1258 info->io.sampleMask = i;
1259 break;
1260 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1261 info->io.viewportId = i;
1262 break;
1263 case TGSI_SEMANTIC_PATCH:
1264 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1265 /* fallthrough */
1266 case TGSI_SEMANTIC_TESSOUTER:
1267 case TGSI_SEMANTIC_TESSINNER:
1268 info->out[i].patch = 1;
1269 break;
1270 default:
1271 break;
1272 }
1273 info->out[i].id = i;
1274 info->out[i].sn = sn;
1275 info->out[i].si = si;
1276 }
1277 break;
1278 case TGSI_FILE_SYSTEM_VALUE:
1279 switch (sn) {
1280 case TGSI_SEMANTIC_INSTANCEID:
1281 info->io.instanceId = first;
1282 break;
1283 case TGSI_SEMANTIC_VERTEXID:
1284 info->io.vertexId = first;
1285 break;
1286 case TGSI_SEMANTIC_BASEVERTEX:
1287 case TGSI_SEMANTIC_BASEINSTANCE:
1288 case TGSI_SEMANTIC_DRAWID:
1289 info->prop.vp.usesDrawParameters = true;
1290 break;
1291 case TGSI_SEMANTIC_SAMPLEID:
1292 case TGSI_SEMANTIC_SAMPLEPOS:
1293 info->prop.fp.persampleInvocation = true;
1294 break;
1295 case TGSI_SEMANTIC_SAMPLEMASK:
1296 info->prop.fp.usesSampleMaskIn = true;
1297 break;
1298 default:
1299 break;
1300 }
1301 for (i = first; i <= last; ++i, ++si) {
1302 info->sv[i].sn = sn;
1303 info->sv[i].si = si;
1304 info->sv[i].input = inferSysValDirection(sn);
1305
1306 switch (sn) {
1307 case TGSI_SEMANTIC_TESSOUTER:
1308 case TGSI_SEMANTIC_TESSINNER:
1309 info->sv[i].patch = 1;
1310 break;
1311 }
1312 }
1313 break;
1314 /*
1315 case TGSI_FILE_RESOURCE:
1316 for (i = first; i <= last; ++i) {
1317 resources[i].target = decl->Resource.Resource;
1318 resources[i].raw = decl->Resource.Raw;
1319 resources[i].slot = i;
1320 }
1321 break;
1322 */
1323 case TGSI_FILE_IMAGE:
1324 for (i = first; i <= last; ++i) {
1325 images[i].target = decl->Image.Resource;
1326 images[i].raw = decl->Image.Raw;
1327 images[i].format = decl->Image.Format;
1328 images[i].slot = i;
1329 }
1330 break;
1331 case TGSI_FILE_SAMPLER_VIEW:
1332 for (i = first; i <= last; ++i)
1333 textureViews[i].target = decl->SamplerView.Resource;
1334 break;
1335 case TGSI_FILE_MEMORY:
1336 for (i = first; i <= last; ++i)
1337 memoryFiles[i].mem_type = decl->Declaration.MemType;
1338 break;
1339 case TGSI_FILE_NULL:
1340 case TGSI_FILE_TEMPORARY:
1341 for (i = first; i <= last; ++i)
1342 tempArrayId[i] = arrayId;
1343 if (arrayId)
1344 tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
1345 first, last - first + 1)));
1346 break;
1347 case TGSI_FILE_ADDRESS:
1348 case TGSI_FILE_CONSTANT:
1349 case TGSI_FILE_IMMEDIATE:
1350 case TGSI_FILE_PREDICATE:
1351 case TGSI_FILE_SAMPLER:
1352 case TGSI_FILE_BUFFER:
1353 break;
1354 default:
1355 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1356 return false;
1357 }
1358 return true;
1359 }
1360
1361 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1362 {
1363 return insn.getOpcode() == TGSI_OPCODE_MOV &&
1364 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1365 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1366 }
1367
1368 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1369 {
1370 Instruction insn(inst);
1371
1372 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1373 info->numBarriers = 1;
1374
1375 if (insn.dstCount()) {
1376 Instruction::DstRegister dst = insn.getDst(0);
1377
1378 if (dst.getFile() == TGSI_FILE_OUTPUT) {
1379 if (dst.isIndirect(0))
1380 for (unsigned i = 0; i < info->numOutputs; ++i)
1381 info->out[i].mask = 0xf;
1382 else
1383 info->out[dst.getIndex(0)].mask |= dst.getMask();
1384
1385 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1386 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1387 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1388 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1389 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1390 info->out[dst.getIndex(0)].mask &= 1;
1391
1392 if (isEdgeFlagPassthrough(insn))
1393 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1394 } else
1395 if (dst.getFile() == TGSI_FILE_TEMPORARY) {
1396 if (dst.isIndirect(0))
1397 indirectTempArrays.insert(dst.getArrayId());
1398 } else
1399 if (dst.getFile() == TGSI_FILE_BUFFER ||
1400 dst.getFile() == TGSI_FILE_IMAGE ||
1401 (dst.getFile() == TGSI_FILE_MEMORY &&
1402 memoryFiles[dst.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1403 info->io.globalAccess |= 0x2;
1404 }
1405 }
1406
1407 for (unsigned s = 0; s < insn.srcCount(); ++s) {
1408 Instruction::SrcRegister src = insn.getSrc(s);
1409 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1410 if (src.isIndirect(0))
1411 indirectTempArrays.insert(src.getArrayId());
1412 } else
1413 if (src.getFile() == TGSI_FILE_BUFFER ||
1414 src.getFile() == TGSI_FILE_IMAGE ||
1415 (src.getFile() == TGSI_FILE_MEMORY &&
1416 memoryFiles[src.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1417 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1418 0x1 : 0x2;
1419 } else
1420 if (src.getFile() == TGSI_FILE_OUTPUT) {
1421 if (src.isIndirect(0)) {
1422 // We don't know which one is accessed, just mark everything for
1423 // reading. This is an extremely unlikely occurrence.
1424 for (unsigned i = 0; i < info->numOutputs; ++i)
1425 info->out[i].oread = 1;
1426 } else {
1427 info->out[src.getIndex(0)].oread = 1;
1428 }
1429 }
1430 if (src.getFile() != TGSI_FILE_INPUT)
1431 continue;
1432 unsigned mask = insn.srcMask(s);
1433
1434 if (src.isIndirect(0)) {
1435 for (unsigned i = 0; i < info->numInputs; ++i)
1436 info->in[i].mask = 0xf;
1437 } else {
1438 const int i = src.getIndex(0);
1439 for (unsigned c = 0; c < 4; ++c) {
1440 if (!(mask & (1 << c)))
1441 continue;
1442 int k = src.getSwizzle(c);
1443 if (k <= TGSI_SWIZZLE_W)
1444 info->in[i].mask |= 1 << k;
1445 }
1446 switch (info->in[i].sn) {
1447 case TGSI_SEMANTIC_PSIZE:
1448 case TGSI_SEMANTIC_PRIMID:
1449 case TGSI_SEMANTIC_FOG:
1450 info->in[i].mask &= 0x1;
1451 break;
1452 case TGSI_SEMANTIC_PCOORD:
1453 info->in[i].mask &= 0x3;
1454 break;
1455 default:
1456 break;
1457 }
1458 }
1459 }
1460 return true;
1461 }
1462
1463 nv50_ir::TexInstruction::Target
1464 Instruction::getTexture(const tgsi::Source *code, int s) const
1465 {
1466 // XXX: indirect access
1467 unsigned int r;
1468
1469 switch (getSrc(s).getFile()) {
1470 /*
1471 case TGSI_FILE_RESOURCE:
1472 r = getSrc(s).getIndex(0);
1473 return translateTexture(code->resources.at(r).target);
1474 */
1475 case TGSI_FILE_SAMPLER_VIEW:
1476 r = getSrc(s).getIndex(0);
1477 return translateTexture(code->textureViews.at(r).target);
1478 default:
1479 return translateTexture(insn->Texture.Texture);
1480 }
1481 }
1482
1483 } // namespace tgsi
1484
1485 namespace {
1486
1487 using namespace nv50_ir;
1488
1489 class Converter : public BuildUtil
1490 {
1491 public:
1492 Converter(Program *, const tgsi::Source *);
1493 ~Converter();
1494
1495 bool run();
1496
1497 private:
1498 struct Subroutine
1499 {
1500 Subroutine(Function *f) : f(f) { }
1501 Function *f;
1502 ValueMap values;
1503 };
1504
1505 Value *shiftAddress(Value *);
1506 Value *getVertexBase(int s);
1507 Value *getOutputBase(int s);
1508 DataArray *getArrayForFile(unsigned file, int idx);
1509 Value *fetchSrc(int s, int c);
1510 Value *acquireDst(int d, int c);
1511 void storeDst(int d, int c, Value *);
1512
1513 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1514 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1515 Value *val, Value *ptr);
1516
1517 void adjustTempIndex(int arrayId, int &idx, int &idx2d) const;
1518 Value *applySrcMod(Value *, int s, int c);
1519
1520 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1521 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1522 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1523
1524 bool handleInstruction(const struct tgsi_full_instruction *);
1525 void exportOutputs();
1526 inline Subroutine *getSubroutine(unsigned ip);
1527 inline Subroutine *getSubroutine(Function *);
1528 inline bool isEndOfSubroutine(uint ip);
1529
1530 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1531
1532 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1533 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1534 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1535 void handleTXF(Value *dst0[4], int R, int L_M);
1536 void handleTXQ(Value *dst0[4], enum TexQuery, int R);
1537 void handleLIT(Value *dst0[4]);
1538 void handleUserClipPlanes();
1539
1540 // Symbol *getResourceBase(int r);
1541 void getImageCoords(std::vector<Value *>&, int r, int s);
1542
1543 void handleLOAD(Value *dst0[4]);
1544 void handleSTORE();
1545 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1546
1547 void handleINTERP(Value *dst0[4]);
1548
1549 uint8_t translateInterpMode(const struct nv50_ir_varying *var,
1550 operation& op);
1551 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1552
1553 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1554
1555 Value *buildDot(int dim);
1556
1557 class BindArgumentsPass : public Pass {
1558 public:
1559 BindArgumentsPass(Converter &conv) : conv(conv) { }
1560
1561 private:
1562 Converter &conv;
1563 Subroutine *sub;
1564
1565 inline const Location *getValueLocation(Subroutine *, Value *);
1566
1567 template<typename T> inline void
1568 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1569 T (Function::*proto));
1570
1571 template<typename T> inline void
1572 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1573 T (Function::*proto));
1574
1575 protected:
1576 bool visit(Function *);
1577 bool visit(BasicBlock *bb) { return false; }
1578 };
1579
1580 private:
1581 const tgsi::Source *code;
1582 const struct nv50_ir_prog_info *info;
1583
1584 struct {
1585 std::map<unsigned, Subroutine> map;
1586 Subroutine *cur;
1587 } sub;
1588
1589 uint ip; // instruction pointer
1590
1591 tgsi::Instruction tgsi;
1592
1593 DataType dstTy;
1594 DataType srcTy;
1595
1596 DataArray tData; // TGSI_FILE_TEMPORARY
1597 DataArray lData; // TGSI_FILE_TEMPORARY, for indirect arrays
1598 DataArray aData; // TGSI_FILE_ADDRESS
1599 DataArray pData; // TGSI_FILE_PREDICATE
1600 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1601
1602 Value *zero;
1603 Value *fragCoord[4];
1604 Value *clipVtx[4];
1605
1606 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1607 uint8_t vtxBaseValid;
1608
1609 Value *outBase; // base address of vertex out patch (for TCP)
1610
1611 Stack condBBs; // fork BB, then else clause BB
1612 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1613 Stack loopBBs; // loop headers
1614 Stack breakBBs; // end of / after loop
1615
1616 Value *viewport;
1617 };
1618
1619 Symbol *
1620 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1621 {
1622 const int swz = src.getSwizzle(c);
1623
1624 /* TODO: Use Array ID when it's available for the index */
1625 return makeSym(src.getFile(),
1626 src.is2D() ? src.getIndex(1) : 0,
1627 src.getIndex(0), swz,
1628 src.getIndex(0) * 16 + swz * 4);
1629 }
1630
1631 Symbol *
1632 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1633 {
1634 /* TODO: Use Array ID when it's available for the index */
1635 return makeSym(dst.getFile(),
1636 dst.is2D() ? dst.getIndex(1) : 0,
1637 dst.getIndex(0), c,
1638 dst.getIndex(0) * 16 + c * 4);
1639 }
1640
1641 Symbol *
1642 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1643 {
1644 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1645
1646 sym->reg.fileIndex = fileIdx;
1647
1648 if (tgsiFile == TGSI_FILE_MEMORY) {
1649 switch (code->memoryFiles[fileIdx].mem_type) {
1650 case TGSI_MEMORY_TYPE_GLOBAL:
1651 /* No-op this is the default for TGSI_FILE_MEMORY */
1652 sym->setFile(FILE_MEMORY_GLOBAL);
1653 break;
1654 case TGSI_MEMORY_TYPE_SHARED:
1655 sym->setFile(FILE_MEMORY_SHARED);
1656 break;
1657 case TGSI_MEMORY_TYPE_INPUT:
1658 assert(prog->getType() == Program::TYPE_COMPUTE);
1659 assert(idx == -1);
1660 sym->setFile(FILE_SHADER_INPUT);
1661 address += info->prop.cp.inputOffset;
1662 break;
1663 default:
1664 assert(0); /* TODO: Add support for global and private memory */
1665 }
1666 }
1667
1668 if (idx >= 0) {
1669 if (sym->reg.file == FILE_SHADER_INPUT)
1670 sym->setOffset(info->in[idx].slot[c] * 4);
1671 else
1672 if (sym->reg.file == FILE_SHADER_OUTPUT)
1673 sym->setOffset(info->out[idx].slot[c] * 4);
1674 else
1675 if (sym->reg.file == FILE_SYSTEM_VALUE)
1676 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1677 else
1678 sym->setOffset(address);
1679 } else {
1680 sym->setOffset(address);
1681 }
1682 return sym;
1683 }
1684
1685 uint8_t
1686 Converter::translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1687 {
1688 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1689
1690 if (var->flat)
1691 mode = NV50_IR_INTERP_FLAT;
1692 else
1693 if (var->linear)
1694 mode = NV50_IR_INTERP_LINEAR;
1695 else
1696 if (var->sc)
1697 mode = NV50_IR_INTERP_SC;
1698
1699 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1700 ? OP_PINTERP : OP_LINTERP;
1701
1702 if (var->centroid)
1703 mode |= NV50_IR_INTERP_CENTROID;
1704
1705 return mode;
1706 }
1707
1708 Value *
1709 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1710 {
1711 operation op;
1712
1713 // XXX: no way to know interpolation mode if we don't know what's accessed
1714 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1715 src.getIndex(0)], op);
1716
1717 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1718
1719 insn->setDef(0, getScratch());
1720 insn->setSrc(0, srcToSym(src, c));
1721 if (op == OP_PINTERP)
1722 insn->setSrc(1, fragCoord[3]);
1723 if (ptr)
1724 insn->setIndirect(0, 0, ptr);
1725
1726 insn->setInterpolate(mode);
1727
1728 bb->insertTail(insn);
1729 return insn->getDef(0);
1730 }
1731
1732 Value *
1733 Converter::applySrcMod(Value *val, int s, int c)
1734 {
1735 Modifier m = tgsi.getSrc(s).getMod(c);
1736 DataType ty = tgsi.inferSrcType();
1737
1738 if (m & Modifier(NV50_IR_MOD_ABS))
1739 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1740
1741 if (m & Modifier(NV50_IR_MOD_NEG))
1742 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1743
1744 return val;
1745 }
1746
1747 Value *
1748 Converter::getVertexBase(int s)
1749 {
1750 assert(s < 5);
1751 if (!(vtxBaseValid & (1 << s))) {
1752 const int index = tgsi.getSrc(s).getIndex(1);
1753 Value *rel = NULL;
1754 if (tgsi.getSrc(s).isIndirect(1))
1755 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1756 vtxBaseValid |= 1 << s;
1757 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1758 mkImm(index), rel);
1759 }
1760 return vtxBase[s];
1761 }
1762
1763 Value *
1764 Converter::getOutputBase(int s)
1765 {
1766 assert(s < 5);
1767 if (!(vtxBaseValid & (1 << s))) {
1768 Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1));
1769 if (tgsi.getSrc(s).isIndirect(1))
1770 offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(),
1771 fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL),
1772 offset);
1773 vtxBaseValid |= 1 << s;
1774 vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset);
1775 }
1776 return vtxBase[s];
1777 }
1778
1779 Value *
1780 Converter::fetchSrc(int s, int c)
1781 {
1782 Value *res;
1783 Value *ptr = NULL, *dimRel = NULL;
1784
1785 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1786
1787 if (src.isIndirect(0))
1788 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1789
1790 if (src.is2D()) {
1791 switch (src.getFile()) {
1792 case TGSI_FILE_OUTPUT:
1793 dimRel = getOutputBase(s);
1794 break;
1795 case TGSI_FILE_INPUT:
1796 dimRel = getVertexBase(s);
1797 break;
1798 case TGSI_FILE_CONSTANT:
1799 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1800 if (src.isIndirect(1))
1801 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1802 break;
1803 default:
1804 break;
1805 }
1806 }
1807
1808 res = fetchSrc(src, c, ptr);
1809
1810 if (dimRel)
1811 res->getInsn()->setIndirect(0, 1, dimRel);
1812
1813 return applySrcMod(res, s, c);
1814 }
1815
1816 Converter::DataArray *
1817 Converter::getArrayForFile(unsigned file, int idx)
1818 {
1819 switch (file) {
1820 case TGSI_FILE_TEMPORARY:
1821 return idx == 0 ? &tData : &lData;
1822 case TGSI_FILE_PREDICATE:
1823 return &pData;
1824 case TGSI_FILE_ADDRESS:
1825 return &aData;
1826 case TGSI_FILE_OUTPUT:
1827 assert(prog->getType() == Program::TYPE_FRAGMENT);
1828 return &oData;
1829 default:
1830 assert(!"invalid/unhandled TGSI source file");
1831 return NULL;
1832 }
1833 }
1834
1835 Value *
1836 Converter::shiftAddress(Value *index)
1837 {
1838 if (!index)
1839 return NULL;
1840 return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1841 }
1842
1843 void
1844 Converter::adjustTempIndex(int arrayId, int &idx, int &idx2d) const
1845 {
1846 std::map<int, int>::const_iterator it =
1847 code->indirectTempOffsets.find(arrayId);
1848 if (it == code->indirectTempOffsets.end())
1849 return;
1850
1851 idx2d = 1;
1852 idx += it->second;
1853 }
1854
1855 Value *
1856 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1857 {
1858 int idx2d = src.is2D() ? src.getIndex(1) : 0;
1859 int idx = src.getIndex(0);
1860 const int swz = src.getSwizzle(c);
1861 Instruction *ld;
1862
1863 switch (src.getFile()) {
1864 case TGSI_FILE_IMMEDIATE:
1865 assert(!ptr);
1866 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1867 case TGSI_FILE_CONSTANT:
1868 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1869 case TGSI_FILE_INPUT:
1870 if (prog->getType() == Program::TYPE_FRAGMENT) {
1871 // don't load masked inputs, won't be assigned a slot
1872 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1873 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1874 return interpolate(src, c, shiftAddress(ptr));
1875 } else
1876 if (prog->getType() == Program::TYPE_GEOMETRY) {
1877 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1878 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1879 // XXX: This is going to be a problem with scalar arrays, i.e. when
1880 // we cannot assume that the address is given in units of vec4.
1881 //
1882 // nv50 and nvc0 need different things here, so let the lowering
1883 // passes decide what to do with the address
1884 if (ptr)
1885 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1886 }
1887 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1888 ld->perPatch = info->in[idx].patch;
1889 return ld->getDef(0);
1890 case TGSI_FILE_OUTPUT:
1891 assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
1892 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1893 ld->perPatch = info->out[idx].patch;
1894 return ld->getDef(0);
1895 case TGSI_FILE_SYSTEM_VALUE:
1896 assert(!ptr);
1897 ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1898 ld->perPatch = info->sv[idx].patch;
1899 return ld->getDef(0);
1900 case TGSI_FILE_TEMPORARY: {
1901 int arrayid = src.getArrayId();
1902 if (!arrayid)
1903 arrayid = code->tempArrayId[idx];
1904 adjustTempIndex(arrayid, idx, idx2d);
1905 }
1906 /* fallthrough */
1907 default:
1908 return getArrayForFile(src.getFile(), idx2d)->load(
1909 sub.cur->values, idx, swz, shiftAddress(ptr));
1910 }
1911 }
1912
1913 Value *
1914 Converter::acquireDst(int d, int c)
1915 {
1916 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1917 const unsigned f = dst.getFile();
1918 int idx = dst.getIndex(0);
1919 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1920
1921 if (dst.isMasked(c) || f == TGSI_FILE_BUFFER || f == TGSI_FILE_MEMORY ||
1922 f == TGSI_FILE_IMAGE)
1923 return NULL;
1924
1925 if (dst.isIndirect(0) ||
1926 f == TGSI_FILE_SYSTEM_VALUE ||
1927 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1928 return getScratch();
1929
1930 if (f == TGSI_FILE_TEMPORARY) {
1931 int arrayid = dst.getArrayId();
1932 if (!arrayid)
1933 arrayid = code->tempArrayId[idx];
1934 adjustTempIndex(arrayid, idx, idx2d);
1935 }
1936
1937 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1938 }
1939
1940 void
1941 Converter::storeDst(int d, int c, Value *val)
1942 {
1943 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1944
1945 if (tgsi.getSaturate()) {
1946 mkOp1(OP_SAT, dstTy, val, val);
1947 }
1948
1949 Value *ptr = NULL;
1950 if (dst.isIndirect(0))
1951 ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1952
1953 if (info->io.genUserClip > 0 &&
1954 dst.getFile() == TGSI_FILE_OUTPUT &&
1955 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1956 mkMov(clipVtx[c], val);
1957 val = clipVtx[c];
1958 }
1959
1960 storeDst(dst, c, val, ptr);
1961 }
1962
1963 void
1964 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1965 Value *val, Value *ptr)
1966 {
1967 const unsigned f = dst.getFile();
1968 int idx = dst.getIndex(0);
1969 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1970
1971 if (f == TGSI_FILE_SYSTEM_VALUE) {
1972 assert(!ptr);
1973 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1974 } else
1975 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1976
1977 if (ptr || (info->out[idx].mask & (1 << c))) {
1978 /* Save the viewport index into a scratch register so that it can be
1979 exported at EMIT time */
1980 if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
1981 viewport != NULL)
1982 mkOp1(OP_MOV, TYPE_U32, viewport, val);
1983 else
1984 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
1985 info->out[idx].patch;
1986 }
1987 } else
1988 if (f == TGSI_FILE_TEMPORARY ||
1989 f == TGSI_FILE_PREDICATE ||
1990 f == TGSI_FILE_ADDRESS ||
1991 f == TGSI_FILE_OUTPUT) {
1992 if (f == TGSI_FILE_TEMPORARY) {
1993 int arrayid = dst.getArrayId();
1994 if (!arrayid)
1995 arrayid = code->tempArrayId[idx];
1996 adjustTempIndex(arrayid, idx, idx2d);
1997 }
1998
1999 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
2000 } else {
2001 assert(!"invalid dst file");
2002 }
2003 }
2004
2005 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
2006 for (chan = 0; chan < 4; ++chan) \
2007 if (!inst.getDst(d).isMasked(chan))
2008
2009 Value *
2010 Converter::buildDot(int dim)
2011 {
2012 assert(dim > 0);
2013
2014 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
2015 Value *dotp = getScratch();
2016
2017 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
2018
2019 for (int c = 1; c < dim; ++c) {
2020 src0 = fetchSrc(0, c);
2021 src1 = fetchSrc(1, c);
2022 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
2023 }
2024 return dotp;
2025 }
2026
2027 void
2028 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
2029 {
2030 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
2031 join->fixed = 1;
2032 conv->insertHead(join);
2033
2034 assert(!fork->joinAt);
2035 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
2036 fork->insertBefore(fork->getExit(), fork->joinAt);
2037 }
2038
2039 void
2040 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
2041 {
2042 unsigned rIdx = 0, sIdx = 0;
2043
2044 if (R >= 0)
2045 rIdx = tgsi.getSrc(R).getIndex(0);
2046 if (S >= 0)
2047 sIdx = tgsi.getSrc(S).getIndex(0);
2048
2049 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
2050
2051 if (tgsi.getSrc(R).isIndirect(0)) {
2052 tex->tex.rIndirectSrc = s;
2053 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
2054 }
2055 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
2056 tex->tex.sIndirectSrc = s;
2057 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
2058 }
2059 }
2060
2061 void
2062 Converter::handleTXQ(Value *dst0[4], enum TexQuery query, int R)
2063 {
2064 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
2065 tex->tex.query = query;
2066 unsigned int c, d;
2067
2068 for (d = 0, c = 0; c < 4; ++c) {
2069 if (!dst0[c])
2070 continue;
2071 tex->tex.mask |= 1 << c;
2072 tex->setDef(d++, dst0[c]);
2073 }
2074 if (query == TXQ_DIMS)
2075 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
2076 else
2077 tex->setSrc((c = 0), zero);
2078
2079 setTexRS(tex, ++c, R, -1);
2080
2081 bb->insertTail(tex);
2082 }
2083
2084 void
2085 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
2086 {
2087 Value *proj = fetchSrc(0, 3);
2088 Instruction *insn = proj->getUniqueInsn();
2089 int c;
2090
2091 if (insn->op == OP_PINTERP) {
2092 bb->insertTail(insn = cloneForward(func, insn));
2093 insn->op = OP_LINTERP;
2094 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
2095 insn->setSrc(1, NULL);
2096 proj = insn->getDef(0);
2097 }
2098 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
2099
2100 for (c = 0; c < 4; ++c) {
2101 if (!(mask & (1 << c)))
2102 continue;
2103 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
2104 continue;
2105 mask &= ~(1 << c);
2106
2107 bb->insertTail(insn = cloneForward(func, insn));
2108 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
2109 insn->setSrc(1, proj);
2110 dst[c] = insn->getDef(0);
2111 }
2112 if (!mask)
2113 return;
2114
2115 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
2116
2117 for (c = 0; c < 4; ++c)
2118 if (mask & (1 << c))
2119 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
2120 }
2121
2122 // order of nv50 ir sources: x y z layer lod/bias shadow
2123 // order of TGSI TEX sources: x y z layer shadow lod/bias
2124 // lowering will finally set the hw specific order (like array first on nvc0)
2125 void
2126 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
2127 {
2128 Value *arg[4], *src[8];
2129 Value *lod = NULL, *shd = NULL;
2130 unsigned int s, c, d;
2131 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2132
2133 TexInstruction::Target tgt = tgsi.getTexture(code, R);
2134
2135 for (s = 0; s < tgt.getArgCount(); ++s)
2136 arg[s] = src[s] = fetchSrc(0, s);
2137
2138 if (texi->op == OP_TXL || texi->op == OP_TXB)
2139 lod = fetchSrc(L >> 4, L & 3);
2140
2141 if (C == 0x0f)
2142 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
2143
2144 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
2145 tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
2146 shd = fetchSrc(1, 0);
2147 else if (tgt.isShadow())
2148 shd = fetchSrc(C >> 4, C & 3);
2149
2150 if (texi->op == OP_TXD) {
2151 for (c = 0; c < tgt.getDim() + tgt.isCube(); ++c) {
2152 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
2153 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
2154 }
2155 }
2156
2157 // cube textures don't care about projection value, it's divided out
2158 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
2159 unsigned int n = tgt.getDim();
2160 if (shd) {
2161 arg[n] = shd;
2162 ++n;
2163 assert(tgt.getDim() == tgt.getArgCount());
2164 }
2165 loadProjTexCoords(src, arg, (1 << n) - 1);
2166 if (shd)
2167 shd = src[n - 1];
2168 }
2169
2170 for (c = 0, d = 0; c < 4; ++c) {
2171 if (dst[c]) {
2172 texi->setDef(d++, dst[c]);
2173 texi->tex.mask |= 1 << c;
2174 } else {
2175 // NOTE: maybe hook up def too, for CSE
2176 }
2177 }
2178 for (s = 0; s < tgt.getArgCount(); ++s)
2179 texi->setSrc(s, src[s]);
2180 if (lod)
2181 texi->setSrc(s++, lod);
2182 if (shd)
2183 texi->setSrc(s++, shd);
2184
2185 setTexRS(texi, s, R, S);
2186
2187 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
2188 texi->tex.levelZero = true;
2189 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
2190 texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
2191
2192 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2193 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2194 for (c = 0; c < 3; ++c) {
2195 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2196 texi->offset[s][c].setInsn(texi);
2197 }
2198 }
2199
2200 bb->insertTail(texi);
2201 }
2202
2203 // 1st source: xyz = coordinates, w = lod/sample
2204 // 2nd source: offset
2205 void
2206 Converter::handleTXF(Value *dst[4], int R, int L_M)
2207 {
2208 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2209 int ms;
2210 unsigned int c, d, s;
2211
2212 texi->tex.target = tgsi.getTexture(code, R);
2213
2214 ms = texi->tex.target.isMS() ? 1 : 0;
2215 texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
2216
2217 for (c = 0, d = 0; c < 4; ++c) {
2218 if (dst[c]) {
2219 texi->setDef(d++, dst[c]);
2220 texi->tex.mask |= 1 << c;
2221 }
2222 }
2223 for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
2224 texi->setSrc(c, fetchSrc(0, c));
2225 texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
2226
2227 setTexRS(texi, c, R, -1);
2228
2229 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2230 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2231 for (c = 0; c < 3; ++c) {
2232 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2233 texi->offset[s][c].setInsn(texi);
2234 }
2235 }
2236
2237 bb->insertTail(texi);
2238 }
2239
2240 void
2241 Converter::handleLIT(Value *dst0[4])
2242 {
2243 Value *val0 = NULL;
2244 unsigned int mask = tgsi.getDst(0).getMask();
2245
2246 if (mask & (1 << 0))
2247 loadImm(dst0[0], 1.0f);
2248
2249 if (mask & (1 << 3))
2250 loadImm(dst0[3], 1.0f);
2251
2252 if (mask & (3 << 1)) {
2253 val0 = getScratch();
2254 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
2255 if (mask & (1 << 1))
2256 mkMov(dst0[1], val0);
2257 }
2258
2259 if (mask & (1 << 2)) {
2260 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
2261 Value *val1 = getScratch(), *val3 = getScratch();
2262
2263 Value *pos128 = loadImm(NULL, +127.999999f);
2264 Value *neg128 = loadImm(NULL, -127.999999f);
2265
2266 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
2267 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
2268 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
2269 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
2270
2271 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
2272 }
2273 }
2274
2275 /* Keep this around for now as reference when adding img support
2276 static inline bool
2277 isResourceSpecial(const int r)
2278 {
2279 return (r == TGSI_RESOURCE_GLOBAL ||
2280 r == TGSI_RESOURCE_LOCAL ||
2281 r == TGSI_RESOURCE_PRIVATE ||
2282 r == TGSI_RESOURCE_INPUT);
2283 }
2284
2285 static inline bool
2286 isResourceRaw(const tgsi::Source *code, const int r)
2287 {
2288 return isResourceSpecial(r) || code->resources[r].raw;
2289 }
2290
2291 static inline nv50_ir::TexTarget
2292 getResourceTarget(const tgsi::Source *code, int r)
2293 {
2294 if (isResourceSpecial(r))
2295 return nv50_ir::TEX_TARGET_BUFFER;
2296 return tgsi::translateTexture(code->resources.at(r).target);
2297 }
2298
2299 Symbol *
2300 Converter::getResourceBase(const int r)
2301 {
2302 Symbol *sym = NULL;
2303
2304 switch (r) {
2305 case TGSI_RESOURCE_GLOBAL:
2306 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL,
2307 info->io.auxCBSlot);
2308 break;
2309 case TGSI_RESOURCE_LOCAL:
2310 assert(prog->getType() == Program::TYPE_COMPUTE);
2311 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2312 info->prop.cp.sharedOffset);
2313 break;
2314 case TGSI_RESOURCE_PRIVATE:
2315 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2316 info->bin.tlsSpace);
2317 break;
2318 case TGSI_RESOURCE_INPUT:
2319 assert(prog->getType() == Program::TYPE_COMPUTE);
2320 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2321 info->prop.cp.inputOffset);
2322 break;
2323 default:
2324 sym = new_Symbol(prog,
2325 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2326 break;
2327 }
2328 return sym;
2329 }
2330
2331 void
2332 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2333 {
2334 const int arg =
2335 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2336
2337 for (int c = 0; c < arg; ++c)
2338 coords.push_back(fetchSrc(s, c));
2339
2340 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2341 if (r == TGSI_RESOURCE_LOCAL ||
2342 r == TGSI_RESOURCE_PRIVATE ||
2343 r == TGSI_RESOURCE_INPUT)
2344 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2345 coords[0]);
2346 }
2347 */
2348 static inline int
2349 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2350 {
2351 int n = 0;
2352
2353 while (mask) {
2354 if (mask & 1) {
2355 size[n]++;
2356 } else {
2357 if (size[n])
2358 comp[n = 1] = size[0] + 1;
2359 else
2360 comp[n]++;
2361 }
2362 mask >>= 1;
2363 }
2364 if (size[0] == 3) {
2365 n = 1;
2366 size[0] = (comp[0] == 1) ? 1 : 2;
2367 size[1] = 3 - size[0];
2368 comp[1] = comp[0] + size[0];
2369 }
2370 return n + 1;
2371 }
2372
2373 static inline nv50_ir::TexTarget
2374 getImageTarget(const tgsi::Source *code, int r)
2375 {
2376 return tgsi::translateTexture(code->images.at(r).target);
2377 }
2378
2379 static inline const nv50_ir::TexInstruction::ImgFormatDesc *
2380 getImageFormat(const tgsi::Source *code, int r)
2381 {
2382 return &nv50_ir::TexInstruction::formatTable[
2383 tgsi::translateImgFormat(code->images.at(r).format)];
2384 }
2385
2386 void
2387 Converter::getImageCoords(std::vector<Value *> &coords, int r, int s)
2388 {
2389 TexInstruction::Target t =
2390 TexInstruction::Target(getImageTarget(code, r));
2391 const int arg = t.getDim() + (t.isArray() || t.isCube());
2392
2393 for (int c = 0; c < arg; ++c)
2394 coords.push_back(fetchSrc(s, c));
2395
2396 if (t.isMS())
2397 coords.push_back(fetchSrc(s, 3));
2398 }
2399
2400 // For raw loads, granularity is 4 byte.
2401 // Usage of the texture read mask on OP_SULDP is not allowed.
2402 void
2403 Converter::handleLOAD(Value *dst0[4])
2404 {
2405 const int r = tgsi.getSrc(0).getIndex(0);
2406 int c;
2407 std::vector<Value *> off, src, ldv, def;
2408
2409 switch (tgsi.getSrc(0).getFile()) {
2410 case TGSI_FILE_BUFFER:
2411 case TGSI_FILE_MEMORY:
2412 for (c = 0; c < 4; ++c) {
2413 if (!dst0[c])
2414 continue;
2415
2416 Value *off;
2417 Symbol *sym;
2418 uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
2419
2420 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
2421 off = NULL;
2422 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2423 tgsi.getSrc(1).getValueU32(0, info) +
2424 src0_component_offset);
2425 } else {
2426 // yzw are ignored for buffers
2427 off = fetchSrc(1, 0);
2428 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2429 src0_component_offset);
2430 }
2431
2432 Instruction *ld = mkLoad(TYPE_U32, dst0[c], sym, off);
2433 ld->cache = tgsi.getCacheMode();
2434 if (tgsi.getSrc(0).isIndirect(0))
2435 ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
2436 }
2437 break;
2438 case TGSI_FILE_IMAGE: {
2439 assert(!code->images[r].raw);
2440
2441 getImageCoords(off, r, 1);
2442 def.resize(4);
2443
2444 for (c = 0; c < 4; ++c) {
2445 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2446 def[c] = getScratch();
2447 else
2448 def[c] = dst0[c];
2449 }
2450
2451 TexInstruction *ld =
2452 mkTex(OP_SULDP, getImageTarget(code, r), code->images[r].slot, 0,
2453 def, off);
2454 ld->tex.mask = tgsi.getDst(0).getMask();
2455 ld->tex.format = getImageFormat(code, r);
2456 ld->cache = tgsi.getCacheMode();
2457 if (tgsi.getSrc(0).isIndirect(0))
2458 ld->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2459
2460 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2461 if (dst0[c] != def[c])
2462 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2463 }
2464 break;
2465 default:
2466 assert(!"Unsupported srcFile for LOAD");
2467 }
2468
2469 /* Keep this around for now as reference when adding img support
2470 getResourceCoords(off, r, 1);
2471
2472 if (isResourceRaw(code, r)) {
2473 uint8_t mask = 0;
2474 uint8_t comp[2] = { 0, 0 };
2475 uint8_t size[2] = { 0, 0 };
2476
2477 Symbol *base = getResourceBase(r);
2478
2479 // determine the base and size of the at most 2 load ops
2480 for (c = 0; c < 4; ++c)
2481 if (!tgsi.getDst(0).isMasked(c))
2482 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2483
2484 int n = partitionLoadStore(comp, size, mask);
2485
2486 src = off;
2487
2488 def.resize(4); // index by component, the ones we need will be non-NULL
2489 for (c = 0; c < 4; ++c) {
2490 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2491 def[c] = dst0[c];
2492 else
2493 if (mask & (1 << c))
2494 def[c] = getScratch();
2495 }
2496
2497 const bool useLd = isResourceSpecial(r) ||
2498 (info->io.nv50styleSurfaces &&
2499 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2500
2501 for (int i = 0; i < n; ++i) {
2502 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2503
2504 if (comp[i]) // adjust x component of source address if necessary
2505 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2506 off[0], mkImm(comp[i] * 4));
2507 else
2508 src[0] = off[0];
2509
2510 if (useLd) {
2511 Instruction *ld =
2512 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2513 for (size_t c = 1; c < ldv.size(); ++c)
2514 ld->setDef(c, ldv[c]);
2515 } else {
2516 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2517 0, ldv, src)->dType = typeOfSize(size[i] * 4);
2518 }
2519 }
2520 } else {
2521 def.resize(4);
2522 for (c = 0; c < 4; ++c) {
2523 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2524 def[c] = getScratch();
2525 else
2526 def[c] = dst0[c];
2527 }
2528
2529 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2530 def, off);
2531 }
2532 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2533 if (dst0[c] != def[c])
2534 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2535 */
2536 }
2537
2538 // For formatted stores, the write mask on OP_SUSTP can be used.
2539 // Raw stores have to be split.
2540 void
2541 Converter::handleSTORE()
2542 {
2543 const int r = tgsi.getDst(0).getIndex(0);
2544 int c;
2545 std::vector<Value *> off, src, dummy;
2546
2547 switch (tgsi.getDst(0).getFile()) {
2548 case TGSI_FILE_BUFFER:
2549 case TGSI_FILE_MEMORY:
2550 for (c = 0; c < 4; ++c) {
2551 if (!(tgsi.getDst(0).getMask() & (1 << c)))
2552 continue;
2553
2554 Symbol *sym;
2555 Value *off;
2556 if (tgsi.getSrc(0).getFile() == TGSI_FILE_IMMEDIATE) {
2557 off = NULL;
2558 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c,
2559 tgsi.getSrc(0).getValueU32(0, info) + 4 * c);
2560 } else {
2561 // yzw are ignored for buffers
2562 off = fetchSrc(0, 0);
2563 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c, 4 * c);
2564 }
2565
2566 Instruction *st = mkStore(OP_STORE, TYPE_U32, sym, off, fetchSrc(1, c));
2567 st->cache = tgsi.getCacheMode();
2568 if (tgsi.getDst(0).isIndirect(0))
2569 st->setIndirect(0, 1, fetchSrc(tgsi.getDst(0).getIndirect(0), 0, 0));
2570 }
2571 break;
2572 case TGSI_FILE_IMAGE: {
2573 assert(!code->images[r].raw);
2574
2575 getImageCoords(off, r, 0);
2576 src = off;
2577
2578 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2579 src.push_back(fetchSrc(1, c));
2580
2581 TexInstruction *st =
2582 mkTex(OP_SUSTP, getImageTarget(code, r), code->images[r].slot,
2583 0, dummy, src);
2584 st->tex.mask = tgsi.getDst(0).getMask();
2585 st->tex.format = getImageFormat(code, r);
2586 st->cache = tgsi.getCacheMode();
2587 if (tgsi.getDst(0).isIndirect(0))
2588 st->setIndirectR(fetchSrc(tgsi.getDst(0).getIndirect(0), 0, NULL));
2589 }
2590 break;
2591 default:
2592 assert(!"Unsupported dstFile for STORE");
2593 }
2594
2595 /* Keep this around for now as reference when adding img support
2596 getResourceCoords(off, r, 0);
2597 src = off;
2598 const int s = src.size();
2599
2600 if (isResourceRaw(code, r)) {
2601 uint8_t comp[2] = { 0, 0 };
2602 uint8_t size[2] = { 0, 0 };
2603
2604 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2605
2606 Symbol *base = getResourceBase(r);
2607
2608 const bool useSt = isResourceSpecial(r) ||
2609 (info->io.nv50styleSurfaces &&
2610 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2611
2612 for (int i = 0; i < n; ++i) {
2613 if (comp[i]) // adjust x component of source address if necessary
2614 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2615 off[0], mkImm(comp[i] * 4));
2616 else
2617 src[0] = off[0];
2618
2619 const DataType stTy = typeOfSize(size[i] * 4);
2620
2621 if (useSt) {
2622 Instruction *st =
2623 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2624 for (c = 1; c < size[i]; ++c)
2625 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2626 st->setIndirect(0, 0, src[0]);
2627 } else {
2628 // attach values to be stored
2629 src.resize(s + size[i]);
2630 for (c = 0; c < size[i]; ++c)
2631 src[s + c] = fetchSrc(1, comp[i] + c);
2632 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2633 0, dummy, src)->setType(stTy);
2634 }
2635 }
2636 } else {
2637 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2638 src.push_back(fetchSrc(1, c));
2639
2640 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2641 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2642 }
2643 */
2644 }
2645
2646 // XXX: These only work on resources with the single-component u32/s32 formats.
2647 // Therefore the result is replicated. This might not be intended by TGSI, but
2648 // operating on more than 1 component would produce undefined results because
2649 // they do not exist.
2650 void
2651 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2652 {
2653 const int r = tgsi.getSrc(0).getIndex(0);
2654 std::vector<Value *> srcv;
2655 std::vector<Value *> defv;
2656 LValue *dst = getScratch();
2657
2658 switch (tgsi.getSrc(0).getFile()) {
2659 case TGSI_FILE_BUFFER:
2660 case TGSI_FILE_MEMORY:
2661 for (int c = 0; c < 4; ++c) {
2662 if (!dst0[c])
2663 continue;
2664
2665 Instruction *insn;
2666 Value *off = fetchSrc(1, c), *off2 = NULL;
2667 Value *sym;
2668 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE)
2669 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2670 tgsi.getSrc(1).getValueU32(c, info));
2671 else
2672 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c, 0);
2673 if (tgsi.getSrc(0).isIndirect(0))
2674 off2 = fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0);
2675 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2676 insn = mkOp3(OP_ATOM, ty, dst, sym, fetchSrc(2, c), fetchSrc(3, c));
2677 else
2678 insn = mkOp2(OP_ATOM, ty, dst, sym, fetchSrc(2, c));
2679 if (tgsi.getSrc(1).getFile() != TGSI_FILE_IMMEDIATE)
2680 insn->setIndirect(0, 0, off);
2681 if (off2)
2682 insn->setIndirect(0, 1, off2);
2683 insn->subOp = subOp;
2684 }
2685 for (int c = 0; c < 4; ++c)
2686 if (dst0[c])
2687 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2688 break;
2689 case TGSI_FILE_IMAGE: {
2690 assert(!code->images[r].raw);
2691
2692 getImageCoords(srcv, r, 1);
2693 defv.push_back(dst);
2694 srcv.push_back(fetchSrc(2, 0));
2695
2696 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2697 srcv.push_back(fetchSrc(3, 0));
2698
2699 TexInstruction *tex = mkTex(OP_SUREDP, getImageTarget(code, r),
2700 code->images[r].slot, 0, defv, srcv);
2701 tex->subOp = subOp;
2702 tex->tex.mask = 1;
2703 tex->tex.format = getImageFormat(code, r);
2704 tex->setType(ty);
2705 if (tgsi.getSrc(0).isIndirect(0))
2706 tex->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2707
2708 for (int c = 0; c < 4; ++c)
2709 if (dst0[c])
2710 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2711 }
2712 break;
2713 default:
2714 assert(!"Unsupported srcFile for ATOM");
2715 }
2716
2717 /* Keep this around for now as reference when adding img support
2718 getResourceCoords(srcv, r, 1);
2719
2720 if (isResourceSpecial(r)) {
2721 assert(r != TGSI_RESOURCE_INPUT);
2722 Instruction *insn;
2723 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2724 insn->subOp = subOp;
2725 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2726 insn->setSrc(2, fetchSrc(3, 0));
2727 insn->setIndirect(0, 0, srcv.at(0));
2728 } else {
2729 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2730 TexTarget targ = getResourceTarget(code, r);
2731 int idx = code->resources[r].slot;
2732 defv.push_back(dst);
2733 srcv.push_back(fetchSrc(2, 0));
2734 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2735 srcv.push_back(fetchSrc(3, 0));
2736 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2737 tex->subOp = subOp;
2738 tex->tex.mask = 1;
2739 tex->setType(ty);
2740 }
2741
2742 for (int c = 0; c < 4; ++c)
2743 if (dst0[c])
2744 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2745 */
2746 }
2747
2748 void
2749 Converter::handleINTERP(Value *dst[4])
2750 {
2751 // Check whether the input is linear. All other attributes ignored.
2752 Instruction *insn;
2753 Value *offset = NULL, *ptr = NULL, *w = NULL;
2754 Symbol *sym[4] = { NULL };
2755 bool linear;
2756 operation op = OP_NOP;
2757 int c, mode = 0;
2758
2759 tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2760
2761 // In some odd cases, in large part due to varying packing, the source
2762 // might not actually be an input. This is illegal TGSI, but it's easier to
2763 // account for it here than it is to fix it where the TGSI is being
2764 // generated. In that case, it's going to be a straight up mov (or sequence
2765 // of mov's) from the input in question. We follow the mov chain to see
2766 // which input we need to use.
2767 if (src.getFile() != TGSI_FILE_INPUT) {
2768 if (src.isIndirect(0)) {
2769 ERROR("Ignoring indirect input interpolation\n");
2770 return;
2771 }
2772 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2773 Value *val = fetchSrc(0, c);
2774 assert(val->defs.size() == 1);
2775 insn = val->getInsn();
2776 while (insn->op == OP_MOV) {
2777 assert(insn->getSrc(0)->defs.size() == 1);
2778 insn = insn->getSrc(0)->getInsn();
2779 if (!insn) {
2780 ERROR("Miscompiling shader due to unhandled INTERP\n");
2781 return;
2782 }
2783 }
2784 if (insn->op != OP_LINTERP && insn->op != OP_PINTERP) {
2785 ERROR("Trying to interpolate non-input, this is not allowed.\n");
2786 return;
2787 }
2788 sym[c] = insn->getSrc(0)->asSym();
2789 assert(sym[c]);
2790 op = insn->op;
2791 mode = insn->ipa;
2792 }
2793 } else {
2794 if (src.isIndirect(0))
2795 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2796
2797 // We can assume that the fixed index will point to an input of the same
2798 // interpolation type in case of an indirect.
2799 // TODO: Make use of ArrayID.
2800 linear = info->in[src.getIndex(0)].linear;
2801 if (linear) {
2802 op = OP_LINTERP;
2803 mode = NV50_IR_INTERP_LINEAR;
2804 } else {
2805 op = OP_PINTERP;
2806 mode = NV50_IR_INTERP_PERSPECTIVE;
2807 }
2808 }
2809
2810 switch (tgsi.getOpcode()) {
2811 case TGSI_OPCODE_INTERP_CENTROID:
2812 mode |= NV50_IR_INTERP_CENTROID;
2813 break;
2814 case TGSI_OPCODE_INTERP_SAMPLE:
2815 insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2816 insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2817 mode |= NV50_IR_INTERP_OFFSET;
2818 break;
2819 case TGSI_OPCODE_INTERP_OFFSET: {
2820 // The input in src1.xy is float, but we need a single 32-bit value
2821 // where the upper and lower 16 bits are encoded in S0.12 format. We need
2822 // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2823 // and then convert to s32.
2824 Value *offs[2];
2825 for (c = 0; c < 2; c++) {
2826 offs[c] = fetchSrc(1, c);
2827 mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2828 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2829 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2830 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2831 }
2832 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2833 offs[1], mkImm(0x1010), offs[0]);
2834 mode |= NV50_IR_INTERP_OFFSET;
2835 break;
2836 }
2837 }
2838
2839 if (op == OP_PINTERP) {
2840 if (offset) {
2841 w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2842 mkOp1(OP_RCP, TYPE_F32, w, w);
2843 } else {
2844 w = fragCoord[3];
2845 }
2846 }
2847
2848
2849 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2850 insn = mkOp1(op, TYPE_F32, dst[c], sym[c] ? sym[c] : srcToSym(src, c));
2851 if (op == OP_PINTERP)
2852 insn->setSrc(1, w);
2853 if (ptr)
2854 insn->setIndirect(0, 0, ptr);
2855 if (offset)
2856 insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2857
2858 insn->setInterpolate(mode);
2859 }
2860 }
2861
2862 Converter::Subroutine *
2863 Converter::getSubroutine(unsigned ip)
2864 {
2865 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2866
2867 if (it == sub.map.end())
2868 it = sub.map.insert(std::make_pair(
2869 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2870
2871 return &it->second;
2872 }
2873
2874 Converter::Subroutine *
2875 Converter::getSubroutine(Function *f)
2876 {
2877 unsigned ip = f->getLabel();
2878 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2879
2880 if (it == sub.map.end())
2881 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2882
2883 return &it->second;
2884 }
2885
2886 bool
2887 Converter::isEndOfSubroutine(uint ip)
2888 {
2889 assert(ip < code->scan.num_instructions);
2890 tgsi::Instruction insn(&code->insns[ip]);
2891 return (insn.getOpcode() == TGSI_OPCODE_END ||
2892 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2893 // does END occur at end of main or the very end ?
2894 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2895 }
2896
2897 bool
2898 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2899 {
2900 Instruction *geni;
2901
2902 Value *dst0[4], *rDst0[4];
2903 Value *src0, *src1, *src2, *src3;
2904 Value *val0, *val1;
2905 int c;
2906
2907 tgsi = tgsi::Instruction(insn);
2908
2909 bool useScratchDst = tgsi.checkDstSrcAliasing();
2910
2911 operation op = tgsi.getOP();
2912 dstTy = tgsi.inferDstType();
2913 srcTy = tgsi.inferSrcType();
2914
2915 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2916
2917 if (tgsi.dstCount()) {
2918 for (c = 0; c < 4; ++c) {
2919 rDst0[c] = acquireDst(0, c);
2920 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2921 }
2922 }
2923
2924 switch (tgsi.getOpcode()) {
2925 case TGSI_OPCODE_ADD:
2926 case TGSI_OPCODE_UADD:
2927 case TGSI_OPCODE_AND:
2928 case TGSI_OPCODE_DIV:
2929 case TGSI_OPCODE_IDIV:
2930 case TGSI_OPCODE_UDIV:
2931 case TGSI_OPCODE_MAX:
2932 case TGSI_OPCODE_MIN:
2933 case TGSI_OPCODE_IMAX:
2934 case TGSI_OPCODE_IMIN:
2935 case TGSI_OPCODE_UMAX:
2936 case TGSI_OPCODE_UMIN:
2937 case TGSI_OPCODE_MOD:
2938 case TGSI_OPCODE_UMOD:
2939 case TGSI_OPCODE_MUL:
2940 case TGSI_OPCODE_UMUL:
2941 case TGSI_OPCODE_IMUL_HI:
2942 case TGSI_OPCODE_UMUL_HI:
2943 case TGSI_OPCODE_OR:
2944 case TGSI_OPCODE_SHL:
2945 case TGSI_OPCODE_ISHR:
2946 case TGSI_OPCODE_USHR:
2947 case TGSI_OPCODE_SUB:
2948 case TGSI_OPCODE_XOR:
2949 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2950 src0 = fetchSrc(0, c);
2951 src1 = fetchSrc(1, c);
2952 geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2953 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2954 }
2955 break;
2956 case TGSI_OPCODE_MAD:
2957 case TGSI_OPCODE_UMAD:
2958 case TGSI_OPCODE_SAD:
2959 case TGSI_OPCODE_FMA:
2960 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2961 src0 = fetchSrc(0, c);
2962 src1 = fetchSrc(1, c);
2963 src2 = fetchSrc(2, c);
2964 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2965 }
2966 break;
2967 case TGSI_OPCODE_MOV:
2968 case TGSI_OPCODE_ABS:
2969 case TGSI_OPCODE_CEIL:
2970 case TGSI_OPCODE_FLR:
2971 case TGSI_OPCODE_TRUNC:
2972 case TGSI_OPCODE_RCP:
2973 case TGSI_OPCODE_SQRT:
2974 case TGSI_OPCODE_IABS:
2975 case TGSI_OPCODE_INEG:
2976 case TGSI_OPCODE_NOT:
2977 case TGSI_OPCODE_DDX:
2978 case TGSI_OPCODE_DDY:
2979 case TGSI_OPCODE_DDX_FINE:
2980 case TGSI_OPCODE_DDY_FINE:
2981 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2982 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2983 break;
2984 case TGSI_OPCODE_RSQ:
2985 src0 = fetchSrc(0, 0);
2986 val0 = getScratch();
2987 mkOp1(OP_ABS, TYPE_F32, val0, src0);
2988 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2989 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2990 mkMov(dst0[c], val0);
2991 break;
2992 case TGSI_OPCODE_ARL:
2993 case TGSI_OPCODE_ARR:
2994 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2995 const RoundMode rnd =
2996 tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
2997 src0 = fetchSrc(0, c);
2998 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
2999 }
3000 break;
3001 case TGSI_OPCODE_UARL:
3002 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3003 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
3004 break;
3005 case TGSI_OPCODE_POW:
3006 val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
3007 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3008 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3009 break;
3010 case TGSI_OPCODE_EX2:
3011 case TGSI_OPCODE_LG2:
3012 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
3013 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3014 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3015 break;
3016 case TGSI_OPCODE_COS:
3017 case TGSI_OPCODE_SIN:
3018 val0 = getScratch();
3019 if (mask & 7) {
3020 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
3021 mkOp1(op, TYPE_F32, val0, val0);
3022 for (c = 0; c < 3; ++c)
3023 if (dst0[c])
3024 mkMov(dst0[c], val0);
3025 }
3026 if (dst0[3]) {
3027 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
3028 mkOp1(op, TYPE_F32, dst0[3], val0);
3029 }
3030 break;
3031 case TGSI_OPCODE_SCS:
3032 if (mask & 3) {
3033 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
3034 if (dst0[0])
3035 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
3036 if (dst0[1])
3037 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
3038 }
3039 if (dst0[2])
3040 loadImm(dst0[2], 0.0f);
3041 if (dst0[3])
3042 loadImm(dst0[3], 1.0f);
3043 break;
3044 case TGSI_OPCODE_EXP:
3045 src0 = fetchSrc(0, 0);
3046 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
3047 if (dst0[1])
3048 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
3049 if (dst0[0])
3050 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
3051 if (dst0[2])
3052 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
3053 if (dst0[3])
3054 loadImm(dst0[3], 1.0f);
3055 break;
3056 case TGSI_OPCODE_LOG:
3057 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
3058 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
3059 if (dst0[0] || dst0[1])
3060 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
3061 if (dst0[1]) {
3062 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
3063 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
3064 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
3065 }
3066 if (dst0[3])
3067 loadImm(dst0[3], 1.0f);
3068 break;
3069 case TGSI_OPCODE_DP2:
3070 val0 = buildDot(2);
3071 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3072 mkMov(dst0[c], val0);
3073 break;
3074 case TGSI_OPCODE_DP3:
3075 val0 = buildDot(3);
3076 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3077 mkMov(dst0[c], val0);
3078 break;
3079 case TGSI_OPCODE_DP4:
3080 val0 = buildDot(4);
3081 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3082 mkMov(dst0[c], val0);
3083 break;
3084 case TGSI_OPCODE_DPH:
3085 val0 = buildDot(3);
3086 src1 = fetchSrc(1, 3);
3087 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
3088 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3089 mkMov(dst0[c], val0);
3090 break;
3091 case TGSI_OPCODE_DST:
3092 if (dst0[0])
3093 loadImm(dst0[0], 1.0f);
3094 if (dst0[1]) {
3095 src0 = fetchSrc(0, 1);
3096 src1 = fetchSrc(1, 1);
3097 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
3098 }
3099 if (dst0[2])
3100 mkMov(dst0[2], fetchSrc(0, 2));
3101 if (dst0[3])
3102 mkMov(dst0[3], fetchSrc(1, 3));
3103 break;
3104 case TGSI_OPCODE_LRP:
3105 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3106 src0 = fetchSrc(0, c);
3107 src1 = fetchSrc(1, c);
3108 src2 = fetchSrc(2, c);
3109 mkOp3(OP_MAD, TYPE_F32, dst0[c],
3110 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
3111 }
3112 break;
3113 case TGSI_OPCODE_LIT:
3114 handleLIT(dst0);
3115 break;
3116 case TGSI_OPCODE_XPD:
3117 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3118 if (c < 3) {
3119 val0 = getSSA();
3120 src0 = fetchSrc(1, (c + 1) % 3);
3121 src1 = fetchSrc(0, (c + 2) % 3);
3122 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
3123 mkOp1(OP_NEG, TYPE_F32, val0, val0);
3124
3125 src0 = fetchSrc(0, (c + 1) % 3);
3126 src1 = fetchSrc(1, (c + 2) % 3);
3127 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
3128 } else {
3129 loadImm(dst0[c], 1.0f);
3130 }
3131 }
3132 break;
3133 case TGSI_OPCODE_ISSG:
3134 case TGSI_OPCODE_SSG:
3135 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3136 src0 = fetchSrc(0, c);
3137 val0 = getScratch();
3138 val1 = getScratch();
3139 mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
3140 mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
3141 if (srcTy == TYPE_F32)
3142 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
3143 else
3144 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
3145 }
3146 break;
3147 case TGSI_OPCODE_UCMP:
3148 srcTy = TYPE_U32;
3149 /* fallthrough */
3150 case TGSI_OPCODE_CMP:
3151 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3152 src0 = fetchSrc(0, c);
3153 src1 = fetchSrc(1, c);
3154 src2 = fetchSrc(2, c);
3155 if (src1 == src2)
3156 mkMov(dst0[c], src1);
3157 else
3158 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
3159 srcTy, dst0[c], srcTy, src1, src2, src0);
3160 }
3161 break;
3162 case TGSI_OPCODE_FRC:
3163 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3164 src0 = fetchSrc(0, c);
3165 val0 = getScratch();
3166 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
3167 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
3168 }
3169 break;
3170 case TGSI_OPCODE_ROUND:
3171 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3172 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
3173 ->rnd = ROUND_NI;
3174 break;
3175 case TGSI_OPCODE_CLAMP:
3176 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3177 src0 = fetchSrc(0, c);
3178 src1 = fetchSrc(1, c);
3179 src2 = fetchSrc(2, c);
3180 val0 = getScratch();
3181 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
3182 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
3183 }
3184 break;
3185 case TGSI_OPCODE_SLT:
3186 case TGSI_OPCODE_SGE:
3187 case TGSI_OPCODE_SEQ:
3188 case TGSI_OPCODE_SGT:
3189 case TGSI_OPCODE_SLE:
3190 case TGSI_OPCODE_SNE:
3191 case TGSI_OPCODE_FSEQ:
3192 case TGSI_OPCODE_FSGE:
3193 case TGSI_OPCODE_FSLT:
3194 case TGSI_OPCODE_FSNE:
3195 case TGSI_OPCODE_ISGE:
3196 case TGSI_OPCODE_ISLT:
3197 case TGSI_OPCODE_USEQ:
3198 case TGSI_OPCODE_USGE:
3199 case TGSI_OPCODE_USLT:
3200 case TGSI_OPCODE_USNE:
3201 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3202 src0 = fetchSrc(0, c);
3203 src1 = fetchSrc(1, c);
3204 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3205 }
3206 break;
3207 case TGSI_OPCODE_VOTE_ALL:
3208 case TGSI_OPCODE_VOTE_ANY:
3209 case TGSI_OPCODE_VOTE_EQ:
3210 val0 = new_LValue(func, FILE_PREDICATE);
3211 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3212 mkCmp(OP_SET, CC_NE, TYPE_U32, val0, TYPE_U32, fetchSrc(0, c), zero);
3213 mkOp1(op, dstTy, val0, val0)
3214 ->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3215 mkCvt(OP_CVT, TYPE_U32, dst0[c], TYPE_U8, val0);
3216 }
3217 break;
3218 case TGSI_OPCODE_KILL_IF:
3219 val0 = new_LValue(func, FILE_PREDICATE);
3220 mask = 0;
3221 for (c = 0; c < 4; ++c) {
3222 const int s = tgsi.getSrc(0).getSwizzle(c);
3223 if (mask & (1 << s))
3224 continue;
3225 mask |= 1 << s;
3226 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
3227 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
3228 }
3229 break;
3230 case TGSI_OPCODE_KILL:
3231 mkOp(OP_DISCARD, TYPE_NONE, NULL);
3232 break;
3233 case TGSI_OPCODE_TEX:
3234 case TGSI_OPCODE_TXB:
3235 case TGSI_OPCODE_TXL:
3236 case TGSI_OPCODE_TXP:
3237 case TGSI_OPCODE_LODQ:
3238 // R S L C Dx Dy
3239 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
3240 break;
3241 case TGSI_OPCODE_TXD:
3242 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
3243 break;
3244 case TGSI_OPCODE_TG4:
3245 handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
3246 break;
3247 case TGSI_OPCODE_TEX2:
3248 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
3249 break;
3250 case TGSI_OPCODE_TXB2:
3251 case TGSI_OPCODE_TXL2:
3252 handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
3253 break;
3254 case TGSI_OPCODE_SAMPLE:
3255 case TGSI_OPCODE_SAMPLE_B:
3256 case TGSI_OPCODE_SAMPLE_D:
3257 case TGSI_OPCODE_SAMPLE_L:
3258 case TGSI_OPCODE_SAMPLE_C:
3259 case TGSI_OPCODE_SAMPLE_C_LZ:
3260 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
3261 break;
3262 case TGSI_OPCODE_TXF:
3263 handleTXF(dst0, 1, 0x03);
3264 break;
3265 case TGSI_OPCODE_SAMPLE_I:
3266 handleTXF(dst0, 1, 0x03);
3267 break;
3268 case TGSI_OPCODE_SAMPLE_I_MS:
3269 handleTXF(dst0, 1, 0x20);
3270 break;
3271 case TGSI_OPCODE_TXQ:
3272 case TGSI_OPCODE_SVIEWINFO:
3273 handleTXQ(dst0, TXQ_DIMS, 1);
3274 break;
3275 case TGSI_OPCODE_TXQS:
3276 // The TXQ_TYPE query returns samples in its 3rd arg, but we need it to
3277 // be in .x
3278 dst0[1] = dst0[2] = dst0[3] = NULL;
3279 std::swap(dst0[0], dst0[2]);
3280 handleTXQ(dst0, TXQ_TYPE, 0);
3281 std::swap(dst0[0], dst0[2]);
3282 break;
3283 case TGSI_OPCODE_F2I:
3284 case TGSI_OPCODE_F2U:
3285 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3286 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
3287 break;
3288 case TGSI_OPCODE_I2F:
3289 case TGSI_OPCODE_U2F:
3290 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3291 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
3292 break;
3293 case TGSI_OPCODE_PK2H:
3294 val0 = getScratch();
3295 val1 = getScratch();
3296 mkCvt(OP_CVT, TYPE_F16, val0, TYPE_F32, fetchSrc(0, 0));
3297 mkCvt(OP_CVT, TYPE_F16, val1, TYPE_F32, fetchSrc(0, 1));
3298 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3299 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3300 break;
3301 case TGSI_OPCODE_UP2H:
3302 src0 = fetchSrc(0, 0);
3303 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3304 geni = mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F16, src0);
3305 geni->subOp = c & 1;
3306 }
3307 break;
3308 case TGSI_OPCODE_EMIT:
3309 /* export the saved viewport index */
3310 if (viewport != NULL) {
3311 Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
3312 info->out[info->io.viewportId].slot[0] * 4);
3313 mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
3314 }
3315 /* fallthrough */
3316 case TGSI_OPCODE_ENDPRIM:
3317 {
3318 // get vertex stream (must be immediate)
3319 unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
3320 if (stream && op == OP_RESTART)
3321 break;
3322 if (info->prop.gp.maxVertices == 0)
3323 break;
3324 src0 = mkImm(stream);
3325 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
3326 break;
3327 }
3328 case TGSI_OPCODE_IF:
3329 case TGSI_OPCODE_UIF:
3330 {
3331 BasicBlock *ifBB = new BasicBlock(func);
3332
3333 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
3334 condBBs.push(bb);
3335 joinBBs.push(bb);
3336
3337 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
3338
3339 setPosition(ifBB, true);
3340 }
3341 break;
3342 case TGSI_OPCODE_ELSE:
3343 {
3344 BasicBlock *elseBB = new BasicBlock(func);
3345 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3346
3347 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
3348 condBBs.push(bb);
3349
3350 forkBB->getExit()->asFlow()->target.bb = elseBB;
3351 if (!bb->isTerminated())
3352 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
3353
3354 setPosition(elseBB, true);
3355 }
3356 break;
3357 case TGSI_OPCODE_ENDIF:
3358 {
3359 BasicBlock *convBB = new BasicBlock(func);
3360 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3361 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
3362
3363 if (!bb->isTerminated()) {
3364 // we only want join if none of the clauses ended with CONT/BREAK/RET
3365 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
3366 insertConvergenceOps(convBB, forkBB);
3367 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
3368 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3369 }
3370
3371 if (prevBB->getExit()->op == OP_BRA) {
3372 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3373 prevBB->getExit()->asFlow()->target.bb = convBB;
3374 }
3375 setPosition(convBB, true);
3376 }
3377 break;
3378 case TGSI_OPCODE_BGNLOOP:
3379 {
3380 BasicBlock *lbgnBB = new BasicBlock(func);
3381 BasicBlock *lbrkBB = new BasicBlock(func);
3382
3383 loopBBs.push(lbgnBB);
3384 breakBBs.push(lbrkBB);
3385 if (loopBBs.getSize() > func->loopNestingBound)
3386 func->loopNestingBound++;
3387
3388 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
3389
3390 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
3391 setPosition(lbgnBB, true);
3392 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
3393 }
3394 break;
3395 case TGSI_OPCODE_ENDLOOP:
3396 {
3397 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
3398
3399 if (!bb->isTerminated()) {
3400 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
3401 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
3402 }
3403 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
3404
3405 // If the loop never breaks (e.g. only has RET's inside), then there
3406 // will be no way to get to the break bb. However BGNLOOP will have
3407 // already made a PREBREAK to it, so it must be in the CFG.
3408 if (getBB()->cfg.incidentCount() == 0)
3409 loopBB->cfg.attach(&getBB()->cfg, Graph::Edge::TREE);
3410 }
3411 break;
3412 case TGSI_OPCODE_BRK:
3413 {
3414 if (bb->isTerminated())
3415 break;
3416 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
3417 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
3418 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
3419 }
3420 break;
3421 case TGSI_OPCODE_CONT:
3422 {
3423 if (bb->isTerminated())
3424 break;
3425 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
3426 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
3427 contBB->explicitCont = true;
3428 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
3429 }
3430 break;
3431 case TGSI_OPCODE_BGNSUB:
3432 {
3433 Subroutine *s = getSubroutine(ip);
3434 BasicBlock *entry = new BasicBlock(s->f);
3435 BasicBlock *leave = new BasicBlock(s->f);
3436
3437 // multiple entrypoints possible, keep the graph connected
3438 if (prog->getType() == Program::TYPE_COMPUTE)
3439 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
3440
3441 sub.cur = s;
3442 s->f->setEntry(entry);
3443 s->f->setExit(leave);
3444 setPosition(entry, true);
3445 return true;
3446 }
3447 case TGSI_OPCODE_ENDSUB:
3448 {
3449 sub.cur = getSubroutine(prog->main);
3450 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
3451 return true;
3452 }
3453 case TGSI_OPCODE_CAL:
3454 {
3455 Subroutine *s = getSubroutine(tgsi.getLabel());
3456 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
3457 func->call.attach(&s->f->call, Graph::Edge::TREE);
3458 return true;
3459 }
3460 case TGSI_OPCODE_RET:
3461 {
3462 if (bb->isTerminated())
3463 return true;
3464 BasicBlock *leave = BasicBlock::get(func->cfgExit);
3465
3466 if (!isEndOfSubroutine(ip + 1)) {
3467 // insert a PRERET at the entry if this is an early return
3468 // (only needed for sharing code in the epilogue)
3469 BasicBlock *root = BasicBlock::get(func->cfg.getRoot());
3470 if (root->getEntry() == NULL || root->getEntry()->op != OP_PRERET) {
3471 BasicBlock *pos = getBB();
3472 setPosition(root, false);
3473 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
3474 setPosition(pos, true);
3475 }
3476 }
3477 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
3478 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
3479 }
3480 break;
3481 case TGSI_OPCODE_END:
3482 {
3483 // attach and generate epilogue code
3484 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
3485 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
3486 setPosition(epilogue, true);
3487 if (prog->getType() == Program::TYPE_FRAGMENT)
3488 exportOutputs();
3489 if (info->io.genUserClip > 0)
3490 handleUserClipPlanes();
3491 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
3492 }
3493 break;
3494 case TGSI_OPCODE_SWITCH:
3495 case TGSI_OPCODE_CASE:
3496 ERROR("switch/case opcode encountered, should have been lowered\n");
3497 abort();
3498 break;
3499 case TGSI_OPCODE_LOAD:
3500 handleLOAD(dst0);
3501 break;
3502 case TGSI_OPCODE_STORE:
3503 handleSTORE();
3504 break;
3505 case TGSI_OPCODE_BARRIER:
3506 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
3507 geni->fixed = 1;
3508 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
3509 break;
3510 case TGSI_OPCODE_MFENCE:
3511 case TGSI_OPCODE_LFENCE:
3512 case TGSI_OPCODE_SFENCE:
3513 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3514 geni->fixed = 1;
3515 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3516 break;
3517 case TGSI_OPCODE_MEMBAR:
3518 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3519 geni->fixed = 1;
3520 if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
3521 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
3522 else
3523 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
3524 break;
3525 case TGSI_OPCODE_ATOMUADD:
3526 case TGSI_OPCODE_ATOMXCHG:
3527 case TGSI_OPCODE_ATOMCAS:
3528 case TGSI_OPCODE_ATOMAND:
3529 case TGSI_OPCODE_ATOMOR:
3530 case TGSI_OPCODE_ATOMXOR:
3531 case TGSI_OPCODE_ATOMUMIN:
3532 case TGSI_OPCODE_ATOMIMIN:
3533 case TGSI_OPCODE_ATOMUMAX:
3534 case TGSI_OPCODE_ATOMIMAX:
3535 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
3536 break;
3537 case TGSI_OPCODE_RESQ:
3538 if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER) {
3539 geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
3540 makeSym(tgsi.getSrc(0).getFile(),
3541 tgsi.getSrc(0).getIndex(0), -1, 0, 0));
3542 if (tgsi.getSrc(0).isIndirect(0))
3543 geni->setIndirect(0, 1,
3544 fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
3545 } else {
3546 assert(tgsi.getSrc(0).getFile() == TGSI_FILE_IMAGE);
3547
3548 TexInstruction *texi = new_TexInstruction(func, OP_SUQ);
3549 for (int c = 0, d = 0; c < 4; ++c) {
3550 if (dst0[c]) {
3551 texi->setDef(d++, dst0[c]);
3552 texi->tex.mask |= 1 << c;
3553 }
3554 }
3555 texi->tex.r = tgsi.getSrc(0).getIndex(0);
3556 texi->tex.target = getImageTarget(code, texi->tex.r);
3557 bb->insertTail(texi);
3558
3559 if (tgsi.getSrc(0).isIndirect(0))
3560 texi->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
3561 }
3562 break;
3563 case TGSI_OPCODE_IBFE:
3564 case TGSI_OPCODE_UBFE:
3565 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3566 src0 = fetchSrc(0, c);
3567 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
3568 tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
3569 src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
3570 tgsi.getSrc(1).getValueU32(c, info));
3571 } else {
3572 src1 = fetchSrc(1, c);
3573 src2 = fetchSrc(2, c);
3574 mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
3575 }
3576 mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
3577 }
3578 break;
3579 case TGSI_OPCODE_BFI:
3580 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3581 src0 = fetchSrc(0, c);
3582 src1 = fetchSrc(1, c);
3583 src2 = fetchSrc(2, c);
3584 src3 = fetchSrc(3, c);
3585 mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
3586 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
3587 }
3588 break;
3589 case TGSI_OPCODE_LSB:
3590 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3591 src0 = fetchSrc(0, c);
3592 geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
3593 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3594 geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
3595 geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3596 }
3597 break;
3598 case TGSI_OPCODE_IMSB:
3599 case TGSI_OPCODE_UMSB:
3600 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3601 src0 = fetchSrc(0, c);
3602 mkOp1(OP_BFIND, srcTy, dst0[c], src0);
3603 }
3604 break;
3605 case TGSI_OPCODE_BREV:
3606 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3607 src0 = fetchSrc(0, c);
3608 geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
3609 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3610 }
3611 break;
3612 case TGSI_OPCODE_POPC:
3613 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3614 src0 = fetchSrc(0, c);
3615 mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
3616 }
3617 break;
3618 case TGSI_OPCODE_INTERP_CENTROID:
3619 case TGSI_OPCODE_INTERP_SAMPLE:
3620 case TGSI_OPCODE_INTERP_OFFSET:
3621 handleINTERP(dst0);
3622 break;
3623 case TGSI_OPCODE_D2I:
3624 case TGSI_OPCODE_D2U:
3625 case TGSI_OPCODE_D2F: {
3626 int pos = 0;
3627 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3628 Value *dreg = getSSA(8);
3629 src0 = fetchSrc(0, pos);
3630 src1 = fetchSrc(0, pos + 1);
3631 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3632 Instruction *cvt = mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
3633 if (!isFloatType(dstTy))
3634 cvt->rnd = ROUND_Z;
3635 pos += 2;
3636 }
3637 break;
3638 }
3639 case TGSI_OPCODE_I2D:
3640 case TGSI_OPCODE_U2D:
3641 case TGSI_OPCODE_F2D:
3642 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3643 Value *dreg = getSSA(8);
3644 mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
3645 mkSplit(&dst0[c], 4, dreg);
3646 c++;
3647 }
3648 break;
3649 case TGSI_OPCODE_DABS:
3650 case TGSI_OPCODE_DNEG:
3651 case TGSI_OPCODE_DRCP:
3652 case TGSI_OPCODE_DSQRT:
3653 case TGSI_OPCODE_DRSQ:
3654 case TGSI_OPCODE_DTRUNC:
3655 case TGSI_OPCODE_DCEIL:
3656 case TGSI_OPCODE_DFLR:
3657 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3658 src0 = getSSA(8);
3659 Value *dst = getSSA(8), *tmp[2];
3660 tmp[0] = fetchSrc(0, c);
3661 tmp[1] = fetchSrc(0, c + 1);
3662 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3663 mkOp1(op, dstTy, dst, src0);
3664 mkSplit(&dst0[c], 4, dst);
3665 c++;
3666 }
3667 break;
3668 case TGSI_OPCODE_DFRAC:
3669 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3670 src0 = getSSA(8);
3671 Value *dst = getSSA(8), *tmp[2];
3672 tmp[0] = fetchSrc(0, c);
3673 tmp[1] = fetchSrc(0, c + 1);
3674 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3675 mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3676 mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3677 mkSplit(&dst0[c], 4, dst);
3678 c++;
3679 }
3680 break;
3681 case TGSI_OPCODE_DSLT:
3682 case TGSI_OPCODE_DSGE:
3683 case TGSI_OPCODE_DSEQ:
3684 case TGSI_OPCODE_DSNE: {
3685 int pos = 0;
3686 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3687 Value *tmp[2];
3688
3689 src0 = getSSA(8);
3690 src1 = getSSA(8);
3691 tmp[0] = fetchSrc(0, pos);
3692 tmp[1] = fetchSrc(0, pos + 1);
3693 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3694 tmp[0] = fetchSrc(1, pos);
3695 tmp[1] = fetchSrc(1, pos + 1);
3696 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3697 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3698 pos += 2;
3699 }
3700 break;
3701 }
3702 case TGSI_OPCODE_DADD:
3703 case TGSI_OPCODE_DMUL:
3704 case TGSI_OPCODE_DMAX:
3705 case TGSI_OPCODE_DMIN:
3706 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3707 src0 = getSSA(8);
3708 src1 = getSSA(8);
3709 Value *dst = getSSA(8), *tmp[2];
3710 tmp[0] = fetchSrc(0, c);
3711 tmp[1] = fetchSrc(0, c + 1);
3712 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3713 tmp[0] = fetchSrc(1, c);
3714 tmp[1] = fetchSrc(1, c + 1);
3715 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3716 mkOp2(op, dstTy, dst, src0, src1);
3717 mkSplit(&dst0[c], 4, dst);
3718 c++;
3719 }
3720 break;
3721 case TGSI_OPCODE_DMAD:
3722 case TGSI_OPCODE_DFMA:
3723 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3724 src0 = getSSA(8);
3725 src1 = getSSA(8);
3726 src2 = getSSA(8);
3727 Value *dst = getSSA(8), *tmp[2];
3728 tmp[0] = fetchSrc(0, c);
3729 tmp[1] = fetchSrc(0, c + 1);
3730 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3731 tmp[0] = fetchSrc(1, c);
3732 tmp[1] = fetchSrc(1, c + 1);
3733 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3734 tmp[0] = fetchSrc(2, c);
3735 tmp[1] = fetchSrc(2, c + 1);
3736 mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3737 mkOp3(op, dstTy, dst, src0, src1, src2);
3738 mkSplit(&dst0[c], 4, dst);
3739 c++;
3740 }
3741 break;
3742 case TGSI_OPCODE_DROUND:
3743 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3744 src0 = getSSA(8);
3745 Value *dst = getSSA(8), *tmp[2];
3746 tmp[0] = fetchSrc(0, c);
3747 tmp[1] = fetchSrc(0, c + 1);
3748 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3749 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3750 ->rnd = ROUND_NI;
3751 mkSplit(&dst0[c], 4, dst);
3752 c++;
3753 }
3754 break;
3755 case TGSI_OPCODE_DSSG:
3756 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3757 src0 = getSSA(8);
3758 Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3759 tmp[0] = fetchSrc(0, c);
3760 tmp[1] = fetchSrc(0, c + 1);
3761 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3762
3763 val0 = getScratch();
3764 val1 = getScratch();
3765 // The zero is wrong here since it's only 32-bit, but it works out in
3766 // the end since it gets replaced with $r63.
3767 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3768 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3769 mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3770 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3771 mkSplit(&dst0[c], 4, dst);
3772 c++;
3773 }
3774 break;
3775 default:
3776 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3777 assert(0);
3778 break;
3779 }
3780
3781 if (tgsi.dstCount()) {
3782 for (c = 0; c < 4; ++c) {
3783 if (!dst0[c])
3784 continue;
3785 if (dst0[c] != rDst0[c])
3786 mkMov(rDst0[c], dst0[c]);
3787 storeDst(0, c, rDst0[c]);
3788 }
3789 }
3790 vtxBaseValid = 0;
3791
3792 return true;
3793 }
3794
3795 void
3796 Converter::handleUserClipPlanes()
3797 {
3798 Value *res[8];
3799 int n, i, c;
3800
3801 for (c = 0; c < 4; ++c) {
3802 for (i = 0; i < info->io.genUserClip; ++i) {
3803 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3804 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3805 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3806 if (c == 0)
3807 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3808 else
3809 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3810 }
3811 }
3812
3813 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3814
3815 for (i = 0; i < info->io.genUserClip; ++i) {
3816 n = i / 4 + first;
3817 c = i % 4;
3818 Symbol *sym =
3819 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3820 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3821 }
3822 }
3823
3824 void
3825 Converter::exportOutputs()
3826 {
3827 if (info->io.alphaRefBase) {
3828 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3829 if (info->out[i].sn != TGSI_SEMANTIC_COLOR ||
3830 info->out[i].si != 0)
3831 continue;
3832 const unsigned int c = 3;
3833 if (!oData.exists(sub.cur->values, i, c))
3834 continue;
3835 Value *val = oData.load(sub.cur->values, i, c, NULL);
3836 if (!val)
3837 continue;
3838
3839 Symbol *ref = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3840 TYPE_U32, info->io.alphaRefBase);
3841 Value *pred = new_LValue(func, FILE_PREDICATE);
3842 mkCmp(OP_SET, CC_TR, TYPE_U32, pred, TYPE_F32, val,
3843 mkLoadv(TYPE_U32, ref, NULL))
3844 ->subOp = 1;
3845 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_NOT_P, pred);
3846 }
3847 }
3848
3849 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3850 for (unsigned int c = 0; c < 4; ++c) {
3851 if (!oData.exists(sub.cur->values, i, c))
3852 continue;
3853 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3854 info->out[i].slot[c] * 4);
3855 Value *val = oData.load(sub.cur->values, i, c, NULL);
3856 if (val) {
3857 if (info->out[i].sn == TGSI_SEMANTIC_POSITION)
3858 mkOp1(OP_SAT, TYPE_F32, val, val);
3859 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3860 }
3861 }
3862 }
3863 }
3864
3865 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3866 code(code),
3867 tgsi(NULL),
3868 tData(this), lData(this), aData(this), pData(this), oData(this)
3869 {
3870 info = code->info;
3871
3872 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3873 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3874 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3875 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3876
3877 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, FILE_GPR, 0);
3878 lData.setup(TGSI_FILE_TEMPORARY, 1, 0, tSize, 4, 4, FILE_MEMORY_LOCAL, 0);
3879 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3880 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3881 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3882
3883 zero = mkImm((uint32_t)0);
3884
3885 vtxBaseValid = 0;
3886 }
3887
3888 Converter::~Converter()
3889 {
3890 }
3891
3892 inline const Converter::Location *
3893 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3894 {
3895 ValueMap::l_iterator it = s->values.l.find(v);
3896 return it == s->values.l.end() ? NULL : &it->second;
3897 }
3898
3899 template<typename T> inline void
3900 Converter::BindArgumentsPass::updateCallArgs(
3901 Instruction *i, void (Instruction::*setArg)(int, Value *),
3902 T (Function::*proto))
3903 {
3904 Function *g = i->asFlow()->target.fn;
3905 Subroutine *subg = conv.getSubroutine(g);
3906
3907 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3908 Value *v = (g->*proto)[a].get();
3909 const Converter::Location &l = *getValueLocation(subg, v);
3910 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3911
3912 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3913 }
3914 }
3915
3916 template<typename T> inline void
3917 Converter::BindArgumentsPass::updatePrototype(
3918 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3919 {
3920 (func->*updateSet)();
3921
3922 for (unsigned i = 0; i < set->getSize(); ++i) {
3923 Value *v = func->getLValue(i);
3924 const Converter::Location *l = getValueLocation(sub, v);
3925
3926 // only include values with a matching TGSI register
3927 if (set->test(i) && l && !conv.code->locals.count(*l))
3928 (func->*proto).push_back(v);
3929 }
3930 }
3931
3932 bool
3933 Converter::BindArgumentsPass::visit(Function *f)
3934 {
3935 sub = conv.getSubroutine(f);
3936
3937 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3938 !bi.end(); bi.next()) {
3939 for (Instruction *i = BasicBlock::get(bi)->getFirst();
3940 i; i = i->next) {
3941 if (i->op == OP_CALL && !i->asFlow()->builtin) {
3942 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3943 updateCallArgs(i, &Instruction::setDef, &Function::outs);
3944 }
3945 }
3946 }
3947
3948 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3949 return true;
3950 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3951 &Function::buildLiveSets, &Function::ins);
3952 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3953 &Function::buildDefSets, &Function::outs);
3954
3955 return true;
3956 }
3957
3958 bool
3959 Converter::run()
3960 {
3961 BasicBlock *entry = new BasicBlock(prog->main);
3962 BasicBlock *leave = new BasicBlock(prog->main);
3963
3964 prog->main->setEntry(entry);
3965 prog->main->setExit(leave);
3966
3967 setPosition(entry, true);
3968 sub.cur = getSubroutine(prog->main);
3969
3970 if (info->io.genUserClip > 0) {
3971 for (int c = 0; c < 4; ++c)
3972 clipVtx[c] = getScratch();
3973 }
3974
3975 switch (prog->getType()) {
3976 case Program::TYPE_TESSELLATION_CONTROL:
3977 outBase = mkOp2v(
3978 OP_SUB, TYPE_U32, getSSA(),
3979 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
3980 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
3981 break;
3982 case Program::TYPE_FRAGMENT: {
3983 Symbol *sv = mkSysVal(SV_POSITION, 3);
3984 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
3985 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
3986 break;
3987 }
3988 default:
3989 break;
3990 }
3991
3992 if (info->io.viewportId >= 0)
3993 viewport = getScratch();
3994 else
3995 viewport = NULL;
3996
3997 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
3998 if (!handleInstruction(&code->insns[ip]))
3999 return false;
4000 }
4001
4002 if (!BindArgumentsPass(*this).run(prog))
4003 return false;
4004
4005 return true;
4006 }
4007
4008 } // unnamed namespace
4009
4010 namespace nv50_ir {
4011
4012 bool
4013 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
4014 {
4015 tgsi::Source src(info);
4016 if (!src.scanSource())
4017 return false;
4018 tlsSize = info->bin.tlsSpace;
4019
4020 Converter builder(this, &src);
4021 return builder.run();
4022 }
4023
4024 } // namespace nv50_ir