src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "tgsi/tgsi_dump.h"
  24 #include "tgsi/tgsi_scan.h"
  25 #include "tgsi/tgsi_util.h"
  26
  27 #include <set>
  28
  29 #include "codegen/nv50_ir.h"
  30 #include "codegen/nv50_ir_util.h"
  31 #include "codegen/nv50_ir_build_util.h"
  32
  33 namespace tgsi {
  34
  35 class Source;
  36
  37 static nv50_ir::operation translateOpcode(uint opcode);
  38 static nv50_ir::DataFile translateFile(uint file);
  39 static nv50_ir::TexTarget translateTexture(uint texTarg);
  40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
  41
  42 class Instruction
  43 {
  44 public:
  45    Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
  46
  47    class SrcRegister
  48    {
  49    public:
  50       SrcRegister(const struct tgsi_full_src_register *src)
  51          : reg(src->Register),
  52            fsr(src)
  53       { }
  54
  55       SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
  56
  57       SrcRegister(const struct tgsi_ind_register& ind)
  58          : reg(tgsi_util_get_src_from_ind(&ind)),
  59            fsr(NULL)
  60       { }
  61
  62       struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
  63       {
  64          struct tgsi_src_register reg;
  65          memset(&reg, 0, sizeof(reg));
  66          reg.Index = off.Index;
  67          reg.File = off.File;
  68          reg.SwizzleX = off.SwizzleX;
  69          reg.SwizzleY = off.SwizzleY;
  70          reg.SwizzleZ = off.SwizzleZ;
  71          return reg;
  72       }
  73
  74       SrcRegister(const struct tgsi_texture_offset& off) :
  75          reg(offsetToSrc(off)),
  76          fsr(NULL)
  77       { }
  78
  79       uint getFile() const { return reg.File; }
  80
  81       bool is2D() const { return reg.Dimension; }
  82
  83       bool isIndirect(int dim) const
  84       {
  85          return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
  86       }
  87
  88       int getIndex(int dim) const
  89       {
  90          return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
  91       }
  92
  93       int getSwizzle(int chan) const
  94       {
  95          return tgsi_util_get_src_register_swizzle(&reg, chan);
  96       }
  97
  98       nv50_ir::Modifier getMod(int chan) const;
  99
 100       SrcRegister getIndirect(int dim) const
 101       {
 102          assert(fsr && isIndirect(dim));
 103          if (dim)
 104             return SrcRegister(fsr->DimIndirect);
 105          return SrcRegister(fsr->Indirect);
 106       }
 107
 108       uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
 109       {
 110          assert(reg.File == TGSI_FILE_IMMEDIATE);
 111          assert(!reg.Absolute);
 112          assert(!reg.Negate);
 113          return info->immd.data[reg.Index * 4 + getSwizzle(c)];
 114       }
 115
 116    private:
 117       const struct tgsi_src_register reg;
 118       const struct tgsi_full_src_register *fsr;
 119    };
 120
 121    class DstRegister
 122    {
 123    public:
 124       DstRegister(const struct tgsi_full_dst_register *dst)
 125          : reg(dst->Register),
 126            fdr(dst)
 127       { }
 128
 129       DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
 130
 131       uint getFile() const { return reg.File; }
 132
 133       bool is2D() const { return reg.Dimension; }
 134
 135       bool isIndirect(int dim) const
 136       {
 137          return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
 138       }
 139
 140       int getIndex(int dim) const
 141       {
 142          return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
 143       }
 144
 145       unsigned int getMask() const { return reg.WriteMask; }
 146
 147       bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
 148
 149       SrcRegister getIndirect(int dim) const
 150       {
 151          assert(fdr && isIndirect(dim));
 152          if (dim)
 153             return SrcRegister(fdr->DimIndirect);
 154          return SrcRegister(fdr->Indirect);
 155       }
 156
 157    private:
 158       const struct tgsi_dst_register reg;
 159       const struct tgsi_full_dst_register *fdr;
 160    };
 161
 162    inline uint getOpcode() const { return insn->Instruction.Opcode; }
 163
 164    unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
 165    unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
 166
 167    // mask of used components of source s
 168    unsigned int srcMask(unsigned int s) const;
 169
 170    SrcRegister getSrc(unsigned int s) const
 171    {
 172       assert(s < srcCount());
 173       return SrcRegister(&insn->Src[s]);
 174    }
 175
 176    DstRegister getDst(unsigned int d) const
 177    {
 178       assert(d < dstCount());
 179       return DstRegister(&insn->Dst[d]);
 180    }
 181
 182    SrcRegister getTexOffset(unsigned int i) const
 183    {
 184       assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
 185       return SrcRegister(insn->TexOffsets[i]);
 186    }
 187
 188    unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
 189
 190    bool checkDstSrcAliasing() const;
 191
 192    inline nv50_ir::operation getOP() const {
 193       return translateOpcode(getOpcode()); }
 194
 195    nv50_ir::DataType inferSrcType() const;
 196    nv50_ir::DataType inferDstType() const;
 197
 198    nv50_ir::CondCode getSetCond() const;
 199
 200    nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
 201
 202    inline uint getLabel() { return insn->Label.Label; }
 203
 204    unsigned getSaturate() const { return insn->Instruction.Saturate; }
 205
 206    void print() const
 207    {
 208       tgsi_dump_instruction(insn, 1);
 209    }
 210
 211 private:
 212    const struct tgsi_full_instruction *insn;
 213 };
 214
 215 unsigned int Instruction::srcMask(unsigned int s) const
 216 {
 217    unsigned int mask = insn->Dst[0].Register.WriteMask;
 218
 219    switch (insn->Instruction.Opcode) {
 220    case TGSI_OPCODE_COS:
 221    case TGSI_OPCODE_SIN:
 222       return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
 223    case TGSI_OPCODE_DP2:
 224       return 0x3;
 225    case TGSI_OPCODE_DP3:
 226       return 0x7;
 227    case TGSI_OPCODE_DP4:
 228    case TGSI_OPCODE_DPH:
 229    case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
 230       return 0xf;
 231    case TGSI_OPCODE_DST:
 232       return mask & (s ? 0xa : 0x6);
 233    case TGSI_OPCODE_EX2:
 234    case TGSI_OPCODE_EXP:
 235    case TGSI_OPCODE_LG2:
 236    case TGSI_OPCODE_LOG:
 237    case TGSI_OPCODE_POW:
 238    case TGSI_OPCODE_RCP:
 239    case TGSI_OPCODE_RSQ:
 240    case TGSI_OPCODE_SCS:
 241       return 0x1;
 242    case TGSI_OPCODE_IF:
 243    case TGSI_OPCODE_UIF:
 244       return 0x1;
 245    case TGSI_OPCODE_LIT:
 246       return 0xb;
 247    case TGSI_OPCODE_TEX2:
 248    case TGSI_OPCODE_TXB2:
 249    case TGSI_OPCODE_TXL2:
 250       return (s == 0) ? 0xf : 0x3;
 251    case TGSI_OPCODE_TEX:
 252    case TGSI_OPCODE_TXB:
 253    case TGSI_OPCODE_TXD:
 254    case TGSI_OPCODE_TXL:
 255    case TGSI_OPCODE_TXP:
 256    case TGSI_OPCODE_LODQ:
 257    {
 258       const struct tgsi_instruction_texture *tex = &insn->Texture;
 259
 260       assert(insn->Instruction.Texture);
 261
 262       mask = 0x7;
 263       if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
 264           insn->Instruction.Opcode != TGSI_OPCODE_TXD)
 265          mask |= 0x8; /* bias, lod or proj */
 266
 267       switch (tex->Texture) {
 268       case TGSI_TEXTURE_1D:
 269          mask &= 0x9;
 270          break;
 271       case TGSI_TEXTURE_SHADOW1D:
 272          mask &= 0xd;
 273          break;
 274       case TGSI_TEXTURE_1D_ARRAY:
 275       case TGSI_TEXTURE_2D:
 276       case TGSI_TEXTURE_RECT:
 277          mask &= 0xb;
 278          break;
 279       case TGSI_TEXTURE_CUBE_ARRAY:
 280       case TGSI_TEXTURE_SHADOW2D_ARRAY:
 281       case TGSI_TEXTURE_SHADOWCUBE:
 282       case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
 283          mask |= 0x8;
 284          break;
 285       default:
 286          break;
 287       }
 288    }
 289       return mask;
 290    case TGSI_OPCODE_XPD:
 291    {
 292       unsigned int x = 0;
 293       if (mask & 1) x |= 0x6;
 294       if (mask & 2) x |= 0x5;
 295       if (mask & 4) x |= 0x3;
 296       return x;
 297    }
 298    case TGSI_OPCODE_D2I:
 299    case TGSI_OPCODE_D2U:
 300    case TGSI_OPCODE_D2F:
 301    case TGSI_OPCODE_DSLT:
 302    case TGSI_OPCODE_DSGE:
 303    case TGSI_OPCODE_DSEQ:
 304    case TGSI_OPCODE_DSNE:
 305       switch (util_bitcount(mask)) {
 306       case 1: return 0x3;
 307       case 2: return 0xf;
 308       default:
 309          assert(!"unexpected mask");
 310          return 0xf;
 311       }
 312    case TGSI_OPCODE_I2D:
 313    case TGSI_OPCODE_U2D:
 314    case TGSI_OPCODE_F2D: {
 315       unsigned int x = 0;
 316       if ((mask & 0x3) == 0x3)
 317          x |= 1;
 318       if ((mask & 0xc) == 0xc)
 319          x |= 2;
 320       return x;
 321    }
 322    default:
 323       break;
 324    }
 325
 326    return mask;
 327 }
 328
 329 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
 330 {
 331    nv50_ir::Modifier m(0);
 332
 333    if (reg.Absolute)
 334       m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
 335    if (reg.Negate)
 336       m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
 337    return m;
 338 }
 339
 340 static nv50_ir::DataFile translateFile(uint file)
 341 {
 342    switch (file) {
 343    case TGSI_FILE_CONSTANT:        return nv50_ir::FILE_MEMORY_CONST;
 344    case TGSI_FILE_INPUT:           return nv50_ir::FILE_SHADER_INPUT;
 345    case TGSI_FILE_OUTPUT:          return nv50_ir::FILE_SHADER_OUTPUT;
 346    case TGSI_FILE_TEMPORARY:       return nv50_ir::FILE_GPR;
 347    case TGSI_FILE_ADDRESS:         return nv50_ir::FILE_ADDRESS;
 348    case TGSI_FILE_PREDICATE:       return nv50_ir::FILE_PREDICATE;
 349    case TGSI_FILE_IMMEDIATE:       return nv50_ir::FILE_IMMEDIATE;
 350    case TGSI_FILE_SYSTEM_VALUE:    return nv50_ir::FILE_SYSTEM_VALUE;
 351    case TGSI_FILE_RESOURCE:        return nv50_ir::FILE_MEMORY_GLOBAL;
 352    case TGSI_FILE_SAMPLER:
 353    case TGSI_FILE_NULL:
 354    default:
 355       return nv50_ir::FILE_NULL;
 356    }
 357 }
 358
 359 static nv50_ir::SVSemantic translateSysVal(uint sysval)
 360 {
 361    switch (sysval) {
 362    case TGSI_SEMANTIC_FACE:       return nv50_ir::SV_FACE;
 363    case TGSI_SEMANTIC_PSIZE:      return nv50_ir::SV_POINT_SIZE;
 364    case TGSI_SEMANTIC_PRIMID:     return nv50_ir::SV_PRIMITIVE_ID;
 365    case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
 366    case TGSI_SEMANTIC_VERTEXID:   return nv50_ir::SV_VERTEX_ID;
 367    case TGSI_SEMANTIC_GRID_SIZE:  return nv50_ir::SV_NCTAID;
 368    case TGSI_SEMANTIC_BLOCK_ID:   return nv50_ir::SV_CTAID;
 369    case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
 370    case TGSI_SEMANTIC_THREAD_ID:  return nv50_ir::SV_TID;
 371    case TGSI_SEMANTIC_SAMPLEID:   return nv50_ir::SV_SAMPLE_INDEX;
 372    case TGSI_SEMANTIC_SAMPLEPOS:  return nv50_ir::SV_SAMPLE_POS;
 373    case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
 374    case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
 375    default:
 376       assert(0);
 377       return nv50_ir::SV_CLOCK;
 378    }
 379 }
 380
 381 #define NV50_IR_TEX_TARG_CASE(a, b) \
 382    case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
 383
 384 static nv50_ir::TexTarget translateTexture(uint tex)
 385 {
 386    switch (tex) {
 387    NV50_IR_TEX_TARG_CASE(1D, 1D);
 388    NV50_IR_TEX_TARG_CASE(2D, 2D);
 389    NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
 390    NV50_IR_TEX_TARG_CASE(3D, 3D);
 391    NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
 392    NV50_IR_TEX_TARG_CASE(RECT, RECT);
 393    NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
 394    NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
 395    NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
 396    NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
 397    NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
 398    NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
 399    NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
 400    NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
 401    NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
 402    NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
 403    NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
 404    NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
 405
 406    case TGSI_TEXTURE_UNKNOWN:
 407    default:
 408       assert(!"invalid texture target");
 409       return nv50_ir::TEX_TARGET_2D;
 410    }
 411 }
 412
 413 nv50_ir::DataType Instruction::inferSrcType() const
 414 {
 415    switch (getOpcode()) {
 416    case TGSI_OPCODE_UIF:
 417    case TGSI_OPCODE_AND:
 418    case TGSI_OPCODE_OR:
 419    case TGSI_OPCODE_XOR:
 420    case TGSI_OPCODE_NOT:
 421    case TGSI_OPCODE_U2F:
 422    case TGSI_OPCODE_U2D:
 423    case TGSI_OPCODE_UADD:
 424    case TGSI_OPCODE_UDIV:
 425    case TGSI_OPCODE_UMOD:
 426    case TGSI_OPCODE_UMAD:
 427    case TGSI_OPCODE_UMUL:
 428    case TGSI_OPCODE_UMUL_HI:
 429    case TGSI_OPCODE_UMAX:
 430    case TGSI_OPCODE_UMIN:
 431    case TGSI_OPCODE_USEQ:
 432    case TGSI_OPCODE_USGE:
 433    case TGSI_OPCODE_USLT:
 434    case TGSI_OPCODE_USNE:
 435    case TGSI_OPCODE_USHR:
 436    case TGSI_OPCODE_UCMP:
 437    case TGSI_OPCODE_ATOMUADD:
 438    case TGSI_OPCODE_ATOMXCHG:
 439    case TGSI_OPCODE_ATOMCAS:
 440    case TGSI_OPCODE_ATOMAND:
 441    case TGSI_OPCODE_ATOMOR:
 442    case TGSI_OPCODE_ATOMXOR:
 443    case TGSI_OPCODE_ATOMUMIN:
 444    case TGSI_OPCODE_ATOMUMAX:
 445    case TGSI_OPCODE_UBFE:
 446    case TGSI_OPCODE_UMSB:
 447       return nv50_ir::TYPE_U32;
 448    case TGSI_OPCODE_I2F:
 449    case TGSI_OPCODE_I2D:
 450    case TGSI_OPCODE_IDIV:
 451    case TGSI_OPCODE_IMUL_HI:
 452    case TGSI_OPCODE_IMAX:
 453    case TGSI_OPCODE_IMIN:
 454    case TGSI_OPCODE_IABS:
 455    case TGSI_OPCODE_INEG:
 456    case TGSI_OPCODE_ISGE:
 457    case TGSI_OPCODE_ISHR:
 458    case TGSI_OPCODE_ISLT:
 459    case TGSI_OPCODE_ISSG:
 460    case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
 461    case TGSI_OPCODE_MOD:
 462    case TGSI_OPCODE_UARL:
 463    case TGSI_OPCODE_ATOMIMIN:
 464    case TGSI_OPCODE_ATOMIMAX:
 465    case TGSI_OPCODE_IBFE:
 466    case TGSI_OPCODE_IMSB:
 467       return nv50_ir::TYPE_S32;
 468    case TGSI_OPCODE_D2F:
 469    case TGSI_OPCODE_D2I:
 470    case TGSI_OPCODE_D2U:
 471    case TGSI_OPCODE_DABS:
 472    case TGSI_OPCODE_DNEG:
 473    case TGSI_OPCODE_DADD:
 474    case TGSI_OPCODE_DMUL:
 475    case TGSI_OPCODE_DMAX:
 476    case TGSI_OPCODE_DMIN:
 477    case TGSI_OPCODE_DSLT:
 478    case TGSI_OPCODE_DSGE:
 479    case TGSI_OPCODE_DSEQ:
 480    case TGSI_OPCODE_DSNE:
 481    case TGSI_OPCODE_DRCP:
 482    case TGSI_OPCODE_DSQRT:
 483    case TGSI_OPCODE_DMAD:
 484    case TGSI_OPCODE_DFRAC:
 485    case TGSI_OPCODE_DRSQ:
 486    case TGSI_OPCODE_DTRUNC:
 487    case TGSI_OPCODE_DCEIL:
 488    case TGSI_OPCODE_DFLR:
 489    case TGSI_OPCODE_DROUND:
 490       return nv50_ir::TYPE_F64;
 491    default:
 492       return nv50_ir::TYPE_F32;
 493    }
 494 }
 495
 496 nv50_ir::DataType Instruction::inferDstType() const
 497 {
 498    switch (getOpcode()) {
 499    case TGSI_OPCODE_D2U:
 500    case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
 501    case TGSI_OPCODE_D2I:
 502    case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
 503    case TGSI_OPCODE_FSEQ:
 504    case TGSI_OPCODE_FSGE:
 505    case TGSI_OPCODE_FSLT:
 506    case TGSI_OPCODE_FSNE:
 507    case TGSI_OPCODE_DSEQ:
 508    case TGSI_OPCODE_DSGE:
 509    case TGSI_OPCODE_DSLT:
 510    case TGSI_OPCODE_DSNE:
 511       return nv50_ir::TYPE_U32;
 512    case TGSI_OPCODE_I2F:
 513    case TGSI_OPCODE_U2F:
 514    case TGSI_OPCODE_D2F:
 515       return nv50_ir::TYPE_F32;
 516    case TGSI_OPCODE_I2D:
 517    case TGSI_OPCODE_U2D:
 518    case TGSI_OPCODE_F2D:
 519       return nv50_ir::TYPE_F64;
 520    default:
 521       return inferSrcType();
 522    }
 523 }
 524
 525 nv50_ir::CondCode Instruction::getSetCond() const
 526 {
 527    using namespace nv50_ir;
 528
 529    switch (getOpcode()) {
 530    case TGSI_OPCODE_SLT:
 531    case TGSI_OPCODE_ISLT:
 532    case TGSI_OPCODE_USLT:
 533    case TGSI_OPCODE_FSLT:
 534    case TGSI_OPCODE_DSLT:
 535       return CC_LT;
 536    case TGSI_OPCODE_SLE:
 537       return CC_LE;
 538    case TGSI_OPCODE_SGE:
 539    case TGSI_OPCODE_ISGE:
 540    case TGSI_OPCODE_USGE:
 541    case TGSI_OPCODE_FSGE:
 542    case TGSI_OPCODE_DSGE:
 543       return CC_GE;
 544    case TGSI_OPCODE_SGT:
 545       return CC_GT;
 546    case TGSI_OPCODE_SEQ:
 547    case TGSI_OPCODE_USEQ:
 548    case TGSI_OPCODE_FSEQ:
 549    case TGSI_OPCODE_DSEQ:
 550       return CC_EQ;
 551    case TGSI_OPCODE_SNE:
 552    case TGSI_OPCODE_FSNE:
 553    case TGSI_OPCODE_DSNE:
 554       return CC_NEU;
 555    case TGSI_OPCODE_USNE:
 556       return CC_NE;
 557    default:
 558       return CC_ALWAYS;
 559    }
 560 }
 561
 562 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
 563
 564 static nv50_ir::operation translateOpcode(uint opcode)
 565 {
 566    switch (opcode) {
 567    NV50_IR_OPCODE_CASE(ARL, SHL);
 568    NV50_IR_OPCODE_CASE(MOV, MOV);
 569
 570    NV50_IR_OPCODE_CASE(RCP, RCP);
 571    NV50_IR_OPCODE_CASE(RSQ, RSQ);
 572
 573    NV50_IR_OPCODE_CASE(MUL, MUL);
 574    NV50_IR_OPCODE_CASE(ADD, ADD);
 575
 576    NV50_IR_OPCODE_CASE(MIN, MIN);
 577    NV50_IR_OPCODE_CASE(MAX, MAX);
 578    NV50_IR_OPCODE_CASE(SLT, SET);
 579    NV50_IR_OPCODE_CASE(SGE, SET);
 580    NV50_IR_OPCODE_CASE(MAD, MAD);
 581    NV50_IR_OPCODE_CASE(SUB, SUB);
 582
 583    NV50_IR_OPCODE_CASE(FLR, FLOOR);
 584    NV50_IR_OPCODE_CASE(ROUND, CVT);
 585    NV50_IR_OPCODE_CASE(EX2, EX2);
 586    NV50_IR_OPCODE_CASE(LG2, LG2);
 587    NV50_IR_OPCODE_CASE(POW, POW);
 588
 589    NV50_IR_OPCODE_CASE(ABS, ABS);
 590
 591    NV50_IR_OPCODE_CASE(COS, COS);
 592    NV50_IR_OPCODE_CASE(DDX, DFDX);
 593    NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
 594    NV50_IR_OPCODE_CASE(DDY, DFDY);
 595    NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
 596    NV50_IR_OPCODE_CASE(KILL, DISCARD);
 597
 598    NV50_IR_OPCODE_CASE(SEQ, SET);
 599    NV50_IR_OPCODE_CASE(SGT, SET);
 600    NV50_IR_OPCODE_CASE(SIN, SIN);
 601    NV50_IR_OPCODE_CASE(SLE, SET);
 602    NV50_IR_OPCODE_CASE(SNE, SET);
 603    NV50_IR_OPCODE_CASE(TEX, TEX);
 604    NV50_IR_OPCODE_CASE(TXD, TXD);
 605    NV50_IR_OPCODE_CASE(TXP, TEX);
 606
 607    NV50_IR_OPCODE_CASE(CAL, CALL);
 608    NV50_IR_OPCODE_CASE(RET, RET);
 609    NV50_IR_OPCODE_CASE(CMP, SLCT);
 610
 611    NV50_IR_OPCODE_CASE(TXB, TXB);
 612
 613    NV50_IR_OPCODE_CASE(DIV, DIV);
 614
 615    NV50_IR_OPCODE_CASE(TXL, TXL);
 616
 617    NV50_IR_OPCODE_CASE(CEIL, CEIL);
 618    NV50_IR_OPCODE_CASE(I2F, CVT);
 619    NV50_IR_OPCODE_CASE(NOT, NOT);
 620    NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
 621    NV50_IR_OPCODE_CASE(SHL, SHL);
 622
 623    NV50_IR_OPCODE_CASE(AND, AND);
 624    NV50_IR_OPCODE_CASE(OR, OR);
 625    NV50_IR_OPCODE_CASE(MOD, MOD);
 626    NV50_IR_OPCODE_CASE(XOR, XOR);
 627    NV50_IR_OPCODE_CASE(SAD, SAD);
 628    NV50_IR_OPCODE_CASE(TXF, TXF);
 629    NV50_IR_OPCODE_CASE(TXQ, TXQ);
 630    NV50_IR_OPCODE_CASE(TG4, TXG);
 631    NV50_IR_OPCODE_CASE(LODQ, TXLQ);
 632
 633    NV50_IR_OPCODE_CASE(EMIT, EMIT);
 634    NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
 635
 636    NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
 637
 638    NV50_IR_OPCODE_CASE(F2I, CVT);
 639    NV50_IR_OPCODE_CASE(FSEQ, SET);
 640    NV50_IR_OPCODE_CASE(FSGE, SET);
 641    NV50_IR_OPCODE_CASE(FSLT, SET);
 642    NV50_IR_OPCODE_CASE(FSNE, SET);
 643    NV50_IR_OPCODE_CASE(IDIV, DIV);
 644    NV50_IR_OPCODE_CASE(IMAX, MAX);
 645    NV50_IR_OPCODE_CASE(IMIN, MIN);
 646    NV50_IR_OPCODE_CASE(IABS, ABS);
 647    NV50_IR_OPCODE_CASE(INEG, NEG);
 648    NV50_IR_OPCODE_CASE(ISGE, SET);
 649    NV50_IR_OPCODE_CASE(ISHR, SHR);
 650    NV50_IR_OPCODE_CASE(ISLT, SET);
 651    NV50_IR_OPCODE_CASE(F2U, CVT);
 652    NV50_IR_OPCODE_CASE(U2F, CVT);
 653    NV50_IR_OPCODE_CASE(UADD, ADD);
 654    NV50_IR_OPCODE_CASE(UDIV, DIV);
 655    NV50_IR_OPCODE_CASE(UMAD, MAD);
 656    NV50_IR_OPCODE_CASE(UMAX, MAX);
 657    NV50_IR_OPCODE_CASE(UMIN, MIN);
 658    NV50_IR_OPCODE_CASE(UMOD, MOD);
 659    NV50_IR_OPCODE_CASE(UMUL, MUL);
 660    NV50_IR_OPCODE_CASE(USEQ, SET);
 661    NV50_IR_OPCODE_CASE(USGE, SET);
 662    NV50_IR_OPCODE_CASE(USHR, SHR);
 663    NV50_IR_OPCODE_CASE(USLT, SET);
 664    NV50_IR_OPCODE_CASE(USNE, SET);
 665
 666    NV50_IR_OPCODE_CASE(DABS, ABS);
 667    NV50_IR_OPCODE_CASE(DNEG, NEG);
 668    NV50_IR_OPCODE_CASE(DADD, ADD);
 669    NV50_IR_OPCODE_CASE(DMUL, MUL);
 670    NV50_IR_OPCODE_CASE(DMAX, MAX);
 671    NV50_IR_OPCODE_CASE(DMIN, MIN);
 672    NV50_IR_OPCODE_CASE(DSLT, SET);
 673    NV50_IR_OPCODE_CASE(DSGE, SET);
 674    NV50_IR_OPCODE_CASE(DSEQ, SET);
 675    NV50_IR_OPCODE_CASE(DSNE, SET);
 676    NV50_IR_OPCODE_CASE(DRCP, RCP);
 677    NV50_IR_OPCODE_CASE(DSQRT, SQRT);
 678    NV50_IR_OPCODE_CASE(DMAD, MAD);
 679    NV50_IR_OPCODE_CASE(D2I, CVT);
 680    NV50_IR_OPCODE_CASE(D2U, CVT);
 681    NV50_IR_OPCODE_CASE(I2D, CVT);
 682    NV50_IR_OPCODE_CASE(U2D, CVT);
 683    NV50_IR_OPCODE_CASE(DRSQ, RSQ);
 684    NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
 685    NV50_IR_OPCODE_CASE(DCEIL, CEIL);
 686    NV50_IR_OPCODE_CASE(DFLR, FLOOR);
 687    NV50_IR_OPCODE_CASE(DROUND, CVT);
 688
 689    NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
 690    NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
 691
 692    NV50_IR_OPCODE_CASE(SAMPLE, TEX);
 693    NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
 694    NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
 695    NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
 696    NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
 697    NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
 698    NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
 699    NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
 700    NV50_IR_OPCODE_CASE(GATHER4, TXG);
 701    NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
 702
 703    NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
 704    NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
 705    NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
 706    NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
 707    NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
 708    NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
 709    NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
 710    NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
 711    NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
 712    NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
 713
 714    NV50_IR_OPCODE_CASE(TEX2, TEX);
 715    NV50_IR_OPCODE_CASE(TXB2, TXB);
 716    NV50_IR_OPCODE_CASE(TXL2, TXL);
 717
 718    NV50_IR_OPCODE_CASE(IBFE, EXTBF);
 719    NV50_IR_OPCODE_CASE(UBFE, EXTBF);
 720    NV50_IR_OPCODE_CASE(BFI, INSBF);
 721    NV50_IR_OPCODE_CASE(BREV, EXTBF);
 722    NV50_IR_OPCODE_CASE(POPC, POPCNT);
 723    NV50_IR_OPCODE_CASE(LSB, BFIND);
 724    NV50_IR_OPCODE_CASE(IMSB, BFIND);
 725    NV50_IR_OPCODE_CASE(UMSB, BFIND);
 726
 727    NV50_IR_OPCODE_CASE(END, EXIT);
 728
 729    default:
 730       return nv50_ir::OP_NOP;
 731    }
 732 }
 733
 734 static uint16_t opcodeToSubOp(uint opcode)
 735 {
 736    switch (opcode) {
 737    case TGSI_OPCODE_LFENCE:   return NV50_IR_SUBOP_MEMBAR(L, GL);
 738    case TGSI_OPCODE_SFENCE:   return NV50_IR_SUBOP_MEMBAR(S, GL);
 739    case TGSI_OPCODE_MFENCE:   return NV50_IR_SUBOP_MEMBAR(M, GL);
 740    case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
 741    case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
 742    case TGSI_OPCODE_ATOMCAS:  return NV50_IR_SUBOP_ATOM_CAS;
 743    case TGSI_OPCODE_ATOMAND:  return NV50_IR_SUBOP_ATOM_AND;
 744    case TGSI_OPCODE_ATOMOR:   return NV50_IR_SUBOP_ATOM_OR;
 745    case TGSI_OPCODE_ATOMXOR:  return NV50_IR_SUBOP_ATOM_XOR;
 746    case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
 747    case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
 748    case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
 749    case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
 750    case TGSI_OPCODE_IMUL_HI:
 751    case TGSI_OPCODE_UMUL_HI:
 752       return NV50_IR_SUBOP_MUL_HIGH;
 753    default:
 754       return 0;
 755    }
 756 }
 757
 758 bool Instruction::checkDstSrcAliasing() const
 759 {
 760    if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
 761       return false;
 762
 763    for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
 764       if (insn->Src[s].Register.File == TGSI_FILE_NULL)
 765          break;
 766       if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
 767           insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
 768          return true;
 769    }
 770    return false;
 771 }
 772
 773 class Source
 774 {
 775 public:
 776    Source(struct nv50_ir_prog_info *);
 777    ~Source();
 778
 779 public:
 780    bool scanSource();
 781    unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
 782
 783 public:
 784    struct tgsi_shader_info scan;
 785    struct tgsi_full_instruction *insns;
 786    const struct tgsi_token *tokens;
 787    struct nv50_ir_prog_info *info;
 788
 789    nv50_ir::DynArray tempArrays;
 790    nv50_ir::DynArray immdArrays;
 791
 792    typedef nv50_ir::BuildUtil::Location Location;
 793    // these registers are per-subroutine, cannot be used for parameter passing
 794    std::set<Location> locals;
 795
 796    bool mainTempsInLMem;
 797
 798    int clipVertexOutput;
 799
 800    struct TextureView {
 801       uint8_t target; // TGSI_TEXTURE_*
 802    };
 803    std::vector<TextureView> textureViews;
 804
 805    struct Resource {
 806       uint8_t target; // TGSI_TEXTURE_*
 807       bool raw;
 808       uint8_t slot; // $surface index
 809    };
 810    std::vector<Resource> resources;
 811
 812 private:
 813    int inferSysValDirection(unsigned sn) const;
 814    bool scanDeclaration(const struct tgsi_full_declaration *);
 815    bool scanInstruction(const struct tgsi_full_instruction *);
 816    void scanProperty(const struct tgsi_full_property *);
 817    void scanImmediate(const struct tgsi_full_immediate *);
 818
 819    inline bool isEdgeFlagPassthrough(const Instruction&) const;
 820 };
 821
 822 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
 823 {
 824    tokens = (const struct tgsi_token *)info->bin.source;
 825
 826    if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
 827       tgsi_dump(tokens, 0);
 828
 829    mainTempsInLMem = FALSE;
 830 }
 831
 832 Source::~Source()
 833 {
 834    if (insns)
 835       FREE(insns);
 836
 837    if (info->immd.data)
 838       FREE(info->immd.data);
 839    if (info->immd.type)
 840       FREE(info->immd.type);
 841 }
 842
 843 bool Source::scanSource()
 844 {
 845    unsigned insnCount = 0;
 846    struct tgsi_parse_context parse;
 847
 848    tgsi_scan_shader(tokens, &scan);
 849
 850    insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
 851                                                   sizeof(insns[0]));
 852    if (!insns)
 853       return false;
 854
 855    clipVertexOutput = -1;
 856
 857    textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
 858    resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
 859
 860    info->immd.bufSize = 0;
 861
 862    info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
 863    info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
 864    info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
 865
 866    if (info->type == PIPE_SHADER_FRAGMENT) {
 867       info->prop.fp.writesDepth = scan.writes_z;
 868       info->prop.fp.usesDiscard = scan.uses_kill;
 869    } else
 870    if (info->type == PIPE_SHADER_GEOMETRY) {
 871       info->prop.gp.instanceCount = 1; // default value
 872    }
 873
 874    info->io.viewportId = -1;
 875
 876    info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
 877    info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
 878
 879    tgsi_parse_init(&parse, tokens);
 880    while (!tgsi_parse_end_of_tokens(&parse)) {
 881       tgsi_parse_token(&parse);
 882
 883       switch (parse.FullToken.Token.Type) {
 884       case TGSI_TOKEN_TYPE_IMMEDIATE:
 885          scanImmediate(&parse.FullToken.FullImmediate);
 886          break;
 887       case TGSI_TOKEN_TYPE_DECLARATION:
 888          scanDeclaration(&parse.FullToken.FullDeclaration);
 889          break;
 890       case TGSI_TOKEN_TYPE_INSTRUCTION:
 891          insns[insnCount++] = parse.FullToken.FullInstruction;
 892          scanInstruction(&parse.FullToken.FullInstruction);
 893          break;
 894       case TGSI_TOKEN_TYPE_PROPERTY:
 895          scanProperty(&parse.FullToken.FullProperty);
 896          break;
 897       default:
 898          INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
 899          break;
 900       }
 901    }
 902    tgsi_parse_free(&parse);
 903
 904    if (mainTempsInLMem)
 905       info->bin.tlsSpace += (scan.file_max[TGSI_FILE_TEMPORARY] + 1) * 16;
 906
 907    if (info->io.genUserClip > 0) {
 908       info->io.clipDistanceMask = (1 << info->io.genUserClip) - 1;
 909
 910       const unsigned int nOut = (info->io.genUserClip + 3) / 4;
 911
 912       for (unsigned int n = 0; n < nOut; ++n) {
 913          unsigned int i = info->numOutputs++;
 914          info->out[i].id = i;
 915          info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
 916          info->out[i].si = n;
 917          info->out[i].mask = info->io.clipDistanceMask >> (n * 4);
 918       }
 919    }
 920
 921    return info->assignSlots(info) == 0;
 922 }
 923
 924 void Source::scanProperty(const struct tgsi_full_property *prop)
 925 {
 926    switch (prop->Property.PropertyName) {
 927    case TGSI_PROPERTY_GS_OUTPUT_PRIM:
 928       info->prop.gp.outputPrim = prop->u[0].Data;
 929       break;
 930    case TGSI_PROPERTY_GS_INPUT_PRIM:
 931       info->prop.gp.inputPrim = prop->u[0].Data;
 932       break;
 933    case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
 934       info->prop.gp.maxVertices = prop->u[0].Data;
 935       break;
 936    case TGSI_PROPERTY_GS_INVOCATIONS:
 937       info->prop.gp.instanceCount = prop->u[0].Data;
 938       break;
 939    case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
 940       info->prop.fp.separateFragData = TRUE;
 941       break;
 942    case TGSI_PROPERTY_FS_COORD_ORIGIN:
 943    case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
 944       // we don't care
 945       break;
 946    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
 947       info->io.genUserClip = -1;
 948       break;
 949    default:
 950       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
 951       break;
 952    }
 953 }
 954
 955 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
 956 {
 957    const unsigned n = info->immd.count++;
 958
 959    assert(n < scan.immediate_count);
 960
 961    for (int c = 0; c < 4; ++c)
 962       info->immd.data[n * 4 + c] = imm->u[c].Uint;
 963
 964    info->immd.type[n] = imm->Immediate.DataType;
 965 }
 966
 967 int Source::inferSysValDirection(unsigned sn) const
 968 {
 969    switch (sn) {
 970    case TGSI_SEMANTIC_INSTANCEID:
 971    case TGSI_SEMANTIC_VERTEXID:
 972       return 1;
 973    case TGSI_SEMANTIC_LAYER:
 974 #if 0
 975    case TGSI_SEMANTIC_VIEWPORTINDEX:
 976       return 0;
 977 #endif
 978    case TGSI_SEMANTIC_PRIMID:
 979       return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
 980    default:
 981       return 0;
 982    }
 983 }
 984
 985 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
 986 {
 987    unsigned i, c;
 988    unsigned sn = TGSI_SEMANTIC_GENERIC;
 989    unsigned si = 0;
 990    const unsigned first = decl->Range.First, last = decl->Range.Last;
 991
 992    if (decl->Declaration.Semantic) {
 993       sn = decl->Semantic.Name;
 994       si = decl->Semantic.Index;
 995    }
 996
 997    if (decl->Declaration.Local) {
 998       for (i = first; i <= last; ++i) {
 999          for (c = 0; c < 4; ++c) {
1000             locals.insert(
1001                Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1002          }
1003       }
1004    }
1005
1006    switch (decl->Declaration.File) {
1007    case TGSI_FILE_INPUT:
1008       if (info->type == PIPE_SHADER_VERTEX) {
1009          // all vertex attributes are equal
1010          for (i = first; i <= last; ++i) {
1011             info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1012             info->in[i].si = i;
1013          }
1014       } else {
1015          for (i = first; i <= last; ++i, ++si) {
1016             info->in[i].id = i;
1017             info->in[i].sn = sn;
1018             info->in[i].si = si;
1019             if (info->type == PIPE_SHADER_FRAGMENT) {
1020                // translate interpolation mode
1021                switch (decl->Interp.Interpolate) {
1022                case TGSI_INTERPOLATE_CONSTANT:
1023                   info->in[i].flat = 1;
1024                   break;
1025                case TGSI_INTERPOLATE_COLOR:
1026                   info->in[i].sc = 1;
1027                   break;
1028                case TGSI_INTERPOLATE_LINEAR:
1029                   info->in[i].linear = 1;
1030                   break;
1031                default:
1032                   break;
1033                }
1034                if (decl->Interp.Location || info->io.sampleInterp)
1035                   info->in[i].centroid = 1;
1036             }
1037          }
1038       }
1039       break;
1040    case TGSI_FILE_OUTPUT:
1041       for (i = first; i <= last; ++i, ++si) {
1042          switch (sn) {
1043          case TGSI_SEMANTIC_POSITION:
1044             if (info->type == PIPE_SHADER_FRAGMENT)
1045                info->io.fragDepth = i;
1046             else
1047             if (clipVertexOutput < 0)
1048                clipVertexOutput = i;
1049             break;
1050          case TGSI_SEMANTIC_COLOR:
1051             if (info->type == PIPE_SHADER_FRAGMENT)
1052                info->prop.fp.numColourResults++;
1053             break;
1054          case TGSI_SEMANTIC_EDGEFLAG:
1055             info->io.edgeFlagOut = i;
1056             break;
1057          case TGSI_SEMANTIC_CLIPVERTEX:
1058             clipVertexOutput = i;
1059             break;
1060          case TGSI_SEMANTIC_CLIPDIST:
1061             info->io.clipDistanceMask |=
1062                decl->Declaration.UsageMask << (si * 4);
1063             info->io.genUserClip = -1;
1064             break;
1065          case TGSI_SEMANTIC_SAMPLEMASK:
1066             info->io.sampleMask = i;
1067             break;
1068          case TGSI_SEMANTIC_VIEWPORT_INDEX:
1069             info->io.viewportId = i;
1070             break;
1071          default:
1072             break;
1073          }
1074          info->out[i].id = i;
1075          info->out[i].sn = sn;
1076          info->out[i].si = si;
1077       }
1078       break;
1079    case TGSI_FILE_SYSTEM_VALUE:
1080       switch (sn) {
1081       case TGSI_SEMANTIC_INSTANCEID:
1082          info->io.instanceId = first;
1083          break;
1084       case TGSI_SEMANTIC_VERTEXID:
1085          info->io.vertexId = first;
1086          break;
1087       default:
1088          break;
1089       }
1090       for (i = first; i <= last; ++i, ++si) {
1091          info->sv[i].sn = sn;
1092          info->sv[i].si = si;
1093          info->sv[i].input = inferSysValDirection(sn);
1094       }
1095       break;
1096    case TGSI_FILE_RESOURCE:
1097       for (i = first; i <= last; ++i) {
1098          resources[i].target = decl->Resource.Resource;
1099          resources[i].raw = decl->Resource.Raw;
1100          resources[i].slot = i;
1101       }
1102       break;
1103    case TGSI_FILE_SAMPLER_VIEW:
1104       for (i = first; i <= last; ++i)
1105          textureViews[i].target = decl->SamplerView.Resource;
1106       break;
1107    case TGSI_FILE_NULL:
1108    case TGSI_FILE_TEMPORARY:
1109    case TGSI_FILE_ADDRESS:
1110    case TGSI_FILE_CONSTANT:
1111    case TGSI_FILE_IMMEDIATE:
1112    case TGSI_FILE_PREDICATE:
1113    case TGSI_FILE_SAMPLER:
1114       break;
1115    default:
1116       ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1117       return false;
1118    }
1119    return true;
1120 }
1121
1122 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1123 {
1124    return insn.getOpcode() == TGSI_OPCODE_MOV &&
1125       insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1126       insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1127 }
1128
1129 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1130 {
1131    Instruction insn(inst);
1132
1133    if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1134       info->numBarriers = 1;
1135
1136    if (insn.dstCount()) {
1137       if (insn.getDst(0).getFile() == TGSI_FILE_OUTPUT) {
1138          Instruction::DstRegister dst = insn.getDst(0);
1139
1140          if (dst.isIndirect(0))
1141             for (unsigned i = 0; i < info->numOutputs; ++i)
1142                info->out[i].mask = 0xf;
1143          else
1144             info->out[dst.getIndex(0)].mask |= dst.getMask();
1145
1146          if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1147              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1148              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1149              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1150              info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1151             info->out[dst.getIndex(0)].mask &= 1;
1152
1153          if (isEdgeFlagPassthrough(insn))
1154             info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1155       } else
1156       if (insn.getDst(0).getFile() == TGSI_FILE_TEMPORARY) {
1157          if (insn.getDst(0).isIndirect(0))
1158             mainTempsInLMem = TRUE;
1159       }
1160    }
1161
1162    for (unsigned s = 0; s < insn.srcCount(); ++s) {
1163       Instruction::SrcRegister src = insn.getSrc(s);
1164       if (src.getFile() == TGSI_FILE_TEMPORARY) {
1165          if (src.isIndirect(0))
1166             mainTempsInLMem = TRUE;
1167       } else
1168       if (src.getFile() == TGSI_FILE_RESOURCE) {
1169          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
1170             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1171                0x1 : 0x2;
1172       }
1173       if (src.getFile() != TGSI_FILE_INPUT)
1174          continue;
1175       unsigned mask = insn.srcMask(s);
1176
1177       if (src.isIndirect(0)) {
1178          for (unsigned i = 0; i < info->numInputs; ++i)
1179             info->in[i].mask = 0xf;
1180       } else {
1181          const int i = src.getIndex(0);
1182          for (unsigned c = 0; c < 4; ++c) {
1183             if (!(mask & (1 << c)))
1184                continue;
1185             int k = src.getSwizzle(c);
1186             if (k <= TGSI_SWIZZLE_W)
1187                info->in[i].mask |= 1 << k;
1188          }
1189          switch (info->in[i].sn) {
1190          case TGSI_SEMANTIC_PSIZE:
1191          case TGSI_SEMANTIC_PRIMID:
1192          case TGSI_SEMANTIC_FOG:
1193             info->in[i].mask &= 0x1;
1194             break;
1195          case TGSI_SEMANTIC_PCOORD:
1196             info->in[i].mask &= 0x3;
1197             break;
1198          default:
1199             break;
1200          }
1201       }
1202    }
1203    return true;
1204 }
1205
1206 nv50_ir::TexInstruction::Target
1207 Instruction::getTexture(const tgsi::Source *code, int s) const
1208 {
1209    // XXX: indirect access
1210    unsigned int r;
1211
1212    switch (getSrc(s).getFile()) {
1213    case TGSI_FILE_RESOURCE:
1214       r = getSrc(s).getIndex(0);
1215       return translateTexture(code->resources.at(r).target);
1216    case TGSI_FILE_SAMPLER_VIEW:
1217       r = getSrc(s).getIndex(0);
1218       return translateTexture(code->textureViews.at(r).target);
1219    default:
1220       return translateTexture(insn->Texture.Texture);
1221    }
1222 }
1223
1224 } // namespace tgsi
1225
1226 namespace {
1227
1228 using namespace nv50_ir;
1229
1230 class Converter : public BuildUtil
1231 {
1232 public:
1233    Converter(Program *, const tgsi::Source *);
1234    ~Converter();
1235
1236    bool run();
1237
1238 private:
1239    struct Subroutine
1240    {
1241       Subroutine(Function *f) : f(f) { }
1242       Function *f;
1243       ValueMap values;
1244    };
1245
1246    Value *shiftAddress(Value *);
1247    Value *getVertexBase(int s);
1248    DataArray *getArrayForFile(unsigned file, int idx);
1249    Value *fetchSrc(int s, int c);
1250    Value *acquireDst(int d, int c);
1251    void storeDst(int d, int c, Value *);
1252
1253    Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1254    void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1255                  Value *val, Value *ptr);
1256
1257    Value *applySrcMod(Value *, int s, int c);
1258
1259    Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1260    Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1261    Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1262
1263    bool handleInstruction(const struct tgsi_full_instruction *);
1264    void exportOutputs();
1265    inline Subroutine *getSubroutine(unsigned ip);
1266    inline Subroutine *getSubroutine(Function *);
1267    inline bool isEndOfSubroutine(uint ip);
1268
1269    void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1270
1271    // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1272    void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1273    void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1274    void handleTXF(Value *dst0[4], int R, int L_M);
1275    void handleTXQ(Value *dst0[4], enum TexQuery);
1276    void handleLIT(Value *dst0[4]);
1277    void handleUserClipPlanes();
1278
1279    Symbol *getResourceBase(int r);
1280    void getResourceCoords(std::vector<Value *>&, int r, int s);
1281
1282    void handleLOAD(Value *dst0[4]);
1283    void handleSTORE();
1284    void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1285
1286    void handleINTERP(Value *dst0[4]);
1287
1288    Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1289
1290    void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1291
1292    Value *buildDot(int dim);
1293
1294    class BindArgumentsPass : public Pass {
1295    public:
1296       BindArgumentsPass(Converter &conv) : conv(conv) { }
1297
1298    private:
1299       Converter &conv;
1300       Subroutine *sub;
1301
1302       inline const Location *getValueLocation(Subroutine *, Value *);
1303
1304       template<typename T> inline void
1305       updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1306                      T (Function::*proto));
1307
1308       template<typename T> inline void
1309       updatePrototype(BitSet *set, void (Function::*updateSet)(),
1310                       T (Function::*proto));
1311
1312    protected:
1313       bool visit(Function *);
1314       bool visit(BasicBlock *bb) { return false; }
1315    };
1316
1317 private:
1318    const struct tgsi::Source *code;
1319    const struct nv50_ir_prog_info *info;
1320
1321    struct {
1322       std::map<unsigned, Subroutine> map;
1323       Subroutine *cur;
1324    } sub;
1325
1326    uint ip; // instruction pointer
1327
1328    tgsi::Instruction tgsi;
1329
1330    DataType dstTy;
1331    DataType srcTy;
1332
1333    DataArray tData; // TGSI_FILE_TEMPORARY
1334    DataArray aData; // TGSI_FILE_ADDRESS
1335    DataArray pData; // TGSI_FILE_PREDICATE
1336    DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1337
1338    Value *zero;
1339    Value *fragCoord[4];
1340    Value *clipVtx[4];
1341
1342    Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1343    uint8_t vtxBaseValid;
1344
1345    Stack condBBs;  // fork BB, then else clause BB
1346    Stack joinBBs;  // fork BB, for inserting join ops on ENDIF
1347    Stack loopBBs;  // loop headers
1348    Stack breakBBs; // end of / after loop
1349
1350    Value *viewport;
1351 };
1352
1353 Symbol *
1354 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1355 {
1356    const int swz = src.getSwizzle(c);
1357
1358    return makeSym(src.getFile(),
1359                   src.is2D() ? src.getIndex(1) : 0,
1360                   src.isIndirect(0) ? -1 : src.getIndex(0), swz,
1361                   src.getIndex(0) * 16 + swz * 4);
1362 }
1363
1364 Symbol *
1365 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1366 {
1367    return makeSym(dst.getFile(),
1368                   dst.is2D() ? dst.getIndex(1) : 0,
1369                   dst.isIndirect(0) ? -1 : dst.getIndex(0), c,
1370                   dst.getIndex(0) * 16 + c * 4);
1371 }
1372
1373 Symbol *
1374 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1375 {
1376    Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1377
1378    sym->reg.fileIndex = fileIdx;
1379
1380    if (idx >= 0) {
1381       if (sym->reg.file == FILE_SHADER_INPUT)
1382          sym->setOffset(info->in[idx].slot[c] * 4);
1383       else
1384       if (sym->reg.file == FILE_SHADER_OUTPUT)
1385          sym->setOffset(info->out[idx].slot[c] * 4);
1386       else
1387       if (sym->reg.file == FILE_SYSTEM_VALUE)
1388          sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1389       else
1390          sym->setOffset(address);
1391    } else {
1392       sym->setOffset(address);
1393    }
1394    return sym;
1395 }
1396
1397 static inline uint8_t
1398 translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1399 {
1400    uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1401
1402    if (var->flat)
1403       mode = NV50_IR_INTERP_FLAT;
1404    else
1405    if (var->linear)
1406       mode = NV50_IR_INTERP_LINEAR;
1407    else
1408    if (var->sc)
1409       mode = NV50_IR_INTERP_SC;
1410
1411    op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1412       ? OP_PINTERP : OP_LINTERP;
1413
1414    if (var->centroid)
1415       mode |= NV50_IR_INTERP_CENTROID;
1416
1417    return mode;
1418 }
1419
1420 Value *
1421 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1422 {
1423    operation op;
1424
1425    // XXX: no way to know interpolation mode if we don't know what's accessed
1426    const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1427                                                       src.getIndex(0)], op);
1428
1429    Instruction *insn = new_Instruction(func, op, TYPE_F32);
1430
1431    insn->setDef(0, getScratch());
1432    insn->setSrc(0, srcToSym(src, c));
1433    if (op == OP_PINTERP)
1434       insn->setSrc(1, fragCoord[3]);
1435    if (ptr)
1436       insn->setIndirect(0, 0, ptr);
1437
1438    insn->setInterpolate(mode);
1439
1440    bb->insertTail(insn);
1441    return insn->getDef(0);
1442 }
1443
1444 Value *
1445 Converter::applySrcMod(Value *val, int s, int c)
1446 {
1447    Modifier m = tgsi.getSrc(s).getMod(c);
1448    DataType ty = tgsi.inferSrcType();
1449
1450    if (m & Modifier(NV50_IR_MOD_ABS))
1451       val = mkOp1v(OP_ABS, ty, getScratch(), val);
1452
1453    if (m & Modifier(NV50_IR_MOD_NEG))
1454       val = mkOp1v(OP_NEG, ty, getScratch(), val);
1455
1456    return val;
1457 }
1458
1459 Value *
1460 Converter::getVertexBase(int s)
1461 {
1462    assert(s < 5);
1463    if (!(vtxBaseValid & (1 << s))) {
1464       const int index = tgsi.getSrc(s).getIndex(1);
1465       Value *rel = NULL;
1466       if (tgsi.getSrc(s).isIndirect(1))
1467          rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1468       vtxBaseValid |= 1 << s;
1469       vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1470                           mkImm(index), rel);
1471    }
1472    return vtxBase[s];
1473 }
1474
1475 Value *
1476 Converter::fetchSrc(int s, int c)
1477 {
1478    Value *res;
1479    Value *ptr = NULL, *dimRel = NULL;
1480
1481    tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1482
1483    if (src.isIndirect(0))
1484       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1485
1486    if (src.is2D()) {
1487       switch (src.getFile()) {
1488       case TGSI_FILE_INPUT:
1489          dimRel = getVertexBase(s);
1490          break;
1491       case TGSI_FILE_CONSTANT:
1492          // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1493          if (src.isIndirect(1))
1494             dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1495          break;
1496       default:
1497          break;
1498       }
1499    }
1500
1501    res = fetchSrc(src, c, ptr);
1502
1503    if (dimRel)
1504       res->getInsn()->setIndirect(0, 1, dimRel);
1505
1506    return applySrcMod(res, s, c);
1507 }
1508
1509 Converter::DataArray *
1510 Converter::getArrayForFile(unsigned file, int idx)
1511 {
1512    switch (file) {
1513    case TGSI_FILE_TEMPORARY:
1514       return &tData;
1515    case TGSI_FILE_PREDICATE:
1516       return &pData;
1517    case TGSI_FILE_ADDRESS:
1518       return &aData;
1519    case TGSI_FILE_OUTPUT:
1520       assert(prog->getType() == Program::TYPE_FRAGMENT);
1521       return &oData;
1522    default:
1523       assert(!"invalid/unhandled TGSI source file");
1524       return NULL;
1525    }
1526 }
1527
1528 Value *
1529 Converter::shiftAddress(Value *index)
1530 {
1531    if (!index)
1532       return NULL;
1533    return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1534 }
1535
1536 Value *
1537 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1538 {
1539    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
1540    const int idx = src.getIndex(0);
1541    const int swz = src.getSwizzle(c);
1542
1543    switch (src.getFile()) {
1544    case TGSI_FILE_IMMEDIATE:
1545       assert(!ptr);
1546       return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1547    case TGSI_FILE_CONSTANT:
1548       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1549    case TGSI_FILE_INPUT:
1550       if (prog->getType() == Program::TYPE_FRAGMENT) {
1551          // don't load masked inputs, won't be assigned a slot
1552          if (!ptr && !(info->in[idx].mask & (1 << swz)))
1553             return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1554          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_FACE)
1555             return mkOp1v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_FACE, 0));
1556          return interpolate(src, c, shiftAddress(ptr));
1557       } else
1558       if (prog->getType() == Program::TYPE_GEOMETRY) {
1559          if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1560             return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1561          // XXX: This is going to be a problem with scalar arrays, i.e. when
1562          // we cannot assume that the address is given in units of vec4.
1563          //
1564          // nv50 and nvc0 need different things here, so let the lowering
1565          // passes decide what to do with the address
1566          if (ptr)
1567             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1568       }
1569       return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1570    case TGSI_FILE_OUTPUT:
1571       assert(!"load from output file");
1572       return NULL;
1573    case TGSI_FILE_SYSTEM_VALUE:
1574       assert(!ptr);
1575       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1576    default:
1577       return getArrayForFile(src.getFile(), idx2d)->load(
1578          sub.cur->values, idx, swz, shiftAddress(ptr));
1579    }
1580 }
1581
1582 Value *
1583 Converter::acquireDst(int d, int c)
1584 {
1585    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1586    const unsigned f = dst.getFile();
1587    const int idx = dst.getIndex(0);
1588    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1589
1590    if (dst.isMasked(c) || f == TGSI_FILE_RESOURCE)
1591       return NULL;
1592
1593    if (dst.isIndirect(0) ||
1594        f == TGSI_FILE_SYSTEM_VALUE ||
1595        (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1596       return getScratch();
1597
1598    return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1599 }
1600
1601 void
1602 Converter::storeDst(int d, int c, Value *val)
1603 {
1604    const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1605
1606    switch (tgsi.getSaturate()) {
1607    case TGSI_SAT_NONE:
1608       break;
1609    case TGSI_SAT_ZERO_ONE:
1610       mkOp1(OP_SAT, dstTy, val, val);
1611       break;
1612    case TGSI_SAT_MINUS_PLUS_ONE:
1613       mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
1614       mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
1615       break;
1616    default:
1617       assert(!"invalid saturation mode");
1618       break;
1619    }
1620
1621    Value *ptr = NULL;
1622    if (dst.isIndirect(0))
1623       ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1624
1625    if (info->io.genUserClip > 0 &&
1626        dst.getFile() == TGSI_FILE_OUTPUT &&
1627        !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1628       mkMov(clipVtx[c], val);
1629       val = clipVtx[c];
1630    }
1631
1632    storeDst(dst, c, val, ptr);
1633 }
1634
1635 void
1636 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
1637                     Value *val, Value *ptr)
1638 {
1639    const unsigned f = dst.getFile();
1640    const int idx = dst.getIndex(0);
1641    const int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1642
1643    if (f == TGSI_FILE_SYSTEM_VALUE) {
1644       assert(!ptr);
1645       mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
1646    } else
1647    if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
1648
1649       if (ptr || (info->out[idx].mask & (1 << c))) {
1650          /* Save the viewport index into a scratch register so that it can be
1651             exported at EMIT time */
1652          if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
1653              viewport != NULL)
1654             mkOp1(OP_MOV, TYPE_U32, viewport, val);
1655          else
1656             mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
1657       }
1658    } else
1659    if (f == TGSI_FILE_TEMPORARY ||
1660        f == TGSI_FILE_PREDICATE ||
1661        f == TGSI_FILE_ADDRESS ||
1662        f == TGSI_FILE_OUTPUT) {
1663       getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
1664    } else {
1665       assert(!"invalid dst file");
1666    }
1667 }
1668
1669 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
1670    for (chan = 0; chan < 4; ++chan)                 \
1671       if (!inst.getDst(d).isMasked(chan))
1672
1673 Value *
1674 Converter::buildDot(int dim)
1675 {
1676    assert(dim > 0);
1677
1678    Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
1679    Value *dotp = getScratch();
1680
1681    mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
1682
1683    for (int c = 1; c < dim; ++c) {
1684       src0 = fetchSrc(0, c);
1685       src1 = fetchSrc(1, c);
1686       mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
1687    }
1688    return dotp;
1689 }
1690
1691 void
1692 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
1693 {
1694    FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
1695    join->fixed = 1;
1696    conv->insertHead(join);
1697
1698    fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
1699    fork->insertBefore(fork->getExit(), fork->joinAt);
1700 }
1701
1702 void
1703 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
1704 {
1705    unsigned rIdx = 0, sIdx = 0;
1706
1707    if (R >= 0)
1708       rIdx = tgsi.getSrc(R).getIndex(0);
1709    if (S >= 0)
1710       sIdx = tgsi.getSrc(S).getIndex(0);
1711
1712    tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
1713
1714    if (tgsi.getSrc(R).isIndirect(0)) {
1715       tex->tex.rIndirectSrc = s;
1716       tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
1717    }
1718    if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
1719       tex->tex.sIndirectSrc = s;
1720       tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
1721    }
1722 }
1723
1724 void
1725 Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
1726 {
1727    TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
1728    tex->tex.query = query;
1729    unsigned int c, d;
1730
1731    for (d = 0, c = 0; c < 4; ++c) {
1732       if (!dst0[c])
1733          continue;
1734       tex->tex.mask |= 1 << c;
1735       tex->setDef(d++, dst0[c]);
1736    }
1737    tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
1738
1739    setTexRS(tex, c, 1, -1);
1740
1741    bb->insertTail(tex);
1742 }
1743
1744 void
1745 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
1746 {
1747    Value *proj = fetchSrc(0, 3);
1748    Instruction *insn = proj->getUniqueInsn();
1749    int c;
1750
1751    if (insn->op == OP_PINTERP) {
1752       bb->insertTail(insn = cloneForward(func, insn));
1753       insn->op = OP_LINTERP;
1754       insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
1755       insn->setSrc(1, NULL);
1756       proj = insn->getDef(0);
1757    }
1758    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
1759
1760    for (c = 0; c < 4; ++c) {
1761       if (!(mask & (1 << c)))
1762          continue;
1763       if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
1764          continue;
1765       mask &= ~(1 << c);
1766
1767       bb->insertTail(insn = cloneForward(func, insn));
1768       insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
1769       insn->setSrc(1, proj);
1770       dst[c] = insn->getDef(0);
1771    }
1772    if (!mask)
1773       return;
1774
1775    proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
1776
1777    for (c = 0; c < 4; ++c)
1778       if (mask & (1 << c))
1779          dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
1780 }
1781
1782 // order of nv50 ir sources: x y z layer lod/bias shadow
1783 // order of TGSI TEX sources: x y z layer shadow lod/bias
1784 //  lowering will finally set the hw specific order (like array first on nvc0)
1785 void
1786 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
1787 {
1788    Value *val;
1789    Value *arg[4], *src[8];
1790    Value *lod = NULL, *shd = NULL;
1791    unsigned int s, c, d;
1792    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1793
1794    TexInstruction::Target tgt = tgsi.getTexture(code, R);
1795
1796    for (s = 0; s < tgt.getArgCount(); ++s)
1797       arg[s] = src[s] = fetchSrc(0, s);
1798
1799    if (texi->op == OP_TXL || texi->op == OP_TXB)
1800       lod = fetchSrc(L >> 4, L & 3);
1801
1802    if (C == 0x0f)
1803       C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
1804
1805    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
1806        tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
1807       shd = fetchSrc(1, 0);
1808    else if (tgt.isShadow())
1809       shd = fetchSrc(C >> 4, C & 3);
1810
1811    if (texi->op == OP_TXD) {
1812       for (c = 0; c < tgt.getDim(); ++c) {
1813          texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
1814          texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
1815       }
1816    }
1817
1818    // cube textures don't care about projection value, it's divided out
1819    if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
1820       unsigned int n = tgt.getDim();
1821       if (shd) {
1822          arg[n] = shd;
1823          ++n;
1824          assert(tgt.getDim() == tgt.getArgCount());
1825       }
1826       loadProjTexCoords(src, arg, (1 << n) - 1);
1827       if (shd)
1828          shd = src[n - 1];
1829    }
1830
1831    if (tgt.isCube()) {
1832       for (c = 0; c < 3; ++c)
1833          src[c] = mkOp1v(OP_ABS, TYPE_F32, getSSA(), arg[c]);
1834       val = getScratch();
1835       mkOp2(OP_MAX, TYPE_F32, val, src[0], src[1]);
1836       mkOp2(OP_MAX, TYPE_F32, val, src[2], val);
1837       mkOp1(OP_RCP, TYPE_F32, val, val);
1838       for (c = 0; c < 3; ++c)
1839          src[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), arg[c], val);
1840    }
1841
1842    for (c = 0, d = 0; c < 4; ++c) {
1843       if (dst[c]) {
1844          texi->setDef(d++, dst[c]);
1845          texi->tex.mask |= 1 << c;
1846       } else {
1847          // NOTE: maybe hook up def too, for CSE
1848       }
1849    }
1850    for (s = 0; s < tgt.getArgCount(); ++s)
1851       texi->setSrc(s, src[s]);
1852    if (lod)
1853       texi->setSrc(s++, lod);
1854    if (shd)
1855       texi->setSrc(s++, shd);
1856
1857    setTexRS(texi, s, R, S);
1858
1859    if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
1860       texi->tex.levelZero = true;
1861    if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
1862       texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
1863
1864    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1865    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1866       for (c = 0; c < 3; ++c) {
1867          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1868          texi->offset[s][c].setInsn(texi);
1869       }
1870    }
1871
1872    bb->insertTail(texi);
1873 }
1874
1875 // 1st source: xyz = coordinates, w = lod/sample
1876 // 2nd source: offset
1877 void
1878 Converter::handleTXF(Value *dst[4], int R, int L_M)
1879 {
1880    TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
1881    int ms;
1882    unsigned int c, d, s;
1883
1884    texi->tex.target = tgsi.getTexture(code, R);
1885
1886    ms = texi->tex.target.isMS() ? 1 : 0;
1887    texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
1888
1889    for (c = 0, d = 0; c < 4; ++c) {
1890       if (dst[c]) {
1891          texi->setDef(d++, dst[c]);
1892          texi->tex.mask |= 1 << c;
1893       }
1894    }
1895    for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
1896       texi->setSrc(c, fetchSrc(0, c));
1897    texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
1898
1899    setTexRS(texi, c, R, -1);
1900
1901    texi->tex.useOffsets = tgsi.getNumTexOffsets();
1902    for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
1903       for (c = 0; c < 3; ++c) {
1904          texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
1905          texi->offset[s][c].setInsn(texi);
1906       }
1907    }
1908
1909    bb->insertTail(texi);
1910 }
1911
1912 void
1913 Converter::handleLIT(Value *dst0[4])
1914 {
1915    Value *val0 = NULL;
1916    unsigned int mask = tgsi.getDst(0).getMask();
1917
1918    if (mask & (1 << 0))
1919       loadImm(dst0[0], 1.0f);
1920
1921    if (mask & (1 << 3))
1922       loadImm(dst0[3], 1.0f);
1923
1924    if (mask & (3 << 1)) {
1925       val0 = getScratch();
1926       mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
1927       if (mask & (1 << 1))
1928          mkMov(dst0[1], val0);
1929    }
1930
1931    if (mask & (1 << 2)) {
1932       Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
1933       Value *val1 = getScratch(), *val3 = getScratch();
1934
1935       Value *pos128 = loadImm(NULL, +127.999999f);
1936       Value *neg128 = loadImm(NULL, -127.999999f);
1937
1938       mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
1939       mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
1940       mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
1941       mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
1942
1943       mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
1944    }
1945 }
1946
1947 static inline bool
1948 isResourceSpecial(const int r)
1949 {
1950    return (r == TGSI_RESOURCE_GLOBAL ||
1951            r == TGSI_RESOURCE_LOCAL ||
1952            r == TGSI_RESOURCE_PRIVATE ||
1953            r == TGSI_RESOURCE_INPUT);
1954 }
1955
1956 static inline bool
1957 isResourceRaw(const struct tgsi::Source *code, const int r)
1958 {
1959    return isResourceSpecial(r) || code->resources[r].raw;
1960 }
1961
1962 static inline nv50_ir::TexTarget
1963 getResourceTarget(const struct tgsi::Source *code, int r)
1964 {
1965    if (isResourceSpecial(r))
1966       return nv50_ir::TEX_TARGET_BUFFER;
1967    return tgsi::translateTexture(code->resources.at(r).target);
1968 }
1969
1970 Symbol *
1971 Converter::getResourceBase(const int r)
1972 {
1973    Symbol *sym = NULL;
1974
1975    switch (r) {
1976    case TGSI_RESOURCE_GLOBAL:
1977       sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL, 15);
1978       break;
1979    case TGSI_RESOURCE_LOCAL:
1980       assert(prog->getType() == Program::TYPE_COMPUTE);
1981       sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
1982                      info->prop.cp.sharedOffset);
1983       break;
1984    case TGSI_RESOURCE_PRIVATE:
1985       sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
1986                      info->bin.tlsSpace);
1987       break;
1988    case TGSI_RESOURCE_INPUT:
1989       assert(prog->getType() == Program::TYPE_COMPUTE);
1990       sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
1991                      info->prop.cp.inputOffset);
1992       break;
1993    default:
1994       sym = new_Symbol(prog,
1995                        nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
1996       break;
1997    }
1998    return sym;
1999 }
2000
2001 void
2002 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2003 {
2004    const int arg =
2005       TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2006
2007    for (int c = 0; c < arg; ++c)
2008       coords.push_back(fetchSrc(s, c));
2009
2010    // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2011    if (r == TGSI_RESOURCE_LOCAL ||
2012        r == TGSI_RESOURCE_PRIVATE ||
2013        r == TGSI_RESOURCE_INPUT)
2014       coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2015                          coords[0]);
2016 }
2017
2018 static inline int
2019 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2020 {
2021    int n = 0;
2022
2023    while (mask) {
2024       if (mask & 1) {
2025          size[n]++;
2026       } else {
2027          if (size[n])
2028             comp[n = 1] = size[0] + 1;
2029          else
2030             comp[n]++;
2031       }
2032       mask >>= 1;
2033    }
2034    if (size[0] == 3) {
2035       n = 1;
2036       size[0] = (comp[0] == 1) ? 1 : 2;
2037       size[1] = 3 - size[0];
2038       comp[1] = comp[0] + size[0];
2039    }
2040    return n + 1;
2041 }
2042
2043 // For raw loads, granularity is 4 byte.
2044 // Usage of the texture read mask on OP_SULDP is not allowed.
2045 void
2046 Converter::handleLOAD(Value *dst0[4])
2047 {
2048    const int r = tgsi.getSrc(0).getIndex(0);
2049    int c;
2050    std::vector<Value *> off, src, ldv, def;
2051
2052    getResourceCoords(off, r, 1);
2053
2054    if (isResourceRaw(code, r)) {
2055       uint8_t mask = 0;
2056       uint8_t comp[2] = { 0, 0 };
2057       uint8_t size[2] = { 0, 0 };
2058
2059       Symbol *base = getResourceBase(r);
2060
2061       // determine the base and size of the at most 2 load ops
2062       for (c = 0; c < 4; ++c)
2063          if (!tgsi.getDst(0).isMasked(c))
2064             mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2065
2066       int n = partitionLoadStore(comp, size, mask);
2067
2068       src = off;
2069
2070       def.resize(4); // index by component, the ones we need will be non-NULL
2071       for (c = 0; c < 4; ++c) {
2072          if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2073             def[c] = dst0[c];
2074          else
2075          if (mask & (1 << c))
2076             def[c] = getScratch();
2077       }
2078
2079       const bool useLd = isResourceSpecial(r) ||
2080          (info->io.nv50styleSurfaces &&
2081           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2082
2083       for (int i = 0; i < n; ++i) {
2084          ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2085
2086          if (comp[i]) // adjust x component of source address if necessary
2087             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2088                             off[0], mkImm(comp[i] * 4));
2089          else
2090             src[0] = off[0];
2091
2092          if (useLd) {
2093             Instruction *ld =
2094                mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2095             for (size_t c = 1; c < ldv.size(); ++c)
2096                ld->setDef(c, ldv[c]);
2097          } else {
2098             mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2099                   0, ldv, src)->dType = typeOfSize(size[i] * 4);
2100          }
2101       }
2102    } else {
2103       def.resize(4);
2104       for (c = 0; c < 4; ++c) {
2105          if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2106             def[c] = getScratch();
2107          else
2108             def[c] = dst0[c];
2109       }
2110
2111       mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2112             def, off);
2113    }
2114    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2115       if (dst0[c] != def[c])
2116          mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2117 }
2118
2119 // For formatted stores, the write mask on OP_SUSTP can be used.
2120 // Raw stores have to be split.
2121 void
2122 Converter::handleSTORE()
2123 {
2124    const int r = tgsi.getDst(0).getIndex(0);
2125    int c;
2126    std::vector<Value *> off, src, dummy;
2127
2128    getResourceCoords(off, r, 0);
2129    src = off;
2130    const int s = src.size();
2131
2132    if (isResourceRaw(code, r)) {
2133       uint8_t comp[2] = { 0, 0 };
2134       uint8_t size[2] = { 0, 0 };
2135
2136       int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2137
2138       Symbol *base = getResourceBase(r);
2139
2140       const bool useSt = isResourceSpecial(r) ||
2141          (info->io.nv50styleSurfaces &&
2142           code->resources[r].target == TGSI_TEXTURE_BUFFER);
2143
2144       for (int i = 0; i < n; ++i) {
2145          if (comp[i]) // adjust x component of source address if necessary
2146             src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2147                             off[0], mkImm(comp[i] * 4));
2148          else
2149             src[0] = off[0];
2150
2151          const DataType stTy = typeOfSize(size[i] * 4);
2152
2153          if (useSt) {
2154             Instruction *st =
2155                mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2156             for (c = 1; c < size[i]; ++c)
2157                st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2158             st->setIndirect(0, 0, src[0]);
2159          } else {
2160             // attach values to be stored
2161             src.resize(s + size[i]);
2162             for (c = 0; c < size[i]; ++c)
2163                src[s + c] = fetchSrc(1, comp[i] + c);
2164             mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2165                   0, dummy, src)->setType(stTy);
2166          }
2167       }
2168    } else {
2169       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2170          src.push_back(fetchSrc(1, c));
2171
2172       mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2173             dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2174    }
2175 }
2176
2177 // XXX: These only work on resources with the single-component u32/s32 formats.
2178 // Therefore the result is replicated. This might not be intended by TGSI, but
2179 // operating on more than 1 component would produce undefined results because
2180 // they do not exist.
2181 void
2182 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2183 {
2184    const int r = tgsi.getSrc(0).getIndex(0);
2185    std::vector<Value *> srcv;
2186    std::vector<Value *> defv;
2187    LValue *dst = getScratch();
2188
2189    getResourceCoords(srcv, r, 1);
2190
2191    if (isResourceSpecial(r)) {
2192       assert(r != TGSI_RESOURCE_INPUT);
2193       Instruction *insn;
2194       insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2195       insn->subOp = subOp;
2196       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2197          insn->setSrc(2, fetchSrc(3, 0));
2198       insn->setIndirect(0, 0, srcv.at(0));
2199    } else {
2200       operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2201       TexTarget targ = getResourceTarget(code, r);
2202       int idx = code->resources[r].slot;
2203       defv.push_back(dst);
2204       srcv.push_back(fetchSrc(2, 0));
2205       if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2206          srcv.push_back(fetchSrc(3, 0));
2207       TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2208       tex->subOp = subOp;
2209       tex->tex.mask = 1;
2210       tex->setType(ty);
2211    }
2212
2213    for (int c = 0; c < 4; ++c)
2214       if (dst0[c])
2215          dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2216 }
2217
2218 void
2219 Converter::handleINTERP(Value *dst[4])
2220 {
2221    // Check whether the input is linear. All other attributes ignored.
2222    Instruction *insn;
2223    Value *offset = NULL, *ptr = NULL, *w = NULL;
2224    bool linear;
2225    operation op;
2226    int c, mode;
2227
2228    tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2229    assert(src.getFile() == TGSI_FILE_INPUT);
2230
2231    if (src.isIndirect(0))
2232       ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2233
2234    // XXX: no way to know interp mode if we don't know the index
2235    linear = info->in[ptr ? 0 : src.getIndex(0)].linear;
2236    if (linear) {
2237       op = OP_LINTERP;
2238       mode = NV50_IR_INTERP_LINEAR;
2239    } else {
2240       op = OP_PINTERP;
2241       mode = NV50_IR_INTERP_PERSPECTIVE;
2242    }
2243
2244    switch (tgsi.getOpcode()) {
2245    case TGSI_OPCODE_INTERP_CENTROID:
2246       mode |= NV50_IR_INTERP_CENTROID;
2247       break;
2248    case TGSI_OPCODE_INTERP_SAMPLE:
2249       insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2250       insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2251       mode |= NV50_IR_INTERP_OFFSET;
2252       break;
2253    case TGSI_OPCODE_INTERP_OFFSET: {
2254       // The input in src1.xy is float, but we need a single 32-bit value
2255       // where the upper and lower 16 bits are encoded in S0.12 format. We need
2256       // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2257       // and then convert to s32.
2258       Value *offs[2];
2259       for (c = 0; c < 2; c++) {
2260          offs[c] = fetchSrc(1, c);
2261          mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2262          mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2263          mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2264          mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2265       }
2266       offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2267                       offs[1], mkImm(0x1010), offs[0]);
2268       mode |= NV50_IR_INTERP_OFFSET;
2269       break;
2270    }
2271    }
2272
2273    if (op == OP_PINTERP) {
2274       if (offset) {
2275          w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2276          mkOp1(OP_RCP, TYPE_F32, w, w);
2277       } else {
2278          w = fragCoord[3];
2279       }
2280    }
2281
2282
2283    FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2284       insn = mkOp1(op, TYPE_F32, dst[c], srcToSym(src, c));
2285       if (op == OP_PINTERP)
2286          insn->setSrc(1, w);
2287       if (ptr)
2288          insn->setIndirect(0, 0, ptr);
2289       if (offset)
2290          insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2291
2292       insn->setInterpolate(mode);
2293    }
2294 }
2295
2296 Converter::Subroutine *
2297 Converter::getSubroutine(unsigned ip)
2298 {
2299    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2300
2301    if (it == sub.map.end())
2302       it = sub.map.insert(std::make_pair(
2303               ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2304
2305    return &it->second;
2306 }
2307
2308 Converter::Subroutine *
2309 Converter::getSubroutine(Function *f)
2310 {
2311    unsigned ip = f->getLabel();
2312    std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2313
2314    if (it == sub.map.end())
2315       it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2316
2317    return &it->second;
2318 }
2319
2320 bool
2321 Converter::isEndOfSubroutine(uint ip)
2322 {
2323    assert(ip < code->scan.num_instructions);
2324    tgsi::Instruction insn(&code->insns[ip]);
2325    return (insn.getOpcode() == TGSI_OPCODE_END ||
2326            insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2327            // does END occur at end of main or the very end ?
2328            insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2329 }
2330
2331 bool
2332 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2333 {
2334    Instruction *geni;
2335
2336    Value *dst0[4], *rDst0[4];
2337    Value *src0, *src1, *src2, *src3;
2338    Value *val0, *val1;
2339    int c;
2340
2341    tgsi = tgsi::Instruction(insn);
2342
2343    bool useScratchDst = tgsi.checkDstSrcAliasing();
2344
2345    operation op = tgsi.getOP();
2346    dstTy = tgsi.inferDstType();
2347    srcTy = tgsi.inferSrcType();
2348
2349    unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2350
2351    if (tgsi.dstCount()) {
2352       for (c = 0; c < 4; ++c) {
2353          rDst0[c] = acquireDst(0, c);
2354          dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2355       }
2356    }
2357
2358    switch (tgsi.getOpcode()) {
2359    case TGSI_OPCODE_ADD:
2360    case TGSI_OPCODE_UADD:
2361    case TGSI_OPCODE_AND:
2362    case TGSI_OPCODE_DIV:
2363    case TGSI_OPCODE_IDIV:
2364    case TGSI_OPCODE_UDIV:
2365    case TGSI_OPCODE_MAX:
2366    case TGSI_OPCODE_MIN:
2367    case TGSI_OPCODE_IMAX:
2368    case TGSI_OPCODE_IMIN:
2369    case TGSI_OPCODE_UMAX:
2370    case TGSI_OPCODE_UMIN:
2371    case TGSI_OPCODE_MOD:
2372    case TGSI_OPCODE_UMOD:
2373    case TGSI_OPCODE_MUL:
2374    case TGSI_OPCODE_UMUL:
2375    case TGSI_OPCODE_IMUL_HI:
2376    case TGSI_OPCODE_UMUL_HI:
2377    case TGSI_OPCODE_OR:
2378    case TGSI_OPCODE_SHL:
2379    case TGSI_OPCODE_ISHR:
2380    case TGSI_OPCODE_USHR:
2381    case TGSI_OPCODE_SUB:
2382    case TGSI_OPCODE_XOR:
2383       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2384          src0 = fetchSrc(0, c);
2385          src1 = fetchSrc(1, c);
2386          geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2387          geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2388       }
2389       break;
2390    case TGSI_OPCODE_MAD:
2391    case TGSI_OPCODE_UMAD:
2392    case TGSI_OPCODE_SAD:
2393       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2394          src0 = fetchSrc(0, c);
2395          src1 = fetchSrc(1, c);
2396          src2 = fetchSrc(2, c);
2397          mkOp3(op, dstTy, dst0[c], src0, src1, src2);
2398       }
2399       break;
2400    case TGSI_OPCODE_MOV:
2401    case TGSI_OPCODE_ABS:
2402    case TGSI_OPCODE_CEIL:
2403    case TGSI_OPCODE_FLR:
2404    case TGSI_OPCODE_TRUNC:
2405    case TGSI_OPCODE_RCP:
2406    case TGSI_OPCODE_IABS:
2407    case TGSI_OPCODE_INEG:
2408    case TGSI_OPCODE_NOT:
2409    case TGSI_OPCODE_DDX:
2410    case TGSI_OPCODE_DDY:
2411    case TGSI_OPCODE_DDX_FINE:
2412    case TGSI_OPCODE_DDY_FINE:
2413       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2414          mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
2415       break;
2416    case TGSI_OPCODE_RSQ:
2417       src0 = fetchSrc(0, 0);
2418       val0 = getScratch();
2419       mkOp1(OP_ABS, TYPE_F32, val0, src0);
2420       mkOp1(OP_RSQ, TYPE_F32, val0, val0);
2421       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2422          mkMov(dst0[c], val0);
2423       break;
2424    case TGSI_OPCODE_ARL:
2425    case TGSI_OPCODE_ARR:
2426       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2427          const RoundMode rnd =
2428             tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
2429          src0 = fetchSrc(0, c);
2430          mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
2431       }
2432       break;
2433    case TGSI_OPCODE_UARL:
2434       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2435          mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
2436       break;
2437    case TGSI_OPCODE_POW:
2438       val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
2439       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2440          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2441       break;
2442    case TGSI_OPCODE_EX2:
2443    case TGSI_OPCODE_LG2:
2444       val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
2445       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2446          mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
2447       break;
2448    case TGSI_OPCODE_COS:
2449    case TGSI_OPCODE_SIN:
2450       val0 = getScratch();
2451       if (mask & 7) {
2452          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
2453          mkOp1(op, TYPE_F32, val0, val0);
2454          for (c = 0; c < 3; ++c)
2455             if (dst0[c])
2456                mkMov(dst0[c], val0);
2457       }
2458       if (dst0[3]) {
2459          mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
2460          mkOp1(op, TYPE_F32, dst0[3], val0);
2461       }
2462       break;
2463    case TGSI_OPCODE_SCS:
2464       if (mask & 3) {
2465          val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
2466          if (dst0[0])
2467             mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
2468          if (dst0[1])
2469             mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
2470       }
2471       if (dst0[2])
2472          loadImm(dst0[2], 0.0f);
2473       if (dst0[3])
2474          loadImm(dst0[3], 1.0f);
2475       break;
2476    case TGSI_OPCODE_EXP:
2477       src0 = fetchSrc(0, 0);
2478       val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
2479       if (dst0[1])
2480          mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
2481       if (dst0[0])
2482          mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
2483       if (dst0[2])
2484          mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
2485       if (dst0[3])
2486          loadImm(dst0[3], 1.0f);
2487       break;
2488    case TGSI_OPCODE_LOG:
2489       src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
2490       val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
2491       if (dst0[0] || dst0[1])
2492          val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
2493       if (dst0[1]) {
2494          mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
2495          mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
2496          mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
2497       }
2498       if (dst0[3])
2499          loadImm(dst0[3], 1.0f);
2500       break;
2501    case TGSI_OPCODE_DP2:
2502       val0 = buildDot(2);
2503       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2504          mkMov(dst0[c], val0);
2505       break;
2506    case TGSI_OPCODE_DP3:
2507       val0 = buildDot(3);
2508       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2509          mkMov(dst0[c], val0);
2510       break;
2511    case TGSI_OPCODE_DP4:
2512       val0 = buildDot(4);
2513       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2514          mkMov(dst0[c], val0);
2515       break;
2516    case TGSI_OPCODE_DPH:
2517       val0 = buildDot(3);
2518       src1 = fetchSrc(1, 3);
2519       mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
2520       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2521          mkMov(dst0[c], val0);
2522       break;
2523    case TGSI_OPCODE_DST:
2524       if (dst0[0])
2525          loadImm(dst0[0], 1.0f);
2526       if (dst0[1]) {
2527          src0 = fetchSrc(0, 1);
2528          src1 = fetchSrc(1, 1);
2529          mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
2530       }
2531       if (dst0[2])
2532          mkMov(dst0[2], fetchSrc(0, 2));
2533       if (dst0[3])
2534          mkMov(dst0[3], fetchSrc(1, 3));
2535       break;
2536    case TGSI_OPCODE_LRP:
2537       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2538          src0 = fetchSrc(0, c);
2539          src1 = fetchSrc(1, c);
2540          src2 = fetchSrc(2, c);
2541          mkOp3(OP_MAD, TYPE_F32, dst0[c],
2542                mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
2543       }
2544       break;
2545    case TGSI_OPCODE_LIT:
2546       handleLIT(dst0);
2547       break;
2548    case TGSI_OPCODE_XPD:
2549       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2550          if (c < 3) {
2551             val0 = getSSA();
2552             src0 = fetchSrc(1, (c + 1) % 3);
2553             src1 = fetchSrc(0, (c + 2) % 3);
2554             mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
2555             mkOp1(OP_NEG, TYPE_F32, val0, val0);
2556
2557             src0 = fetchSrc(0, (c + 1) % 3);
2558             src1 = fetchSrc(1, (c + 2) % 3);
2559             mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
2560          } else {
2561             loadImm(dst0[c], 1.0f);
2562          }
2563       }
2564       break;
2565    case TGSI_OPCODE_ISSG:
2566    case TGSI_OPCODE_SSG:
2567       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2568          src0 = fetchSrc(0, c);
2569          val0 = getScratch();
2570          val1 = getScratch();
2571          mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
2572          mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
2573          if (srcTy == TYPE_F32)
2574             mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
2575          else
2576             mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
2577       }
2578       break;
2579    case TGSI_OPCODE_UCMP:
2580    case TGSI_OPCODE_CMP:
2581       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2582          src0 = fetchSrc(0, c);
2583          src1 = fetchSrc(1, c);
2584          src2 = fetchSrc(2, c);
2585          if (src1 == src2)
2586             mkMov(dst0[c], src1);
2587          else
2588             mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
2589                   srcTy, dst0[c], srcTy, src1, src2, src0);
2590       }
2591       break;
2592    case TGSI_OPCODE_FRC:
2593       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2594          src0 = fetchSrc(0, c);
2595          val0 = getScratch();
2596          mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
2597          mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
2598       }
2599       break;
2600    case TGSI_OPCODE_ROUND:
2601       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2602          mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
2603          ->rnd = ROUND_NI;
2604       break;
2605    case TGSI_OPCODE_CLAMP:
2606       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2607          src0 = fetchSrc(0, c);
2608          src1 = fetchSrc(1, c);
2609          src2 = fetchSrc(2, c);
2610          val0 = getScratch();
2611          mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
2612          mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
2613       }
2614       break;
2615    case TGSI_OPCODE_SLT:
2616    case TGSI_OPCODE_SGE:
2617    case TGSI_OPCODE_SEQ:
2618    case TGSI_OPCODE_SGT:
2619    case TGSI_OPCODE_SLE:
2620    case TGSI_OPCODE_SNE:
2621    case TGSI_OPCODE_FSEQ:
2622    case TGSI_OPCODE_FSGE:
2623    case TGSI_OPCODE_FSLT:
2624    case TGSI_OPCODE_FSNE:
2625    case TGSI_OPCODE_ISGE:
2626    case TGSI_OPCODE_ISLT:
2627    case TGSI_OPCODE_USEQ:
2628    case TGSI_OPCODE_USGE:
2629    case TGSI_OPCODE_USLT:
2630    case TGSI_OPCODE_USNE:
2631       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2632          src0 = fetchSrc(0, c);
2633          src1 = fetchSrc(1, c);
2634          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
2635       }
2636       break;
2637    case TGSI_OPCODE_KILL_IF:
2638       val0 = new_LValue(func, FILE_PREDICATE);
2639       mask = 0;
2640       for (c = 0; c < 4; ++c) {
2641          const int s = tgsi.getSrc(0).getSwizzle(c);
2642          if (mask & (1 << s))
2643             continue;
2644          mask |= 1 << s;
2645          mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
2646          mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
2647       }
2648       break;
2649    case TGSI_OPCODE_KILL:
2650       mkOp(OP_DISCARD, TYPE_NONE, NULL);
2651       break;
2652    case TGSI_OPCODE_TEX:
2653    case TGSI_OPCODE_TXB:
2654    case TGSI_OPCODE_TXL:
2655    case TGSI_OPCODE_TXP:
2656    case TGSI_OPCODE_LODQ:
2657       //              R  S     L     C    Dx    Dy
2658       handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
2659       break;
2660    case TGSI_OPCODE_TXD:
2661       handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
2662       break;
2663    case TGSI_OPCODE_TG4:
2664       handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
2665       break;
2666    case TGSI_OPCODE_TEX2:
2667       handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
2668       break;
2669    case TGSI_OPCODE_TXB2:
2670    case TGSI_OPCODE_TXL2:
2671       handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
2672       break;
2673    case TGSI_OPCODE_SAMPLE:
2674    case TGSI_OPCODE_SAMPLE_B:
2675    case TGSI_OPCODE_SAMPLE_D:
2676    case TGSI_OPCODE_SAMPLE_L:
2677    case TGSI_OPCODE_SAMPLE_C:
2678    case TGSI_OPCODE_SAMPLE_C_LZ:
2679       handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
2680       break;
2681    case TGSI_OPCODE_TXF:
2682       handleTXF(dst0, 1, 0x03);
2683       break;
2684    case TGSI_OPCODE_SAMPLE_I:
2685       handleTXF(dst0, 1, 0x03);
2686       break;
2687    case TGSI_OPCODE_SAMPLE_I_MS:
2688       handleTXF(dst0, 1, 0x20);
2689       break;
2690    case TGSI_OPCODE_TXQ:
2691    case TGSI_OPCODE_SVIEWINFO:
2692       handleTXQ(dst0, TXQ_DIMS);
2693       break;
2694    case TGSI_OPCODE_F2I:
2695    case TGSI_OPCODE_F2U:
2696       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2697          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
2698       break;
2699    case TGSI_OPCODE_I2F:
2700    case TGSI_OPCODE_U2F:
2701       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2702          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
2703       break;
2704    case TGSI_OPCODE_EMIT:
2705       /* export the saved viewport index */
2706       if (viewport != NULL) {
2707          Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
2708                                   info->out[info->io.viewportId].slot[0] * 4);
2709          mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
2710       }
2711       /* fallthrough */
2712    case TGSI_OPCODE_ENDPRIM:
2713    {
2714       // get vertex stream (must be immediate)
2715       unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
2716       if (stream && op == OP_RESTART)
2717          break;
2718       src0 = mkImm(stream);
2719       mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
2720       break;
2721    }
2722    case TGSI_OPCODE_IF:
2723    case TGSI_OPCODE_UIF:
2724    {
2725       BasicBlock *ifBB = new BasicBlock(func);
2726
2727       bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
2728       condBBs.push(bb);
2729       joinBBs.push(bb);
2730
2731       mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
2732
2733       setPosition(ifBB, true);
2734    }
2735       break;
2736    case TGSI_OPCODE_ELSE:
2737    {
2738       BasicBlock *elseBB = new BasicBlock(func);
2739       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2740
2741       forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
2742       condBBs.push(bb);
2743
2744       forkBB->getExit()->asFlow()->target.bb = elseBB;
2745       if (!bb->isTerminated())
2746          mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
2747
2748       setPosition(elseBB, true);
2749    }
2750       break;
2751    case TGSI_OPCODE_ENDIF:
2752    {
2753       BasicBlock *convBB = new BasicBlock(func);
2754       BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
2755       BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
2756
2757       if (!bb->isTerminated()) {
2758          // we only want join if none of the clauses ended with CONT/BREAK/RET
2759          if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
2760             insertConvergenceOps(convBB, forkBB);
2761          mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
2762          bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2763       }
2764
2765       if (prevBB->getExit()->op == OP_BRA) {
2766          prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
2767          prevBB->getExit()->asFlow()->target.bb = convBB;
2768       }
2769       setPosition(convBB, true);
2770    }
2771       break;
2772    case TGSI_OPCODE_BGNLOOP:
2773    {
2774       BasicBlock *lbgnBB = new BasicBlock(func);
2775       BasicBlock *lbrkBB = new BasicBlock(func);
2776
2777       loopBBs.push(lbgnBB);
2778       breakBBs.push(lbrkBB);
2779       if (loopBBs.getSize() > func->loopNestingBound)
2780          func->loopNestingBound++;
2781
2782       mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
2783
2784       bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
2785       setPosition(lbgnBB, true);
2786       mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
2787    }
2788       break;
2789    case TGSI_OPCODE_ENDLOOP:
2790    {
2791       BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
2792
2793       if (!bb->isTerminated()) {
2794          mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
2795          bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
2796       }
2797       setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
2798    }
2799       break;
2800    case TGSI_OPCODE_BRK:
2801    {
2802       if (bb->isTerminated())
2803          break;
2804       BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
2805       mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
2806       bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
2807    }
2808       break;
2809    case TGSI_OPCODE_CONT:
2810    {
2811       if (bb->isTerminated())
2812          break;
2813       BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
2814       mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
2815       contBB->explicitCont = true;
2816       bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
2817    }
2818       break;
2819    case TGSI_OPCODE_BGNSUB:
2820    {
2821       Subroutine *s = getSubroutine(ip);
2822       BasicBlock *entry = new BasicBlock(s->f);
2823       BasicBlock *leave = new BasicBlock(s->f);
2824
2825       // multiple entrypoints possible, keep the graph connected
2826       if (prog->getType() == Program::TYPE_COMPUTE)
2827          prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
2828
2829       sub.cur = s;
2830       s->f->setEntry(entry);
2831       s->f->setExit(leave);
2832       setPosition(entry, true);
2833       return true;
2834    }
2835    case TGSI_OPCODE_ENDSUB:
2836    {
2837       sub.cur = getSubroutine(prog->main);
2838       setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
2839       return true;
2840    }
2841    case TGSI_OPCODE_CAL:
2842    {
2843       Subroutine *s = getSubroutine(tgsi.getLabel());
2844       mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
2845       func->call.attach(&s->f->call, Graph::Edge::TREE);
2846       return true;
2847    }
2848    case TGSI_OPCODE_RET:
2849    {
2850       if (bb->isTerminated())
2851          return true;
2852       BasicBlock *leave = BasicBlock::get(func->cfgExit);
2853
2854       if (!isEndOfSubroutine(ip + 1)) {
2855          // insert a PRERET at the entry if this is an early return
2856          // (only needed for sharing code in the epilogue)
2857          BasicBlock *pos = getBB();
2858          setPosition(BasicBlock::get(func->cfg.getRoot()), false);
2859          mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
2860          setPosition(pos, true);
2861       }
2862       mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
2863       bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
2864    }
2865       break;
2866    case TGSI_OPCODE_END:
2867    {
2868       // attach and generate epilogue code
2869       BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
2870       bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
2871       setPosition(epilogue, true);
2872       if (prog->getType() == Program::TYPE_FRAGMENT)
2873          exportOutputs();
2874       if (info->io.genUserClip > 0)
2875          handleUserClipPlanes();
2876       mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
2877    }
2878       break;
2879    case TGSI_OPCODE_SWITCH:
2880    case TGSI_OPCODE_CASE:
2881       ERROR("switch/case opcode encountered, should have been lowered\n");
2882       abort();
2883       break;
2884    case TGSI_OPCODE_LOAD:
2885       handleLOAD(dst0);
2886       break;
2887    case TGSI_OPCODE_STORE:
2888       handleSTORE();
2889       break;
2890    case TGSI_OPCODE_BARRIER:
2891       geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
2892       geni->fixed = 1;
2893       geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
2894       break;
2895    case TGSI_OPCODE_MFENCE:
2896    case TGSI_OPCODE_LFENCE:
2897    case TGSI_OPCODE_SFENCE:
2898       geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
2899       geni->fixed = 1;
2900       geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2901       break;
2902    case TGSI_OPCODE_ATOMUADD:
2903    case TGSI_OPCODE_ATOMXCHG:
2904    case TGSI_OPCODE_ATOMCAS:
2905    case TGSI_OPCODE_ATOMAND:
2906    case TGSI_OPCODE_ATOMOR:
2907    case TGSI_OPCODE_ATOMXOR:
2908    case TGSI_OPCODE_ATOMUMIN:
2909    case TGSI_OPCODE_ATOMIMIN:
2910    case TGSI_OPCODE_ATOMUMAX:
2911    case TGSI_OPCODE_ATOMIMAX:
2912       handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
2913       break;
2914    case TGSI_OPCODE_IBFE:
2915    case TGSI_OPCODE_UBFE:
2916       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2917          src0 = fetchSrc(0, c);
2918          src1 = fetchSrc(1, c);
2919          src2 = fetchSrc(2, c);
2920          mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
2921          mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
2922       }
2923       break;
2924    case TGSI_OPCODE_BFI:
2925       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2926          src0 = fetchSrc(0, c);
2927          src1 = fetchSrc(1, c);
2928          src2 = fetchSrc(2, c);
2929          src3 = fetchSrc(3, c);
2930          mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
2931          mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
2932       }
2933       break;
2934    case TGSI_OPCODE_LSB:
2935       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2936          src0 = fetchSrc(0, c);
2937          geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
2938          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2939          geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
2940          geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
2941       }
2942       break;
2943    case TGSI_OPCODE_IMSB:
2944    case TGSI_OPCODE_UMSB:
2945       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2946          src0 = fetchSrc(0, c);
2947          mkOp1(OP_BFIND, srcTy, dst0[c], src0);
2948       }
2949       break;
2950    case TGSI_OPCODE_BREV:
2951       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2952          src0 = fetchSrc(0, c);
2953          geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
2954          geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
2955       }
2956       break;
2957    case TGSI_OPCODE_POPC:
2958       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2959          src0 = fetchSrc(0, c);
2960          mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
2961       }
2962       break;
2963    case TGSI_OPCODE_INTERP_CENTROID:
2964    case TGSI_OPCODE_INTERP_SAMPLE:
2965    case TGSI_OPCODE_INTERP_OFFSET:
2966       handleINTERP(dst0);
2967       break;
2968    case TGSI_OPCODE_D2I:
2969    case TGSI_OPCODE_D2U:
2970    case TGSI_OPCODE_D2F: {
2971       int pos = 0;
2972       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2973          Value *dreg = getSSA(8);
2974          src0 = fetchSrc(0, pos);
2975          src1 = fetchSrc(0, pos + 1);
2976          mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
2977          mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
2978          pos += 2;
2979       }
2980       break;
2981    }
2982    case TGSI_OPCODE_I2D:
2983    case TGSI_OPCODE_U2D:
2984    case TGSI_OPCODE_F2D:
2985       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2986          Value *dreg = getSSA(8);
2987          mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
2988          mkSplit(&dst0[c], 4, dreg);
2989          c++;
2990       }
2991       break;
2992    case TGSI_OPCODE_DABS:
2993    case TGSI_OPCODE_DNEG:
2994    case TGSI_OPCODE_DRCP:
2995    case TGSI_OPCODE_DSQRT:
2996    case TGSI_OPCODE_DRSQ:
2997    case TGSI_OPCODE_DTRUNC:
2998    case TGSI_OPCODE_DCEIL:
2999    case TGSI_OPCODE_DFLR:
3000       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3001          src0 = getSSA(8);
3002          Value *dst = getSSA(8), *tmp[2];
3003          tmp[0] = fetchSrc(0, c);
3004          tmp[1] = fetchSrc(0, c + 1);
3005          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3006          mkOp1(op, dstTy, dst, src0);
3007          mkSplit(&dst0[c], 4, dst);
3008          c++;
3009       }
3010       break;
3011    case TGSI_OPCODE_DFRAC:
3012       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3013          src0 = getSSA(8);
3014          Value *dst = getSSA(8), *tmp[2];
3015          tmp[0] = fetchSrc(0, c);
3016          tmp[1] = fetchSrc(0, c + 1);
3017          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3018          mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3019          mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3020          mkSplit(&dst0[c], 4, dst);
3021          c++;
3022       }
3023       break;
3024    case TGSI_OPCODE_DSLT:
3025    case TGSI_OPCODE_DSGE:
3026    case TGSI_OPCODE_DSEQ:
3027    case TGSI_OPCODE_DSNE: {
3028       int pos = 0;
3029       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3030          Value *tmp[2];
3031
3032          src0 = getSSA(8);
3033          src1 = getSSA(8);
3034          tmp[0] = fetchSrc(0, pos);
3035          tmp[1] = fetchSrc(0, pos + 1);
3036          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3037          tmp[0] = fetchSrc(1, pos);
3038          tmp[1] = fetchSrc(1, pos + 1);
3039          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3040          mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3041          pos += 2;
3042       }
3043       break;
3044    }
3045    case TGSI_OPCODE_DADD:
3046    case TGSI_OPCODE_DMUL:
3047    case TGSI_OPCODE_DMAX:
3048    case TGSI_OPCODE_DMIN:
3049       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3050          src0 = getSSA(8);
3051          src1 = getSSA(8);
3052          Value *dst = getSSA(8), *tmp[2];
3053          tmp[0] = fetchSrc(0, c);
3054          tmp[1] = fetchSrc(0, c + 1);
3055          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3056          tmp[0] = fetchSrc(1, c);
3057          tmp[1] = fetchSrc(1, c + 1);
3058          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3059          mkOp2(op, dstTy, dst, src0, src1);
3060          mkSplit(&dst0[c], 4, dst);
3061          c++;
3062       }
3063       break;
3064    case TGSI_OPCODE_DMAD:
3065       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3066          src0 = getSSA(8);
3067          src1 = getSSA(8);
3068          src2 = getSSA(8);
3069          Value *dst = getSSA(8), *tmp[2];
3070          tmp[0] = fetchSrc(0, c);
3071          tmp[1] = fetchSrc(0, c + 1);
3072          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3073          tmp[0] = fetchSrc(1, c);
3074          tmp[1] = fetchSrc(1, c + 1);
3075          mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3076          tmp[0] = fetchSrc(2, c);
3077          tmp[1] = fetchSrc(2, c + 1);
3078          mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3079          mkOp3(op, dstTy, dst, src0, src1, src2);
3080          mkSplit(&dst0[c], 4, dst);
3081          c++;
3082       }
3083       break;
3084    case TGSI_OPCODE_DROUND:
3085       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3086          src0 = getSSA(8);
3087          Value *dst = getSSA(8), *tmp[2];
3088          tmp[0] = fetchSrc(0, c);
3089          tmp[1] = fetchSrc(0, c + 1);
3090          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3091          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3092          ->rnd = ROUND_NI;
3093          mkSplit(&dst0[c], 4, dst);
3094          c++;
3095       }
3096       break;
3097    case TGSI_OPCODE_DSSG:
3098       FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3099          src0 = getSSA(8);
3100          Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3101          tmp[0] = fetchSrc(0, c);
3102          tmp[1] = fetchSrc(0, c + 1);
3103          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3104
3105          val0 = getScratch();
3106          val1 = getScratch();
3107          // The zero is wrong here since it's only 32-bit, but it works out in
3108          // the end since it gets replaced with $r63.
3109          mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3110          mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3111          mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3112          mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3113          mkSplit(&dst0[c], 4, dst);
3114          c++;
3115       }
3116       break;
3117    default:
3118       ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3119       assert(0);
3120       break;
3121    }
3122
3123    if (tgsi.dstCount()) {
3124       for (c = 0; c < 4; ++c) {
3125          if (!dst0[c])
3126             continue;
3127          if (dst0[c] != rDst0[c])
3128             mkMov(rDst0[c], dst0[c]);
3129          storeDst(0, c, rDst0[c]);
3130       }
3131    }
3132    vtxBaseValid = 0;
3133
3134    return true;
3135 }
3136
3137 void
3138 Converter::handleUserClipPlanes()
3139 {
3140    Value *res[8];
3141    int n, i, c;
3142
3143    for (c = 0; c < 4; ++c) {
3144       for (i = 0; i < info->io.genUserClip; ++i) {
3145          Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.ucpCBSlot,
3146                                 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3147          Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3148          if (c == 0)
3149             res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3150          else
3151             mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3152       }
3153    }
3154
3155    const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3156
3157    for (i = 0; i < info->io.genUserClip; ++i) {
3158       n = i / 4 + first;
3159       c = i % 4;
3160       Symbol *sym =
3161          mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3162       mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3163    }
3164 }
3165
3166 void
3167 Converter::exportOutputs()
3168 {
3169    for (unsigned int i = 0; i < info->numOutputs; ++i) {
3170       for (unsigned int c = 0; c < 4; ++c) {
3171          if (!oData.exists(sub.cur->values, i, c))
3172             continue;
3173          Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3174                                 info->out[i].slot[c] * 4);
3175          Value *val = oData.load(sub.cur->values, i, c, NULL);
3176          if (val)
3177             mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3178       }
3179    }
3180 }
3181
3182 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3183      code(code),
3184      tgsi(NULL),
3185      tData(this), aData(this), pData(this), oData(this)
3186 {
3187    info = code->info;
3188
3189    const DataFile tFile = code->mainTempsInLMem ? FILE_MEMORY_LOCAL : FILE_GPR;
3190
3191    const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3192    const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3193    const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3194    const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3195
3196    tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, tFile, 0);
3197    pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3198    aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3199    oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3200
3201    zero = mkImm((uint32_t)0);
3202
3203    vtxBaseValid = 0;
3204 }
3205
3206 Converter::~Converter()
3207 {
3208 }
3209
3210 inline const Converter::Location *
3211 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3212 {
3213    ValueMap::l_iterator it = s->values.l.find(v);
3214    return it == s->values.l.end() ? NULL : &it->second;
3215 }
3216
3217 template<typename T> inline void
3218 Converter::BindArgumentsPass::updateCallArgs(
3219    Instruction *i, void (Instruction::*setArg)(int, Value *),
3220    T (Function::*proto))
3221 {
3222    Function *g = i->asFlow()->target.fn;
3223    Subroutine *subg = conv.getSubroutine(g);
3224
3225    for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3226       Value *v = (g->*proto)[a].get();
3227       const Converter::Location &l = *getValueLocation(subg, v);
3228       Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3229
3230       (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3231    }
3232 }
3233
3234 template<typename T> inline void
3235 Converter::BindArgumentsPass::updatePrototype(
3236    BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3237 {
3238    (func->*updateSet)();
3239
3240    for (unsigned i = 0; i < set->getSize(); ++i) {
3241       Value *v = func->getLValue(i);
3242       const Converter::Location *l = getValueLocation(sub, v);
3243
3244       // only include values with a matching TGSI register
3245       if (set->test(i) && l && !conv.code->locals.count(*l))
3246          (func->*proto).push_back(v);
3247    }
3248 }
3249
3250 bool
3251 Converter::BindArgumentsPass::visit(Function *f)
3252 {
3253    sub = conv.getSubroutine(f);
3254
3255    for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3256         !bi.end(); bi.next()) {
3257       for (Instruction *i = BasicBlock::get(bi)->getFirst();
3258            i; i = i->next) {
3259          if (i->op == OP_CALL && !i->asFlow()->builtin) {
3260             updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3261             updateCallArgs(i, &Instruction::setDef, &Function::outs);
3262          }
3263       }
3264    }
3265
3266    if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3267       return true;
3268    updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3269                    &Function::buildLiveSets, &Function::ins);
3270    updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3271                    &Function::buildDefSets, &Function::outs);
3272
3273    return true;
3274 }
3275
3276 bool
3277 Converter::run()
3278 {
3279    BasicBlock *entry = new BasicBlock(prog->main);
3280    BasicBlock *leave = new BasicBlock(prog->main);
3281
3282    prog->main->setEntry(entry);
3283    prog->main->setExit(leave);
3284
3285    setPosition(entry, true);
3286    sub.cur = getSubroutine(prog->main);
3287
3288    if (info->io.genUserClip > 0) {
3289       for (int c = 0; c < 4; ++c)
3290          clipVtx[c] = getScratch();
3291    }
3292
3293    if (prog->getType() == Program::TYPE_FRAGMENT) {
3294       Symbol *sv = mkSysVal(SV_POSITION, 3);
3295       fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
3296       mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
3297    }
3298
3299    if (info->io.viewportId >= 0)
3300       viewport = getScratch();
3301    else
3302       viewport = NULL;
3303
3304    for (ip = 0; ip < code->scan.num_instructions; ++ip) {
3305       if (!handleInstruction(&code->insns[ip]))
3306          return false;
3307    }
3308
3309    if (!BindArgumentsPass(*this).run(prog))
3310       return false;
3311
3312    return true;
3313 }
3314
3315 } // unnamed namespace
3316
3317 namespace nv50_ir {
3318
3319 bool
3320 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
3321 {
3322    tgsi::Source src(info);
3323    if (!src.scanSource())
3324       return false;
3325    tlsSize = info->bin.tlsSpace;
3326
3327    Converter builder(this, &src);
3328    return builder.run();
3329 }
3330
3331 } // namespace nv50_ir