2 * Copyright 2011 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include "tgsi/tgsi_build.h"
24 #include "tgsi/tgsi_dump.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_util.h"
30 #include "codegen/nv50_ir.h"
31 #include "codegen/nv50_ir_from_common.h"
32 #include "codegen/nv50_ir_util.h"
38 static nv50_ir::operation
translateOpcode(uint opcode
);
39 static nv50_ir::DataFile
translateFile(uint file
);
40 static nv50_ir::TexTarget
translateTexture(uint texTarg
);
41 static nv50_ir::SVSemantic
translateSysVal(uint sysval
);
42 static nv50_ir::CacheMode
translateCacheMode(uint qualifier
);
47 Instruction(const struct tgsi_full_instruction
*inst
) : insn(inst
) { }
52 SrcRegister(const struct tgsi_full_src_register
*src
)
57 SrcRegister(const struct tgsi_src_register
& src
) : reg(src
), fsr(NULL
) { }
59 SrcRegister(const struct tgsi_ind_register
& ind
)
60 : reg(tgsi_util_get_src_from_ind(&ind
)),
64 struct tgsi_src_register
offsetToSrc(struct tgsi_texture_offset off
)
66 struct tgsi_src_register reg
;
67 memset(®
, 0, sizeof(reg
));
68 reg
.Index
= off
.Index
;
70 reg
.SwizzleX
= off
.SwizzleX
;
71 reg
.SwizzleY
= off
.SwizzleY
;
72 reg
.SwizzleZ
= off
.SwizzleZ
;
76 SrcRegister(const struct tgsi_texture_offset
& off
) :
77 reg(offsetToSrc(off
)),
81 uint
getFile() const { return reg
.File
; }
83 bool is2D() const { return reg
.Dimension
; }
85 bool isIndirect(int dim
) const
87 return (dim
&& fsr
) ? fsr
->Dimension
.Indirect
: reg
.Indirect
;
90 int getIndex(int dim
) const
92 return (dim
&& fsr
) ? fsr
->Dimension
.Index
: reg
.Index
;
95 int getSwizzle(int chan
) const
97 return tgsi_util_get_src_register_swizzle(®
, chan
);
100 int getArrayId() const
103 return fsr
->Indirect
.ArrayID
;
107 nv50_ir::Modifier
getMod(int chan
) const;
109 SrcRegister
getIndirect(int dim
) const
111 assert(fsr
&& isIndirect(dim
));
113 return SrcRegister(fsr
->DimIndirect
);
114 return SrcRegister(fsr
->Indirect
);
117 uint32_t getValueU32(int c
, const struct nv50_ir_prog_info
*info
) const
119 assert(reg
.File
== TGSI_FILE_IMMEDIATE
);
120 assert(!reg
.Absolute
);
122 return info
->immd
.data
[reg
.Index
* 4 + getSwizzle(c
)];
126 const struct tgsi_src_register reg
;
127 const struct tgsi_full_src_register
*fsr
;
133 DstRegister(const struct tgsi_full_dst_register
*dst
)
134 : reg(dst
->Register
),
138 DstRegister(const struct tgsi_dst_register
& dst
) : reg(dst
), fdr(NULL
) { }
140 uint
getFile() const { return reg
.File
; }
142 bool is2D() const { return reg
.Dimension
; }
144 bool isIndirect(int dim
) const
146 return (dim
&& fdr
) ? fdr
->Dimension
.Indirect
: reg
.Indirect
;
149 int getIndex(int dim
) const
151 return (dim
&& fdr
) ? fdr
->Dimension
.Dimension
: reg
.Index
;
154 unsigned int getMask() const { return reg
.WriteMask
; }
156 bool isMasked(int chan
) const { return !(getMask() & (1 << chan
)); }
158 SrcRegister
getIndirect(int dim
) const
160 assert(fdr
&& isIndirect(dim
));
162 return SrcRegister(fdr
->DimIndirect
);
163 return SrcRegister(fdr
->Indirect
);
166 struct tgsi_full_src_register
asSrc()
169 return tgsi_full_src_register_from_dst(fdr
);
172 int getArrayId() const
175 return fdr
->Indirect
.ArrayID
;
180 const struct tgsi_dst_register reg
;
181 const struct tgsi_full_dst_register
*fdr
;
184 inline uint
getOpcode() const { return insn
->Instruction
.Opcode
; }
186 unsigned int srcCount() const { return insn
->Instruction
.NumSrcRegs
; }
187 unsigned int dstCount() const { return insn
->Instruction
.NumDstRegs
; }
189 // mask of used components of source s
190 unsigned int srcMask(unsigned int s
) const;
191 unsigned int texOffsetMask() const;
193 SrcRegister
getSrc(unsigned int s
) const
195 assert(s
< srcCount());
196 return SrcRegister(&insn
->Src
[s
]);
199 DstRegister
getDst(unsigned int d
) const
201 assert(d
< dstCount());
202 return DstRegister(&insn
->Dst
[d
]);
205 SrcRegister
getTexOffset(unsigned int i
) const
207 assert(i
< TGSI_FULL_MAX_TEX_OFFSETS
);
208 return SrcRegister(insn
->TexOffsets
[i
]);
211 unsigned int getNumTexOffsets() const { return insn
->Texture
.NumOffsets
; }
213 bool checkDstSrcAliasing() const;
215 inline nv50_ir::operation
getOP() const {
216 return translateOpcode(getOpcode()); }
218 nv50_ir::DataType
inferSrcType() const;
219 nv50_ir::DataType
inferDstType() const;
221 nv50_ir::CondCode
getSetCond() const;
223 nv50_ir::TexInstruction::Target
getTexture(const Source
*, int s
) const;
225 const nv50_ir::TexInstruction::ImgFormatDesc
*getImageFormat() const {
226 return nv50_ir::TexInstruction::translateImgFormat((enum pipe_format
)insn
->Memory
.Format
);
229 nv50_ir::TexTarget
getImageTarget() const {
230 return translateTexture(insn
->Memory
.Texture
);
233 nv50_ir::CacheMode
getCacheMode() const {
234 if (!insn
->Instruction
.Memory
)
235 return nv50_ir::CACHE_CA
;
236 return translateCacheMode(insn
->Memory
.Qualifier
);
239 inline uint
getLabel() { return insn
->Label
.Label
; }
241 unsigned getSaturate() const { return insn
->Instruction
.Saturate
; }
245 tgsi_dump_instruction(insn
, 1);
249 const struct tgsi_full_instruction
*insn
;
252 unsigned int Instruction::texOffsetMask() const
254 const struct tgsi_instruction_texture
*tex
= &insn
->Texture
;
255 assert(insn
->Instruction
.Texture
);
257 switch (tex
->Texture
) {
258 case TGSI_TEXTURE_BUFFER
:
259 case TGSI_TEXTURE_1D
:
260 case TGSI_TEXTURE_SHADOW1D
:
261 case TGSI_TEXTURE_1D_ARRAY
:
262 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
264 case TGSI_TEXTURE_2D
:
265 case TGSI_TEXTURE_SHADOW2D
:
266 case TGSI_TEXTURE_2D_ARRAY
:
267 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
268 case TGSI_TEXTURE_RECT
:
269 case TGSI_TEXTURE_SHADOWRECT
:
270 case TGSI_TEXTURE_2D_MSAA
:
271 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
273 case TGSI_TEXTURE_3D
:
276 assert(!"Unexpected texture target");
281 unsigned int Instruction::srcMask(unsigned int s
) const
283 unsigned int mask
= insn
->Dst
[0].Register
.WriteMask
;
285 switch (insn
->Instruction
.Opcode
) {
286 case TGSI_OPCODE_COS
:
287 case TGSI_OPCODE_SIN
:
288 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
289 case TGSI_OPCODE_DP2
:
291 case TGSI_OPCODE_DP3
:
293 case TGSI_OPCODE_DP4
:
294 case TGSI_OPCODE_KILL_IF
: /* WriteMask ignored */
296 case TGSI_OPCODE_DST
:
297 return mask
& (s
? 0xa : 0x6);
298 case TGSI_OPCODE_EX2
:
299 case TGSI_OPCODE_EXP
:
300 case TGSI_OPCODE_LG2
:
301 case TGSI_OPCODE_LOG
:
302 case TGSI_OPCODE_POW
:
303 case TGSI_OPCODE_RCP
:
304 case TGSI_OPCODE_RSQ
:
307 case TGSI_OPCODE_UIF
:
309 case TGSI_OPCODE_LIT
:
311 case TGSI_OPCODE_TEX2
:
312 case TGSI_OPCODE_TXB2
:
313 case TGSI_OPCODE_TXL2
:
314 return (s
== 0) ? 0xf : 0x3;
315 case TGSI_OPCODE_TEX
:
316 case TGSI_OPCODE_TXB
:
317 case TGSI_OPCODE_TXD
:
318 case TGSI_OPCODE_TXL
:
319 case TGSI_OPCODE_TXP
:
320 case TGSI_OPCODE_TXF
:
321 case TGSI_OPCODE_TG4
:
322 case TGSI_OPCODE_TEX_LZ
:
323 case TGSI_OPCODE_TXF_LZ
:
324 case TGSI_OPCODE_LODQ
:
326 const struct tgsi_instruction_texture
*tex
= &insn
->Texture
;
328 assert(insn
->Instruction
.Texture
);
331 if (insn
->Instruction
.Opcode
!= TGSI_OPCODE_TEX
&&
332 insn
->Instruction
.Opcode
!= TGSI_OPCODE_TEX_LZ
&&
333 insn
->Instruction
.Opcode
!= TGSI_OPCODE_TXF_LZ
&&
334 insn
->Instruction
.Opcode
!= TGSI_OPCODE_TXD
)
335 mask
|= 0x8; /* bias, lod or proj */
337 switch (tex
->Texture
) {
338 case TGSI_TEXTURE_1D
:
341 case TGSI_TEXTURE_SHADOW1D
:
344 case TGSI_TEXTURE_1D_ARRAY
:
345 case TGSI_TEXTURE_2D
:
346 case TGSI_TEXTURE_RECT
:
349 case TGSI_TEXTURE_CUBE_ARRAY
:
350 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
351 case TGSI_TEXTURE_SHADOWCUBE
:
352 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
360 case TGSI_OPCODE_TXQ
:
362 case TGSI_OPCODE_D2I
:
363 case TGSI_OPCODE_D2U
:
364 case TGSI_OPCODE_D2F
:
365 case TGSI_OPCODE_DSLT
:
366 case TGSI_OPCODE_DSGE
:
367 case TGSI_OPCODE_DSEQ
:
368 case TGSI_OPCODE_DSNE
:
369 case TGSI_OPCODE_U64SEQ
:
370 case TGSI_OPCODE_U64SNE
:
371 case TGSI_OPCODE_I64SLT
:
372 case TGSI_OPCODE_U64SLT
:
373 case TGSI_OPCODE_I64SGE
:
374 case TGSI_OPCODE_U64SGE
:
375 case TGSI_OPCODE_I642F
:
376 case TGSI_OPCODE_U642F
:
377 switch (util_bitcount(mask
)) {
381 assert(!"unexpected mask");
384 case TGSI_OPCODE_I2D
:
385 case TGSI_OPCODE_U2D
:
386 case TGSI_OPCODE_F2D
: {
388 if ((mask
& 0x3) == 0x3)
390 if ((mask
& 0xc) == 0xc)
394 case TGSI_OPCODE_PK2H
:
396 case TGSI_OPCODE_UP2H
:
405 nv50_ir::Modifier
Instruction::SrcRegister::getMod(int chan
) const
407 nv50_ir::Modifier
m(0);
410 m
= m
| nv50_ir::Modifier(NV50_IR_MOD_ABS
);
412 m
= m
| nv50_ir::Modifier(NV50_IR_MOD_NEG
);
416 static nv50_ir::DataFile
translateFile(uint file
)
419 case TGSI_FILE_CONSTANT
: return nv50_ir::FILE_MEMORY_CONST
;
420 case TGSI_FILE_INPUT
: return nv50_ir::FILE_SHADER_INPUT
;
421 case TGSI_FILE_OUTPUT
: return nv50_ir::FILE_SHADER_OUTPUT
;
422 case TGSI_FILE_TEMPORARY
: return nv50_ir::FILE_GPR
;
423 case TGSI_FILE_ADDRESS
: return nv50_ir::FILE_ADDRESS
;
424 case TGSI_FILE_IMMEDIATE
: return nv50_ir::FILE_IMMEDIATE
;
425 case TGSI_FILE_SYSTEM_VALUE
: return nv50_ir::FILE_SYSTEM_VALUE
;
426 case TGSI_FILE_BUFFER
: return nv50_ir::FILE_MEMORY_BUFFER
;
427 case TGSI_FILE_IMAGE
: return nv50_ir::FILE_MEMORY_GLOBAL
;
428 case TGSI_FILE_MEMORY
: return nv50_ir::FILE_MEMORY_GLOBAL
;
429 case TGSI_FILE_SAMPLER
:
432 return nv50_ir::FILE_NULL
;
436 static nv50_ir::SVSemantic
translateSysVal(uint sysval
)
439 case TGSI_SEMANTIC_FACE
: return nv50_ir::SV_FACE
;
440 case TGSI_SEMANTIC_PSIZE
: return nv50_ir::SV_POINT_SIZE
;
441 case TGSI_SEMANTIC_PRIMID
: return nv50_ir::SV_PRIMITIVE_ID
;
442 case TGSI_SEMANTIC_INSTANCEID
: return nv50_ir::SV_INSTANCE_ID
;
443 case TGSI_SEMANTIC_VERTEXID
: return nv50_ir::SV_VERTEX_ID
;
444 case TGSI_SEMANTIC_GRID_SIZE
: return nv50_ir::SV_NCTAID
;
445 case TGSI_SEMANTIC_BLOCK_ID
: return nv50_ir::SV_CTAID
;
446 case TGSI_SEMANTIC_BLOCK_SIZE
: return nv50_ir::SV_NTID
;
447 case TGSI_SEMANTIC_THREAD_ID
: return nv50_ir::SV_TID
;
448 case TGSI_SEMANTIC_SAMPLEID
: return nv50_ir::SV_SAMPLE_INDEX
;
449 case TGSI_SEMANTIC_SAMPLEPOS
: return nv50_ir::SV_SAMPLE_POS
;
450 case TGSI_SEMANTIC_SAMPLEMASK
: return nv50_ir::SV_SAMPLE_MASK
;
451 case TGSI_SEMANTIC_INVOCATIONID
: return nv50_ir::SV_INVOCATION_ID
;
452 case TGSI_SEMANTIC_TESSCOORD
: return nv50_ir::SV_TESS_COORD
;
453 case TGSI_SEMANTIC_TESSOUTER
: return nv50_ir::SV_TESS_OUTER
;
454 case TGSI_SEMANTIC_TESSINNER
: return nv50_ir::SV_TESS_INNER
;
455 case TGSI_SEMANTIC_VERTICESIN
: return nv50_ir::SV_VERTEX_COUNT
;
456 case TGSI_SEMANTIC_HELPER_INVOCATION
: return nv50_ir::SV_THREAD_KILL
;
457 case TGSI_SEMANTIC_BASEVERTEX
: return nv50_ir::SV_BASEVERTEX
;
458 case TGSI_SEMANTIC_BASEINSTANCE
: return nv50_ir::SV_BASEINSTANCE
;
459 case TGSI_SEMANTIC_DRAWID
: return nv50_ir::SV_DRAWID
;
460 case TGSI_SEMANTIC_WORK_DIM
: return nv50_ir::SV_WORK_DIM
;
461 case TGSI_SEMANTIC_SUBGROUP_INVOCATION
: return nv50_ir::SV_LANEID
;
462 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
: return nv50_ir::SV_LANEMASK_EQ
;
463 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
: return nv50_ir::SV_LANEMASK_LT
;
464 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
: return nv50_ir::SV_LANEMASK_LE
;
465 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
: return nv50_ir::SV_LANEMASK_GT
;
466 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
: return nv50_ir::SV_LANEMASK_GE
;
469 return nv50_ir::SV_CLOCK
;
473 #define NV50_IR_TEX_TARG_CASE(a, b) \
474 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
476 static nv50_ir::TexTarget
translateTexture(uint tex
)
479 NV50_IR_TEX_TARG_CASE(1D
, 1D
);
480 NV50_IR_TEX_TARG_CASE(2D
, 2D
);
481 NV50_IR_TEX_TARG_CASE(2D_MSAA
, 2D_MS
);
482 NV50_IR_TEX_TARG_CASE(3D
, 3D
);
483 NV50_IR_TEX_TARG_CASE(CUBE
, CUBE
);
484 NV50_IR_TEX_TARG_CASE(RECT
, RECT
);
485 NV50_IR_TEX_TARG_CASE(1D_ARRAY
, 1D_ARRAY
);
486 NV50_IR_TEX_TARG_CASE(2D_ARRAY
, 2D_ARRAY
);
487 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA
, 2D_MS_ARRAY
);
488 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY
, CUBE_ARRAY
);
489 NV50_IR_TEX_TARG_CASE(SHADOW1D
, 1D_SHADOW
);
490 NV50_IR_TEX_TARG_CASE(SHADOW2D
, 2D_SHADOW
);
491 NV50_IR_TEX_TARG_CASE(SHADOWCUBE
, CUBE_SHADOW
);
492 NV50_IR_TEX_TARG_CASE(SHADOWRECT
, RECT_SHADOW
);
493 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY
, 1D_ARRAY_SHADOW
);
494 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY
, 2D_ARRAY_SHADOW
);
495 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY
, CUBE_ARRAY_SHADOW
);
496 NV50_IR_TEX_TARG_CASE(BUFFER
, BUFFER
);
498 case TGSI_TEXTURE_UNKNOWN
:
500 assert(!"invalid texture target");
501 return nv50_ir::TEX_TARGET_2D
;
505 static nv50_ir::CacheMode
translateCacheMode(uint qualifier
)
507 if (qualifier
& TGSI_MEMORY_VOLATILE
)
508 return nv50_ir::CACHE_CV
;
509 if (qualifier
& TGSI_MEMORY_COHERENT
)
510 return nv50_ir::CACHE_CG
;
511 return nv50_ir::CACHE_CA
;
514 nv50_ir::DataType
Instruction::inferSrcType() const
516 switch (getOpcode()) {
517 case TGSI_OPCODE_UIF
:
518 case TGSI_OPCODE_AND
:
520 case TGSI_OPCODE_XOR
:
521 case TGSI_OPCODE_NOT
:
522 case TGSI_OPCODE_SHL
:
523 case TGSI_OPCODE_U2F
:
524 case TGSI_OPCODE_U2D
:
525 case TGSI_OPCODE_U2I64
:
526 case TGSI_OPCODE_UADD
:
527 case TGSI_OPCODE_UDIV
:
528 case TGSI_OPCODE_UMOD
:
529 case TGSI_OPCODE_UMAD
:
530 case TGSI_OPCODE_UMUL
:
531 case TGSI_OPCODE_UMUL_HI
:
532 case TGSI_OPCODE_UMAX
:
533 case TGSI_OPCODE_UMIN
:
534 case TGSI_OPCODE_USEQ
:
535 case TGSI_OPCODE_USGE
:
536 case TGSI_OPCODE_USLT
:
537 case TGSI_OPCODE_USNE
:
538 case TGSI_OPCODE_USHR
:
539 case TGSI_OPCODE_ATOMUADD
:
540 case TGSI_OPCODE_ATOMXCHG
:
541 case TGSI_OPCODE_ATOMCAS
:
542 case TGSI_OPCODE_ATOMAND
:
543 case TGSI_OPCODE_ATOMOR
:
544 case TGSI_OPCODE_ATOMXOR
:
545 case TGSI_OPCODE_ATOMUMIN
:
546 case TGSI_OPCODE_ATOMUMAX
:
547 case TGSI_OPCODE_ATOMDEC_WRAP
:
548 case TGSI_OPCODE_ATOMINC_WRAP
:
549 case TGSI_OPCODE_UBFE
:
550 case TGSI_OPCODE_UMSB
:
551 case TGSI_OPCODE_UP2H
:
552 case TGSI_OPCODE_VOTE_ALL
:
553 case TGSI_OPCODE_VOTE_ANY
:
554 case TGSI_OPCODE_VOTE_EQ
:
555 return nv50_ir::TYPE_U32
;
556 case TGSI_OPCODE_I2F
:
557 case TGSI_OPCODE_I2D
:
558 case TGSI_OPCODE_I2I64
:
559 case TGSI_OPCODE_IDIV
:
560 case TGSI_OPCODE_IMUL_HI
:
561 case TGSI_OPCODE_IMAX
:
562 case TGSI_OPCODE_IMIN
:
563 case TGSI_OPCODE_IABS
:
564 case TGSI_OPCODE_INEG
:
565 case TGSI_OPCODE_ISGE
:
566 case TGSI_OPCODE_ISHR
:
567 case TGSI_OPCODE_ISLT
:
568 case TGSI_OPCODE_ISSG
:
569 case TGSI_OPCODE_MOD
:
570 case TGSI_OPCODE_UARL
:
571 case TGSI_OPCODE_ATOMIMIN
:
572 case TGSI_OPCODE_ATOMIMAX
:
573 case TGSI_OPCODE_IBFE
:
574 case TGSI_OPCODE_IMSB
:
575 return nv50_ir::TYPE_S32
;
576 case TGSI_OPCODE_D2F
:
577 case TGSI_OPCODE_D2I
:
578 case TGSI_OPCODE_D2U
:
579 case TGSI_OPCODE_D2I64
:
580 case TGSI_OPCODE_D2U64
:
581 case TGSI_OPCODE_DABS
:
582 case TGSI_OPCODE_DNEG
:
583 case TGSI_OPCODE_DADD
:
584 case TGSI_OPCODE_DMUL
:
585 case TGSI_OPCODE_DDIV
:
586 case TGSI_OPCODE_DMAX
:
587 case TGSI_OPCODE_DMIN
:
588 case TGSI_OPCODE_DSLT
:
589 case TGSI_OPCODE_DSGE
:
590 case TGSI_OPCODE_DSEQ
:
591 case TGSI_OPCODE_DSNE
:
592 case TGSI_OPCODE_DRCP
:
593 case TGSI_OPCODE_DSQRT
:
594 case TGSI_OPCODE_DMAD
:
595 case TGSI_OPCODE_DFMA
:
596 case TGSI_OPCODE_DFRAC
:
597 case TGSI_OPCODE_DRSQ
:
598 case TGSI_OPCODE_DTRUNC
:
599 case TGSI_OPCODE_DCEIL
:
600 case TGSI_OPCODE_DFLR
:
601 case TGSI_OPCODE_DROUND
:
602 return nv50_ir::TYPE_F64
;
603 case TGSI_OPCODE_U64SEQ
:
604 case TGSI_OPCODE_U64SNE
:
605 case TGSI_OPCODE_U64SLT
:
606 case TGSI_OPCODE_U64SGE
:
607 case TGSI_OPCODE_U64MIN
:
608 case TGSI_OPCODE_U64MAX
:
609 case TGSI_OPCODE_U64ADD
:
610 case TGSI_OPCODE_U64MUL
:
611 case TGSI_OPCODE_U64SHL
:
612 case TGSI_OPCODE_U64SHR
:
613 case TGSI_OPCODE_U64DIV
:
614 case TGSI_OPCODE_U64MOD
:
615 case TGSI_OPCODE_U642F
:
616 case TGSI_OPCODE_U642D
:
617 return nv50_ir::TYPE_U64
;
618 case TGSI_OPCODE_I64ABS
:
619 case TGSI_OPCODE_I64SSG
:
620 case TGSI_OPCODE_I64NEG
:
621 case TGSI_OPCODE_I64SLT
:
622 case TGSI_OPCODE_I64SGE
:
623 case TGSI_OPCODE_I64MIN
:
624 case TGSI_OPCODE_I64MAX
:
625 case TGSI_OPCODE_I64SHR
:
626 case TGSI_OPCODE_I64DIV
:
627 case TGSI_OPCODE_I64MOD
:
628 case TGSI_OPCODE_I642F
:
629 case TGSI_OPCODE_I642D
:
630 return nv50_ir::TYPE_S64
;
632 return nv50_ir::TYPE_F32
;
636 nv50_ir::DataType
Instruction::inferDstType() const
638 switch (getOpcode()) {
639 case TGSI_OPCODE_D2U
:
640 case TGSI_OPCODE_F2U
: return nv50_ir::TYPE_U32
;
641 case TGSI_OPCODE_D2I
:
642 case TGSI_OPCODE_F2I
: return nv50_ir::TYPE_S32
;
643 case TGSI_OPCODE_FSEQ
:
644 case TGSI_OPCODE_FSGE
:
645 case TGSI_OPCODE_FSLT
:
646 case TGSI_OPCODE_FSNE
:
647 case TGSI_OPCODE_DSEQ
:
648 case TGSI_OPCODE_DSGE
:
649 case TGSI_OPCODE_DSLT
:
650 case TGSI_OPCODE_DSNE
:
651 case TGSI_OPCODE_I64SLT
:
652 case TGSI_OPCODE_I64SGE
:
653 case TGSI_OPCODE_U64SEQ
:
654 case TGSI_OPCODE_U64SNE
:
655 case TGSI_OPCODE_U64SLT
:
656 case TGSI_OPCODE_U64SGE
:
657 case TGSI_OPCODE_PK2H
:
658 return nv50_ir::TYPE_U32
;
659 case TGSI_OPCODE_I2F
:
660 case TGSI_OPCODE_U2F
:
661 case TGSI_OPCODE_D2F
:
662 case TGSI_OPCODE_I642F
:
663 case TGSI_OPCODE_U642F
:
664 case TGSI_OPCODE_UP2H
:
665 return nv50_ir::TYPE_F32
;
666 case TGSI_OPCODE_I2D
:
667 case TGSI_OPCODE_U2D
:
668 case TGSI_OPCODE_F2D
:
669 case TGSI_OPCODE_I642D
:
670 case TGSI_OPCODE_U642D
:
671 return nv50_ir::TYPE_F64
;
672 case TGSI_OPCODE_I2I64
:
673 case TGSI_OPCODE_U2I64
:
674 case TGSI_OPCODE_F2I64
:
675 case TGSI_OPCODE_D2I64
:
676 return nv50_ir::TYPE_S64
;
677 case TGSI_OPCODE_F2U64
:
678 case TGSI_OPCODE_D2U64
:
679 return nv50_ir::TYPE_U64
;
681 return inferSrcType();
685 nv50_ir::CondCode
Instruction::getSetCond() const
687 using namespace nv50_ir
;
689 switch (getOpcode()) {
690 case TGSI_OPCODE_SLT
:
691 case TGSI_OPCODE_ISLT
:
692 case TGSI_OPCODE_USLT
:
693 case TGSI_OPCODE_FSLT
:
694 case TGSI_OPCODE_DSLT
:
695 case TGSI_OPCODE_I64SLT
:
696 case TGSI_OPCODE_U64SLT
:
698 case TGSI_OPCODE_SLE
:
700 case TGSI_OPCODE_SGE
:
701 case TGSI_OPCODE_ISGE
:
702 case TGSI_OPCODE_USGE
:
703 case TGSI_OPCODE_FSGE
:
704 case TGSI_OPCODE_DSGE
:
705 case TGSI_OPCODE_I64SGE
:
706 case TGSI_OPCODE_U64SGE
:
708 case TGSI_OPCODE_SGT
:
710 case TGSI_OPCODE_SEQ
:
711 case TGSI_OPCODE_USEQ
:
712 case TGSI_OPCODE_FSEQ
:
713 case TGSI_OPCODE_DSEQ
:
714 case TGSI_OPCODE_U64SEQ
:
716 case TGSI_OPCODE_SNE
:
717 case TGSI_OPCODE_FSNE
:
718 case TGSI_OPCODE_DSNE
:
719 case TGSI_OPCODE_U64SNE
:
721 case TGSI_OPCODE_USNE
:
728 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
730 static nv50_ir::operation
translateOpcode(uint opcode
)
733 NV50_IR_OPCODE_CASE(ARL
, SHL
);
734 NV50_IR_OPCODE_CASE(MOV
, MOV
);
736 NV50_IR_OPCODE_CASE(RCP
, RCP
);
737 NV50_IR_OPCODE_CASE(RSQ
, RSQ
);
738 NV50_IR_OPCODE_CASE(SQRT
, SQRT
);
740 NV50_IR_OPCODE_CASE(MUL
, MUL
);
741 NV50_IR_OPCODE_CASE(ADD
, ADD
);
743 NV50_IR_OPCODE_CASE(MIN
, MIN
);
744 NV50_IR_OPCODE_CASE(MAX
, MAX
);
745 NV50_IR_OPCODE_CASE(SLT
, SET
);
746 NV50_IR_OPCODE_CASE(SGE
, SET
);
747 NV50_IR_OPCODE_CASE(MAD
, MAD
);
748 NV50_IR_OPCODE_CASE(FMA
, FMA
);
750 NV50_IR_OPCODE_CASE(FLR
, FLOOR
);
751 NV50_IR_OPCODE_CASE(ROUND
, CVT
);
752 NV50_IR_OPCODE_CASE(EX2
, EX2
);
753 NV50_IR_OPCODE_CASE(LG2
, LG2
);
754 NV50_IR_OPCODE_CASE(POW
, POW
);
756 NV50_IR_OPCODE_CASE(COS
, COS
);
757 NV50_IR_OPCODE_CASE(DDX
, DFDX
);
758 NV50_IR_OPCODE_CASE(DDX_FINE
, DFDX
);
759 NV50_IR_OPCODE_CASE(DDY
, DFDY
);
760 NV50_IR_OPCODE_CASE(DDY_FINE
, DFDY
);
761 NV50_IR_OPCODE_CASE(KILL
, DISCARD
);
762 NV50_IR_OPCODE_CASE(DEMOTE
, DISCARD
);
764 NV50_IR_OPCODE_CASE(SEQ
, SET
);
765 NV50_IR_OPCODE_CASE(SGT
, SET
);
766 NV50_IR_OPCODE_CASE(SIN
, SIN
);
767 NV50_IR_OPCODE_CASE(SLE
, SET
);
768 NV50_IR_OPCODE_CASE(SNE
, SET
);
769 NV50_IR_OPCODE_CASE(TEX
, TEX
);
770 NV50_IR_OPCODE_CASE(TXD
, TXD
);
771 NV50_IR_OPCODE_CASE(TXP
, TEX
);
773 NV50_IR_OPCODE_CASE(CAL
, CALL
);
774 NV50_IR_OPCODE_CASE(RET
, RET
);
775 NV50_IR_OPCODE_CASE(CMP
, SLCT
);
777 NV50_IR_OPCODE_CASE(TXB
, TXB
);
779 NV50_IR_OPCODE_CASE(DIV
, DIV
);
781 NV50_IR_OPCODE_CASE(TXL
, TXL
);
782 NV50_IR_OPCODE_CASE(TEX_LZ
, TXL
);
784 NV50_IR_OPCODE_CASE(CEIL
, CEIL
);
785 NV50_IR_OPCODE_CASE(I2F
, CVT
);
786 NV50_IR_OPCODE_CASE(NOT
, NOT
);
787 NV50_IR_OPCODE_CASE(TRUNC
, TRUNC
);
788 NV50_IR_OPCODE_CASE(SHL
, SHL
);
790 NV50_IR_OPCODE_CASE(AND
, AND
);
791 NV50_IR_OPCODE_CASE(OR
, OR
);
792 NV50_IR_OPCODE_CASE(MOD
, MOD
);
793 NV50_IR_OPCODE_CASE(XOR
, XOR
);
794 NV50_IR_OPCODE_CASE(TXF
, TXF
);
795 NV50_IR_OPCODE_CASE(TXF_LZ
, TXF
);
796 NV50_IR_OPCODE_CASE(TXQ
, TXQ
);
797 NV50_IR_OPCODE_CASE(TXQS
, TXQ
);
798 NV50_IR_OPCODE_CASE(TG4
, TXG
);
799 NV50_IR_OPCODE_CASE(LODQ
, TXLQ
);
801 NV50_IR_OPCODE_CASE(EMIT
, EMIT
);
802 NV50_IR_OPCODE_CASE(ENDPRIM
, RESTART
);
804 NV50_IR_OPCODE_CASE(KILL_IF
, DISCARD
);
806 NV50_IR_OPCODE_CASE(F2I
, CVT
);
807 NV50_IR_OPCODE_CASE(FSEQ
, SET
);
808 NV50_IR_OPCODE_CASE(FSGE
, SET
);
809 NV50_IR_OPCODE_CASE(FSLT
, SET
);
810 NV50_IR_OPCODE_CASE(FSNE
, SET
);
811 NV50_IR_OPCODE_CASE(IDIV
, DIV
);
812 NV50_IR_OPCODE_CASE(IMAX
, MAX
);
813 NV50_IR_OPCODE_CASE(IMIN
, MIN
);
814 NV50_IR_OPCODE_CASE(IABS
, ABS
);
815 NV50_IR_OPCODE_CASE(INEG
, NEG
);
816 NV50_IR_OPCODE_CASE(ISGE
, SET
);
817 NV50_IR_OPCODE_CASE(ISHR
, SHR
);
818 NV50_IR_OPCODE_CASE(ISLT
, SET
);
819 NV50_IR_OPCODE_CASE(F2U
, CVT
);
820 NV50_IR_OPCODE_CASE(U2F
, CVT
);
821 NV50_IR_OPCODE_CASE(UADD
, ADD
);
822 NV50_IR_OPCODE_CASE(UDIV
, DIV
);
823 NV50_IR_OPCODE_CASE(UMAD
, MAD
);
824 NV50_IR_OPCODE_CASE(UMAX
, MAX
);
825 NV50_IR_OPCODE_CASE(UMIN
, MIN
);
826 NV50_IR_OPCODE_CASE(UMOD
, MOD
);
827 NV50_IR_OPCODE_CASE(UMUL
, MUL
);
828 NV50_IR_OPCODE_CASE(USEQ
, SET
);
829 NV50_IR_OPCODE_CASE(USGE
, SET
);
830 NV50_IR_OPCODE_CASE(USHR
, SHR
);
831 NV50_IR_OPCODE_CASE(USLT
, SET
);
832 NV50_IR_OPCODE_CASE(USNE
, SET
);
834 NV50_IR_OPCODE_CASE(DABS
, ABS
);
835 NV50_IR_OPCODE_CASE(DNEG
, NEG
);
836 NV50_IR_OPCODE_CASE(DADD
, ADD
);
837 NV50_IR_OPCODE_CASE(DMUL
, MUL
);
838 NV50_IR_OPCODE_CASE(DDIV
, DIV
);
839 NV50_IR_OPCODE_CASE(DMAX
, MAX
);
840 NV50_IR_OPCODE_CASE(DMIN
, MIN
);
841 NV50_IR_OPCODE_CASE(DSLT
, SET
);
842 NV50_IR_OPCODE_CASE(DSGE
, SET
);
843 NV50_IR_OPCODE_CASE(DSEQ
, SET
);
844 NV50_IR_OPCODE_CASE(DSNE
, SET
);
845 NV50_IR_OPCODE_CASE(DRCP
, RCP
);
846 NV50_IR_OPCODE_CASE(DSQRT
, SQRT
);
847 NV50_IR_OPCODE_CASE(DMAD
, MAD
);
848 NV50_IR_OPCODE_CASE(DFMA
, FMA
);
849 NV50_IR_OPCODE_CASE(D2I
, CVT
);
850 NV50_IR_OPCODE_CASE(D2U
, CVT
);
851 NV50_IR_OPCODE_CASE(I2D
, CVT
);
852 NV50_IR_OPCODE_CASE(U2D
, CVT
);
853 NV50_IR_OPCODE_CASE(DRSQ
, RSQ
);
854 NV50_IR_OPCODE_CASE(DTRUNC
, TRUNC
);
855 NV50_IR_OPCODE_CASE(DCEIL
, CEIL
);
856 NV50_IR_OPCODE_CASE(DFLR
, FLOOR
);
857 NV50_IR_OPCODE_CASE(DROUND
, CVT
);
859 NV50_IR_OPCODE_CASE(U64SEQ
, SET
);
860 NV50_IR_OPCODE_CASE(U64SNE
, SET
);
861 NV50_IR_OPCODE_CASE(U64SLT
, SET
);
862 NV50_IR_OPCODE_CASE(U64SGE
, SET
);
863 NV50_IR_OPCODE_CASE(I64SLT
, SET
);
864 NV50_IR_OPCODE_CASE(I64SGE
, SET
);
865 NV50_IR_OPCODE_CASE(I2I64
, CVT
);
866 NV50_IR_OPCODE_CASE(U2I64
, CVT
);
867 NV50_IR_OPCODE_CASE(F2I64
, CVT
);
868 NV50_IR_OPCODE_CASE(F2U64
, CVT
);
869 NV50_IR_OPCODE_CASE(D2I64
, CVT
);
870 NV50_IR_OPCODE_CASE(D2U64
, CVT
);
871 NV50_IR_OPCODE_CASE(I642F
, CVT
);
872 NV50_IR_OPCODE_CASE(U642F
, CVT
);
873 NV50_IR_OPCODE_CASE(I642D
, CVT
);
874 NV50_IR_OPCODE_CASE(U642D
, CVT
);
876 NV50_IR_OPCODE_CASE(I64MIN
, MIN
);
877 NV50_IR_OPCODE_CASE(U64MIN
, MIN
);
878 NV50_IR_OPCODE_CASE(I64MAX
, MAX
);
879 NV50_IR_OPCODE_CASE(U64MAX
, MAX
);
880 NV50_IR_OPCODE_CASE(I64ABS
, ABS
);
881 NV50_IR_OPCODE_CASE(I64NEG
, NEG
);
882 NV50_IR_OPCODE_CASE(U64ADD
, ADD
);
883 NV50_IR_OPCODE_CASE(U64MUL
, MUL
);
884 NV50_IR_OPCODE_CASE(U64SHL
, SHL
);
885 NV50_IR_OPCODE_CASE(I64SHR
, SHR
);
886 NV50_IR_OPCODE_CASE(U64SHR
, SHR
);
888 NV50_IR_OPCODE_CASE(IMUL_HI
, MUL
);
889 NV50_IR_OPCODE_CASE(UMUL_HI
, MUL
);
891 NV50_IR_OPCODE_CASE(SAMPLE
, TEX
);
892 NV50_IR_OPCODE_CASE(SAMPLE_B
, TXB
);
893 NV50_IR_OPCODE_CASE(SAMPLE_C
, TEX
);
894 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ
, TEX
);
895 NV50_IR_OPCODE_CASE(SAMPLE_D
, TXD
);
896 NV50_IR_OPCODE_CASE(SAMPLE_L
, TXL
);
897 NV50_IR_OPCODE_CASE(SAMPLE_I
, TXF
);
898 NV50_IR_OPCODE_CASE(SAMPLE_I_MS
, TXF
);
899 NV50_IR_OPCODE_CASE(GATHER4
, TXG
);
900 NV50_IR_OPCODE_CASE(SVIEWINFO
, TXQ
);
902 NV50_IR_OPCODE_CASE(ATOMUADD
, ATOM
);
903 NV50_IR_OPCODE_CASE(ATOMXCHG
, ATOM
);
904 NV50_IR_OPCODE_CASE(ATOMCAS
, ATOM
);
905 NV50_IR_OPCODE_CASE(ATOMAND
, ATOM
);
906 NV50_IR_OPCODE_CASE(ATOMOR
, ATOM
);
907 NV50_IR_OPCODE_CASE(ATOMXOR
, ATOM
);
908 NV50_IR_OPCODE_CASE(ATOMUMIN
, ATOM
);
909 NV50_IR_OPCODE_CASE(ATOMUMAX
, ATOM
);
910 NV50_IR_OPCODE_CASE(ATOMIMIN
, ATOM
);
911 NV50_IR_OPCODE_CASE(ATOMIMAX
, ATOM
);
912 NV50_IR_OPCODE_CASE(ATOMFADD
, ATOM
);
913 NV50_IR_OPCODE_CASE(ATOMDEC_WRAP
, ATOM
);
914 NV50_IR_OPCODE_CASE(ATOMINC_WRAP
, ATOM
);
916 NV50_IR_OPCODE_CASE(TEX2
, TEX
);
917 NV50_IR_OPCODE_CASE(TXB2
, TXB
);
918 NV50_IR_OPCODE_CASE(TXL2
, TXL
);
920 NV50_IR_OPCODE_CASE(IBFE
, EXTBF
);
921 NV50_IR_OPCODE_CASE(UBFE
, EXTBF
);
922 NV50_IR_OPCODE_CASE(BFI
, INSBF
);
923 NV50_IR_OPCODE_CASE(BREV
, EXTBF
);
924 NV50_IR_OPCODE_CASE(POPC
, POPCNT
);
925 NV50_IR_OPCODE_CASE(LSB
, BFIND
);
926 NV50_IR_OPCODE_CASE(IMSB
, BFIND
);
927 NV50_IR_OPCODE_CASE(UMSB
, BFIND
);
929 NV50_IR_OPCODE_CASE(VOTE_ALL
, VOTE
);
930 NV50_IR_OPCODE_CASE(VOTE_ANY
, VOTE
);
931 NV50_IR_OPCODE_CASE(VOTE_EQ
, VOTE
);
933 NV50_IR_OPCODE_CASE(BALLOT
, VOTE
);
934 NV50_IR_OPCODE_CASE(READ_INVOC
, SHFL
);
935 NV50_IR_OPCODE_CASE(READ_FIRST
, SHFL
);
937 NV50_IR_OPCODE_CASE(END
, EXIT
);
940 return nv50_ir::OP_NOP
;
944 static uint16_t opcodeToSubOp(uint opcode
)
947 case TGSI_OPCODE_ATOMUADD
: return NV50_IR_SUBOP_ATOM_ADD
;
948 case TGSI_OPCODE_ATOMXCHG
: return NV50_IR_SUBOP_ATOM_EXCH
;
949 case TGSI_OPCODE_ATOMCAS
: return NV50_IR_SUBOP_ATOM_CAS
;
950 case TGSI_OPCODE_ATOMAND
: return NV50_IR_SUBOP_ATOM_AND
;
951 case TGSI_OPCODE_ATOMOR
: return NV50_IR_SUBOP_ATOM_OR
;
952 case TGSI_OPCODE_ATOMXOR
: return NV50_IR_SUBOP_ATOM_XOR
;
953 case TGSI_OPCODE_ATOMUMIN
: return NV50_IR_SUBOP_ATOM_MIN
;
954 case TGSI_OPCODE_ATOMIMIN
: return NV50_IR_SUBOP_ATOM_MIN
;
955 case TGSI_OPCODE_ATOMUMAX
: return NV50_IR_SUBOP_ATOM_MAX
;
956 case TGSI_OPCODE_ATOMIMAX
: return NV50_IR_SUBOP_ATOM_MAX
;
957 case TGSI_OPCODE_ATOMFADD
: return NV50_IR_SUBOP_ATOM_ADD
;
958 case TGSI_OPCODE_ATOMDEC_WRAP
: return NV50_IR_SUBOP_ATOM_DEC
;
959 case TGSI_OPCODE_ATOMINC_WRAP
: return NV50_IR_SUBOP_ATOM_INC
;
960 case TGSI_OPCODE_IMUL_HI
:
961 case TGSI_OPCODE_UMUL_HI
:
962 return NV50_IR_SUBOP_MUL_HIGH
;
963 case TGSI_OPCODE_VOTE_ALL
: return NV50_IR_SUBOP_VOTE_ALL
;
964 case TGSI_OPCODE_VOTE_ANY
: return NV50_IR_SUBOP_VOTE_ANY
;
965 case TGSI_OPCODE_VOTE_EQ
: return NV50_IR_SUBOP_VOTE_UNI
;
971 bool Instruction::checkDstSrcAliasing() const
973 if (insn
->Dst
[0].Register
.Indirect
) // no danger if indirect, using memory
976 for (int s
= 0; s
< TGSI_FULL_MAX_SRC_REGISTERS
; ++s
) {
977 if (insn
->Src
[s
].Register
.File
== TGSI_FILE_NULL
)
979 if (insn
->Src
[s
].Register
.File
== insn
->Dst
[0].Register
.File
&&
980 insn
->Src
[s
].Register
.Index
== insn
->Dst
[0].Register
.Index
)
989 Source(struct nv50_ir_prog_info
*);
994 unsigned fileSize(unsigned file
) const { return scan
.file_max
[file
] + 1; }
997 struct tgsi_shader_info scan
;
998 struct tgsi_full_instruction
*insns
;
999 const struct tgsi_token
*tokens
;
1000 struct nv50_ir_prog_info
*info
;
1002 nv50_ir::DynArray tempArrays
;
1003 nv50_ir::DynArray immdArrays
;
1005 typedef nv50_ir::BuildUtil::Location Location
;
1006 // these registers are per-subroutine, cannot be used for parameter passing
1007 std::set
<Location
> locals
;
1009 std::set
<int> indirectTempArrays
;
1010 std::map
<int, int> indirectTempOffsets
;
1011 std::map
<int, std::pair
<int, int> > tempArrayInfo
;
1012 std::vector
<int> tempArrayId
;
1014 int clipVertexOutput
;
1016 struct TextureView
{
1017 uint8_t target
; // TGSI_TEXTURE_*
1019 std::vector
<TextureView
> textureViews
;
1023 uint8_t target; // TGSI_TEXTURE_*
1025 uint8_t slot; // $surface index
1027 std::vector<Resource> resources;
1031 uint8_t mem_type
; // TGSI_MEMORY_TYPE_*
1033 std::vector
<MemoryFile
> memoryFiles
;
1035 std::vector
<bool> bufferAtomics
;
1038 int inferSysValDirection(unsigned sn
) const;
1039 bool scanDeclaration(const struct tgsi_full_declaration
*);
1040 bool scanInstruction(const struct tgsi_full_instruction
*);
1041 void scanInstructionSrc(const Instruction
& insn
,
1042 const Instruction::SrcRegister
& src
,
1044 void scanProperty(const struct tgsi_full_property
*);
1045 void scanImmediate(const struct tgsi_full_immediate
*);
1047 inline bool isEdgeFlagPassthrough(const Instruction
&) const;
1050 Source::Source(struct nv50_ir_prog_info
*prog
) : info(prog
)
1052 tokens
= (const struct tgsi_token
*)info
->bin
.source
;
1054 if (prog
->dbgFlags
& NV50_IR_DEBUG_BASIC
)
1055 tgsi_dump(tokens
, 0);
1063 if (info
->immd
.data
)
1064 FREE(info
->immd
.data
);
1065 if (info
->immd
.type
)
1066 FREE(info
->immd
.type
);
1069 bool Source::scanSource()
1071 unsigned insnCount
= 0;
1072 struct tgsi_parse_context parse
;
1074 tgsi_scan_shader(tokens
, &scan
);
1076 insns
= (struct tgsi_full_instruction
*)MALLOC(scan
.num_instructions
*
1081 clipVertexOutput
= -1;
1083 textureViews
.resize(scan
.file_max
[TGSI_FILE_SAMPLER_VIEW
] + 1);
1084 //resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
1085 tempArrayId
.resize(scan
.file_max
[TGSI_FILE_TEMPORARY
] + 1);
1086 memoryFiles
.resize(scan
.file_max
[TGSI_FILE_MEMORY
] + 1);
1087 bufferAtomics
.resize(scan
.file_max
[TGSI_FILE_BUFFER
] + 1);
1089 info
->immd
.bufSize
= 0;
1091 info
->numInputs
= scan
.file_max
[TGSI_FILE_INPUT
] + 1;
1092 info
->numOutputs
= scan
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1093 info
->numSysVals
= scan
.file_max
[TGSI_FILE_SYSTEM_VALUE
] + 1;
1095 if (info
->type
== PIPE_SHADER_FRAGMENT
) {
1096 info
->prop
.fp
.writesDepth
= scan
.writes_z
;
1097 info
->prop
.fp
.usesDiscard
= scan
.uses_kill
|| info
->io
.alphaRefBase
;
1099 if (info
->type
== PIPE_SHADER_GEOMETRY
) {
1100 info
->prop
.gp
.instanceCount
= 1; // default value
1103 info
->io
.viewportId
= -1;
1105 info
->immd
.data
= (uint32_t *)MALLOC(scan
.immediate_count
* 16);
1106 info
->immd
.type
= (ubyte
*)MALLOC(scan
.immediate_count
* sizeof(ubyte
));
1108 tgsi_parse_init(&parse
, tokens
);
1109 while (!tgsi_parse_end_of_tokens(&parse
)) {
1110 tgsi_parse_token(&parse
);
1112 switch (parse
.FullToken
.Token
.Type
) {
1113 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1114 scanImmediate(&parse
.FullToken
.FullImmediate
);
1116 case TGSI_TOKEN_TYPE_DECLARATION
:
1117 scanDeclaration(&parse
.FullToken
.FullDeclaration
);
1119 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1120 insns
[insnCount
++] = parse
.FullToken
.FullInstruction
;
1121 scanInstruction(&parse
.FullToken
.FullInstruction
);
1123 case TGSI_TOKEN_TYPE_PROPERTY
:
1124 scanProperty(&parse
.FullToken
.FullProperty
);
1127 INFO("unknown TGSI token type: %d\n", parse
.FullToken
.Token
.Type
);
1131 tgsi_parse_free(&parse
);
1133 if (indirectTempArrays
.size()) {
1135 for (std::set
<int>::const_iterator it
= indirectTempArrays
.begin();
1136 it
!= indirectTempArrays
.end(); ++it
) {
1137 std::pair
<int, int>& info
= tempArrayInfo
[*it
];
1138 indirectTempOffsets
.insert(std::make_pair(*it
, tempBase
- info
.first
));
1139 tempBase
+= info
.second
;
1141 info
->bin
.tlsSpace
+= tempBase
* 16;
1144 if (info
->io
.genUserClip
> 0) {
1145 info
->io
.clipDistances
= info
->io
.genUserClip
;
1147 const unsigned int nOut
= (info
->io
.genUserClip
+ 3) / 4;
1149 for (unsigned int n
= 0; n
< nOut
; ++n
) {
1150 unsigned int i
= info
->numOutputs
++;
1151 info
->out
[i
].id
= i
;
1152 info
->out
[i
].sn
= TGSI_SEMANTIC_CLIPDIST
;
1153 info
->out
[i
].si
= n
;
1154 info
->out
[i
].mask
= ((1 << info
->io
.clipDistances
) - 1) >> (n
* 4);
1158 return info
->assignSlots(info
) == 0;
1161 void Source::scanProperty(const struct tgsi_full_property
*prop
)
1163 switch (prop
->Property
.PropertyName
) {
1164 case TGSI_PROPERTY_GS_OUTPUT_PRIM
:
1165 info
->prop
.gp
.outputPrim
= prop
->u
[0].Data
;
1167 case TGSI_PROPERTY_GS_INPUT_PRIM
:
1168 info
->prop
.gp
.inputPrim
= prop
->u
[0].Data
;
1170 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
:
1171 info
->prop
.gp
.maxVertices
= prop
->u
[0].Data
;
1173 case TGSI_PROPERTY_GS_INVOCATIONS
:
1174 info
->prop
.gp
.instanceCount
= prop
->u
[0].Data
;
1176 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
1177 info
->prop
.fp
.separateFragData
= true;
1179 case TGSI_PROPERTY_FS_COORD_ORIGIN
:
1180 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
:
1181 case TGSI_PROPERTY_FS_DEPTH_LAYOUT
:
1184 case TGSI_PROPERTY_VS_PROHIBIT_UCPS
:
1185 info
->io
.genUserClip
= -1;
1187 case TGSI_PROPERTY_TCS_VERTICES_OUT
:
1188 info
->prop
.tp
.outputPatchSize
= prop
->u
[0].Data
;
1190 case TGSI_PROPERTY_TES_PRIM_MODE
:
1191 info
->prop
.tp
.domain
= prop
->u
[0].Data
;
1193 case TGSI_PROPERTY_TES_SPACING
:
1194 info
->prop
.tp
.partitioning
= prop
->u
[0].Data
;
1196 case TGSI_PROPERTY_TES_VERTEX_ORDER_CW
:
1197 info
->prop
.tp
.winding
= prop
->u
[0].Data
;
1199 case TGSI_PROPERTY_TES_POINT_MODE
:
1200 if (prop
->u
[0].Data
)
1201 info
->prop
.tp
.outputPrim
= PIPE_PRIM_POINTS
;
1203 info
->prop
.tp
.outputPrim
= PIPE_PRIM_TRIANGLES
; /* anything but points */
1205 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
:
1206 info
->prop
.cp
.numThreads
[0] = prop
->u
[0].Data
;
1208 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
:
1209 info
->prop
.cp
.numThreads
[1] = prop
->u
[0].Data
;
1211 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
:
1212 info
->prop
.cp
.numThreads
[2] = prop
->u
[0].Data
;
1214 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
:
1215 info
->io
.clipDistances
= prop
->u
[0].Data
;
1217 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED
:
1218 info
->io
.cullDistances
= prop
->u
[0].Data
;
1220 case TGSI_PROPERTY_NEXT_SHADER
:
1221 /* Do not need to know the next shader stage. */
1223 case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
:
1224 info
->prop
.fp
.earlyFragTests
= prop
->u
[0].Data
;
1226 case TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
:
1227 info
->prop
.fp
.postDepthCoverage
= prop
->u
[0].Data
;
1229 case TGSI_PROPERTY_MUL_ZERO_WINS
:
1230 info
->io
.mul_zero_wins
= prop
->u
[0].Data
;
1233 INFO("unhandled TGSI property %d\n", prop
->Property
.PropertyName
);
1238 void Source::scanImmediate(const struct tgsi_full_immediate
*imm
)
1240 const unsigned n
= info
->immd
.count
++;
1242 assert(n
< scan
.immediate_count
);
1244 for (int c
= 0; c
< 4; ++c
)
1245 info
->immd
.data
[n
* 4 + c
] = imm
->u
[c
].Uint
;
1247 info
->immd
.type
[n
] = imm
->Immediate
.DataType
;
1250 int Source::inferSysValDirection(unsigned sn
) const
1253 case TGSI_SEMANTIC_INSTANCEID
:
1254 case TGSI_SEMANTIC_VERTEXID
:
1256 case TGSI_SEMANTIC_LAYER
:
1258 case TGSI_SEMANTIC_VIEWPORTINDEX
:
1261 case TGSI_SEMANTIC_PRIMID
:
1262 return (info
->type
== PIPE_SHADER_FRAGMENT
) ? 1 : 0;
1268 bool Source::scanDeclaration(const struct tgsi_full_declaration
*decl
)
1271 unsigned sn
= TGSI_SEMANTIC_GENERIC
;
1273 const unsigned first
= decl
->Range
.First
, last
= decl
->Range
.Last
;
1274 const int arrayId
= decl
->Array
.ArrayID
;
1276 if (decl
->Declaration
.Semantic
) {
1277 sn
= decl
->Semantic
.Name
;
1278 si
= decl
->Semantic
.Index
;
1281 if (decl
->Declaration
.Local
|| decl
->Declaration
.File
== TGSI_FILE_ADDRESS
) {
1282 for (i
= first
; i
<= last
; ++i
) {
1283 for (c
= 0; c
< 4; ++c
) {
1285 Location(decl
->Declaration
.File
, decl
->Dim
.Index2D
, i
, c
));
1290 switch (decl
->Declaration
.File
) {
1291 case TGSI_FILE_INPUT
:
1292 if (info
->type
== PIPE_SHADER_VERTEX
) {
1293 // all vertex attributes are equal
1294 for (i
= first
; i
<= last
; ++i
) {
1295 info
->in
[i
].sn
= TGSI_SEMANTIC_GENERIC
;
1299 for (i
= first
; i
<= last
; ++i
, ++si
) {
1301 info
->in
[i
].sn
= sn
;
1302 info
->in
[i
].si
= si
;
1303 if (info
->type
== PIPE_SHADER_FRAGMENT
) {
1304 // translate interpolation mode
1305 switch (decl
->Interp
.Interpolate
) {
1306 case TGSI_INTERPOLATE_CONSTANT
:
1307 info
->in
[i
].flat
= 1;
1309 case TGSI_INTERPOLATE_COLOR
:
1312 case TGSI_INTERPOLATE_LINEAR
:
1313 info
->in
[i
].linear
= 1;
1318 if (decl
->Interp
.Location
)
1319 info
->in
[i
].centroid
= 1;
1322 if (sn
== TGSI_SEMANTIC_PATCH
)
1323 info
->in
[i
].patch
= 1;
1324 if (sn
== TGSI_SEMANTIC_PATCH
)
1325 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, si
+ 1);
1329 case TGSI_FILE_OUTPUT
:
1330 for (i
= first
; i
<= last
; ++i
, ++si
) {
1332 case TGSI_SEMANTIC_POSITION
:
1333 if (info
->type
== PIPE_SHADER_FRAGMENT
)
1334 info
->io
.fragDepth
= i
;
1336 if (clipVertexOutput
< 0)
1337 clipVertexOutput
= i
;
1339 case TGSI_SEMANTIC_COLOR
:
1340 if (info
->type
== PIPE_SHADER_FRAGMENT
)
1341 info
->prop
.fp
.numColourResults
++;
1343 case TGSI_SEMANTIC_EDGEFLAG
:
1344 info
->io
.edgeFlagOut
= i
;
1346 case TGSI_SEMANTIC_CLIPVERTEX
:
1347 clipVertexOutput
= i
;
1349 case TGSI_SEMANTIC_CLIPDIST
:
1350 info
->io
.genUserClip
= -1;
1352 case TGSI_SEMANTIC_SAMPLEMASK
:
1353 info
->io
.sampleMask
= i
;
1355 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
1356 info
->io
.viewportId
= i
;
1358 case TGSI_SEMANTIC_PATCH
:
1359 info
->numPatchConstants
= MAX2(info
->numPatchConstants
, si
+ 1);
1361 case TGSI_SEMANTIC_TESSOUTER
:
1362 case TGSI_SEMANTIC_TESSINNER
:
1363 info
->out
[i
].patch
= 1;
1368 info
->out
[i
].id
= i
;
1369 info
->out
[i
].sn
= sn
;
1370 info
->out
[i
].si
= si
;
1373 case TGSI_FILE_SYSTEM_VALUE
:
1375 case TGSI_SEMANTIC_INSTANCEID
:
1376 info
->io
.instanceId
= first
;
1378 case TGSI_SEMANTIC_VERTEXID
:
1379 info
->io
.vertexId
= first
;
1381 case TGSI_SEMANTIC_BASEVERTEX
:
1382 case TGSI_SEMANTIC_BASEINSTANCE
:
1383 case TGSI_SEMANTIC_DRAWID
:
1384 info
->prop
.vp
.usesDrawParameters
= true;
1386 case TGSI_SEMANTIC_SAMPLEID
:
1387 case TGSI_SEMANTIC_SAMPLEPOS
:
1388 info
->prop
.fp
.persampleInvocation
= true;
1390 case TGSI_SEMANTIC_SAMPLEMASK
:
1391 info
->prop
.fp
.usesSampleMaskIn
= true;
1396 for (i
= first
; i
<= last
; ++i
, ++si
) {
1397 info
->sv
[i
].sn
= sn
;
1398 info
->sv
[i
].si
= si
;
1399 info
->sv
[i
].input
= inferSysValDirection(sn
);
1402 case TGSI_SEMANTIC_TESSOUTER
:
1403 case TGSI_SEMANTIC_TESSINNER
:
1404 info
->sv
[i
].patch
= 1;
1410 case TGSI_FILE_RESOURCE:
1411 for (i = first; i <= last; ++i) {
1412 resources[i].target = decl->Resource.Resource;
1413 resources[i].raw = decl->Resource.Raw;
1414 resources[i].slot = i;
1418 case TGSI_FILE_SAMPLER_VIEW
:
1419 for (i
= first
; i
<= last
; ++i
)
1420 textureViews
[i
].target
= decl
->SamplerView
.Resource
;
1422 case TGSI_FILE_MEMORY
:
1423 for (i
= first
; i
<= last
; ++i
)
1424 memoryFiles
[i
].mem_type
= decl
->Declaration
.MemType
;
1426 case TGSI_FILE_NULL
:
1427 case TGSI_FILE_TEMPORARY
:
1428 for (i
= first
; i
<= last
; ++i
)
1429 tempArrayId
[i
] = arrayId
;
1431 tempArrayInfo
.insert(std::make_pair(arrayId
, std::make_pair(
1432 first
, last
- first
+ 1)));
1434 case TGSI_FILE_BUFFER
:
1435 for (i
= first
; i
<= last
; ++i
)
1436 bufferAtomics
[i
] = decl
->Declaration
.Atomic
;
1438 case TGSI_FILE_ADDRESS
:
1439 case TGSI_FILE_CONSTANT
:
1440 case TGSI_FILE_IMMEDIATE
:
1441 case TGSI_FILE_SAMPLER
:
1442 case TGSI_FILE_IMAGE
:
1445 ERROR("unhandled TGSI_FILE %d\n", decl
->Declaration
.File
);
1451 inline bool Source::isEdgeFlagPassthrough(const Instruction
& insn
) const
1453 return insn
.getOpcode() == TGSI_OPCODE_MOV
&&
1454 insn
.getDst(0).getIndex(0) == info
->io
.edgeFlagOut
&&
1455 insn
.getSrc(0).getFile() == TGSI_FILE_INPUT
;
1458 void Source::scanInstructionSrc(const Instruction
& insn
,
1459 const Instruction::SrcRegister
& src
,
1462 if (src
.getFile() == TGSI_FILE_TEMPORARY
) {
1463 if (src
.isIndirect(0))
1464 indirectTempArrays
.insert(src
.getArrayId());
1466 if (src
.getFile() == TGSI_FILE_OUTPUT
) {
1467 if (src
.isIndirect(0)) {
1468 // We don't know which one is accessed, just mark everything for
1469 // reading. This is an extremely unlikely occurrence.
1470 for (unsigned i
= 0; i
< info
->numOutputs
; ++i
)
1471 info
->out
[i
].oread
= 1;
1473 info
->out
[src
.getIndex(0)].oread
= 1;
1476 if (src
.getFile() == TGSI_FILE_SYSTEM_VALUE
) {
1477 if (info
->sv
[src
.getIndex(0)].sn
== TGSI_SEMANTIC_SAMPLEPOS
)
1478 info
->prop
.fp
.readsSampleLocations
= true;
1480 if (src
.getFile() != TGSI_FILE_INPUT
)
1483 if (src
.isIndirect(0)) {
1484 for (unsigned i
= 0; i
< info
->numInputs
; ++i
)
1485 info
->in
[i
].mask
= 0xf;
1487 const int i
= src
.getIndex(0);
1488 for (unsigned c
= 0; c
< 4; ++c
) {
1489 if (!(mask
& (1 << c
)))
1491 int k
= src
.getSwizzle(c
);
1492 if (k
<= TGSI_SWIZZLE_W
)
1493 info
->in
[i
].mask
|= 1 << k
;
1495 switch (info
->in
[i
].sn
) {
1496 case TGSI_SEMANTIC_PSIZE
:
1497 case TGSI_SEMANTIC_PRIMID
:
1498 case TGSI_SEMANTIC_FOG
:
1499 info
->in
[i
].mask
&= 0x1;
1501 case TGSI_SEMANTIC_PCOORD
:
1502 info
->in
[i
].mask
&= 0x3;
1510 bool Source::scanInstruction(const struct tgsi_full_instruction
*inst
)
1512 Instruction
insn(inst
);
1514 if (insn
.getOpcode() == TGSI_OPCODE_BARRIER
)
1515 info
->numBarriers
= 1;
1517 if (insn
.getOpcode() == TGSI_OPCODE_FBFETCH
)
1518 info
->prop
.fp
.readsFramebuffer
= true;
1520 if (insn
.getOpcode() == TGSI_OPCODE_INTERP_SAMPLE
)
1521 info
->prop
.fp
.readsSampleLocations
= true;
1523 if (insn
.getOpcode() == TGSI_OPCODE_DEMOTE
)
1524 info
->prop
.fp
.usesDiscard
= true;
1526 if (insn
.dstCount()) {
1527 Instruction::DstRegister dst
= insn
.getDst(0);
1529 if (insn
.getOpcode() == TGSI_OPCODE_STORE
&&
1530 dst
.getFile() != TGSI_FILE_MEMORY
) {
1531 info
->io
.globalAccess
|= 0x2;
1533 if (dst
.getFile() == TGSI_FILE_INPUT
) {
1534 // TODO: Handle indirect somehow?
1535 const int i
= dst
.getIndex(0);
1536 info
->in
[i
].mask
|= 1;
1540 if (dst
.getFile() == TGSI_FILE_OUTPUT
) {
1541 if (dst
.isIndirect(0))
1542 for (unsigned i
= 0; i
< info
->numOutputs
; ++i
)
1543 info
->out
[i
].mask
= 0xf;
1545 info
->out
[dst
.getIndex(0)].mask
|= dst
.getMask();
1547 if (info
->out
[dst
.getIndex(0)].sn
== TGSI_SEMANTIC_PSIZE
||
1548 info
->out
[dst
.getIndex(0)].sn
== TGSI_SEMANTIC_PRIMID
||
1549 info
->out
[dst
.getIndex(0)].sn
== TGSI_SEMANTIC_LAYER
||
1550 info
->out
[dst
.getIndex(0)].sn
== TGSI_SEMANTIC_VIEWPORT_INDEX
||
1551 info
->out
[dst
.getIndex(0)].sn
== TGSI_SEMANTIC_FOG
)
1552 info
->out
[dst
.getIndex(0)].mask
&= 1;
1554 if (isEdgeFlagPassthrough(insn
))
1555 info
->io
.edgeFlagIn
= insn
.getSrc(0).getIndex(0);
1557 if (dst
.getFile() == TGSI_FILE_TEMPORARY
) {
1558 if (dst
.isIndirect(0))
1559 indirectTempArrays
.insert(dst
.getArrayId());
1561 if (dst
.getFile() == TGSI_FILE_BUFFER
||
1562 dst
.getFile() == TGSI_FILE_IMAGE
||
1563 (dst
.getFile() == TGSI_FILE_MEMORY
&&
1564 memoryFiles
[dst
.getIndex(0)].mem_type
== TGSI_MEMORY_TYPE_GLOBAL
)) {
1565 info
->io
.globalAccess
|= 0x2;
1569 if (insn
.srcCount() && (
1570 insn
.getSrc(0).getFile() != TGSI_FILE_MEMORY
||
1571 memoryFiles
[insn
.getSrc(0).getIndex(0)].mem_type
==
1572 TGSI_MEMORY_TYPE_GLOBAL
)) {
1573 switch (insn
.getOpcode()) {
1574 case TGSI_OPCODE_ATOMUADD
:
1575 case TGSI_OPCODE_ATOMXCHG
:
1576 case TGSI_OPCODE_ATOMCAS
:
1577 case TGSI_OPCODE_ATOMAND
:
1578 case TGSI_OPCODE_ATOMOR
:
1579 case TGSI_OPCODE_ATOMXOR
:
1580 case TGSI_OPCODE_ATOMUMIN
:
1581 case TGSI_OPCODE_ATOMIMIN
:
1582 case TGSI_OPCODE_ATOMUMAX
:
1583 case TGSI_OPCODE_ATOMIMAX
:
1584 case TGSI_OPCODE_ATOMFADD
:
1585 case TGSI_OPCODE_ATOMDEC_WRAP
:
1586 case TGSI_OPCODE_ATOMINC_WRAP
:
1587 case TGSI_OPCODE_LOAD
:
1588 info
->io
.globalAccess
|= (insn
.getOpcode() == TGSI_OPCODE_LOAD
) ?
1595 for (unsigned s
= 0; s
< insn
.srcCount(); ++s
)
1596 scanInstructionSrc(insn
, insn
.getSrc(s
), insn
.srcMask(s
));
1598 for (unsigned s
= 0; s
< insn
.getNumTexOffsets(); ++s
)
1599 scanInstructionSrc(insn
, insn
.getTexOffset(s
), insn
.texOffsetMask());
1604 nv50_ir::TexInstruction::Target
1605 Instruction::getTexture(const tgsi::Source
*code
, int s
) const
1607 // XXX: indirect access
1610 switch (getSrc(s
).getFile()) {
1612 case TGSI_FILE_RESOURCE:
1613 r = getSrc(s).getIndex(0);
1614 return translateTexture(code->resources.at(r).target);
1616 case TGSI_FILE_SAMPLER_VIEW
:
1617 r
= getSrc(s
).getIndex(0);
1618 return translateTexture(code
->textureViews
.at(r
).target
);
1620 return translateTexture(insn
->Texture
.Texture
);
1628 using namespace nv50_ir
;
1630 class Converter
: public ConverterCommon
1633 Converter(Program
*, const tgsi::Source
*);
1639 Value
*shiftAddress(Value
*);
1640 Value
*getVertexBase(int s
);
1641 Value
*getOutputBase(int s
);
1642 DataArray
*getArrayForFile(unsigned file
, int idx
);
1643 Value
*fetchSrc(int s
, int c
);
1644 Value
*fetchDst(int d
, int c
);
1645 Value
*acquireDst(int d
, int c
);
1646 void storeDst(int d
, int c
, Value
*);
1648 Value
*fetchSrc(const tgsi::Instruction::SrcRegister src
, int c
, Value
*ptr
);
1649 void storeDst(const tgsi::Instruction::DstRegister dst
, int c
,
1650 Value
*val
, Value
*ptr
);
1652 void adjustTempIndex(int arrayId
, int &idx
, int &idx2d
) const;
1653 Value
*applySrcMod(Value
*, int s
, int c
);
1655 Symbol
*makeSym(uint file
, int fileIndex
, int idx
, int c
, uint32_t addr
);
1656 Symbol
*srcToSym(tgsi::Instruction::SrcRegister
, int c
);
1657 Symbol
*dstToSym(tgsi::Instruction::DstRegister
, int c
);
1659 bool isSubGroupMask(uint8_t semantic
);
1661 bool handleInstruction(const struct tgsi_full_instruction
*);
1662 void exportOutputs();
1663 inline bool isEndOfSubroutine(uint ip
);
1665 void loadProjTexCoords(Value
*dst
[4], Value
*src
[4], unsigned int mask
);
1667 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1668 void setTexRS(TexInstruction
*, unsigned int& s
, int R
, int S
);
1669 void handleTEX(Value
*dst0
[4], int R
, int S
, int L
, int C
, int Dx
, int Dy
);
1670 void handleTXF(Value
*dst0
[4], int R
, int L_M
);
1671 void handleTXQ(Value
*dst0
[4], enum TexQuery
, int R
);
1672 void handleFBFETCH(Value
*dst0
[4]);
1673 void handleLIT(Value
*dst0
[4]);
1675 // Symbol *getResourceBase(int r);
1676 void getImageCoords(std::vector
<Value
*>&, int s
);
1678 void handleLOAD(Value
*dst0
[4]);
1680 void handleATOM(Value
*dst0
[4], DataType
, uint16_t subOp
);
1682 void handleINTERP(Value
*dst0
[4]);
1684 Value
*interpolate(tgsi::Instruction::SrcRegister
, int c
, Value
*ptr
);
1686 void insertConvergenceOps(BasicBlock
*conv
, BasicBlock
*fork
);
1688 Value
*buildDot(int dim
);
1690 class BindArgumentsPass
: public Pass
{
1692 BindArgumentsPass(Converter
&conv
) : conv(conv
) { }
1698 inline const Location
*getValueLocation(Subroutine
*, Value
*);
1700 template<typename T
> inline void
1701 updateCallArgs(Instruction
*i
, void (Instruction::*setArg
)(int, Value
*),
1702 T (Function::*proto
));
1704 template<typename T
> inline void
1705 updatePrototype(BitSet
*set
, void (Function::*updateSet
)(),
1706 T (Function::*proto
));
1709 bool visit(Function
*);
1710 bool visit(BasicBlock
*bb
) { return false; }
1714 const tgsi::Source
*code
;
1716 uint ip
; // instruction pointer
1718 tgsi::Instruction tgsi
;
1723 DataArray tData
; // TGSI_FILE_TEMPORARY
1724 DataArray lData
; // TGSI_FILE_TEMPORARY, for indirect arrays
1725 DataArray aData
; // TGSI_FILE_ADDRESS
1726 DataArray oData
; // TGSI_FILE_OUTPUT (if outputs in registers)
1730 Value
*vtxBase
[5]; // base address of vertex in primitive (for TP/GP)
1731 uint8_t vtxBaseValid
;
1733 Stack condBBs
; // fork BB, then else clause BB
1734 Stack joinBBs
; // fork BB, for inserting join ops on ENDIF
1735 Stack loopBBs
; // loop headers
1736 Stack breakBBs
; // end of / after loop
1742 Converter::srcToSym(tgsi::Instruction::SrcRegister src
, int c
)
1744 const int swz
= src
.getSwizzle(c
);
1746 /* TODO: Use Array ID when it's available for the index */
1747 return makeSym(src
.getFile(),
1748 src
.is2D() ? src
.getIndex(1) : 0,
1749 src
.getIndex(0), swz
,
1750 src
.getIndex(0) * 16 + swz
* 4);
1754 Converter::dstToSym(tgsi::Instruction::DstRegister dst
, int c
)
1756 /* TODO: Use Array ID when it's available for the index */
1757 return makeSym(dst
.getFile(),
1758 dst
.is2D() ? dst
.getIndex(1) : 0,
1760 dst
.getIndex(0) * 16 + c
* 4);
1764 Converter::makeSym(uint tgsiFile
, int fileIdx
, int idx
, int c
, uint32_t address
)
1766 Symbol
*sym
= new_Symbol(prog
, tgsi::translateFile(tgsiFile
));
1768 sym
->reg
.fileIndex
= fileIdx
;
1770 if (tgsiFile
== TGSI_FILE_MEMORY
) {
1771 switch (code
->memoryFiles
[fileIdx
].mem_type
) {
1772 case TGSI_MEMORY_TYPE_GLOBAL
:
1773 /* No-op this is the default for TGSI_FILE_MEMORY */
1774 sym
->setFile(FILE_MEMORY_GLOBAL
);
1776 case TGSI_MEMORY_TYPE_SHARED
:
1777 sym
->setFile(FILE_MEMORY_SHARED
);
1779 case TGSI_MEMORY_TYPE_INPUT
:
1780 assert(prog
->getType() == Program::TYPE_COMPUTE
);
1782 sym
->setFile(FILE_SHADER_INPUT
);
1783 address
+= info
->prop
.cp
.inputOffset
;
1786 assert(0); /* TODO: Add support for global and private memory */
1791 if (sym
->reg
.file
== FILE_SHADER_INPUT
)
1792 sym
->setOffset(info
->in
[idx
].slot
[c
] * 4);
1794 if (sym
->reg
.file
== FILE_SHADER_OUTPUT
)
1795 sym
->setOffset(info
->out
[idx
].slot
[c
] * 4);
1797 if (sym
->reg
.file
== FILE_SYSTEM_VALUE
)
1798 sym
->setSV(tgsi::translateSysVal(info
->sv
[idx
].sn
), c
);
1800 sym
->setOffset(address
);
1802 sym
->setOffset(address
);
1808 Converter::interpolate(tgsi::Instruction::SrcRegister src
, int c
, Value
*ptr
)
1812 // XXX: no way to know interpolation mode if we don't know what's accessed
1813 const uint8_t mode
= translateInterpMode(&info
->in
[ptr
? 0 :
1814 src
.getIndex(0)], op
);
1816 Instruction
*insn
= new_Instruction(func
, op
, TYPE_F32
);
1818 insn
->setDef(0, getScratch());
1819 insn
->setSrc(0, srcToSym(src
, c
));
1820 if (op
== OP_PINTERP
)
1821 insn
->setSrc(1, fragCoord
[3]);
1823 insn
->setIndirect(0, 0, ptr
);
1825 insn
->setInterpolate(mode
);
1827 bb
->insertTail(insn
);
1828 return insn
->getDef(0);
1832 Converter::applySrcMod(Value
*val
, int s
, int c
)
1834 Modifier m
= tgsi
.getSrc(s
).getMod(c
);
1835 DataType ty
= tgsi
.inferSrcType();
1837 if (m
& Modifier(NV50_IR_MOD_ABS
))
1838 val
= mkOp1v(OP_ABS
, ty
, getScratch(), val
);
1840 if (m
& Modifier(NV50_IR_MOD_NEG
))
1841 val
= mkOp1v(OP_NEG
, ty
, getScratch(), val
);
1847 Converter::getVertexBase(int s
)
1850 if (!(vtxBaseValid
& (1 << s
))) {
1851 const int index
= tgsi
.getSrc(s
).getIndex(1);
1853 if (tgsi
.getSrc(s
).isIndirect(1))
1854 rel
= fetchSrc(tgsi
.getSrc(s
).getIndirect(1), 0, NULL
);
1855 vtxBaseValid
|= 1 << s
;
1856 vtxBase
[s
] = mkOp2v(OP_PFETCH
, TYPE_U32
, getSSA(4, FILE_ADDRESS
),
1863 Converter::getOutputBase(int s
)
1866 if (!(vtxBaseValid
& (1 << s
))) {
1867 Value
*offset
= loadImm(NULL
, tgsi
.getSrc(s
).getIndex(1));
1868 if (tgsi
.getSrc(s
).isIndirect(1))
1869 offset
= mkOp2v(OP_ADD
, TYPE_U32
, getSSA(),
1870 fetchSrc(tgsi
.getSrc(s
).getIndirect(1), 0, NULL
),
1872 vtxBaseValid
|= 1 << s
;
1873 vtxBase
[s
] = mkOp2v(OP_ADD
, TYPE_U32
, getSSA(), outBase
, offset
);
1879 Converter::fetchSrc(int s
, int c
)
1882 Value
*ptr
= NULL
, *dimRel
= NULL
;
1884 tgsi::Instruction::SrcRegister src
= tgsi
.getSrc(s
);
1886 if (src
.isIndirect(0))
1887 ptr
= fetchSrc(src
.getIndirect(0), 0, NULL
);
1890 switch (src
.getFile()) {
1891 case TGSI_FILE_OUTPUT
:
1892 dimRel
= getOutputBase(s
);
1894 case TGSI_FILE_INPUT
:
1895 dimRel
= getVertexBase(s
);
1897 case TGSI_FILE_CONSTANT
:
1898 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1899 if (src
.isIndirect(1))
1900 dimRel
= fetchSrc(src
.getIndirect(1), 0, 0);
1907 res
= fetchSrc(src
, c
, ptr
);
1910 res
->getInsn()->setIndirect(0, 1, dimRel
);
1912 return applySrcMod(res
, s
, c
);
1916 Converter::fetchDst(int d
, int c
)
1919 Value
*ptr
= NULL
, *dimRel
= NULL
;
1921 tgsi::Instruction::DstRegister dst
= tgsi
.getDst(d
);
1923 if (dst
.isIndirect(0))
1924 ptr
= fetchSrc(dst
.getIndirect(0), 0, NULL
);
1927 switch (dst
.getFile()) {
1928 case TGSI_FILE_OUTPUT
:
1932 case TGSI_FILE_INPUT
:
1936 case TGSI_FILE_CONSTANT
:
1937 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1938 if (dst
.isIndirect(1))
1939 dimRel
= fetchSrc(dst
.getIndirect(1), 0, 0);
1946 struct tgsi_full_src_register fsr
= dst
.asSrc();
1947 tgsi::Instruction::SrcRegister
src(&fsr
);
1948 res
= fetchSrc(src
, c
, ptr
);
1951 res
->getInsn()->setIndirect(0, 1, dimRel
);
1956 Converter::DataArray
*
1957 Converter::getArrayForFile(unsigned file
, int idx
)
1960 case TGSI_FILE_TEMPORARY
:
1961 return idx
== 0 ? &tData
: &lData
;
1962 case TGSI_FILE_ADDRESS
:
1964 case TGSI_FILE_OUTPUT
:
1965 assert(prog
->getType() == Program::TYPE_FRAGMENT
);
1968 assert(!"invalid/unhandled TGSI source file");
1974 Converter::shiftAddress(Value
*index
)
1978 return mkOp2v(OP_SHL
, TYPE_U32
, getSSA(4, FILE_ADDRESS
), index
, mkImm(4));
1982 Converter::adjustTempIndex(int arrayId
, int &idx
, int &idx2d
) const
1984 std::map
<int, int>::const_iterator it
=
1985 code
->indirectTempOffsets
.find(arrayId
);
1986 if (it
== code
->indirectTempOffsets
.end())
1994 Converter::isSubGroupMask(uint8_t semantic
)
1997 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK
:
1998 case TGSI_SEMANTIC_SUBGROUP_LT_MASK
:
1999 case TGSI_SEMANTIC_SUBGROUP_LE_MASK
:
2000 case TGSI_SEMANTIC_SUBGROUP_GT_MASK
:
2001 case TGSI_SEMANTIC_SUBGROUP_GE_MASK
:
2009 Converter::fetchSrc(tgsi::Instruction::SrcRegister src
, int c
, Value
*ptr
)
2011 int idx2d
= src
.is2D() ? src
.getIndex(1) : 0;
2012 int idx
= src
.getIndex(0);
2013 const int swz
= src
.getSwizzle(c
);
2016 switch (src
.getFile()) {
2017 case TGSI_FILE_IMMEDIATE
:
2019 return loadImm(NULL
, info
->immd
.data
[idx
* 4 + swz
]);
2020 case TGSI_FILE_CONSTANT
:
2021 return mkLoadv(TYPE_U32
, srcToSym(src
, c
), shiftAddress(ptr
));
2022 case TGSI_FILE_INPUT
:
2023 if (prog
->getType() == Program::TYPE_FRAGMENT
) {
2024 // don't load masked inputs, won't be assigned a slot
2025 if (!ptr
&& !(info
->in
[idx
].mask
& (1 << swz
)))
2026 return loadImm(NULL
, swz
== TGSI_SWIZZLE_W
? 1.0f
: 0.0f
);
2027 return interpolate(src
, c
, shiftAddress(ptr
));
2029 if (prog
->getType() == Program::TYPE_GEOMETRY
) {
2030 if (!ptr
&& info
->in
[idx
].sn
== TGSI_SEMANTIC_PRIMID
)
2031 return mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_PRIMITIVE_ID
, 0));
2032 // XXX: This is going to be a problem with scalar arrays, i.e. when
2033 // we cannot assume that the address is given in units of vec4.
2035 // nv50 and nvc0 need different things here, so let the lowering
2036 // passes decide what to do with the address
2038 return mkLoadv(TYPE_U32
, srcToSym(src
, c
), ptr
);
2040 ld
= mkLoad(TYPE_U32
, getSSA(), srcToSym(src
, c
), shiftAddress(ptr
));
2041 ld
->perPatch
= info
->in
[idx
].patch
;
2042 return ld
->getDef(0);
2043 case TGSI_FILE_OUTPUT
:
2044 assert(prog
->getType() == Program::TYPE_TESSELLATION_CONTROL
);
2045 ld
= mkLoad(TYPE_U32
, getSSA(), srcToSym(src
, c
), shiftAddress(ptr
));
2046 ld
->perPatch
= info
->out
[idx
].patch
;
2047 return ld
->getDef(0);
2048 case TGSI_FILE_SYSTEM_VALUE
:
2050 if (info
->sv
[idx
].sn
== TGSI_SEMANTIC_THREAD_ID
&&
2051 info
->prop
.cp
.numThreads
[swz
] == 1)
2052 return loadImm(NULL
, 0u);
2053 if (isSubGroupMask(info
->sv
[idx
].sn
) && swz
> 0)
2054 return loadImm(NULL
, 0u);
2055 if (info
->sv
[idx
].sn
== TGSI_SEMANTIC_SUBGROUP_SIZE
)
2056 return loadImm(NULL
, 32u);
2057 ld
= mkOp1(OP_RDSV
, TYPE_U32
, getSSA(), srcToSym(src
, c
));
2058 ld
->perPatch
= info
->sv
[idx
].patch
;
2059 return ld
->getDef(0);
2060 case TGSI_FILE_TEMPORARY
: {
2061 int arrayid
= src
.getArrayId();
2063 arrayid
= code
->tempArrayId
[idx
];
2064 adjustTempIndex(arrayid
, idx
, idx2d
);
2068 return getArrayForFile(src
.getFile(), idx2d
)->load(
2069 sub
.cur
->values
, idx
, swz
, shiftAddress(ptr
));
2074 Converter::acquireDst(int d
, int c
)
2076 const tgsi::Instruction::DstRegister dst
= tgsi
.getDst(d
);
2077 const unsigned f
= dst
.getFile();
2078 int idx
= dst
.getIndex(0);
2079 int idx2d
= dst
.is2D() ? dst
.getIndex(1) : 0;
2081 if (dst
.isMasked(c
) || f
== TGSI_FILE_BUFFER
|| f
== TGSI_FILE_MEMORY
||
2082 f
== TGSI_FILE_IMAGE
)
2085 if (dst
.isIndirect(0) ||
2086 f
== TGSI_FILE_SYSTEM_VALUE
||
2087 (f
== TGSI_FILE_OUTPUT
&& prog
->getType() != Program::TYPE_FRAGMENT
))
2088 return getScratch();
2090 if (f
== TGSI_FILE_TEMPORARY
) {
2091 int arrayid
= dst
.getArrayId();
2093 arrayid
= code
->tempArrayId
[idx
];
2094 adjustTempIndex(arrayid
, idx
, idx2d
);
2097 return getArrayForFile(f
, idx2d
)-> acquire(sub
.cur
->values
, idx
, c
);
2101 Converter::storeDst(int d
, int c
, Value
*val
)
2103 const tgsi::Instruction::DstRegister dst
= tgsi
.getDst(d
);
2105 if (tgsi
.getSaturate()) {
2106 mkOp1(OP_SAT
, dstTy
, val
, val
);
2110 if (dst
.isIndirect(0))
2111 ptr
= shiftAddress(fetchSrc(dst
.getIndirect(0), 0, NULL
));
2113 if (info
->io
.genUserClip
> 0 &&
2114 dst
.getFile() == TGSI_FILE_OUTPUT
&&
2115 !dst
.isIndirect(0) && dst
.getIndex(0) == code
->clipVertexOutput
) {
2116 mkMov(clipVtx
[c
], val
);
2120 storeDst(dst
, c
, val
, ptr
);
2124 Converter::storeDst(const tgsi::Instruction::DstRegister dst
, int c
,
2125 Value
*val
, Value
*ptr
)
2127 const unsigned f
= dst
.getFile();
2128 int idx
= dst
.getIndex(0);
2129 int idx2d
= dst
.is2D() ? dst
.getIndex(1) : 0;
2131 if (f
== TGSI_FILE_SYSTEM_VALUE
) {
2133 mkOp2(OP_WRSV
, TYPE_U32
, NULL
, dstToSym(dst
, c
), val
);
2135 if (f
== TGSI_FILE_OUTPUT
&& prog
->getType() != Program::TYPE_FRAGMENT
) {
2137 if (ptr
|| (info
->out
[idx
].mask
& (1 << c
))) {
2138 /* Save the viewport index into a scratch register so that it can be
2139 exported at EMIT time */
2140 if (info
->out
[idx
].sn
== TGSI_SEMANTIC_VIEWPORT_INDEX
&&
2141 prog
->getType() == Program::TYPE_GEOMETRY
&&
2143 mkOp1(OP_MOV
, TYPE_U32
, viewport
, val
);
2145 mkStore(OP_EXPORT
, TYPE_U32
, dstToSym(dst
, c
), ptr
, val
)->perPatch
=
2146 info
->out
[idx
].patch
;
2149 if (f
== TGSI_FILE_TEMPORARY
||
2150 f
== TGSI_FILE_ADDRESS
||
2151 f
== TGSI_FILE_OUTPUT
) {
2152 if (f
== TGSI_FILE_TEMPORARY
) {
2153 int arrayid
= dst
.getArrayId();
2155 arrayid
= code
->tempArrayId
[idx
];
2156 adjustTempIndex(arrayid
, idx
, idx2d
);
2159 getArrayForFile(f
, idx2d
)->store(sub
.cur
->values
, idx
, c
, ptr
, val
);
2161 assert(!"invalid dst file");
2165 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
2166 for (chan = 0; chan < 4; ++chan) \
2167 if (!inst.getDst(d).isMasked(chan))
2170 Converter::buildDot(int dim
)
2174 Value
*src0
= fetchSrc(0, 0), *src1
= fetchSrc(1, 0);
2175 Value
*dotp
= getScratch();
2177 mkOp2(OP_MUL
, TYPE_F32
, dotp
, src0
, src1
)
2178 ->dnz
= info
->io
.mul_zero_wins
;
2180 for (int c
= 1; c
< dim
; ++c
) {
2181 src0
= fetchSrc(0, c
);
2182 src1
= fetchSrc(1, c
);
2183 mkOp3(OP_MAD
, TYPE_F32
, dotp
, src0
, src1
, dotp
)
2184 ->dnz
= info
->io
.mul_zero_wins
;
2190 Converter::insertConvergenceOps(BasicBlock
*conv
, BasicBlock
*fork
)
2192 FlowInstruction
*join
= new_FlowInstruction(func
, OP_JOIN
, NULL
);
2194 conv
->insertHead(join
);
2196 assert(!fork
->joinAt
);
2197 fork
->joinAt
= new_FlowInstruction(func
, OP_JOINAT
, conv
);
2198 fork
->insertBefore(fork
->getExit(), fork
->joinAt
);
2202 Converter::setTexRS(TexInstruction
*tex
, unsigned int& s
, int R
, int S
)
2204 unsigned rIdx
= 0, sIdx
= 0;
2206 if (R
>= 0 && tgsi
.getSrc(R
).getFile() != TGSI_FILE_SAMPLER
) {
2207 // This is the bindless case. We have to get the actual value and pass
2208 // it in. This will be the complete handle.
2209 tex
->tex
.rIndirectSrc
= s
;
2210 tex
->setSrc(s
++, fetchSrc(R
, 0));
2211 tex
->setTexture(tgsi
.getTexture(code
, R
), 0xff, 0x1f);
2212 tex
->tex
.bindless
= true;
2217 rIdx
= tgsi
.getSrc(R
).getIndex(0);
2219 sIdx
= tgsi
.getSrc(S
).getIndex(0);
2221 tex
->setTexture(tgsi
.getTexture(code
, R
), rIdx
, sIdx
);
2223 if (tgsi
.getSrc(R
).isIndirect(0)) {
2224 tex
->tex
.rIndirectSrc
= s
;
2225 tex
->setSrc(s
++, fetchSrc(tgsi
.getSrc(R
).getIndirect(0), 0, NULL
));
2227 if (S
>= 0 && tgsi
.getSrc(S
).isIndirect(0)) {
2228 tex
->tex
.sIndirectSrc
= s
;
2229 tex
->setSrc(s
++, fetchSrc(tgsi
.getSrc(S
).getIndirect(0), 0, NULL
));
2234 Converter::handleTXQ(Value
*dst0
[4], enum TexQuery query
, int R
)
2236 TexInstruction
*tex
= new_TexInstruction(func
, OP_TXQ
);
2237 tex
->tex
.query
= query
;
2240 for (d
= 0, c
= 0; c
< 4; ++c
) {
2243 tex
->tex
.mask
|= 1 << c
;
2244 tex
->setDef(d
++, dst0
[c
]);
2246 if (query
== TXQ_DIMS
)
2247 tex
->setSrc((c
= 0), fetchSrc(0, 0)); // mip level
2249 tex
->setSrc((c
= 0), zero
);
2251 setTexRS(tex
, ++c
, R
, -1);
2253 bb
->insertTail(tex
);
2257 Converter::loadProjTexCoords(Value
*dst
[4], Value
*src
[4], unsigned int mask
)
2259 Value
*proj
= fetchSrc(0, 3);
2260 Instruction
*insn
= proj
->getUniqueInsn();
2263 if (insn
->op
== OP_PINTERP
) {
2264 bb
->insertTail(insn
= cloneForward(func
, insn
));
2265 insn
->op
= OP_LINTERP
;
2266 insn
->setInterpolate(NV50_IR_INTERP_LINEAR
| insn
->getSampleMode());
2267 insn
->setSrc(1, NULL
);
2268 proj
= insn
->getDef(0);
2270 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getSSA(), proj
);
2272 for (c
= 0; c
< 4; ++c
) {
2273 if (!(mask
& (1 << c
)))
2275 if ((insn
= src
[c
]->getUniqueInsn())->op
!= OP_PINTERP
)
2279 bb
->insertTail(insn
= cloneForward(func
, insn
));
2280 insn
->setInterpolate(NV50_IR_INTERP_PERSPECTIVE
| insn
->getSampleMode());
2281 insn
->setSrc(1, proj
);
2282 dst
[c
] = insn
->getDef(0);
2287 proj
= mkOp1v(OP_RCP
, TYPE_F32
, getSSA(), fetchSrc(0, 3));
2289 for (c
= 0; c
< 4; ++c
)
2290 if (mask
& (1 << c
))
2291 dst
[c
] = mkOp2v(OP_MUL
, TYPE_F32
, getSSA(), src
[c
], proj
);
2294 // order of nv50 ir sources: x y z layer lod/bias shadow
2295 // order of TGSI TEX sources: x y z layer shadow lod/bias
2296 // lowering will finally set the hw specific order (like array first on nvc0)
2298 Converter::handleTEX(Value
*dst
[4], int R
, int S
, int L
, int C
, int Dx
, int Dy
)
2300 Value
*arg
[4], *src
[8];
2301 Value
*lod
= NULL
, *shd
= NULL
;
2302 unsigned int s
, c
, d
;
2303 TexInstruction
*texi
= new_TexInstruction(func
, tgsi
.getOP());
2305 TexInstruction::Target tgt
= tgsi
.getTexture(code
, R
);
2307 for (s
= 0; s
< tgt
.getArgCount(); ++s
)
2308 arg
[s
] = src
[s
] = fetchSrc(0, s
);
2310 if (tgsi
.getOpcode() == TGSI_OPCODE_TEX_LZ
)
2311 lod
= loadImm(NULL
, 0);
2312 else if (texi
->op
== OP_TXL
|| texi
->op
== OP_TXB
)
2313 lod
= fetchSrc(L
>> 4, L
& 3);
2316 C
= 0x00 | MAX2(tgt
.getArgCount(), 2); // guess DC src
2318 if (tgt
== TEX_TARGET_CUBE_ARRAY_SHADOW
) {
2319 switch (tgsi
.getOpcode()) {
2320 case TGSI_OPCODE_TG4
: shd
= fetchSrc(1, 0); break;
2321 case TGSI_OPCODE_TEX2
: shd
= fetchSrc(1, 0); break;
2322 case TGSI_OPCODE_TXB2
: shd
= fetchSrc(1, 1); break;
2323 case TGSI_OPCODE_TXL2
: shd
= fetchSrc(1, 1); break;
2324 default: assert(!"unexpected opcode with cube array shadow"); break;
2327 else if (tgt
.isShadow())
2328 shd
= fetchSrc(C
>> 4, C
& 3);
2330 if (texi
->op
== OP_TXD
) {
2331 for (c
= 0; c
< tgt
.getDim() + tgt
.isCube(); ++c
) {
2332 texi
->dPdx
[c
].set(fetchSrc(Dx
>> 4, (Dx
& 3) + c
));
2333 texi
->dPdy
[c
].set(fetchSrc(Dy
>> 4, (Dy
& 3) + c
));
2337 // cube textures don't care about projection value, it's divided out
2338 if (tgsi
.getOpcode() == TGSI_OPCODE_TXP
&& !tgt
.isCube() && !tgt
.isArray()) {
2339 unsigned int n
= tgt
.getDim();
2343 assert(tgt
.getDim() == tgt
.getArgCount());
2345 loadProjTexCoords(src
, arg
, (1 << n
) - 1);
2350 for (c
= 0, d
= 0; c
< 4; ++c
) {
2352 texi
->setDef(d
++, dst
[c
]);
2353 texi
->tex
.mask
|= 1 << c
;
2355 // NOTE: maybe hook up def too, for CSE
2358 for (s
= 0; s
< tgt
.getArgCount(); ++s
)
2359 texi
->setSrc(s
, src
[s
]);
2361 texi
->setSrc(s
++, lod
);
2363 texi
->setSrc(s
++, shd
);
2365 setTexRS(texi
, s
, R
, S
);
2367 if (tgsi
.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ
)
2368 texi
->tex
.levelZero
= true;
2369 if (prog
->getType() != Program::TYPE_FRAGMENT
&&
2370 (tgsi
.getOpcode() == TGSI_OPCODE_TEX
||
2371 tgsi
.getOpcode() == TGSI_OPCODE_TEX2
||
2372 tgsi
.getOpcode() == TGSI_OPCODE_TXP
))
2373 texi
->tex
.levelZero
= true;
2374 if (tgsi
.getOpcode() == TGSI_OPCODE_TG4
&& !tgt
.isShadow())
2375 texi
->tex
.gatherComp
= tgsi
.getSrc(1).getValueU32(0, info
);
2377 texi
->tex
.useOffsets
= tgsi
.getNumTexOffsets();
2378 for (s
= 0; s
< tgsi
.getNumTexOffsets(); ++s
) {
2379 for (c
= 0; c
< 3; ++c
) {
2380 texi
->offset
[s
][c
].set(fetchSrc(tgsi
.getTexOffset(s
), c
, NULL
));
2381 texi
->offset
[s
][c
].setInsn(texi
);
2385 bb
->insertTail(texi
);
2388 // 1st source: xyz = coordinates, w = lod/sample
2389 // 2nd source: offset
2391 Converter::handleTXF(Value
*dst
[4], int R
, int L_M
)
2393 TexInstruction
*texi
= new_TexInstruction(func
, tgsi
.getOP());
2395 unsigned int c
, d
, s
;
2397 texi
->tex
.target
= tgsi
.getTexture(code
, R
);
2399 ms
= texi
->tex
.target
.isMS() ? 1 : 0;
2400 texi
->tex
.levelZero
= ms
; /* MS textures don't have mip-maps */
2402 for (c
= 0, d
= 0; c
< 4; ++c
) {
2404 texi
->setDef(d
++, dst
[c
]);
2405 texi
->tex
.mask
|= 1 << c
;
2408 for (c
= 0; c
< (texi
->tex
.target
.getArgCount() - ms
); ++c
)
2409 texi
->setSrc(c
, fetchSrc(0, c
));
2410 if (!ms
&& tgsi
.getOpcode() == TGSI_OPCODE_TXF_LZ
)
2411 texi
->setSrc(c
++, loadImm(NULL
, 0));
2413 texi
->setSrc(c
++, fetchSrc(L_M
>> 4, L_M
& 3)); // lod or ms
2415 setTexRS(texi
, c
, R
, -1);
2417 texi
->tex
.useOffsets
= tgsi
.getNumTexOffsets();
2418 for (s
= 0; s
< tgsi
.getNumTexOffsets(); ++s
) {
2419 for (c
= 0; c
< 3; ++c
) {
2420 texi
->offset
[s
][c
].set(fetchSrc(tgsi
.getTexOffset(s
), c
, NULL
));
2421 texi
->offset
[s
][c
].setInsn(texi
);
2425 bb
->insertTail(texi
);
2429 Converter::handleFBFETCH(Value
*dst
[4])
2431 TexInstruction
*texi
= new_TexInstruction(func
, OP_TXF
);
2434 texi
->tex
.target
= TEX_TARGET_2D_MS_ARRAY
;
2435 texi
->tex
.levelZero
= 1;
2436 texi
->tex
.useOffsets
= 0;
2438 for (c
= 0, d
= 0; c
< 4; ++c
) {
2440 texi
->setDef(d
++, dst
[c
]);
2441 texi
->tex
.mask
|= 1 << c
;
2445 Value
*x
= mkOp1v(OP_RDSV
, TYPE_F32
, getScratch(), mkSysVal(SV_POSITION
, 0));
2446 Value
*y
= mkOp1v(OP_RDSV
, TYPE_F32
, getScratch(), mkSysVal(SV_POSITION
, 1));
2447 Value
*z
= mkOp1v(OP_RDSV
, TYPE_U32
, getScratch(), mkSysVal(SV_LAYER
, 0));
2448 Value
*ms
= mkOp1v(OP_RDSV
, TYPE_U32
, getScratch(), mkSysVal(SV_SAMPLE_INDEX
, 0));
2450 mkCvt(OP_CVT
, TYPE_U32
, x
, TYPE_F32
, x
)->rnd
= ROUND_Z
;
2451 mkCvt(OP_CVT
, TYPE_U32
, y
, TYPE_F32
, y
)->rnd
= ROUND_Z
;
2455 texi
->setSrc(3, ms
);
2457 texi
->tex
.r
= texi
->tex
.s
= -1;
2459 bb
->insertTail(texi
);
2463 Converter::handleLIT(Value
*dst0
[4])
2466 unsigned int mask
= tgsi
.getDst(0).getMask();
2468 if (mask
& (1 << 0))
2469 loadImm(dst0
[0], 1.0f
);
2471 if (mask
& (1 << 3))
2472 loadImm(dst0
[3], 1.0f
);
2474 if (mask
& (3 << 1)) {
2475 val0
= getScratch();
2476 mkOp2(OP_MAX
, TYPE_F32
, val0
, fetchSrc(0, 0), zero
);
2477 if (mask
& (1 << 1))
2478 mkMov(dst0
[1], val0
);
2481 if (mask
& (1 << 2)) {
2482 Value
*src1
= fetchSrc(0, 1), *src3
= fetchSrc(0, 3);
2483 Value
*val1
= getScratch(), *val3
= getScratch();
2485 Value
*pos128
= loadImm(NULL
, +127.999999f
);
2486 Value
*neg128
= loadImm(NULL
, -127.999999f
);
2488 mkOp2(OP_MAX
, TYPE_F32
, val1
, src1
, zero
);
2489 mkOp2(OP_MAX
, TYPE_F32
, val3
, src3
, neg128
);
2490 mkOp2(OP_MIN
, TYPE_F32
, val3
, val3
, pos128
);
2491 mkOp2(OP_POW
, TYPE_F32
, val3
, val1
, val3
);
2493 mkCmp(OP_SLCT
, CC_GT
, TYPE_F32
, dst0
[2], TYPE_F32
, val3
, zero
, val0
);
2497 /* Keep this around for now as reference when adding img support
2499 isResourceSpecial(const int r)
2501 return (r == TGSI_RESOURCE_GLOBAL ||
2502 r == TGSI_RESOURCE_LOCAL ||
2503 r == TGSI_RESOURCE_PRIVATE ||
2504 r == TGSI_RESOURCE_INPUT);
2508 isResourceRaw(const tgsi::Source *code, const int r)
2510 return isResourceSpecial(r) || code->resources[r].raw;
2513 static inline nv50_ir::TexTarget
2514 getResourceTarget(const tgsi::Source *code, int r)
2516 if (isResourceSpecial(r))
2517 return nv50_ir::TEX_TARGET_BUFFER;
2518 return tgsi::translateTexture(code->resources.at(r).target);
2522 Converter::getResourceBase(const int r)
2527 case TGSI_RESOURCE_GLOBAL:
2528 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL,
2529 info->io.auxCBSlot);
2531 case TGSI_RESOURCE_LOCAL:
2532 assert(prog->getType() == Program::TYPE_COMPUTE);
2533 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2534 info->prop.cp.sharedOffset);
2536 case TGSI_RESOURCE_PRIVATE:
2537 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2538 info->bin.tlsSpace);
2540 case TGSI_RESOURCE_INPUT:
2541 assert(prog->getType() == Program::TYPE_COMPUTE);
2542 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2543 info->prop.cp.inputOffset);
2546 sym = new_Symbol(prog,
2547 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2554 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2557 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2559 for (int c = 0; c < arg; ++c)
2560 coords.push_back(fetchSrc(s, c));
2562 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2563 if (r == TGSI_RESOURCE_LOCAL ||
2564 r == TGSI_RESOURCE_PRIVATE ||
2565 r == TGSI_RESOURCE_INPUT)
2566 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2571 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2580 comp[n = 1] = size[0] + 1;
2588 size[0] = (comp[0] == 1) ? 1 : 2;
2589 size[1] = 3 - size[0];
2590 comp[1] = comp[0] + size[0];
2596 Converter::getImageCoords(std::vector
<Value
*> &coords
, int s
)
2598 TexInstruction::Target t
=
2599 TexInstruction::Target(tgsi
.getImageTarget());
2600 const int arg
= t
.getDim() + (t
.isArray() || t
.isCube());
2602 for (int c
= 0; c
< arg
; ++c
)
2603 coords
.push_back(fetchSrc(s
, c
));
2606 coords
.push_back(fetchSrc(s
, 3));
2609 // For raw loads, granularity is 4 byte.
2610 // Usage of the texture read mask on OP_SULDP is not allowed.
2612 Converter::handleLOAD(Value
*dst0
[4])
2614 const int r
= tgsi
.getSrc(0).getIndex(0);
2616 std::vector
<Value
*> off
, src
, ldv
, def
;
2619 if (tgsi
.getSrc(0).isIndirect(0))
2620 ind
= fetchSrc(tgsi
.getSrc(0).getIndirect(0), 0, 0);
2622 switch (tgsi
.getSrc(0).getFile()) {
2623 case TGSI_FILE_BUFFER
:
2624 case TGSI_FILE_MEMORY
:
2625 for (c
= 0; c
< 4; ++c
) {
2631 uint32_t src0_component_offset
= tgsi
.getSrc(0).getSwizzle(c
) * 4;
2633 if (tgsi
.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE
) {
2635 sym
= makeSym(tgsi
.getSrc(0).getFile(), r
, -1, c
,
2636 tgsi
.getSrc(1).getValueU32(0, info
) +
2637 src0_component_offset
);
2639 // yzw are ignored for buffers
2640 off
= fetchSrc(1, 0);
2641 sym
= makeSym(tgsi
.getSrc(0).getFile(), r
, -1, c
,
2642 src0_component_offset
);
2645 Instruction
*ld
= mkLoad(TYPE_U32
, dst0
[c
], sym
, off
);
2646 if (tgsi
.getSrc(0).getFile() == TGSI_FILE_BUFFER
&&
2647 code
->bufferAtomics
[r
])
2648 ld
->cache
= nv50_ir::CACHE_CG
;
2650 ld
->cache
= tgsi
.getCacheMode();
2652 ld
->setIndirect(0, 1, ind
);
2656 getImageCoords(off
, 1);
2659 for (c
= 0; c
< 4; ++c
) {
2660 if (!dst0
[c
] || tgsi
.getSrc(0).getSwizzle(c
) != (TGSI_SWIZZLE_X
+ c
))
2661 def
[c
] = getScratch();
2666 bool bindless
= tgsi
.getSrc(0).getFile() != TGSI_FILE_IMAGE
;
2668 ind
= fetchSrc(0, 0);
2670 TexInstruction
*ld
=
2671 mkTex(OP_SULDP
, tgsi
.getImageTarget(), 0, 0, def
, off
);
2672 ld
->tex
.mask
= tgsi
.getDst(0).getMask();
2673 ld
->tex
.format
= tgsi
.getImageFormat();
2674 ld
->cache
= tgsi
.getCacheMode();
2675 ld
->tex
.bindless
= bindless
;
2679 ld
->setIndirectR(ind
);
2681 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
2682 if (dst0
[c
] != def
[c
])
2683 mkMov(dst0
[c
], def
[tgsi
.getSrc(0).getSwizzle(c
)]);
2689 /* Keep this around for now as reference when adding img support
2690 getResourceCoords(off, r, 1);
2692 if (isResourceRaw(code, r)) {
2694 uint8_t comp[2] = { 0, 0 };
2695 uint8_t size[2] = { 0, 0 };
2697 Symbol *base = getResourceBase(r);
2699 // determine the base and size of the at most 2 load ops
2700 for (c = 0; c < 4; ++c)
2701 if (!tgsi.getDst(0).isMasked(c))
2702 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2704 int n = partitionLoadStore(comp, size, mask);
2708 def.resize(4); // index by component, the ones we need will be non-NULL
2709 for (c = 0; c < 4; ++c) {
2710 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2713 if (mask & (1 << c))
2714 def[c] = getScratch();
2717 const bool useLd = isResourceSpecial(r) ||
2718 (info->io.nv50styleSurfaces &&
2719 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2721 for (int i = 0; i < n; ++i) {
2722 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2724 if (comp[i]) // adjust x component of source address if necessary
2725 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2726 off[0], mkImm(comp[i] * 4));
2732 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2733 for (size_t c = 1; c < ldv.size(); ++c)
2734 ld->setDef(c, ldv[c]);
2736 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2737 0, ldv, src)->dType = typeOfSize(size[i] * 4);
2742 for (c = 0; c < 4; ++c) {
2743 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2744 def[c] = getScratch();
2749 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2752 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2753 if (dst0[c] != def[c])
2754 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2758 // For formatted stores, the write mask on OP_SUSTP can be used.
2759 // Raw stores have to be split.
2761 Converter::handleSTORE()
2763 const int r
= tgsi
.getDst(0).getIndex(0);
2765 std::vector
<Value
*> off
, src
, dummy
;
2768 if (tgsi
.getDst(0).isIndirect(0))
2769 ind
= fetchSrc(tgsi
.getDst(0).getIndirect(0), 0, 0);
2771 switch (tgsi
.getDst(0).getFile()) {
2772 case TGSI_FILE_BUFFER
:
2773 case TGSI_FILE_MEMORY
:
2774 for (c
= 0; c
< 4; ++c
) {
2775 if (!(tgsi
.getDst(0).getMask() & (1 << c
)))
2780 if (tgsi
.getSrc(0).getFile() == TGSI_FILE_IMMEDIATE
) {
2782 sym
= makeSym(tgsi
.getDst(0).getFile(), r
, -1, c
,
2783 tgsi
.getSrc(0).getValueU32(0, info
) + 4 * c
);
2785 // yzw are ignored for buffers
2786 off
= fetchSrc(0, 0);
2787 sym
= makeSym(tgsi
.getDst(0).getFile(), r
, -1, c
, 4 * c
);
2790 Instruction
*st
= mkStore(OP_STORE
, TYPE_U32
, sym
, off
, fetchSrc(1, c
));
2791 st
->cache
= tgsi
.getCacheMode();
2793 st
->setIndirect(0, 1, ind
);
2797 getImageCoords(off
, 0);
2800 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
2801 src
.push_back(fetchSrc(1, c
));
2803 bool bindless
= tgsi
.getDst(0).getFile() != TGSI_FILE_IMAGE
;
2805 ind
= fetchDst(0, 0);
2807 TexInstruction
*st
=
2808 mkTex(OP_SUSTP
, tgsi
.getImageTarget(), 0, 0, dummy
, src
);
2809 st
->tex
.mask
= tgsi
.getDst(0).getMask();
2810 st
->tex
.format
= tgsi
.getImageFormat();
2811 st
->cache
= tgsi
.getCacheMode();
2812 st
->tex
.bindless
= bindless
;
2816 st
->setIndirectR(ind
);
2822 /* Keep this around for now as reference when adding img support
2823 getResourceCoords(off, r, 0);
2825 const int s = src.size();
2827 if (isResourceRaw(code, r)) {
2828 uint8_t comp[2] = { 0, 0 };
2829 uint8_t size[2] = { 0, 0 };
2831 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2833 Symbol *base = getResourceBase(r);
2835 const bool useSt = isResourceSpecial(r) ||
2836 (info->io.nv50styleSurfaces &&
2837 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2839 for (int i = 0; i < n; ++i) {
2840 if (comp[i]) // adjust x component of source address if necessary
2841 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2842 off[0], mkImm(comp[i] * 4));
2846 const DataType stTy = typeOfSize(size[i] * 4);
2850 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2851 for (c = 1; c < size[i]; ++c)
2852 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2853 st->setIndirect(0, 0, src[0]);
2855 // attach values to be stored
2856 src.resize(s + size[i]);
2857 for (c = 0; c < size[i]; ++c)
2858 src[s + c] = fetchSrc(1, comp[i] + c);
2859 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2860 0, dummy, src)->setType(stTy);
2864 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2865 src.push_back(fetchSrc(1, c));
2867 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2868 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2873 // XXX: These only work on resources with the single-component u32/s32 formats.
2874 // Therefore the result is replicated. This might not be intended by TGSI, but
2875 // operating on more than 1 component would produce undefined results because
2876 // they do not exist.
2878 Converter::handleATOM(Value
*dst0
[4], DataType ty
, uint16_t subOp
)
2880 const int r
= tgsi
.getSrc(0).getIndex(0);
2881 std::vector
<Value
*> srcv
;
2882 std::vector
<Value
*> defv
;
2883 LValue
*dst
= getScratch();
2886 if (tgsi
.getSrc(0).isIndirect(0))
2887 ind
= fetchSrc(tgsi
.getSrc(0).getIndirect(0), 0, 0);
2889 switch (tgsi
.getSrc(0).getFile()) {
2890 case TGSI_FILE_BUFFER
:
2891 case TGSI_FILE_MEMORY
:
2892 for (int c
= 0; c
< 4; ++c
) {
2897 Value
*off
= fetchSrc(1, c
);
2899 if (tgsi
.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE
)
2900 sym
= makeSym(tgsi
.getSrc(0).getFile(), r
, -1, c
,
2901 tgsi
.getSrc(1).getValueU32(c
, info
));
2903 sym
= makeSym(tgsi
.getSrc(0).getFile(), r
, -1, c
, 0);
2904 if (subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2905 insn
= mkOp3(OP_ATOM
, ty
, dst
, sym
, fetchSrc(2, c
), fetchSrc(3, c
));
2907 insn
= mkOp2(OP_ATOM
, ty
, dst
, sym
, fetchSrc(2, c
));
2908 if (tgsi
.getSrc(1).getFile() != TGSI_FILE_IMMEDIATE
)
2909 insn
->setIndirect(0, 0, off
);
2911 insn
->setIndirect(0, 1, ind
);
2912 insn
->subOp
= subOp
;
2914 for (int c
= 0; c
< 4; ++c
)
2916 dst0
[c
] = dst
; // not equal to rDst so handleInstruction will do mkMov
2919 getImageCoords(srcv
, 1);
2920 defv
.push_back(dst
);
2921 srcv
.push_back(fetchSrc(2, 0));
2923 if (subOp
== NV50_IR_SUBOP_ATOM_CAS
)
2924 srcv
.push_back(fetchSrc(3, 0));
2926 bool bindless
= tgsi
.getSrc(0).getFile() != TGSI_FILE_IMAGE
;
2928 ind
= fetchSrc(0, 0);
2930 TexInstruction
*tex
= mkTex(OP_SUREDP
, tgsi
.getImageTarget(),
2934 tex
->tex
.format
= tgsi
.getImageFormat();
2936 tex
->tex
.bindless
= bindless
;
2940 tex
->setIndirectR(ind
);
2942 for (int c
= 0; c
< 4; ++c
)
2944 dst0
[c
] = dst
; // not equal to rDst so handleInstruction will do mkMov
2949 /* Keep this around for now as reference when adding img support
2950 getResourceCoords(srcv, r, 1);
2952 if (isResourceSpecial(r)) {
2953 assert(r != TGSI_RESOURCE_INPUT);
2955 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2956 insn->subOp = subOp;
2957 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2958 insn->setSrc(2, fetchSrc(3, 0));
2959 insn->setIndirect(0, 0, srcv.at(0));
2961 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2962 TexTarget targ = getResourceTarget(code, r);
2963 int idx = code->resources[r].slot;
2964 defv.push_back(dst);
2965 srcv.push_back(fetchSrc(2, 0));
2966 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2967 srcv.push_back(fetchSrc(3, 0));
2968 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2974 for (int c = 0; c < 4; ++c)
2976 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2981 Converter::handleINTERP(Value
*dst
[4])
2983 // Check whether the input is linear. All other attributes ignored.
2985 Value
*offset
= NULL
, *ptr
= NULL
, *w
= NULL
;
2986 Symbol
*sym
[4] = { NULL
};
2988 operation op
= OP_NOP
;
2991 tgsi::Instruction::SrcRegister src
= tgsi
.getSrc(0);
2993 // In some odd cases, in large part due to varying packing, the source
2994 // might not actually be an input. This is illegal TGSI, but it's easier to
2995 // account for it here than it is to fix it where the TGSI is being
2996 // generated. In that case, it's going to be a straight up mov (or sequence
2997 // of mov's) from the input in question. We follow the mov chain to see
2998 // which input we need to use.
2999 if (src
.getFile() != TGSI_FILE_INPUT
) {
3000 if (src
.isIndirect(0)) {
3001 ERROR("Ignoring indirect input interpolation\n");
3004 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3005 Value
*val
= fetchSrc(0, c
);
3006 assert(val
->defs
.size() == 1);
3007 insn
= val
->getInsn();
3008 while (insn
->op
== OP_MOV
) {
3009 assert(insn
->getSrc(0)->defs
.size() == 1);
3010 insn
= insn
->getSrc(0)->getInsn();
3012 ERROR("Miscompiling shader due to unhandled INTERP\n");
3016 if (insn
->op
!= OP_LINTERP
&& insn
->op
!= OP_PINTERP
) {
3017 ERROR("Trying to interpolate non-input, this is not allowed.\n");
3020 sym
[c
] = insn
->getSrc(0)->asSym();
3024 ptr
= insn
->getIndirect(0, 0);
3027 if (src
.isIndirect(0))
3028 ptr
= shiftAddress(fetchSrc(src
.getIndirect(0), 0, NULL
));
3030 // We can assume that the fixed index will point to an input of the same
3031 // interpolation type in case of an indirect.
3032 // TODO: Make use of ArrayID.
3033 linear
= info
->in
[src
.getIndex(0)].linear
;
3036 mode
= NV50_IR_INTERP_LINEAR
;
3039 mode
= NV50_IR_INTERP_PERSPECTIVE
;
3043 switch (tgsi
.getOpcode()) {
3044 case TGSI_OPCODE_INTERP_CENTROID
:
3045 mode
|= NV50_IR_INTERP_CENTROID
;
3047 case TGSI_OPCODE_INTERP_SAMPLE
:
3048 insn
= mkOp1(OP_PIXLD
, TYPE_U32
, (offset
= getScratch()), fetchSrc(1, 0));
3049 insn
->subOp
= NV50_IR_SUBOP_PIXLD_OFFSET
;
3050 mode
|= NV50_IR_INTERP_OFFSET
;
3052 case TGSI_OPCODE_INTERP_OFFSET
: {
3053 // The input in src1.xy is float, but we need a single 32-bit value
3054 // where the upper and lower 16 bits are encoded in S0.12 format. We need
3055 // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
3056 // and then convert to s32.
3058 for (c
= 0; c
< 2; c
++) {
3059 offs
[c
] = getScratch();
3060 mkOp2(OP_MIN
, TYPE_F32
, offs
[c
], fetchSrc(1, c
), loadImm(NULL
, 0.4375f
));
3061 mkOp2(OP_MAX
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, -0.5f
));
3062 mkOp2(OP_MUL
, TYPE_F32
, offs
[c
], offs
[c
], loadImm(NULL
, 4096.0f
));
3063 mkCvt(OP_CVT
, TYPE_S32
, offs
[c
], TYPE_F32
, offs
[c
]);
3065 offset
= mkOp3v(OP_INSBF
, TYPE_U32
, getScratch(),
3066 offs
[1], mkImm(0x1010), offs
[0]);
3067 mode
|= NV50_IR_INTERP_OFFSET
;
3072 if (op
== OP_PINTERP
) {
3074 w
= mkOp2v(OP_RDSV
, TYPE_F32
, getSSA(), mkSysVal(SV_POSITION
, 3), offset
);
3075 mkOp1(OP_RCP
, TYPE_F32
, w
, w
);
3082 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3083 insn
= mkOp1(op
, TYPE_F32
, dst
[c
], sym
[c
] ? sym
[c
] : srcToSym(src
, c
));
3084 if (op
== OP_PINTERP
)
3087 insn
->setSrc(op
== OP_PINTERP
? 2 : 1, offset
);
3089 insn
->setIndirect(0, 0, ptr
);
3091 insn
->setInterpolate(mode
);
3096 Converter::isEndOfSubroutine(uint ip
)
3098 assert(ip
< code
->scan
.num_instructions
);
3099 tgsi::Instruction
insn(&code
->insns
[ip
]);
3100 return (insn
.getOpcode() == TGSI_OPCODE_END
||
3101 insn
.getOpcode() == TGSI_OPCODE_ENDSUB
||
3102 // does END occur at end of main or the very end ?
3103 insn
.getOpcode() == TGSI_OPCODE_BGNSUB
);
3107 Converter::handleInstruction(const struct tgsi_full_instruction
*insn
)
3111 Value
*dst0
[4], *rDst0
[4];
3112 Value
*src0
, *src1
, *src2
, *src3
;
3116 tgsi
= tgsi::Instruction(insn
);
3118 bool useScratchDst
= tgsi
.checkDstSrcAliasing();
3120 operation op
= tgsi
.getOP();
3121 dstTy
= tgsi
.inferDstType();
3122 srcTy
= tgsi
.inferSrcType();
3124 unsigned int mask
= tgsi
.dstCount() ? tgsi
.getDst(0).getMask() : 0;
3126 if (tgsi
.dstCount() && tgsi
.getOpcode() != TGSI_OPCODE_STORE
) {
3127 for (c
= 0; c
< 4; ++c
) {
3128 rDst0
[c
] = acquireDst(0, c
);
3129 dst0
[c
] = (useScratchDst
&& rDst0
[c
]) ? getScratch() : rDst0
[c
];
3133 switch (tgsi
.getOpcode()) {
3134 case TGSI_OPCODE_ADD
:
3135 case TGSI_OPCODE_UADD
:
3136 case TGSI_OPCODE_AND
:
3137 case TGSI_OPCODE_DIV
:
3138 case TGSI_OPCODE_IDIV
:
3139 case TGSI_OPCODE_UDIV
:
3140 case TGSI_OPCODE_MAX
:
3141 case TGSI_OPCODE_MIN
:
3142 case TGSI_OPCODE_IMAX
:
3143 case TGSI_OPCODE_IMIN
:
3144 case TGSI_OPCODE_UMAX
:
3145 case TGSI_OPCODE_UMIN
:
3146 case TGSI_OPCODE_MOD
:
3147 case TGSI_OPCODE_UMOD
:
3148 case TGSI_OPCODE_MUL
:
3149 case TGSI_OPCODE_UMUL
:
3150 case TGSI_OPCODE_IMUL_HI
:
3151 case TGSI_OPCODE_UMUL_HI
:
3152 case TGSI_OPCODE_OR
:
3153 case TGSI_OPCODE_SHL
:
3154 case TGSI_OPCODE_ISHR
:
3155 case TGSI_OPCODE_USHR
:
3156 case TGSI_OPCODE_XOR
:
3157 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3158 src0
= fetchSrc(0, c
);
3159 src1
= fetchSrc(1, c
);
3160 geni
= mkOp2(op
, dstTy
, dst0
[c
], src0
, src1
);
3161 geni
->subOp
= tgsi::opcodeToSubOp(tgsi
.getOpcode());
3162 if (op
== OP_MUL
&& dstTy
== TYPE_F32
)
3163 geni
->dnz
= info
->io
.mul_zero_wins
;
3164 geni
->precise
= insn
->Instruction
.Precise
;
3167 case TGSI_OPCODE_MAD
:
3168 case TGSI_OPCODE_UMAD
:
3169 case TGSI_OPCODE_FMA
:
3170 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3171 src0
= fetchSrc(0, c
);
3172 src1
= fetchSrc(1, c
);
3173 src2
= fetchSrc(2, c
);
3174 geni
= mkOp3(op
, dstTy
, dst0
[c
], src0
, src1
, src2
);
3175 if (dstTy
== TYPE_F32
)
3176 geni
->dnz
= info
->io
.mul_zero_wins
;
3177 geni
->precise
= insn
->Instruction
.Precise
;
3180 case TGSI_OPCODE_MOV
:
3181 case TGSI_OPCODE_CEIL
:
3182 case TGSI_OPCODE_FLR
:
3183 case TGSI_OPCODE_TRUNC
:
3184 case TGSI_OPCODE_RCP
:
3185 case TGSI_OPCODE_SQRT
:
3186 case TGSI_OPCODE_IABS
:
3187 case TGSI_OPCODE_INEG
:
3188 case TGSI_OPCODE_NOT
:
3189 case TGSI_OPCODE_DDX
:
3190 case TGSI_OPCODE_DDY
:
3191 case TGSI_OPCODE_DDX_FINE
:
3192 case TGSI_OPCODE_DDY_FINE
:
3193 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3194 mkOp1(op
, dstTy
, dst0
[c
], fetchSrc(0, c
));
3196 case TGSI_OPCODE_RSQ
:
3197 src0
= fetchSrc(0, 0);
3198 val0
= getScratch();
3199 mkOp1(OP_ABS
, TYPE_F32
, val0
, src0
);
3200 mkOp1(OP_RSQ
, TYPE_F32
, val0
, val0
);
3201 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3202 mkMov(dst0
[c
], val0
);
3204 case TGSI_OPCODE_ARL
:
3205 case TGSI_OPCODE_ARR
:
3206 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3207 const RoundMode rnd
=
3208 tgsi
.getOpcode() == TGSI_OPCODE_ARR
? ROUND_N
: ROUND_M
;
3209 src0
= fetchSrc(0, c
);
3210 mkCvt(OP_CVT
, TYPE_S32
, dst0
[c
], TYPE_F32
, src0
)->rnd
= rnd
;
3213 case TGSI_OPCODE_UARL
:
3214 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3215 mkOp1(OP_MOV
, TYPE_U32
, dst0
[c
], fetchSrc(0, c
));
3217 case TGSI_OPCODE_POW
:
3218 val0
= mkOp2v(op
, TYPE_F32
, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
3219 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3220 mkOp1(OP_MOV
, TYPE_F32
, dst0
[c
], val0
);
3222 case TGSI_OPCODE_EX2
:
3223 case TGSI_OPCODE_LG2
:
3224 val0
= mkOp1(op
, TYPE_F32
, getScratch(), fetchSrc(0, 0))->getDef(0);
3225 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3226 mkOp1(OP_MOV
, TYPE_F32
, dst0
[c
], val0
);
3228 case TGSI_OPCODE_COS
:
3229 case TGSI_OPCODE_SIN
:
3230 val0
= getScratch();
3232 mkOp1(OP_PRESIN
, TYPE_F32
, val0
, fetchSrc(0, 0));
3233 mkOp1(op
, TYPE_F32
, val0
, val0
);
3234 for (c
= 0; c
< 3; ++c
)
3236 mkMov(dst0
[c
], val0
);
3239 mkOp1(OP_PRESIN
, TYPE_F32
, val0
, fetchSrc(0, 3));
3240 mkOp1(op
, TYPE_F32
, dst0
[3], val0
);
3243 case TGSI_OPCODE_EXP
:
3244 src0
= fetchSrc(0, 0);
3245 val0
= mkOp1v(OP_FLOOR
, TYPE_F32
, getSSA(), src0
);
3247 mkOp2(OP_SUB
, TYPE_F32
, dst0
[1], src0
, val0
);
3249 mkOp1(OP_EX2
, TYPE_F32
, dst0
[0], val0
);
3251 mkOp1(OP_EX2
, TYPE_F32
, dst0
[2], src0
);
3253 loadImm(dst0
[3], 1.0f
);
3255 case TGSI_OPCODE_LOG
:
3256 src0
= mkOp1v(OP_ABS
, TYPE_F32
, getSSA(), fetchSrc(0, 0));
3257 val0
= mkOp1v(OP_LG2
, TYPE_F32
, dst0
[2] ? dst0
[2] : getSSA(), src0
);
3258 if (dst0
[0] || dst0
[1])
3259 val1
= mkOp1v(OP_FLOOR
, TYPE_F32
, dst0
[0] ? dst0
[0] : getSSA(), val0
);
3261 mkOp1(OP_EX2
, TYPE_F32
, dst0
[1], val1
);
3262 mkOp1(OP_RCP
, TYPE_F32
, dst0
[1], dst0
[1]);
3263 mkOp2(OP_MUL
, TYPE_F32
, dst0
[1], dst0
[1], src0
)
3264 ->dnz
= info
->io
.mul_zero_wins
;
3267 loadImm(dst0
[3], 1.0f
);
3269 case TGSI_OPCODE_DP2
:
3271 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3272 mkMov(dst0
[c
], val0
);
3274 case TGSI_OPCODE_DP3
:
3276 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3277 mkMov(dst0
[c
], val0
);
3279 case TGSI_OPCODE_DP4
:
3281 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3282 mkMov(dst0
[c
], val0
);
3284 case TGSI_OPCODE_DST
:
3286 loadImm(dst0
[0], 1.0f
);
3288 src0
= fetchSrc(0, 1);
3289 src1
= fetchSrc(1, 1);
3290 mkOp2(OP_MUL
, TYPE_F32
, dst0
[1], src0
, src1
)
3291 ->dnz
= info
->io
.mul_zero_wins
;
3294 mkMov(dst0
[2], fetchSrc(0, 2));
3296 mkMov(dst0
[3], fetchSrc(1, 3));
3298 case TGSI_OPCODE_LRP
:
3299 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3300 src0
= fetchSrc(0, c
);
3301 src1
= fetchSrc(1, c
);
3302 src2
= fetchSrc(2, c
);
3303 mkOp3(OP_MAD
, TYPE_F32
, dst0
[c
],
3304 mkOp2v(OP_SUB
, TYPE_F32
, getSSA(), src1
, src2
), src0
, src2
)
3305 ->dnz
= info
->io
.mul_zero_wins
;
3308 case TGSI_OPCODE_LIT
:
3311 case TGSI_OPCODE_ISSG
:
3312 case TGSI_OPCODE_SSG
:
3313 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3314 src0
= fetchSrc(0, c
);
3315 val0
= getScratch();
3316 val1
= getScratch();
3317 mkCmp(OP_SET
, CC_GT
, srcTy
, val0
, srcTy
, src0
, zero
);
3318 mkCmp(OP_SET
, CC_LT
, srcTy
, val1
, srcTy
, src0
, zero
);
3319 if (srcTy
== TYPE_F32
)
3320 mkOp2(OP_SUB
, TYPE_F32
, dst0
[c
], val0
, val1
);
3322 mkOp2(OP_SUB
, TYPE_S32
, dst0
[c
], val1
, val0
);
3325 case TGSI_OPCODE_UCMP
:
3328 case TGSI_OPCODE_CMP
:
3329 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3330 src0
= fetchSrc(0, c
);
3331 src1
= fetchSrc(1, c
);
3332 src2
= fetchSrc(2, c
);
3334 mkMov(dst0
[c
], src1
);
3336 mkCmp(OP_SLCT
, (srcTy
== TYPE_F32
) ? CC_LT
: CC_NE
,
3337 srcTy
, dst0
[c
], srcTy
, src1
, src2
, src0
);
3340 case TGSI_OPCODE_FRC
:
3341 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3342 src0
= fetchSrc(0, c
);
3343 val0
= getScratch();
3344 mkOp1(OP_FLOOR
, TYPE_F32
, val0
, src0
);
3345 mkOp2(OP_SUB
, TYPE_F32
, dst0
[c
], src0
, val0
);
3348 case TGSI_OPCODE_ROUND
:
3349 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3350 mkCvt(OP_CVT
, TYPE_F32
, dst0
[c
], TYPE_F32
, fetchSrc(0, c
))
3353 case TGSI_OPCODE_SLT
:
3354 case TGSI_OPCODE_SGE
:
3355 case TGSI_OPCODE_SEQ
:
3356 case TGSI_OPCODE_SGT
:
3357 case TGSI_OPCODE_SLE
:
3358 case TGSI_OPCODE_SNE
:
3359 case TGSI_OPCODE_FSEQ
:
3360 case TGSI_OPCODE_FSGE
:
3361 case TGSI_OPCODE_FSLT
:
3362 case TGSI_OPCODE_FSNE
:
3363 case TGSI_OPCODE_ISGE
:
3364 case TGSI_OPCODE_ISLT
:
3365 case TGSI_OPCODE_USEQ
:
3366 case TGSI_OPCODE_USGE
:
3367 case TGSI_OPCODE_USLT
:
3368 case TGSI_OPCODE_USNE
:
3369 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3370 src0
= fetchSrc(0, c
);
3371 src1
= fetchSrc(1, c
);
3372 mkCmp(op
, tgsi
.getSetCond(), dstTy
, dst0
[c
], srcTy
, src0
, src1
);
3375 case TGSI_OPCODE_VOTE_ALL
:
3376 case TGSI_OPCODE_VOTE_ANY
:
3377 case TGSI_OPCODE_VOTE_EQ
:
3378 val0
= new_LValue(func
, FILE_PREDICATE
);
3379 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3380 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, val0
, TYPE_U32
, fetchSrc(0, c
), zero
);
3381 mkOp1(op
, dstTy
, val0
, val0
)
3382 ->subOp
= tgsi::opcodeToSubOp(tgsi
.getOpcode());
3383 mkCvt(OP_CVT
, TYPE_U32
, dst0
[c
], TYPE_U8
, val0
);
3386 case TGSI_OPCODE_BALLOT
:
3387 if (!tgsi
.getDst(0).isMasked(0)) {
3388 val0
= new_LValue(func
, FILE_PREDICATE
);
3389 mkCmp(OP_SET
, CC_NE
, TYPE_U32
, val0
, TYPE_U32
, fetchSrc(0, 0), zero
);
3390 mkOp1(op
, TYPE_U32
, dst0
[0], val0
)->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
3392 if (!tgsi
.getDst(0).isMasked(1))
3393 mkMov(dst0
[1], zero
, TYPE_U32
);
3395 case TGSI_OPCODE_READ_FIRST
:
3396 // ReadFirstInvocationARB(src) is implemented as
3397 // ReadInvocationARB(src, findLSB(ballot(true)))
3398 val0
= getScratch();
3399 mkOp1(OP_VOTE
, TYPE_U32
, val0
, mkImm(1))->subOp
= NV50_IR_SUBOP_VOTE_ANY
;
3400 mkOp2(OP_EXTBF
, TYPE_U32
, val0
, val0
, mkImm(0x2000))
3401 ->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
3402 mkOp1(OP_BFIND
, TYPE_U32
, val0
, val0
)->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
3405 case TGSI_OPCODE_READ_INVOC
:
3406 if (tgsi
.getOpcode() == TGSI_OPCODE_READ_INVOC
)
3407 src1
= fetchSrc(1, 0);
3408 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3409 geni
= mkOp3(op
, dstTy
, dst0
[c
], fetchSrc(0, c
), src1
, mkImm(0x1f));
3410 geni
->subOp
= NV50_IR_SUBOP_SHFL_IDX
;
3413 case TGSI_OPCODE_CLOCK
:
3414 // Stick the 32-bit clock into the high dword of the logical result.
3415 if (!tgsi
.getDst(0).isMasked(0))
3416 mkOp1(OP_MOV
, TYPE_U32
, dst0
[0], zero
);
3417 if (!tgsi
.getDst(0).isMasked(1))
3418 mkOp1(OP_RDSV
, TYPE_U32
, dst0
[1], mkSysVal(SV_CLOCK
, 0))->fixed
= 1;
3420 case TGSI_OPCODE_READ_HELPER
:
3421 if (!tgsi
.getDst(0).isMasked(0))
3422 mkOp1(OP_RDSV
, TYPE_U32
, dst0
[0], mkSysVal(SV_THREAD_KILL
, 0))
3425 case TGSI_OPCODE_KILL_IF
:
3426 val0
= new_LValue(func
, FILE_PREDICATE
);
3428 for (c
= 0; c
< 4; ++c
) {
3429 const int s
= tgsi
.getSrc(0).getSwizzle(c
);
3430 if (mask
& (1 << s
))
3433 mkCmp(OP_SET
, CC_LT
, TYPE_F32
, val0
, TYPE_F32
, fetchSrc(0, c
), zero
);
3434 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_P
, val0
);
3437 case TGSI_OPCODE_KILL
:
3438 case TGSI_OPCODE_DEMOTE
:
3439 // TODO: Should we make KILL exit that invocation? Some old shaders
3441 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
);
3443 case TGSI_OPCODE_TEX
:
3444 case TGSI_OPCODE_TEX_LZ
:
3445 case TGSI_OPCODE_TXB
:
3446 case TGSI_OPCODE_TXL
:
3447 case TGSI_OPCODE_TXP
:
3448 case TGSI_OPCODE_LODQ
:
3450 handleTEX(dst0
, 1, 1, 0x03, 0x0f, 0x00, 0x00);
3452 case TGSI_OPCODE_TXD
:
3453 handleTEX(dst0
, 3, 3, 0x03, 0x0f, 0x10, 0x20);
3455 case TGSI_OPCODE_TG4
:
3456 handleTEX(dst0
, 2, 2, 0x03, 0x0f, 0x00, 0x00);
3458 case TGSI_OPCODE_TEX2
:
3459 handleTEX(dst0
, 2, 2, 0x03, 0x10, 0x00, 0x00);
3461 case TGSI_OPCODE_TXB2
:
3462 case TGSI_OPCODE_TXL2
:
3463 handleTEX(dst0
, 2, 2, 0x10, 0x0f, 0x00, 0x00);
3465 case TGSI_OPCODE_SAMPLE
:
3466 case TGSI_OPCODE_SAMPLE_B
:
3467 case TGSI_OPCODE_SAMPLE_D
:
3468 case TGSI_OPCODE_SAMPLE_L
:
3469 case TGSI_OPCODE_SAMPLE_C
:
3470 case TGSI_OPCODE_SAMPLE_C_LZ
:
3471 handleTEX(dst0
, 1, 2, 0x30, 0x30, 0x30, 0x40);
3473 case TGSI_OPCODE_TXF_LZ
:
3474 case TGSI_OPCODE_TXF
:
3475 handleTXF(dst0
, 1, 0x03);
3477 case TGSI_OPCODE_SAMPLE_I
:
3478 handleTXF(dst0
, 1, 0x03);
3480 case TGSI_OPCODE_SAMPLE_I_MS
:
3481 handleTXF(dst0
, 1, 0x20);
3483 case TGSI_OPCODE_TXQ
:
3484 case TGSI_OPCODE_SVIEWINFO
:
3485 handleTXQ(dst0
, TXQ_DIMS
, 1);
3487 case TGSI_OPCODE_TXQS
:
3488 // The TXQ_TYPE query returns samples in its 3rd arg, but we need it to
3490 dst0
[1] = dst0
[2] = dst0
[3] = NULL
;
3491 std::swap(dst0
[0], dst0
[2]);
3492 handleTXQ(dst0
, TXQ_TYPE
, 0);
3493 std::swap(dst0
[0], dst0
[2]);
3495 case TGSI_OPCODE_FBFETCH
:
3496 handleFBFETCH(dst0
);
3498 case TGSI_OPCODE_F2I
:
3499 case TGSI_OPCODE_F2U
:
3500 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3501 mkCvt(OP_CVT
, dstTy
, dst0
[c
], srcTy
, fetchSrc(0, c
))->rnd
= ROUND_Z
;
3503 case TGSI_OPCODE_I2F
:
3504 case TGSI_OPCODE_U2F
:
3505 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3506 mkCvt(OP_CVT
, dstTy
, dst0
[c
], srcTy
, fetchSrc(0, c
));
3508 case TGSI_OPCODE_PK2H
:
3509 val0
= getScratch();
3510 val1
= getScratch();
3511 mkCvt(OP_CVT
, TYPE_F16
, val0
, TYPE_F32
, fetchSrc(0, 0));
3512 mkCvt(OP_CVT
, TYPE_F16
, val1
, TYPE_F32
, fetchSrc(0, 1));
3513 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
)
3514 mkOp3(OP_INSBF
, TYPE_U32
, dst0
[c
], val1
, mkImm(0x1010), val0
);
3516 case TGSI_OPCODE_UP2H
:
3517 src0
= fetchSrc(0, 0);
3518 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3519 geni
= mkCvt(OP_CVT
, TYPE_F32
, dst0
[c
], TYPE_F16
, src0
);
3520 geni
->subOp
= c
& 1;
3523 case TGSI_OPCODE_EMIT
:
3524 /* export the saved viewport index */
3525 if (viewport
!= NULL
) {
3526 Symbol
*vpSym
= mkSymbol(FILE_SHADER_OUTPUT
, 0, TYPE_U32
,
3527 info
->out
[info
->io
.viewportId
].slot
[0] * 4);
3528 mkStore(OP_EXPORT
, TYPE_U32
, vpSym
, NULL
, viewport
);
3530 /* handle user clip planes for each emitted vertex */
3531 if (info
->io
.genUserClip
> 0)
3532 handleUserClipPlanes();
3534 case TGSI_OPCODE_ENDPRIM
:
3536 // get vertex stream (must be immediate)
3537 unsigned int stream
= tgsi
.getSrc(0).getValueU32(0, info
);
3538 if (stream
&& op
== OP_RESTART
)
3540 if (info
->prop
.gp
.maxVertices
== 0)
3542 src0
= mkImm(stream
);
3543 mkOp1(op
, TYPE_U32
, NULL
, src0
)->fixed
= 1;
3546 case TGSI_OPCODE_IF
:
3547 case TGSI_OPCODE_UIF
:
3549 BasicBlock
*ifBB
= new BasicBlock(func
);
3551 bb
->cfg
.attach(&ifBB
->cfg
, Graph::Edge::TREE
);
3555 mkFlow(OP_BRA
, NULL
, CC_NOT_P
, fetchSrc(0, 0))->setType(srcTy
);
3557 setPosition(ifBB
, true);
3560 case TGSI_OPCODE_ELSE
:
3562 BasicBlock
*elseBB
= new BasicBlock(func
);
3563 BasicBlock
*forkBB
= reinterpret_cast<BasicBlock
*>(condBBs
.pop().u
.p
);
3565 forkBB
->cfg
.attach(&elseBB
->cfg
, Graph::Edge::TREE
);
3568 forkBB
->getExit()->asFlow()->target
.bb
= elseBB
;
3569 if (!bb
->isTerminated())
3570 mkFlow(OP_BRA
, NULL
, CC_ALWAYS
, NULL
);
3572 setPosition(elseBB
, true);
3575 case TGSI_OPCODE_ENDIF
:
3577 BasicBlock
*convBB
= new BasicBlock(func
);
3578 BasicBlock
*prevBB
= reinterpret_cast<BasicBlock
*>(condBBs
.pop().u
.p
);
3579 BasicBlock
*forkBB
= reinterpret_cast<BasicBlock
*>(joinBBs
.pop().u
.p
);
3581 if (!bb
->isTerminated()) {
3582 // we only want join if none of the clauses ended with CONT/BREAK/RET
3583 if (prevBB
->getExit()->op
== OP_BRA
&& joinBBs
.getSize() < 6)
3584 insertConvergenceOps(convBB
, forkBB
);
3585 mkFlow(OP_BRA
, convBB
, CC_ALWAYS
, NULL
);
3586 bb
->cfg
.attach(&convBB
->cfg
, Graph::Edge::FORWARD
);
3589 if (prevBB
->getExit()->op
== OP_BRA
) {
3590 prevBB
->cfg
.attach(&convBB
->cfg
, Graph::Edge::FORWARD
);
3591 prevBB
->getExit()->asFlow()->target
.bb
= convBB
;
3593 setPosition(convBB
, true);
3596 case TGSI_OPCODE_BGNLOOP
:
3598 BasicBlock
*lbgnBB
= new BasicBlock(func
);
3599 BasicBlock
*lbrkBB
= new BasicBlock(func
);
3601 loopBBs
.push(lbgnBB
);
3602 breakBBs
.push(lbrkBB
);
3603 if (loopBBs
.getSize() > func
->loopNestingBound
)
3604 func
->loopNestingBound
++;
3606 mkFlow(OP_PREBREAK
, lbrkBB
, CC_ALWAYS
, NULL
);
3608 bb
->cfg
.attach(&lbgnBB
->cfg
, Graph::Edge::TREE
);
3609 setPosition(lbgnBB
, true);
3610 mkFlow(OP_PRECONT
, lbgnBB
, CC_ALWAYS
, NULL
);
3613 case TGSI_OPCODE_ENDLOOP
:
3615 BasicBlock
*loopBB
= reinterpret_cast<BasicBlock
*>(loopBBs
.pop().u
.p
);
3617 if (!bb
->isTerminated()) {
3618 mkFlow(OP_CONT
, loopBB
, CC_ALWAYS
, NULL
);
3619 bb
->cfg
.attach(&loopBB
->cfg
, Graph::Edge::BACK
);
3621 setPosition(reinterpret_cast<BasicBlock
*>(breakBBs
.pop().u
.p
), true);
3623 // If the loop never breaks (e.g. only has RET's inside), then there
3624 // will be no way to get to the break bb. However BGNLOOP will have
3625 // already made a PREBREAK to it, so it must be in the CFG.
3626 if (getBB()->cfg
.incidentCount() == 0)
3627 loopBB
->cfg
.attach(&getBB()->cfg
, Graph::Edge::TREE
);
3630 case TGSI_OPCODE_BRK
:
3632 if (bb
->isTerminated())
3634 BasicBlock
*brkBB
= reinterpret_cast<BasicBlock
*>(breakBBs
.peek().u
.p
);
3635 mkFlow(OP_BREAK
, brkBB
, CC_ALWAYS
, NULL
);
3636 bb
->cfg
.attach(&brkBB
->cfg
, Graph::Edge::CROSS
);
3639 case TGSI_OPCODE_CONT
:
3641 if (bb
->isTerminated())
3643 BasicBlock
*contBB
= reinterpret_cast<BasicBlock
*>(loopBBs
.peek().u
.p
);
3644 mkFlow(OP_CONT
, contBB
, CC_ALWAYS
, NULL
);
3645 contBB
->explicitCont
= true;
3646 bb
->cfg
.attach(&contBB
->cfg
, Graph::Edge::BACK
);
3649 case TGSI_OPCODE_BGNSUB
:
3651 Subroutine
*s
= getSubroutine(ip
);
3652 BasicBlock
*entry
= new BasicBlock(s
->f
);
3653 BasicBlock
*leave
= new BasicBlock(s
->f
);
3655 // multiple entrypoints possible, keep the graph connected
3656 if (prog
->getType() == Program::TYPE_COMPUTE
)
3657 prog
->main
->call
.attach(&s
->f
->call
, Graph::Edge::TREE
);
3660 s
->f
->setEntry(entry
);
3661 s
->f
->setExit(leave
);
3662 setPosition(entry
, true);
3665 case TGSI_OPCODE_ENDSUB
:
3667 sub
.cur
= getSubroutine(prog
->main
);
3668 setPosition(BasicBlock::get(sub
.cur
->f
->cfg
.getRoot()), true);
3671 case TGSI_OPCODE_CAL
:
3673 Subroutine
*s
= getSubroutine(tgsi
.getLabel());
3674 mkFlow(OP_CALL
, s
->f
, CC_ALWAYS
, NULL
);
3675 func
->call
.attach(&s
->f
->call
, Graph::Edge::TREE
);
3678 case TGSI_OPCODE_RET
:
3680 if (bb
->isTerminated())
3682 BasicBlock
*leave
= BasicBlock::get(func
->cfgExit
);
3684 if (!isEndOfSubroutine(ip
+ 1)) {
3685 // insert a PRERET at the entry if this is an early return
3686 // (only needed for sharing code in the epilogue)
3687 BasicBlock
*root
= BasicBlock::get(func
->cfg
.getRoot());
3688 if (root
->getEntry() == NULL
|| root
->getEntry()->op
!= OP_PRERET
) {
3689 BasicBlock
*pos
= getBB();
3690 setPosition(root
, false);
3691 mkFlow(OP_PRERET
, leave
, CC_ALWAYS
, NULL
)->fixed
= 1;
3692 setPosition(pos
, true);
3695 mkFlow(OP_RET
, NULL
, CC_ALWAYS
, NULL
)->fixed
= 1;
3696 bb
->cfg
.attach(&leave
->cfg
, Graph::Edge::CROSS
);
3699 case TGSI_OPCODE_END
:
3701 // attach and generate epilogue code
3702 BasicBlock
*epilogue
= BasicBlock::get(func
->cfgExit
);
3703 bb
->cfg
.attach(&epilogue
->cfg
, Graph::Edge::TREE
);
3704 setPosition(epilogue
, true);
3705 if (prog
->getType() == Program::TYPE_FRAGMENT
)
3707 if ((prog
->getType() == Program::TYPE_VERTEX
||
3708 prog
->getType() == Program::TYPE_TESSELLATION_EVAL
3709 ) && info
->io
.genUserClip
> 0)
3710 handleUserClipPlanes();
3711 mkOp(OP_EXIT
, TYPE_NONE
, NULL
)->terminator
= 1;
3714 case TGSI_OPCODE_SWITCH
:
3715 case TGSI_OPCODE_CASE
:
3716 ERROR("switch/case opcode encountered, should have been lowered\n");
3719 case TGSI_OPCODE_LOAD
:
3722 case TGSI_OPCODE_STORE
:
3725 case TGSI_OPCODE_BARRIER
:
3726 geni
= mkOp2(OP_BAR
, TYPE_U32
, NULL
, mkImm(0), mkImm(0));
3728 geni
->subOp
= NV50_IR_SUBOP_BAR_SYNC
;
3730 case TGSI_OPCODE_MEMBAR
:
3732 uint32_t level
= tgsi
.getSrc(0).getValueU32(0, info
);
3733 geni
= mkOp(OP_MEMBAR
, TYPE_NONE
, NULL
);
3735 if (!(level
& ~(TGSI_MEMBAR_THREAD_GROUP
| TGSI_MEMBAR_SHARED
)))
3736 geni
->subOp
= NV50_IR_SUBOP_MEMBAR(M
, CTA
);
3738 geni
->subOp
= NV50_IR_SUBOP_MEMBAR(M
, GL
);
3741 case TGSI_OPCODE_ATOMUADD
:
3742 case TGSI_OPCODE_ATOMXCHG
:
3743 case TGSI_OPCODE_ATOMCAS
:
3744 case TGSI_OPCODE_ATOMAND
:
3745 case TGSI_OPCODE_ATOMOR
:
3746 case TGSI_OPCODE_ATOMXOR
:
3747 case TGSI_OPCODE_ATOMUMIN
:
3748 case TGSI_OPCODE_ATOMIMIN
:
3749 case TGSI_OPCODE_ATOMUMAX
:
3750 case TGSI_OPCODE_ATOMIMAX
:
3751 case TGSI_OPCODE_ATOMFADD
:
3752 case TGSI_OPCODE_ATOMDEC_WRAP
:
3753 case TGSI_OPCODE_ATOMINC_WRAP
:
3754 handleATOM(dst0
, dstTy
, tgsi::opcodeToSubOp(tgsi
.getOpcode()));
3756 case TGSI_OPCODE_RESQ
:
3757 if (tgsi
.getSrc(0).getFile() == TGSI_FILE_BUFFER
) {
3759 if (tgsi
.getSrc(0).isIndirect(0))
3760 ind
= fetchSrc(tgsi
.getSrc(0).getIndirect(0), 0, 0);
3761 geni
= mkOp1(OP_BUFQ
, TYPE_U32
, dst0
[0],
3762 makeSym(tgsi
.getSrc(0).getFile(),
3763 tgsi
.getSrc(0).getIndex(0), -1, 0, 0));
3765 geni
->setIndirect(0, 1, ind
);
3767 TexInstruction
*texi
= new_TexInstruction(func
, OP_SUQ
);
3768 for (int c
= 0, d
= 0; c
< 4; ++c
) {
3770 texi
->setDef(d
++, dst0
[c
]);
3771 texi
->tex
.mask
|= 1 << c
;
3774 if (tgsi
.getSrc(0).getFile() == TGSI_FILE_IMAGE
) {
3775 texi
->tex
.r
= tgsi
.getSrc(0).getIndex(0);
3776 if (tgsi
.getSrc(0).isIndirect(0))
3777 texi
->setIndirectR(fetchSrc(tgsi
.getSrc(0).getIndirect(0), 0, NULL
));
3779 texi
->tex
.bindless
= true;
3780 texi
->setIndirectR(fetchSrc(0, 0));
3782 texi
->tex
.target
= tgsi
.getImageTarget();
3784 bb
->insertTail(texi
);
3787 case TGSI_OPCODE_IBFE
:
3788 case TGSI_OPCODE_UBFE
:
3789 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3790 src0
= fetchSrc(0, c
);
3791 val0
= getScratch();
3792 if (tgsi
.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE
&&
3793 tgsi
.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE
) {
3794 loadImm(val0
, (tgsi
.getSrc(2).getValueU32(c
, info
) << 8) |
3795 tgsi
.getSrc(1).getValueU32(c
, info
));
3797 src1
= fetchSrc(1, c
);
3798 src2
= fetchSrc(2, c
);
3799 mkOp3(OP_INSBF
, TYPE_U32
, val0
, src2
, mkImm(0x808), src1
);
3801 mkOp2(OP_EXTBF
, dstTy
, dst0
[c
], src0
, val0
);
3804 case TGSI_OPCODE_BFI
:
3805 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3806 src0
= fetchSrc(0, c
);
3807 src1
= fetchSrc(1, c
);
3808 src2
= fetchSrc(2, c
);
3809 src3
= fetchSrc(3, c
);
3810 val0
= getScratch();
3811 mkOp3(OP_INSBF
, TYPE_U32
, val0
, src3
, mkImm(0x808), src2
);
3812 mkOp3(OP_INSBF
, TYPE_U32
, dst0
[c
], src1
, val0
, src0
);
3815 case TGSI_OPCODE_LSB
:
3816 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3817 src0
= fetchSrc(0, c
);
3818 val0
= getScratch();
3819 geni
= mkOp2(OP_EXTBF
, TYPE_U32
, val0
, src0
, mkImm(0x2000));
3820 geni
->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
3821 geni
= mkOp1(OP_BFIND
, TYPE_U32
, dst0
[c
], val0
);
3822 geni
->subOp
= NV50_IR_SUBOP_BFIND_SAMT
;
3825 case TGSI_OPCODE_IMSB
:
3826 case TGSI_OPCODE_UMSB
:
3827 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3828 src0
= fetchSrc(0, c
);
3829 mkOp1(OP_BFIND
, srcTy
, dst0
[c
], src0
);
3832 case TGSI_OPCODE_BREV
:
3833 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3834 src0
= fetchSrc(0, c
);
3835 geni
= mkOp2(OP_EXTBF
, TYPE_U32
, dst0
[c
], src0
, mkImm(0x2000));
3836 geni
->subOp
= NV50_IR_SUBOP_EXTBF_REV
;
3839 case TGSI_OPCODE_POPC
:
3840 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3841 src0
= fetchSrc(0, c
);
3842 mkOp2(OP_POPCNT
, TYPE_U32
, dst0
[c
], src0
, src0
);
3845 case TGSI_OPCODE_INTERP_CENTROID
:
3846 case TGSI_OPCODE_INTERP_SAMPLE
:
3847 case TGSI_OPCODE_INTERP_OFFSET
:
3850 case TGSI_OPCODE_I642F
:
3851 case TGSI_OPCODE_U642F
:
3852 case TGSI_OPCODE_D2I
:
3853 case TGSI_OPCODE_D2U
:
3854 case TGSI_OPCODE_D2F
: {
3856 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3857 Value
*dreg
= getSSA(8);
3858 src0
= fetchSrc(0, pos
);
3859 src1
= fetchSrc(0, pos
+ 1);
3860 mkOp2(OP_MERGE
, TYPE_U64
, dreg
, src0
, src1
);
3861 Instruction
*cvt
= mkCvt(OP_CVT
, dstTy
, dst0
[c
], srcTy
, dreg
);
3862 if (!isFloatType(dstTy
))
3868 case TGSI_OPCODE_I2I64
:
3869 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3870 dst0
[c
] = fetchSrc(0, c
/ 2);
3871 mkOp2(OP_SHR
, TYPE_S32
, dst0
[c
+ 1], dst0
[c
], loadImm(NULL
, 31));
3875 case TGSI_OPCODE_U2I64
:
3876 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3877 dst0
[c
] = fetchSrc(0, c
/ 2);
3882 case TGSI_OPCODE_F2I64
:
3883 case TGSI_OPCODE_F2U64
:
3884 case TGSI_OPCODE_I2D
:
3885 case TGSI_OPCODE_U2D
:
3886 case TGSI_OPCODE_F2D
:
3887 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3888 Value
*dreg
= getSSA(8);
3889 Instruction
*cvt
= mkCvt(OP_CVT
, dstTy
, dreg
, srcTy
, fetchSrc(0, c
/ 2));
3890 if (!isFloatType(dstTy
))
3892 mkSplit(&dst0
[c
], 4, dreg
);
3896 case TGSI_OPCODE_D2I64
:
3897 case TGSI_OPCODE_D2U64
:
3898 case TGSI_OPCODE_I642D
:
3899 case TGSI_OPCODE_U642D
:
3900 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3902 Value
*dst
= getSSA(8), *tmp
[2];
3903 tmp
[0] = fetchSrc(0, c
);
3904 tmp
[1] = fetchSrc(0, c
+ 1);
3905 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
3906 Instruction
*cvt
= mkCvt(OP_CVT
, dstTy
, dst
, srcTy
, src0
);
3907 if (!isFloatType(dstTy
))
3909 mkSplit(&dst0
[c
], 4, dst
);
3913 case TGSI_OPCODE_I64NEG
:
3914 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3916 Value
*dst
= getSSA(8), *tmp
[2];
3917 tmp
[0] = fetchSrc(0, c
);
3918 tmp
[1] = fetchSrc(0, c
+ 1);
3919 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
3920 mkOp2(OP_SUB
, dstTy
, dst
, zero
, src0
);
3921 mkSplit(&dst0
[c
], 4, dst
);
3925 case TGSI_OPCODE_I64ABS
:
3926 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3928 Value
*neg
= getSSA(8), *srcComp
[2], *negComp
[2];
3929 srcComp
[0] = fetchSrc(0, c
);
3930 srcComp
[1] = fetchSrc(0, c
+ 1);
3931 mkOp2(OP_MERGE
, TYPE_U64
, src0
, srcComp
[0], srcComp
[1]);
3932 mkOp2(OP_SUB
, dstTy
, neg
, zero
, src0
);
3933 mkSplit(negComp
, 4, neg
);
3934 mkCmp(OP_SLCT
, CC_LT
, TYPE_S32
, dst0
[c
], TYPE_S32
,
3935 negComp
[0], srcComp
[0], srcComp
[1]);
3936 mkCmp(OP_SLCT
, CC_LT
, TYPE_S32
, dst0
[c
+ 1], TYPE_S32
,
3937 negComp
[1], srcComp
[1], srcComp
[1]);
3941 case TGSI_OPCODE_DABS
:
3942 case TGSI_OPCODE_DNEG
:
3943 case TGSI_OPCODE_DRCP
:
3944 case TGSI_OPCODE_DSQRT
:
3945 case TGSI_OPCODE_DRSQ
:
3946 case TGSI_OPCODE_DTRUNC
:
3947 case TGSI_OPCODE_DCEIL
:
3948 case TGSI_OPCODE_DFLR
:
3949 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3951 Value
*dst
= getSSA(8), *tmp
[2];
3952 tmp
[0] = fetchSrc(0, c
);
3953 tmp
[1] = fetchSrc(0, c
+ 1);
3954 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
3955 mkOp1(op
, dstTy
, dst
, src0
);
3956 mkSplit(&dst0
[c
], 4, dst
);
3960 case TGSI_OPCODE_DFRAC
:
3961 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3963 Value
*dst
= getSSA(8), *tmp
[2];
3964 tmp
[0] = fetchSrc(0, c
);
3965 tmp
[1] = fetchSrc(0, c
+ 1);
3966 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
3967 mkOp1(OP_FLOOR
, TYPE_F64
, dst
, src0
);
3968 mkOp2(OP_SUB
, TYPE_F64
, dst
, src0
, dst
);
3969 mkSplit(&dst0
[c
], 4, dst
);
3973 case TGSI_OPCODE_U64SEQ
:
3974 case TGSI_OPCODE_U64SNE
:
3975 case TGSI_OPCODE_U64SLT
:
3976 case TGSI_OPCODE_U64SGE
:
3977 case TGSI_OPCODE_I64SLT
:
3978 case TGSI_OPCODE_I64SGE
:
3979 case TGSI_OPCODE_DSLT
:
3980 case TGSI_OPCODE_DSGE
:
3981 case TGSI_OPCODE_DSEQ
:
3982 case TGSI_OPCODE_DSNE
: {
3984 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
3989 tmp
[0] = fetchSrc(0, pos
);
3990 tmp
[1] = fetchSrc(0, pos
+ 1);
3991 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
3992 tmp
[0] = fetchSrc(1, pos
);
3993 tmp
[1] = fetchSrc(1, pos
+ 1);
3994 mkOp2(OP_MERGE
, TYPE_U64
, src1
, tmp
[0], tmp
[1]);
3995 mkCmp(op
, tgsi
.getSetCond(), dstTy
, dst0
[c
], srcTy
, src0
, src1
);
4000 case TGSI_OPCODE_U64MIN
:
4001 case TGSI_OPCODE_U64MAX
:
4002 case TGSI_OPCODE_I64MIN
:
4003 case TGSI_OPCODE_I64MAX
: {
4004 dstTy
= isSignedIntType(dstTy
) ? TYPE_S32
: TYPE_U32
;
4005 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4006 Value
*flag
= getSSA(1, FILE_FLAGS
);
4007 src0
= fetchSrc(0, c
+ 1);
4008 src1
= fetchSrc(1, c
+ 1);
4009 geni
= mkOp2(op
, dstTy
, dst0
[c
+ 1], src0
, src1
);
4010 geni
->subOp
= NV50_IR_SUBOP_MINMAX_HIGH
;
4011 geni
->setFlagsDef(1, flag
);
4013 src0
= fetchSrc(0, c
);
4014 src1
= fetchSrc(1, c
);
4015 geni
= mkOp2(op
, TYPE_U32
, dst0
[c
], src0
, src1
);
4016 geni
->subOp
= NV50_IR_SUBOP_MINMAX_LOW
;
4017 geni
->setFlagsSrc(2, flag
);
4023 case TGSI_OPCODE_U64SHL
:
4024 case TGSI_OPCODE_I64SHR
:
4025 case TGSI_OPCODE_U64SHR
:
4026 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4028 Value
*dst
= getSSA(8), *tmp
[2];
4029 tmp
[0] = fetchSrc(0, c
);
4030 tmp
[1] = fetchSrc(0, c
+ 1);
4031 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4032 // Theoretically src1 is a 64-bit value but in practice only the low
4033 // bits matter. The IR expects this to be a 32-bit value.
4034 src1
= fetchSrc(1, c
);
4035 mkOp2(op
, dstTy
, dst
, src0
, src1
);
4036 mkSplit(&dst0
[c
], 4, dst
);
4040 case TGSI_OPCODE_U64ADD
:
4041 case TGSI_OPCODE_U64MUL
:
4042 case TGSI_OPCODE_DADD
:
4043 case TGSI_OPCODE_DMUL
:
4044 case TGSI_OPCODE_DDIV
:
4045 case TGSI_OPCODE_DMAX
:
4046 case TGSI_OPCODE_DMIN
:
4047 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4050 Value
*dst
= getSSA(8), *tmp
[2];
4051 tmp
[0] = fetchSrc(0, c
);
4052 tmp
[1] = fetchSrc(0, c
+ 1);
4053 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4054 tmp
[0] = fetchSrc(1, c
);
4055 tmp
[1] = fetchSrc(1, c
+ 1);
4056 mkOp2(OP_MERGE
, TYPE_U64
, src1
, tmp
[0], tmp
[1]);
4057 mkOp2(op
, dstTy
, dst
, src0
, src1
);
4058 mkSplit(&dst0
[c
], 4, dst
);
4062 case TGSI_OPCODE_DMAD
:
4063 case TGSI_OPCODE_DFMA
:
4064 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4068 Value
*dst
= getSSA(8), *tmp
[2];
4069 tmp
[0] = fetchSrc(0, c
);
4070 tmp
[1] = fetchSrc(0, c
+ 1);
4071 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4072 tmp
[0] = fetchSrc(1, c
);
4073 tmp
[1] = fetchSrc(1, c
+ 1);
4074 mkOp2(OP_MERGE
, TYPE_U64
, src1
, tmp
[0], tmp
[1]);
4075 tmp
[0] = fetchSrc(2, c
);
4076 tmp
[1] = fetchSrc(2, c
+ 1);
4077 mkOp2(OP_MERGE
, TYPE_U64
, src2
, tmp
[0], tmp
[1]);
4078 mkOp3(op
, dstTy
, dst
, src0
, src1
, src2
);
4079 mkSplit(&dst0
[c
], 4, dst
);
4083 case TGSI_OPCODE_DROUND
:
4084 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4086 Value
*dst
= getSSA(8), *tmp
[2];
4087 tmp
[0] = fetchSrc(0, c
);
4088 tmp
[1] = fetchSrc(0, c
+ 1);
4089 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4090 mkCvt(OP_CVT
, TYPE_F64
, dst
, TYPE_F64
, src0
)
4092 mkSplit(&dst0
[c
], 4, dst
);
4096 case TGSI_OPCODE_DSSG
:
4097 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4099 Value
*dst
= getSSA(8), *dstF32
= getSSA(), *tmp
[2];
4100 tmp
[0] = fetchSrc(0, c
);
4101 tmp
[1] = fetchSrc(0, c
+ 1);
4102 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4104 val0
= getScratch();
4105 val1
= getScratch();
4106 // The zero is wrong here since it's only 32-bit, but it works out in
4107 // the end since it gets replaced with $r63.
4108 mkCmp(OP_SET
, CC_GT
, TYPE_F32
, val0
, TYPE_F64
, src0
, zero
);
4109 mkCmp(OP_SET
, CC_LT
, TYPE_F32
, val1
, TYPE_F64
, src0
, zero
);
4110 mkOp2(OP_SUB
, TYPE_F32
, dstF32
, val0
, val1
);
4111 mkCvt(OP_CVT
, TYPE_F64
, dst
, TYPE_F32
, dstF32
);
4112 mkSplit(&dst0
[c
], 4, dst
);
4116 case TGSI_OPCODE_I64SSG
:
4117 FOR_EACH_DST_ENABLED_CHANNEL(0, c
, tgsi
) {
4120 tmp
[0] = fetchSrc(0, c
);
4121 tmp
[1] = fetchSrc(0, c
+ 1);
4122 mkOp2(OP_MERGE
, TYPE_U64
, src0
, tmp
[0], tmp
[1]);
4124 val0
= getScratch();
4125 val1
= getScratch();
4126 mkCmp(OP_SET
, CC_GT
, TYPE_U32
, val0
, TYPE_S64
, src0
, zero
);
4127 mkCmp(OP_SET
, CC_LT
, TYPE_U32
, val1
, TYPE_S64
, src0
, zero
);
4128 mkOp2(OP_SUB
, TYPE_S32
, dst0
[c
], val1
, val0
);
4129 mkOp2(OP_SHR
, TYPE_S32
, dst0
[c
+ 1], dst0
[c
], loadImm(0, 31));
4134 ERROR("unhandled TGSI opcode: %u\n", tgsi
.getOpcode());
4139 if (tgsi
.dstCount() && tgsi
.getOpcode() != TGSI_OPCODE_STORE
) {
4140 for (c
= 0; c
< 4; ++c
) {
4143 if (dst0
[c
] != rDst0
[c
])
4144 mkMov(rDst0
[c
], dst0
[c
]);
4145 storeDst(0, c
, rDst0
[c
]);
4154 Converter::exportOutputs()
4156 if (info
->io
.alphaRefBase
) {
4157 for (unsigned int i
= 0; i
< info
->numOutputs
; ++i
) {
4158 if (info
->out
[i
].sn
!= TGSI_SEMANTIC_COLOR
||
4159 info
->out
[i
].si
!= 0)
4161 const unsigned int c
= 3;
4162 if (!oData
.exists(sub
.cur
->values
, i
, c
))
4164 Value
*val
= oData
.load(sub
.cur
->values
, i
, c
, NULL
);
4168 Symbol
*ref
= mkSymbol(FILE_MEMORY_CONST
, info
->io
.auxCBSlot
,
4169 TYPE_U32
, info
->io
.alphaRefBase
);
4170 Value
*pred
= new_LValue(func
, FILE_PREDICATE
);
4171 mkCmp(OP_SET
, CC_TR
, TYPE_U32
, pred
, TYPE_F32
, val
,
4172 mkLoadv(TYPE_U32
, ref
, NULL
))
4174 mkOp(OP_DISCARD
, TYPE_NONE
, NULL
)->setPredicate(CC_NOT_P
, pred
);
4178 for (unsigned int i
= 0; i
< info
->numOutputs
; ++i
) {
4179 for (unsigned int c
= 0; c
< 4; ++c
) {
4180 if (!oData
.exists(sub
.cur
->values
, i
, c
))
4182 Symbol
*sym
= mkSymbol(FILE_SHADER_OUTPUT
, 0, TYPE_F32
,
4183 info
->out
[i
].slot
[c
] * 4);
4184 Value
*val
= oData
.load(sub
.cur
->values
, i
, c
, NULL
);
4186 if (info
->out
[i
].sn
== TGSI_SEMANTIC_POSITION
)
4187 mkOp1(OP_SAT
, TYPE_F32
, val
, val
);
4188 mkStore(OP_EXPORT
, TYPE_F32
, sym
, NULL
, val
);
4194 Converter::Converter(Program
*ir
, const tgsi::Source
*code
) : ConverterCommon(ir
, code
->info
),
4197 tData(this), lData(this), aData(this), oData(this)
4199 const unsigned tSize
= code
->fileSize(TGSI_FILE_TEMPORARY
);
4200 const unsigned aSize
= code
->fileSize(TGSI_FILE_ADDRESS
);
4201 const unsigned oSize
= code
->fileSize(TGSI_FILE_OUTPUT
);
4203 tData
.setup(TGSI_FILE_TEMPORARY
, 0, 0, tSize
, 4, 4, FILE_GPR
, 0);
4204 lData
.setup(TGSI_FILE_TEMPORARY
, 1, 0, tSize
, 4, 4, FILE_MEMORY_LOCAL
, 0);
4205 aData
.setup(TGSI_FILE_ADDRESS
, 0, 0, aSize
, 4, 4, FILE_GPR
, 0);
4206 oData
.setup(TGSI_FILE_OUTPUT
, 0, 0, oSize
, 4, 4, FILE_GPR
, 0);
4208 zero
= mkImm((uint32_t)0);
4213 Converter::~Converter()
4217 inline const Converter::Location
*
4218 Converter::BindArgumentsPass::getValueLocation(Subroutine
*s
, Value
*v
)
4220 ValueMap::l_iterator it
= s
->values
.l
.find(v
);
4221 return it
== s
->values
.l
.end() ? NULL
: &it
->second
;
4224 template<typename T
> inline void
4225 Converter::BindArgumentsPass::updateCallArgs(
4226 Instruction
*i
, void (Instruction::*setArg
)(int, Value
*),
4227 T (Function::*proto
))
4229 Function
*g
= i
->asFlow()->target
.fn
;
4230 Subroutine
*subg
= conv
.getSubroutine(g
);
4232 for (unsigned a
= 0; a
< (g
->*proto
).size(); ++a
) {
4233 Value
*v
= (g
->*proto
)[a
].get();
4234 const Converter::Location
&l
= *getValueLocation(subg
, v
);
4235 Converter::DataArray
*array
= conv
.getArrayForFile(l
.array
, l
.arrayIdx
);
4237 (i
->*setArg
)(a
, array
->acquire(sub
->values
, l
.i
, l
.c
));
4241 template<typename T
> inline void
4242 Converter::BindArgumentsPass::updatePrototype(
4243 BitSet
*set
, void (Function::*updateSet
)(), T (Function::*proto
))
4245 (func
->*updateSet
)();
4247 for (unsigned i
= 0; i
< set
->getSize(); ++i
) {
4248 Value
*v
= func
->getLValue(i
);
4249 const Converter::Location
*l
= getValueLocation(sub
, v
);
4251 // only include values with a matching TGSI register
4252 if (set
->test(i
) && l
&& !conv
.code
->locals
.count(*l
))
4253 (func
->*proto
).push_back(v
);
4258 Converter::BindArgumentsPass::visit(Function
*f
)
4260 sub
= conv
.getSubroutine(f
);
4262 for (ArrayList::Iterator bi
= f
->allBBlocks
.iterator();
4263 !bi
.end(); bi
.next()) {
4264 for (Instruction
*i
= BasicBlock::get(bi
)->getFirst();
4266 if (i
->op
== OP_CALL
&& !i
->asFlow()->builtin
) {
4267 updateCallArgs(i
, &Instruction::setSrc
, &Function::ins
);
4268 updateCallArgs(i
, &Instruction::setDef
, &Function::outs
);
4273 if (func
== prog
->main
/* && prog->getType() != Program::TYPE_COMPUTE */)
4275 updatePrototype(&BasicBlock::get(f
->cfg
.getRoot())->liveSet
,
4276 &Function::buildLiveSets
, &Function::ins
);
4277 updatePrototype(&BasicBlock::get(f
->cfgExit
)->defSet
,
4278 &Function::buildDefSets
, &Function::outs
);
4286 BasicBlock
*entry
= new BasicBlock(prog
->main
);
4287 BasicBlock
*leave
= new BasicBlock(prog
->main
);
4289 prog
->main
->setEntry(entry
);
4290 prog
->main
->setExit(leave
);
4292 setPosition(entry
, true);
4293 sub
.cur
= getSubroutine(prog
->main
);
4295 if (info
->io
.genUserClip
> 0) {
4296 for (int c
= 0; c
< 4; ++c
)
4297 clipVtx
[c
] = getScratch();
4300 switch (prog
->getType()) {
4301 case Program::TYPE_TESSELLATION_CONTROL
:
4303 OP_SUB
, TYPE_U32
, getSSA(),
4304 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_LANEID
, 0)),
4305 mkOp1v(OP_RDSV
, TYPE_U32
, getSSA(), mkSysVal(SV_INVOCATION_ID
, 0)));
4307 case Program::TYPE_FRAGMENT
: {
4308 Symbol
*sv
= mkSysVal(SV_POSITION
, 3);
4309 fragCoord
[3] = mkOp1v(OP_RDSV
, TYPE_F32
, getSSA(), sv
);
4310 mkOp1(OP_RCP
, TYPE_F32
, fragCoord
[3], fragCoord
[3]);
4317 if (info
->io
.viewportId
>= 0)
4318 viewport
= getScratch();
4322 for (ip
= 0; ip
< code
->scan
.num_instructions
; ++ip
) {
4323 if (!handleInstruction(&code
->insns
[ip
]))
4327 if (!BindArgumentsPass(*this).run(prog
))
4333 } // unnamed namespace
4338 Program::makeFromTGSI(struct nv50_ir_prog_info
*info
)
4340 tgsi::Source
src(info
);
4341 if (!src
.scanSource())
4343 tlsSize
= info
->bin
.tlsSpace
;
4345 Converter
builder(this, &src
);
4346 return builder
.run();
4349 } // namespace nv50_ir