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nv50/ir: process texture offset sources as regular sources
[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_from_tgsi.cpp
1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "tgsi/tgsi_dump.h"
24 #include "tgsi/tgsi_scan.h"
25 #include "tgsi/tgsi_util.h"
26
27 #include <set>
28
29 #include "codegen/nv50_ir.h"
30 #include "codegen/nv50_ir_util.h"
31 #include "codegen/nv50_ir_build_util.h"
32
33 namespace tgsi {
34
35 class Source;
36
37 static nv50_ir::operation translateOpcode(uint opcode);
38 static nv50_ir::DataFile translateFile(uint file);
39 static nv50_ir::TexTarget translateTexture(uint texTarg);
40 static nv50_ir::SVSemantic translateSysVal(uint sysval);
41 static nv50_ir::CacheMode translateCacheMode(uint qualifier);
42 static nv50_ir::ImgFormat translateImgFormat(uint format);
43
44 class Instruction
45 {
46 public:
47 Instruction(const struct tgsi_full_instruction *inst) : insn(inst) { }
48
49 class SrcRegister
50 {
51 public:
52 SrcRegister(const struct tgsi_full_src_register *src)
53 : reg(src->Register),
54 fsr(src)
55 { }
56
57 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
58
59 SrcRegister(const struct tgsi_ind_register& ind)
60 : reg(tgsi_util_get_src_from_ind(&ind)),
61 fsr(NULL)
62 { }
63
64 struct tgsi_src_register offsetToSrc(struct tgsi_texture_offset off)
65 {
66 struct tgsi_src_register reg;
67 memset(&reg, 0, sizeof(reg));
68 reg.Index = off.Index;
69 reg.File = off.File;
70 reg.SwizzleX = off.SwizzleX;
71 reg.SwizzleY = off.SwizzleY;
72 reg.SwizzleZ = off.SwizzleZ;
73 return reg;
74 }
75
76 SrcRegister(const struct tgsi_texture_offset& off) :
77 reg(offsetToSrc(off)),
78 fsr(NULL)
79 { }
80
81 uint getFile() const { return reg.File; }
82
83 bool is2D() const { return reg.Dimension; }
84
85 bool isIndirect(int dim) const
86 {
87 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
88 }
89
90 int getIndex(int dim) const
91 {
92 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
93 }
94
95 int getSwizzle(int chan) const
96 {
97 return tgsi_util_get_src_register_swizzle(&reg, chan);
98 }
99
100 int getArrayId() const
101 {
102 if (isIndirect(0))
103 return fsr->Indirect.ArrayID;
104 return 0;
105 }
106
107 nv50_ir::Modifier getMod(int chan) const;
108
109 SrcRegister getIndirect(int dim) const
110 {
111 assert(fsr && isIndirect(dim));
112 if (dim)
113 return SrcRegister(fsr->DimIndirect);
114 return SrcRegister(fsr->Indirect);
115 }
116
117 uint32_t getValueU32(int c, const struct nv50_ir_prog_info *info) const
118 {
119 assert(reg.File == TGSI_FILE_IMMEDIATE);
120 assert(!reg.Absolute);
121 assert(!reg.Negate);
122 return info->immd.data[reg.Index * 4 + getSwizzle(c)];
123 }
124
125 private:
126 const struct tgsi_src_register reg;
127 const struct tgsi_full_src_register *fsr;
128 };
129
130 class DstRegister
131 {
132 public:
133 DstRegister(const struct tgsi_full_dst_register *dst)
134 : reg(dst->Register),
135 fdr(dst)
136 { }
137
138 DstRegister(const struct tgsi_dst_register& dst) : reg(dst), fdr(NULL) { }
139
140 uint getFile() const { return reg.File; }
141
142 bool is2D() const { return reg.Dimension; }
143
144 bool isIndirect(int dim) const
145 {
146 return (dim && fdr) ? fdr->Dimension.Indirect : reg.Indirect;
147 }
148
149 int getIndex(int dim) const
150 {
151 return (dim && fdr) ? fdr->Dimension.Dimension : reg.Index;
152 }
153
154 unsigned int getMask() const { return reg.WriteMask; }
155
156 bool isMasked(int chan) const { return !(getMask() & (1 << chan)); }
157
158 SrcRegister getIndirect(int dim) const
159 {
160 assert(fdr && isIndirect(dim));
161 if (dim)
162 return SrcRegister(fdr->DimIndirect);
163 return SrcRegister(fdr->Indirect);
164 }
165
166 int getArrayId() const
167 {
168 if (isIndirect(0))
169 return fdr->Indirect.ArrayID;
170 return 0;
171 }
172
173 private:
174 const struct tgsi_dst_register reg;
175 const struct tgsi_full_dst_register *fdr;
176 };
177
178 inline uint getOpcode() const { return insn->Instruction.Opcode; }
179
180 unsigned int srcCount() const { return insn->Instruction.NumSrcRegs; }
181 unsigned int dstCount() const { return insn->Instruction.NumDstRegs; }
182
183 // mask of used components of source s
184 unsigned int srcMask(unsigned int s) const;
185 unsigned int texOffsetMask() const;
186
187 SrcRegister getSrc(unsigned int s) const
188 {
189 assert(s < srcCount());
190 return SrcRegister(&insn->Src[s]);
191 }
192
193 DstRegister getDst(unsigned int d) const
194 {
195 assert(d < dstCount());
196 return DstRegister(&insn->Dst[d]);
197 }
198
199 SrcRegister getTexOffset(unsigned int i) const
200 {
201 assert(i < TGSI_FULL_MAX_TEX_OFFSETS);
202 return SrcRegister(insn->TexOffsets[i]);
203 }
204
205 unsigned int getNumTexOffsets() const { return insn->Texture.NumOffsets; }
206
207 bool checkDstSrcAliasing() const;
208
209 inline nv50_ir::operation getOP() const {
210 return translateOpcode(getOpcode()); }
211
212 nv50_ir::DataType inferSrcType() const;
213 nv50_ir::DataType inferDstType() const;
214
215 nv50_ir::CondCode getSetCond() const;
216
217 nv50_ir::TexInstruction::Target getTexture(const Source *, int s) const;
218
219 nv50_ir::CacheMode getCacheMode() const {
220 if (!insn->Instruction.Memory)
221 return nv50_ir::CACHE_CA;
222 return translateCacheMode(insn->Memory.Qualifier);
223 }
224
225 inline uint getLabel() { return insn->Label.Label; }
226
227 unsigned getSaturate() const { return insn->Instruction.Saturate; }
228
229 void print() const
230 {
231 tgsi_dump_instruction(insn, 1);
232 }
233
234 private:
235 const struct tgsi_full_instruction *insn;
236 };
237
238 unsigned int Instruction::texOffsetMask() const
239 {
240 const struct tgsi_instruction_texture *tex = &insn->Texture;
241 assert(insn->Instruction.Texture);
242
243 switch (tex->Texture) {
244 case TGSI_TEXTURE_BUFFER:
245 case TGSI_TEXTURE_1D:
246 case TGSI_TEXTURE_SHADOW1D:
247 case TGSI_TEXTURE_1D_ARRAY:
248 case TGSI_TEXTURE_SHADOW1D_ARRAY:
249 return 0x1;
250 case TGSI_TEXTURE_2D:
251 case TGSI_TEXTURE_SHADOW2D:
252 case TGSI_TEXTURE_2D_ARRAY:
253 case TGSI_TEXTURE_SHADOW2D_ARRAY:
254 case TGSI_TEXTURE_RECT:
255 case TGSI_TEXTURE_SHADOWRECT:
256 case TGSI_TEXTURE_2D_MSAA:
257 case TGSI_TEXTURE_2D_ARRAY_MSAA:
258 return 0x3;
259 case TGSI_TEXTURE_3D:
260 return 0x7;
261 default:
262 assert(!"Unexpected texture target");
263 return 0xf;
264 }
265 }
266
267 unsigned int Instruction::srcMask(unsigned int s) const
268 {
269 unsigned int mask = insn->Dst[0].Register.WriteMask;
270
271 switch (insn->Instruction.Opcode) {
272 case TGSI_OPCODE_COS:
273 case TGSI_OPCODE_SIN:
274 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
275 case TGSI_OPCODE_DP2:
276 return 0x3;
277 case TGSI_OPCODE_DP3:
278 return 0x7;
279 case TGSI_OPCODE_DP4:
280 case TGSI_OPCODE_DPH:
281 case TGSI_OPCODE_KILL_IF: /* WriteMask ignored */
282 return 0xf;
283 case TGSI_OPCODE_DST:
284 return mask & (s ? 0xa : 0x6);
285 case TGSI_OPCODE_EX2:
286 case TGSI_OPCODE_EXP:
287 case TGSI_OPCODE_LG2:
288 case TGSI_OPCODE_LOG:
289 case TGSI_OPCODE_POW:
290 case TGSI_OPCODE_RCP:
291 case TGSI_OPCODE_RSQ:
292 case TGSI_OPCODE_SCS:
293 return 0x1;
294 case TGSI_OPCODE_IF:
295 case TGSI_OPCODE_UIF:
296 return 0x1;
297 case TGSI_OPCODE_LIT:
298 return 0xb;
299 case TGSI_OPCODE_TEX2:
300 case TGSI_OPCODE_TXB2:
301 case TGSI_OPCODE_TXL2:
302 return (s == 0) ? 0xf : 0x3;
303 case TGSI_OPCODE_TEX:
304 case TGSI_OPCODE_TXB:
305 case TGSI_OPCODE_TXD:
306 case TGSI_OPCODE_TXL:
307 case TGSI_OPCODE_TXP:
308 case TGSI_OPCODE_LODQ:
309 {
310 const struct tgsi_instruction_texture *tex = &insn->Texture;
311
312 assert(insn->Instruction.Texture);
313
314 mask = 0x7;
315 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
316 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
317 mask |= 0x8; /* bias, lod or proj */
318
319 switch (tex->Texture) {
320 case TGSI_TEXTURE_1D:
321 mask &= 0x9;
322 break;
323 case TGSI_TEXTURE_SHADOW1D:
324 mask &= 0xd;
325 break;
326 case TGSI_TEXTURE_1D_ARRAY:
327 case TGSI_TEXTURE_2D:
328 case TGSI_TEXTURE_RECT:
329 mask &= 0xb;
330 break;
331 case TGSI_TEXTURE_CUBE_ARRAY:
332 case TGSI_TEXTURE_SHADOW2D_ARRAY:
333 case TGSI_TEXTURE_SHADOWCUBE:
334 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
335 mask |= 0x8;
336 break;
337 default:
338 break;
339 }
340 }
341 return mask;
342 case TGSI_OPCODE_XPD:
343 {
344 unsigned int x = 0;
345 if (mask & 1) x |= 0x6;
346 if (mask & 2) x |= 0x5;
347 if (mask & 4) x |= 0x3;
348 return x;
349 }
350 case TGSI_OPCODE_D2I:
351 case TGSI_OPCODE_D2U:
352 case TGSI_OPCODE_D2F:
353 case TGSI_OPCODE_DSLT:
354 case TGSI_OPCODE_DSGE:
355 case TGSI_OPCODE_DSEQ:
356 case TGSI_OPCODE_DSNE:
357 switch (util_bitcount(mask)) {
358 case 1: return 0x3;
359 case 2: return 0xf;
360 default:
361 assert(!"unexpected mask");
362 return 0xf;
363 }
364 case TGSI_OPCODE_I2D:
365 case TGSI_OPCODE_U2D:
366 case TGSI_OPCODE_F2D: {
367 unsigned int x = 0;
368 if ((mask & 0x3) == 0x3)
369 x |= 1;
370 if ((mask & 0xc) == 0xc)
371 x |= 2;
372 return x;
373 }
374 case TGSI_OPCODE_PK2H:
375 return 0x3;
376 case TGSI_OPCODE_UP2H:
377 return 0x1;
378 default:
379 break;
380 }
381
382 return mask;
383 }
384
385 nv50_ir::Modifier Instruction::SrcRegister::getMod(int chan) const
386 {
387 nv50_ir::Modifier m(0);
388
389 if (reg.Absolute)
390 m = m | nv50_ir::Modifier(NV50_IR_MOD_ABS);
391 if (reg.Negate)
392 m = m | nv50_ir::Modifier(NV50_IR_MOD_NEG);
393 return m;
394 }
395
396 static nv50_ir::DataFile translateFile(uint file)
397 {
398 switch (file) {
399 case TGSI_FILE_CONSTANT: return nv50_ir::FILE_MEMORY_CONST;
400 case TGSI_FILE_INPUT: return nv50_ir::FILE_SHADER_INPUT;
401 case TGSI_FILE_OUTPUT: return nv50_ir::FILE_SHADER_OUTPUT;
402 case TGSI_FILE_TEMPORARY: return nv50_ir::FILE_GPR;
403 case TGSI_FILE_ADDRESS: return nv50_ir::FILE_ADDRESS;
404 case TGSI_FILE_PREDICATE: return nv50_ir::FILE_PREDICATE;
405 case TGSI_FILE_IMMEDIATE: return nv50_ir::FILE_IMMEDIATE;
406 case TGSI_FILE_SYSTEM_VALUE: return nv50_ir::FILE_SYSTEM_VALUE;
407 case TGSI_FILE_BUFFER: return nv50_ir::FILE_MEMORY_BUFFER;
408 case TGSI_FILE_IMAGE: return nv50_ir::FILE_MEMORY_GLOBAL;
409 case TGSI_FILE_MEMORY: return nv50_ir::FILE_MEMORY_GLOBAL;
410 case TGSI_FILE_SAMPLER:
411 case TGSI_FILE_NULL:
412 default:
413 return nv50_ir::FILE_NULL;
414 }
415 }
416
417 static nv50_ir::SVSemantic translateSysVal(uint sysval)
418 {
419 switch (sysval) {
420 case TGSI_SEMANTIC_FACE: return nv50_ir::SV_FACE;
421 case TGSI_SEMANTIC_PSIZE: return nv50_ir::SV_POINT_SIZE;
422 case TGSI_SEMANTIC_PRIMID: return nv50_ir::SV_PRIMITIVE_ID;
423 case TGSI_SEMANTIC_INSTANCEID: return nv50_ir::SV_INSTANCE_ID;
424 case TGSI_SEMANTIC_VERTEXID: return nv50_ir::SV_VERTEX_ID;
425 case TGSI_SEMANTIC_GRID_SIZE: return nv50_ir::SV_NCTAID;
426 case TGSI_SEMANTIC_BLOCK_ID: return nv50_ir::SV_CTAID;
427 case TGSI_SEMANTIC_BLOCK_SIZE: return nv50_ir::SV_NTID;
428 case TGSI_SEMANTIC_THREAD_ID: return nv50_ir::SV_TID;
429 case TGSI_SEMANTIC_SAMPLEID: return nv50_ir::SV_SAMPLE_INDEX;
430 case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
431 case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
432 case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
433 case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD;
434 case TGSI_SEMANTIC_TESSOUTER: return nv50_ir::SV_TESS_OUTER;
435 case TGSI_SEMANTIC_TESSINNER: return nv50_ir::SV_TESS_INNER;
436 case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
437 case TGSI_SEMANTIC_HELPER_INVOCATION: return nv50_ir::SV_THREAD_KILL;
438 case TGSI_SEMANTIC_BASEVERTEX: return nv50_ir::SV_BASEVERTEX;
439 case TGSI_SEMANTIC_BASEINSTANCE: return nv50_ir::SV_BASEINSTANCE;
440 case TGSI_SEMANTIC_DRAWID: return nv50_ir::SV_DRAWID;
441 case TGSI_SEMANTIC_WORK_DIM: return nv50_ir::SV_WORK_DIM;
442 default:
443 assert(0);
444 return nv50_ir::SV_CLOCK;
445 }
446 }
447
448 #define NV50_IR_TEX_TARG_CASE(a, b) \
449 case TGSI_TEXTURE_##a: return nv50_ir::TEX_TARGET_##b;
450
451 static nv50_ir::TexTarget translateTexture(uint tex)
452 {
453 switch (tex) {
454 NV50_IR_TEX_TARG_CASE(1D, 1D);
455 NV50_IR_TEX_TARG_CASE(2D, 2D);
456 NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
457 NV50_IR_TEX_TARG_CASE(3D, 3D);
458 NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
459 NV50_IR_TEX_TARG_CASE(RECT, RECT);
460 NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
461 NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
462 NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
463 NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
464 NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
465 NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
466 NV50_IR_TEX_TARG_CASE(SHADOWCUBE, CUBE_SHADOW);
467 NV50_IR_TEX_TARG_CASE(SHADOWRECT, RECT_SHADOW);
468 NV50_IR_TEX_TARG_CASE(SHADOW1D_ARRAY, 1D_ARRAY_SHADOW);
469 NV50_IR_TEX_TARG_CASE(SHADOW2D_ARRAY, 2D_ARRAY_SHADOW);
470 NV50_IR_TEX_TARG_CASE(SHADOWCUBE_ARRAY, CUBE_ARRAY_SHADOW);
471 NV50_IR_TEX_TARG_CASE(BUFFER, BUFFER);
472
473 case TGSI_TEXTURE_UNKNOWN:
474 default:
475 assert(!"invalid texture target");
476 return nv50_ir::TEX_TARGET_2D;
477 }
478 }
479
480 static nv50_ir::CacheMode translateCacheMode(uint qualifier)
481 {
482 if (qualifier & TGSI_MEMORY_VOLATILE)
483 return nv50_ir::CACHE_CV;
484 if (qualifier & TGSI_MEMORY_COHERENT)
485 return nv50_ir::CACHE_CG;
486 return nv50_ir::CACHE_CA;
487 }
488
489 static nv50_ir::ImgFormat translateImgFormat(uint format)
490 {
491
492 #define FMT_CASE(a, b) \
493 case PIPE_FORMAT_ ## a: return nv50_ir::FMT_ ## b
494
495 switch (format) {
496 FMT_CASE(NONE, NONE);
497
498 FMT_CASE(R32G32B32A32_FLOAT, RGBA32F);
499 FMT_CASE(R16G16B16A16_FLOAT, RGBA16F);
500 FMT_CASE(R32G32_FLOAT, RG32F);
501 FMT_CASE(R16G16_FLOAT, RG16F);
502 FMT_CASE(R11G11B10_FLOAT, R11G11B10F);
503 FMT_CASE(R32_FLOAT, R32F);
504 FMT_CASE(R16_FLOAT, R16F);
505
506 FMT_CASE(R32G32B32A32_UINT, RGBA32UI);
507 FMT_CASE(R16G16B16A16_UINT, RGBA16UI);
508 FMT_CASE(R10G10B10A2_UINT, RGB10A2UI);
509 FMT_CASE(R8G8B8A8_UINT, RGBA8UI);
510 FMT_CASE(R32G32_UINT, RG32UI);
511 FMT_CASE(R16G16_UINT, RG16UI);
512 FMT_CASE(R8G8_UINT, RG8UI);
513 FMT_CASE(R32_UINT, R32UI);
514 FMT_CASE(R16_UINT, R16UI);
515 FMT_CASE(R8_UINT, R8UI);
516
517 FMT_CASE(R32G32B32A32_SINT, RGBA32I);
518 FMT_CASE(R16G16B16A16_SINT, RGBA16I);
519 FMT_CASE(R8G8B8A8_SINT, RGBA8I);
520 FMT_CASE(R32G32_SINT, RG32I);
521 FMT_CASE(R16G16_SINT, RG16I);
522 FMT_CASE(R8G8_SINT, RG8I);
523 FMT_CASE(R32_SINT, R32I);
524 FMT_CASE(R16_SINT, R16I);
525 FMT_CASE(R8_SINT, R8I);
526
527 FMT_CASE(R16G16B16A16_UNORM, RGBA16);
528 FMT_CASE(R10G10B10A2_UNORM, RGB10A2);
529 FMT_CASE(R8G8B8A8_UNORM, RGBA8);
530 FMT_CASE(R16G16_UNORM, RG16);
531 FMT_CASE(R8G8_UNORM, RG8);
532 FMT_CASE(R16_UNORM, R16);
533 FMT_CASE(R8_UNORM, R8);
534
535 FMT_CASE(R16G16B16A16_SNORM, RGBA16_SNORM);
536 FMT_CASE(R8G8B8A8_SNORM, RGBA8_SNORM);
537 FMT_CASE(R16G16_SNORM, RG16_SNORM);
538 FMT_CASE(R8G8_SNORM, RG8_SNORM);
539 FMT_CASE(R16_SNORM, R16_SNORM);
540 FMT_CASE(R8_SNORM, R8_SNORM);
541
542 FMT_CASE(B8G8R8A8_UNORM, BGRA8);
543 }
544
545 assert(!"Unexpected format");
546 return nv50_ir::FMT_NONE;
547 }
548
549 nv50_ir::DataType Instruction::inferSrcType() const
550 {
551 switch (getOpcode()) {
552 case TGSI_OPCODE_UIF:
553 case TGSI_OPCODE_AND:
554 case TGSI_OPCODE_OR:
555 case TGSI_OPCODE_XOR:
556 case TGSI_OPCODE_NOT:
557 case TGSI_OPCODE_SHL:
558 case TGSI_OPCODE_U2F:
559 case TGSI_OPCODE_U2D:
560 case TGSI_OPCODE_UADD:
561 case TGSI_OPCODE_UDIV:
562 case TGSI_OPCODE_UMOD:
563 case TGSI_OPCODE_UMAD:
564 case TGSI_OPCODE_UMUL:
565 case TGSI_OPCODE_UMUL_HI:
566 case TGSI_OPCODE_UMAX:
567 case TGSI_OPCODE_UMIN:
568 case TGSI_OPCODE_USEQ:
569 case TGSI_OPCODE_USGE:
570 case TGSI_OPCODE_USLT:
571 case TGSI_OPCODE_USNE:
572 case TGSI_OPCODE_USHR:
573 case TGSI_OPCODE_ATOMUADD:
574 case TGSI_OPCODE_ATOMXCHG:
575 case TGSI_OPCODE_ATOMCAS:
576 case TGSI_OPCODE_ATOMAND:
577 case TGSI_OPCODE_ATOMOR:
578 case TGSI_OPCODE_ATOMXOR:
579 case TGSI_OPCODE_ATOMUMIN:
580 case TGSI_OPCODE_ATOMUMAX:
581 case TGSI_OPCODE_UBFE:
582 case TGSI_OPCODE_UMSB:
583 case TGSI_OPCODE_UP2H:
584 case TGSI_OPCODE_VOTE_ALL:
585 case TGSI_OPCODE_VOTE_ANY:
586 case TGSI_OPCODE_VOTE_EQ:
587 return nv50_ir::TYPE_U32;
588 case TGSI_OPCODE_I2F:
589 case TGSI_OPCODE_I2D:
590 case TGSI_OPCODE_IDIV:
591 case TGSI_OPCODE_IMUL_HI:
592 case TGSI_OPCODE_IMAX:
593 case TGSI_OPCODE_IMIN:
594 case TGSI_OPCODE_IABS:
595 case TGSI_OPCODE_INEG:
596 case TGSI_OPCODE_ISGE:
597 case TGSI_OPCODE_ISHR:
598 case TGSI_OPCODE_ISLT:
599 case TGSI_OPCODE_ISSG:
600 case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version
601 case TGSI_OPCODE_MOD:
602 case TGSI_OPCODE_UARL:
603 case TGSI_OPCODE_ATOMIMIN:
604 case TGSI_OPCODE_ATOMIMAX:
605 case TGSI_OPCODE_IBFE:
606 case TGSI_OPCODE_IMSB:
607 return nv50_ir::TYPE_S32;
608 case TGSI_OPCODE_D2F:
609 case TGSI_OPCODE_D2I:
610 case TGSI_OPCODE_D2U:
611 case TGSI_OPCODE_DABS:
612 case TGSI_OPCODE_DNEG:
613 case TGSI_OPCODE_DADD:
614 case TGSI_OPCODE_DMUL:
615 case TGSI_OPCODE_DMAX:
616 case TGSI_OPCODE_DMIN:
617 case TGSI_OPCODE_DSLT:
618 case TGSI_OPCODE_DSGE:
619 case TGSI_OPCODE_DSEQ:
620 case TGSI_OPCODE_DSNE:
621 case TGSI_OPCODE_DRCP:
622 case TGSI_OPCODE_DSQRT:
623 case TGSI_OPCODE_DMAD:
624 case TGSI_OPCODE_DFMA:
625 case TGSI_OPCODE_DFRAC:
626 case TGSI_OPCODE_DRSQ:
627 case TGSI_OPCODE_DTRUNC:
628 case TGSI_OPCODE_DCEIL:
629 case TGSI_OPCODE_DFLR:
630 case TGSI_OPCODE_DROUND:
631 return nv50_ir::TYPE_F64;
632 default:
633 return nv50_ir::TYPE_F32;
634 }
635 }
636
637 nv50_ir::DataType Instruction::inferDstType() const
638 {
639 switch (getOpcode()) {
640 case TGSI_OPCODE_D2U:
641 case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
642 case TGSI_OPCODE_D2I:
643 case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
644 case TGSI_OPCODE_FSEQ:
645 case TGSI_OPCODE_FSGE:
646 case TGSI_OPCODE_FSLT:
647 case TGSI_OPCODE_FSNE:
648 case TGSI_OPCODE_DSEQ:
649 case TGSI_OPCODE_DSGE:
650 case TGSI_OPCODE_DSLT:
651 case TGSI_OPCODE_DSNE:
652 case TGSI_OPCODE_PK2H:
653 return nv50_ir::TYPE_U32;
654 case TGSI_OPCODE_I2F:
655 case TGSI_OPCODE_U2F:
656 case TGSI_OPCODE_D2F:
657 case TGSI_OPCODE_UP2H:
658 return nv50_ir::TYPE_F32;
659 case TGSI_OPCODE_I2D:
660 case TGSI_OPCODE_U2D:
661 case TGSI_OPCODE_F2D:
662 return nv50_ir::TYPE_F64;
663 default:
664 return inferSrcType();
665 }
666 }
667
668 nv50_ir::CondCode Instruction::getSetCond() const
669 {
670 using namespace nv50_ir;
671
672 switch (getOpcode()) {
673 case TGSI_OPCODE_SLT:
674 case TGSI_OPCODE_ISLT:
675 case TGSI_OPCODE_USLT:
676 case TGSI_OPCODE_FSLT:
677 case TGSI_OPCODE_DSLT:
678 return CC_LT;
679 case TGSI_OPCODE_SLE:
680 return CC_LE;
681 case TGSI_OPCODE_SGE:
682 case TGSI_OPCODE_ISGE:
683 case TGSI_OPCODE_USGE:
684 case TGSI_OPCODE_FSGE:
685 case TGSI_OPCODE_DSGE:
686 return CC_GE;
687 case TGSI_OPCODE_SGT:
688 return CC_GT;
689 case TGSI_OPCODE_SEQ:
690 case TGSI_OPCODE_USEQ:
691 case TGSI_OPCODE_FSEQ:
692 case TGSI_OPCODE_DSEQ:
693 return CC_EQ;
694 case TGSI_OPCODE_SNE:
695 case TGSI_OPCODE_FSNE:
696 case TGSI_OPCODE_DSNE:
697 return CC_NEU;
698 case TGSI_OPCODE_USNE:
699 return CC_NE;
700 default:
701 return CC_ALWAYS;
702 }
703 }
704
705 #define NV50_IR_OPCODE_CASE(a, b) case TGSI_OPCODE_##a: return nv50_ir::OP_##b
706
707 static nv50_ir::operation translateOpcode(uint opcode)
708 {
709 switch (opcode) {
710 NV50_IR_OPCODE_CASE(ARL, SHL);
711 NV50_IR_OPCODE_CASE(MOV, MOV);
712
713 NV50_IR_OPCODE_CASE(RCP, RCP);
714 NV50_IR_OPCODE_CASE(RSQ, RSQ);
715 NV50_IR_OPCODE_CASE(SQRT, SQRT);
716
717 NV50_IR_OPCODE_CASE(MUL, MUL);
718 NV50_IR_OPCODE_CASE(ADD, ADD);
719
720 NV50_IR_OPCODE_CASE(MIN, MIN);
721 NV50_IR_OPCODE_CASE(MAX, MAX);
722 NV50_IR_OPCODE_CASE(SLT, SET);
723 NV50_IR_OPCODE_CASE(SGE, SET);
724 NV50_IR_OPCODE_CASE(MAD, MAD);
725 NV50_IR_OPCODE_CASE(FMA, FMA);
726 NV50_IR_OPCODE_CASE(SUB, SUB);
727
728 NV50_IR_OPCODE_CASE(FLR, FLOOR);
729 NV50_IR_OPCODE_CASE(ROUND, CVT);
730 NV50_IR_OPCODE_CASE(EX2, EX2);
731 NV50_IR_OPCODE_CASE(LG2, LG2);
732 NV50_IR_OPCODE_CASE(POW, POW);
733
734 NV50_IR_OPCODE_CASE(ABS, ABS);
735
736 NV50_IR_OPCODE_CASE(COS, COS);
737 NV50_IR_OPCODE_CASE(DDX, DFDX);
738 NV50_IR_OPCODE_CASE(DDX_FINE, DFDX);
739 NV50_IR_OPCODE_CASE(DDY, DFDY);
740 NV50_IR_OPCODE_CASE(DDY_FINE, DFDY);
741 NV50_IR_OPCODE_CASE(KILL, DISCARD);
742
743 NV50_IR_OPCODE_CASE(SEQ, SET);
744 NV50_IR_OPCODE_CASE(SGT, SET);
745 NV50_IR_OPCODE_CASE(SIN, SIN);
746 NV50_IR_OPCODE_CASE(SLE, SET);
747 NV50_IR_OPCODE_CASE(SNE, SET);
748 NV50_IR_OPCODE_CASE(TEX, TEX);
749 NV50_IR_OPCODE_CASE(TXD, TXD);
750 NV50_IR_OPCODE_CASE(TXP, TEX);
751
752 NV50_IR_OPCODE_CASE(CAL, CALL);
753 NV50_IR_OPCODE_CASE(RET, RET);
754 NV50_IR_OPCODE_CASE(CMP, SLCT);
755
756 NV50_IR_OPCODE_CASE(TXB, TXB);
757
758 NV50_IR_OPCODE_CASE(DIV, DIV);
759
760 NV50_IR_OPCODE_CASE(TXL, TXL);
761
762 NV50_IR_OPCODE_CASE(CEIL, CEIL);
763 NV50_IR_OPCODE_CASE(I2F, CVT);
764 NV50_IR_OPCODE_CASE(NOT, NOT);
765 NV50_IR_OPCODE_CASE(TRUNC, TRUNC);
766 NV50_IR_OPCODE_CASE(SHL, SHL);
767
768 NV50_IR_OPCODE_CASE(AND, AND);
769 NV50_IR_OPCODE_CASE(OR, OR);
770 NV50_IR_OPCODE_CASE(MOD, MOD);
771 NV50_IR_OPCODE_CASE(XOR, XOR);
772 NV50_IR_OPCODE_CASE(SAD, SAD);
773 NV50_IR_OPCODE_CASE(TXF, TXF);
774 NV50_IR_OPCODE_CASE(TXQ, TXQ);
775 NV50_IR_OPCODE_CASE(TXQS, TXQ);
776 NV50_IR_OPCODE_CASE(TG4, TXG);
777 NV50_IR_OPCODE_CASE(LODQ, TXLQ);
778
779 NV50_IR_OPCODE_CASE(EMIT, EMIT);
780 NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
781
782 NV50_IR_OPCODE_CASE(KILL_IF, DISCARD);
783
784 NV50_IR_OPCODE_CASE(F2I, CVT);
785 NV50_IR_OPCODE_CASE(FSEQ, SET);
786 NV50_IR_OPCODE_CASE(FSGE, SET);
787 NV50_IR_OPCODE_CASE(FSLT, SET);
788 NV50_IR_OPCODE_CASE(FSNE, SET);
789 NV50_IR_OPCODE_CASE(IDIV, DIV);
790 NV50_IR_OPCODE_CASE(IMAX, MAX);
791 NV50_IR_OPCODE_CASE(IMIN, MIN);
792 NV50_IR_OPCODE_CASE(IABS, ABS);
793 NV50_IR_OPCODE_CASE(INEG, NEG);
794 NV50_IR_OPCODE_CASE(ISGE, SET);
795 NV50_IR_OPCODE_CASE(ISHR, SHR);
796 NV50_IR_OPCODE_CASE(ISLT, SET);
797 NV50_IR_OPCODE_CASE(F2U, CVT);
798 NV50_IR_OPCODE_CASE(U2F, CVT);
799 NV50_IR_OPCODE_CASE(UADD, ADD);
800 NV50_IR_OPCODE_CASE(UDIV, DIV);
801 NV50_IR_OPCODE_CASE(UMAD, MAD);
802 NV50_IR_OPCODE_CASE(UMAX, MAX);
803 NV50_IR_OPCODE_CASE(UMIN, MIN);
804 NV50_IR_OPCODE_CASE(UMOD, MOD);
805 NV50_IR_OPCODE_CASE(UMUL, MUL);
806 NV50_IR_OPCODE_CASE(USEQ, SET);
807 NV50_IR_OPCODE_CASE(USGE, SET);
808 NV50_IR_OPCODE_CASE(USHR, SHR);
809 NV50_IR_OPCODE_CASE(USLT, SET);
810 NV50_IR_OPCODE_CASE(USNE, SET);
811
812 NV50_IR_OPCODE_CASE(DABS, ABS);
813 NV50_IR_OPCODE_CASE(DNEG, NEG);
814 NV50_IR_OPCODE_CASE(DADD, ADD);
815 NV50_IR_OPCODE_CASE(DMUL, MUL);
816 NV50_IR_OPCODE_CASE(DMAX, MAX);
817 NV50_IR_OPCODE_CASE(DMIN, MIN);
818 NV50_IR_OPCODE_CASE(DSLT, SET);
819 NV50_IR_OPCODE_CASE(DSGE, SET);
820 NV50_IR_OPCODE_CASE(DSEQ, SET);
821 NV50_IR_OPCODE_CASE(DSNE, SET);
822 NV50_IR_OPCODE_CASE(DRCP, RCP);
823 NV50_IR_OPCODE_CASE(DSQRT, SQRT);
824 NV50_IR_OPCODE_CASE(DMAD, MAD);
825 NV50_IR_OPCODE_CASE(DFMA, FMA);
826 NV50_IR_OPCODE_CASE(D2I, CVT);
827 NV50_IR_OPCODE_CASE(D2U, CVT);
828 NV50_IR_OPCODE_CASE(I2D, CVT);
829 NV50_IR_OPCODE_CASE(U2D, CVT);
830 NV50_IR_OPCODE_CASE(DRSQ, RSQ);
831 NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
832 NV50_IR_OPCODE_CASE(DCEIL, CEIL);
833 NV50_IR_OPCODE_CASE(DFLR, FLOOR);
834 NV50_IR_OPCODE_CASE(DROUND, CVT);
835
836 NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
837 NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
838
839 NV50_IR_OPCODE_CASE(SAMPLE, TEX);
840 NV50_IR_OPCODE_CASE(SAMPLE_B, TXB);
841 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX);
842 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
843 NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
844 NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
845 NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
846 NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
847 NV50_IR_OPCODE_CASE(GATHER4, TXG);
848 NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
849
850 NV50_IR_OPCODE_CASE(ATOMUADD, ATOM);
851 NV50_IR_OPCODE_CASE(ATOMXCHG, ATOM);
852 NV50_IR_OPCODE_CASE(ATOMCAS, ATOM);
853 NV50_IR_OPCODE_CASE(ATOMAND, ATOM);
854 NV50_IR_OPCODE_CASE(ATOMOR, ATOM);
855 NV50_IR_OPCODE_CASE(ATOMXOR, ATOM);
856 NV50_IR_OPCODE_CASE(ATOMUMIN, ATOM);
857 NV50_IR_OPCODE_CASE(ATOMUMAX, ATOM);
858 NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM);
859 NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM);
860
861 NV50_IR_OPCODE_CASE(TEX2, TEX);
862 NV50_IR_OPCODE_CASE(TXB2, TXB);
863 NV50_IR_OPCODE_CASE(TXL2, TXL);
864
865 NV50_IR_OPCODE_CASE(IBFE, EXTBF);
866 NV50_IR_OPCODE_CASE(UBFE, EXTBF);
867 NV50_IR_OPCODE_CASE(BFI, INSBF);
868 NV50_IR_OPCODE_CASE(BREV, EXTBF);
869 NV50_IR_OPCODE_CASE(POPC, POPCNT);
870 NV50_IR_OPCODE_CASE(LSB, BFIND);
871 NV50_IR_OPCODE_CASE(IMSB, BFIND);
872 NV50_IR_OPCODE_CASE(UMSB, BFIND);
873
874 NV50_IR_OPCODE_CASE(VOTE_ALL, VOTE);
875 NV50_IR_OPCODE_CASE(VOTE_ANY, VOTE);
876 NV50_IR_OPCODE_CASE(VOTE_EQ, VOTE);
877
878 NV50_IR_OPCODE_CASE(END, EXIT);
879
880 default:
881 return nv50_ir::OP_NOP;
882 }
883 }
884
885 static uint16_t opcodeToSubOp(uint opcode)
886 {
887 switch (opcode) {
888 case TGSI_OPCODE_LFENCE: return NV50_IR_SUBOP_MEMBAR(L, GL);
889 case TGSI_OPCODE_SFENCE: return NV50_IR_SUBOP_MEMBAR(S, GL);
890 case TGSI_OPCODE_MFENCE: return NV50_IR_SUBOP_MEMBAR(M, GL);
891 case TGSI_OPCODE_ATOMUADD: return NV50_IR_SUBOP_ATOM_ADD;
892 case TGSI_OPCODE_ATOMXCHG: return NV50_IR_SUBOP_ATOM_EXCH;
893 case TGSI_OPCODE_ATOMCAS: return NV50_IR_SUBOP_ATOM_CAS;
894 case TGSI_OPCODE_ATOMAND: return NV50_IR_SUBOP_ATOM_AND;
895 case TGSI_OPCODE_ATOMOR: return NV50_IR_SUBOP_ATOM_OR;
896 case TGSI_OPCODE_ATOMXOR: return NV50_IR_SUBOP_ATOM_XOR;
897 case TGSI_OPCODE_ATOMUMIN: return NV50_IR_SUBOP_ATOM_MIN;
898 case TGSI_OPCODE_ATOMIMIN: return NV50_IR_SUBOP_ATOM_MIN;
899 case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX;
900 case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX;
901 case TGSI_OPCODE_IMUL_HI:
902 case TGSI_OPCODE_UMUL_HI:
903 return NV50_IR_SUBOP_MUL_HIGH;
904 case TGSI_OPCODE_VOTE_ALL: return NV50_IR_SUBOP_VOTE_ALL;
905 case TGSI_OPCODE_VOTE_ANY: return NV50_IR_SUBOP_VOTE_ANY;
906 case TGSI_OPCODE_VOTE_EQ: return NV50_IR_SUBOP_VOTE_UNI;
907 default:
908 return 0;
909 }
910 }
911
912 bool Instruction::checkDstSrcAliasing() const
913 {
914 if (insn->Dst[0].Register.Indirect) // no danger if indirect, using memory
915 return false;
916
917 for (int s = 0; s < TGSI_FULL_MAX_SRC_REGISTERS; ++s) {
918 if (insn->Src[s].Register.File == TGSI_FILE_NULL)
919 break;
920 if (insn->Src[s].Register.File == insn->Dst[0].Register.File &&
921 insn->Src[s].Register.Index == insn->Dst[0].Register.Index)
922 return true;
923 }
924 return false;
925 }
926
927 class Source
928 {
929 public:
930 Source(struct nv50_ir_prog_info *);
931 ~Source();
932
933 public:
934 bool scanSource();
935 unsigned fileSize(unsigned file) const { return scan.file_max[file] + 1; }
936
937 public:
938 struct tgsi_shader_info scan;
939 struct tgsi_full_instruction *insns;
940 const struct tgsi_token *tokens;
941 struct nv50_ir_prog_info *info;
942
943 nv50_ir::DynArray tempArrays;
944 nv50_ir::DynArray immdArrays;
945
946 typedef nv50_ir::BuildUtil::Location Location;
947 // these registers are per-subroutine, cannot be used for parameter passing
948 std::set<Location> locals;
949
950 std::set<int> indirectTempArrays;
951 std::map<int, int> indirectTempOffsets;
952 std::map<int, std::pair<int, int> > tempArrayInfo;
953 std::vector<int> tempArrayId;
954
955 int clipVertexOutput;
956
957 struct TextureView {
958 uint8_t target; // TGSI_TEXTURE_*
959 };
960 std::vector<TextureView> textureViews;
961
962 /*
963 struct Resource {
964 uint8_t target; // TGSI_TEXTURE_*
965 bool raw;
966 uint8_t slot; // $surface index
967 };
968 std::vector<Resource> resources;
969 */
970
971 struct Image {
972 uint8_t target; // TGSI_TEXTURE_*
973 bool raw;
974 uint8_t slot;
975 uint16_t format; // PIPE_FORMAT_*
976 };
977 std::vector<Image> images;
978
979 struct MemoryFile {
980 uint8_t mem_type; // TGSI_MEMORY_TYPE_*
981 };
982 std::vector<MemoryFile> memoryFiles;
983
984 private:
985 int inferSysValDirection(unsigned sn) const;
986 bool scanDeclaration(const struct tgsi_full_declaration *);
987 bool scanInstruction(const struct tgsi_full_instruction *);
988 void scanInstructionSrc(const Instruction& insn,
989 const Instruction::SrcRegister& src,
990 unsigned mask);
991 void scanProperty(const struct tgsi_full_property *);
992 void scanImmediate(const struct tgsi_full_immediate *);
993
994 inline bool isEdgeFlagPassthrough(const Instruction&) const;
995 };
996
997 Source::Source(struct nv50_ir_prog_info *prog) : info(prog)
998 {
999 tokens = (const struct tgsi_token *)info->bin.source;
1000
1001 if (prog->dbgFlags & NV50_IR_DEBUG_BASIC)
1002 tgsi_dump(tokens, 0);
1003 }
1004
1005 Source::~Source()
1006 {
1007 if (insns)
1008 FREE(insns);
1009
1010 if (info->immd.data)
1011 FREE(info->immd.data);
1012 if (info->immd.type)
1013 FREE(info->immd.type);
1014 }
1015
1016 bool Source::scanSource()
1017 {
1018 unsigned insnCount = 0;
1019 struct tgsi_parse_context parse;
1020
1021 tgsi_scan_shader(tokens, &scan);
1022
1023 insns = (struct tgsi_full_instruction *)MALLOC(scan.num_instructions *
1024 sizeof(insns[0]));
1025 if (!insns)
1026 return false;
1027
1028 clipVertexOutput = -1;
1029
1030 textureViews.resize(scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1);
1031 //resources.resize(scan.file_max[TGSI_FILE_RESOURCE] + 1);
1032 images.resize(scan.file_max[TGSI_FILE_IMAGE] + 1);
1033 tempArrayId.resize(scan.file_max[TGSI_FILE_TEMPORARY] + 1);
1034 memoryFiles.resize(scan.file_max[TGSI_FILE_MEMORY] + 1);
1035
1036 info->immd.bufSize = 0;
1037
1038 info->numInputs = scan.file_max[TGSI_FILE_INPUT] + 1;
1039 info->numOutputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
1040 info->numSysVals = scan.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
1041
1042 if (info->type == PIPE_SHADER_FRAGMENT) {
1043 info->prop.fp.writesDepth = scan.writes_z;
1044 info->prop.fp.usesDiscard = scan.uses_kill || info->io.alphaRefBase;
1045 } else
1046 if (info->type == PIPE_SHADER_GEOMETRY) {
1047 info->prop.gp.instanceCount = 1; // default value
1048 }
1049
1050 info->io.viewportId = -1;
1051 info->prop.cp.numThreads = 1;
1052
1053 info->immd.data = (uint32_t *)MALLOC(scan.immediate_count * 16);
1054 info->immd.type = (ubyte *)MALLOC(scan.immediate_count * sizeof(ubyte));
1055
1056 tgsi_parse_init(&parse, tokens);
1057 while (!tgsi_parse_end_of_tokens(&parse)) {
1058 tgsi_parse_token(&parse);
1059
1060 switch (parse.FullToken.Token.Type) {
1061 case TGSI_TOKEN_TYPE_IMMEDIATE:
1062 scanImmediate(&parse.FullToken.FullImmediate);
1063 break;
1064 case TGSI_TOKEN_TYPE_DECLARATION:
1065 scanDeclaration(&parse.FullToken.FullDeclaration);
1066 break;
1067 case TGSI_TOKEN_TYPE_INSTRUCTION:
1068 insns[insnCount++] = parse.FullToken.FullInstruction;
1069 scanInstruction(&parse.FullToken.FullInstruction);
1070 break;
1071 case TGSI_TOKEN_TYPE_PROPERTY:
1072 scanProperty(&parse.FullToken.FullProperty);
1073 break;
1074 default:
1075 INFO("unknown TGSI token type: %d\n", parse.FullToken.Token.Type);
1076 break;
1077 }
1078 }
1079 tgsi_parse_free(&parse);
1080
1081 if (indirectTempArrays.size()) {
1082 int tempBase = 0;
1083 for (std::set<int>::const_iterator it = indirectTempArrays.begin();
1084 it != indirectTempArrays.end(); ++it) {
1085 std::pair<int, int>& info = tempArrayInfo[*it];
1086 indirectTempOffsets.insert(std::make_pair(*it, tempBase - info.first));
1087 tempBase += info.second;
1088 }
1089 info->bin.tlsSpace += tempBase * 16;
1090 }
1091
1092 if (info->io.genUserClip > 0) {
1093 info->io.clipDistances = info->io.genUserClip;
1094
1095 const unsigned int nOut = (info->io.genUserClip + 3) / 4;
1096
1097 for (unsigned int n = 0; n < nOut; ++n) {
1098 unsigned int i = info->numOutputs++;
1099 info->out[i].id = i;
1100 info->out[i].sn = TGSI_SEMANTIC_CLIPDIST;
1101 info->out[i].si = n;
1102 info->out[i].mask = ((1 << info->io.clipDistances) - 1) >> (n * 4);
1103 }
1104 }
1105
1106 return info->assignSlots(info) == 0;
1107 }
1108
1109 void Source::scanProperty(const struct tgsi_full_property *prop)
1110 {
1111 switch (prop->Property.PropertyName) {
1112 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1113 info->prop.gp.outputPrim = prop->u[0].Data;
1114 break;
1115 case TGSI_PROPERTY_GS_INPUT_PRIM:
1116 info->prop.gp.inputPrim = prop->u[0].Data;
1117 break;
1118 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1119 info->prop.gp.maxVertices = prop->u[0].Data;
1120 break;
1121 case TGSI_PROPERTY_GS_INVOCATIONS:
1122 info->prop.gp.instanceCount = prop->u[0].Data;
1123 break;
1124 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1125 info->prop.fp.separateFragData = true;
1126 break;
1127 case TGSI_PROPERTY_FS_COORD_ORIGIN:
1128 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
1129 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
1130 // we don't care
1131 break;
1132 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1133 info->io.genUserClip = -1;
1134 break;
1135 case TGSI_PROPERTY_TCS_VERTICES_OUT:
1136 info->prop.tp.outputPatchSize = prop->u[0].Data;
1137 break;
1138 case TGSI_PROPERTY_TES_PRIM_MODE:
1139 info->prop.tp.domain = prop->u[0].Data;
1140 break;
1141 case TGSI_PROPERTY_TES_SPACING:
1142 info->prop.tp.partitioning = prop->u[0].Data;
1143 break;
1144 case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
1145 info->prop.tp.winding = prop->u[0].Data;
1146 break;
1147 case TGSI_PROPERTY_TES_POINT_MODE:
1148 if (prop->u[0].Data)
1149 info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
1150 else
1151 info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
1152 break;
1153 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
1154 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
1155 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
1156 info->prop.cp.numThreads *= prop->u[0].Data;
1157 break;
1158 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
1159 info->io.clipDistances = prop->u[0].Data;
1160 break;
1161 case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
1162 info->io.cullDistances = prop->u[0].Data;
1163 break;
1164 case TGSI_PROPERTY_NEXT_SHADER:
1165 /* Do not need to know the next shader stage. */
1166 break;
1167 case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
1168 info->prop.fp.earlyFragTests = prop->u[0].Data;
1169 break;
1170 default:
1171 INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
1172 break;
1173 }
1174 }
1175
1176 void Source::scanImmediate(const struct tgsi_full_immediate *imm)
1177 {
1178 const unsigned n = info->immd.count++;
1179
1180 assert(n < scan.immediate_count);
1181
1182 for (int c = 0; c < 4; ++c)
1183 info->immd.data[n * 4 + c] = imm->u[c].Uint;
1184
1185 info->immd.type[n] = imm->Immediate.DataType;
1186 }
1187
1188 int Source::inferSysValDirection(unsigned sn) const
1189 {
1190 switch (sn) {
1191 case TGSI_SEMANTIC_INSTANCEID:
1192 case TGSI_SEMANTIC_VERTEXID:
1193 return 1;
1194 case TGSI_SEMANTIC_LAYER:
1195 #if 0
1196 case TGSI_SEMANTIC_VIEWPORTINDEX:
1197 return 0;
1198 #endif
1199 case TGSI_SEMANTIC_PRIMID:
1200 return (info->type == PIPE_SHADER_FRAGMENT) ? 1 : 0;
1201 default:
1202 return 0;
1203 }
1204 }
1205
1206 bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
1207 {
1208 unsigned i, c;
1209 unsigned sn = TGSI_SEMANTIC_GENERIC;
1210 unsigned si = 0;
1211 const unsigned first = decl->Range.First, last = decl->Range.Last;
1212 const int arrayId = decl->Array.ArrayID;
1213
1214 if (decl->Declaration.Semantic) {
1215 sn = decl->Semantic.Name;
1216 si = decl->Semantic.Index;
1217 }
1218
1219 if (decl->Declaration.Local || decl->Declaration.File == TGSI_FILE_ADDRESS) {
1220 for (i = first; i <= last; ++i) {
1221 for (c = 0; c < 4; ++c) {
1222 locals.insert(
1223 Location(decl->Declaration.File, decl->Dim.Index2D, i, c));
1224 }
1225 }
1226 }
1227
1228 switch (decl->Declaration.File) {
1229 case TGSI_FILE_INPUT:
1230 if (info->type == PIPE_SHADER_VERTEX) {
1231 // all vertex attributes are equal
1232 for (i = first; i <= last; ++i) {
1233 info->in[i].sn = TGSI_SEMANTIC_GENERIC;
1234 info->in[i].si = i;
1235 }
1236 } else {
1237 for (i = first; i <= last; ++i, ++si) {
1238 info->in[i].id = i;
1239 info->in[i].sn = sn;
1240 info->in[i].si = si;
1241 if (info->type == PIPE_SHADER_FRAGMENT) {
1242 // translate interpolation mode
1243 switch (decl->Interp.Interpolate) {
1244 case TGSI_INTERPOLATE_CONSTANT:
1245 info->in[i].flat = 1;
1246 break;
1247 case TGSI_INTERPOLATE_COLOR:
1248 info->in[i].sc = 1;
1249 break;
1250 case TGSI_INTERPOLATE_LINEAR:
1251 info->in[i].linear = 1;
1252 break;
1253 default:
1254 break;
1255 }
1256 if (decl->Interp.Location)
1257 info->in[i].centroid = 1;
1258 }
1259
1260 if (sn == TGSI_SEMANTIC_PATCH)
1261 info->in[i].patch = 1;
1262 if (sn == TGSI_SEMANTIC_PATCH)
1263 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1264 }
1265 }
1266 break;
1267 case TGSI_FILE_OUTPUT:
1268 for (i = first; i <= last; ++i, ++si) {
1269 switch (sn) {
1270 case TGSI_SEMANTIC_POSITION:
1271 if (info->type == PIPE_SHADER_FRAGMENT)
1272 info->io.fragDepth = i;
1273 else
1274 if (clipVertexOutput < 0)
1275 clipVertexOutput = i;
1276 break;
1277 case TGSI_SEMANTIC_COLOR:
1278 if (info->type == PIPE_SHADER_FRAGMENT)
1279 info->prop.fp.numColourResults++;
1280 break;
1281 case TGSI_SEMANTIC_EDGEFLAG:
1282 info->io.edgeFlagOut = i;
1283 break;
1284 case TGSI_SEMANTIC_CLIPVERTEX:
1285 clipVertexOutput = i;
1286 break;
1287 case TGSI_SEMANTIC_CLIPDIST:
1288 info->io.genUserClip = -1;
1289 break;
1290 case TGSI_SEMANTIC_SAMPLEMASK:
1291 info->io.sampleMask = i;
1292 break;
1293 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1294 info->io.viewportId = i;
1295 break;
1296 case TGSI_SEMANTIC_PATCH:
1297 info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
1298 /* fallthrough */
1299 case TGSI_SEMANTIC_TESSOUTER:
1300 case TGSI_SEMANTIC_TESSINNER:
1301 info->out[i].patch = 1;
1302 break;
1303 default:
1304 break;
1305 }
1306 info->out[i].id = i;
1307 info->out[i].sn = sn;
1308 info->out[i].si = si;
1309 }
1310 break;
1311 case TGSI_FILE_SYSTEM_VALUE:
1312 switch (sn) {
1313 case TGSI_SEMANTIC_INSTANCEID:
1314 info->io.instanceId = first;
1315 break;
1316 case TGSI_SEMANTIC_VERTEXID:
1317 info->io.vertexId = first;
1318 break;
1319 case TGSI_SEMANTIC_BASEVERTEX:
1320 case TGSI_SEMANTIC_BASEINSTANCE:
1321 case TGSI_SEMANTIC_DRAWID:
1322 info->prop.vp.usesDrawParameters = true;
1323 break;
1324 case TGSI_SEMANTIC_SAMPLEID:
1325 case TGSI_SEMANTIC_SAMPLEPOS:
1326 info->prop.fp.persampleInvocation = true;
1327 break;
1328 case TGSI_SEMANTIC_SAMPLEMASK:
1329 info->prop.fp.usesSampleMaskIn = true;
1330 break;
1331 default:
1332 break;
1333 }
1334 for (i = first; i <= last; ++i, ++si) {
1335 info->sv[i].sn = sn;
1336 info->sv[i].si = si;
1337 info->sv[i].input = inferSysValDirection(sn);
1338
1339 switch (sn) {
1340 case TGSI_SEMANTIC_TESSOUTER:
1341 case TGSI_SEMANTIC_TESSINNER:
1342 info->sv[i].patch = 1;
1343 break;
1344 }
1345 }
1346 break;
1347 /*
1348 case TGSI_FILE_RESOURCE:
1349 for (i = first; i <= last; ++i) {
1350 resources[i].target = decl->Resource.Resource;
1351 resources[i].raw = decl->Resource.Raw;
1352 resources[i].slot = i;
1353 }
1354 break;
1355 */
1356 case TGSI_FILE_IMAGE:
1357 for (i = first; i <= last; ++i) {
1358 images[i].target = decl->Image.Resource;
1359 images[i].raw = decl->Image.Raw;
1360 images[i].format = decl->Image.Format;
1361 images[i].slot = i;
1362 }
1363 break;
1364 case TGSI_FILE_SAMPLER_VIEW:
1365 for (i = first; i <= last; ++i)
1366 textureViews[i].target = decl->SamplerView.Resource;
1367 break;
1368 case TGSI_FILE_MEMORY:
1369 for (i = first; i <= last; ++i)
1370 memoryFiles[i].mem_type = decl->Declaration.MemType;
1371 break;
1372 case TGSI_FILE_NULL:
1373 case TGSI_FILE_TEMPORARY:
1374 for (i = first; i <= last; ++i)
1375 tempArrayId[i] = arrayId;
1376 if (arrayId)
1377 tempArrayInfo.insert(std::make_pair(arrayId, std::make_pair(
1378 first, last - first + 1)));
1379 break;
1380 case TGSI_FILE_ADDRESS:
1381 case TGSI_FILE_CONSTANT:
1382 case TGSI_FILE_IMMEDIATE:
1383 case TGSI_FILE_PREDICATE:
1384 case TGSI_FILE_SAMPLER:
1385 case TGSI_FILE_BUFFER:
1386 break;
1387 default:
1388 ERROR("unhandled TGSI_FILE %d\n", decl->Declaration.File);
1389 return false;
1390 }
1391 return true;
1392 }
1393
1394 inline bool Source::isEdgeFlagPassthrough(const Instruction& insn) const
1395 {
1396 return insn.getOpcode() == TGSI_OPCODE_MOV &&
1397 insn.getDst(0).getIndex(0) == info->io.edgeFlagOut &&
1398 insn.getSrc(0).getFile() == TGSI_FILE_INPUT;
1399 }
1400
1401 void Source::scanInstructionSrc(const Instruction& insn,
1402 const Instruction::SrcRegister& src,
1403 unsigned mask)
1404 {
1405 if (src.getFile() == TGSI_FILE_TEMPORARY) {
1406 if (src.isIndirect(0))
1407 indirectTempArrays.insert(src.getArrayId());
1408 } else
1409 if (src.getFile() == TGSI_FILE_BUFFER ||
1410 src.getFile() == TGSI_FILE_IMAGE ||
1411 (src.getFile() == TGSI_FILE_MEMORY &&
1412 memoryFiles[src.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1413 info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
1414 0x1 : 0x2;
1415 } else
1416 if (src.getFile() == TGSI_FILE_OUTPUT) {
1417 if (src.isIndirect(0)) {
1418 // We don't know which one is accessed, just mark everything for
1419 // reading. This is an extremely unlikely occurrence.
1420 for (unsigned i = 0; i < info->numOutputs; ++i)
1421 info->out[i].oread = 1;
1422 } else {
1423 info->out[src.getIndex(0)].oread = 1;
1424 }
1425 }
1426 if (src.getFile() != TGSI_FILE_INPUT)
1427 return;
1428
1429 if (src.isIndirect(0)) {
1430 for (unsigned i = 0; i < info->numInputs; ++i)
1431 info->in[i].mask = 0xf;
1432 } else {
1433 const int i = src.getIndex(0);
1434 for (unsigned c = 0; c < 4; ++c) {
1435 if (!(mask & (1 << c)))
1436 continue;
1437 int k = src.getSwizzle(c);
1438 if (k <= TGSI_SWIZZLE_W)
1439 info->in[i].mask |= 1 << k;
1440 }
1441 switch (info->in[i].sn) {
1442 case TGSI_SEMANTIC_PSIZE:
1443 case TGSI_SEMANTIC_PRIMID:
1444 case TGSI_SEMANTIC_FOG:
1445 info->in[i].mask &= 0x1;
1446 break;
1447 case TGSI_SEMANTIC_PCOORD:
1448 info->in[i].mask &= 0x3;
1449 break;
1450 default:
1451 break;
1452 }
1453 }
1454 }
1455
1456 bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
1457 {
1458 Instruction insn(inst);
1459
1460 if (insn.getOpcode() == TGSI_OPCODE_BARRIER)
1461 info->numBarriers = 1;
1462
1463 if (insn.dstCount()) {
1464 Instruction::DstRegister dst = insn.getDst(0);
1465
1466 if (dst.getFile() == TGSI_FILE_OUTPUT) {
1467 if (dst.isIndirect(0))
1468 for (unsigned i = 0; i < info->numOutputs; ++i)
1469 info->out[i].mask = 0xf;
1470 else
1471 info->out[dst.getIndex(0)].mask |= dst.getMask();
1472
1473 if (info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
1474 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
1475 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_LAYER ||
1476 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1477 info->out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
1478 info->out[dst.getIndex(0)].mask &= 1;
1479
1480 if (isEdgeFlagPassthrough(insn))
1481 info->io.edgeFlagIn = insn.getSrc(0).getIndex(0);
1482 } else
1483 if (dst.getFile() == TGSI_FILE_TEMPORARY) {
1484 if (dst.isIndirect(0))
1485 indirectTempArrays.insert(dst.getArrayId());
1486 } else
1487 if (dst.getFile() == TGSI_FILE_BUFFER ||
1488 dst.getFile() == TGSI_FILE_IMAGE ||
1489 (dst.getFile() == TGSI_FILE_MEMORY &&
1490 memoryFiles[dst.getIndex(0)].mem_type == TGSI_MEMORY_TYPE_GLOBAL)) {
1491 info->io.globalAccess |= 0x2;
1492 }
1493 }
1494
1495 for (unsigned s = 0; s < insn.srcCount(); ++s)
1496 scanInstructionSrc(insn, insn.getSrc(s), insn.srcMask(s));
1497
1498 for (unsigned s = 0; s < insn.getNumTexOffsets(); ++s)
1499 scanInstructionSrc(insn, insn.getTexOffset(s), insn.texOffsetMask());
1500
1501 return true;
1502 }
1503
1504 nv50_ir::TexInstruction::Target
1505 Instruction::getTexture(const tgsi::Source *code, int s) const
1506 {
1507 // XXX: indirect access
1508 unsigned int r;
1509
1510 switch (getSrc(s).getFile()) {
1511 /*
1512 case TGSI_FILE_RESOURCE:
1513 r = getSrc(s).getIndex(0);
1514 return translateTexture(code->resources.at(r).target);
1515 */
1516 case TGSI_FILE_SAMPLER_VIEW:
1517 r = getSrc(s).getIndex(0);
1518 return translateTexture(code->textureViews.at(r).target);
1519 default:
1520 return translateTexture(insn->Texture.Texture);
1521 }
1522 }
1523
1524 } // namespace tgsi
1525
1526 namespace {
1527
1528 using namespace nv50_ir;
1529
1530 class Converter : public BuildUtil
1531 {
1532 public:
1533 Converter(Program *, const tgsi::Source *);
1534 ~Converter();
1535
1536 bool run();
1537
1538 private:
1539 struct Subroutine
1540 {
1541 Subroutine(Function *f) : f(f) { }
1542 Function *f;
1543 ValueMap values;
1544 };
1545
1546 Value *shiftAddress(Value *);
1547 Value *getVertexBase(int s);
1548 Value *getOutputBase(int s);
1549 DataArray *getArrayForFile(unsigned file, int idx);
1550 Value *fetchSrc(int s, int c);
1551 Value *acquireDst(int d, int c);
1552 void storeDst(int d, int c, Value *);
1553
1554 Value *fetchSrc(const tgsi::Instruction::SrcRegister src, int c, Value *ptr);
1555 void storeDst(const tgsi::Instruction::DstRegister dst, int c,
1556 Value *val, Value *ptr);
1557
1558 void adjustTempIndex(int arrayId, int &idx, int &idx2d) const;
1559 Value *applySrcMod(Value *, int s, int c);
1560
1561 Symbol *makeSym(uint file, int fileIndex, int idx, int c, uint32_t addr);
1562 Symbol *srcToSym(tgsi::Instruction::SrcRegister, int c);
1563 Symbol *dstToSym(tgsi::Instruction::DstRegister, int c);
1564
1565 bool handleInstruction(const struct tgsi_full_instruction *);
1566 void exportOutputs();
1567 inline Subroutine *getSubroutine(unsigned ip);
1568 inline Subroutine *getSubroutine(Function *);
1569 inline bool isEndOfSubroutine(uint ip);
1570
1571 void loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask);
1572
1573 // R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
1574 void setTexRS(TexInstruction *, unsigned int& s, int R, int S);
1575 void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
1576 void handleTXF(Value *dst0[4], int R, int L_M);
1577 void handleTXQ(Value *dst0[4], enum TexQuery, int R);
1578 void handleLIT(Value *dst0[4]);
1579 void handleUserClipPlanes();
1580
1581 // Symbol *getResourceBase(int r);
1582 void getImageCoords(std::vector<Value *>&, int r, int s);
1583
1584 void handleLOAD(Value *dst0[4]);
1585 void handleSTORE();
1586 void handleATOM(Value *dst0[4], DataType, uint16_t subOp);
1587
1588 void handleINTERP(Value *dst0[4]);
1589
1590 uint8_t translateInterpMode(const struct nv50_ir_varying *var,
1591 operation& op);
1592 Value *interpolate(tgsi::Instruction::SrcRegister, int c, Value *ptr);
1593
1594 void insertConvergenceOps(BasicBlock *conv, BasicBlock *fork);
1595
1596 Value *buildDot(int dim);
1597
1598 class BindArgumentsPass : public Pass {
1599 public:
1600 BindArgumentsPass(Converter &conv) : conv(conv) { }
1601
1602 private:
1603 Converter &conv;
1604 Subroutine *sub;
1605
1606 inline const Location *getValueLocation(Subroutine *, Value *);
1607
1608 template<typename T> inline void
1609 updateCallArgs(Instruction *i, void (Instruction::*setArg)(int, Value *),
1610 T (Function::*proto));
1611
1612 template<typename T> inline void
1613 updatePrototype(BitSet *set, void (Function::*updateSet)(),
1614 T (Function::*proto));
1615
1616 protected:
1617 bool visit(Function *);
1618 bool visit(BasicBlock *bb) { return false; }
1619 };
1620
1621 private:
1622 const tgsi::Source *code;
1623 const struct nv50_ir_prog_info *info;
1624
1625 struct {
1626 std::map<unsigned, Subroutine> map;
1627 Subroutine *cur;
1628 } sub;
1629
1630 uint ip; // instruction pointer
1631
1632 tgsi::Instruction tgsi;
1633
1634 DataType dstTy;
1635 DataType srcTy;
1636
1637 DataArray tData; // TGSI_FILE_TEMPORARY
1638 DataArray lData; // TGSI_FILE_TEMPORARY, for indirect arrays
1639 DataArray aData; // TGSI_FILE_ADDRESS
1640 DataArray pData; // TGSI_FILE_PREDICATE
1641 DataArray oData; // TGSI_FILE_OUTPUT (if outputs in registers)
1642
1643 Value *zero;
1644 Value *fragCoord[4];
1645 Value *clipVtx[4];
1646
1647 Value *vtxBase[5]; // base address of vertex in primitive (for TP/GP)
1648 uint8_t vtxBaseValid;
1649
1650 Value *outBase; // base address of vertex out patch (for TCP)
1651
1652 Stack condBBs; // fork BB, then else clause BB
1653 Stack joinBBs; // fork BB, for inserting join ops on ENDIF
1654 Stack loopBBs; // loop headers
1655 Stack breakBBs; // end of / after loop
1656
1657 Value *viewport;
1658 };
1659
1660 Symbol *
1661 Converter::srcToSym(tgsi::Instruction::SrcRegister src, int c)
1662 {
1663 const int swz = src.getSwizzle(c);
1664
1665 /* TODO: Use Array ID when it's available for the index */
1666 return makeSym(src.getFile(),
1667 src.is2D() ? src.getIndex(1) : 0,
1668 src.getIndex(0), swz,
1669 src.getIndex(0) * 16 + swz * 4);
1670 }
1671
1672 Symbol *
1673 Converter::dstToSym(tgsi::Instruction::DstRegister dst, int c)
1674 {
1675 /* TODO: Use Array ID when it's available for the index */
1676 return makeSym(dst.getFile(),
1677 dst.is2D() ? dst.getIndex(1) : 0,
1678 dst.getIndex(0), c,
1679 dst.getIndex(0) * 16 + c * 4);
1680 }
1681
1682 Symbol *
1683 Converter::makeSym(uint tgsiFile, int fileIdx, int idx, int c, uint32_t address)
1684 {
1685 Symbol *sym = new_Symbol(prog, tgsi::translateFile(tgsiFile));
1686
1687 sym->reg.fileIndex = fileIdx;
1688
1689 if (tgsiFile == TGSI_FILE_MEMORY) {
1690 switch (code->memoryFiles[fileIdx].mem_type) {
1691 case TGSI_MEMORY_TYPE_GLOBAL:
1692 /* No-op this is the default for TGSI_FILE_MEMORY */
1693 sym->setFile(FILE_MEMORY_GLOBAL);
1694 break;
1695 case TGSI_MEMORY_TYPE_SHARED:
1696 sym->setFile(FILE_MEMORY_SHARED);
1697 break;
1698 case TGSI_MEMORY_TYPE_INPUT:
1699 assert(prog->getType() == Program::TYPE_COMPUTE);
1700 assert(idx == -1);
1701 sym->setFile(FILE_SHADER_INPUT);
1702 address += info->prop.cp.inputOffset;
1703 break;
1704 default:
1705 assert(0); /* TODO: Add support for global and private memory */
1706 }
1707 }
1708
1709 if (idx >= 0) {
1710 if (sym->reg.file == FILE_SHADER_INPUT)
1711 sym->setOffset(info->in[idx].slot[c] * 4);
1712 else
1713 if (sym->reg.file == FILE_SHADER_OUTPUT)
1714 sym->setOffset(info->out[idx].slot[c] * 4);
1715 else
1716 if (sym->reg.file == FILE_SYSTEM_VALUE)
1717 sym->setSV(tgsi::translateSysVal(info->sv[idx].sn), c);
1718 else
1719 sym->setOffset(address);
1720 } else {
1721 sym->setOffset(address);
1722 }
1723 return sym;
1724 }
1725
1726 uint8_t
1727 Converter::translateInterpMode(const struct nv50_ir_varying *var, operation& op)
1728 {
1729 uint8_t mode = NV50_IR_INTERP_PERSPECTIVE;
1730
1731 if (var->flat)
1732 mode = NV50_IR_INTERP_FLAT;
1733 else
1734 if (var->linear)
1735 mode = NV50_IR_INTERP_LINEAR;
1736 else
1737 if (var->sc)
1738 mode = NV50_IR_INTERP_SC;
1739
1740 op = (mode == NV50_IR_INTERP_PERSPECTIVE || mode == NV50_IR_INTERP_SC)
1741 ? OP_PINTERP : OP_LINTERP;
1742
1743 if (var->centroid)
1744 mode |= NV50_IR_INTERP_CENTROID;
1745
1746 return mode;
1747 }
1748
1749 Value *
1750 Converter::interpolate(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1751 {
1752 operation op;
1753
1754 // XXX: no way to know interpolation mode if we don't know what's accessed
1755 const uint8_t mode = translateInterpMode(&info->in[ptr ? 0 :
1756 src.getIndex(0)], op);
1757
1758 Instruction *insn = new_Instruction(func, op, TYPE_F32);
1759
1760 insn->setDef(0, getScratch());
1761 insn->setSrc(0, srcToSym(src, c));
1762 if (op == OP_PINTERP)
1763 insn->setSrc(1, fragCoord[3]);
1764 if (ptr)
1765 insn->setIndirect(0, 0, ptr);
1766
1767 insn->setInterpolate(mode);
1768
1769 bb->insertTail(insn);
1770 return insn->getDef(0);
1771 }
1772
1773 Value *
1774 Converter::applySrcMod(Value *val, int s, int c)
1775 {
1776 Modifier m = tgsi.getSrc(s).getMod(c);
1777 DataType ty = tgsi.inferSrcType();
1778
1779 if (m & Modifier(NV50_IR_MOD_ABS))
1780 val = mkOp1v(OP_ABS, ty, getScratch(), val);
1781
1782 if (m & Modifier(NV50_IR_MOD_NEG))
1783 val = mkOp1v(OP_NEG, ty, getScratch(), val);
1784
1785 return val;
1786 }
1787
1788 Value *
1789 Converter::getVertexBase(int s)
1790 {
1791 assert(s < 5);
1792 if (!(vtxBaseValid & (1 << s))) {
1793 const int index = tgsi.getSrc(s).getIndex(1);
1794 Value *rel = NULL;
1795 if (tgsi.getSrc(s).isIndirect(1))
1796 rel = fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL);
1797 vtxBaseValid |= 1 << s;
1798 vtxBase[s] = mkOp2v(OP_PFETCH, TYPE_U32, getSSA(4, FILE_ADDRESS),
1799 mkImm(index), rel);
1800 }
1801 return vtxBase[s];
1802 }
1803
1804 Value *
1805 Converter::getOutputBase(int s)
1806 {
1807 assert(s < 5);
1808 if (!(vtxBaseValid & (1 << s))) {
1809 Value *offset = loadImm(NULL, tgsi.getSrc(s).getIndex(1));
1810 if (tgsi.getSrc(s).isIndirect(1))
1811 offset = mkOp2v(OP_ADD, TYPE_U32, getSSA(),
1812 fetchSrc(tgsi.getSrc(s).getIndirect(1), 0, NULL),
1813 offset);
1814 vtxBaseValid |= 1 << s;
1815 vtxBase[s] = mkOp2v(OP_ADD, TYPE_U32, getSSA(), outBase, offset);
1816 }
1817 return vtxBase[s];
1818 }
1819
1820 Value *
1821 Converter::fetchSrc(int s, int c)
1822 {
1823 Value *res;
1824 Value *ptr = NULL, *dimRel = NULL;
1825
1826 tgsi::Instruction::SrcRegister src = tgsi.getSrc(s);
1827
1828 if (src.isIndirect(0))
1829 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
1830
1831 if (src.is2D()) {
1832 switch (src.getFile()) {
1833 case TGSI_FILE_OUTPUT:
1834 dimRel = getOutputBase(s);
1835 break;
1836 case TGSI_FILE_INPUT:
1837 dimRel = getVertexBase(s);
1838 break;
1839 case TGSI_FILE_CONSTANT:
1840 // on NVC0, this is valid and c{I+J}[k] == cI[(J << 16) + k]
1841 if (src.isIndirect(1))
1842 dimRel = fetchSrc(src.getIndirect(1), 0, 0);
1843 break;
1844 default:
1845 break;
1846 }
1847 }
1848
1849 res = fetchSrc(src, c, ptr);
1850
1851 if (dimRel)
1852 res->getInsn()->setIndirect(0, 1, dimRel);
1853
1854 return applySrcMod(res, s, c);
1855 }
1856
1857 Converter::DataArray *
1858 Converter::getArrayForFile(unsigned file, int idx)
1859 {
1860 switch (file) {
1861 case TGSI_FILE_TEMPORARY:
1862 return idx == 0 ? &tData : &lData;
1863 case TGSI_FILE_PREDICATE:
1864 return &pData;
1865 case TGSI_FILE_ADDRESS:
1866 return &aData;
1867 case TGSI_FILE_OUTPUT:
1868 assert(prog->getType() == Program::TYPE_FRAGMENT);
1869 return &oData;
1870 default:
1871 assert(!"invalid/unhandled TGSI source file");
1872 return NULL;
1873 }
1874 }
1875
1876 Value *
1877 Converter::shiftAddress(Value *index)
1878 {
1879 if (!index)
1880 return NULL;
1881 return mkOp2v(OP_SHL, TYPE_U32, getSSA(4, FILE_ADDRESS), index, mkImm(4));
1882 }
1883
1884 void
1885 Converter::adjustTempIndex(int arrayId, int &idx, int &idx2d) const
1886 {
1887 std::map<int, int>::const_iterator it =
1888 code->indirectTempOffsets.find(arrayId);
1889 if (it == code->indirectTempOffsets.end())
1890 return;
1891
1892 idx2d = 1;
1893 idx += it->second;
1894 }
1895
1896 Value *
1897 Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
1898 {
1899 int idx2d = src.is2D() ? src.getIndex(1) : 0;
1900 int idx = src.getIndex(0);
1901 const int swz = src.getSwizzle(c);
1902 Instruction *ld;
1903
1904 switch (src.getFile()) {
1905 case TGSI_FILE_IMMEDIATE:
1906 assert(!ptr);
1907 return loadImm(NULL, info->immd.data[idx * 4 + swz]);
1908 case TGSI_FILE_CONSTANT:
1909 return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
1910 case TGSI_FILE_INPUT:
1911 if (prog->getType() == Program::TYPE_FRAGMENT) {
1912 // don't load masked inputs, won't be assigned a slot
1913 if (!ptr && !(info->in[idx].mask & (1 << swz)))
1914 return loadImm(NULL, swz == TGSI_SWIZZLE_W ? 1.0f : 0.0f);
1915 return interpolate(src, c, shiftAddress(ptr));
1916 } else
1917 if (prog->getType() == Program::TYPE_GEOMETRY) {
1918 if (!ptr && info->in[idx].sn == TGSI_SEMANTIC_PRIMID)
1919 return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_PRIMITIVE_ID, 0));
1920 // XXX: This is going to be a problem with scalar arrays, i.e. when
1921 // we cannot assume that the address is given in units of vec4.
1922 //
1923 // nv50 and nvc0 need different things here, so let the lowering
1924 // passes decide what to do with the address
1925 if (ptr)
1926 return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
1927 }
1928 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1929 ld->perPatch = info->in[idx].patch;
1930 return ld->getDef(0);
1931 case TGSI_FILE_OUTPUT:
1932 assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
1933 ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
1934 ld->perPatch = info->out[idx].patch;
1935 return ld->getDef(0);
1936 case TGSI_FILE_SYSTEM_VALUE:
1937 assert(!ptr);
1938 ld = mkOp1(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
1939 ld->perPatch = info->sv[idx].patch;
1940 return ld->getDef(0);
1941 case TGSI_FILE_TEMPORARY: {
1942 int arrayid = src.getArrayId();
1943 if (!arrayid)
1944 arrayid = code->tempArrayId[idx];
1945 adjustTempIndex(arrayid, idx, idx2d);
1946 }
1947 /* fallthrough */
1948 default:
1949 return getArrayForFile(src.getFile(), idx2d)->load(
1950 sub.cur->values, idx, swz, shiftAddress(ptr));
1951 }
1952 }
1953
1954 Value *
1955 Converter::acquireDst(int d, int c)
1956 {
1957 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1958 const unsigned f = dst.getFile();
1959 int idx = dst.getIndex(0);
1960 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
1961
1962 if (dst.isMasked(c) || f == TGSI_FILE_BUFFER || f == TGSI_FILE_MEMORY ||
1963 f == TGSI_FILE_IMAGE)
1964 return NULL;
1965
1966 if (dst.isIndirect(0) ||
1967 f == TGSI_FILE_SYSTEM_VALUE ||
1968 (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT))
1969 return getScratch();
1970
1971 if (f == TGSI_FILE_TEMPORARY) {
1972 int arrayid = dst.getArrayId();
1973 if (!arrayid)
1974 arrayid = code->tempArrayId[idx];
1975 adjustTempIndex(arrayid, idx, idx2d);
1976 }
1977
1978 return getArrayForFile(f, idx2d)-> acquire(sub.cur->values, idx, c);
1979 }
1980
1981 void
1982 Converter::storeDst(int d, int c, Value *val)
1983 {
1984 const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
1985
1986 if (tgsi.getSaturate()) {
1987 mkOp1(OP_SAT, dstTy, val, val);
1988 }
1989
1990 Value *ptr = NULL;
1991 if (dst.isIndirect(0))
1992 ptr = shiftAddress(fetchSrc(dst.getIndirect(0), 0, NULL));
1993
1994 if (info->io.genUserClip > 0 &&
1995 dst.getFile() == TGSI_FILE_OUTPUT &&
1996 !dst.isIndirect(0) && dst.getIndex(0) == code->clipVertexOutput) {
1997 mkMov(clipVtx[c], val);
1998 val = clipVtx[c];
1999 }
2000
2001 storeDst(dst, c, val, ptr);
2002 }
2003
2004 void
2005 Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
2006 Value *val, Value *ptr)
2007 {
2008 const unsigned f = dst.getFile();
2009 int idx = dst.getIndex(0);
2010 int idx2d = dst.is2D() ? dst.getIndex(1) : 0;
2011
2012 if (f == TGSI_FILE_SYSTEM_VALUE) {
2013 assert(!ptr);
2014 mkOp2(OP_WRSV, TYPE_U32, NULL, dstToSym(dst, c), val);
2015 } else
2016 if (f == TGSI_FILE_OUTPUT && prog->getType() != Program::TYPE_FRAGMENT) {
2017
2018 if (ptr || (info->out[idx].mask & (1 << c))) {
2019 /* Save the viewport index into a scratch register so that it can be
2020 exported at EMIT time */
2021 if (info->out[idx].sn == TGSI_SEMANTIC_VIEWPORT_INDEX &&
2022 viewport != NULL)
2023 mkOp1(OP_MOV, TYPE_U32, viewport, val);
2024 else
2025 mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
2026 info->out[idx].patch;
2027 }
2028 } else
2029 if (f == TGSI_FILE_TEMPORARY ||
2030 f == TGSI_FILE_PREDICATE ||
2031 f == TGSI_FILE_ADDRESS ||
2032 f == TGSI_FILE_OUTPUT) {
2033 if (f == TGSI_FILE_TEMPORARY) {
2034 int arrayid = dst.getArrayId();
2035 if (!arrayid)
2036 arrayid = code->tempArrayId[idx];
2037 adjustTempIndex(arrayid, idx, idx2d);
2038 }
2039
2040 getArrayForFile(f, idx2d)->store(sub.cur->values, idx, c, ptr, val);
2041 } else {
2042 assert(!"invalid dst file");
2043 }
2044 }
2045
2046 #define FOR_EACH_DST_ENABLED_CHANNEL(d, chan, inst) \
2047 for (chan = 0; chan < 4; ++chan) \
2048 if (!inst.getDst(d).isMasked(chan))
2049
2050 Value *
2051 Converter::buildDot(int dim)
2052 {
2053 assert(dim > 0);
2054
2055 Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
2056 Value *dotp = getScratch();
2057
2058 mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
2059
2060 for (int c = 1; c < dim; ++c) {
2061 src0 = fetchSrc(0, c);
2062 src1 = fetchSrc(1, c);
2063 mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
2064 }
2065 return dotp;
2066 }
2067
2068 void
2069 Converter::insertConvergenceOps(BasicBlock *conv, BasicBlock *fork)
2070 {
2071 FlowInstruction *join = new_FlowInstruction(func, OP_JOIN, NULL);
2072 join->fixed = 1;
2073 conv->insertHead(join);
2074
2075 assert(!fork->joinAt);
2076 fork->joinAt = new_FlowInstruction(func, OP_JOINAT, conv);
2077 fork->insertBefore(fork->getExit(), fork->joinAt);
2078 }
2079
2080 void
2081 Converter::setTexRS(TexInstruction *tex, unsigned int& s, int R, int S)
2082 {
2083 unsigned rIdx = 0, sIdx = 0;
2084
2085 if (R >= 0)
2086 rIdx = tgsi.getSrc(R).getIndex(0);
2087 if (S >= 0)
2088 sIdx = tgsi.getSrc(S).getIndex(0);
2089
2090 tex->setTexture(tgsi.getTexture(code, R), rIdx, sIdx);
2091
2092 if (tgsi.getSrc(R).isIndirect(0)) {
2093 tex->tex.rIndirectSrc = s;
2094 tex->setSrc(s++, fetchSrc(tgsi.getSrc(R).getIndirect(0), 0, NULL));
2095 }
2096 if (S >= 0 && tgsi.getSrc(S).isIndirect(0)) {
2097 tex->tex.sIndirectSrc = s;
2098 tex->setSrc(s++, fetchSrc(tgsi.getSrc(S).getIndirect(0), 0, NULL));
2099 }
2100 }
2101
2102 void
2103 Converter::handleTXQ(Value *dst0[4], enum TexQuery query, int R)
2104 {
2105 TexInstruction *tex = new_TexInstruction(func, OP_TXQ);
2106 tex->tex.query = query;
2107 unsigned int c, d;
2108
2109 for (d = 0, c = 0; c < 4; ++c) {
2110 if (!dst0[c])
2111 continue;
2112 tex->tex.mask |= 1 << c;
2113 tex->setDef(d++, dst0[c]);
2114 }
2115 if (query == TXQ_DIMS)
2116 tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
2117 else
2118 tex->setSrc((c = 0), zero);
2119
2120 setTexRS(tex, ++c, R, -1);
2121
2122 bb->insertTail(tex);
2123 }
2124
2125 void
2126 Converter::loadProjTexCoords(Value *dst[4], Value *src[4], unsigned int mask)
2127 {
2128 Value *proj = fetchSrc(0, 3);
2129 Instruction *insn = proj->getUniqueInsn();
2130 int c;
2131
2132 if (insn->op == OP_PINTERP) {
2133 bb->insertTail(insn = cloneForward(func, insn));
2134 insn->op = OP_LINTERP;
2135 insn->setInterpolate(NV50_IR_INTERP_LINEAR | insn->getSampleMode());
2136 insn->setSrc(1, NULL);
2137 proj = insn->getDef(0);
2138 }
2139 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), proj);
2140
2141 for (c = 0; c < 4; ++c) {
2142 if (!(mask & (1 << c)))
2143 continue;
2144 if ((insn = src[c]->getUniqueInsn())->op != OP_PINTERP)
2145 continue;
2146 mask &= ~(1 << c);
2147
2148 bb->insertTail(insn = cloneForward(func, insn));
2149 insn->setInterpolate(NV50_IR_INTERP_PERSPECTIVE | insn->getSampleMode());
2150 insn->setSrc(1, proj);
2151 dst[c] = insn->getDef(0);
2152 }
2153 if (!mask)
2154 return;
2155
2156 proj = mkOp1v(OP_RCP, TYPE_F32, getSSA(), fetchSrc(0, 3));
2157
2158 for (c = 0; c < 4; ++c)
2159 if (mask & (1 << c))
2160 dst[c] = mkOp2v(OP_MUL, TYPE_F32, getSSA(), src[c], proj);
2161 }
2162
2163 // order of nv50 ir sources: x y z layer lod/bias shadow
2164 // order of TGSI TEX sources: x y z layer shadow lod/bias
2165 // lowering will finally set the hw specific order (like array first on nvc0)
2166 void
2167 Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
2168 {
2169 Value *arg[4], *src[8];
2170 Value *lod = NULL, *shd = NULL;
2171 unsigned int s, c, d;
2172 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2173
2174 TexInstruction::Target tgt = tgsi.getTexture(code, R);
2175
2176 for (s = 0; s < tgt.getArgCount(); ++s)
2177 arg[s] = src[s] = fetchSrc(0, s);
2178
2179 if (texi->op == OP_TXL || texi->op == OP_TXB)
2180 lod = fetchSrc(L >> 4, L & 3);
2181
2182 if (C == 0x0f)
2183 C = 0x00 | MAX2(tgt.getArgCount(), 2); // guess DC src
2184
2185 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 &&
2186 tgt == TEX_TARGET_CUBE_ARRAY_SHADOW)
2187 shd = fetchSrc(1, 0);
2188 else if (tgt.isShadow())
2189 shd = fetchSrc(C >> 4, C & 3);
2190
2191 if (texi->op == OP_TXD) {
2192 for (c = 0; c < tgt.getDim() + tgt.isCube(); ++c) {
2193 texi->dPdx[c].set(fetchSrc(Dx >> 4, (Dx & 3) + c));
2194 texi->dPdy[c].set(fetchSrc(Dy >> 4, (Dy & 3) + c));
2195 }
2196 }
2197
2198 // cube textures don't care about projection value, it's divided out
2199 if (tgsi.getOpcode() == TGSI_OPCODE_TXP && !tgt.isCube() && !tgt.isArray()) {
2200 unsigned int n = tgt.getDim();
2201 if (shd) {
2202 arg[n] = shd;
2203 ++n;
2204 assert(tgt.getDim() == tgt.getArgCount());
2205 }
2206 loadProjTexCoords(src, arg, (1 << n) - 1);
2207 if (shd)
2208 shd = src[n - 1];
2209 }
2210
2211 for (c = 0, d = 0; c < 4; ++c) {
2212 if (dst[c]) {
2213 texi->setDef(d++, dst[c]);
2214 texi->tex.mask |= 1 << c;
2215 } else {
2216 // NOTE: maybe hook up def too, for CSE
2217 }
2218 }
2219 for (s = 0; s < tgt.getArgCount(); ++s)
2220 texi->setSrc(s, src[s]);
2221 if (lod)
2222 texi->setSrc(s++, lod);
2223 if (shd)
2224 texi->setSrc(s++, shd);
2225
2226 setTexRS(texi, s, R, S);
2227
2228 if (tgsi.getOpcode() == TGSI_OPCODE_SAMPLE_C_LZ)
2229 texi->tex.levelZero = true;
2230 if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
2231 texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
2232
2233 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2234 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2235 for (c = 0; c < 3; ++c) {
2236 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2237 texi->offset[s][c].setInsn(texi);
2238 }
2239 }
2240
2241 bb->insertTail(texi);
2242 }
2243
2244 // 1st source: xyz = coordinates, w = lod/sample
2245 // 2nd source: offset
2246 void
2247 Converter::handleTXF(Value *dst[4], int R, int L_M)
2248 {
2249 TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
2250 int ms;
2251 unsigned int c, d, s;
2252
2253 texi->tex.target = tgsi.getTexture(code, R);
2254
2255 ms = texi->tex.target.isMS() ? 1 : 0;
2256 texi->tex.levelZero = ms; /* MS textures don't have mip-maps */
2257
2258 for (c = 0, d = 0; c < 4; ++c) {
2259 if (dst[c]) {
2260 texi->setDef(d++, dst[c]);
2261 texi->tex.mask |= 1 << c;
2262 }
2263 }
2264 for (c = 0; c < (texi->tex.target.getArgCount() - ms); ++c)
2265 texi->setSrc(c, fetchSrc(0, c));
2266 texi->setSrc(c++, fetchSrc(L_M >> 4, L_M & 3)); // lod or ms
2267
2268 setTexRS(texi, c, R, -1);
2269
2270 texi->tex.useOffsets = tgsi.getNumTexOffsets();
2271 for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
2272 for (c = 0; c < 3; ++c) {
2273 texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
2274 texi->offset[s][c].setInsn(texi);
2275 }
2276 }
2277
2278 bb->insertTail(texi);
2279 }
2280
2281 void
2282 Converter::handleLIT(Value *dst0[4])
2283 {
2284 Value *val0 = NULL;
2285 unsigned int mask = tgsi.getDst(0).getMask();
2286
2287 if (mask & (1 << 0))
2288 loadImm(dst0[0], 1.0f);
2289
2290 if (mask & (1 << 3))
2291 loadImm(dst0[3], 1.0f);
2292
2293 if (mask & (3 << 1)) {
2294 val0 = getScratch();
2295 mkOp2(OP_MAX, TYPE_F32, val0, fetchSrc(0, 0), zero);
2296 if (mask & (1 << 1))
2297 mkMov(dst0[1], val0);
2298 }
2299
2300 if (mask & (1 << 2)) {
2301 Value *src1 = fetchSrc(0, 1), *src3 = fetchSrc(0, 3);
2302 Value *val1 = getScratch(), *val3 = getScratch();
2303
2304 Value *pos128 = loadImm(NULL, +127.999999f);
2305 Value *neg128 = loadImm(NULL, -127.999999f);
2306
2307 mkOp2(OP_MAX, TYPE_F32, val1, src1, zero);
2308 mkOp2(OP_MAX, TYPE_F32, val3, src3, neg128);
2309 mkOp2(OP_MIN, TYPE_F32, val3, val3, pos128);
2310 mkOp2(OP_POW, TYPE_F32, val3, val1, val3);
2311
2312 mkCmp(OP_SLCT, CC_GT, TYPE_F32, dst0[2], TYPE_F32, val3, zero, val0);
2313 }
2314 }
2315
2316 /* Keep this around for now as reference when adding img support
2317 static inline bool
2318 isResourceSpecial(const int r)
2319 {
2320 return (r == TGSI_RESOURCE_GLOBAL ||
2321 r == TGSI_RESOURCE_LOCAL ||
2322 r == TGSI_RESOURCE_PRIVATE ||
2323 r == TGSI_RESOURCE_INPUT);
2324 }
2325
2326 static inline bool
2327 isResourceRaw(const tgsi::Source *code, const int r)
2328 {
2329 return isResourceSpecial(r) || code->resources[r].raw;
2330 }
2331
2332 static inline nv50_ir::TexTarget
2333 getResourceTarget(const tgsi::Source *code, int r)
2334 {
2335 if (isResourceSpecial(r))
2336 return nv50_ir::TEX_TARGET_BUFFER;
2337 return tgsi::translateTexture(code->resources.at(r).target);
2338 }
2339
2340 Symbol *
2341 Converter::getResourceBase(const int r)
2342 {
2343 Symbol *sym = NULL;
2344
2345 switch (r) {
2346 case TGSI_RESOURCE_GLOBAL:
2347 sym = new_Symbol(prog, nv50_ir::FILE_MEMORY_GLOBAL,
2348 info->io.auxCBSlot);
2349 break;
2350 case TGSI_RESOURCE_LOCAL:
2351 assert(prog->getType() == Program::TYPE_COMPUTE);
2352 sym = mkSymbol(nv50_ir::FILE_MEMORY_SHARED, 0, TYPE_U32,
2353 info->prop.cp.sharedOffset);
2354 break;
2355 case TGSI_RESOURCE_PRIVATE:
2356 sym = mkSymbol(nv50_ir::FILE_MEMORY_LOCAL, 0, TYPE_U32,
2357 info->bin.tlsSpace);
2358 break;
2359 case TGSI_RESOURCE_INPUT:
2360 assert(prog->getType() == Program::TYPE_COMPUTE);
2361 sym = mkSymbol(nv50_ir::FILE_SHADER_INPUT, 0, TYPE_U32,
2362 info->prop.cp.inputOffset);
2363 break;
2364 default:
2365 sym = new_Symbol(prog,
2366 nv50_ir::FILE_MEMORY_GLOBAL, code->resources.at(r).slot);
2367 break;
2368 }
2369 return sym;
2370 }
2371
2372 void
2373 Converter::getResourceCoords(std::vector<Value *> &coords, int r, int s)
2374 {
2375 const int arg =
2376 TexInstruction::Target(getResourceTarget(code, r)).getArgCount();
2377
2378 for (int c = 0; c < arg; ++c)
2379 coords.push_back(fetchSrc(s, c));
2380
2381 // NOTE: TGSI_RESOURCE_GLOBAL needs FILE_GPR; this is an nv50 quirk
2382 if (r == TGSI_RESOURCE_LOCAL ||
2383 r == TGSI_RESOURCE_PRIVATE ||
2384 r == TGSI_RESOURCE_INPUT)
2385 coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
2386 coords[0]);
2387 }
2388 */
2389 static inline int
2390 partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
2391 {
2392 int n = 0;
2393
2394 while (mask) {
2395 if (mask & 1) {
2396 size[n]++;
2397 } else {
2398 if (size[n])
2399 comp[n = 1] = size[0] + 1;
2400 else
2401 comp[n]++;
2402 }
2403 mask >>= 1;
2404 }
2405 if (size[0] == 3) {
2406 n = 1;
2407 size[0] = (comp[0] == 1) ? 1 : 2;
2408 size[1] = 3 - size[0];
2409 comp[1] = comp[0] + size[0];
2410 }
2411 return n + 1;
2412 }
2413
2414 static inline nv50_ir::TexTarget
2415 getImageTarget(const tgsi::Source *code, int r)
2416 {
2417 return tgsi::translateTexture(code->images.at(r).target);
2418 }
2419
2420 static inline const nv50_ir::TexInstruction::ImgFormatDesc *
2421 getImageFormat(const tgsi::Source *code, int r)
2422 {
2423 return &nv50_ir::TexInstruction::formatTable[
2424 tgsi::translateImgFormat(code->images.at(r).format)];
2425 }
2426
2427 void
2428 Converter::getImageCoords(std::vector<Value *> &coords, int r, int s)
2429 {
2430 TexInstruction::Target t =
2431 TexInstruction::Target(getImageTarget(code, r));
2432 const int arg = t.getDim() + (t.isArray() || t.isCube());
2433
2434 for (int c = 0; c < arg; ++c)
2435 coords.push_back(fetchSrc(s, c));
2436
2437 if (t.isMS())
2438 coords.push_back(fetchSrc(s, 3));
2439 }
2440
2441 // For raw loads, granularity is 4 byte.
2442 // Usage of the texture read mask on OP_SULDP is not allowed.
2443 void
2444 Converter::handleLOAD(Value *dst0[4])
2445 {
2446 const int r = tgsi.getSrc(0).getIndex(0);
2447 int c;
2448 std::vector<Value *> off, src, ldv, def;
2449
2450 switch (tgsi.getSrc(0).getFile()) {
2451 case TGSI_FILE_BUFFER:
2452 case TGSI_FILE_MEMORY:
2453 for (c = 0; c < 4; ++c) {
2454 if (!dst0[c])
2455 continue;
2456
2457 Value *off;
2458 Symbol *sym;
2459 uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
2460
2461 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
2462 off = NULL;
2463 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2464 tgsi.getSrc(1).getValueU32(0, info) +
2465 src0_component_offset);
2466 } else {
2467 // yzw are ignored for buffers
2468 off = fetchSrc(1, 0);
2469 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2470 src0_component_offset);
2471 }
2472
2473 Instruction *ld = mkLoad(TYPE_U32, dst0[c], sym, off);
2474 ld->cache = tgsi.getCacheMode();
2475 if (tgsi.getSrc(0).isIndirect(0))
2476 ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
2477 }
2478 break;
2479 case TGSI_FILE_IMAGE: {
2480 assert(!code->images[r].raw);
2481
2482 getImageCoords(off, r, 1);
2483 def.resize(4);
2484
2485 for (c = 0; c < 4; ++c) {
2486 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2487 def[c] = getScratch();
2488 else
2489 def[c] = dst0[c];
2490 }
2491
2492 TexInstruction *ld =
2493 mkTex(OP_SULDP, getImageTarget(code, r), code->images[r].slot, 0,
2494 def, off);
2495 ld->tex.mask = tgsi.getDst(0).getMask();
2496 ld->tex.format = getImageFormat(code, r);
2497 ld->cache = tgsi.getCacheMode();
2498 if (tgsi.getSrc(0).isIndirect(0))
2499 ld->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2500
2501 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2502 if (dst0[c] != def[c])
2503 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2504 }
2505 break;
2506 default:
2507 assert(!"Unsupported srcFile for LOAD");
2508 }
2509
2510 /* Keep this around for now as reference when adding img support
2511 getResourceCoords(off, r, 1);
2512
2513 if (isResourceRaw(code, r)) {
2514 uint8_t mask = 0;
2515 uint8_t comp[2] = { 0, 0 };
2516 uint8_t size[2] = { 0, 0 };
2517
2518 Symbol *base = getResourceBase(r);
2519
2520 // determine the base and size of the at most 2 load ops
2521 for (c = 0; c < 4; ++c)
2522 if (!tgsi.getDst(0).isMasked(c))
2523 mask |= 1 << (tgsi.getSrc(0).getSwizzle(c) - TGSI_SWIZZLE_X);
2524
2525 int n = partitionLoadStore(comp, size, mask);
2526
2527 src = off;
2528
2529 def.resize(4); // index by component, the ones we need will be non-NULL
2530 for (c = 0; c < 4; ++c) {
2531 if (dst0[c] && tgsi.getSrc(0).getSwizzle(c) == (TGSI_SWIZZLE_X + c))
2532 def[c] = dst0[c];
2533 else
2534 if (mask & (1 << c))
2535 def[c] = getScratch();
2536 }
2537
2538 const bool useLd = isResourceSpecial(r) ||
2539 (info->io.nv50styleSurfaces &&
2540 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2541
2542 for (int i = 0; i < n; ++i) {
2543 ldv.assign(def.begin() + comp[i], def.begin() + comp[i] + size[i]);
2544
2545 if (comp[i]) // adjust x component of source address if necessary
2546 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2547 off[0], mkImm(comp[i] * 4));
2548 else
2549 src[0] = off[0];
2550
2551 if (useLd) {
2552 Instruction *ld =
2553 mkLoad(typeOfSize(size[i] * 4), ldv[0], base, src[0]);
2554 for (size_t c = 1; c < ldv.size(); ++c)
2555 ld->setDef(c, ldv[c]);
2556 } else {
2557 mkTex(OP_SULDB, getResourceTarget(code, r), code->resources[r].slot,
2558 0, ldv, src)->dType = typeOfSize(size[i] * 4);
2559 }
2560 }
2561 } else {
2562 def.resize(4);
2563 for (c = 0; c < 4; ++c) {
2564 if (!dst0[c] || tgsi.getSrc(0).getSwizzle(c) != (TGSI_SWIZZLE_X + c))
2565 def[c] = getScratch();
2566 else
2567 def[c] = dst0[c];
2568 }
2569
2570 mkTex(OP_SULDP, getResourceTarget(code, r), code->resources[r].slot, 0,
2571 def, off);
2572 }
2573 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2574 if (dst0[c] != def[c])
2575 mkMov(dst0[c], def[tgsi.getSrc(0).getSwizzle(c)]);
2576 */
2577 }
2578
2579 // For formatted stores, the write mask on OP_SUSTP can be used.
2580 // Raw stores have to be split.
2581 void
2582 Converter::handleSTORE()
2583 {
2584 const int r = tgsi.getDst(0).getIndex(0);
2585 int c;
2586 std::vector<Value *> off, src, dummy;
2587
2588 switch (tgsi.getDst(0).getFile()) {
2589 case TGSI_FILE_BUFFER:
2590 case TGSI_FILE_MEMORY:
2591 for (c = 0; c < 4; ++c) {
2592 if (!(tgsi.getDst(0).getMask() & (1 << c)))
2593 continue;
2594
2595 Symbol *sym;
2596 Value *off;
2597 if (tgsi.getSrc(0).getFile() == TGSI_FILE_IMMEDIATE) {
2598 off = NULL;
2599 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c,
2600 tgsi.getSrc(0).getValueU32(0, info) + 4 * c);
2601 } else {
2602 // yzw are ignored for buffers
2603 off = fetchSrc(0, 0);
2604 sym = makeSym(tgsi.getDst(0).getFile(), r, -1, c, 4 * c);
2605 }
2606
2607 Instruction *st = mkStore(OP_STORE, TYPE_U32, sym, off, fetchSrc(1, c));
2608 st->cache = tgsi.getCacheMode();
2609 if (tgsi.getDst(0).isIndirect(0))
2610 st->setIndirect(0, 1, fetchSrc(tgsi.getDst(0).getIndirect(0), 0, 0));
2611 }
2612 break;
2613 case TGSI_FILE_IMAGE: {
2614 assert(!code->images[r].raw);
2615
2616 getImageCoords(off, r, 0);
2617 src = off;
2618
2619 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2620 src.push_back(fetchSrc(1, c));
2621
2622 TexInstruction *st =
2623 mkTex(OP_SUSTP, getImageTarget(code, r), code->images[r].slot,
2624 0, dummy, src);
2625 st->tex.mask = tgsi.getDst(0).getMask();
2626 st->tex.format = getImageFormat(code, r);
2627 st->cache = tgsi.getCacheMode();
2628 if (tgsi.getDst(0).isIndirect(0))
2629 st->setIndirectR(fetchSrc(tgsi.getDst(0).getIndirect(0), 0, NULL));
2630 }
2631 break;
2632 default:
2633 assert(!"Unsupported dstFile for STORE");
2634 }
2635
2636 /* Keep this around for now as reference when adding img support
2637 getResourceCoords(off, r, 0);
2638 src = off;
2639 const int s = src.size();
2640
2641 if (isResourceRaw(code, r)) {
2642 uint8_t comp[2] = { 0, 0 };
2643 uint8_t size[2] = { 0, 0 };
2644
2645 int n = partitionLoadStore(comp, size, tgsi.getDst(0).getMask());
2646
2647 Symbol *base = getResourceBase(r);
2648
2649 const bool useSt = isResourceSpecial(r) ||
2650 (info->io.nv50styleSurfaces &&
2651 code->resources[r].target == TGSI_TEXTURE_BUFFER);
2652
2653 for (int i = 0; i < n; ++i) {
2654 if (comp[i]) // adjust x component of source address if necessary
2655 src[0] = mkOp2v(OP_ADD, TYPE_U32, getSSA(4, off[0]->reg.file),
2656 off[0], mkImm(comp[i] * 4));
2657 else
2658 src[0] = off[0];
2659
2660 const DataType stTy = typeOfSize(size[i] * 4);
2661
2662 if (useSt) {
2663 Instruction *st =
2664 mkStore(OP_STORE, stTy, base, NULL, fetchSrc(1, comp[i]));
2665 for (c = 1; c < size[i]; ++c)
2666 st->setSrc(1 + c, fetchSrc(1, comp[i] + c));
2667 st->setIndirect(0, 0, src[0]);
2668 } else {
2669 // attach values to be stored
2670 src.resize(s + size[i]);
2671 for (c = 0; c < size[i]; ++c)
2672 src[s + c] = fetchSrc(1, comp[i] + c);
2673 mkTex(OP_SUSTB, getResourceTarget(code, r), code->resources[r].slot,
2674 0, dummy, src)->setType(stTy);
2675 }
2676 }
2677 } else {
2678 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
2679 src.push_back(fetchSrc(1, c));
2680
2681 mkTex(OP_SUSTP, getResourceTarget(code, r), code->resources[r].slot, 0,
2682 dummy, src)->tex.mask = tgsi.getDst(0).getMask();
2683 }
2684 */
2685 }
2686
2687 // XXX: These only work on resources with the single-component u32/s32 formats.
2688 // Therefore the result is replicated. This might not be intended by TGSI, but
2689 // operating on more than 1 component would produce undefined results because
2690 // they do not exist.
2691 void
2692 Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
2693 {
2694 const int r = tgsi.getSrc(0).getIndex(0);
2695 std::vector<Value *> srcv;
2696 std::vector<Value *> defv;
2697 LValue *dst = getScratch();
2698
2699 switch (tgsi.getSrc(0).getFile()) {
2700 case TGSI_FILE_BUFFER:
2701 case TGSI_FILE_MEMORY:
2702 for (int c = 0; c < 4; ++c) {
2703 if (!dst0[c])
2704 continue;
2705
2706 Instruction *insn;
2707 Value *off = fetchSrc(1, c), *off2 = NULL;
2708 Value *sym;
2709 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE)
2710 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
2711 tgsi.getSrc(1).getValueU32(c, info));
2712 else
2713 sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c, 0);
2714 if (tgsi.getSrc(0).isIndirect(0))
2715 off2 = fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0);
2716 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2717 insn = mkOp3(OP_ATOM, ty, dst, sym, fetchSrc(2, c), fetchSrc(3, c));
2718 else
2719 insn = mkOp2(OP_ATOM, ty, dst, sym, fetchSrc(2, c));
2720 if (tgsi.getSrc(1).getFile() != TGSI_FILE_IMMEDIATE)
2721 insn->setIndirect(0, 0, off);
2722 if (off2)
2723 insn->setIndirect(0, 1, off2);
2724 insn->subOp = subOp;
2725 }
2726 for (int c = 0; c < 4; ++c)
2727 if (dst0[c])
2728 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2729 break;
2730 case TGSI_FILE_IMAGE: {
2731 assert(!code->images[r].raw);
2732
2733 getImageCoords(srcv, r, 1);
2734 defv.push_back(dst);
2735 srcv.push_back(fetchSrc(2, 0));
2736
2737 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2738 srcv.push_back(fetchSrc(3, 0));
2739
2740 TexInstruction *tex = mkTex(OP_SUREDP, getImageTarget(code, r),
2741 code->images[r].slot, 0, defv, srcv);
2742 tex->subOp = subOp;
2743 tex->tex.mask = 1;
2744 tex->tex.format = getImageFormat(code, r);
2745 tex->setType(ty);
2746 if (tgsi.getSrc(0).isIndirect(0))
2747 tex->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
2748
2749 for (int c = 0; c < 4; ++c)
2750 if (dst0[c])
2751 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2752 }
2753 break;
2754 default:
2755 assert(!"Unsupported srcFile for ATOM");
2756 }
2757
2758 /* Keep this around for now as reference when adding img support
2759 getResourceCoords(srcv, r, 1);
2760
2761 if (isResourceSpecial(r)) {
2762 assert(r != TGSI_RESOURCE_INPUT);
2763 Instruction *insn;
2764 insn = mkOp2(OP_ATOM, ty, dst, getResourceBase(r), fetchSrc(2, 0));
2765 insn->subOp = subOp;
2766 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2767 insn->setSrc(2, fetchSrc(3, 0));
2768 insn->setIndirect(0, 0, srcv.at(0));
2769 } else {
2770 operation op = isResourceRaw(code, r) ? OP_SUREDB : OP_SUREDP;
2771 TexTarget targ = getResourceTarget(code, r);
2772 int idx = code->resources[r].slot;
2773 defv.push_back(dst);
2774 srcv.push_back(fetchSrc(2, 0));
2775 if (subOp == NV50_IR_SUBOP_ATOM_CAS)
2776 srcv.push_back(fetchSrc(3, 0));
2777 TexInstruction *tex = mkTex(op, targ, idx, 0, defv, srcv);
2778 tex->subOp = subOp;
2779 tex->tex.mask = 1;
2780 tex->setType(ty);
2781 }
2782
2783 for (int c = 0; c < 4; ++c)
2784 if (dst0[c])
2785 dst0[c] = dst; // not equal to rDst so handleInstruction will do mkMov
2786 */
2787 }
2788
2789 void
2790 Converter::handleINTERP(Value *dst[4])
2791 {
2792 // Check whether the input is linear. All other attributes ignored.
2793 Instruction *insn;
2794 Value *offset = NULL, *ptr = NULL, *w = NULL;
2795 Symbol *sym[4] = { NULL };
2796 bool linear;
2797 operation op = OP_NOP;
2798 int c, mode = 0;
2799
2800 tgsi::Instruction::SrcRegister src = tgsi.getSrc(0);
2801
2802 // In some odd cases, in large part due to varying packing, the source
2803 // might not actually be an input. This is illegal TGSI, but it's easier to
2804 // account for it here than it is to fix it where the TGSI is being
2805 // generated. In that case, it's going to be a straight up mov (or sequence
2806 // of mov's) from the input in question. We follow the mov chain to see
2807 // which input we need to use.
2808 if (src.getFile() != TGSI_FILE_INPUT) {
2809 if (src.isIndirect(0)) {
2810 ERROR("Ignoring indirect input interpolation\n");
2811 return;
2812 }
2813 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2814 Value *val = fetchSrc(0, c);
2815 assert(val->defs.size() == 1);
2816 insn = val->getInsn();
2817 while (insn->op == OP_MOV) {
2818 assert(insn->getSrc(0)->defs.size() == 1);
2819 insn = insn->getSrc(0)->getInsn();
2820 if (!insn) {
2821 ERROR("Miscompiling shader due to unhandled INTERP\n");
2822 return;
2823 }
2824 }
2825 if (insn->op != OP_LINTERP && insn->op != OP_PINTERP) {
2826 ERROR("Trying to interpolate non-input, this is not allowed.\n");
2827 return;
2828 }
2829 sym[c] = insn->getSrc(0)->asSym();
2830 assert(sym[c]);
2831 op = insn->op;
2832 mode = insn->ipa;
2833 }
2834 } else {
2835 if (src.isIndirect(0))
2836 ptr = fetchSrc(src.getIndirect(0), 0, NULL);
2837
2838 // We can assume that the fixed index will point to an input of the same
2839 // interpolation type in case of an indirect.
2840 // TODO: Make use of ArrayID.
2841 linear = info->in[src.getIndex(0)].linear;
2842 if (linear) {
2843 op = OP_LINTERP;
2844 mode = NV50_IR_INTERP_LINEAR;
2845 } else {
2846 op = OP_PINTERP;
2847 mode = NV50_IR_INTERP_PERSPECTIVE;
2848 }
2849 }
2850
2851 switch (tgsi.getOpcode()) {
2852 case TGSI_OPCODE_INTERP_CENTROID:
2853 mode |= NV50_IR_INTERP_CENTROID;
2854 break;
2855 case TGSI_OPCODE_INTERP_SAMPLE:
2856 insn = mkOp1(OP_PIXLD, TYPE_U32, (offset = getScratch()), fetchSrc(1, 0));
2857 insn->subOp = NV50_IR_SUBOP_PIXLD_OFFSET;
2858 mode |= NV50_IR_INTERP_OFFSET;
2859 break;
2860 case TGSI_OPCODE_INTERP_OFFSET: {
2861 // The input in src1.xy is float, but we need a single 32-bit value
2862 // where the upper and lower 16 bits are encoded in S0.12 format. We need
2863 // to clamp the input coordinates to (-0.5, 0.4375), multiply by 4096,
2864 // and then convert to s32.
2865 Value *offs[2];
2866 for (c = 0; c < 2; c++) {
2867 offs[c] = fetchSrc(1, c);
2868 mkOp2(OP_MIN, TYPE_F32, offs[c], offs[c], loadImm(NULL, 0.4375f));
2869 mkOp2(OP_MAX, TYPE_F32, offs[c], offs[c], loadImm(NULL, -0.5f));
2870 mkOp2(OP_MUL, TYPE_F32, offs[c], offs[c], loadImm(NULL, 4096.0f));
2871 mkCvt(OP_CVT, TYPE_S32, offs[c], TYPE_F32, offs[c]);
2872 }
2873 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
2874 offs[1], mkImm(0x1010), offs[0]);
2875 mode |= NV50_IR_INTERP_OFFSET;
2876 break;
2877 }
2878 }
2879
2880 if (op == OP_PINTERP) {
2881 if (offset) {
2882 w = mkOp2v(OP_RDSV, TYPE_F32, getSSA(), mkSysVal(SV_POSITION, 3), offset);
2883 mkOp1(OP_RCP, TYPE_F32, w, w);
2884 } else {
2885 w = fragCoord[3];
2886 }
2887 }
2888
2889
2890 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2891 insn = mkOp1(op, TYPE_F32, dst[c], sym[c] ? sym[c] : srcToSym(src, c));
2892 if (op == OP_PINTERP)
2893 insn->setSrc(1, w);
2894 if (ptr)
2895 insn->setIndirect(0, 0, ptr);
2896 if (offset)
2897 insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
2898
2899 insn->setInterpolate(mode);
2900 }
2901 }
2902
2903 Converter::Subroutine *
2904 Converter::getSubroutine(unsigned ip)
2905 {
2906 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2907
2908 if (it == sub.map.end())
2909 it = sub.map.insert(std::make_pair(
2910 ip, Subroutine(new Function(prog, "SUB", ip)))).first;
2911
2912 return &it->second;
2913 }
2914
2915 Converter::Subroutine *
2916 Converter::getSubroutine(Function *f)
2917 {
2918 unsigned ip = f->getLabel();
2919 std::map<unsigned, Subroutine>::iterator it = sub.map.find(ip);
2920
2921 if (it == sub.map.end())
2922 it = sub.map.insert(std::make_pair(ip, Subroutine(f))).first;
2923
2924 return &it->second;
2925 }
2926
2927 bool
2928 Converter::isEndOfSubroutine(uint ip)
2929 {
2930 assert(ip < code->scan.num_instructions);
2931 tgsi::Instruction insn(&code->insns[ip]);
2932 return (insn.getOpcode() == TGSI_OPCODE_END ||
2933 insn.getOpcode() == TGSI_OPCODE_ENDSUB ||
2934 // does END occur at end of main or the very end ?
2935 insn.getOpcode() == TGSI_OPCODE_BGNSUB);
2936 }
2937
2938 bool
2939 Converter::handleInstruction(const struct tgsi_full_instruction *insn)
2940 {
2941 Instruction *geni;
2942
2943 Value *dst0[4], *rDst0[4];
2944 Value *src0, *src1, *src2, *src3;
2945 Value *val0, *val1;
2946 int c;
2947
2948 tgsi = tgsi::Instruction(insn);
2949
2950 bool useScratchDst = tgsi.checkDstSrcAliasing();
2951
2952 operation op = tgsi.getOP();
2953 dstTy = tgsi.inferDstType();
2954 srcTy = tgsi.inferSrcType();
2955
2956 unsigned int mask = tgsi.dstCount() ? tgsi.getDst(0).getMask() : 0;
2957
2958 if (tgsi.dstCount()) {
2959 for (c = 0; c < 4; ++c) {
2960 rDst0[c] = acquireDst(0, c);
2961 dst0[c] = (useScratchDst && rDst0[c]) ? getScratch() : rDst0[c];
2962 }
2963 }
2964
2965 switch (tgsi.getOpcode()) {
2966 case TGSI_OPCODE_ADD:
2967 case TGSI_OPCODE_UADD:
2968 case TGSI_OPCODE_AND:
2969 case TGSI_OPCODE_DIV:
2970 case TGSI_OPCODE_IDIV:
2971 case TGSI_OPCODE_UDIV:
2972 case TGSI_OPCODE_MAX:
2973 case TGSI_OPCODE_MIN:
2974 case TGSI_OPCODE_IMAX:
2975 case TGSI_OPCODE_IMIN:
2976 case TGSI_OPCODE_UMAX:
2977 case TGSI_OPCODE_UMIN:
2978 case TGSI_OPCODE_MOD:
2979 case TGSI_OPCODE_UMOD:
2980 case TGSI_OPCODE_MUL:
2981 case TGSI_OPCODE_UMUL:
2982 case TGSI_OPCODE_IMUL_HI:
2983 case TGSI_OPCODE_UMUL_HI:
2984 case TGSI_OPCODE_OR:
2985 case TGSI_OPCODE_SHL:
2986 case TGSI_OPCODE_ISHR:
2987 case TGSI_OPCODE_USHR:
2988 case TGSI_OPCODE_SUB:
2989 case TGSI_OPCODE_XOR:
2990 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
2991 src0 = fetchSrc(0, c);
2992 src1 = fetchSrc(1, c);
2993 geni = mkOp2(op, dstTy, dst0[c], src0, src1);
2994 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
2995 }
2996 break;
2997 case TGSI_OPCODE_MAD:
2998 case TGSI_OPCODE_UMAD:
2999 case TGSI_OPCODE_SAD:
3000 case TGSI_OPCODE_FMA:
3001 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3002 src0 = fetchSrc(0, c);
3003 src1 = fetchSrc(1, c);
3004 src2 = fetchSrc(2, c);
3005 mkOp3(op, dstTy, dst0[c], src0, src1, src2);
3006 }
3007 break;
3008 case TGSI_OPCODE_MOV:
3009 case TGSI_OPCODE_ABS:
3010 case TGSI_OPCODE_CEIL:
3011 case TGSI_OPCODE_FLR:
3012 case TGSI_OPCODE_TRUNC:
3013 case TGSI_OPCODE_RCP:
3014 case TGSI_OPCODE_SQRT:
3015 case TGSI_OPCODE_IABS:
3016 case TGSI_OPCODE_INEG:
3017 case TGSI_OPCODE_NOT:
3018 case TGSI_OPCODE_DDX:
3019 case TGSI_OPCODE_DDY:
3020 case TGSI_OPCODE_DDX_FINE:
3021 case TGSI_OPCODE_DDY_FINE:
3022 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3023 mkOp1(op, dstTy, dst0[c], fetchSrc(0, c));
3024 break;
3025 case TGSI_OPCODE_RSQ:
3026 src0 = fetchSrc(0, 0);
3027 val0 = getScratch();
3028 mkOp1(OP_ABS, TYPE_F32, val0, src0);
3029 mkOp1(OP_RSQ, TYPE_F32, val0, val0);
3030 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3031 mkMov(dst0[c], val0);
3032 break;
3033 case TGSI_OPCODE_ARL:
3034 case TGSI_OPCODE_ARR:
3035 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3036 const RoundMode rnd =
3037 tgsi.getOpcode() == TGSI_OPCODE_ARR ? ROUND_N : ROUND_M;
3038 src0 = fetchSrc(0, c);
3039 mkCvt(OP_CVT, TYPE_S32, dst0[c], TYPE_F32, src0)->rnd = rnd;
3040 }
3041 break;
3042 case TGSI_OPCODE_UARL:
3043 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3044 mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
3045 break;
3046 case TGSI_OPCODE_POW:
3047 val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
3048 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3049 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3050 break;
3051 case TGSI_OPCODE_EX2:
3052 case TGSI_OPCODE_LG2:
3053 val0 = mkOp1(op, TYPE_F32, getScratch(), fetchSrc(0, 0))->getDef(0);
3054 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3055 mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
3056 break;
3057 case TGSI_OPCODE_COS:
3058 case TGSI_OPCODE_SIN:
3059 val0 = getScratch();
3060 if (mask & 7) {
3061 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 0));
3062 mkOp1(op, TYPE_F32, val0, val0);
3063 for (c = 0; c < 3; ++c)
3064 if (dst0[c])
3065 mkMov(dst0[c], val0);
3066 }
3067 if (dst0[3]) {
3068 mkOp1(OP_PRESIN, TYPE_F32, val0, fetchSrc(0, 3));
3069 mkOp1(op, TYPE_F32, dst0[3], val0);
3070 }
3071 break;
3072 case TGSI_OPCODE_SCS:
3073 if (mask & 3) {
3074 val0 = mkOp1v(OP_PRESIN, TYPE_F32, getSSA(), fetchSrc(0, 0));
3075 if (dst0[0])
3076 mkOp1(OP_COS, TYPE_F32, dst0[0], val0);
3077 if (dst0[1])
3078 mkOp1(OP_SIN, TYPE_F32, dst0[1], val0);
3079 }
3080 if (dst0[2])
3081 loadImm(dst0[2], 0.0f);
3082 if (dst0[3])
3083 loadImm(dst0[3], 1.0f);
3084 break;
3085 case TGSI_OPCODE_EXP:
3086 src0 = fetchSrc(0, 0);
3087 val0 = mkOp1v(OP_FLOOR, TYPE_F32, getSSA(), src0);
3088 if (dst0[1])
3089 mkOp2(OP_SUB, TYPE_F32, dst0[1], src0, val0);
3090 if (dst0[0])
3091 mkOp1(OP_EX2, TYPE_F32, dst0[0], val0);
3092 if (dst0[2])
3093 mkOp1(OP_EX2, TYPE_F32, dst0[2], src0);
3094 if (dst0[3])
3095 loadImm(dst0[3], 1.0f);
3096 break;
3097 case TGSI_OPCODE_LOG:
3098 src0 = mkOp1v(OP_ABS, TYPE_F32, getSSA(), fetchSrc(0, 0));
3099 val0 = mkOp1v(OP_LG2, TYPE_F32, dst0[2] ? dst0[2] : getSSA(), src0);
3100 if (dst0[0] || dst0[1])
3101 val1 = mkOp1v(OP_FLOOR, TYPE_F32, dst0[0] ? dst0[0] : getSSA(), val0);
3102 if (dst0[1]) {
3103 mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
3104 mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
3105 mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
3106 }
3107 if (dst0[3])
3108 loadImm(dst0[3], 1.0f);
3109 break;
3110 case TGSI_OPCODE_DP2:
3111 val0 = buildDot(2);
3112 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3113 mkMov(dst0[c], val0);
3114 break;
3115 case TGSI_OPCODE_DP3:
3116 val0 = buildDot(3);
3117 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3118 mkMov(dst0[c], val0);
3119 break;
3120 case TGSI_OPCODE_DP4:
3121 val0 = buildDot(4);
3122 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3123 mkMov(dst0[c], val0);
3124 break;
3125 case TGSI_OPCODE_DPH:
3126 val0 = buildDot(3);
3127 src1 = fetchSrc(1, 3);
3128 mkOp2(OP_ADD, TYPE_F32, val0, val0, src1);
3129 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3130 mkMov(dst0[c], val0);
3131 break;
3132 case TGSI_OPCODE_DST:
3133 if (dst0[0])
3134 loadImm(dst0[0], 1.0f);
3135 if (dst0[1]) {
3136 src0 = fetchSrc(0, 1);
3137 src1 = fetchSrc(1, 1);
3138 mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
3139 }
3140 if (dst0[2])
3141 mkMov(dst0[2], fetchSrc(0, 2));
3142 if (dst0[3])
3143 mkMov(dst0[3], fetchSrc(1, 3));
3144 break;
3145 case TGSI_OPCODE_LRP:
3146 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3147 src0 = fetchSrc(0, c);
3148 src1 = fetchSrc(1, c);
3149 src2 = fetchSrc(2, c);
3150 mkOp3(OP_MAD, TYPE_F32, dst0[c],
3151 mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
3152 }
3153 break;
3154 case TGSI_OPCODE_LIT:
3155 handleLIT(dst0);
3156 break;
3157 case TGSI_OPCODE_XPD:
3158 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3159 if (c < 3) {
3160 val0 = getSSA();
3161 src0 = fetchSrc(1, (c + 1) % 3);
3162 src1 = fetchSrc(0, (c + 2) % 3);
3163 mkOp2(OP_MUL, TYPE_F32, val0, src0, src1);
3164 mkOp1(OP_NEG, TYPE_F32, val0, val0);
3165
3166 src0 = fetchSrc(0, (c + 1) % 3);
3167 src1 = fetchSrc(1, (c + 2) % 3);
3168 mkOp3(OP_MAD, TYPE_F32, dst0[c], src0, src1, val0);
3169 } else {
3170 loadImm(dst0[c], 1.0f);
3171 }
3172 }
3173 break;
3174 case TGSI_OPCODE_ISSG:
3175 case TGSI_OPCODE_SSG:
3176 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3177 src0 = fetchSrc(0, c);
3178 val0 = getScratch();
3179 val1 = getScratch();
3180 mkCmp(OP_SET, CC_GT, srcTy, val0, srcTy, src0, zero);
3181 mkCmp(OP_SET, CC_LT, srcTy, val1, srcTy, src0, zero);
3182 if (srcTy == TYPE_F32)
3183 mkOp2(OP_SUB, TYPE_F32, dst0[c], val0, val1);
3184 else
3185 mkOp2(OP_SUB, TYPE_S32, dst0[c], val1, val0);
3186 }
3187 break;
3188 case TGSI_OPCODE_UCMP:
3189 srcTy = TYPE_U32;
3190 /* fallthrough */
3191 case TGSI_OPCODE_CMP:
3192 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3193 src0 = fetchSrc(0, c);
3194 src1 = fetchSrc(1, c);
3195 src2 = fetchSrc(2, c);
3196 if (src1 == src2)
3197 mkMov(dst0[c], src1);
3198 else
3199 mkCmp(OP_SLCT, (srcTy == TYPE_F32) ? CC_LT : CC_NE,
3200 srcTy, dst0[c], srcTy, src1, src2, src0);
3201 }
3202 break;
3203 case TGSI_OPCODE_FRC:
3204 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3205 src0 = fetchSrc(0, c);
3206 val0 = getScratch();
3207 mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
3208 mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
3209 }
3210 break;
3211 case TGSI_OPCODE_ROUND:
3212 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3213 mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F32, fetchSrc(0, c))
3214 ->rnd = ROUND_NI;
3215 break;
3216 case TGSI_OPCODE_CLAMP:
3217 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3218 src0 = fetchSrc(0, c);
3219 src1 = fetchSrc(1, c);
3220 src2 = fetchSrc(2, c);
3221 val0 = getScratch();
3222 mkOp2(OP_MIN, TYPE_F32, val0, src0, src1);
3223 mkOp2(OP_MAX, TYPE_F32, dst0[c], val0, src2);
3224 }
3225 break;
3226 case TGSI_OPCODE_SLT:
3227 case TGSI_OPCODE_SGE:
3228 case TGSI_OPCODE_SEQ:
3229 case TGSI_OPCODE_SGT:
3230 case TGSI_OPCODE_SLE:
3231 case TGSI_OPCODE_SNE:
3232 case TGSI_OPCODE_FSEQ:
3233 case TGSI_OPCODE_FSGE:
3234 case TGSI_OPCODE_FSLT:
3235 case TGSI_OPCODE_FSNE:
3236 case TGSI_OPCODE_ISGE:
3237 case TGSI_OPCODE_ISLT:
3238 case TGSI_OPCODE_USEQ:
3239 case TGSI_OPCODE_USGE:
3240 case TGSI_OPCODE_USLT:
3241 case TGSI_OPCODE_USNE:
3242 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3243 src0 = fetchSrc(0, c);
3244 src1 = fetchSrc(1, c);
3245 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3246 }
3247 break;
3248 case TGSI_OPCODE_VOTE_ALL:
3249 case TGSI_OPCODE_VOTE_ANY:
3250 case TGSI_OPCODE_VOTE_EQ:
3251 val0 = new_LValue(func, FILE_PREDICATE);
3252 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3253 mkCmp(OP_SET, CC_NE, TYPE_U32, val0, TYPE_U32, fetchSrc(0, c), zero);
3254 mkOp1(op, dstTy, val0, val0)
3255 ->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3256 mkCvt(OP_CVT, TYPE_U32, dst0[c], TYPE_U8, val0);
3257 }
3258 break;
3259 case TGSI_OPCODE_KILL_IF:
3260 val0 = new_LValue(func, FILE_PREDICATE);
3261 mask = 0;
3262 for (c = 0; c < 4; ++c) {
3263 const int s = tgsi.getSrc(0).getSwizzle(c);
3264 if (mask & (1 << s))
3265 continue;
3266 mask |= 1 << s;
3267 mkCmp(OP_SET, CC_LT, TYPE_F32, val0, TYPE_F32, fetchSrc(0, c), zero);
3268 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_P, val0);
3269 }
3270 break;
3271 case TGSI_OPCODE_KILL:
3272 mkOp(OP_DISCARD, TYPE_NONE, NULL);
3273 break;
3274 case TGSI_OPCODE_TEX:
3275 case TGSI_OPCODE_TXB:
3276 case TGSI_OPCODE_TXL:
3277 case TGSI_OPCODE_TXP:
3278 case TGSI_OPCODE_LODQ:
3279 // R S L C Dx Dy
3280 handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
3281 break;
3282 case TGSI_OPCODE_TXD:
3283 handleTEX(dst0, 3, 3, 0x03, 0x0f, 0x10, 0x20);
3284 break;
3285 case TGSI_OPCODE_TG4:
3286 handleTEX(dst0, 2, 2, 0x03, 0x0f, 0x00, 0x00);
3287 break;
3288 case TGSI_OPCODE_TEX2:
3289 handleTEX(dst0, 2, 2, 0x03, 0x10, 0x00, 0x00);
3290 break;
3291 case TGSI_OPCODE_TXB2:
3292 case TGSI_OPCODE_TXL2:
3293 handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
3294 break;
3295 case TGSI_OPCODE_SAMPLE:
3296 case TGSI_OPCODE_SAMPLE_B:
3297 case TGSI_OPCODE_SAMPLE_D:
3298 case TGSI_OPCODE_SAMPLE_L:
3299 case TGSI_OPCODE_SAMPLE_C:
3300 case TGSI_OPCODE_SAMPLE_C_LZ:
3301 handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
3302 break;
3303 case TGSI_OPCODE_TXF:
3304 handleTXF(dst0, 1, 0x03);
3305 break;
3306 case TGSI_OPCODE_SAMPLE_I:
3307 handleTXF(dst0, 1, 0x03);
3308 break;
3309 case TGSI_OPCODE_SAMPLE_I_MS:
3310 handleTXF(dst0, 1, 0x20);
3311 break;
3312 case TGSI_OPCODE_TXQ:
3313 case TGSI_OPCODE_SVIEWINFO:
3314 handleTXQ(dst0, TXQ_DIMS, 1);
3315 break;
3316 case TGSI_OPCODE_TXQS:
3317 // The TXQ_TYPE query returns samples in its 3rd arg, but we need it to
3318 // be in .x
3319 dst0[1] = dst0[2] = dst0[3] = NULL;
3320 std::swap(dst0[0], dst0[2]);
3321 handleTXQ(dst0, TXQ_TYPE, 0);
3322 std::swap(dst0[0], dst0[2]);
3323 break;
3324 case TGSI_OPCODE_F2I:
3325 case TGSI_OPCODE_F2U:
3326 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3327 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c))->rnd = ROUND_Z;
3328 break;
3329 case TGSI_OPCODE_I2F:
3330 case TGSI_OPCODE_U2F:
3331 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3332 mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
3333 break;
3334 case TGSI_OPCODE_PK2H:
3335 val0 = getScratch();
3336 val1 = getScratch();
3337 mkCvt(OP_CVT, TYPE_F16, val0, TYPE_F32, fetchSrc(0, 0));
3338 mkCvt(OP_CVT, TYPE_F16, val1, TYPE_F32, fetchSrc(0, 1));
3339 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
3340 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3341 break;
3342 case TGSI_OPCODE_UP2H:
3343 src0 = fetchSrc(0, 0);
3344 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3345 geni = mkCvt(OP_CVT, TYPE_F32, dst0[c], TYPE_F16, src0);
3346 geni->subOp = c & 1;
3347 }
3348 break;
3349 case TGSI_OPCODE_EMIT:
3350 /* export the saved viewport index */
3351 if (viewport != NULL) {
3352 Symbol *vpSym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_U32,
3353 info->out[info->io.viewportId].slot[0] * 4);
3354 mkStore(OP_EXPORT, TYPE_U32, vpSym, NULL, viewport);
3355 }
3356 /* fallthrough */
3357 case TGSI_OPCODE_ENDPRIM:
3358 {
3359 // get vertex stream (must be immediate)
3360 unsigned int stream = tgsi.getSrc(0).getValueU32(0, info);
3361 if (stream && op == OP_RESTART)
3362 break;
3363 if (info->prop.gp.maxVertices == 0)
3364 break;
3365 src0 = mkImm(stream);
3366 mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
3367 break;
3368 }
3369 case TGSI_OPCODE_IF:
3370 case TGSI_OPCODE_UIF:
3371 {
3372 BasicBlock *ifBB = new BasicBlock(func);
3373
3374 bb->cfg.attach(&ifBB->cfg, Graph::Edge::TREE);
3375 condBBs.push(bb);
3376 joinBBs.push(bb);
3377
3378 mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
3379
3380 setPosition(ifBB, true);
3381 }
3382 break;
3383 case TGSI_OPCODE_ELSE:
3384 {
3385 BasicBlock *elseBB = new BasicBlock(func);
3386 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3387
3388 forkBB->cfg.attach(&elseBB->cfg, Graph::Edge::TREE);
3389 condBBs.push(bb);
3390
3391 forkBB->getExit()->asFlow()->target.bb = elseBB;
3392 if (!bb->isTerminated())
3393 mkFlow(OP_BRA, NULL, CC_ALWAYS, NULL);
3394
3395 setPosition(elseBB, true);
3396 }
3397 break;
3398 case TGSI_OPCODE_ENDIF:
3399 {
3400 BasicBlock *convBB = new BasicBlock(func);
3401 BasicBlock *prevBB = reinterpret_cast<BasicBlock *>(condBBs.pop().u.p);
3402 BasicBlock *forkBB = reinterpret_cast<BasicBlock *>(joinBBs.pop().u.p);
3403
3404 if (!bb->isTerminated()) {
3405 // we only want join if none of the clauses ended with CONT/BREAK/RET
3406 if (prevBB->getExit()->op == OP_BRA && joinBBs.getSize() < 6)
3407 insertConvergenceOps(convBB, forkBB);
3408 mkFlow(OP_BRA, convBB, CC_ALWAYS, NULL);
3409 bb->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3410 }
3411
3412 if (prevBB->getExit()->op == OP_BRA) {
3413 prevBB->cfg.attach(&convBB->cfg, Graph::Edge::FORWARD);
3414 prevBB->getExit()->asFlow()->target.bb = convBB;
3415 }
3416 setPosition(convBB, true);
3417 }
3418 break;
3419 case TGSI_OPCODE_BGNLOOP:
3420 {
3421 BasicBlock *lbgnBB = new BasicBlock(func);
3422 BasicBlock *lbrkBB = new BasicBlock(func);
3423
3424 loopBBs.push(lbgnBB);
3425 breakBBs.push(lbrkBB);
3426 if (loopBBs.getSize() > func->loopNestingBound)
3427 func->loopNestingBound++;
3428
3429 mkFlow(OP_PREBREAK, lbrkBB, CC_ALWAYS, NULL);
3430
3431 bb->cfg.attach(&lbgnBB->cfg, Graph::Edge::TREE);
3432 setPosition(lbgnBB, true);
3433 mkFlow(OP_PRECONT, lbgnBB, CC_ALWAYS, NULL);
3434 }
3435 break;
3436 case TGSI_OPCODE_ENDLOOP:
3437 {
3438 BasicBlock *loopBB = reinterpret_cast<BasicBlock *>(loopBBs.pop().u.p);
3439
3440 if (!bb->isTerminated()) {
3441 mkFlow(OP_CONT, loopBB, CC_ALWAYS, NULL);
3442 bb->cfg.attach(&loopBB->cfg, Graph::Edge::BACK);
3443 }
3444 setPosition(reinterpret_cast<BasicBlock *>(breakBBs.pop().u.p), true);
3445
3446 // If the loop never breaks (e.g. only has RET's inside), then there
3447 // will be no way to get to the break bb. However BGNLOOP will have
3448 // already made a PREBREAK to it, so it must be in the CFG.
3449 if (getBB()->cfg.incidentCount() == 0)
3450 loopBB->cfg.attach(&getBB()->cfg, Graph::Edge::TREE);
3451 }
3452 break;
3453 case TGSI_OPCODE_BRK:
3454 {
3455 if (bb->isTerminated())
3456 break;
3457 BasicBlock *brkBB = reinterpret_cast<BasicBlock *>(breakBBs.peek().u.p);
3458 mkFlow(OP_BREAK, brkBB, CC_ALWAYS, NULL);
3459 bb->cfg.attach(&brkBB->cfg, Graph::Edge::CROSS);
3460 }
3461 break;
3462 case TGSI_OPCODE_CONT:
3463 {
3464 if (bb->isTerminated())
3465 break;
3466 BasicBlock *contBB = reinterpret_cast<BasicBlock *>(loopBBs.peek().u.p);
3467 mkFlow(OP_CONT, contBB, CC_ALWAYS, NULL);
3468 contBB->explicitCont = true;
3469 bb->cfg.attach(&contBB->cfg, Graph::Edge::BACK);
3470 }
3471 break;
3472 case TGSI_OPCODE_BGNSUB:
3473 {
3474 Subroutine *s = getSubroutine(ip);
3475 BasicBlock *entry = new BasicBlock(s->f);
3476 BasicBlock *leave = new BasicBlock(s->f);
3477
3478 // multiple entrypoints possible, keep the graph connected
3479 if (prog->getType() == Program::TYPE_COMPUTE)
3480 prog->main->call.attach(&s->f->call, Graph::Edge::TREE);
3481
3482 sub.cur = s;
3483 s->f->setEntry(entry);
3484 s->f->setExit(leave);
3485 setPosition(entry, true);
3486 return true;
3487 }
3488 case TGSI_OPCODE_ENDSUB:
3489 {
3490 sub.cur = getSubroutine(prog->main);
3491 setPosition(BasicBlock::get(sub.cur->f->cfg.getRoot()), true);
3492 return true;
3493 }
3494 case TGSI_OPCODE_CAL:
3495 {
3496 Subroutine *s = getSubroutine(tgsi.getLabel());
3497 mkFlow(OP_CALL, s->f, CC_ALWAYS, NULL);
3498 func->call.attach(&s->f->call, Graph::Edge::TREE);
3499 return true;
3500 }
3501 case TGSI_OPCODE_RET:
3502 {
3503 if (bb->isTerminated())
3504 return true;
3505 BasicBlock *leave = BasicBlock::get(func->cfgExit);
3506
3507 if (!isEndOfSubroutine(ip + 1)) {
3508 // insert a PRERET at the entry if this is an early return
3509 // (only needed for sharing code in the epilogue)
3510 BasicBlock *root = BasicBlock::get(func->cfg.getRoot());
3511 if (root->getEntry() == NULL || root->getEntry()->op != OP_PRERET) {
3512 BasicBlock *pos = getBB();
3513 setPosition(root, false);
3514 mkFlow(OP_PRERET, leave, CC_ALWAYS, NULL)->fixed = 1;
3515 setPosition(pos, true);
3516 }
3517 }
3518 mkFlow(OP_RET, NULL, CC_ALWAYS, NULL)->fixed = 1;
3519 bb->cfg.attach(&leave->cfg, Graph::Edge::CROSS);
3520 }
3521 break;
3522 case TGSI_OPCODE_END:
3523 {
3524 // attach and generate epilogue code
3525 BasicBlock *epilogue = BasicBlock::get(func->cfgExit);
3526 bb->cfg.attach(&epilogue->cfg, Graph::Edge::TREE);
3527 setPosition(epilogue, true);
3528 if (prog->getType() == Program::TYPE_FRAGMENT)
3529 exportOutputs();
3530 if (info->io.genUserClip > 0)
3531 handleUserClipPlanes();
3532 mkOp(OP_EXIT, TYPE_NONE, NULL)->terminator = 1;
3533 }
3534 break;
3535 case TGSI_OPCODE_SWITCH:
3536 case TGSI_OPCODE_CASE:
3537 ERROR("switch/case opcode encountered, should have been lowered\n");
3538 abort();
3539 break;
3540 case TGSI_OPCODE_LOAD:
3541 handleLOAD(dst0);
3542 break;
3543 case TGSI_OPCODE_STORE:
3544 handleSTORE();
3545 break;
3546 case TGSI_OPCODE_BARRIER:
3547 geni = mkOp2(OP_BAR, TYPE_U32, NULL, mkImm(0), mkImm(0));
3548 geni->fixed = 1;
3549 geni->subOp = NV50_IR_SUBOP_BAR_SYNC;
3550 break;
3551 case TGSI_OPCODE_MFENCE:
3552 case TGSI_OPCODE_LFENCE:
3553 case TGSI_OPCODE_SFENCE:
3554 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3555 geni->fixed = 1;
3556 geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
3557 break;
3558 case TGSI_OPCODE_MEMBAR:
3559 geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
3560 geni->fixed = 1;
3561 if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
3562 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
3563 else
3564 geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
3565 break;
3566 case TGSI_OPCODE_ATOMUADD:
3567 case TGSI_OPCODE_ATOMXCHG:
3568 case TGSI_OPCODE_ATOMCAS:
3569 case TGSI_OPCODE_ATOMAND:
3570 case TGSI_OPCODE_ATOMOR:
3571 case TGSI_OPCODE_ATOMXOR:
3572 case TGSI_OPCODE_ATOMUMIN:
3573 case TGSI_OPCODE_ATOMIMIN:
3574 case TGSI_OPCODE_ATOMUMAX:
3575 case TGSI_OPCODE_ATOMIMAX:
3576 handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
3577 break;
3578 case TGSI_OPCODE_RESQ:
3579 if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER) {
3580 geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
3581 makeSym(tgsi.getSrc(0).getFile(),
3582 tgsi.getSrc(0).getIndex(0), -1, 0, 0));
3583 if (tgsi.getSrc(0).isIndirect(0))
3584 geni->setIndirect(0, 1,
3585 fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
3586 } else {
3587 assert(tgsi.getSrc(0).getFile() == TGSI_FILE_IMAGE);
3588
3589 TexInstruction *texi = new_TexInstruction(func, OP_SUQ);
3590 for (int c = 0, d = 0; c < 4; ++c) {
3591 if (dst0[c]) {
3592 texi->setDef(d++, dst0[c]);
3593 texi->tex.mask |= 1 << c;
3594 }
3595 }
3596 texi->tex.r = tgsi.getSrc(0).getIndex(0);
3597 texi->tex.target = getImageTarget(code, texi->tex.r);
3598 bb->insertTail(texi);
3599
3600 if (tgsi.getSrc(0).isIndirect(0))
3601 texi->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
3602 }
3603 break;
3604 case TGSI_OPCODE_IBFE:
3605 case TGSI_OPCODE_UBFE:
3606 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3607 src0 = fetchSrc(0, c);
3608 if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
3609 tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
3610 src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
3611 tgsi.getSrc(1).getValueU32(c, info));
3612 } else {
3613 src1 = fetchSrc(1, c);
3614 src2 = fetchSrc(2, c);
3615 mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
3616 }
3617 mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
3618 }
3619 break;
3620 case TGSI_OPCODE_BFI:
3621 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3622 src0 = fetchSrc(0, c);
3623 src1 = fetchSrc(1, c);
3624 src2 = fetchSrc(2, c);
3625 src3 = fetchSrc(3, c);
3626 mkOp3(OP_INSBF, TYPE_U32, src2, src3, mkImm(0x808), src2);
3627 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, src2, src0);
3628 }
3629 break;
3630 case TGSI_OPCODE_LSB:
3631 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3632 src0 = fetchSrc(0, c);
3633 geni = mkOp2(OP_EXTBF, TYPE_U32, src0, src0, mkImm(0x2000));
3634 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3635 geni = mkOp1(OP_BFIND, TYPE_U32, dst0[c], src0);
3636 geni->subOp = NV50_IR_SUBOP_BFIND_SAMT;
3637 }
3638 break;
3639 case TGSI_OPCODE_IMSB:
3640 case TGSI_OPCODE_UMSB:
3641 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3642 src0 = fetchSrc(0, c);
3643 mkOp1(OP_BFIND, srcTy, dst0[c], src0);
3644 }
3645 break;
3646 case TGSI_OPCODE_BREV:
3647 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3648 src0 = fetchSrc(0, c);
3649 geni = mkOp2(OP_EXTBF, TYPE_U32, dst0[c], src0, mkImm(0x2000));
3650 geni->subOp = NV50_IR_SUBOP_EXTBF_REV;
3651 }
3652 break;
3653 case TGSI_OPCODE_POPC:
3654 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3655 src0 = fetchSrc(0, c);
3656 mkOp2(OP_POPCNT, TYPE_U32, dst0[c], src0, src0);
3657 }
3658 break;
3659 case TGSI_OPCODE_INTERP_CENTROID:
3660 case TGSI_OPCODE_INTERP_SAMPLE:
3661 case TGSI_OPCODE_INTERP_OFFSET:
3662 handleINTERP(dst0);
3663 break;
3664 case TGSI_OPCODE_D2I:
3665 case TGSI_OPCODE_D2U:
3666 case TGSI_OPCODE_D2F: {
3667 int pos = 0;
3668 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3669 Value *dreg = getSSA(8);
3670 src0 = fetchSrc(0, pos);
3671 src1 = fetchSrc(0, pos + 1);
3672 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
3673 Instruction *cvt = mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
3674 if (!isFloatType(dstTy))
3675 cvt->rnd = ROUND_Z;
3676 pos += 2;
3677 }
3678 break;
3679 }
3680 case TGSI_OPCODE_I2D:
3681 case TGSI_OPCODE_U2D:
3682 case TGSI_OPCODE_F2D:
3683 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3684 Value *dreg = getSSA(8);
3685 mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
3686 mkSplit(&dst0[c], 4, dreg);
3687 c++;
3688 }
3689 break;
3690 case TGSI_OPCODE_DABS:
3691 case TGSI_OPCODE_DNEG:
3692 case TGSI_OPCODE_DRCP:
3693 case TGSI_OPCODE_DSQRT:
3694 case TGSI_OPCODE_DRSQ:
3695 case TGSI_OPCODE_DTRUNC:
3696 case TGSI_OPCODE_DCEIL:
3697 case TGSI_OPCODE_DFLR:
3698 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3699 src0 = getSSA(8);
3700 Value *dst = getSSA(8), *tmp[2];
3701 tmp[0] = fetchSrc(0, c);
3702 tmp[1] = fetchSrc(0, c + 1);
3703 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3704 mkOp1(op, dstTy, dst, src0);
3705 mkSplit(&dst0[c], 4, dst);
3706 c++;
3707 }
3708 break;
3709 case TGSI_OPCODE_DFRAC:
3710 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3711 src0 = getSSA(8);
3712 Value *dst = getSSA(8), *tmp[2];
3713 tmp[0] = fetchSrc(0, c);
3714 tmp[1] = fetchSrc(0, c + 1);
3715 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3716 mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
3717 mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
3718 mkSplit(&dst0[c], 4, dst);
3719 c++;
3720 }
3721 break;
3722 case TGSI_OPCODE_DSLT:
3723 case TGSI_OPCODE_DSGE:
3724 case TGSI_OPCODE_DSEQ:
3725 case TGSI_OPCODE_DSNE: {
3726 int pos = 0;
3727 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3728 Value *tmp[2];
3729
3730 src0 = getSSA(8);
3731 src1 = getSSA(8);
3732 tmp[0] = fetchSrc(0, pos);
3733 tmp[1] = fetchSrc(0, pos + 1);
3734 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3735 tmp[0] = fetchSrc(1, pos);
3736 tmp[1] = fetchSrc(1, pos + 1);
3737 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3738 mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
3739 pos += 2;
3740 }
3741 break;
3742 }
3743 case TGSI_OPCODE_DADD:
3744 case TGSI_OPCODE_DMUL:
3745 case TGSI_OPCODE_DMAX:
3746 case TGSI_OPCODE_DMIN:
3747 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3748 src0 = getSSA(8);
3749 src1 = getSSA(8);
3750 Value *dst = getSSA(8), *tmp[2];
3751 tmp[0] = fetchSrc(0, c);
3752 tmp[1] = fetchSrc(0, c + 1);
3753 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3754 tmp[0] = fetchSrc(1, c);
3755 tmp[1] = fetchSrc(1, c + 1);
3756 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3757 mkOp2(op, dstTy, dst, src0, src1);
3758 mkSplit(&dst0[c], 4, dst);
3759 c++;
3760 }
3761 break;
3762 case TGSI_OPCODE_DMAD:
3763 case TGSI_OPCODE_DFMA:
3764 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3765 src0 = getSSA(8);
3766 src1 = getSSA(8);
3767 src2 = getSSA(8);
3768 Value *dst = getSSA(8), *tmp[2];
3769 tmp[0] = fetchSrc(0, c);
3770 tmp[1] = fetchSrc(0, c + 1);
3771 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3772 tmp[0] = fetchSrc(1, c);
3773 tmp[1] = fetchSrc(1, c + 1);
3774 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
3775 tmp[0] = fetchSrc(2, c);
3776 tmp[1] = fetchSrc(2, c + 1);
3777 mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
3778 mkOp3(op, dstTy, dst, src0, src1, src2);
3779 mkSplit(&dst0[c], 4, dst);
3780 c++;
3781 }
3782 break;
3783 case TGSI_OPCODE_DROUND:
3784 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3785 src0 = getSSA(8);
3786 Value *dst = getSSA(8), *tmp[2];
3787 tmp[0] = fetchSrc(0, c);
3788 tmp[1] = fetchSrc(0, c + 1);
3789 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3790 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
3791 ->rnd = ROUND_NI;
3792 mkSplit(&dst0[c], 4, dst);
3793 c++;
3794 }
3795 break;
3796 case TGSI_OPCODE_DSSG:
3797 FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
3798 src0 = getSSA(8);
3799 Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
3800 tmp[0] = fetchSrc(0, c);
3801 tmp[1] = fetchSrc(0, c + 1);
3802 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
3803
3804 val0 = getScratch();
3805 val1 = getScratch();
3806 // The zero is wrong here since it's only 32-bit, but it works out in
3807 // the end since it gets replaced with $r63.
3808 mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
3809 mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
3810 mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
3811 mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
3812 mkSplit(&dst0[c], 4, dst);
3813 c++;
3814 }
3815 break;
3816 default:
3817 ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
3818 assert(0);
3819 break;
3820 }
3821
3822 if (tgsi.dstCount()) {
3823 for (c = 0; c < 4; ++c) {
3824 if (!dst0[c])
3825 continue;
3826 if (dst0[c] != rDst0[c])
3827 mkMov(rDst0[c], dst0[c]);
3828 storeDst(0, c, rDst0[c]);
3829 }
3830 }
3831 vtxBaseValid = 0;
3832
3833 return true;
3834 }
3835
3836 void
3837 Converter::handleUserClipPlanes()
3838 {
3839 Value *res[8];
3840 int n, i, c;
3841
3842 for (c = 0; c < 4; ++c) {
3843 for (i = 0; i < info->io.genUserClip; ++i) {
3844 Symbol *sym = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3845 TYPE_F32, info->io.ucpBase + i * 16 + c * 4);
3846 Value *ucp = mkLoadv(TYPE_F32, sym, NULL);
3847 if (c == 0)
3848 res[i] = mkOp2v(OP_MUL, TYPE_F32, getScratch(), clipVtx[c], ucp);
3849 else
3850 mkOp3(OP_MAD, TYPE_F32, res[i], clipVtx[c], ucp, res[i]);
3851 }
3852 }
3853
3854 const int first = info->numOutputs - (info->io.genUserClip + 3) / 4;
3855
3856 for (i = 0; i < info->io.genUserClip; ++i) {
3857 n = i / 4 + first;
3858 c = i % 4;
3859 Symbol *sym =
3860 mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32, info->out[n].slot[c] * 4);
3861 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, res[i]);
3862 }
3863 }
3864
3865 void
3866 Converter::exportOutputs()
3867 {
3868 if (info->io.alphaRefBase) {
3869 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3870 if (info->out[i].sn != TGSI_SEMANTIC_COLOR ||
3871 info->out[i].si != 0)
3872 continue;
3873 const unsigned int c = 3;
3874 if (!oData.exists(sub.cur->values, i, c))
3875 continue;
3876 Value *val = oData.load(sub.cur->values, i, c, NULL);
3877 if (!val)
3878 continue;
3879
3880 Symbol *ref = mkSymbol(FILE_MEMORY_CONST, info->io.auxCBSlot,
3881 TYPE_U32, info->io.alphaRefBase);
3882 Value *pred = new_LValue(func, FILE_PREDICATE);
3883 mkCmp(OP_SET, CC_TR, TYPE_U32, pred, TYPE_F32, val,
3884 mkLoadv(TYPE_U32, ref, NULL))
3885 ->subOp = 1;
3886 mkOp(OP_DISCARD, TYPE_NONE, NULL)->setPredicate(CC_NOT_P, pred);
3887 }
3888 }
3889
3890 for (unsigned int i = 0; i < info->numOutputs; ++i) {
3891 for (unsigned int c = 0; c < 4; ++c) {
3892 if (!oData.exists(sub.cur->values, i, c))
3893 continue;
3894 Symbol *sym = mkSymbol(FILE_SHADER_OUTPUT, 0, TYPE_F32,
3895 info->out[i].slot[c] * 4);
3896 Value *val = oData.load(sub.cur->values, i, c, NULL);
3897 if (val) {
3898 if (info->out[i].sn == TGSI_SEMANTIC_POSITION)
3899 mkOp1(OP_SAT, TYPE_F32, val, val);
3900 mkStore(OP_EXPORT, TYPE_F32, sym, NULL, val);
3901 }
3902 }
3903 }
3904 }
3905
3906 Converter::Converter(Program *ir, const tgsi::Source *code) : BuildUtil(ir),
3907 code(code),
3908 tgsi(NULL),
3909 tData(this), lData(this), aData(this), pData(this), oData(this)
3910 {
3911 info = code->info;
3912
3913 const unsigned tSize = code->fileSize(TGSI_FILE_TEMPORARY);
3914 const unsigned pSize = code->fileSize(TGSI_FILE_PREDICATE);
3915 const unsigned aSize = code->fileSize(TGSI_FILE_ADDRESS);
3916 const unsigned oSize = code->fileSize(TGSI_FILE_OUTPUT);
3917
3918 tData.setup(TGSI_FILE_TEMPORARY, 0, 0, tSize, 4, 4, FILE_GPR, 0);
3919 lData.setup(TGSI_FILE_TEMPORARY, 1, 0, tSize, 4, 4, FILE_MEMORY_LOCAL, 0);
3920 pData.setup(TGSI_FILE_PREDICATE, 0, 0, pSize, 4, 4, FILE_PREDICATE, 0);
3921 aData.setup(TGSI_FILE_ADDRESS, 0, 0, aSize, 4, 4, FILE_GPR, 0);
3922 oData.setup(TGSI_FILE_OUTPUT, 0, 0, oSize, 4, 4, FILE_GPR, 0);
3923
3924 zero = mkImm((uint32_t)0);
3925
3926 vtxBaseValid = 0;
3927 }
3928
3929 Converter::~Converter()
3930 {
3931 }
3932
3933 inline const Converter::Location *
3934 Converter::BindArgumentsPass::getValueLocation(Subroutine *s, Value *v)
3935 {
3936 ValueMap::l_iterator it = s->values.l.find(v);
3937 return it == s->values.l.end() ? NULL : &it->second;
3938 }
3939
3940 template<typename T> inline void
3941 Converter::BindArgumentsPass::updateCallArgs(
3942 Instruction *i, void (Instruction::*setArg)(int, Value *),
3943 T (Function::*proto))
3944 {
3945 Function *g = i->asFlow()->target.fn;
3946 Subroutine *subg = conv.getSubroutine(g);
3947
3948 for (unsigned a = 0; a < (g->*proto).size(); ++a) {
3949 Value *v = (g->*proto)[a].get();
3950 const Converter::Location &l = *getValueLocation(subg, v);
3951 Converter::DataArray *array = conv.getArrayForFile(l.array, l.arrayIdx);
3952
3953 (i->*setArg)(a, array->acquire(sub->values, l.i, l.c));
3954 }
3955 }
3956
3957 template<typename T> inline void
3958 Converter::BindArgumentsPass::updatePrototype(
3959 BitSet *set, void (Function::*updateSet)(), T (Function::*proto))
3960 {
3961 (func->*updateSet)();
3962
3963 for (unsigned i = 0; i < set->getSize(); ++i) {
3964 Value *v = func->getLValue(i);
3965 const Converter::Location *l = getValueLocation(sub, v);
3966
3967 // only include values with a matching TGSI register
3968 if (set->test(i) && l && !conv.code->locals.count(*l))
3969 (func->*proto).push_back(v);
3970 }
3971 }
3972
3973 bool
3974 Converter::BindArgumentsPass::visit(Function *f)
3975 {
3976 sub = conv.getSubroutine(f);
3977
3978 for (ArrayList::Iterator bi = f->allBBlocks.iterator();
3979 !bi.end(); bi.next()) {
3980 for (Instruction *i = BasicBlock::get(bi)->getFirst();
3981 i; i = i->next) {
3982 if (i->op == OP_CALL && !i->asFlow()->builtin) {
3983 updateCallArgs(i, &Instruction::setSrc, &Function::ins);
3984 updateCallArgs(i, &Instruction::setDef, &Function::outs);
3985 }
3986 }
3987 }
3988
3989 if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE)
3990 return true;
3991 updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet,
3992 &Function::buildLiveSets, &Function::ins);
3993 updatePrototype(&BasicBlock::get(f->cfgExit)->defSet,
3994 &Function::buildDefSets, &Function::outs);
3995
3996 return true;
3997 }
3998
3999 bool
4000 Converter::run()
4001 {
4002 BasicBlock *entry = new BasicBlock(prog->main);
4003 BasicBlock *leave = new BasicBlock(prog->main);
4004
4005 prog->main->setEntry(entry);
4006 prog->main->setExit(leave);
4007
4008 setPosition(entry, true);
4009 sub.cur = getSubroutine(prog->main);
4010
4011 if (info->io.genUserClip > 0) {
4012 for (int c = 0; c < 4; ++c)
4013 clipVtx[c] = getScratch();
4014 }
4015
4016 switch (prog->getType()) {
4017 case Program::TYPE_TESSELLATION_CONTROL:
4018 outBase = mkOp2v(
4019 OP_SUB, TYPE_U32, getSSA(),
4020 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_LANEID, 0)),
4021 mkOp1v(OP_RDSV, TYPE_U32, getSSA(), mkSysVal(SV_INVOCATION_ID, 0)));
4022 break;
4023 case Program::TYPE_FRAGMENT: {
4024 Symbol *sv = mkSysVal(SV_POSITION, 3);
4025 fragCoord[3] = mkOp1v(OP_RDSV, TYPE_F32, getSSA(), sv);
4026 mkOp1(OP_RCP, TYPE_F32, fragCoord[3], fragCoord[3]);
4027 break;
4028 }
4029 default:
4030 break;
4031 }
4032
4033 if (info->io.viewportId >= 0)
4034 viewport = getScratch();
4035 else
4036 viewport = NULL;
4037
4038 for (ip = 0; ip < code->scan.num_instructions; ++ip) {
4039 if (!handleInstruction(&code->insns[ip]))
4040 return false;
4041 }
4042
4043 if (!BindArgumentsPass(*this).run(prog))
4044 return false;
4045
4046 return true;
4047 }
4048
4049 } // unnamed namespace
4050
4051 namespace nv50_ir {
4052
4053 bool
4054 Program::makeFromTGSI(struct nv50_ir_prog_info *info)
4055 {
4056 tgsi::Source src(info);
4057 if (!src.scanSource())
4058 return false;
4059 tlsSize = info->bin.tlsSpace;
4060
4061 Converter builder(this, &src);
4062 return builder.run();
4063 }
4064
4065 } // namespace nv50_ir